Electronic Components Datasheet Search
English 中文版
Manufacturer Upload
Part Name:
DIFFCLK_1P Cyclone III Device Handbook
Prototype PCB
Part No.:   DIFFCLK_1P
Download: Download   Right selection Save Target As
View Datasheet (Html)   No need to install PDF reader software
Description:   Cyclone III Device Handbook
File Size :   7302 K    
Page : 274 Pages
Maker   ALTERA [ ALTERA CORPORATION ]http://www.altera.com
Buy Now :   
  DIFFCLK_1P Datasheet PDF page 45 DIFFCLK_1P Datasheet PDF page 46 DIFFCLK_1P Datasheet PDF page 47 DIFFCLK_1P Datasheet PDF page 48 DIFFCLK_1P Datasheet PDF page 50 DIFFCLK_1P Datasheet PDF page 51 DIFFCLK_1P Datasheet PDF page 52 DIFFCLK_1P Datasheet PDF page 53  
Chapter 3: Memory Blocks in the Cyclone III Device Family
Design Considerations
Read or Write Clock Mode
Cyclone III device family M9K memory blocks can implement read or write clock
mode for FIFO and simple dual-port memories. In this mode, a write clock controls
the data inputs, write address, and
registers. Similarly, a read clock controls the
data outputs, read address, and
registers. M9K memory blocks support
independent clock enables for both the read and write clocks.
When using read or write mode, if you perform a simultaneous read or write to the
same address location, the output read data is unknown. If you require the output
data to be a known value, use either single-clock mode, input clock mode, or output
clock mode and choose the appropriate read-during-write behavior in the
MegaWizard Plug-In Manager.
Single-Clock Mode
Cyclone III device family M9K memory blocks can implement single-clock mode for
FIFO, ROM, true dual-port, simple dual-port, and single-port memories. In this mode,
you can control all registers of the M9K memory block with a single clock together
with clock enable.
Design Considerations
This section describes designing with M9K memory blocks.
Read-During-Write Operations
describe the functionality of the various RAM
configurations when reading from an address during a write operation at that same
There are two read-during-write data flows: same-port and mixed-port.
shows the difference between these flows.
Figure 3–14. Cyclone III Device Family Read-During-Write Data Flow
Port A
data in
Port B
data in
data flow
data flow
Port A
data out
Port B
data out
December 2011
Altera Corporation
Cyclone III Device Handbook
Volume 1
Home - IC Supply - Link
Copyright© 2001 - 2014 ICPDF All Rights Reserved ICPDF.COM

粤公网安备 44030402000629号