Electronic Components Datasheet Search
English 中文版
Manufacturer Upload
Part Name:
 
Description:
BZG05C3V3  BZG05C36  BZG05C5V6  BZG05C5V1  BZG05C33  BZG05C3V9  BZG05C4V7  BZG05C3V6  BZG05C30  BZG05C4V3  
DIFFCLK_3N Cyclone III Device Handbook
Prototype PCB
Part No.:   DIFFCLK_3N
Download: Download   Right selection Save Target As
View Datasheet (Html)   No need to install PDF reader software
Description:   Cyclone III Device Handbook
File Size :   7302 K    
Page : 274 Pages
Logo:   
Maker   ALTERA [ ALTERA CORPORATION ]http://www.altera.com
Buy Now :   
  DIFFCLK_3N Datasheet PDF page 87 DIFFCLK_3N Datasheet PDF page 88 DIFFCLK_3N Datasheet PDF page 89 DIFFCLK_3N Datasheet PDF page 90 DIFFCLK_3N Datasheet PDF page 92 DIFFCLK_3N Datasheet PDF page 93 DIFFCLK_3N Datasheet PDF page 94 DIFFCLK_3N Datasheet PDF page 95  
100%
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
PLL Reconfiguration
5–31
Table 5–7. Loop Filter Control of High Frequency Capacitor
LFC[1]
0
0
1
LFC[0]
0
1
1
Setting (Decimal)
0
1
3
Bypassing PLL Counter
Bypassing a PLL counter results in a multiply (M counter) or a divide (N, C0 to C4
counters) factor of one.
lists the settings for bypassing the counters in Cyclone III device family
PLLs.
Table 5–8. PLL Counter Settings
PLL Scan Chain Bits [0..8] Settings
Description
LSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
MSB
1
0
PLL counter bypassed
PLL counter not bypassed
Note to
(1) Bypass bit.
To bypass any of the PLL counters, set the bypass bit to 1. The values on the other bits
are then ignored.
Dynamic Phase Shifting
The dynamic phase shifting feature allows the output phase of individual PLL
outputs to be dynamically adjusted relative to each other and the reference clock
without sending serial data through the scan chain of the corresponding PLL. This
feature simplifies the interface and allows you to quickly adjust t
CO
delays by
changing output clock phase shift in real time. This is achieved by incrementing or
decrementing the VCO phase-tap selection to a given C counter or to the M counter.
The phase is shifted by 1/8 the VCO frequency at a time. The output clocks are active
during this phase reconfiguration process.
lists the control signals that are used for dynamic phase shifting.
Table 5–9. Dynamic Phase Shifting Control Signals (Part 1 of 2)
Signal Name
Description
Counter Select. Three bits decoded to select
either the M or one of the C counters for
phase adjustment. One address map to select
all C counters. This signal is registered in the
PLL on the rising edge of
SCANCLK.
Selects dynamic phase shift direction; 1= UP,
0 = DOWN. Signal is registered in the PLL on
the rising edge of
SCANCLK.
Source
Destination
PLL
reconfiguration
circuit
PLL
reconfiguration
circuit
PHASECOUNTERSELECT[2:0]
Logic array or I/O
pins
PHASEUPDOWN
Logic array or I/O
pins
July 2012
Altera Corporation
Cyclone III Device Handbook
Volume 1
Home - IC Supply - Link
Copyright© 2001 - 2014 ICPDF All Rights Reserved ICPDF.COM

粤公网安备 44030402000629号


粤ICP备13051289号-7