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DIFFCLK_3N Cyclone III Device Handbook
Prototype PCB
Part No.:   DIFFCLK_3N
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Description:   Cyclone III Device Handbook
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Page : 274 Pages
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5–32
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
PLL Reconfiguration
Table 5–9. Dynamic Phase Shifting Control Signals (Part 2 of 2)
Signal Name
PHASESTEP
Description
Logic high enables dynamic phase shifting.
Free running clock from core used in
combination with
PHASESTEP
to enable or
disable dynamic phase shifting. Shared with
SCANCLK
for dynamic reconfiguration.
When asserted, it indicates to core logic that
the phase adjustment is complete and PLL is
ready to act on a possible second adjustment
pulse. Asserts based on internal PLL timing.
Deasserts on rising edge of
SCANCLK.
Source
Logic array or I/O
pins
Destination
PLL
reconfiguration
circuit
PLL
reconfiguration
circuit
SCANCLK
GCLK or I/O pins
PHASEDONE
PLL reconfiguration Logic array or
circuit
I/O pins
lists the PLL counter selection based on the corresponding
PHASECOUNTERSELECT
setting.
Table 5–10. Phase Counter Select Mapping
PHASECOUNTERSELECT [2]
0
0
0
0
1
1
1
[1]
0
0
1
1
0
0
1
[0]
0
1
0
1
0
1
0
Selects
All Output Counters
M Counter
C0 Counter
C1 Counter
C2 Counter
C3 Counter
C4 Counter
To perform one dynamic phase shift step, you must perform the following
procedures:
1. Set
PHASEUPDOWN
and
PHASECOUNTERSELECT
as required.
2. Assert
PHASESTEP
for at least two
SCANCLK
cycles. Each
PHASESTEP
pulse allows one
phase shift.
3. Deassert
PHASESTEP
after
PHASEDONE
goes low.
4. Wait for
PHASEDONE
to go high.
5. Repeat steps
1
through
4
as many times as required to perform multiple phase-
shifts.
PHASEUPDOWN
and
PHASECOUNTERSELECT
signals are synchronous to
SCANCLK
and must
meet the t
su
and t
h
requirements with respect to the
SCANCLK
edges.
1
You can repeat dynamic phase-shifting indefinitely. For example, in a design where
the VCO frequency is set to 1,000 MHz and the output clock frequency is set to
100 MHz, performing 40 dynamic phase shifts (each one yields 125 ps phase shift)
results in shifting the output clock by 180, in other words, a phase shift of 5 ns.
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
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