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DIFFCLK_3N Cyclone III Device Handbook
Prototype PCB
Part No.:   DIFFCLK_3N
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Description:   Cyclone III Device Handbook
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Page : 274 Pages
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Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
Spread-Spectrum Clocking
5–33
shows the dynamic phase shifting waveform.
Figure 5–24. Timing Diagram for Dynamic Phase Shift
SCANCLK
PHASESTEP
PHASEUPDOWN
PHASECOUNTERSELECT
PHASEDONE
a
b
PHASEDONE goes low
synchronous with SCANCLK
c
d
The
PHASESTEP
signal is latched on the negative edge of
SCANCLK
(a,c) and must remain
asserted for at least two
SCANCLK
cycles. Deassert
PHASESTEP
after
PHASEDONE
goes low.
On the second
SCANCLK
rising edge (b,d) after
PHASESTEP
is latched, the values of
PHASEUPDOWN
and
PHASECOUNTERSELECT
are latched and the PLL starts dynamic
phase-shifting for the specified counters, and in the indicated direction.
PHASEDONE
is
deasserted synchronous to
SCANCLK
at the second rising edge (b,d) and remains low
until the PLL finishes dynamic phase-shifting. Depending on the VCO and
SCANCLK
frequencies,
PHASEDONE
low time may be greater than or less than one
SCANCLK
cycle.
You can perform another dynamic phase-shift after the
PHASEDONE
signal goes from
low to high. Each
PHASESTEP
pulse enables one phase shift.
PHASESTEP
pulses must be
at least one
SCANCLK
cycle apart.
f
For information about the ALTPLL_RECONFIG MegaWizard Plug-In Manager, refer
to the
user
guide.
Spread-Spectrum Clocking
The Cyclone III device family can accept a spread-spectrum input with typical
modulation frequencies. However, the device cannot automatically detect that the
input is a spread-spectrum signal. Instead, the input signal looks like deterministic
jitter at the input of the PLL. Cyclone III device family PLLs can track a
spread-spectrum input clock as long as it is in the input jitter tolerance specifications
and the modulation frequency of the input clock is below the PLL bandwidth, which
is specified in the fitter report. The Cyclone III device family cannot generate
spread-spectrum signals internally.
PLL Specifications
f
For information about PLL specifications, refer to the
and
chapters.
July 2012
Altera Corporation
Cyclone III Device Handbook
Volume 1
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