EP1SGX25_技术文档

1. Enhanced Configuration Devices

(EPC4, EPC8, and EPC16) Data Sheet

CF52002-2.8

Features

This chapter describes the EPC4, EPC8, and EPC16 enhanced configuration devices

(EPC).

■

Single-chip configuration solution for Altera^®ACEX^®1K, APEX^™20K (including

APEX 20K, APEX 20KC, and APEX 20KE), APEX II, Arria^®GX, Cyclone^®, Cyclone

II, FLEX^®10K (including FLEX 10KE and FLEX 10KA), Mercury^™, Stratix^®II, and

Stratix II GX devices

■

Contains 4-, 8-, and 16-Mbit flash memories for configuration data storage

■

On-chip decompression feature almost doubles the effective configuration

density

■

Standard flash die and a controller die combined into single stacked chip package

External flash interface supports parallel programming of flash and external

processor access to unused portions of memory

■

Flash memory block/sector protection capability via external flash interface

Supported in EPC16 and EPC4 devices

■

Page mode support for remote and local reconfiguration with up to eight

configurations for the entire system

■

Compatible with Stratix series Remote System Configuration feature

Supports byte-wide configuration mode fast passive parallel (FPP); 8-bit data

output per DCLKcycle

■

Supports true n-bit concurrent configuration (n = 1, 2, 4, and 8) of Altera FPGAs

Pin-selectable 2-ms or 100-ms power-on reset (POR) time

Configuration clock supports programmable input source and frequency synthesis

■

Multiple configuration clock sources supported (internal oscillator and

external clock input pin)

■

External clock source with frequencies up to 100 MHz

Internal oscillator defaults to 10 MHz; Programmable for higher frequencies of

33, 50, and 66 MHz

■

Clock synthesis supported via user programmable divide counter

■

Available in the 100-pin plastic quad flat pack (PQFP) and the 88-pin Ultra

FineLine BGA^®(UFBGA) packages

■

Vertical migration between all devices supported in the 100-pin PQFP package

■

Supply voltage of 3.3 V (core and I/O)

Hardware compliant with IEEE Std. 1532 in-system programmability (ISP)

specification

Configuration Handbook (Complete Two-Volume Set)

1–2

Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet

Functional Description

■

Supports ISP via Jam Standard Test and Programming Language (STAPL)

Supports JTAG boundary scan

nINIT_CONFpin allows private JTAG instruction to start FPGA configuration

Internal pull-up resistor on nINIT_CONFalways enabled

User programmable weak internal pull-up resistors on nCSand OEpins

Internal weak pull-up resistors on external flash interface address and control

lines, bus hold on data lines

■

Standby mode with reduced power consumption

f

For more information about FPGA configuration schemes and advanced features,

refer to the appropriate FPGA family chapter in the Configuration Handbook.

Functional Description

The Altera enhanced configuration device is a single-device, high-speed, advanced

configuration solution for very high-density FPGAs. The core of an enhanced

configuration device is divided into two major blocks: a configuration controller and a

flash memory. The flash memory is used to store configuration data for systems made

up of one or more Altera FPGAs. Unused portions of the flash memory can be used to

store processor code or data that can be accessed via the external flash interface after

FPGA configuration is complete. Table 1–1 summarizes the features of Altera

configuration devices and the amount of configuration space they hold.

Table 1–1. Altera Configuration Devices

On-Chip

Decompression

Support

Memory Size

(bits)

ISP

Cascading

Support

Operating

Device

EPC4

Support

Reprogrammable

Voltage (V)

4,194,304

8,388,608

16,777,216

Yes

No

Yes

3.3

EPC8

EPC16

Table 1–2 lists the supported configuration devices required to configure an ACEX 1K,

APEX 1K, APEX 20K, APEX 20KC, APEX 20KE, APEX II, Arria GX, Cyclone,

Cyclone II, FLEX 10K, FLEX 10KA, FLEX 10KE, Stratix, Stratix GX, Stratix II, Stratix II

GX, or Mercury device.

Configuration Handbook (Complete Two-Volume Set)

Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet

1–3

Functional Description

Table 1–2. Configuration Devices Required (Part 1 of 3)

Data Size (Bits)

Family

Arria GX

Device

EP1AGX20C

EP1AGX35C

EP1AGX35D

EP1AGX50C

EP1AGX50D

EP1AGX60C

EP1AGX60D

EP1AGX60E

EP1AGX90E

EP1S10

(1)

EPC4 (2) EPC8 (2) EPC16 (2)

9,640,672

—

1

16,951,824

—

1

25,699,104

3,534,640

5,904,832

7,894,144

10,379,368

12,389,632

17,543,968

23,834,032

3,534,640

7,894,144

12,389,632

4,721,544

9,640,672

16,951,824

25,699,104

37,325,760

49,814,760

9,640,672

16,951,824

25,699,104

37,325,760

627,376

—

1

—

1

Stratix

EP1S20

1

EP1S25

—

1

EP1S30

1

EP1S40

1

EP1S60

—

1

EP1S80

1

Stratix GX

Stratix II

EP1SGX10

EP1SGX25

EP1SGX40

EP2S15

1

—

1

EP2S30

—

1

EP2S60

—

1

EP2S90

—

1

EP2S130

EP2S180

Stratix II GX

EP2SGX30C

EP2SGX30D

EP2SGX60C

EP2SGX60D

EP2SGX60E

EP2SGX90E

EP2SGX90F

EP2SGX130G

EP1C3

1

—

1

Cyclone

EP1C4

924,512

1

EP1C6

1,167,216

2,326,528

3,559,608

1

EP1C12

1

EP1C20

1

Configuration Handbook (Complete Two-Volume Set)

1–4

Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet

Functional Description

Table 1–2. Configuration Devices Required (Part 2 of 3)

Data Size (Bits)

Family

Cyclone II

Device

EP2C5

(1)

EPC4 (2) EPC8 (2) EPC16 (2)

1,223,980

1,983,792

3,930,986

7,071,234

9,122,148

10,249,694

159,160

1

—

1

EP2C8

EP2C20

1

EP2C35

—

1

EP2C50

EP2C70

ACEX 1K

EP1K10

EP1K30

473,720

1

EP1K50

784,184

1

EP1K100

EP20K100

EP20K200

EP20K400

EP20K200C

EP20K400C

EP20K600C

EP20K1000C

EP20K30E

EP20K60E

EP20K100E

EP20K160E

EP20K200E

EP20K300E

EP20K400E

EP20K600E

EP20K1000E

EP20K1500E

EP2A15

1,335,720

993,360

1

APEX 20K

1

1,950,800

3,880,720

196,8016

390,9776

567,3936

8,960,016

354,832

1

APEX 20KC

1

—

1

APEX 20KE

648,016

1

1,008,016

1,524,016

1,968,016

2,741,616

3,909,776

5,673,936

8,960,016

12,042,256

4,358,512

6,275,200

9,640,528

17,417,088

118,000

1

—

1

APEX II

EP2A25

1

EP2A40

—

1

EP2A70

FLEX 10K

EPF10K10

EPF10K20

EPF10K30

EPF10K40

EPF10K50

EPF10K70

EPF10K100

231,000

1

376,000

1

498,000

1

621,000

1

892,000

1

1,200,000

1

Configuration Handbook (Complete Two-Volume Set)

Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet

1–5

Functional Description

Table 1–2. Configuration Devices Required (Part 3 of 3)

Data Size (Bits)

Family

FLEX 10KA

Device

EPF10K10A

EPF10K30A

EPF10K50V

EPF10K100A

EPF10K130V

EPF10K250A

EPF10K30E

EPF10K50E

EPF10K50S

EPF10K100B

EPF10K100E

EPF10K130E

EPF10K200E

EPF10K200S

EP1M120

(1)

EPC4 (2) EPC8 (2) EPC16 (2)

120,000

1

406,000

621,000

1

1,200,000

1,600,000

3,300,000

473,720

1

FLEX 10KE

1

784,184

1

784,184

1

1,200,000

1,335,720

1,838,360

2,756,296

1,303,120

4,394,032

1

Mercury

—

EP1M350

Notes to Table 1–2:

(1) Raw Binary Files (.rbf) were used to determine these sizes.

(2) These values with the enhanced configuration device compression feature enabled.

f

For more information about additional enhanced configuration devices, refer to the

Process Change Notification PCN0506: Addition of Intel Flash Memory As Source For

EPC4, EPC8 and EPC16 Enhanced Configuration Devices and Using the Intel Flash

Memory-Based EPC4, EPC8 and EPC16 Devices white paper.

EPC devices support three different types of flash memory. Table 1–3 lists the

supported flash memory for all EPC devices.

Table 1–3. Enhanced Configuration Devices Flash Memory (Part 1 of 2)

Flash Memory

Device

EPC4

Grade

Commercial

Industrial

Package

PQFP 100

Leaded

Lead-Fee

Intel (1) or Micron

Intel (1)

Intel (1) or Micron

Intel (1) or Sharp

PQFP 100

EPC8

Commercial/

Industrial

Intel (1)

Configuration Handbook (Complete Two-Volume Set)

1–6

Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet

Functional Description

Table 1–3. Enhanced Configuration Devices Flash Memory (Part 2 of 2)

Flash Memory

Device

EPC16

Grade

Commercial

Industrial

Package

UBGA 88

Leaded

Lead-Fee

Intel (1) or Sharp

Intel (1)

Intel (1) or Sharp

UBGA 88

PQFP 100

Commercial/

Industrial

Intel (1)

Note to Table 1–3:

(1) For more information, refer to the Process Change Notification PCN0506: Addition of Intel Flash Memory As

Source for EPC4, EPC8 and EPC16 Enhanced Configuration Devices.

The external flash interface is currently supported in the EPC16 and EPC4 devices.

For information about using this feature in the EPC8 device, contact Altera Applica-

tions at www.altera.com/support.

Enhanced configuration devices have a 3.3-V core and I/O interface. The controller

chip is a synchronous system that implements the various interfaces and features.

Figure 1–1 shows a block diagram of the enhanced configuration device. The

controller chip features three separate interfaces:

■

A configuration interface between the controller and the Altera FPGAs

A JTAG interface on the controller that enables ISP of the flash memory

An external flash interface that the controller shares with an external processor, or

FPGA implementing a Nios^®embedded processor (interface available after ISP

and configuration)

Figure 1–1. Enhanced Configuration Device Block Diagram

JTAG/ISP Interface

Enhanced Configuration Device

Shared Flash

Interface

FPGA

Flash

Controller

Shared Flash Interface

Configuration Handbook (Complete Two-Volume Set)

Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet

1–7

Functional Description

The enhanced configuration device features multiple configuration schemes. In

addition to supporting the traditional passive serial (PS) configuration scheme for a

single device or a serial device chain, the enhanced configuration device features

concurrent configuration and parallel configuration. With the concurrent

configuration scheme, up to eight PS device chains can be configured simultaneously.

In the FPP configuration scheme, 8-bits of data are clocked into the FPGA each cycle.

These schemes offer significantly reduced configuration times over traditional

schemes.

Furthermore, the enhanced configuration device features a dynamic configuration or

page mode feature. This feature allows you to dynamically reconfigure all the FPGAs

in your system with new images stored in the configuration memory. Up to eight

different system configurations or pages can be stored in memory and selected using

the PGM[2..0]pins. Your system can be dynamically reconfigured by selecting one

of the eight pages and initiating a reconfiguration cycle.

This page mode feature combined with the external flash interface allows remote and

local updates of system configuration data. The enhanced configuration devices are

compatible with the Stratix Remote System Configuration feature.

1

For more information about Stratix Remote System Configuration, refer to the Remote

System Configuration with Stratix & Stratix GX Devices chapter in the Stratix Device

Handbook.

Other user programmable features include:

■

Real-time decompression of configuration data

Programmable configuration clock (DCLK)

Flash ISP

Programmable power-on-reset delay (PORSEL)

FPGA Configuration

FPGA configuration is managed by the configuration controller chip. This process

includes reading configuration data from the flash memory, decompressing it if

necessary, transmitting configuration data via the appropriate DATA[]pins, and

handling error conditions.

After POR, the controller determines the user-defined configuration options by

reading its option bits from the flash memory. These options include the configuration

scheme, configuration clock speed, decompression, and configuration page settings.

The option bits are stored at flash address location 0x8000 (word address) and occupy

512-bits or 32-words of memory. These options bits are read using the internal flash

interface and the default 10 MHz internal oscillator.

After obtaining the configuration settings, the configuration controller chip checks if

the FPGA is ready to accept configuration data by monitoring the nSTATUSand

CONF_DONElines. When the FPGA is ready (nSTATUSis high and CONF_DONEis low),

the controller begins data transfer using the DCLKand DATA[]output pins. The

controller selects the configuration page to be transmitted to the FPGA by sampling

its PGM[2..0]pins after POR or reset.

Configuration Handbook (Complete Two-Volume Set)

1–8

Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet

Functional Description

The function of the configuration unit is to transmit decompressed data to the FPGA,

depending on the configuration scheme. The enhanced configuration device supports

four concurrent configuration modes, with n = 1, 2, 4, or 8 (where n is the number of

bits that are sent per DCLKcycle on the DATA[n]lines). The value n = 1 corresponds

to the traditional PS configuration scheme. The values n = 2, 4, and 8 correspond to

concurrent configuration of 2, 4, or 8 different PS configuration chains, respectively.

Additionally, the FPGA can be configured in FPP mode, where eight bits of DATAare

clocked into the FPGA per DCLKcycle. Depending on the configuration bus width (n),

the circuit shifts uncompressed configuration data to the valid DATA[n]pins. Unused

DATA[]pins drive low.

In addition to transmitting configuration data to the FPGAs, the configuration circuit

is also responsible for pausing configuration whenever there is insufficient data

available for transmission. This occurs when the flash read bandwidth is lower than

the configuration write bandwidth. Configuration is paused by stopping the DCLKto

the FPGA, when waiting for data to be read from the flash or for data to be

decompressed. This technique is called “Pausing DCLK”.

The enhanced configuration device flash-memories feature a 90-ns access time

(approximately 10 MHz). Hence, the flash read bandwidth is limited to about 160

megabits per second (Mbps) (16-bit flash data bus, DQ[], at 10 MHz). However, the

configuration speeds supported by Altera FPGAs are much higher and translate to

high configuration write bandwidths. For instance, 100-MHz Stratix FPP

configuration requires data at the rate of 800 Mbps (8-bit DATA[]bus at 100 MHz).

This is much higher than the 160 Mbps the flash memory can support, and is the

limiting factor for configuration time. Compression increases the effective flash-read

bandwidth as the same amount of configuration data takes up less space in the flash

memory after compression. Since Stratix configuration data compression ratios are

approximately two, the effective read bandwidth doubles to about 320 Mbps.

Finally, the configuration controller also manages errors during configuration. A

CONF_DONEerror occurs when the FPGA does not de-assert its CONF_DONEsignal

within 64 DCLKcycles after the last bit of configuration data is transmitted. When a

CONF_DONEerror is detected, the controller pulses the OEline low, which pulls

nSTATUSlow and triggers another configuration cycle.

A cyclical redundancy check (CRC) error occurs when the FPGA detects corruption in

the configuration data. This corruption could be a result of noise coupling on the

board such as poor signal integrity on the configuration signals. When this error is

signaled by the FPGA (by driving the nSTATUSline low), the controller stops

configuration. If the Auto-Restart Configuration After Error option is enabled in the

FPGA, it releases its nSTATUSsignal after a reset time-out period and the controller

attempts to reconfigure the FPGA.

After the FPGA configuration process is complete, the controller drives DCLKlow and

the DATA[]pins high. Additionally, the controller tri-states its internal interface to the

flash memory, enables the weak internal pull-ups on the flash address and control

lines, and enables bus-keep circuits on flash data lines.

The following sections briefly describe the different configuration schemes supported

by the enhanced configuration device: FPP, PS, and concurrent configuration.

f

For detailed information about using these schemes to configure your Altera FPGA,

refer to the appropriate FPGA family chapter in the Configuration Handbook.

Configuration Handbook (Complete Two-Volume Set)

Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet

1–9

Functional Description

Configuration Signals

Table 1–4 lists the configuration signal connections between the enhanced

configuration device and Altera FPGAs.

Table 1–4. Configuration Signals

Enhanced

Configuration

Device Pin

Altera FPGA Pin

Description

DATA[]

Configuration data transmitted from the configuration

device to the FPGA, which is latched on the rising edge of

DCLK.

DCLK

Configuration device generated clock used by the FPGA to

latch configuration data provided on the DATA[]pins.

nINIT_CONF,

which

nCONFIG

Open-drain output from the configuration device that is

used to start FPGA reconfiguration using the initiate

configuration (INIT_CONF) JTAG instruction. This

connection is not needed if the INIT_CONFJTAG

instruction is not needed. If nINIT_CONFis not

connected to nCONFIG, nCONFIGmust be tied to V_CC

either directly or through a pull-up resistor.

OE

nSTATUS

Open-drain bidirectional configuration status signal,

which is driven low by either device during POR and to

signal an error during configuration. Low pulse on OE

resets the enhanced configuration device controller.

nCS

CONF_DONE

Configuration done output signal driven by the FPGA.

Fast Passive Parallel Configuration

Stratix series and APEX II devices can be configured using the enhanced

configuration device in FPP mode. In this mode, the enhanced configuration device

sends a byte of data on the DATA[7..0]pins, which connect to the DATA[7..0]

input pins of the FPGA, per DCLKcycle. Stratix series and APEX II FPGAs receive

byte-wide configuration data per DCLKcycle. Figure 1–2 shows the enhanced

configuration device in FPP configuration mode. In this figure, the external flash

interface is not used and hence most flash pins are left unconnected (with the few

noted exceptions). For specific details about configuration interface connections

including pull-up resistor values, supply voltages, and MSELpin settings, refer to the

appropriate FPGA family chapter in the Configuration Handbook.

Configuration Handbook (Complete Two-Volume Set)

1–10

Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet

Functional Description

Figure 1–2. FPP Configuration

Enhanced Configuration

Device

V

CC

V

CC (1)

(1)

Stratix Series

or

APEX II Device

WE#C

RP#C

DCLK

WE#F

RP#F

(3)

n

DCLK

(6)

MSEL

A[20..0]

RY/BY#

CE#

N.C.

DATA[7..0]

nSTATUS

CONF_DONE

nCONFIG

DATA[7..0]

(3)

nCS

OE

nINIT_CONF (2)

OE#

V

(1)

CC

DQ[15..0]

nCE

N.C.

nCEO

V

(7)

WP#

CC

BYTE# (5)

TM1

VCCW

GND

(4)

PORSEL

(4)

PGM[2..0]

(4)

TMO

EXCLK

GND

C-A0 (5)

C-A1 (5)

C-A15 (5)

C-A16 (5)

A0-F

A1-F

A15-F

A16-F

Notes to Figure 1–2:

(1) The V_CCshould be connected to the same supply voltage as the configuration device.

(2) The nINIT_CONFpin is available on enhanced configuration devices and has an internal pull-up resistor that is always active. This means an

external pull-up resistor is not required on the nINIT_CONF/ nCONFIGline. The nINIT_CONFpin does not need to be connected if its

functionality is not used. If nINIT_CONFis not used, nCONFIGmust be pulled to V_CCeither directly or through a resistor.

(3) The enhanced configuration devices’ OEand nCSpins have internal programmable pull-up resistors. If internal pull-up resistors are used, external

pull-up resistors should not be used on these pins. The internal pull-up resistors are used by default in the Quartus^®II software. To turn off the

internal pull-up resistors, check the Disable nCS and OE pull-ups on configuration device option when generating programming files.

(4) For PORSEL, PGM[], and EXCLKpin connections, refer to Table 1–10.

(5) In the 100-pin PQFP package, you must externally connect the following pins: C-A0to F-A0, C-A1to F-A1, C-A15to F-A15, C-A16to

F-A16, and BYTE#to V_CC. Additionally, you must make the following pin connections in both 100-pin PQFP and 88-pin UFBGA packages:

C-RP#to F-RP#, C-WE#to F-WE#, TM1to V_CC, TM0to GND, and WP#to V_CC

.

(6) Connect the FPGA MSEL[]input pins to select the FPP configuration mode. For details, refer to the appropriate FPGA family chapter in the

Configuration Handbook.

(7) To protect Intel Flash based EPC devices content, isolate the V_CCWsupply from V_CC. For more information, refer section “Intel-Flash-Based EPC

Device Protection” on page 1–15.

Multiple FPGAs can be configured using a single enhanced configuration device in

FPP mode. In this mode, multiple Stratix series FPGAs, APEX II FPGAs, or both, are

cascaded together in a daisy chain.

After the first FPGA completes configuration, its nCEOpin asserts to activate the nCE

pin for the second FPGA, which prompts the second device to start capturing

configuration data. In this setup, the FPGAs CONF_DONEpins are tied together, and

hence all devices initialize and enter user mode simultaneously. If the enhanced

configuration device or one of the FPGAs detects an error, configuration stops (and

simultaneously restarts) for the whole chain because the nSTATUSpins are tied

together.

1

While Altera FPGAs can be cascaded in a configuration chain, the enhanced

configuration devices cannot be cascaded to configure larger devices or chains.

Configuration Handbook (Complete Two-Volume Set)

Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet

1–11

Functional Description

f

For configuration schematics and more information about multi-device FPP

configuration, refer to the appropriate FPGA family chapter in the Configuration

Handbook.

Passive Serial Configuration

APEX 20KC, APEX 20KE, APEX 20K, APEX II, Cyclone series, FLEX 10K, and Stratix

series devices can be configured using enhanced configuration devices in the PS

mode. This mode is similar to the FPP mode, with the exception that only one bit of

data (DATA[0]) is transmitted to the FPGA per DCLKcycle. The remaining

DATA[7..1]output pins are unused in this mode and drive low.

The configuration schematic for PS configuration of a single FPGA or single serial

chain is identical to the FPP schematic (with the exception that only DATA[0]output

from the enhanced configuration device connects to the FPGA DATA0input pin;

remaining DATA[7..1]pins are left floating).

f

For configuration schematics and more information about multi-device PS

configuration, refer to the appropriate FPGA family chapter in the Configuration

Handbook.

Concurrent Configuration

Enhanced configuration devices support concurrent configuration of multiple FPGAs

(or FPGA chains) in PS mode. Concurrent configuration is when the enhanced

configuration device simultaneously outputs n bits of configuration data on the

DATA[n-1..0]pins (n = 1, 2, 4, or 8), and each DATA[]line serially configures a

different FPGA (chain). The number of concurrent serial chains is user-defined via the

Quartus II software and can be any number from 1 to 8. For example, three concurrent

chains you can select the 4-bit PS mode, and connect the least significant DATA bits to

the FPGAs or FPGA chains. Leave the most significant DATAbit (DATA[3])

unconnected. Similarly, for 5-, 6-, or 7-bit concurrent chains you can select the 8-bit PS

mode.

Figure 1–3 shows the schematic for configuring multiple FPGAs concurrently in the

PS mode using an enhanced configuration device.

f

For specific details about configuration interface connections including pull-up

resistor values, supply voltages, and MSELpin settings, refer to the appropriate FPGA

family chapter in the Configuration Handbook.

Configuration Handbook (Complete Two-Volume Set)

1–12

Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet

Functional Description

Figure 1–3. Concurrent Configuration of Multiple FPGAs in PS Mode (n = 8)

Enhanced Configuration

Device

V

(1)

V

CC

(1)

CC

WE#C

WE#F

(3)

FPGA0

RP#C

RP#F

DCLK

N.C.

A[20..0]

RY/BY#

CE#

DATA0

n

nSTATUS

CONF_DONE

nCONFIG

(6)

MSEL

nCEO

DATA1

N.C.

OE#

nCE

(3)

OE

DQ[15..0]

N.C.

n

(3)

nCS

nINIT_CONF (2)

GND

FPGA1

DCLK

DATA 7

DATA0

nSTATUS

CONF_DONE

nCONFIG

(6)

MSEL

nCEO

(1)

V

(7)

CC

V

CC

VCCW

nCE

WP#

BYTE# (5)

N.C.

TM1

GND

(4)

PORSEL

(4)

PGM[2..0]

EXCLK

(4)

FPGA7

DCLK

n

DATA0

nSTATUS

CONF_DONE

TMO

(6)

MSEL

nCEO

nCONFIG

GND

nCE

C-A0 (5)

C-A1 (5)

C-A15 (5)

C-A16 (5)

A0-F

A1-F

A15-F

A16-F

N.C.

GND

Notes to Figure 1–3:

(1) Connect V_CCto the same supply voltage as the configuration device.

(2) The nINIT_CONFpin is available on enhanced configuration devices and has an internal pull-up resistor that is always active. This means an

external pull-up resistor is not required on the nINIT_CONF/nCONFIGline. The nINIT_CONFpin does not need to be connected if its

functionality is not used. If nINIT_CONFis not used, nCONFIGmust be pulled to V_CCeither directly or through a resistor.

(3) The enhanced configuration devices’ OEand nCSpins have internal programmable pull-up resistors. If internal pull-up resistors are used, external

pull-up resistors should not be used on these pins. The internal pull-up resistors are used by default in the Quartus II software. To turn off the

internal pull-up resistors, check the Disable nCS and OE pull-ups on configuration device option when generating programming files.

(4) For PORSEL, PGM[], and EXCLKpin connections, refer to Table 1–10.

(5) In the 100-pin PQFP package, you must externally connect the following pins: C-A0to F-A0, C-A1to F-A1, C-A15to F-A15, C-A16to

F-A16, and BYTE#to V_CC. Additionally, you must make the following pin connections in both 100-pin PQFP and 88-pin UFBGA packages:

C-RP#to F-RP#, C-WE#to F-WE#, TM1to V_CC, TM0to GND, and WP#to V_CC

.

(6) Connect the FPGA MSEL[]input pins to select the PS configuration mode. For details, refer to the appropriate FPGA family chapter in the

Configuration Handbook.

(7) To protect Intel Flash based EPC devices content, isolate the V_CCWsupply from V_CC. For more information, refer section “Intel-Flash-Based EPC

Device Protection” on page 1–15.

Configuration Handbook (Complete Two-Volume Set)

Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet

1–13

Functional Description

Table 1–5 summarizes the concurrent PS configuration modes supported in the

enhanced configuration device.

Table 1–5. Enhanced Configuration Devices in PS Mode

Mode Name

Mode (n =) (1)

Used Outputs

DATA0

Unused Outputs

DATA[7..1]drive low

DATA[7..2]drive low

Passive serial mode

1

2

Multi-device passive

serial mode

DATA[1..0]

DATA[3..0]

DATA[7..0]

Multi-device passive

serial mode

4

8

DATA[7..4]drive low

Multi-device passive

serial mode

—

Note to Table 1–5:

(1) This is the number of valid DATAoutputs for each configuration mode.

f

For configuration schematics and more information about concurrent configurations,

refer to the appropriate FPGA family chapter in the Configuration Handbook.

External Flash Interface

The enhanced configuration devices support external FPGA or processor access to its

flash memory. The unused portions of the flash memory can be used by the external

device to store code or data. This interface can also be used in systems that implement

remote configuration capabilities. Configuration data within a particular

configuration page can be updated via the external flash interface and the system

could be reconfigured with the new FPGA image. This interface is also useful to store

Nios boot code, application code, or both.

f

For more information about the Stratix remote configuration feature, refer to the

Remote System Configuration with Stratix & Stratix GX Devices chapter in the Stratix

Device Handbook.

The address, data, and control ports of the flash memory are internally connected to

the enhanced configuration device controller and to external device pins. An external

source can drive these external device pins to access the flash memory when the flash

interface is available.

This external flash interface is a shared bus interface with the configuration controller

chip. The configuration controller is the primary bus master. Since there is no bus

arbitration support, the external device can only access the flash interface when the

controller has tri-stated its internal interface to the flash. Simultaneous access by the

controller and the external device will cause contention, and result in configuration

and programming failures.

Since the internal flash interface is directly connected to the external flash interface

pins, controller flash access cycles will toggle the external flash interface pins. The

external device must be able to tri-state its flash interface during these operations and

ignore transitions on the flash interface pins.

Configuration Handbook (Complete Two-Volume Set)

1–14

Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet

Functional Description

1

The external flash interface signals cannot be shared between multiple enhanced

configuration devices because this causes contention during in-system programming

and configuration. During these operations, the controller chips inside the enhanced

configuration devices are actively accessing flash memory. Therefore, enhanced

configuration devices do not support shared flash bus interfaces.

The enhanced configuration device controller chip accesses flash memory during:

■

FPGA configuration—reading configuration data from flash

JTAG-based flash programming—storing configuration data in flash

At POR—reading option bits from flash

During these operations, the external FPGA or processor must tri-state its interface to

the flash memory. After configuration and programming, the enhanced configuration

device’s controller tri-states the internal interface and goes into an idle mode. To

interrupt a configuration cycle in order to access the flash via the external flash

interface, the external device can hold the FPGA’s nCONFIGinput low. This keeps the

configuration device in reset by holding the nSTATUS-OEline low, allowing external

flash access.

f

For more information about the software support for the external flash interface

feature, refer to the Altera Enhanced Configuration Devices chapter in volume 2 of the

Configuration Handbook. For details about flash commands, timing, memory

organization, and write protection features, refer to the following documents:

■

For Micron flash-based EPC4, refer to the Micron Flash Memory MT28F400B3 Data

Sheet at www.micron.com.

For Sharp flash-based EPC16, refer to the Sharp LHF16J06 Data Sheet Flash Memory

Used in EPC16 Devices at www.sharpsma.com.

For the Intel Advanced Boot Block Flash Memory (B3) 28F008/800B3, 28F016/160B3,

28F320B3, 28F640B3 Datasheet, visit www.intel.com.

Configuration Handbook (Complete Two-Volume Set)

Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet

1–15

Functional Description

Figure 1–4 shows an FPP configuration schematic with the external flash interface in

use.

Figure 1–4. FPP Configuration with External Flash Interface (Note 1)

Enhanced Configuration

Device

V

PLD or Processor

V

CC

Stratix Series

or

APEX II Device

WE#C

RP#C

DCLK

DATA[7..0]

OE

WE#

RP#

WE#F

RP#F

DCLK

n

A[20..0]

RY/BY#

CE#

A[20..0] (2)

RY/BY# (5)

CE#

DATA[7..0]

nSTATUS

CONF_DONE

nCONFIG

MSEL

nCEO

nCS

nINIT_CONF

OE#

N.C.

DQ[15..0]

nCE

V

CC

V (6)

CC

WP#

BYTE# (3)

VCCW

GND

TM1

PORSEL

(4)

PGM[2..0]

TMO

EXCLK

(4)

GND

C-A0 (3)

C-A1 (3)

C-A15 (3)

C-A16 (3)

A0-F

A1-F

A15-F

A16-F

Notes to Figure 1–4:

(1) For external flash interface support in EPC8 enhanced configuration device, contact Altera Applications.

(2) Pin A20in EPC16 devices, pins A20and A19in EPC8 devices, and pins A20, A19, and A18in EPC4 devices should be left floating. These pins

should not be connected to any signal; they are no-connect pins.

(3) In the 100-pin PQFP package, you must externally connect the following pins: C-A0to F-A0, C-A1to F-A1, C-A15to F-A15, C-A16to

F-A16, and BYTE#to V_CC. Additionally, you must make the following pin connections in both 100-pin PQFP and 88-pin UFBGA packages:

C-RP#to F-RP#, C-WE#to F-WE#, TM1to V_CC, TM0to GND, and WP#to V_CC

(4) For PORSEL, PGM[], and EXCLKpin connections, refer to Table 1–10.

(5) RY/BY#pin is only available for Sharp flash-based EPC8 and EPC16.

.

(6) To protect Intel Flash based EPC devices content, isolate the V_CCWsupply from V_CC. For more information, refer section “Intel-Flash-Based EPC

Device Protection” on page 1–15.

Intel-Flash-Based EPC Device Protection

In the absence of the lock bit protection feature in the EPC4, EPC8, and EPC16 devices

with Intel flash, Altera recommends four methods to protect the Intel Flash content in

EPC4, EPC8, and EPC16 devices. Any method alone is sufficient to protect the flash.

The methods are listed here in the order of descending protection level:

1. Using an RP#of less than 0.3 V on power-up and power-down for a minimum of

100 ns to a maximum 25 ms disables all control pins, making it impossible for a

write to occur.

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Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet

Functional Description

2. Using V_PP< V_PPLK, where the maximum value of V_PPLKis 1 V, disables writes.

V

_PP< V_PPLKmeans programming or writes cannot occur. V_PPis a programming

supply voltage input pin on the Intel flash. V_PPis equivalent to the VCCWpin on

EPC devices.

3. Using a high CE#disables the chip. The requirement for a write is a low CE#and

low WE#. A high CE#by itself prevents writes from occurring.

4. Using a high WE#prevent writes because a write only occurs when the WE#is low.

Performing all four methods simultaneously is the safest protection for the flash

content.

The ideal power-up sequence is as follows:

1. Power-up V_CC

2. Maintain V_PP< V_PPLKuntil V_CCis fully powered up.

3. Power-up V_PP

.

4. Drive RP#low during the entire power-up process. RP#must be released high

within 25 ms after V_PPis powered up.

1 CE#and WE#must be high for the entire power-up sequence.

The ideal power-down sequence is as follows:

1. Drive RP#low for 100ns before power-down.

2. Power-down V_PP< V_PPLK

.

3. Power-down V_CC

.

4. Drive RP#low during the entire power-down process.

1 CE#and WE#must be high for the entire power-down sequence.

The RP#pin is not internally connected to the controller. Therefore, an external

loop-back connection between C-RP#and F-RP#must be made on the board even

when you are not using the external device to the RP#pin with the loop-back. Always

tri-state RP#when the flash is not in use.

If an external power-up monitoring circuit is connected to the RP#pin with the

loop-back, use the following guidelines to avoid contention on the RP#line:

■

The power-up sequence on the 3.3-V supply should complete within 50 ms of

power-up. The 3.3-V V_CCshould reach the minimum V_CCbefore 50 ms and RP#

should then be released.

■ RP#should be driven low by the power-up monitoring circuit during power-up.

After power-up, RP#should be tri-stated externally by the power-up monitoring

circuit.

If the preceding guidelines cannot be completed within 50 ms, then the OEpin must

be driven low externally until RP#is ready to be released.

Configuration Handbook (Complete Two-Volume Set)

Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet

1–17

Functional Description

Dynamic Configuration (Page Mode)

The dynamic configuration (or page mode) feature allows the enhanced configuration

device to store up to eight different sets of designs for all the FPGAs in your system.

You can then choose which page (set of configuration files) the enhanced

configuration device should use for FPGA configuration.

Dynamic configuration or the page mode feature enables you to store a minimum of

two pages: a factory default or fail-safe configuration, and an application

configuration. The fail-safe configuration page could be programmed during system

production, while the application configuration page could support remote or local

updates. These remote updates could add or enhance system features and

performance. However, with remote update capabilities comes the risk of possible

corruption of configuration data. In the event of such a corruption, the system could

automatically switch to the fail-safe configuration and avoid system downtime.

The enhanced configuration device page mode feature works with the Stratix Remote

System Configuration feature, to enable intelligent remote updates to your systems.

f

1

For more information about remotely updating Stratix FPGAs, refer to Remote System

Configuration with Stratix & Stratix GX Devices in the Stratix Device Handbook.

The three PGM[2..0]input pins control which page is used for configuration, and

these pins are sampled at the start of each configuration cycle when OEgoes high. The

page mode selection allows you to dynamically reconfigure the functionality of your

FPGA by switching the PGM[2..0]pins and asserting nCONFIG. Page 0 is defined as

the default page and the PGM[2]pin is the most significant bit (MSB).

The PGM[2..0]input pins must not be left floating on your board, regardless of

whether this feature is used or not. When this feature is not used, connect the

PGM[2..0]pins to GND to select the default page 000.

The enhanced configuration device pages are dynamically sized regions in memory.

The start address and length of each page is programmed into the option-bit space of

the flash memory during initial programming. All subsequent configuration cycles

will sample the PGM[]pins and use the option-bit information to jump to the start of

the corresponding configuration page. Each page must have configuration files for all

FPGAs in your system that are connected to that enhanced configuration device.

For example, if your system requires three configuration pages and includes two

FPGAs, each page will store two SRAM Object Files (.sof) for a total of six .sof in the

configuration device.

Furthermore, all enhanced configuration device configuration schemes (PS, FPP, and

concurrent PS) are supported with the page-mode feature. The number of pages,

devices, or both, that can be configured using a single enhanced configuration device

is only limited by the size of the flash memory.

f

For detailed information about the page-mode feature implementation and

programming file generation steps using the Quartus II software, refer to the Altera

Enhanced Configuration Devices chapter in volume 2 of the Configuration Handbook.

Configuration Handbook (Complete Two-Volume Set)

1–18

Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet

Functional Description

Real-Time Decompression

Enhanced configuration devices support on-chip real time decompression of

configuration data. FPGA configuration data is compressed by the Quartus II

software and stored in the enhanced configuration device. During configuration, the

decompression engine inside the enhanced configuration device will decompress or

expand configuration data. This feature increases the effective-configuration density

of the enhanced configuration device up to 7, 15, or 30 Mbits in the EPC4, EPC8, and

EPC16, respectively.

The enhanced configuration device also supports a parallel 8-bit data bus to the FPGA

to reduce configuration time. However, in some cases, the FPGA data-transfer time is

limited by the flash-read bandwidth. For example, when configuring an APEX II

device in FPP (byte-wide data per cycle) mode at a configuration speed of 66 MHz,

the FPGA write bandwidth is equal to 8 bits × 66 MHz = 528 Mbps. The flash read

interface, however, is limited to approximately 10 MHz (since the flash access time is

~90 ns). This translates to a flash-read bandwidth of

16 bits × 10 MHz = 160 Mbps. Hence, the configuration time is limited by the

flash-read time.

When configuration data is compressed, the amount of data that needs to be read out

of the flash is reduced by about 50%. If 16 bits of compressed data yields 30 bits of

uncompressed data, the flash-read bandwidth increases to 30 bits × 10 MHz =

300 Mbps, reducing overall configuration time.

You can enable the controller's decompression feature in the Quartus II software,

Configuration Device Options window by turning on Compression Mode.

1

The decompression feature supported in the enhanced configuration devices is

different from the decompression feature supported by the Stratix II FPGAs and the

Cyclone series. When configuring Stratix II FPGAs or the Cyclone series using

enhanced configuration devices, Altera recommends enabling decompression in

Stratix II FPGAS or the Cyclone series only for faster configuration.

The compression algorithm used in Altera devices is optimized for FPGA

configuration bitstreams. Since FPGAs have several layers of routing structures (for

high performance and easy routability), large amounts of resources go unused. These

unused routing and logic resources as well as un-initialized memory structures result

in a large number of configuration RAM bits in the disabled state. Altera's proprietary

compression algorithm takes advantage of such bitstream qualities.

The general guideline for effectiveness of compression is the higher the device

logic/routing utilization, the lower the compression ratio (where the compression

ratio is defined as the original bitstream size divided by the compressed bitstream

size).

For Stratix designs, based on a suite of designs with varying amounts of logic

utilization, the minimum compression ratio was observed to be 1.9 or a ~47% size

reduction for these designs. Table 1–6 lists sample compression ratios from a suite of

Stratix designs. These numbers serve as a guideline (not a specification) to help you

allocate sufficient configuration memory to store compressed bitstreams.

Configuration Handbook (Complete Two-Volume Set)

Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet

1–19

Functional Description

Table 1–6. Stratix Compression Ratios (Note 1)

Item

Logic Utilization

Minimum

Average

64%

98%

1.9

Compression Ratio

% Size Reduction

Note to Table 1–6:

2.3

47%

57%

(1) These numbers are preliminary. They are intended to serve as a guideline, not a specification.

Programmable Configuration Clock

The configuration clock (DCLK) speed is user programmable. One of two clock sources

can be used to synthesize the configuration clock; a programmable oscillator or an

external clock input pin (EXCLK). The configuration clock frequency can be further

synthesized using the clock divider circuitry. This clock can be divided by the N

counter to generate your DCLKoutput. The N divider supports all integer dividers

between 1 and 16, as well as a 1.5 divider and a 2.5 divider. The duty cycle for all clock

divisions other than non-integer divisions is 50% (for the non-integer dividers, the

duty cycle will not be 50%). Refer to Figure 1–5 for a block diagram of the clock

divider unit.

Figure 1–5. Clock Divider Unit

Configuration Device

Clock Divider Unit

External Clock

(Up to 100 MHz)

Divide

by N

DCLK

10 MHz

33 MHz

50 MHz

66 MHz

Internal Oscillator

The DCLKfrequency is limited by the maximum DCLKfrequency the FPGA supports.

f

The maximum DCLKinput frequency supported by the FGPA is specified in the

appropriate FPGA family chapter in the Configuration Handbook.

Configuration Handbook (Complete Two-Volume Set)

1–20

Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet

Functional Description

The controller chip features a programmable oscillator that can output four different

frequencies. The various settings generate clock outputs at frequencies as high as 10,

33, 50, and 66 MHz, as listed in Table 1–7.

Table 1–7. Internal Oscillator Frequencies

Frequency Setting

Min (MHz)

6.4

Typ (MHz)

8.0

Max (MHz)

10.0

10

33

50

66

21.0

26.5

33.0

32.0

40.0

50.0

42.0

53.0

66.0

Clock source, oscillator frequency, and clock divider (N) settings can be made in the

Quartus II software, by accessing the Configuration Device Options inside the

Device Settings window or the Convert Programming Files window. The same

window can be used to select between the internal oscillator and the external clock

(EXCLK) input pin as your configuration clock source. The default setting selects the

internal oscillator at the 10 MHz setting as the clock source, with a divide factor of 1.

f

For more information about making the configuration clock source, frequency, and

divider settings, refer to the Altera Enhanced Configuration Devices chapter in volume 2

of the Configuration Handbook.

Flash In-System Programming (ISP)

The flash memory inside enhanced configuration devices can be programmed

in-system via the JTAG interface and the external flash interface. JTAG-based

programming is facilitated by the configuration controller in the enhanced

configuration device. External flash interface programming requires an external

processor or FPGA to control the flash.

1

The enhanced configuration device flash memory supports 100,000 erase cycles.

JTAG-based Programming

The IEEE Std. 1149.1 JTAG Boundary Scan is implemented in enhanced configuration

devices to facilitate the testing of its interconnection and functionality. Enhanced

configuration devices also support the ISP mode. The enhanced configuration device

is compliant with the IEEE Std. 1532 draft 2.0 specification.

The JTAG unit of the configuration controller communicates directly with the flash

memory. The controller processes the ISP instructions and performs the necessary

flash operations. The enhanced configuration devices support a maximum JTAG TCK

frequency of 10 MHz.

During JTAG-based ISP, the external flash interface is not available. Before the JTAG

interface programs the flash memory, an optional JTAG instruction (PENDCFG) can be

used to assert the FPGA’s nCONFIGpin (via the nINIT_CONFpin). This will keep the

FPGA in reset and terminate any internal flash access. This function prevents

contention on the flash pins when both JTAG ISP and an external FPGA or processor

try to access the flash simultaneously. The nINIT_CONFpin is released when the

initiate configuration (nINIT_CONF) JTAG instruction is updated. As a result, the

FPGA is configured with the new configuration data stored in flash.

Configuration Handbook (Complete Two-Volume Set)

Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet

1–21

Pin Description

An initiate configuration (nINIT_CONF) JTAG instruction can be added to your

programming file in the Quartus II software by enabling the Initiate configuration

after programming option in the Programmer options window (Options menu).

Programming via External Flash Interface

This method allows parallel programming of the flash memory (using the 16-bit data

bus). An external processor or FPGA acts as the flash controller and has access to

programming data (via a communication link such as UART, Ethernet, and PCI). In

addition to the program, erase, and verify operations, the external flash interface

supports block/sector protection instructions.

f

For information about protection commands, areas, and lock bits, refer to the

appropriate flash data sheets.

■

For Micron flash-based EPC4, refer to the Micron Flash Memory MT28F400B3 Data

Sheet at www.micron.com.

For Sharp flash-based EPC16, refer to the Sharp LHF16J06 Data Sheet Flash Memory

Used in EPC16 Devices at www.sharpsma.com.

For the Intel Advanced Boot Block Flash Memory (B3) 28F008/800B3, 28F016/160B3,

28F320B3, 28F640B3 Datasheet, visit www.intel.com.

External flash interface programming is only allowed when the configuration

controller has relinquished flash access (by tri-stating its internal interface). If the

controller has not relinquished flash access (during configuration or JTAG-based ISP),

you must hold the controller in reset before initiating external programming. The

controller can be reset by holding the FPGA nCONFIGline at a logic low level. This

keeps the controller in reset by holding the nSTATUS-OEline low, allowing external

flash access.

1

If initial programming of the enhanced configuration device is done in-system via the

external flash interface, the controller must be kept in reset by driving the FPGA

nCONFIGline low to prevent contention on the flash interface.

Pin Description

Table 1–8 through Table 1–10 describe the enhanced configuration device pins. These

tables include configuration interface pins, external flash interface pins, JTAG

interface pins, and other pins.

Table 1–8. Configuration Interface Pins (Part 1 of 2)

Pin Name

Pin Type

Description

DATA[7..0]

Output

Configuration data output bus. DATAchanges on each falling edge of DCLK.

DATAis latched into the FPGA on the rising edge of DCLK.

DCLK

Output

The DCLKoutput pin from the enhanced configuration device serves as the FPGA

configuration clock. DATAis latched by the FPGA on the rising edge of DCLK.

Configuration Handbook (Complete Two-Volume Set)

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Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet

Pin Description

Table 1–8. Configuration Interface Pins (Part 2 of 2)

Pin Name

nCS

Pin Type

Description

Input

The nCSpin is an input to the enhanced configuration device and is connected to

the FPGA’s CONF_DONEsignal for error detection after all configuration data is

transmitted to the FPGA. The FPGA will always drive nCSand OElow when

nCONFIGis asserted. This pin contains a programmable internal weak pull-up

resistor of 6K  that can be disabled/enabled in the Quartus II software through

the Disable nCS and OE pull-ups on configuration device option.

nINIT_CONF

Open-Drain Output The nINIT_CONFpin can be connected to the nCONFIGpin on the FPGA to

initiate configuration from the enhanced configuration device via a private JTAG

instruction. This pin contains an internal weak pull-up resistor of 6K that is

always active. The INIT_CONFpin does not need to be connected if its

functionality is not used. If nINIT_CONFis not used, nCONFIGmust be pulled

to V_CCeither directly or through a pull-up resistor.

OE

Open-Drain

Bidirectional

This pin is driven low when POR is not complete. A user-selectable 2-ms or

100-ms counter holds off the release of OEduring initial power up to permit

voltage levels to stabilize. POR time can be extended by externally holding OE

low. OEis connected to the FPGA nSTATUSsignal. After the enhanced

configuration device controller releases OE, it waits for the nSTATUS-OEline to

go high before starting the FPGA configuration process. This pin contains a

programmable internal weak pull-up resistor of 6K that can be

disabled/enabled in the Quartus II software through the Disable nCS and OE

pull-ups on configuration device option.

Table 1–9. External Flash Interface Pins (Part 1 of 3)

Pin Name

Pin Type

Description

A[20..0]

Input

These pins are the address input to the flash memory for read and write

operations. The addresses are internally latched during a write cycle.

When the external flash interface is not used, leave these pins floating (with a few

exceptions(1)). These flash address, data, and control pins are internally

connected to the configuration controller.

In the 100-pin PQFP package, four address pins (A0, A1, A15, A16) are not

internally connected to the controller. These loop-back connections must be made

on the board between the C-A[]and F-A[]pins even when not using the

external flash interface. All other address pins are connected internal to the

package.

All address pins are connected internally in the 88-pin UFBGA package.

Pin A20in EPC16 devices, pins A20and A19in EPC8 devices, and pins A20,

A19, and A18in EPC4 devices are no-connects. These pins should be left

floating on the board.

DQ[15..0]

Bidirectional

This is the flash data bus interface between the flash memory and the controller.

The controller or an external source drives DQ[15..0]during the flash

command and the data write bus cycles. During the data read cycle, the flash

memory drives the DQ[15..0]to the controller or external device.

Leave these pins floating on the board when the external flash interface is not

used.

CE#

Input

Active low flash input pin that activates the flash memory when asserted. When it

is high, it deselects the device and reduces power consumption to standby levels.

This flash input pin is internally connected to the controller.

Leave this pin floating on the board when the external flash interface is not used.

Configuration Handbook (Complete Two-Volume Set)

Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet

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Pin Description

Table 1–9. External Flash Interface Pins (Part 2 of 3)

Pin Name

RP#(1)

Pin Type

Description

Input

Active low flash input pin that resets the flash when asserted. When high, it

enables normal operation. When low, it inhibits write operation to the flash

memory, which provides data protection during power transitions.

This flash input is not internally connected to the controller. Hence, an external

loop-back connection between C-RP#and F-RP#must be made on the board

even when you are not using the external flash interface.

When using the external flash interface, connect the external device to the RP#

pin with the loop back. Always tri-state RP#when the flash is not in use.

OE#

Input

Active-low flash-control input that is asserted by the controller or external device

during flash read cycles. When asserted, it enables the drivers of the flash output

pins.

Leave this pin floating on the board when the external flash interface is not used.

WE#(1)

Active-low flash-write strobe asserted by the controller or external device during

flash write cycles. When asserted, it controls writes to the flash memory. In the

flash memory, addresses and data are latched on the rising edge of the WE#

pulse.

This flash input is not internally connected to the controller. Hence, an external

loop-back connection between C-WE#and F-WE#must be made on the board

even when you are not using the external flash interface.

When using the external flash interface, connect the external device to the WE#

pin with the loop back.

WP#

Input

Usually tied to V_CCor ground on the board. The controller does not drive this pin

because it could cause contention.

Connection to V_CCis recommended for faster block erase/programming times and

to allow programming of the flash-bottom boot block, which is required when

programming the device using the Quartus II software.

This pin should be connected to V_CCeven when the external flash interface is not

used.

V_CCW

Supply

Block erase, full-chip erase, word write, or lock-bit configuration power supply.

Connect this pin to the 3.3-V V_CCsupply, even when you are not using the external

flash interface.

RY/BY#

Open-Drain Output Flash asserts this pin when a write or erase operation is complete. This pin is not

connected to the controller. RY/BY#is only available in Sharp flash-based EPC8

and EPC16. (2)

Leave this pin floating when the external flash interface is not used.

Configuration Handbook (Complete Two-Volume Set)

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Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet

Pin Description

Table 1–9. External Flash Interface Pins (Part 3 of 3)

Pin Name

BYTE#

Pin Type

Description

Input

Flash byte-enable pin and is only available for enhanced configuration devices in

the 100-pin PQFP package.

This pin must be connected to V_CCon the board even when you are not using the

external flash interface (the controller uses the flash in 16-bit mode). For Intel

flash-based EPC device, this pin is connected to the V_CCQof the Intel flash die

internally. Therefore, BYTE#must be connected directly to V_CCwithout using any

pull-up resistor.

Notes to Table 1–9:

(1) These pins can be driven to 12 V during production testing of the flash memory. Since the controller cannot tolerate the 12-V level, connections

from the controller to these pins are not made internal to the package. Instead they are available as two separate pins. You must connect the

two pins at the board level (for example, on the printed circuit board (PCB), connect the C-WE#pin from controller to F-WE#pin from the

flash memory).

(2) For more information, refer to the Process Change Notification PCN0506: Addition of Intel Flash Memory As Source For EPC4, EPC8 and EPC16

Enhanced Configuration Devices and Using the Intel Flash Memory-Based EPC4, EPC8 and EPC16 white paper.

Table 1–10. JTAG Interface Pins and Other Required Controller Pins

Pin Name

TDI

Pin Type

Description

Input

JTAG data input pin.

Connect this pin to V_CCif the JTAG circuitry is not used.

JTAG data output pin.

TDO

Output

Input

Do not connect this pin if the JTAG circuitry is not used (leave floating).

JTAG clock pin.

TCK

Connect this pin to GND if the JTAG circuitry is not used.

JTAG mode select pin.

TMS

Connect this pin to V_CCif the JTAG circuitry is not used.

PGM[2..0]

These three input pins select one of the eight pages of configuration data to

configure the FPGAs in the system.

Connect these pins on the board to select the page specified in the Quartus II

software when generating the enhanced configuration device POF. PGM[2]is the

MSB. The default selection is page 0; PGM[2..0]=000. These pins must not be

left floating.

EXCLK

Input

Optional external clock input pin that can be used to generate the configuration

clock (DCLK).

When an external clock source is not used, connect this pin to a valid logic level

(high or low) to prevent a floating-input buffer. If EXCLKis used, toggling the

EXCLKinput pin after the FPGA enters user mode will not effect the enhanced

configuration device operation.

PORSEL

This pin selects a 2-ms or 100-ms POR counter delay during power up. When

PORSELis low, POR time is 100 ms. When PORSELis high, POR time is 2 ms.

This pin must be connected to a valid logic level.

TM0

TM1

Input

For normal operation, this test pin must be connected to GND.

For normal operating, this test pin must be connected to V_CC.

Configuration Handbook (Complete Two-Volume Set)

Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet

1–25

Power-On Reset

The POR circuit keeps the system in reset until power-supply voltage levels have

stabilized. The POR time consists of the V_CCramp time and a user-programmable

POR delay counter. When the supply is stable and the POR counter expires, the POR

circuit releases the OEpin. The POR time can be further extended by an external

device by driving the OEpin low.

1

Do not execute JTAG or ISP instructions until POR is complete.

The enhanced configuration device supports a programmable POR delay setting. You

can set the POR delay to the default 100-ms setting or reduce the POR delay to 2 ms

for systems that require fast power-up. The PORSELinput pin controls this POR

delay; a logic-high level selects the 2-ms delay, while a logic-low level selects the

100-ms delay.

The enhanced configuration device can enter reset under the following conditions:

■

The POR reset starts at initial power-up during V_CCramp-up or if V_CCdrops

below the minimum operating condition anytime after V_CChas stabilized

The FPGA initiates reconfiguration by driving nSTATUSlow, which occurs if the

FPGA detects a CRC error or if the FPGA’s nCONFIGinput pin is asserted

The controller detects a configuration error and asserts OEto begin

re-configuration of the Altera FPGA (for example, when CONF_DONEstays low

after all configuration data has been transmitted)

Power Sequencing

Altera requires that you power-up the FPGA's V_CCINTsupply before the enhanced

configuration device's POR expires.

Power up needs to be controlled so that the enhanced configuration device’s OEsignal

goes high after the CONF_DONEsignal is pulled low. If the EEPC device exits POR

before the FPGA is powered up, the CONF_DONEsignal will be high because the

pull-up resistor is holding this signal high. When the enhanced configuration device

exits POR, OEis released and pulled high by a pull-up resistor. Since the enhanced

configuration device samples the nCSsignal on the rising edge of OE, it detects a high

level on CONF_DONEand enters an idle mode. DATAand DCLKoutputs will not toggle

in this state and configuration will not begin. The enhanced configuration device will

only exit this mode if it is powered down and then powered up correctly.

1

To ensure the enhanced configuration device enters configuration mode properly, you

must ensure that the FPGA completes power-up before the enhanced configuration

device exits POR.

The pin-selectable POR time feature is useful for ensuring this power-up sequence.

The enhanced configuration device has two POR settings, 2 ms when PORSELis set to

a high level and 100 ms when PORSELis set to a low level. For more margin, the

100-ms setting can be selected to allow the FPGA to power-up before configuration is

attempted.

Configuration Handbook (Complete Two-Volume Set)

1–26

Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet

Programming and Configuration File Support

Alternatively, a power-monitoring circuit or a power-good signal can be used to keep

the FPGA’s nCONFIGpin asserted low until both supplies have stabilized. This

ensures the correct power up sequence for successful configuration.

Programming and Configuration File Support

The Quartus II software provides programming support for the enhanced

configuration device and automatically generates the .pof for the EPC4, EPC8, and

EPC16 devices. In a multi-device project, the software can combine the .sof for

multiple ACEX 1K, APEX 20K, APEX II, Cyclone series, FLEX 10K, Mercury, and

Stratix series FPGAs into one programming file for the enhanced configuration

device.

f

For details about generating programming files, refer to the Altera Enhanced

Configuration Devices chapter and the Software Settings section in volume 2 of the

Configuration Handbook.

Enhanced configuration devices can be programmed in-system through the

industry-standard 4-pin JTAG interface. The ISP feature in the enhanced

configuration device provides ease in prototyping and updating FPGA functionality.

After programming an enhanced configuration device in-system, FPGA configuration

can be initiated by including the enhanced configuration device’s JTAG INIT_CONF

instruction (Table 1–11).

The ISP circuitry in the enhanced configuration device is compliant with the IEEE Std.

1532 specification. The IEEE Std. 1532 is a standard that allows concurrent ISP

between devices from multiple vendors.

Table 1–11. Enhanced Configuration Device JTAG Instructions (Part 1 of 2) (Note 1)

JTAG Instruction

OPCODE

Description

SAMPLE/

PRELOAD

00 0101 0101 Allows a snapshot of the state of the enhanced configuration device pins to be

captured and examined during normal device operation and permits an initial

data pattern output at the device pins.

EXTEST

BYPASS

00 0000 0000 Allows the external circuitry and board-level interconnections to be tested by

forcing a test pattern at the output pins and capturing results at the input pins.

11 1111 1111 Places the 1-bit bypass register between the TDIand the TDOpins, which allow

the BST data to pass synchronously through a selected device to adjacent

devices during normal device operation.

IDCODE

00 0101 1001 Selects the device IDCODEregister and places it between TDIand TDO,

allowing the device IDCODEto be serially shifted out to TDO. The device

IDCODEfor all enhanced configuration devices is the same and shown below:

0100A0DDh

USERCODE

00 0111 1001 Selects the USERCODEregister and places it between TDIand TDO, allowing

the USERCODEto be serially shifted out the TDO. The 32-bit USERCODEis a

programmable user-defined pattern.

Configuration Handbook (Complete Two-Volume Set)

Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet

1–27

Programming and Configuration File Support

Table 1–11. Enhanced Configuration Device JTAG Instructions (Part 2 of 2) (Note 1)

JTAG Instruction

OPCODE

Description

INIT_CONF

00 0110 0001 This function initiates the FPGA re-configuration process by pulsing the

nINIT_CONFpin low, which is connected to the FPGA nCONFIGpin. After

this instruction is updated, the nINIT_CONFpin is pulsed low when the JTAG

state machine enters Run-Test/Idlestate. The nINIT_CONFpin is then

released and nCONFIGis pulled high by the resistor after the JTAG state

machine goes out of Run-Test/Idlestate. The FPGA configuration starts after

nCONFIGgoes high. As a result, the FPGA is configured with the new

configuration data stored in flash via ISP. This function can be added to your

programming file (.pof, .jam, .jbc) in the Quartus II software by enabling the

Initiate configuration after programming option in the Programmer options

window (Options menu).

PENDCFG

00 0110 0101 This optional function can be used to hold the nINIT_CONFpin low during

JTAG-based ISP of the enhanced configuration device. This feature is useful

when the external flash interface is controlled by an external FPGA/processor.

This function prevents contention on the flash pins when both the controller and

external device try to access the flash simultaneously. Before the enhanced

configuration device’s controller can access the flash memory, the external

FPGA/processor needs to tri-state its interface to flash.This can be ensured by

resetting the FPGA using the nINIT_CONF, which drives the nCONFIGpin and

keeps the external FPGA/processor in the “reset” state. The nINIT_CONFpin is

released when the initiate configuration (INIT_CONF) JTAG instruction is

issued.

Note to Table 1–11:

(1) Enhanced configuration device instruction register length is 10 and boundary scan length is 174.

f

For more information about the enhanced configuration device JTAG support, refer to

the BSDL files provided at the Altera website.

Enhanced configuration devices can also be programmed by third-party flash

programmers or on-board processors using the external flash interface. Programming

files (.pof) can be converted to an Intel HEX format file (.hexout) using the Quartus II

Convert Programming Files utility, for use with the programmers or processors.

You can also program the enhanced configuration devices using the Quartus II

software, the Altera Programming Unit (APU), and the appropriate configuration

device programming adapter. Table 1–12 lists which programming adapter to use

with each enhanced configuration device.

Table 1–12. Programming Adapters

Device

Package

88-pin UFBGA

Adapter

PLMUEPC-88

EPC16

100-pin PQFP

PLMQEPC-100

EPC8

EPC4

Configuration Handbook (Complete Two-Volume Set)

1–28

Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet

IEEE Std. 1149.1 (JTAG) Boundary-Scan

The enhanced configuration device provides JTAG BST circuitry that complies with

the IEEE Std. 1149.1-1990 specification. JTAG boundary-scan testing can be performed

before or after configuration, but not during configuration.

Figure 1–6 shows the timing requirements for the JTAG signals.

Figure 1–6. JTAG Timing Waveforms

TMS

TDI

t_JCP

t_JCH

t_JCL

t_JPH

t_JPSU

TCK

TDO

t_JPZX

t_JPCO

t_JPXZ

t_JSSU

t_JSH

Signal

to be

Captured

t_JSZX

t_JSCO

t_JSXZ

Signal

to be

Driven

Table 1–13 lists the timing parameters and values for the enhanced configuration

device.

Table 1–13. JTAG Timing Parameters and Values

Symbol Parameter

Min

100

50

20

45

—

20

45

—

Max

—

25

—

25

Unit

ns

t_JCP

TCKclock period

t_JCH

TCKclock high time

TCKclock low time

t_JCL

t_JPSU

t_JPH

JTAG port setup time

JTAG port hold time

t_JPCO

t_JPZX

t_JPXZ

t_JSSU

t_JSH

JTAG port clock output

JTAG port high impedance to valid output

JTAG port valid output to high impedance

Capture register setup time

Capture register hold time

t_JSCO

t_JSZX

t_JSXZ

Update register clock to output

Update register high-impedance to valid output

Update register valid output to high impedance

Configuration Handbook (Complete Two-Volume Set)

Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet

1–29

Timing Information

Figure 1–7 shows the configuration timing waveform when using an enhanced

configuration device.

Figure 1–7. Configuration Timing Waveform Using an Enhanced Configuration Device

nINIT_CONF or VCC/nCONFIG

t_POR

OE/nSTATUS

nCS/CONF_DONE

t_CH

t_DSU

t_CL

DCLK

t_OEZX

t_DH

Byte0 Byte1 Byte2 Byte3

Byten

DATA[7..0]

(2)

t_CO

User I/O

User Mode

Tri-State

INIT_DONE

Notes to Figure 1–7:

(1) The enhanced configuration device will drive DCLKlow after configuration.

(2) The enhanced configuration device will drive DATA[]high after configuration.

Table 1–14 defines the timing parameters when using the enhanced configuration

devices.

f

For more information about the flash memory (external flash interface) timing, refer

to the appropriate flash data sheet on the Altera website at www.altera.com.

■

For Micron flash-based EPC4, refer to the Micron MT28F400B3 Data Sheet Flash

Memory Used in EPC4 Devices at www.micron.com.

For Sharp flash-based EPC16, refer to the Sharp LHF16J06 Data Sheet Flash Memory

Used in EPC16 Devices at www.sharpsma.com.

For Intel flash-based EPC4 and EPC16, refer to Intel Flash 28F016B3 at

www.intel.com.

Table 1–14. Enhanced Configuration Device Configuration Parameters (Part 1 of 2)

Symbol

f_DCLK

t_DCLK

t_HC

Parameter

DCLKfrequency

Condition

Min

—

15

6

Typ

—

Max

66.7

—

Unit

MHz

ns

40% duty cycle

DCLKperiod

—

DCLKduty cycle high time

DCLKduty cycle low time

OEto first DCLKdelay

40% duty cycle

—

ns

t_LC

40% duty cycle

6

—

ns

t_CE

—

40

(1)

277

60

—

ns

t_OE

OEto first DATAavailable

DCLKrising edge to DATAchange

OEassert to DCLKdisable delay

OEassert to DATAdisable delay

DCLKrising edge to OE

—

ns

t_OH

—

ns

t_CF(2)

—

ns

t

_DF(2)

_RE(3)

—

ns

t

—

ns

Configuration Handbook (Complete Two-Volume Set)

1–30

Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet

Operating Conditions

Table 1–14. Enhanced Configuration Device Configuration Parameters (Part 2 of 2)

Symbol

Parameter

OEassert time to assure reset

EXCLKinput frequency

EXCLKinput period

Condition

—

Min

60

—

10

4

Typ

—

2

Max

—

100

—

3

Unit

ns

t_LOE

f_ECLK

40% duty cycle

—

MHz

ns

t_ECLK

t_ECLKH

t_ECLKL

t_ECLKR

t_ECLKF

t_POR(4)

EXCLKinput duty cycle high time

EXCLKinput duty cycle low time

EXCLKinput rise time

EXCLKinput fall time

40% duty cycle

100 MHz

2 ms

ns

4

ns

—

1

ns

3

ns

POR time

3

ms

100 ms

70

100

120

Notes to Table 1–14:

(1) To calculate t_OH, use the following equation: t_OH= 0.5 (DCLKperiod) - 2.5 ns.

(2) This parameter is used for CRC error detection by the FPGA.

(3) This parameter is used for CONF_DONEerror detection by the enhanced configuration device.

(4) The FPGA V_CCINTramp time should be less than 1-ms for 2-ms POR, and it should be less than 70 ms for 100-ms POR.

Operating Conditions

Table 1–15 through Table 1–19 provide information about absolute maximum ratings,

recommended operating conditions, DC operating conditions, supply current values,

and pin capacitance data for the enhanced configuration devices.

Table 1–15. Enhanced Configuration Device Absolute Maximum Rating

Symbol

Parameter

Supply voltage

Condition

Min

-0.2

-0.5

—

Max

4.6

Unit

V

V_CC

V_I

With respect to ground

DC input voltage

With respect to ground

3.6

V

I_MAX

I_OUT

P_D

DC V_CCor ground current

DC output current, per pin

Power dissipation

—

100

25

mA

mW

C

-25

—

360

150

135

T_STG

T_AMB

T_J

Storage temperature

Ambient temperature

Junction temperature

No bias

Under bias

-65

—

C

Table 1–16. Enhanced Configuration Device Recommended Operating Conditions

Symbol

V_CC

Parameter

Supplies voltage for 3.3-V operation

Input voltage

Condition

Min

Max

3.6

Unit

V

—

3.0

–0.3

0

V_I

With respect to ground

V_CC+ 0.3

V_CC

V

V_O

T_A

Output voltage

—

V

Operating temperature

For commercial use

0

70

C

For industrial use

–40

—

85

C

T_R

T_F

Input rise time

Input fall time

—

20

ns

—

20

Configuration Handbook (Complete Two-Volume Set)

Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet

1–31

Package

Table 1–17. Enhanced Configuration Device DC Operating Conditions

Symbol

V_CC

Parameter

Supplies voltage to core

High-level input voltage

Condition

Min

3.0

2.0

Typ

3.3

—

Max

Unit

—

3.6

V

V_IH

V_CC

+

0.3

V_IL

Low-level input voltage

—

0.8

—

V

V_OH

3.3-V mode high-level TTL output

voltage

I_OH= –4 mA

2.4

3.3-V mode high-level CMOS

output voltage

I_OH= –0.1 mA

V_CC

0.2

–

—

V

V_OL

Low-level output voltage TTL

Low-level output voltage CMOS

Input leakage current

I_OL= –4 mA DC

_OL= –0.1 mA DC

—

0.45

0.2

10

V

I

I_I

V_I= V_CCor ground

V_O= V_CCor ground

–10

A

I_OZ

Tri-state output off-state current

10

Table 1–18. Enhanced Configuration Device I_CCSupply Current Values

Symbol

Parameter

Current (standby)

Condition

Min

—

Typ

50

Max

Unit

A

I_CC0

I_CC1

—

150

90

V_CCsupply current (during

configuration)

—

60

mA

I_CCW

V_CCWsupply current

—

(1)

—

Note to Table 1–18:

(1) For V_CCWsupply current information, refer to the appropriate flash memory data sheet at www.altera.com.

Table 1–19. Enhanced Configuration Device Capacitance

Symbol

Parameter

Input pin capacitance

Output pin capacitance

Condition

Min

—

Max

Unit

CIN

—

10

pF

COUT

—

Package

The EPC16 enhanced configuration device is available in both the 88-pin UFBGA

package and the 100-pin PQFP package. The UFBGA package, which is based on

0.8-mm ball pitch, maximizes board space efficiency. A board can be laid out for this

package using a single PCB layer. The EPC8 and EPC4 devices are available in the

100-pin PQFP package.

Enhanced configuration devices support vertical migration in the 100-pin PQFP

package.

Configuration Handbook (Complete Two-Volume Set)

1–32

Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet

Package

Figure 1–8 shows the PCB routing for the 88-pin UFBGA package. The Gerber file for

this layout is on the Altera website.

Figure 1–8. PCB Routing for 88-Pin UFBGA Package (Note 1)

DCLK

DQ7

DQ5

VCC

DQ3

NC

VCC

A20

A16

A11

A8

A15

A10

A14

A9

A13

A12

PGM0

DQ6

GND

DQ14

DQ4

VCC

DQ2

DATA7

DATA5

DATA4

DATA3

DATA2

NC

OE

C-WE#

(2)

DQ15

DQ13

DQ12

VCC

DATA6

nINIT

TCK

TDI

F-WE#

(2)

RY/BY#

(4)

PGM1

VCC

DQ11

CONF

F-RP#

(2)

GND

(5)

TM1

A19

C-RP#

(2)

WP#

TDO

VCCW

DQ10

(3)

TMS

nCS

NC

PGM2

A7

PORSEL

A6

DQ9

A3

DQ8

A2

DQ0

A1

DQ1

DATA1

VCC

NC

A18

A17

VCC

GND

DATA0

GND

EXCLK

A5

A4

A0

CE#

GND

OE#

TM0

GND

NC

Notes to Figure 1–8:

(1) If the external flash interface feature is not used, then the flash pins should be left unconnected because they are internally connected to the

controller unit. The only pins that need external connections are WP#, WE#, and RP#. If the flash is being used as an external memory source,

then the flash pins should be connected as outlined in the pin descriptions section.

(2) F-RP#and F-WE#are pins on the flash die. C-RP#and C-WE#are pins on the controller die. C-WE#and F-WE#should be connected together

on the PCB. F-RP#and C-RP#should also be connected together on the PCB.

(3) WP#(write protection pin) should be connected to a high level (3.3 V) to be able to program the flash bottom boot block, which is required when

programming the device using the Quartus II software.

(4) RY/BY#is only available in Sharp flash-based enhanced configuration devices.

(5) Pin D3is a NCpin for Intel Flash-based EPC16.

Package Layout Recommendation

Sharp flash-based EPC16 and EPC8 enhanced configuration devices in the 100-pin

PQFP packages have different package dimensions than other Altera 100-pin PQFP

devices (including the Micron flash-based EPC4, Intel flash-based EPC16, EPC8 and

EPC4). Figure 1–9 shows the 100-pin PQFP PCB footprint specifications for enhanced

configuration devices that allows for vertical migration between all devices. These

footprint dimensions are based on vendor-supplied package outline diagrams.

Configuration Handbook (Complete Two-Volume Set)

Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet

1–33

Device Pin-Outs

Figure 1–9. Enhanced Configuration Device PCB Footprint Specifications for 100-Pin PQFP Packages (Note 1), (2)

0.65-mm Pad Pitch

0.325 mm

19.3 mm

0.410 mm

25.3 mm

2.4 mm

0.5

1.5

1.0

2.0mm

Notes to Figure 1–9:

(1) Used 0.5-mm increase for front and back of nominal foot length.

(2) Used 0.3-mm increase to maximum foot width.

f

For package outline drawings, refer to the Altera Device Package Information Data Sheet.

Device Pin-Outs

f

For pin-out information, refer to Altera Configuration Devices Pin-Out Files.

Configuration Handbook (Complete Two-Volume Set)

1–34

Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet

Chapter Revision History

Table 1–20 lists the revision history for this chapter.

Table 1–20. Chapter Revision History

Date

Version

Changes Made

December 2009

2.8

■ Added Table 1–1 and Table 1–2.

■ Updated Table 1–17 and Table 1–18.

■ Removed “Referenced Documents” section.

■ Updated Table 2–1, Table 2–7, and Table 2–8.

■ Updated Figure 2–2, Figure 2–3, and Figure 2–4.

■ Updated “JTAG-based Programming” section.

■ Added “Intel-Flash-Based EPC Device Protection” section.

■ Updated new document format.

October 2008

2.7

May 2008

2.6

2.5

2.4

2.3

2.2

2.0

■ Minor textual and style changes. Added “Referenced Documents” section.

■ Updated Table 2–18 with information about EPC16UI88AA.

■ Added “Intel-Flash-Based EPC Device Protection” section.

■ Added document revision history.

February 2008

May 2007

April 2007

October 2005

July 2004

■ Made changes to content.

■ Added Stratix II and Cyclone II device information throughout chapter.

■ Updated VCCW connection in Figure 2–2, Figure 2–3, and Figure 2–4.

■ Updated (Note 2) of Figure 2–2, Figure 2–3, and Figure 2–4.

■ Updated (Note 4) of Table 2–12.

■ Updated unit of ICC0 in Table 2–16.

■ Added ICCW to Table 2–16.

September 2003

1.0

■ Initial Release.

Configuration Handbook (Complete Two-Volume Set)


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