EP20K1000EBC652XES [ALTERA]
Loadable PLD, PBGA652, 45 X 45 MM, 1.27 MM PITCH, BGA-652;型号: | EP20K1000EBC652XES |
厂家: | ALTERA CORPORATION |
描述: | Loadable PLD, PBGA652, 45 X 45 MM, 1.27 MM PITCH, BGA-652 |
文件: | 总107页 (文件大小:1513K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
APEX 20K
Programmable Logic
Device Family
®
December 2000, ver. 3.2
Data Sheet
ꢀ
Industry’s first programmable logic device (PLD) incorporating
system-on-a-programmable-chip integration
–
Features...
MultiCoreTM architecture integrating look-up table (LUT) logic,
product-term logic, and embedded memory
–
–
LUT logic used for register-intensive functions
Embedded system block (ESB) used to implement memory
functions, including first-in first-out (FIFO) buffers, dual-port
RAM, and content-addressable memory (CAM)
ESB implementation of product-term logic used for
combinatorial-intensive functions
Preliminary
Information
–
ꢀ
High density
–
–
–
30,000 to 1.5 million typical gates (see Tables 1 and 2)
Up to 51,840 logic elements (LEs)
Up to 442,368 RAM bits that can be used without reducing
available logic
–
Up to 3,456 product-term-based macrocells
Table 1. APEX 20K Device Features
Note (1)
Feature
EP20K30E EP20K60E EP20K100 EP20K100E EP20K160E EP20K200
EP20K200E
Maximum
system
gates
113,000
162,000
263,000
100,000
263,000
404,000
526,000
526,000
Typical
gates
30,000
60,000
100,000
160,000
200,000
200,000
LEs
1,200
12
2,560
16
4,160
26
4,160
26
6,400
40
8,320
52
8,320
52
ESBs
Maximum
RAM bits
24,576
32,768
53,248
53,248
81,920
106,496
106,496
Maximum
macrocells
192
128
256
196
416
252
416
246
640
316
832
382
832
376
Maximum
user I/O
pins
Altera Corporation
1
A-DS-APEX20K-03.2
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
Table 2. APEX 20K Device Features
Note (1)
Feature
EP20K300E EP20K400 EP20K400E EP20K600E
EP20K1000E EP20K1500E
Maximum
728,000
1,052,000
1,052,000
1,537,000
1,772,000
2,392,000
system gates
Typical gates
LEs
300,000
11,520
72
400,000
16,640
104
400,000
16,640
104
600,000
24,320
152
1,000,000
38,400
160
1,500,000
51,840
216
ESBs
Maximum
RAM bits
147,456
212,992
212,992
311,296
327,680
442,368
Maximum
macrocells
1,152
408
1,664
502
1,664
488
2,432
588
2,560
708
3,456
808
Maximum user
I/O pins
Note to tables:
(1) The embedded IEEE Std. 1149.1 Joint Test Action Group (JTAG) boundary-scan circuitry contributes up to
57,000 additional gates.
2
Altera Corporation
Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
ꢀ
ꢀ
Designed for low-power operation
...and More
Features
–
–
1.8-V and 2.5-V supply voltage (see Table 3)
MultiVoltTM I/O interface support to interface with 1.8-V, 2.5-V,
3.3-V, and 5.0-V devices (see Table 3)
–
ESB offering programmable power-saving mode
Flexible clock management circuitry with up to four phase-locked
loops (PLLs)
–
–
–
–
Built-in low-skew clock tree
Up to eight global clock signals
ClockLockTM feature reducing clock delay and skew
ClockBoostTM feature providing clock multiplication and
division
–
ClockShiftTM programmable clock phase and delay shifting
ꢀ
Powerful I/O features
–
Compliant with peripheral component interconnect Special
Interest Group (PCI SIG) PCI Local Bus Specification,
Revision 2.2 for 3.3-V operation at 33 or 66 MHz and 32 or 64 bits
Support for high-speed external memories, including DDR
SDRAM and ZBT SRAM (ZBT is a trademark of Integrated
Device Technology, Inc.)
–
–
–
–
Bidirectional I/O performance (t + t ) up to 250 MHz
LVDS performance up to 840 Mbits per channel
Direct connection from I/O pins to local interconnect providing
CO SU
fast t and t times for complex logic
CO
SU
–
MultiVolt I/O interface support to interface with 1.8-V, 2.5-V,
3.3-V, and 5.0-V devices (see Table 3)
–
–
–
Programmable clamp to V
CCIO
Individual tri-state output enable control for each pin
Programmable output slew-rate control to reduce switching
noise
–
Support for advanced I/O standards, including low-voltage
differential signaling (LVDS), LVPECL, PCI-X, AGP, CTT, stub-
series terminated logic (SSTL-3 and SSTL-2), Gunning
transceiver logic plus (GTL+), and high-speed terminated logic
(HSTL Class I)
–
–
Supports hot-socketing operation
Pull-up on I/O pins before and during configuration
Altera Corporation
3
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
Table 3. APEX 20K Supply Voltages
Feature
EP20K100
EP20K200
EP20K400
EP20K30E
EP20K60E
EP20K100E
EP20K160E
EP20K200E
EP20K300E
EP20K400E
EP20K600E
EP20K1000E
EP20K1500E
Internal supply voltage (V
)
2.5 V
1.8 V
CCINT
MultiVolt I/O interface voltage
2.5 V, 3.3 V, 5.0 V (1)
1.8 V, 2.5 V, 3.3 V,
levels (V
)
5.0 V (2)
CCIO
Notes :
(1) Certain APEX 20K devices are 5.0-V tolerant. See “MultiVolt I/O Interface” on page
46 for details.
(2) APEX 20KE devices can be 5.0-V tolerant by using an external resistor.
ꢀ
Advanced interconnect structure
–
Four-level hierarchical FastTrack® Interconnect structure
providing fast, predictable interconnect delays
Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators (automatically used by
software tools and megafunctions)
–
–
–
Dedicated cascade chain that implements high-speed,
high-fan-in logic functions (automatically used by software tools
and megafunctions)
Interleaved local interconnect allows one LE to drive 29 other
LEs through the fast local interconnect
ꢀ
ꢀ
Advanced packaging options
–
Available in a variety of packages with 144 to 1,020 pins (see
Tables 4 through 7)
–
FineLine BGATM packages maximize board space efficiency
Advanced software support
–
Software design support and automatic place-and-route
provided by the Altera® QuartusTM development system for
Windows-based PCs, Sun SPARCstations, and HP 9000
Series 700/800 workstations
–
–
Altera MegaCore® functions and Altera Megafunction Partners
Program (AMPPSM) megafunctions
NativeLinkTM integration with popular synthesis, simulation,
and timing analysis tools
4
Altera Corporation
Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
–
–
Quartus SignalTapTM embedded logic analyzer simplifies
in-system design evaluation by giving access to internal nodes
during device operation
Supports popular revision-control software packages including
PVCS, Revision Control System(RCS), and Source Code Control
System(SCCS )
Table 4. APEX 20K QFP, BGA & PGA Package Options & I/O Count
Notes (1), (2)
Device
144-Pin
TQFP
208-Pin
PQFP
240-Pin
PQFP
356-Pin BGA 652-Pin BGA 655-Pin PGA
RQFP
RQFP
EP20K30E
EP20K60E
EP20K100
92
92
125
148
159
151
143
144
136
151
189
183
175
174
168
152
196
252
246
271
277
101
92
EP20K100E
EP20K160E
EP20K200
88
EP20K200E
EP20K300E
EP20K400
271
376
408
502
488
488
488
488
502
EP20K400E
EP20K600E
EP20K1000E
EP20K1500E
Table 5. APEX 20K FineLine BGA Package Options & I/O Count
, Notes (1), (2)
Device
196-Pin
324-Pin
484-Pin
672-Pin
1,020-Pin
EP20K30E
EP20K60E
EP20K100
93
93
128
196
252
246
EP20K100E
EP20K160E
EP20K200
93
316
382
376
EP20K200E
EP20K300E
EP20K400
376
408
502 (3)
488 (3)
508 (3)
508 (3)
EP20K400E
EP20K600E
EP20K1000E
EP20K1500E
588
708
808
Altera Corporation
5
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
Notes to tables:
(1) I/O counts include dedicated input and clock pins.
(2) APEX 20K device package types include thin quad flat pack (TQFP), plastic quad flat pack (PQFP), power quad flat
pack (RQFP), 1.27-mm pitch ball-grid array (BGA), 1.00-mm pitch FineLine BGA, and pin-grid array (PGA)
packages.
(3) This device uses a thermally enhanced package, which is taller than the regular package. Consult the Altera Device
Package Information Data Sheet for detailed package size information.
Table 6. APEX 20K QFP, BGA & PGA Package Sizes
Feature
144-Pin TQFP 208-Pin QFP 240-Pin QFP 356-Pin BGA 652-Pin BGA 655-Pin PGA
Pitch (mm)
0.50
484
0.50
924
0.50
1,218
1.27
1,225
1.27
2,025
–
2
Area (mm )
3,906
Length × Width
(mm × mm)
22 × 22
30.4 × 30.4
34.9 × 34.9
35 × 35
45 × 45
62.5 × 62.5
Table 7. APEX 20K FineLine BGA Package Sizes
Feature
144-Pin
324-Pin
484-Pin
672-Pin
1,020-Pin
Pitch (mm)
1.00
169
1.00
361
1.00
529
1.00
729
1.00
1,089
2
Area (mm )
Length × Width (mm × mm)
13 × 13
19 × 19
23 × 23
27 × 27
33 × 33
APEXTM 20K devices are the first PLDs designed with the MultiCore
architecture, which combines the strengths of LUT-based and product-
term-based devices with an enhanced memory structure. LUT-based logic
provides optimized performance and efficiency for data-path, register-
intensive, mathematical, or digital signal processing (DSP) designs.
Product-term-based logic is optimized for complex combinatorial paths,
such as complex state machines. LUT- and product-term-based logic
combined with memory functions and a wide variety of MegaCore and
AMPP functions make the APEX 20K architecture uniquely suited for
system-on-a-programmable-chip designs. Applications historically
requiring a combination of LUT-, product-term-, and memory-based
devices can now be integrated into one APEX 20K device.
General
Description
6
Altera Corporation
Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
APEX 20KE devices are a superset of APEX 20K devices and include
additional features such as advanced I/O standard support, CAM,
additional global clocks, and enhanced ClockLock clock circuitry. In
addition, APEX 20KE devices extend the APEX 20K family to over one
million gates. APEX 20KE devices are denoted with an “E” suffix in the
device name (e.g., the EP20K1000E device is an APEX 20KE device).
Table 8 compares the features included in APEX 20K and APEX 20KE
devices.
Altera Corporation
7
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
Table 8. Comparison of APEX 20K & APEX 20KE Features
Feature
APEX 20K Devices
APEX 20KE Devices
MultiCore system integration
Hot-socketing support
Full support
Full support
Full support
Full support
Full support
Full support
SignalTap logic analysis
32/64-Bit, 33-MHz PCI
Full compliance in -1, -2 speed
grades
Full compliance in -1, -2 speed grades
32/64-Bit, 66-MHz PCI
MultiVolt I/O
-
Full compliance in -1 speed grade
2.5-V or 3.3-V V
1.8-V, 2.5-V, or 3.3-V V
CCIO
CCIO
V
selected for device
V
selected block-by-block
CCIO
CCIO
Certain devices are 5.0-V tolerant 5.0-V tolerant with use of external resistor
ClockLock support
Clock delay reduction
2× and 4× clock multiplication
Clock delay reduction
m/(n × v) clock multiplication
Drive ClockLock output off-chip
External clock feedback
ClockShift
LVDS support
Up to four PLLs
ClockShift, clock phase adjustment
Dedicated clock and input pins Six
I/O standard support 2.5-V, 3.3-V, 5.0-V I/O
Eight
1.8-V, 2.5-V, 3.3-V, 5.0-V I/O
2.5-V I/O
3.3-V PCI
Low-voltage complementary
metal-oxide semiconductor
(LVCMOS)
3.3-V PCI and PCI-X
3.3-V Advanced Graphics Port (AGP)
Center tap terminated (CTT)
Low-voltage transistor-to-transistor GTL+
logic (LVTTL)
LVCMOS
LVTTL
True-LVDS and LVPECL data pins up to
840 Mbps (in EP20K300E and larger
devices)
LVDS and LVPECL clock pins (in all
devices)
LVDS and LVPECL data pins up to 156
Mbps (in all devices)
HSTL Class I
PCI-X
SSTL-2 Class I and II
SSTL-3 Class I and II
Memory support
Dual-port RAM
FIFO
RAM
CAM
Dual-port RAM
FIFO
ROM
RAM
ROM
8
Altera Corporation
Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
All APEX 20K devices are reconfigurable and are 100% tested prior to
shipment. As a result, test vectors do not have to be generated for fault
coverage purposes. Instead, the designer can focus on simulation and
design verification. In addition, the designer does not need to manage
inventories of different application-specific integrated circuit (ASIC)
designs; APEX 20K devices can be configured on the board for the specific
functionality required.
APEX 20K devices are configured at system power-up with data stored in
an Altera serial configuration device or provided by a system controller.
Altera offers in-system programmability (ISP)-capable EPC1 and EPC2
configuration devices, which configure APEX 20K devices via a serial
data stream. Moreover, APEX 20K devices contain an optimized interface
that permits microprocessors to configure APEX 20K devices serially or in
parallel, and synchronously or asynchronously. The interface also enables
microprocessors to treat APEX 20K devices as memory and configure the
device by writing to a virtual memory location, making reconfiguration
easy.
1
Contact Altera for information on future configuration devices.
After an APEX 20K device has been configured, it can be reconfigured
in-circuit by resetting the device and loading new data. Real-time changes
can be made during system operation, enabling innovative reconfigurable
computing applications.
APEX 20K devices are supported by the Altera Quartus development
system, a single, integrated package that offers HDL and schematic design
entry, compilation and logic synthesis, full simulation and worst-case
timing analysis, SignalTap logic analysis, and device configuration. The
Quartus software runs on Windows-based PCs, Sun SPARCstations, and
HP 9000 Series 700/800 workstations.
The Quartus software provides NativeLink interfaces to other industry-
standard PC- and UNIX workstation-based EDA tools. For example,
designers can invoke the Quartus software from within third-party
design tools. Further, the Quartus software contains built-in optimized
synthesis libraries; synthesis tools can use these libraries to optimize
designs for APEX 20K devices. For example, the Synopsys Design
Compiler library, supplied with the Quartus development system,
includes DesignWare functions optimized for the APEX 20K architecture.
Altera Corporation
9
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
APEX 20K devices incorporate LUT-based logic, product-term-based
logic, and memory into one device. Signal interconnections within
APEX 20K devices (as well as to and from device pins) are provided by the
FastTrack Interconnect—a series of fast, continuous row and column
channels that run the entire length and width of the device.
Functional
Description
Each I/O pin is fed by an I/O element (IOE) located at the end of each row
and column of the FastTrack Interconnect. Each IOE contains a
bidirectional I/O buffer and a register that can be used as either an input
or output register to feed input, output, or bidirectional signals. When
used with a dedicated clock pin, these registers provide exceptional
performance. IOEs provide a variety of features, such as 3.3-V, 64-bit,
66-MHz PCI compliance; JTAG BST support; slew-rate control; and
tri-state buffers. APEX 20KE devices offer enhanced I/O support,
including support for 1.8-V I/O, 2.5-V I/O, LVCMOS, LVTTL, LVPECL,
3.3-V PCI, PCI-X, LVDS, GTL+, SSTL-2, SSTL-3, HSTL, CTT, and 3.3-V
AGP I/O standards.
The ESB can implement a variety of memory functions, including CAM,
RAM, dual-port RAM, ROM, and FIFO functions. Embedding the
memory directly into the die improves performance and reduces die area
compared to distributed-RAM implementations. Moreover, the
abundance of cascadable ESBs ensures that the APEX 20K device can
implement multiple wide memory blocks for high-density designs. The
ESB’s high speed ensures it can implement small memory blocks without
any speed penalty. The abundance of ESBs ensures that designers can
create as many different-sized memory blocks as the system requires.
Figure 1 shows an overview of the APEX 20K device.
Figure 1. APEX 20K Device Block Diagram
Clock Management Circuitry
FastTrack
Interconnect
IOE
IOE
ClockLock
IOE
LUT
IOE
LUT
LUT
IOE
Four-input LUT
for data path and
DSP functions.
LUT
LUT
IOE
Product Term
Memory
Product Term
Memory
Product Term
Memory
Product Term
Memory
IOEs support
PCI, GTL+,
SSTL-3, LVDS,
and other
Product-term
integration for
high-speed
control logic and
state machines.
standards.
LUT
LUT
LUT
Product Term
Memory
LUT
Product Term
Memory
Product Term
Memory
IOE
IOE
Product Term
Memory
Flexible integration
of embedded
memory, including
CAM, RAM,
IOE
IOE
IOE
IOE
ROM, FIFO, and
other memory
functions.
10
Altera Corporation
Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
APEX 20K devices provide two dedicated clock pins and four dedicated
input pins that drive register control inputs. These signals ensure efficient
distribution of high-speed, low-skew control signals. These signals use
dedicated routing channels to provide short delays and low skews. Four
of the dedicated inputs drive four global signals. These four global signals
can also be driven by internal logic, providing an ideal solution for a clock
divider or internally generated asynchronous clear signals with high
fan-out. The dedicated clock pins featured on the APEX 20K devices can
also feed logic. The devices also feature ClockLock and ClockBoost clock
management circuitry. APEX 20KE devices provide two additional
dedicated clock pins, for a total of four dedicated clock pins.
MegaLAB Structure
APEX 20K devices are constructed from a series of MegaLABTM
structures. Each MegaLAB structure contains 16 logic array blocks
(LABs), one ESB, and a MegaLAB interconnect, which routes signals
within the MegaLAB structure. In EP20K1000E and EP20K1500E devices,
MegaLAB structures contain 24 LABs. Signals are routed between
MegaLAB structures and I/O pins via the FastTrack Interconnect. In
addition, edge LABs can be driven by I/O pins through the local
interconnect. Figure 2 shows the MegaLAB structure.
Figure 2. MegaLAB Structure
MegaLAB Interconnect
LE1
LE2
LE3
LE4
LE5
LE6
LE7
LE8
LE9
LE10
LE1
LE2
LE3
LE4
LE5
LE6
LE7
LE8
LE9
LE10
LE1
LE2
LE3
LE4
LE5
LE6
LE7
To Adjacent
LAB or IOEs
ESB
LE8
LE9
LE10
Local
Interconnect
LABs
Altera Corporation
11
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
Logic Array Block
Each LAB consists of 10 LEs, the LEs’ associated carry and cascade chains,
LAB control signals, and the local interconnect. The local interconnect
transfers signals between LEs in the same or adjacent LABs, IOEs, or ESBs.
The Quartus Compiler places associated logic within an LAB or adjacent
LABs, allowing the use of a fast local interconnect for high performance.
Figure 3 shows the APEX 20K LAB.
APEX 20K devices use an interleaved LAB structure. This structure allows
each LE to drive two local interconnect areas. This feature minimizes use
of the MegaLAB and FastTrack interconnect, providing higher
performance and flexibility. Each LE can drive 29 other LEs through the
fast local interconnect.
Figure 3. LAB Structure
Row
Interconnect
MegaLAB Interconnect
LEs drive local
MegaLAB, row,
and column
interconnects.
To/From
To/From
Adjacent LAB,
ESB, or IOEs
Adjacent LAB,
ESB, or IOEs
Column
Interconnect
Local Interconnect
The 10 LEs in the LAB are driven by
two local interconnect areas. These LEs
can drive two local interconnect areas.
12
Altera Corporation
Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
Each LAB contains dedicated logic for driving control signals to its LEs
and ESBs. The control signals include clock, clock enable, asynchronous
clear, asynchronous preset, asynchronous load, synchronous clear, and
synchronous load signals. A maximum of six control signals can be used
at a time. Although synchronous load and clear signals are generally used
when implementing counters, they can also be used with other functions.
Each LAB can use two clocks and two clock enable signals. Each LAB’s
clock and clock enable signals are linked (e.g., any LE in a particular LAB
using CLK1will also use CLKENA1). LEs with the same clock but different
clock enable signals either use both clock signals in one LAB or are placed
into separate LABs.
If both the rising and falling edges of a clock are used in an LAB, both
LAB-wide clock signals are used.
The LAB-wide control signals can be generated from the LAB local
interconnect, global signals, and dedicated clock pins. The inherent low
skew of the FastTrack Interconnect enables it to be used for clock
distribution. Figure 4 shows the LAB control signal generation circuit.
Figure 4. LAB Control Signal Generation
2 or 4 (1)
4
Dedicated
Clocks
Global
Signals
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
LABCLKENA1
SYNCLOAD
LABCLR1 (2)
or LABCLKENA2
SYNCCLR
or LABCLK2 (3)
LABCLK1
LABCLR2 (2)
Notes:
(1) APEX 20KE devices have four dedicated clocks.
(2) The LABCLR1and LABCLR2signals also control asynchronous load and asynchronous preset for LEs within the
LAB.
(3) The SYNCCLRsignal can be generated by the local interconnect or global signals.
Altera Corporation
13
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
Logic Element
The LE, the smallest unit of logic in the APEX 20K architecture, is compact
and provides efficient logic usage. Each LE contains a four-input LUT,
which is a function generator that can quickly implement any function of
four variables. In addition, each LE contains a programmable register and
carry and cascade chains. Each LE drives the local interconnect, MegaLAB
interconnect, and FastTrack Interconnect routing structures. See Figure 5.
Figure 5. APEX 20K Logic Element
Register Bypass
LAB-wide
Synchronous
Load
LAB-wide
Synchronous
Clear
Packed
Register Select
Carry-In
Cascade-In
Programmable
Register
data1
data2
data3
data4
To FastTrack Interconnect,
MegaLAB Interconnect,
or Local Interconnect
Look-Up
Table
(LUT)
Carry
Chain
Cascade
Chain
Synchronous
Load & Clear
Logic
PRN
D
Q
ENA
CLRN
To FastTrack Interconnect,
MegaLAB Interconnect,
or Local Interconnect
labclr1
Asynchronous
Clear/Preset/
Load Logic
labclr2
Chip-Wide
Reset
Clock &
Clock Enable
Select
labclk1
labclk2
labclkena1
labclkena2
Carry-Out
Cascade-Out
Each LE’s programmable register can be configured for D, T, JK, or SR
operation. The register’s clock and clear control signals can be driven by
global signals, general-purpose I/O pins, or any internal logic. For
combinatorial functions, the register is bypassed and the output of the
LUT drives the outputs of the LE.
14
Altera Corporation
Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
Each LE has two outputs that drive the local, MegaLAB, or FastTrack
Interconnect routing structure. Each output can be driven independently
by the LUT’s or register’s output. For example, the LUT can drive one
output while the register drives the other output. This feature, called
register packing, improves device utilization because the register and the
LUT can be used for unrelated functions. The LE can also drive out
registered and unregistered versions of the LUT output.
The APEX 20K architecture provides two types of dedicated high-speed
data paths that connect adjacent LEs without using local interconnect
paths: carry chains and cascade chains. A carry chain supports high-speed
arithmetic functions such as counters and adders, while a cascade chain
implements wide-input functions such as equality comparators with
minimum delay. Carry and cascade chains connect LEs 1 through 10 in an
LAB and all LABs in the same MegaLAB structure.
Carry Chain
The carry chain provides a very fast carry-forward function between LEs.
The carry-in signal from a lower-order bit drives forward into the higher-
order bit via the carry chain, and feeds into both the LUT and the next
portion of the carry chain. This feature allows the APEX 20K architecture
to implement high-speed counters, adders, and comparators of arbitrary
width. Carry chain logic can be created automatically by the Quartus
Compiler during design processing, or manually by the designer during
design entry. Parameterized functions such as library of parameterized
modules (LPM) and DesignWare functions automatically take advantage
of carry chains for the appropriate functions.
The Quartus Compiler creates carry chains longer than ten LEs by linking
LABs together automatically. For enhanced fitting, a long carry chain
skips alternate LABs in a MegaLAB structure. A carry chain longer than
one LAB skips either from an even-numbered LAB to the next even-
numbered LAB, or from an odd-numbered LAB to the next odd-
numbered LAB. For example, the last LE of the first LAB in the upper-left
MegaLAB structure carries to the first LE of the third LAB in the
MegaLAB structure.
Figure 6 shows how an n-bit full adder can be implemented in n + 1 LEs
with the carry chain. One portion of the LUT generates the sum of two bits
using the input signals and the carry-in signal; the sum is routed to the
output of the LE. The register can be bypassed for simple adders or used
for accumulator functions. Another portion of the LUT and the carry
chain logic generates the carry-out signal, which is routed directly to the
carry-in signal of the next-higher-order bit. The final carry-out signal is
routed to an LE, where it is driven onto the local, MegaLAB, or FastTrack
Interconnect routing structures.
Altera Corporation
15
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
Figure 6. APEX 20K Carry Chain
Carry-In
s1
Register
a1
b1
LUT
Carry Chain
LE1
Register
s2
a2
b2
LUT
Carry Chain
LE2
Register
sn
an
bn
LUT
Carry Chain
LEn
Register
Carry-Out
LUT
Carry Chain
LEn + 1
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Altera Corporation
Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
Cascade Chain
With the cascade chain, the APEX 20K architecture can implement
functions with a very wide fan-in. Adjacent LUTs can compute portions
of a function in parallel; the cascade chain serially connects the
intermediate values. The cascade chain can use a logical ANDor logical OR
(via De Morgan’s inversion) to connect the outputs of adjacent LEs. Each
additional LE provides four more inputs to the effective width of a
function, with a short cascade delay. Cascade chain logic can be created
automatically by the Quartus Compiler during design processing, or
manually by the designer during design entry.
Cascade chains longer than ten LEs are implemented automatically by
linking LABs together. For enhanced fitting, a long cascade chain skips
alternate LABs in a MegaLAB structure. A cascade chain longer than one
LAB skips either from an even-numbered LAB to the next even-numbered
LAB, or from an odd-numbered LAB to the next odd-numbered LAB. For
example, the last LE of the first LAB in the upper-left MegaLAB structure
carries to the first LE of the third LAB in the MegaLAB structure. Figure 7
shows how the cascade function can connect adjacent LEs to form
functions with a wide fan-in.
Figure 7. APEX 20K Cascade Chain
AND Cascade Chain
OR Cascade Chain
d[3..0]
d[7..4]
d[3..0]
LUT
LUT
LUT
LUT
LE1
LE2
LE1
LE2
d[7..4]
d[(4n – 1)..(4n – 4)]
d[(4n – 1)..(4n – 4)]
LUT
LUT
LEn
LEn
Altera Corporation
17
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
LE Operating Modes
The APEX 20K LE can operate in one of the following three modes:
ꢀ
Normal mode
Arithmetic mode
Counter mode
ꢀ
ꢀ
Each mode uses LE resources differently. In each mode, seven available
inputs to the LE—the four data inputs from the LAB local interconnect,
the feedback from the programmable register, and the carry-in and
cascade-in from the previous LE—are directed to different destinations to
implement the desired logic function. LAB-wide signals provide clock,
asynchronous clear, asynchronous preset, asynchronous load,
synchronous clear, synchronous load, and clock enable control for the
register. These LAB-wide signals are available in all LE modes.
The Quartus software, in conjunction with parameterized functions such
as LPM and DesignWare functions, automatically chooses the
appropriate mode for common functions such as counters, adders, and
multipliers. If required, the designer can also create special-purpose
functions that specify which LE operating mode to use for optimal
performance. Figure 8 shows the LE operating modes.
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Altera Corporation
Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
Figure 8. APEX 20K LE Operating Modes
LAB-Wide
Clock Enable (2)
Normal Mode (1)
Carry-In (3)
Cascade-In
LE-Out
LE-Out
data1
data2
4-Input
PRN
D
Q
LUT
data3
ENA
CLRN
data4
Cascade-Out
LAB-Wide
Clock Enable (2)
Arithmetic Mode
Carry-In
Cascade-In
LE-Out
LE-Out
PRN
data1
data2
D
Q
3-Input
LUT
ENA
CLRN
3-Input
LUT
Cascade-Out
Carry-Out
Counter Mode
LAB-Wide
Synchronous
Clear (6)
LAB-Wide
Synchronous
Load (6)
LAB-Wide
Clock Enable (2)
Cascade-In
Carry-In
(4)
LE-Out
data1 (5)
data2 (5)
PRN
3-Input
LUT
D
Q
LE-Out
data3 (data)
ENA
CLRN
3-Input
LUT
Carry-Out Cascade-Out
Notes:
(1) LEs in normal mode support register packing.
(2) There are two LAB-wide clock enables per LAB.
(3) When using the carry-in in normal mode, the packed register feature is unavailable.
(4) A register feedback multiplexer is available on LE1 of each LAB.
(5) The DATA1and DATA2input signals can supply counter enable, up or down control, or register feedback signals for
LEs other than the second LE in an LAB.
(6) The LAB-wide synchronous clear and LAB wide synchronous load affect all registers in an LAB.
Altera Corporation
19
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
Normal Mode
The normal mode is suitable for general logic applications, combinatorial
functions, or wide decoding functions that can take advantage of a
cascade chain. In normal mode, four data inputs from the LAB local
interconnect and the carry-in are inputs to a four-input LUT. The Quartus
Compiler automatically selects the carry-in or the DATA3signal as one of
the inputs to the LUT. The LUT output can be combined with the
cascade-in signal to form a cascade chain through the cascade-out signal.
LEs in normal mode support packed registers.
Arithmetic Mode
The arithmetic mode is ideal for implementing adders, accumulators, and
comparators. An LE in arithmetic mode uses two 3-input LUTs. One LUT
computes a three-input function; the other generates a carry output. As
shown in Figure 8, the first LUT uses the carry-in signal and two data
inputs from the LAB local interconnect to generate a combinatorial or
registered output. For example, when implementing an adder, this output
is the sum of three signals: DATA1, DATA2, and carry-in. The second LUT
uses the same three signals to generate a carry-out signal, thereby creating
a carry chain. The arithmetic mode also supports simultaneous use of the
cascade chain. LEs in arithmetic mode can drive out registered and
unregistered versions of the LUT output.
The Quartus software implements parameterized functions that use the
arithmetic mode automatically where appropriate; the designer does not
need to specify how the carry chain will be used.
Counter Mode
The counter mode offers clock enable, counter enable, synchronous
up/down control, synchronous clear, and synchronous load options. The
counter enable and synchronous up/down control signals are generated
from the data inputs of the LAB local interconnect. The synchronous clear
and synchronous load options are LAB-wide signals that affect all
registers in the LAB. Consequently, if any of the LEs in an LAB use the
counter mode, other LEs in that LAB must be used as part of the same
counter or be used for a combinatorial function. The Quartus software
automatically places any registers that are not used by the counter into
other LABs.
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Altera Corporation
Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
The counter mode uses two three-input LUTs: one generates the counter
data, and the other generates the fast carry bit. A 2-to-1 multiplexer
provides synchronous loading, and another ANDgate provides
synchronous clearing. If the cascade function is used by an LE in counter
mode, the synchronous clear or load overrides any signal carried on the
cascade chain. The synchronous clear overrides the synchronous load.
LEs in arithmetic mode can drive out registered and unregistered versions
of the LUT output.
Clear & Preset Logic Control
Logic for the register’s clear and preset signals is controlled by LAB-wide
signals. The LE directly supports an asynchronous clear function. The
Quartus Compiler can use a NOT-gate push-back technique to emulate an
asynchronous preset. Moreover, the Quartus Compiler can use a
programmable NOT-gate push-back technique to emulate simultaneous
preset and clear or asynchronous load. However, this technique uses three
additional LEs per register. All emulation is performed automatically
when the design is compiled. Registers that emulate simultaneous preset
and load will enter an unknown state upon power-up or when the chip-
wide reset is asserted.
In addition to the two clear and preset modes, APEX 20K devices provide
a chip-wide reset pin (DEV_CLRn) that resets all registers in the device. Use
of this pin is controlled through an option in the Quartus software that is
set before compilation. The chip-wide reset overrides all other control
signals. Registers using an asynchronous preset are preset when the
chip-wide reset is asserted; this effect results from the inversion technique
used to implement the asynchronous preset.
FastTrack Interconnect
In the APEX 20K architecture, connections between LEs, ESBs, and I/O
pins are provided by the FastTrack Interconnect. The FastTrack
Interconnect is a series of continuous horizontal and vertical routing
channels that traverse the device. This global routing structure provides
predictable performance, even in complex designs. In contrast, the
segmented routing in FPGAs requires switch matrices to connect a
variable number of routing paths, increasing the delays between logic
resources and reducing performance.
The FastTrack Interconnect consists of row and column interconnect
channels that span the entire device. The row interconnect routes signals
throughout a row of MegaLAB structures; the column interconnect routes
signals throughout a column of MegaLAB structures. When using the row
and column interconnect, an LE, IOE, or ESB can drive any other LE, IOE,
or ESB in a device. See Figure 9.
Altera Corporation
21
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
Figure 9. APEX 20K Interconnect Structure
Row
Interconnect
I/O
I/O
I/O
I/O
MegaLAB
I/O
I/O
MegaLAB
MegaLAB
MegaLAB
MegaLAB
MegaLAB
MegaLAB
I/O
I/O
MegaLAB
Column
Interconnect
Column
Interconnect
MegaLAB
I/O
MegaLAB
MegaLAB
MegaLAB
I/O
I/O
I/O
I/O
I/O
A row line can be driven directly by LEs, IOEs, or ESBs in that row.
Further, a column line can drive a row line, allowing an LE, IOE, or ESB
to drive elements in a different row via the column and row interconnect.
The row interconnect drives the MegaLAB interconnect to drive LEs,
IOEs, or ESBs in a particular MegaLAB structure.
A column line can be directly driven by LEs, IOEs, or ESBs in that column.
A column line on a device’s left or right edge can also be driven by row
IOEs. The column line is used to route signals from one row to another. A
column line can drive a row line; it can also drive the MegaLAB
interconnect directly, allowing faster connections between rows.
Figure 10 shows how the FastTrack Interconnect uses the local
interconnect to drive LEs within MegaLAB structures.
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Altera Corporation
Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
Figure 10. FastTrack Connection to Local Interconnect
I/O
Row
L
A
B
L
A
B
L
A
B
E
S
B
E
S
B
L
A
B
L
A
B
L
A
B
I/O
MegaLAB
MegaLAB
Row & Column
Column
Interconnect Drives
MegaLAB Interconnect
Row
MegaLAB
Interconnect
MegaLAB
Interconnect Drives
Local Interconnect
Column
L
A
B
L
A
B
L
A
B
E
S
B
Altera Corporation
23
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
Figure 11 shows the intersection of a row and column interconnect, and
how these forms of interconnects and LEs drive each other.
Figure 11. Driving the FastTrack Interconnect
Row Interconnect
MegaLAB Interconnect
Column
Interconnect
LE
Local
Interconnect
APEX 20KE devices include an enhanced interconnect structure for faster
routing of input signals with high fan-out. Column I/O pins can drive the
FastRow interconnect, which routes signals directly into the local
interconnect without having to drive through the MegaLAB interconnect.
FastRow lines traverse two MegaLAB structures. Also, these pins can
drive the local interconnect directly for fast setup times. On EP20K300E
and larger devices, the FastRow interconnect drives the two MegaLABs in
the top left corner and the two MegaLABs in the bottom right corner. On
EP20K200E and smaller devices, FastRow interconnect drives the two
MegaLABs on the top and the two MegaLABs on the bottom of the device.
On all devices, the FastRow interconnect drives all local interconnect in
the appropriate MegaLABs except the interconnect areas on the far left
and far right of the MegaLAB. Pins using the FastRow interconnect
achieve a faster set-up time, as the signal does not need to use a MegaLab
interconnect line to reach the destination LE. Figure 12 shows the
FastRow interconnect.
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Altera Corporation
Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
Figure 12. APEX 20KE FastRow Interconnect
Select Vertical I/O Pins
Drive Local Interconnect
and FastRow
FastRow Interconnect
Drives Local Interconnect
in Two MegaLAB Structures
IOE
IOE
IOE
IOE
FastRow
Interconnect
Interconnect
Local
Interconnect
LEs
MegaLAB
MegaLAB
LABs
Table 9 summarizes how various elements of the APEX 20K architecture
drive each other.
Altera Corporation
25
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
Table 9. APEX 20K Routing Scheme
Source
Destination
Row Column
I/O Pin I/O Pin
LE
ESB
Local
Interconnect Interconnect FastTrack
Interconnect Interconnect
MegaLAB
Row
Column
FastTrack Interconnect
FastRow
Row I/O Pin
v
v
v
v
v
Column I/O
Pin
v(1)
v(1)
LE
v
v
v
v
v
v
v
v
ESB
Local
v
v
v
v
Interconnect
MegaLAB
v
Interconnect
Row
FastTrack
Interconnect
v
v
v
Column
v
FastTrack
Interconnect
FastRow
v(1)
Interconnect
Note:
(1) This connection is supported in APEX 20KE devices only.
Product-Term Logic
The product-term portion of the MultiCore architecture is implemented
with the ESB. The ESB can be configured to act as a block of macrocells on
an ESB-by-ESB basis. Each ESB is fed by 32 inputs from the adjacent local
interconnect; therefore, it can be driven by the MegaLAB interconnect or
the adjacent LAB. Also, nine ESB macrocells feed back into the ESB
through the local interconnect for higher performance. Dedicated clock
pins, global signals, and additional inputs from the local interconnect
drive the ESB control signals.
In product-term mode, each ESB contains 16 macrocells. Each macrocell
consists of two product terms and a programmable register. Figure 13
shows the ESB in product-term mode.
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Altera Corporation
Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
Figure 13. Product-Term Logic in ESB
Dedicated Clocks
Global Signals
MegaLAB Interconnect
4
2 or 4 (1)
65
9
32
Macrocell
Inputs (1-16)
To Row
and Column
Interconnect
From
Adjacent
LAB
2
2
2
16
CLK[1..0]
ENA[1..0]
CLRN[1..0]
Local
Interconnect
Note:
(1) APEX 20KE devices have four dedicated clocks.
Macrocells
APEX 20K macrocells can be configured individually for either sequential
or combinatorial logic operation. The macrocell consists of three
functional blocks: the logic array, the product-term select matrix, and the
programmable register.
Combinatorial logic is implemented in the product terms. The product-
term select matrix allocates these product terms for use as either primary
logic inputs (to the ORand XORgates) to implement combinatorial
functions, or as parallel expanders to be used to increase the logic
available to another macrocell. One product term can be inverted; the
Quartus software uses this feature to perform DeMorgan’s inversion for
more efficient implementation of wide ORfunctions. The Quartus
Compiler can use a NOT-gate push-back technique to emulate an
asynchronous preset. Figure 14 shows the APEX 20K macrocell.
Altera Corporation
27
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
Figure 14. APEX 20K Macrocell
ESB-Wide ESB-Wide
Clears Clock Enables
ESB-Wide
Clocks
2
2
2
Parallel Logic
Expanders
(From Other
Macrocells)
Programmable
Register
ESB
Output
Product-
Term
D
Q
Select
Matrix
ENA
CLRN
Clock/
Enable
Select
32 Signals
from Local
Interconnect
Clear
Select
For registered functions, each macrocell register can be programmed
individually to implement D, T, JK, or SR operation with programmable
clock control. The register can be bypassed for combinatorial operation.
During design entry, the designer specifies the desired register type; the
Quartus software then selects the most efficient register operation for each
registered function to optimize resource utilization. The Quartus software
or other synthesis tools can also select the most efficient register operation
automatically when synthesizing HDL designs.
Each programmable register can be clocked by one of two ESB-wide
clocks. The ESB-wide clocks can be generated from device dedicated clock
pins, global signals, or local interconnect. Each clock also has an
associated clock enable, generated from the local interconnect. The clock
and clock enable signals are related for a particular ESB; any macrocell
using a clock also uses the associated clock enable.
If both the rising and falling edges of a clock are used in an ESB, both
ESB-wide clock signals are used.
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Altera Corporation
Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
The programmable register also supports an asynchronous clear function.
Within the ESB, two asynchronous clears are generated from global
signals and the local interconnect. Each macrocell can either choose
between the two asynchronous clear signals or choose to not be cleared.
Either of the two clear signals can be inverted within the ESB. Figure 15
shows the ESB control logic when implementing product-terms.
Figure 15. ESB Product-Term Mode Control Logic
2 or 4 (1)
Dedicated
Clocks
4
Global
Signals
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
CLK1
CLR2
CLKENA1
CLR1
CLK2
CLKENA2
Note:
(1) APEX 20KE devices have four dedicated clocks.
Parallel Expanders
Parallel expanders are unused product terms that can be allocated to a
neighboring macrocell to implement fast, complex logic functions.
Parallel expanders allow up to 32 product terms to feed the macrocell OR
logic directly, with two product terms provided by the macrocell and 30
parallel expanders provided by the neighboring macrocells in the ESB.
The Quartus Compiler can allocate up to 15 sets of up to two parallel
expanders per set to the macrocells automatically. Each set of two parallel
expanders incurs a small, incremental timing delay. Figure 16 shows the
APEX 20K parallel expanders.
Altera Corporation
29
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
Figure 16. APEX 20K Parallel Expanders
From
Previous
Macrocell
Product-
Term
Select
Matrix
Macrocell
Product-
Term Logic
Parallel Expander
Switch
Product-
Term
Select
Matrix
Macrocell
Product-
Term Logic
Parallel Expander
Switch
32 Signals from
Local Interconnect
To Next
Macrocell
The ESB can implement various types of memory blocks, including
dual-port RAM, ROM, FIFO, and CAM blocks. The ESB includes input
and output registers; the input registers synchronize writes, and the
output registers can pipeline designs to improve system performance.
The ESB offers a dual-port mode, which supports simultaneous reads and
writes at two different clock frequencies. Figure 17 shows the ESB block
diagram.
Embedded
System Block
Figure 17. ESB Block Diagram
wraddress[]
data[]
rdaddress[]
q[]
wren
rden
inclock
inclocken
inaclr
outclock
outclocken
outaclr
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Altera Corporation
Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
ESBs can implement synchronous RAM, which is easier to use than
asynchronous RAM. A circuit using asynchronous RAM must generate
the RAM write enable (WE) signal, while ensuring that its data and address
signals meet setup and hold time specifications relative to the WEsignal.
In contrast, the ESB’s synchronous RAM generates its own WEsignal and
is self-timed with respect to the global clock. Circuits using the ESB’s self-
timed RAM must only meet the setup and hold time specifications of the
global clock.
ESB inputs are driven by the adjacent local interconnect, which in turn can
be driven by the MegaLAB or FastTrack Interconnect. Because the ESB can
be driven by the local interconnect, an adjacent LE can drive it directly for
fast memory access. ESB outputs drive the MegaLAB and FastTrack
Interconnect. In addition, ten ESB outputs, nine of which are unique
output lines, drive the local interconnect for fast connection to adjacent
LEs or for fast feedback product-term logic.
When implementing memory, each ESB can be configured in any of the
following sizes: 128 × 16, 256 × 8, 512 × 4, 1,024 × 2, or 2,048 × 1. By
combining multiple ESBs, the Quartus software implements larger
memory blocks automatically. For example, two 128 × 16 RAM blocks can
be combined to form a 128 × 32 RAM block, and two 512 × 4 RAM blocks
can be combined to form a 512 × 8 RAM block. Memory performance does
not degrade for memory blocks up to 2,048 words deep. Each ESB can
implement a 2,048-word-deep memory; the ESBs are used in parallel,
eliminating the need for any external control logic and its associated
delays.
To create a high-speed memory block that is more than 2,048 words deep,
ESBs drive tri-state lines. Each tri-state line connects all ESBs in a column
of MegaLAB structures, and drives the MegaLAB interconnect and row
and column FastTrack Interconnect throughout the column. Each ESB
incorporates a programmable decoder to activate the tri-state driver
appropriately. For instance, to implement 8,192-word-deep memory, four
ESBs are used. Eleven address lines drive the ESB memory, and two more
drive the tri-state decoder. Depending on which 2,048-word memory
page is selected, the appropriate ESB driver is turned on, driving the
output to the tri-state line. The Quartus software automatically combines
ESBs with tri-state lines to form deeper memory blocks. The internal
tri-state control logic is designed to avoid internal contention and floating
lines. See Figure 18.
Altera Corporation
31
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
Figure 18. Deep Memory Block Implemented with Multiple ESBs
Address Decoder
ESB
ESB
ESB
to System Logic
The ESB implements two forms of dual-port memory: read/write clock
mode and input/output clock mode. The ESB can also be used for
bidirectional, dual-port memory applications in which two ports read or
write simultaneously. To implement this type of dual-port memory, two
ESBs are used to support two simultaneous reads or writes.
The ESB can also use Altera megafunctions to implement dual-port RAM
applications where both ports can read or write, as shown in Figure 19.
Figure 19. APEX 20K ESB Implementing Dual-Port RAM
Port A
address_a[]
data_a[]
Port B
address_b[]
data_b[]
we_a
we_b
clkena_a
clkena_b
Clock A
Clock B
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Altera Corporation
Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
Read/Write Clock Mode
The read/write clock mode contains two clocks. One clock controls all
registers associated with writing: data input, WE, and write address. The
other clock controls all registers associated with reading: read enable
(RE), read address, and data output. The ESB also supports clock enable
and asynchronous clear signals; these signals also control the read and
write registers independently. Read/write clock mode is commonly used
for applications where reads and writes occur at different system
frequencies. Figure 20 shows the ESB in read/write clock mode.
Figure 20. ESB in Read/Write Clock Mode
Note (1)
Dedicated Inputs &
Global Signals
Dedicated Clocks
RAM/ROM
2 or 4
(2)
4
128 × 16
256 × 8
512 × 4
1,024 × 2
2,048 × 1
data[ ]
Data In
D
Q
to MegaLAB,
FastTrack &
Local
ENA
Data Out
D
Q
ENA
Interconnect
rdaddress[ ]
Read Address
Write Address
D
Q
ENA
wraddress[ ]
rden
D
Q
ENA
Read Enable
Write Enable
D
Q
wren
ENA
outclken
inclken
inclock
D
Q
Write
Pulse
Generator
ENA
outclock
Notes:
(1) All registers can be cleared asynchronously by ESB local interconnect signals, global signals, or the chip-wide reset.
(2) APEX 20KE devices have four dedicated clocks.
Altera Corporation
33
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
Input/Output Clock Mode
The input/output clock mode contains two clocks. One clock controls all
registers for inputs into the ESB: data input, WE, RE, read address, and
write address. The other clock controls the ESB data output registers. The
ESB also supports clock enable and asynchronous clear signals; these
signals also control the reading and writing of registers independently.
Input/output clock mode is commonly used for applications where the
reads and writes occur at the same system frequency, but require different
clock enable signals for the input and output registers. Figure 21 shows
the ESB in input/output clock mode.
Figure 21. ESB in Input/Output Clock Mode
Notes (1), (2)
Dedicated Inputs &
Global Signals
Dedicated Clocks
RAM/ROM
2 or 4
(2)
4
128 × 16
256 × 8
512 × 4
1,024 × 2
2,048 × 1
data[ ]
Data In
D
Q
to MegaLAB,
FastTrack &
Local
ENA
Data Out
D
Q
ENA
Interconnect
rdaddress[ ]
Read Address
Write Address
D
Q
ENA
wraddress[ ]
rden
D
Q
ENA
Read Enable
Write Enable
D
Q
wren
ENA
outclken
inclken
inclock
D
Q
Write
Pulse
Generator
ENA
outclock
Notes:
(1) All registers can be cleared asynchronously by ESB local interconnect signals, global signals, or the chip-wide reset.
(2) APEX 20KE devices have four dedicated clocks.
Single-Port Mode
The APEX 20K ESB also supports a single-port mode, which is used when
simultaneous reads and writes are not required. See Figure 22.
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Altera Corporation
Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
Figure 22. ESB in Single-Port Mode
Note (1)
Dedicated Inputs &
Global Signals
Dedicated Clocks
RAM/ROM
2 or 4
(2)
4
128 × 16
256 × 8
512 × 4
1,024 × 2
2,048 × 1
data[ ]
Data In
D
Q
to MegaLAB,
FastTrack &
Local
ENA
Data Out
D
Q
Interconnect
ENA
address[ ]
Address
D
Q
ENA
wren
outclken
Write Enable
inclken
inclock
D
Q
Write
Pulse
Generator
ENA
outclock
Notes:
(1) All registers can be asynchronously cleared by ESB local interconnect signals, global signals, or the chip-wide reset.
(2) APEX 20KE devices have four dedicated clocks.
Content-Addressable Memory
In APEX 20KE devices, the ESB can implement CAM. CAM can be
thought of as the inverse of RAM. When read, RAM outputs the data for
a given address. Conversely, CAM outputs an address for a given data
word. For example, if the data FA12is stored in address 14, the CAM
outputs 14when FA12is driven into it.
CAM is used for high-speed search operations. When searching for data
within a RAM block, the search is performed serially. Thus, finding a
particular data word can take many cycles. CAM searches all addresses in
parallel and outputs the address storing a particular word. When a match
is found, a match flag is set high. Figure 23 shows the CAM block
diagram.
Altera Corporation
35
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
Figure 23. APEX 20KE CAM Block Diagram
wraddress[]
data[]
data_address[]
match
outclock
wren
inclock
inclocken
inaclr
outclocken
outaclr
CAM can be used in any application requiring high-speed searches, such
as networking, communications, data compression, and cache
management.
The APEX 20KE on-chip CAM provides faster system performance than
traditional discrete CAM. Integrating CAM and logic into the APEX 20KE
device eliminates off-chip and on-chip delays, improving system
performance.
When in CAM mode, the ESB implements 32-word, 32-bit CAM. Wider or
deeper CAM can be implemented by combining multiple CAMs with
some ancillary logic implemented in LEs. The Quartus software combines
ESBs and LEs automatically to create larger CAMs.
CAM supports writing “don’t care” bits into words of the memory. The
“don’t-care” bit can be used as a mask for CAM comparisons; any bit set
to “don’t-care” has no effect on matches.
The output of the CAM can be encoded or unencoded. When encoded, the
ESB outputs an encoded address of the data’s location. For instance, if the
data is located in address 12, the ESB output is 12. When unencoded, the
ESB uses its 16 outputs to show the location of the data over two clock
cycles. In this case, if the data is located in address 12, the 12th output line
goes high. When using unencoded outputs, two clock cycles are required
to read the output because a 16-bit output bus is used to show the status
of 32 words.
The encoded output is better suited for designs that ensure duplicate data
is not written into the CAM. If duplicate data is written into two locations,
the CAM’s output will be incorrect. If the CAM may contain duplicate
data, the unencoded output is a better solution; CAM with unencoded
outputs can distinguish multiple data locations.
CAM can be pre-loaded with data during configuration, or it can be
written during system operation. In most cases, two clock cycles are
required to write each word into CAM. When “don’t-care” bits are used,
a third clock cycle is required.
36
Altera Corporation
Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
For more information on APEX 20KE devices and CAM, see Application
Note 119 (Implementing High-Speed Search Applications with APEX CAM).
f
Driving Signals to the ESB
ESBs provide flexible options for driving control signals. Different clocks
can be used for the ESB inputs and outputs. Registers can be inserted
independently on the data input, data output, read address, write
address, WE, and REsignals. The global signals and the local interconnect
can drive the WEand REsignals. The global signals, dedicated clock pins,
and local interconnect can drive the ESB clock signals. Because the LEs
drive the local interconnect, the LEs can control the WEand REsignals and
the ESB clock, clock enable, and asynchronous clear signals. Figure 24
shows the ESB control signal generation logic.
Figure 24. ESB Control Signal Generation
2 or 4 (1)
Dedicated
Clocks
4
Global
Signals
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
INCLKENA
OUTCLKENA
Local
Interconnect
RDEN
WREN INCLOCK
OUTCLOCK
INCLR OUTCLR
Note:
(1) APEX 20KE devices have four dedicated clocks.
An ESB is fed by the local interconnect, which is driven by adjacent LEs
(for high-speed connection to the ESB) or the MegaLAB interconnect. The
ESB can drive the local, MegaLAB, or FastTrack Interconnect routing
structure to drive LEs and IOEs in the same MegaLAB structure or
anywhere in the device.
Altera Corporation
37
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
Implementing Logic in ROM
In addition to implementing logic with product terms, the ESB can
implement logic functions when it is programmed with a read-only
pattern during configuration, creating a large LUT. With LUTs,
combinatorial functions are implemented by looking up the results, rather
than by computing them. This implementation of combinatorial functions
can be faster than using algorithms implemented in general logic, a
performance advantage that is further enhanced by the fast access times
of ESBs. The large capacity of ESBs enables designers to implement
complex functions in one logic level without the routing delays associated
with linked LEs or distributed RAM blocks. Parameterized functions such
as LPM functions can take advantage of the ESB automatically. Further,
the Quartus software can implement portions of a design with ESBs
where appropriate.
Programmable Speed/Power Control
APEX 20K ESBs offer a high-speed mode that supports very fast operation
on an ESB-by-ESB basis. When high speed is not required, this feature can
be turned off to reduce the ESB’s power dissipation by up to 50%. ESBs
that run at low power incur a nominal timing delay adder. This
Turbo BitTM option is available for ESBs that implement product-term
logic or memory functions. An ESB that is not used will be powered down
so that it does not consume DC current.
Designers can program each ESB in the APEX 20K device for either
high-speed or low-power operation. As a result, speed-critical paths in the
design can run at high speed, while the remaining paths operate at
reduced power.
38
Altera Corporation
Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
The APEX 20K IOE contains a bidirectional I/O buffer and a register that
can be used either as an input register for external data requiring fast setup
times, or as an output register for data requiring fast clock-to-output
performance. IOEs can be used as input, output, or bidirectional pins. For
fast bidirectional I/O timing, LE registers using local routing can improve
setup times and OE timing. The Quartus Compiler uses the programmable
inversion option to invert signals from the row and column interconnect
automatically where appropriate. Because the APEX 20K IOE offers one
output enable per pin, the Quartus Compiler can emulate open-drain
operation efficiently.
I/O Structure
The APEX 20K IOE includes programmable delays that can be activated to
ensure zero hold times, minimum clock-to-output times, input IOE
register-to-core register transfers, or core-to-output IOE register transfers.
A path in which a pin directly drives a register may require the delay to
ensure zero hold time, whereas a path in which a pin drives a register
through combinatorial logic may not require the delay.
Table 10 describes the APEX 20K programmable delays and their logic
options in the Quartus software.
Table 10. APEX 20K Programmable Delay Chains
Programmable Delays
Quartus Logic Option
Input pin to core delay
Decrease input delay to internal cells
Decrease input delay to input register
Decrease input delay to output register
Increase delay to output pin
Input pin to input register delay
Core to output register delay
Output register t delay
CO
The Quartus Compiler can program these delays automatically to
minimize setup time while providing a zero hold time. Figure 25 shows
how fast bidirectional I/Os are implemented in APEX 20K devices.
The register in the APEX 20K IOE can be programmed to power-up high
or low after configuration is complete. If it is programmed to power-up
low, an asynchronous clear can control the register. If it is programmed to
power-up high, the register cannot be asynchronously cleared or preset.
This feature is useful for cases where the APEX 20K device controls an
active-low input or another device; it prevents inadvertent activation of
the input upon power-up.
Altera Corporation
39
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
Figure 25. APEX 20K Bidirectional I/O Registers Note (1)
Row, Column,
or Local Interconnect Clock Inputs
2 Dedicated
Peripheral Control
Bus
4 Dedicated
Inputs
OE Register
D
Q
ENA
CLRN
VCC
Chip-Wide Reset
VCC
Chip-Wide
Output Enable
OE[7..0]
VCCIO
Optional
PCI Clamp
Input Pin to
Core Delay
12
2
VCC
Output Register
Delay
Output Register
Core to Output
Register Delay
t
CO
Q
D
Open-Drain
Output
Input Pin to Input
Register Delay
ENA
CLRN
CLK[1..0]
Slew-Rate
Control
CLK[3..2]
ENA[5..0]
VCC
VCC
CLRn[1..0]
Chip-Wide
Reset
Input Register
D
Q
VCC
ENA
CLRN
VCC
Chip-Wide
Reset
Note:
(1) The output enable and input registers are LE registers in the LAB adjacent to the bidirectional pin.
40 Altera Corporation
Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
APEX 20KE devices include an enhanced IOE, which drives the FastRow
interconnect. The FastRow interconnect connects a column I/O pin
directly to the LAB local interconnect within two MegaLAB structures.
This feature provides fast setup times for pins that drive high fan-outs
with complex logic, such as PCI designs. For fast bidirectional I/O timing,
LE registers using local routing can improve setup times and OE timing.
The APEX 20KE IOE also includes direct support for open-drain
operation, giving faster clock-to-output for open-drain signals. Some
programmable delays in the APEX 20KE IOE offer multiple levels of
delay to fine-tune setup and hold time requirements. The Quartus
Compiler can set these delays automatically to minimize setup time while
providing a zero hold time.
Table 11 describes the APEX 20KE programmable delays and their logic
options in the Quartus software.
Table 11. APEX 20KE Programmable Delay Chains
Programmable Delays
Quartus Logic Option
Input Pin to Core Delay
Decrease input delay to internal cells
Decrease input delay to input registers
Decrease input delay to output register
Increase delay to output pin
Input Pin to Input Register Delay
Core to Output Register Delay
Output Register t Delay
CO
Clock Enable Delay
Increase clock enable delay
The register in the APEX 20KE IOE can be programmed to power-up high
or low after configuration is complete. If it is programmed to power-up
low, an asynchronous clear can control the register. If it is programmed to
power-up high, an asynchronous preset can control the register. Figure 26
shows how fast bidirectional I/O pins are implemented in APEX 20KE
devices. This feature is useful for cases where the APEX 20KE device
controls an active-low input or another device; it prevents inadvertent
activation of the input upon power-up.
Altera Corporation
41
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
Figure 26. APEX 20KE Bidirectional I/O Registers
Notes (1), (2)
Row, Column, FastRow,
4 Dedicated
or Local Interconnect Clock Inputs
Peripheral Control
Bus
4 Dedicated
Inputs
OE Register
D
Q
ENA
CLRN
VCC
Chip-Wide Reset
VCC
Chip-Wide
Output Enable
OE[7..0]
VCCIO
Input Pin to
Optional
Core Delay (1)
PCI Clamp
Input Pin to
Core Delay (1)
12
4
VCC
Output Register
Delay
Output Register
Core to Output
Register Delay
t
CO
Q
D
Open-Drain
Output
Input Pin to Input
Register Delay
ENA
CLRN/
PRN
CLK[1..0]
Slew-Rate
Control
CLK[5..2]
ENA[5..0]
VCC
Clock Enable
Delay (1)
VCC
CLRn[1..0]
Input Pin to
Core Delay (1)
Chip-Wide
Reset
Input Register
D
Q
VCC
ENA
CLRN
VCC
Chip-Wide
Reset
42
Altera Corporation
Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
Notes:
(1) This programmable delay has four settings: off and three levels of delay.
(2) The output enable and input registers are LE registers in the LAB adjacent to the bidirectional pin.
Each IOE drives a row, column, MegaLAB, or local interconnect when
used as an input or bidirectional pin. A row IOE can drive a local,
MegaLAB, row, and column interconnect; a column IOE can drive the
column interconnect. Figure 27shows how a row IOE connects to the
interconnect.
Figure 27. Row IOE Connection to the Interconnect
Row Interconnect
MegaLAB Interconnect
Any LE can drive a
pin through the row,
column, and MegaLAB
interconnect.
Each IOE can drive local,
IOE
IOE
MegaLAB, row, and column
interconnect. Each IOE data
and OE signal is driven by
the local interconnect.
LAB
An LE can drive a pin through the
local interconnect for faster
clock-to-output times.
Altera Corporation
43
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
Figure 28 shows how a column IOE connects to the interconnect.
Figure 28. Column IOE Connection to the Interconnect
Each IOE can drive column interconnect. In APEX 20KE devices,
IOEs can also drive FastRow and column interconnect. Each IOE data
and OE signal is driven by local interconnect.
IOE
IOE
An LE or ESB can drive a
pin through a local
interconnect for faster
clock-to-output times.
LAB
Any LE or ESB can drive
a column pin through a
row, column, and MegaLAB
interconnect.
Column Interconnect
MegaLAB Interconnect
Row Interconnect
Dedicated Fast I/Os
APEX 20KE devices incorporate an enhancement to support bidirectional
pins with high internal fanout such as PCI control signals. These pins are
called Dedicated Fast I/Os (FAST1, FAST2, FAST3, and FAST4) and replace
dedicated inputs. These pins can be used for fast clock, clear, or high
fanout logic signal distribution. They also can drive out. The Dedicated
Fast I/O pin data output and tri-state control are driven by local
interconnect from the adjacent MegaLAB for high speed.
44
Altera Corporation
Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
Advanced I/O Standard Support
APEX 20KE IOEs support the following I/O standards: LVTTL,
LVCMOS, 1.8-V I/O, 2.5-V I/O, 3.3-V PCI, PCI-X, 3.3-V AGP, LVDS,
LVPECL, GTL+, CTT, HSTL Class I, SSTL-3 Class I and II, and SSTL-2
Class I and II.
For more information on I/O standards supported by APEX 20KE
devices, see Application Note 117 (Using Selectable I/O Standards in Altera
Devices).
f
The APEX 20KE device contains eight I/O banks. In QFP packages, the
banks are linked to form four I/O banks. The I/O banks directly support
all standards except LVDS and LVPECL. All I/O banks can support LVDS
and LVPECL with the addition of external resistors. In addition, one block
within a bank contains circuitry to support high-speed True-LVDS and
LVPECL inputs, and another block within a bank supports high-speed
True-LVDS and LVPECL outputs. The LVDS blocks support all of the I/O
standards. Each I/O bank has its own VCCIOpins. A single device can
support 1.8-V, 2.5-V, and 3.3-V interfaces; each bank can support a
different standard independently. Each bank can also use a separate V
REF
level so that each bank can support any of the terminated standards (such
as SSTL-3) independently. Within a bank, any one of the terminated
standards can be supported. EP20K300E and larger APEX 20KE devices
support the LVDS interface for data pins (smaller devices support LVDS
clock pins, but not data pins). All EP20K300E and larger devices support
the LVDS interface for data pins up to 155 Mbit per channel; EP20K400E
devices and larger with an X-suffix on the ordering code add a
serializer/deserializer circuit and PLL for support up to 840 Mbit per
channel.
Each bank can support multiple standards with the same VCCIOfor
output pins. Each bank can support one voltage-referenced I/O standard,
but it can support multiple I/O standards with the same VCCIOvoltage
level. For example, when VCCIO is 3.3 V, a bank can support LVTTL,
LVCMOS, 3.3-V PCI, and SSTL-3 for inputs and outputs.
When the LVDS banks are not used for LVDS I/Os, they support all of the
other I/O standards. Figure 29 shows the arrangement of the APEX 20KE
I/O banks.
Altera Corporation
45
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
Figure 29. APEX 20KE I/O Banks
I/O Bank 1
I/O Bank 2
I/O Bank 3
(1)
Regular I/O Blocks Support
ꢀ LVTTL
ꢀ LVCMOS
ꢀ 2.5 V
ꢀ 1.8 V
ꢀ 3.3 V PCI
ꢀ GTL+
I/O Bank 8
LVDS/LVPECL
Input
Block (2)
ꢀ SSTL-2 Class I and II
ꢀ SSTL-3 Class I and II
ꢀ CTT
LVDS/LVPECL
Output
Block (2)
ꢀ AGP
I/O Bank 4
(1)
Individual
Power Bus
I/O Bank 7
I/O Bank 6
I/O Bank 5
Notes:
(1) The first two I/O pins that border the LVDS blocks can only be used for input to
maintain an acceptable noise level on the VCCIO plane.
(2) If the LVDS input and output blocks are not used for LVDS, they can support all of
the I/O standards and can be used as input, output, or bidirectional pins with
VCCIO set to 3.3 V, 2.5 V, or 1.8 V.
Power Sequencing & Hot Socketing
Because APEX 20K devices can be used in a mixed-voltage environment,
they have been designed specifically to tolerate any possible power-up
sequence. Therefore, the V
powered in any order.
and V
power planes may be
CCIO
CCINT
Signals can be driven into APEX 20K devices before and during power-up
without damaging the device. In addition, APEX 20K devices do not drive
out during power-up. Once operating conditions are reached and the
device is configured, APEX 20K devices operate as specified by the user.
The APEX architecture supports the MultiVolt I/O interface feature,
which allows APEX devices in all packages to interface with systems of
different supply voltages. The devices have one set of VCC pins for
internal operation and input buffers (VCCINT), and another set for I/O
output drivers (VCCIO).
MultiVolt I/O
Interface
46
Altera Corporation
Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
The APEX 20K VCCINT pins must always be connected to a 2.5 V power
supply. With a 2.5-V V
level, input pins are 2.5-V and 3.3-V tolerant.
CCINT
The devices, identified by a “V” suffix following the speed grade in the
ordering code (e.g., EP20K400BC652-1V), are 5.0-V tolerant. The VCCIO
pins can be connected to either a 2.5-V or 3.3-V power supply, depending
on the output requirements. When VCCIO pins are connected to a 2.5-V
power supply, the output levels are compatible with 2.5-V systems. When
the VCCIO pins are connected to a 3.3-V power supply, the output high is
3.3 V and is compatible with 3.3-V or 5.0-V systems.
Table 12 summarizes 5.0-V tolerant APEX 20K MultiVolt I/O support.
Table 12. 5.0-V Tolerant APEX 20K MultiVolt I/O Support
V
(V)
Input Signals (V)
3.3
Output Signals (V)
CCIO
2.5
5.0
2.5
3.3
5.0
2.5
3.3
v
v
v(1)
v(1), (2)
v(1), (2)
v
v
v(3)
v
v
Notes:
(1) The PCI clamping diode must be disabled to drive an input with voltages higher
than VCCIO
.
(2) APEX 20K devices with a “V” suffix are 5.0-V tolerant.
(3) When VCCIO = 3.3 V, an APEX 20K device can drive a 2.5-V device with 3.3-V
tolerant inputs.
Open-drain output pins on 5.0-V tolerant APEX 20K devices (with a pull-
up resistor to the 5.0-V supply) can drive 5.0-V CMOS input pins that
require a V of 3.5 V. When the pin is inactive, the trace will be pulled up
IH
to 5.0 V by the resistor. The open-drain pin will only drive low or tri-state;
it will never drive high. The rise time is dependent on the value of the
pull-up resistor and load impedance. The I current specification should
OL
be considered when selecting a pull-up resistor.
APEX 20KE devices also support the MultiVolt I/O interface feature. The
APEX 20KE VCCINT pins must always be connected to a 1.8-V power
supply. With a 1.8-V V
level, input pins are 1.8-V, 2.5-V, and 3.3-V
CCINT
tolerant. The VCCIO pins can be connected to either a 1.8-V, 2.5-V, or 3.3-V
power supply, depending on the I/O standard requirements. When the
VCCIO pins are connected to a 1.8-V power supply, the output levels are
compatible with 1.8-V systems. When VCCIO pins are connected to a 2.5-V
power supply, the output levels are compatible with 2.5-V systems. When
VCCIO pins are connected to a 3.3-V power supply, the output high is
3.3 V and compatible with 3.3-V or 5.0-V systems. An APEX 20KE device
is 5.0-V tolerant with the addition of a resistor.
Altera Corporation
47
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
Table 13 summarizes APEX 20KE MultiVolt I/O support.
Table 13. APEX 20KE MultiVolt I/O Support
V
(V)
Input Signals (V)
Output Signals (V)
CCIO
1.8
2.5
3.3
5.0
1.8
2.5
3.3
5.0
1.8
2.5
3.3
v
v(1)
v
v(1)
v(1)
v
v
v
v
v(3)
v(2)
v
v
Notes:
(1) The PCI clamping diode must be disabled to drive an input with voltages higher than VCCIO, except for the 5.0-V
input case.
(2) When VCCIO = 3.3 V, an APEX 20KE device can drive a 2.5-V device with 3.3-V tolerant inputs.
(3) An APEX 20KE device can be made 5.0-V tolerant with the addition of an external resistor.
APEX 20K devices support the ClockLock and ClockBoost clock
management features, which are implemented with PLLs. The ClockLock
circuitry uses a synchronizing PLL that reduces the clock delay and skew
within a device. This reduction minimizes clock-to-output and setup
times while maintaining zero hold times. The ClockBoost circuitry, which
provides a clock multiplier, allows the designer to enhance device area
efficiency by sharing resources within the device. The ClockBoost
circuitry allows the designer to distribute a low-speed clock and multiply
that clock on-device. APEX 20K devices include a high-speed clock tree;
unlike ASICs, the user does not have to design and optimize the clock tree.
The ClockLock and ClockBoost features work in conjunction with the
APEX 20K device’s high-speed clock to provide significant improvements
in system performance and band-width. Devices with an X-suffix on the
ordering code include the ClockLock circuit.
ClockLock &
ClockBoost
Features
The ClockLock and ClockBoost features in APEX 20K devices are enabled
through the Quartus software. External devices are not required to use
these features.
48
Altera Corporation
Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
For designs that require both a multiplied and non-multiplied clock, the
clock trace on the board can be connected to CLK2p. Table 14 shows the
combinations supported by the ClockLock and ClockBoost circuitry. The
CLK2ppin can feed both the ClockLock and ClockBoost circuitry in the
APEX 20K device. However, when both circuits are used, the other clock
pin (CLK1p) cannot be used.
Table 14. Multiplication Factor Combinations
Clock 1
Clock 2
×1
×1
×2
×4
×1, ×2
×1, ×2, ×4
APEX 20KE ClockLock Feature
APEX 20KE devices include an enhanced ClockLock feature set. These
devices include up to four PLLs, which can be used independently. Two
PLLs are designed for either general-purpose use or LVDS use (on devices
that support LVDS I/O pins). The remaining two PLLs are designed for
general-purpose use. The EP20K200E and smaller devices have two PLLs;
the EP20K300E and larger devices have four PLLs.
The following sections describe some of the features offered by the
APEX 20KE PLLs.
External PLL Feedback
The ClockLock circuit’s output can be driven off-chip to clock other
devices in the system; further, the feedback loop of the PLL can be routed
off-chip. This feature allows the designer to exercise fine control over the
I/O interface between the APEX 20KE device and another high-speed
device, such as SDRAM.
Clock Multiplication
The APEX 20KE ClockBoost circuit can multiply or divide clocks by a
programmable number. The clock can be multiplied by m/(n × k), where
m, and k range from 2 to 160 and n ranges from 1 to 16. Clock
multiplication and division can be used for time-domain multiplexing
and other functions, which can reduce design LE requirements.
Altera Corporation
49
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
Clock Phase & Delay Adjustment
The APEX 20KE ClockShift feature allows the clock phase and delay to be
adjusted. The clock phase can be adjusted by 90˚ steps. The clock delay can
be adjusted to increase or decrease the clock delay by an arbitrary amount,
up to one clock period.
LVDS Support
Two PLLs are designed to support the LVDS interface. When using LVDS,
the I/O clock runs at a slower rate than the data transfer rate. Thus, PLLs
are used to multiply the I/O clock internally to capture the LVDS data.
For example, an I/O clock may run at 105 MHz to support 840 megabits
per second (Mbps) LVDS data transfer. In this example, the PLL
multiplies the incoming clock by eight to support the high-speed data
transfer. You can use PLLs in EP20K400E and larger devices for high-
speed LVDS interfacing.
Lock Signals
The APEX 20KE ClockLock circuitry supports individual LOCK signals.
The LOCK signal drives high when the ClockLock circuit has locked onto
the input clock. The LOCK signals are optional for each ClockLock circuit;
when not used, they are I/O pins.
ClockLock & ClockBoost Timing Parameters
For the ClockLock and ClockBoost circuitry to function properly, the
incoming clock must meet certain requirements. If these specifications are
not met, the circuitry may not lock onto the incoming clock, which
generates an erroneous clock within the device. The clock generated by
the ClockLock and ClockBoost circuitry must also meet certain
specifications. If the incoming clock meets these requirements during
configuration, the APEX 20K ClockLock and ClockBoost circuitry will
lock onto the clock during configuration. The circuit will be ready for use
immediately after configuration. In APEX 20KE devices, the clock input
standard is programmable, so the PLL cannot respond to the clock until
the device is configured. The PLL locks onto the input clock as soon as
configuration is complete. Figure 30 shows the incoming and generated
clock specifications.
1
For more information on ClockLock and ClockBoost circuitry,
see Application Note 115: Using the ClockLock and ClockBoost PLL
Features in APEX Devices.
50
Altera Corporation
Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
Figure 30. Specifications for the Incoming & Generated Clocks
The t parameter refers to the nominal input clock period; the t parameter refers to the
I
O
nominal output clock period.
+
tI tCLKDEV
fCLK1,fCLK2
fCLK4
,
tINDUTY
Input
Clock
+
tI tINCLKSTB
tR
tF
tO
tOUTDUTY
ClockLock
Generated
Clock
+
tO
tO tJITTER
tO tJITTER
Table 15 summarizes the APEX 20K ClockLock and ClockBoost
parameters for -1 speed grade devices.
Table 15. APEX 20K ClockLock & ClockBoost Parameters for -1 Speed-Grade
Devices (Part 1 of 2)
Symbol
Parameter
Min
Max
Unit
fOUT
Output frequency
25
25
180
MHz
MHz
fCLK1
(1)
Input clock frequency (ClockBoost
clock multiplication factor equals 1)
180
(1)
fCLK2
Input clock frequency (ClockBoost
clock multiplication factor equals 2)
16
10
40
90
48
60
MHz
MHz
%
fCLK4
Input clock frequency (ClockBoost
clock multiplication factor equals 4)
tOUTDUTY
Duty cycle for
ClockLock/ClockBoost-generated
clock
fCLKDEV
Input deviation from user
25,000
PPM
specification in the Quartus software
(ClockBoost clock multiplication
factor equals 1) (2)
(3)
tR
tF
Input rise time
Input fall time
5
5
ns
ns
Altera Corporation
51
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
Table 15. APEX 20K ClockLock & ClockBoost Parameters for -1 Speed-Grade
Devices (Part 2 of 2)
Symbol
Parameter
Min
Max
Unit
tLOCK
Time required for
10
µs
ClockLock/ClockBoost to acquire
lock(4))
tSKEW
Skew delay between related
ClockLock/ClockBoost-generated
clocks
500
ps
tJITTER
Jitter on ClockLock/ClockBoost-
generated clock (5)
200
50
ps
ps
tINCLKSTB Input clock stability (measured
between adjacent clocks)
Notes:
(1) The PLL input frequency range for the EP20K100-1X device for 1x multiplication is 25 MHz to 175 MHz.
(2) All input clock specifications must be met. The PLL may not lock onto an incoming clock if the clock specifications
are not met, creating an erroneous clock within the device.
(3) During device configuration, the ClockLock and ClockBoost circuitry is configured first. If the incoming clock is
supplied during configuration, the ClockLock and ClockBoost circuitry locks during configuration, because the lock
time is less than the configuration time.
(4) The jitter specification is measured under long-term observation.
(5) If the input clock stability is 100 ps, tJITTER is 250 ps.
Table 16 summarizes the APEX 20K ClockLock and ClockBoost
parameters for -2 speed grade devices.
Table 16. APEX 20K ClockLock & ClockBoost Parameters for -2 Speed Grade
Devices
(Part 1 of 2)
Symbol
Parameter
Min
Max
Unit
fOUT
Output frequency
25
25
170
170
MHz
MHz
fCLK1
Input clock frequency (ClockBoost
clock multiplication factor equals 1)
fCLK2
Input clock frequency (ClockBoost
clock multiplication factor equals 2)
16
10
40
80
34
60
MHz
MHz
%
fCLK4
Input clock frequency (ClockBoost
clock multiplication factor equals 4)
tOUTDUTY
fCLKDEV
Duty cycle for ClockLock/ClockBoost-
generated clock
Input deviation from user specification
in the Quartus software (ClockBoost
clock multiplication factor equals one)
(1)
25,000
(2)
PPM
tR
tF
Input rise time
Input fall time
5
5
ns
ns
52
Altera Corporation
Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
Table 16. APEX 20K ClockLock & ClockBoost Parameters for -2 Speed Grade
Devices
(Part 2 of 2)
Symbol
Parameter
Min
Max
Unit
tLOCK
Time required for ClockLock/
ClockBoost to acquire lock
(3)
10
µs
tSKEW
Skew delay between related
ClockLock/ ClockBoost-generated
clock
500
500
ps
tJITTER
Jitter on ClockLock/ ClockBoost-
200
50
ps
ps
generated clock (4)
tINCLKSTB
Input clock stability (measured between
adjacent clocks)
Notes:
(1) To implement the ClockLock and ClockBoost circuitry with the Quartus software, designers must specify the input
frequency. The Quartus software tunes the PLL in the ClockLock and ClockBoost circuitry to this frequency. The
fCLKDEV parameter specifies how much the incoming clock can differ from the specified frequency during device
operation. Simulation does not reflect this parameter.
(2) Twenty-five thousand parts per million (PPM) equates to 2.5% of input clock period.
(3) During device configuration, the ClockLock and ClockBoost circuitry is configured before the rest of the device. If
the incoming clock is supplied during configuration, the ClockLock and ClockBoost circuitry locks during
configuration because the tLOCK value is less than the time required for configuration.
(4) The tJITTER specification is measured under long-term observation.
Tables 17 and 18 summarize the ClockLock and ClockBoost parameters
for APEX 20KE devices.
Table 17. APEX 20KE ClockLock & ClockBoost Parameters
Symbol Parameter Condition
Note (1)
Min
Typ
Max
Unit
tR
Input rise time
5
5
ns
ns
%
tF
Input fall time
tINDUTY
tINJITTER
Input duty cycle
40
45
60
Input jitter peak-to-peak
2% of input peak-to-
period
peak
tOUTJITTER Jitter on ClockLock or ClockBoost-
0.35% of
output period
RMS
generated clock
tOUTDUTY
Duty cycle for ClockLock or
ClockBoost-generated clock
55
40
%
tLOCK (2),
Time required for ClockLock or
ClockBoost to acquire lock
µs
(3)
Altera Corporation
53
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
Table 18. APEX 20KE Clock Input and Output Parameters
Note (1)
Symbol
Parameter
I/O Standard -1x Speed Grade
-2x Speed Grade Units
Min
Max
Min
Max
fVCO (4)
fCLOCK0
fCLOCK1
Voltage controlled oscillator
operating range
200
500
200
500
MHz
MHz
MHz
Clock0 PLL output frequency for
internal use
1.5
20
335
335
1.5
20
200
200
Clock1 PLL output frequency for
internal use
fCLOCK0_EXT Output clock frequency for external
3.3V LVTTL
2.5V LVTTL
1.8V LVTTL
GTL+
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
20
245
234
223
205
158
142
166
149
420
245
234
223
205
158
142
166
149
420
290
281
272
303
291
291
300
300
420
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
20
226
221
216
193
157
142
162
146
350
226
221
216
193
157
142
162
146
350
257
250
243
261
253
253
260
260
350
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
clock0 output
SSTL2 Class I
SSTL2 Class II
SSTL3 Class I
SSTL3 Class II
LVDS
fCLOCK1_EXT Output clock frequency for external
3.3V LVTTL
2.5V LVTTL
1.8V LVTTL
GTL+
clock1 output
20
20
20
20
20
20
SSTL2 Class I
SSTL2 Class II
SSTL3 Class I
SSTL3 Class II
LVDS
20
20
20
20
20
20
20
20
20
20
fIN
Input clock frequency
3.3V LVTTL
2.5V LVTTL
1.8V LVTTL
GTL+
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
SSTL2 Class I
SSTL2 Class II
SSTL3 Class I
SSTL3 Class II
LVDS
Notes:
(1) All input clock specifications must be met. The PLL may not lock onto an incoming clock if the clock specifications
are not met, creating an erroneous clock within the device.
(2) The lock time is 40 µs max or 2000 input clock cycles, whichever occurs first.
(3) Before configuration, the PLL circuits are disable and powered down. During configuration, the PLLs are still
disabled. The PLLs begin to lock once the device is in the user mode. If the clock enable feature is used, lock begins
once the CLKLK_ENA pin goes high in user mode.
(4) The PLL VCO operating range is 200 MHz <= fVCO <= 840 MHz for LVDS mode.
54
Altera Corporation
Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
APEX 20K devices include device enhancements to support the SignalTap
embedded logic analyzer. By including this circuitry, the APEX 20K
device provides the ability to monitor design operation over a period of
time through the IEEE Std. 1149.1 (JTAG) circuitry; a designer can analyze
internal logic at speed without bringing internal signals to the I/O pins.
This feature is particularly important for advanced packages such as
FineLine BGA packages because adding a connection to a pin during the
debugging process can be difficult after a board is designed and
manufactured.
SignalTap
Embedded
Logic Analyzer
All APEX 20K devices provide JTAG BST circuitry that complies with the
IEEE Std. 1149.1-1990 specification. JTAG boundary-scan testing can be
performed before or after configuration, but not during configuration.
APEX 20K devices can also use the JTAG port for configuration with the
Quartus software or with hardware using either Jam Files (.jam) or Jam
Byte-Code Files (.jbc). Finally, APEX 20K devices use the JTAG port to
monitor the logic operation of the device with the SignalTap embedded
logic analyzer. APEX 20K devices support the JTAG instructions shown in
Table 19.
IEEE Std.
1149.1 (JTAG)
Boundary-Scan
Support
Table 19. APEX 20K JTAG Instructions
JTAG Instruction
Description
SAMPLE/PRELOAD Allows a snapshot of signals at the device pins to be captured and examined during
normal device operation, and permits an initial data pattern to be output at the device pins.
Also used by the SignalTap embedded logic analyzer.
EXTEST
Allows the external circuitry and board-level interconnections to be tested by forcing a test
pattern at the output pins and capturing test results at the input pins.
BYPASS
Places the 1-bit bypass register between the TDIand TDOpins, which allows the BST data
to pass synchronously through selected devices to adjacent devices during normal device
operation.
USERCODE
IDCODE
Selects the 32-bit USERCODE register and places it between the TDIand TDOpins,
allowing the USERCODE to be serially shifted out of TDO.
Selects the IDCODE register and places it between TDIand TDO, allowing the IDCODE
to be serially shifted out of TDO.
ICR Instructions
Used when configuring an APEX 20K device via the JTAG port with a MasterBlaster or
ByteBlasterMV download cable, or when using a Jam File or Jam Byte-Code File via an
embedded processor.
SignalTap
Monitors internal device operation with the SignalTap embedded logic analyzer.
Instructions
Altera Corporation
55
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
The APEX 20K device instruction register length is 10 bits. The APEX 20K
device USERCODE register length is 32 bits. Tables 20 and 21show the
boundary-scan register length and device IDCODE information for
APEX 20K devices.
Table 20. APEX 20K Boundary-Scan Register Length
Device
Boundary-Scan Register Length
EP20K30E
EP20K60E
EP20K100
420
654
786
EP20K100E
EP20K160E
EP20K200
774
1,176
1,164
1,188
1,266
1,536
1,506
1,866
2,190
2,502
EP20K200E
EP20K300E
EP20K400
EP20K400E
EP20K600E
EP20K1000E
EP20K1500E
56
Altera Corporation
Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
Table 21. 32-Bit APEX 20K Device IDCODE
Device
IDCODE (32 Bits) (1)
Version
(4 Bits)
Part Number (16 Bits)
Manufacturer
Identity (11 Bits)
1 (1 Bit)
(2)
EP20K30E
EP20K60E
EP20K100
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
1000 0000 0011 0000
1000 0000 0110 0000
0000 0100 0001 0110
1000 0001 0000 0000
1000 0001 0110 0000
0000 1000 0011 0010
1000 0010 0000 0000
1000 0011 0000 0000
0001 0110 0110 0100
1000 0100 0000 0000
1000 0110 0000 0000
1001 0000 0000 0000
1001 0101 0000 0000
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
1
1
1
1
1
1
1
1
1
1
1
1
1
EP20K100E
EP20K160E
EP20K200
EP20K200E
EP20K300E
EP20K400
EP20K400E
EP20K600E
EP20K1000E
EP20K1500E
Notes:
(1) The most significant bit (MSB) is on the left.
(2) The IDCODE’s least significant bit (LSB) is always 1.
Figure 31 shows the timing requirements for the JTAG signals.
Altera Corporation
57
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
Figure 31. APEX 20K JTAG Waveforms
TMS
TDI
tJCP
tJCH
t JCL
tJPH
tJPSU
TCK
TDO
tJPXZ
tJPZX
tJPCO
tJSSU
tJSH
Signal
to Be
Captured
tJSCO
tJSZX
tJSXZ
Signal
to Be
Driven
Table 22 shows the JTAG timing parameters and values for APEX 20K
devices.
Table 22. APEX 20K JTAG Timing Parameters & Values
Symbol
Parameter
Min Max Unit
tJCP
TCKclock period
100
50
50
20
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tJCH
TCKclock high time
TCKclock low time
JTAG port setup time
JTAG port hold time
tJCL
tJPSU
tJPH
tJPCO
tJPZX
tJPXZ
tJSSU
tJSH
JTAG port clock to output
25
25
25
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Capture register setup time
20
45
Capture register hold time
tJSCO
tJSZX
tJSXZ
Update register clock to output
35
35
35
Update register high impedance to valid output
Update register valid output to high impedance
For more information, see the following documents:
f
ꢀ
ꢀ
Application Note 39 (IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing in
Altera Devices)
Jam Programming & Test Language Specification
58
Altera Corporation
Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
Each APEX 20K device is functionally tested. Complete testing of each
configurable static random access memory (SRAM) bit and all logic
functionality ensures 100% yield. AC test measurements for FLEX 10KE
devices are made under conditions equivalent to those shown in
Figure 32. Multiple test patterns can be used to configure devices during
all stages of the production flow.
Generic Testing
Figure 32. APEX 20K AC Test Conditions
Power supply transients can affect AC
Device
Output
to Test
System
measurements. Simultaneous transitions of
multiple outputs should be avoided for
accurate measurement. Threshold tests
must not be performed under AC conditions.
Large-amplitude, fast-ground-current
transients normally occur as the device
outputs discharge the load capacitances.
When these transients flow through the
parasitic inductance between the device
ground pin and the test system ground,
significant reductions in observable noise
immunity can result.
C1 (includes
JIG capacitance)
Device input
rise and fall
times < 3 ns
Tables 23 through 26 provide information on absolute maximum ratings,
recommended operating conditions, DC operating conditions, and
capacitance for 2.5-V APEX 20K devices.
Operating
Conditions
Table 23. APEX 20K Device Absolute Maximum Ratings
Note (1)
Symbol
Parameter
Conditions
Min
Max
Unit
VCCINT
VCCIO
VI
Supply voltage
With respect to ground (2)
–0.5
–0.5
–0.5
–25
–65
–65
3.6
4.6
4.6
25
V
V
DC input voltage
V
IOUT
TSTG
TAMB
TJ
DC output current, per pin
Storage temperature
Ambient temperature
Junction temperature
mA
° C
° C
° C
No bias
150
135
135
Under bias
PQFP, RQFP, TQFP, and BGA packages,
under bias
Ceramic PGA packages, under bias
150
° C
Altera Corporation
59
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
Table 24. APEX 20K Device Recommended Operating Conditions
Symbol
Parameter
Conditions
Min
Max
Unit
VCCINT
Supply voltage for internal logic and
input buffers
(3), (4)
2.375
2.625
V
(2.375)
(2.625)
VCCIO
Supply voltage for output buffers, 3.3-V (3), (4)
3.00 (3.00) 3.60 (3.60)
V
V
operation
Supply voltage for output buffers, 2.5-V (3), (4)
2.375
2.625
operation
(2.375)
(2.625)
VI
Input voltage
(2), (5)
–0.5
0
4.1
VCCIO
85
V
V
VO
TJ
Output voltage
Operating temperature
For commercial use
For industrial use
0
° C
° C
ns
ns
–40
100
40
tR
tF
Input rise time
Input fall time
40
Table 25. APEX 20K Device DC Operating Conditions (Part 1 of 2)
Notes (6), (7)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIH
High-level LVTTL, CMOS, or 3.3-V
PCI input voltage
1.7, 0.5 × VCCIO
(8)
4.1
V
VIL
Low-level LVTTL, CMOS, or 3.3-V
PCI input voltage
–0.5
2.4
0.8, 0.3 × VCCIO
(8)
V
V
V
V
V
V
V
VOH
3.3-V high-level LVTTL output
voltage
IOH = –12 mA DC,
VCCIO = 3.00 V (9)
3.3-V high-level LVCMOS output
voltage
I
OH = –0.1 mA DC,
VCCIO – 0.2
VCCIO = 3.00 V (9)
3.3-V high-level PCI output voltage IOH = –0.5 mA DC,
VCCIO = 3.00 to 3.60 V (9)
OH = –0.1 mA DC,
VCCIO = 2.30 V (9)
OH = –1 mA DC,
VCCIO = 2.30 V (9)
OH = –2 mA DC,
VCCIO = 2.30 V (9)
0.9 × VCCIO
2.5-V high-level output voltage
I
2.1
2.0
1.7
I
I
60
Altera Corporation
Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
Table 25. APEX 20K Device DC Operating Conditions (Part 2 of 2)
Notes (6), (7)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VOL
3.3-V low-level LVTTL output
voltage
IOL = 12 mA DC,
0.4
V
VCCIO = 3.00 V (10)
3.3-V low-level LVCMOS output
voltage
I
OL = 0.1 mA DC,
VCCIO = 3.00 V (10)
OL = 1.5 mA DC,
0.2
V
V
3.3-V low-level PCI output voltage
I
0.1 × VCCIO
VCCIO = 3.00 to 3.60 V
(10)
2.5-V low-level output voltage
IOL = 0.1 mA DC,
0.2
0.4
0.7
V
V
V
VCCIO = 2.30 V (10)
I
OL = 1 mA DC,
VCCIO = 2.30 V (10)
OL = 2 mA DC,
I
VCCIO = 2.30 V (10)
II
Input pin leakage current
VI = 4.1 to –0.5 V
–10
–10
10
10
µA
µA
IOZ
ICC0
Tri-stated I/O pin leakage current VO = 4.1 to –0.5 V
VCC supply current (standby)
(All ESBs in power-down mode)
VI = ground, no load, no
toggling inputs, -1 speed
grade
10
5
mA
VI = ground, no load, no
toggling inputs,
mA
-2, -3 speed grades
RCONF
Value of I/O pin pull-up resistor
before and during configuration
VCCIO = 3.0 V (11)
20
30
50
80
kΩ
kΩ
VCCIO = 2.375 V (11)
Table 26. APEX 20K Device Capacitance
Note (12)
Symbol
Parameter
Conditions
Min
Max
Unit
CIN
Input capacitance
VIN = 0 V, f = 1.0 MHz
VIN = 0 V, f = 1.0 MHz
8
pF
pF
CINCLK
Input capacitance on dedicated
clock pin
12
COUT
Output capacitance
VOUT = 0 V, f = 1.0 MHz
8
pF
Altera Corporation
61
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
Notes to tables:
(1) See the Operating Requirements for Altera Devices Data Sheet.
(2) Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to 4.6 V for
input currents less than 100 mA and periods shorter than 20 ns.
(3) Numbers in parentheses are for industrial-temperature-range devices.
(4) Maximum VCC rise time is 100 ms, and VCC must rise monotonically.
(5) All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before VCCINT and VCCIO are
powered.
(6) Typical values are for TA = 25 °C, VCCINT = 2.5 V, and VCCIO = 2.5 V or 3.3 V.
(7) These values are specified under the APEX 20K device recommended operating conditions, shown in Table 24 on
page 60.
(8) The APEX 20K input buffers are compatible with 2.5-V and 3.3-V (LVTTL and LVCMOS) signals. Additionally, the
input buffers are 3.3-V PCI compliant when VCCIO and VCCINT meet the relationship shown in Figure 33 on page
68.
(9) The IOH parameter refers to high-level TTL, PCI, or CMOS output current.
(10) The IOL parameter refers to low-level TTL, PCI, or CMOS output current. This parameter applies to open-drain pins
as well as output pins.
(11) Pin pull-up resistance values will be lower if an external source drives the pin higher than VCCIO
.
(12) Capacitance is sample-tested only.
Tables 27 through 30 provide information on absolute maximum ratings,
recommended operating conditions, DC operating conditions, and
capacitance for 5.0-V tolerant APEX 20K devices. These devices are
identified by a “V” suffix following the speed grade in the ordering code
(e.g., EP20K400BC652-1V).
Table 27. APEX 20K 5.0-V Tolerant Device Absolute Maximum Ratings
Note (1)
Min
Symbol
Parameter
Conditions
Max
Unit
VCCINT
VCCIO
VI
Supply voltage
With respect to ground (2)
–0.5
–0.5
–2.0
–25
–65
–65
3.6
4.6
V
V
DC input voltage
5.75
25
V
IOUT
TSTG
TAMB
TJ
DC output current, per pin
Storage temperature
Ambient temperature
Junction temperature
mA
° C
° C
° C
No bias
150
135
135
Under bias
PQFP, RQFP, TQFP, and BGA packages,
under bias
Ceramic PGA packages, under bias
150
° C
62
Altera Corporation
Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
Table 28. APEX 20K 5.0-V Tolerant Device Recommended Operating Conditions
Symbol
Parameter
Conditions
Min
Max
Unit
VCCINT
Supply voltage for internal logic
and input buffers
(3), (4)
2.375
2.625
V
(2.375)
(2.625)
VCCIO
Supply voltage for output buffers, (3), (4)
3.00 (3.00) 3.60 (3.60)
V
V
3.3-V operation
Supply voltage for output buffers, (3), (4)
2.375
2.625
2.5-V operation
(2.375)
(2.625)
VI
Input voltage
(2), (5)
–0.5
0
5.75
VCCIO
85
V
V
VO
TJ
Output voltage
Operating temperature
For commercial use
For industrial use
0
° C
° C
40
100
tR
tF
Input rise time
Input fall time
40
40
ns
ns
Table 29. APEX 20K 5.0-V Tolerant Device DC Operating Conditions (Part 1 of 2)
Notes (6), (7)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIH
High-level input voltage
1.7, 0.5 × VCCIO
5.75
V
(8))
VIL
Low-level input voltage
–0.5
2.4
0.8, 0.3 × VCCIO
V
V
V
V
V
V
V
(8)
VOH
3.3-V high-level TTL output
voltage
IOH = –8 mA DC,
VCCIO = 3.00 V (9)
3.3-V high-level CMOS output
voltage
I
OH = –0.1 mA DC,
VCCIO – 0.2
VCCIO = 3.00 V (9)
3.3-V high-level PCI output voltage IOH = –0.5 mA DC,
VCCIO = 3.00 to 3.60 V (9)
IOH = –0.1 mA DC,
VCCIO = 2.30 V (9)
OH = –1 mA DC,
VCCIO = 2.30 V (9)
OH = –2 mA DC,
VCCIO = 2.30 V (9)
0.9 × VCCIO
2.5-V high-level output voltage
2.1
2.0
1.7
I
I
Altera Corporation
63
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
Table 29. APEX 20K 5.0-V Tolerant Device DC Operating Conditions (Part 2 of 2)
Notes (6), (7)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VOL
3.3-V low-level TTL output voltage IOL = 12 mA DC,
0.45
V
VCCIO = 3.00 V (10)
3.3-V low-level CMOS output
voltage
I
OL = 0.1 mA DC,
VCCIO = 3.00 V (10)
OL = 1.5 mA DC,
0.2
V
V
3.3-V low-level PCI output voltage
I
0.1 × VCCIO
VCCIO = 3.00 to 3.60 V
(10)
2.5-V low-level output voltage
IOL = 0.1 mA DC,
0.2
0.4
0.7
V
V
V
VCCIO = 2.30 V (10)
I
OL = 1 mA DC,
VCCIO = 2.30 V (10)
OL = 2 mA DC,
I
VCCIO = 2.30 V (10)
II
Input pin leakage current
VI = 5.75 to –0.5 V
–10
–10
10
10
µA
µA
IOZ
ICC0
Tri-stated I/O pin leakage current VO = 5.75 to –0.5 V
VCC supply current (standby)
(All ESBs in power-down mode)
VI = ground, no load, no
toggling inputs, -1 speed
grade
10
5
mA
VI = ground, no load, no
toggling inputs,
mA
-2, -3 speed grades
RCONF
Value of I/O pin pull-up resistor
before and during configuration
VCCIO = 3.0 V 9 (11)
VCCIO = 2.375 V (11)
20
30
50
80
kΩ
kΩ
Table 30. APEX 20K 5.0-V Tolerant Device Capacitance
Note (12)
Symbol
Parameter
Conditions
Min
Max
Unit
CIN
Input capacitance
VIN = 0 V, f = 1.0 MHz
8
pF
pF
CINCLK
Input capacitance on dedicated
clock pin
VIN = 0 V, f = 1.0 MHz
12
COUT
Output capacitance
VOUT = 0 V, f = 1.0 MHz
8
pF
Notes to tables:
(1) See the Operating Requirements for Altera Devices Data Sheet.
(2) Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –0.5 V or overshoot to 5.75 V for
input currents less than 100 mA and periods shorter than 20 ns.
(3) Numbers in parentheses are for industrial-temperature-range devices.
(4) Maximum VCC rise time is 100 ms, and VCC must rise monotonically.
(5) All pins, including dedicated inputs, clock I/O, and JTAG pins, may be driven before VCCINT and VCCIO are
powered.
(6) Typical values are for TA= 25 °C, VCCINT = 2.5 V, and VCCIO = 2.5 or 3.3 V.
(7) These values are specified in the APEX 20K device recommended operating conditions, shown in Table 26 on page
62.
(8) The APEX 20K input buffers are compatible with 2.5-V and 3.3-V (LVTTL and LVCMOS) signals. Additionally, the
input buffers are 3.3-V PCI compliant when VCCIO and VCCINT meet the relationship shown in Figure 33 on page
68.
64
Altera Corporation
Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
(9) The IOH parameter refers to high-level TTL, PCI or CMOS output current.
(10) The IOL parameter refers to low-level TTL, PCI, or CMOS output current. This parameter applies to open-drain pins
as well as output pins.
(11) Pin pull-up resistance values will be lower if an external source drives the pin higher than VCCIO
.
(12) Capacitance is sample-tested only.
Tables 31 through 34 provide information on absolute maximum ratings,
recommended operating conditions, DC operating conditions, and
capacitance for 1.8-V APEX 20KE devices.
Table 31. APEX 20KE Device Absolute Maximum Ratings
Note (1)
Symbol
Parameter
Conditions
Min
Max
Unit
VCCINT
VCCIO
VI
Supply voltage
With respect to ground (2)
–0.5
–0.5
–0.5
–25
–65
–65
2.5
4.6
4.6
25
V
V
DC input voltage
V
IOUT
TSTG
TAMB
TJ
DC output current, per pin
Storage temperature
Ambient temperature
Junction temperature
mA
°C
°C
°C
No bias
150
135
135
Under bias
PQFP, RQFP, TQFP, and BGA packages,
under bias
Ceramic PGA packages, under bias
150
°C
Table 32. APEX 20KE Device Recommended Operating Conditions
Symbol
Parameter
Conditions
Min
Max
Unit
VCCINT
Supply voltage for internal logic and
input buffers
(3), (4)
1.71 (1.71) 1.89 (1.89)
V
VCCIO
Supply voltage for output buffers, 3.3-V (3), (4)
3.00 (3.00) 3.60 (3.60)
V
V
operation
Supply voltage for output buffers, 2.5-V (3), (4)
2.375
2.625
operation
(2.375)
(2.625)
VI
Input voltage
(2), (5)
–0.5
0
4.1
VCCIO
85
V
V
VO
TJ
Output voltage
Operating temperature
For commercial use
For industrial use
0
° C
° C
ns
ns
–40
100
40
tR
tF
Input rise time
Input fall time
40
Altera Corporation
65
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
Table 33. APEX 20KE Device DC Operating Conditions
Notes (6), (7)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIH
High-level LVTTL, CMOS, or 3.3-V
PCI input voltage
1.7, 0.5 × VCCIO
(8)
4.1
V
VIL
Low-level LVTTL, CMOS, or 3.3-V
PCI input voltage
–0.5
0.8, 0.3 × VCCIO
(8)
V
V
V
V
V
V
V
V
V
V
VOH
3.3-V high-level LVTTL output
voltage
IOH = –12 mA DC,
2.4
VCCIO = 3.00 V (9)
3.3-V high-level LVCMOS output
voltage
I
OH = –0.1 mA DC,
V
CCIO – 0.2
VCCIO = 3.00 V (9)
3.3-V high-level PCI output voltage IOH = –0.5 mA DC,
VCCIO = 3.00 to 3.60 V (9)
OH = –0.1 mA DC,
VCCIO = 2.30 V (9)
OH = –1 mA DC,
VCCIO = 2.30 V (9)
OH = –2 mA DC,
0.9 × VCCIO
2.5-V high-level output voltage
I
2.1
2.0
1.7
I
I
VCCIO = 2.30 V (9)
VOL
3.3-V low-level LVTTL output
voltage
IOL = 12 mA DC,
0.4
0.2
VCCIO = 3.00 V (10)
3.3-V low-level LVCMOS output
voltage
I
OL = 0.1 mA DC,
VCCIO = 3.00 V (10)
OL = 1.5 mA DC,
3.3-V low-level PCI output voltage
I
0.1 × VCCIO
VCCIO = 3.00 to 3.60 V
(10)
2.5-V low-level output voltage
I
OL = 0.1 mA DC,
CCIO = 2.30 V (10)
0.2
0.4
0.7
V
V
V
V
IOL = 1 mA DC,
VCCIO = 2.30 V (10)
I
OL = 2 mA DC,
VCCIO = 2.30 V (10)
II
Input pin leakage current
VI = 4.1 to –0.5 V
–10
–10
10
10
µA
µA
IOZ
ICC0
Tri-stated I/O pin leakage current VO = 4.1 to –0.5 V
VCC supply current (standby)
(All ESBs in power-down mode)
VI = ground, no load, no
toggling inputs, -1 speed
grade
10
5
mA
VI = ground, no load, no
toggling inputs,
mA
-2, -3 speed grades
RCONF
Value of I/O pin pull-up resistor
before and during configuration
VCCIO = 3.0 V (11)
VCCIO = 2.375 V (11)
VCCIO = 1.71 V (11)
20
30
60
50
80
kΩ
kΩ
kΩ
150
1
For DC Operating Specifications on APEX 20KE I/O standards,
please refer to Application Note 117 (Using Selectable I/O Standards
in Altera Devices).
66
Altera Corporation
Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
Table 34. APEX 20KE Device Capacitance
Note (12)
Symbol
Parameter
Conditions
Min
Max
Unit
CIN
Input capacitance
VIN = 0 V, f = 1.0 MHz
8
pF
pF
CINCLK
Input capacitance on dedicated
clock pin
VIN = 0 V, f = 1.0 MHz
VOUT = 0 V, f = 1.0 MHz
12
COUT
Output capacitance
8
pF
Notes to tables:
(1) See the Operating Requirements for Altera Devices Data Sheet.
(2) Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –0.5 V or overshoot to 4.6 V for
input currents less than 100 mA and periods shorter than 20 ns.
(3) Numbers in parentheses are for industrial-temperature-range devices.
(4) Maximum VCC rise time is 100 ms, and VCC must rise monotonically.
(5) All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before VCCINT and VCCIO are
powered.
(6) Typical values are for TA = 25° C, VCCINT = 1.8 V, and VCCIO = 1.8 V, 2.5 V or 3.3 V.
(7) These values are specified under the APEX 20KE device recommended operating conditions, shown in Table 32 on
page 65.
(8) The APEX 20KE input buffers are compatible with 1.8-V, 2.5-V and 3.3-V (LVTTL and LVCMOS) signals.
Additionally, the input buffers are 3.3-V PCI compliant. Input buffers also meet specifications for GTL+, CTT, AGP,
SSTL-2, SSTL-3, and HSTL.
(9) The IOH parameter refers to high-level TTL, PCI, or CMOS output current.
(10) The IOL parameter refers to low-level TTL, PCI, or CMOS output current. This parameter applies to open-drain pins
as well as output pins.
(11) Pin pull-up resistance values will be lower if an external source drives the pin higher than VCCIO
.
(12) Capacitance is sample-tested only.
Figure 33 shows the relationship between V
and V
for 3.3-V PCI
CCIO
CCINT
compliance on APEX 20K devices. For information on this relationship on
APEX 20KE devices, contact Altera Applications.
Altera Corporation
67
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
Figure 33. Relationship between V
& V
for 3.3-V PCI Compliance
CCIO
CCINT
2.7
VCCINT (V)
PCI-Compliant Region
2.5
2.3
3.0
3.1
3.3
3.6
VCCIO (V)
Figure 34 shows the typical output drive characteristics of APEX 20K
devices with 3.3-V and 2.5-V V . The output driver is compatible with
CCIO
the 3.3-V PCI Local Bus Specification, Revision 2.2 (when VCCIOpins are
connected to 3.3 V). 5-V tolerant APEX 20K devices in the -1 speed grade
are 5-V PCI compliant over all operating conditions.
Figure 34. Output Drive Characteristics of APEX 20K Device
90
80
70
90
80
70
IOL
IOL
60
50
40
60
50
40
VCCINT = 2.5 V
VCCIO = 2.5 V
Room Temperature
V
CCINT = 2.5 V
Typical IO
Output
Current (mA)
Typical IO
Output
Current (mA)
VCCIO = 3.3 V
Room Temperature
30
20
10
30
20
10
IOH
IOH
1
2
3
1
2
3
VO Output Voltage (V)
VO Output Voltage (V)
68
Altera Corporation
Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
Figure 35 shows the output drive characteristics of APEX 20KE devices.
Figure 35. Output Drive Characteristics of APEX 20KE Devices
60
120
110
55
50
I
I
OL
OL
100
90
45
40
35
30
25
20
15
10
5
80
70
V
V
= 1.8 V
= 3.3 V
V
V
= 1.8 V
= 2.5V
Typical I
Output
Current (mA)
CCINT
CCIO
CCINT
CCIO
Typical I
Output
O
O
Current (mA)
60
Room Temperature
Room Temperature
50
40
30
20
10
I
I
OH
OH
0.5
1
1.5
Vo Output Voltage (V)
2
3
2
2.5
3
0.5
1
1.5
2.5
Vo Output Voltage (V)
26
24
I
OL
22
20
18
Typical I
Output
Current (mA)
V
V
= 1.8V
O
CCINT
= 1.8V
16
CCIO
14
12
10
8
Room Temperature
6
I
OH
4
2
1.5
Vo Output Voltage (V)
0.5
1
2.0
The continuous, high-performance FastTrack and MegaLAB interconnect
routing resources ensure predictable performance, accurate simulation,
and accurate timing analysis. This predictable performance contrasts with
that of FPGAs, which use a segmented connection scheme and therefore
have unpredictable performance.
Timing Model
Altera Corporation
69
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
Figure 36 shows the timing model for bidirectional I/O pin timing.
Figure 36. Synchronous Bidirectional Pin External Timing
(1)
PRN
tXZBIDIR
tZXBIDIR
D
Q
Dedicated
Clock
CLRN
tOUTCOBIDIR
PRN
Bidirectional Pin
D
Q
tINSUBIDIR
tINHBIDIR
CLRN
IOE Register
(1)
PRN
D
Q
CLRN
Note:
(1) The output enable and input registers are LE registers in the LAB adjacent to the
bidirectional pin.
Tables 35 and 36 describe APEX 20K external timing parameters.
Table 35. APEX 20K External Timing Parameters
Note (1)
Symbol
Clock Parameter
Conditions
t
t
t
t
t
t
Setup time with global clock at IOE register
INSU
Hold time with global clock at IOE register
INH
Clock-to-output delay with global clock at IOE register
Setup time with global clock for registers used in PCI designs
Clock-to-output delay with global clock for registers used in PCI designs
Hold time with global clock for registers used in PCI designs
OUTCO
PCISU
PCICO
PCIH
70
Altera Corporation
Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
Table 36. External Bidirectional Timing Parameters
Symbol
Note (1)
Parameter
Condition
t
t
t
Setup time for bidirectional pins with global clock at same-row or same-
column LE register
INSUBIDIR
Hold time for bidirectional pins with global clock at same-row or same-
column LE register
INHBIDIR
Clock-to-output delay for bidirectional pins with global clock at IOE
register
C1 = 35 pF
OUTCOBIDIR
t
t
Synchronous IOE output buffer disable delay
C1 = 35 pF
C1 = 35 pF
XZBIDIR
Synchronous IOE output buffer enable delay, slow slew rate = off
ZXBIDIR
Note to tables:
(1) These timing parameters are sample-tested only.
Figure 37 shows the f
timing model for APEX 20K and APEX 20KE
MAX
devices.
Figure 37. f
Timing Model
MAX
LE
tSU
Routing Delay
tH
tF1–4
tCO
tLUT
tF5–20
tF20+
ESB
tESBRC
tESBWC
tESBWESU
tESBDATASU
tESBADDRSU
tESBDATACO1
tESBDATACO2
tESBDD
tPD
tPTERMSU
tPTERMCO
Altera Corporation
71
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
Table 37describes the f
timing parameters shown in Figure 37.
MAX
Table 37. APEX 20K & APEX 20KE f
Timing Parameters
MAX
Symbol
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
LE register setup time before clock
LE register hold time before clock
LE register clock-to-output delay
LUT delay for data-in
SU
H
CO
LUT
ESB Asynchronous read cycle time
ESB Asynchronous write cycle time
ESBRC
ESBWC
ESBWESU
ESBDATASU
ESBADDRSU
ESBDATACO1
ESBDATACO2
ESBDD
PD
ESB WE setup time before clock when using input register
ESB data setup time before clock when using input register
ESB address setup time before clock when using input registers
ESB clock-to-output delay when using output registers
ESB clock-to-output delay without output registers
ESB data-in to data-out delay for RAM mode
ESB macrocell input to non-registered output
ESB macrocell register setup time before clock
ESB macrocell register clock-to-output delay
Fanout delay using local interconnect
Fanout delay using MegaLab Interconnect
Fanout delay using FastTrack Interconnect
Minimum clock high time from clock pin
Minimum clock low time from clock pin
LE clear pulse width
PTERMSU
PTERMCO
F1-4
F5-20
F20+
CH
CL
CLRP
LE preset pulse width
PREP
Clock high time
ESBCH
ESBCL
ESBWP
ESBRP
Clock low time
Write pulse width
Read pulse width
72
Altera Corporation
Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
Tables 38 through 43 show the f
timing parameters for EP20K100,
MAX
EP20K200, EP20K400, EP20K300E, EP20K400E, EP20K600E, and
EP20K1000E devices.
Table 38. EP20K100 f
Timing Parameters
MAX
Symbol
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Max
Min
Max
Min
Max
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
0.5
0.7
0.6
0.8
0.8
1.0
SU
H
0.3
0.8
1.7
5.7
0.4
1.0
2.1
6.9
0.5
1.3
2.4
8.1
CO
LUT
ESBRC
ESBWC
ESBWESU
ESBDATASU
ESBADDRSU
ESBDATACO1
ESBDATACO2
ESBDD
PD
3.3
2.2
2.4
3.9
2.7
2.9
4.6
3.1
3.3
1.3
2.6
2.5
2.5
1.6
3.1
3.3
3.0
1.8
3.6
3.6
3.6
2.3
2.6
3.2
PTERMSU
PTERMCO
F1-4
1.5
0.5
1.6
2.2
1.8
0.6
1.7
2.2
2.1
0.7
1.8
2.3
F5-20
F20+
2.0
2.0
0.3
0.5
2.0
2.0
1.6
1.0
2.5
2.5
0.4
0.5
2.5
2.5
1.9
1.3
3.0
3.0
0.4
0.5
3.0
3.0
2.2
1.4
CH
CL
CLRP
PREP
ESBCH
ESBCL
ESBWP
ESBRP
Altera Corporation
73
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
Table 39. EP20K200 f
Timing Parameters
MAX
Symbol
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Max
Min
Max
Min
Max
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
0.5
0.7
0.6
0.8
0.8
1.0
SU
H
0.3
0.8
1.7
5.7
0.4
1.0
2.1
6.9
0.5
1.3
2.4
8.1
CO
LUT
ESBRC
ESBWC
ESBWESU
ESBDATASU
ESBADDRSU
ESBDATACO1
ESBDATACO2
ESBDD
PD
3.3
2.2
2.4
3.9
2.7
2.9
4.6
3.1
3.3
1.3
2.6
2.5
2.5
1.6
3.1
3.3
3.0
1.8
3.6
3.6
3.6
2.3
2.7
3.2
PTERMSU
PTERMCO
F1-4
1.5
0.5
1.6
2.2
1.8
0.6
1.7
2.2
2.1
0.7
1.8
2.3
F5-20
F20+
2.0
2.0
0.3
0.4
2.0
2.0
1.6
1.0
2.5
2.5
0.4
0.5
2.5
2.5
1.9
1.3
3.0
3.0
0.4
0.5
3.0
3.0
2.2
1.4
CH
CL
CLRP
PREP
ESBCH
ESBCL
ESBWP
ESBRP
74
Altera Corporation
Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
Table 40. EP20K400 f
Timing Parameters
MAX
Symbol
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Max
Min
Max
Min
Max
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
0.1
0.5
0.3
0.8
0.6
0.9
SU
H
0.1
1.0
1.7
5.7
0.4
1.2
2.1
6.9
0.6
1.4
2.4
8.1
CO
LUT
ESBRC
ESBWC
ESBWESU
ESBDATASU
ESBADDRSU
ESBDATACO1
ESBDATACO2
ESBDD
PD
3.3
2.2
2.4
3.9
2.7
2.9
4.6
3.1
3.3
1.3
2.5
2.5
2.5
1.6
3.1
3.3
3.1
1.8
3.6
3.6
3.6
1.7
2.1
2.4
PTERMSU
PTERMCO
F1-4
1.0
0.4
2.6
3.7
1.2
0.5
2.8
3.8
1.4
0.6
2.9
3.9
F5-20
F20+
2.0
2.0
0.5
0.5
2.0
2.0
1.5
1.0
2.5
2.5
0.6
0.5
2.5
2.5
1.9
1.2
3.0
3.0
0.8
0.5
3.0
3.0
2.2
1.4
CH
CL
CLRP
PREP
ESBCH
ESBCL
ESBWP
ESBRP
Altera Corporation
75
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
Table 41. EP20K300E f
Timing Parameters
MAX
Symbol
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Max
Min
Max
Min
Max
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
0.1
0.3
0.3
0.7
0.6
0.9
SU
H
0.1
0.9
1.5
5.2
0.4
1.0
1.8
5.9
0.6
1.2
2.2
7.4
CO
LUT
ESBRC
ESBWC
ESBWESU
ESBDATASU
ESBADDRSU
ESBDATACO1
ESBDATACO2
ESBDD
PD
2.9
1.9
2.2
3.3
2.2
2.4
4.2
2.9
3.0
1.3
2.3
2.3
2.3
1.4
2.6
3.2
2.6
1.7
3.3
3.5
3.3
1.6
1.8
2.2
PTERMSU
PTERMCO
F1-4
0.9
0.3
2.6
3.5
1.1
0.4
2.6
3.6
1.3
0.5
2.6
3.6
F5-20
F20+
2.0
2.0
0.5
0.5
2.0
2.0
1.4
0.9
2.2
2.2
0.6
0.5
2.2
2.2
1.6
1.0
2.8
2.8
0.7
0.5
2.8
2.8
2.0
1.3
CH
CL
CLRP
PREP
ESBCH
ESBCL
ESBWP
ESBRP
76
Altera Corporation
Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
Table 42. EP20K400E f
Timing Parameters
MAX
Symbol
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Max
Min
Max
Min
Max
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
0.1
0.3
0.3
0.7
0.6
0.9
SU
H
0.1
0.8
1.5
5.2
0.4
0.9
1.8
5.9
0.6
1.1
2.2
7.4
CO
LUT
ESBRC
ESBWC
ESBWESU
ESBDATASU
ESBADDRSU
ESBDATACO1
ESBDATACO2
ESBDD
PD
2.9
1.9
2.2
3.3
2.2
2.4
4.2
2.9
3.0
1.3
2.3
2.3
2.3
1.4
2.6
3.2
2.6
1.7
3.3
3.5
3.3
1.6
1.8
2.2
PTERMSU
PTERMCO
F1-4
0.9
0.3
2.6
3.5
1.1
0.4
2.6
3.6
1.3
0.5
2.6
3.6
F5-20
F20+
2.0
2.0
0.5
0.5
2.0
2.0
1.4
0.9
2.2
2.2
0.6
0.5
2.2
2.2
1.6
1.0
2.8
2.8
0.7
0.5
2.8
2.8
2.0
1.3
CH
CL
CLRP
PREP
ESBCH
ESBCL
ESBWP
ESBRP
Altera Corporation
77
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
Table 43. EP20K600E f
Timing Parameters
MAX
Symbol
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Max
Min
Max
Min
Max
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
0.1
0.5
0.3
0.7
0.6
0.9
SU
H
0.1
0.8
1.5
5.2
0.4
1.1
1.8
5.9
0.6
1.3
2.2
7.4
CO
LUT
ESBRC
ESBWC
ESBWESU
ESBDATASU
ESBADDRSU
ESBDATACO1
ESBDATACO2
ESBDD
PD
2.9
1.9
2.2
3.3
2.2
2.4
4.2
2.9
3.0
1.3
2.3
2.4
2.3
1.4
2.6
3.2
2.6
1.7
3.3
3.5
3.3
1.6
1.8
2.2
PTERMSU
PTERMCO
F1–4
0.9
0.3
2.6
3.5
1.1
0.4
2.6
3.6
1.3
0.5
2.7
3.7
F5-20
F20+
2.0
2.0
0.5
0.5
2.0
2.0
1.4
0.9
2.2
2.2
0.6
0.5
2.2
2.2
1.6
1.0
2.8
2.8
0.7
0.5
2.8
2.8
2.0
1.3
CH
CL
CLRP
PREP
ESBCH
ESBCL
ESBWP
ESBRP
78
Altera Corporation
Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
Table 44. EP20K1000E f
Timing Parameters
MAX
Symbol
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Max
Min
Max
Min
Max
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
0.1
0.5
0.3
0.7
0.6
0.9
SU
H
0.1
0.9
1.5
5.2
0.4
1.1
1.8
5.9
0.6
1.3
2.2
7.4
CO
LUT
ESBRC
ESBWC
ESBWESU
ESBDATASU
ESBADDRSU
ESBDATACO1
ESBDATACO2
ESBDD
PD
2.9
1.9
2.2
3.3
2.2
2.4
4.2
2.9
3.0
1.3
2.3
2.4
2.3
1.4
2.6
3.2
2.6
1.7
3.3
3.5
3.3
1.6
1.8
2.2
PTERMSU
PTERMCO
F1–4
0.9
0.3
4.6
4.1
1.1
0.4
4.6
4.2
1.3
0.5
4.8
4.4
F5-20
F20+
2.0
2.0
0.5
0.5
2.0
2.0
1.4
0.9
2.2
2.2
0.6
0.5
2.2
2.2
1.6
1.0
2.8
2.8
0.7
0.5
2.8
2.8
2.0
1.3
CH
CL
CLRP
PREP
ESBCH
ESBCL
ESBWP
ESBRP
Altera Corporation
79
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
Tables 45 through 62 show the I/O external and external bidirectional
timing parameter values for APEX 20K and APEX 20KE devices.
Table 45. EP20K100 External Timing Parameters
Symbol -1 Speed Grade -2 Speed Grade
-3 Speed Grade
Min Max
Unit
Min
Max
Min
Max
t
t
t
t
t
t
(1)
2.3
0.0
2.0
1.1
0.0
0.5
2.8
0.0
2.0
1.2
0.0
0.5
3.2
0.0
2.0
–
ns
ns
ns
ns
ns
ns
INSU
(1)
INH
OUTCO
(1)
4.5
2.7
4.9
3.1
6.6
4.8
(2)
INSU
(2)
–
INH
(2)
–
OUTCO
Table 46. EP20K100 External Bidirectional Timing Parameters
Symbol
-1 Speed Grade
Min Max
-2 Speed Grade
Min Max
-3 Speed Grade
Min Max
Unit
t
t
t
t
t
t
t
t
t
t
(1)
2.3
0.0
2.0
2.8
0.0
2.0
3.2
0.0
2.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
INSUBIDIR
(1)
INHBIDIR
OUTCOBIDIR
(1)
4.5
5.0
5.0
4.9
5.9
5.9
6.6
6.9
6.9
(1)
(1)
XZBIDIR
ZXBIDIR
(2)
1.0
0.0
0.5
1.2
0.0
0.5
–
–
–
INSUBIDIR
(2)
INHBIDIR
(2)
2.7
4.3
4.3
3.1
5.0
5.0
–
–
–
OUTCOBIDIR
(2)
(2)
XZBIDIR
ZXBIDIR
Notes to tables:
(1) This parameter is measured without using ClockLock or ClockBoost circuits.
(2) This parameter is measured using ClockLock or ClockBoost circuits.
80
Altera Corporation
Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
Table 47. EP20K100E External Timing Parameters
Symbol -1 Speed Grade -2 Speed Grade
-3 Speed Grade
Min Max
Unit
Min
Max
Min
Max
t
t
t
t
t
t
(1)
2.2
0.0
2.0
1.6
0.0
0.5
2.3
0.0
2.0
1.7
0.0
0.5
2.4
0.0
2.0
–
ns
ns
ns
ns
ns
ns
INSU
(1)
INH
OUTCO
(1)
(2)
4.9
3.0
5.3
3.3
5.8
–
(2)
INSU
(2)
–
INH
–
OUTCO
Table 48. EP20K100E External Bidirectional Timing Parameters
Symbol
-1 Speed Grade
-2 Speed Grade
Min Max
-3 Speed Grade
Min Max
Unit
Min
Max
t
t
t
t
t
t
t
t
t
t
(1)
2.2
0.0
2.0
2.3
0.0
2.0
2.4
0.0
2.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
INSUBIDIR
(1)
INHBIDIR
OUTCOBIDIR
(1)
4.9
5.7
5.7
5.3
6.8
6.8
5.8
8.3
8.3
(1)
(1)
XZBIDIR
ZXBIDIR
(2)
1.8
0.0
0.5
2.5
0.0
0.5
–
–
–
INSUBIDIR
(2)
INHBIDIR
(2)
3.0
3.7
3.7
3.3
4.3
4.3
–
–
–
OUTCOBIDIR
(2)
(2)
XZBIDIR
ZXBIDIR
Notes to tables:
(1) This parameter is measured without using ClockLock or ClockBoost circuits.
(2) This parameter is measured using ClockLock or ClockBoost circuits.
Altera Corporation
81
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
Table 49. EP20K200 External Timing Parameters
Symbol
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Unit
Min
Max
Min
Max
Min
Max
t
t
t
t
t
t
(1)
1.9
0.0
2.0
1.1
0.0
0.5
2.3
0.0
2.0
1.2
0.0
0.5
2.6
0.0
2.0
–
ns
ns
ns
ns
ns
ns
INSU
(1)
INH
OUTCO
(1)
(2)
4.6
2.7
5.6
3.1
6.8
–
(2)
INSU
(2)
–
INH
–
OUTCO
Table 50. EP20K200 External Bidirectional Timing Parameters
Symbol -1 Speed Grade -2 Speed Grade
-3 Speed Grade
Unit
Min
Max
Min
Max
Min
Max
t
t
t
t
t
t
t
t
t
t
(1)
1.9
0.0
2.0
2.3
0.0
2.0
2.6
0.0
2.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
INSUBIDIR
(1)
INHBIDIR
OUTCOBIDIR
(1)
4.6
5.0
5.0
5.6
5.9
5.9
6.8
6.9
6.9
(1)
(1)
XZBIDIR
ZXBIDIR
(2)
1.1
0.0
0.5
1.2
0.0
0.5
–
–
–
INSUBIDIR
(2)
INHBIDIR
(2)
2.7
4.3
4.3
3.1
5.0
5.0
–
–
–
OUTCOBIDIR
(2)
(2)
XZBIDIR
ZXBIDIR
Notes to tables:
(1) This parameter is measured without using ClockLock or ClockBoost circuits.
(2) This parameter is measured using ClockLock or ClockBoost circuits.
82
Altera Corporation
Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
Table 51. EP20K200E External Timing Parameters
Symbol -1 Speed Grade -2 Speed Grade
-3 Speed Grade
Min Max
Unit
Min
Max
Min
Max
t
t
t
t
t
t
(1)
2.3
0.0
2.0
1.9
0.0
0.5
2.4
0.0
2.0
2.0
0.0
0.5
2.5
0.0
2.0
–
ns
ns
ns
ns
ns
ns
INSU
(1)
INH
OUTCO
(1)
(2)
5.1
3.0
5.6
3.3
6.1
–
(2)
INSU
(2)
–
INH
–
OUTCO
Table 52. EP20K200E External Bidirectional Timing Parameters
Symbol -1 Speed Grade -2 Speed Grade
-3 Speed Grade
Unit
Min
Max
Min
Max
Min
Max
t
t
t
t
t
t
t
t
t
t
(1)
2.3
0.0
2.0
2.4
0.0
2.0
2.5
0.0
2.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
INSUBIDIR
(1)
INHBIDIR
OUTCOBIDIR
(1)
5.1
6.0
6.0
5.6
7.3
7.3
6.1
9.2
9.2
(1)
(1)
XZBIDIR
ZXBIDIR
(2)
1.8
0.0
0.5
2.0
0.0
0.5
–
–
–
INSUBIDIR
(2)
INHBIDIR
(2)
3.0
4.1
4.1
3.3
4.5
4.5
–
–
–
OUTCOBIDIR
(2)
(2)
XZBIDIR
ZXBIDIR
Notes to tables:
(1) This parameter is measured without using ClockLock or ClockBoost circuits.
(2) This parameter is measured using ClockLock or ClockBoost circuits.
Altera Corporation
83
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
Table 53. EP20K300E External Timing Parameters
Symbol
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Unit
Min
Max
Min
Max
Min
Max
t
t
t
t
t
t
(1)
2.3
0.0
2.0
1.8
0.0
0.5
2.4
0.0
2.0
1.9
0.0
0.5
2.5
0.0
2.0
–
ns
ns
ns
ns
ns
ns
INSU
(1)
INH
OUTCO
(1)
(2)
5.2
2.8
5.7
3.0
6.2
–
(2)
INSU
(2)
–
INH
–
OUTCO
Table 54. EP20K300E External Bidirectional Timing Parameters
Symbol -1 Speed Grade -2 Speed Grade
-3 Speed Grade
Unit
Min
Max
Min
Max
Min
Max
t
t
t
t
t
t
t
t
t
t
(1)
2.3
0.0
2.0
2.4
0.0
2.0
2.5
0.0
2.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
INSUBIDIR
(1)
INHBIDIR
OUTCOBIDIR
(1)
5.2
6.0
6.0
5.7
7.2
7.2
6.2
9.2
9.2
(1)
(1)
XZBIDIR
ZXBIDIR
(2)
1.8
0.0
0.5
1.9
0.0
0.5
–
–
–
INSUBIDIR
(2)
INHBIDIR
(2)
2.8
3.3
3.3
3.0
4.1
4.1
–
–
–
OUTCOBIDIR
(2)
(2)
XZBIDIR
ZXBIDIR
Notes to tables:
(1) This parameter is measured without using ClockLock or ClockBoost circuits.
(2) This parameter is measured using ClockLock or ClockBoost circuits.
84
Altera Corporation
Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
Table 55. EP20K400 External Timing Parameters
Symbol
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Unit
Min
Max
Min
Max
Min
Max
t
t
t
t
t
t
(1)
1.4
0.0
2.0
0.4
0.0
0.5
1.8
0.0
2.0
1.0
0.0
0.5
2.0
0.0
2.0
–
ns
ns
ns
ns
ns
ns
INSU
(1)
INH
OUTCO
(1)
(2)
4.9
3.1
6.1
4.1
7.0
–
(2)
INSU
(2)
–
INH
–
OUTCO
Table 56. EP20K400 External Bidirectional Timing Parameters
Symbol -1 Speed Grade -2 Speed Grade
-3 Speed Grade
Unit
Min
Max
Min
Max
Min
Max
t
t
t
t
t
t
t
t
t
t
(1)
1.4
0.0
2.0
1.8
0.0
2.0
2.0
0.0
2.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
INSUBIDIR
(1)
INHBIDIR
OUTCOBIDIR
(1)
4.9
7.3
7.3
6.1
8.9
8.9
7.0
10.3
10.3
(1)
(1)
XZBIDIR
ZXBIDIR
(2)
0.5
0.0
0.5
1.0
0.0
0.5
–
–
–
INSUBIDIR
(2)
INHBIDIR
(2)
3.1
6.2
6.2
4.1
7.6
7.6
–
–
–
OUTCOBIDIR
(2)
(2)
XZBIDIR
ZXBIDIR
Notes to tables:
(1) This parameter is measured without using ClockLock or ClockBoost circuits.
(2) This parameter is measured using ClockLock or ClockBoost circuits.
Altera Corporation
85
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
Table 57. EP20K400E External Timing Parameters
Symbol
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Unit
Min
Max
Min
Max
Min
Max
t
t
t
t
t
t
(1)
2.5
0.0
2.0
3.2
0.0
0.5
2.6
0.0
2.0
3.4
0.0
0.5
2.8
0.0
2.0
–
ns
ns
ns
ns
ns
ns
INSU
(1)
INH
OUTCO
(1)
(2)
5.3
2.2
5.8
2.4
6.3
–
(2)
INSU
(2)
–
INH
–
OUTCO
Table 58. EP20K400E External Bidirectional Timing Parameters
Symbol
-1 Speed Grade
Min Max
-2 Speed Grade
Min Max
-3 Speed Grade
Unit
Min
Max
t
t
t
t
t
t
t
t
t
t
(1)
2.5
0.0
2.0
2.6
0.0
2.0
2.8
0.0
2.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
INSUBIDIR
(1)
INHBIDIR
OUTCOBIDIR
(1)
5.3
5.4
5.4
5.8
6.0
6.0
6.3
7.0
7.0
(1)
(1)
XZBIDIR
ZXBIDIR
(2)
3.2
0.0
0.5
3.4
0.0
0.5
–
–
–
INSUBIDIR
(2)
INHBIDIR
(2)
2.2
3.5
3.5
2.4
4.0
4.0
–
–
–
OUTCOBIDIR
(2)
(2)
XZBIDIR
ZXBIDIR
Notes to tables:
(1) This parameter is measured without using ClockLock or ClockBoost circuits.
(2) This parameter is measured using ClockLock or ClockBoost circuits.
86
Altera Corporation
Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
Table 59. EP20K600E External Timing Parameters
Symbol -1 Speed Grade -2 Speed Grade
-3 Speed Grade
Min Max
Unit
Min
Max
Min
Max
t
t
t
t
t
t
(1)
2.6
0.0
2.0
1.9
0.0
0.5
2.7
0.0
2.0
2.0
0.0
0.5
2.9
0.0
2.0
–
ns
ns
ns
ns
ns
ns
INSU
(1)
INH
OUTCO
(1)
(2)
5.5
2.6
6.0
2.9
6.6
–
(2)
INSU
(2)
–
INH
–
OUTCO
Table 60. EP20K600E External Bidirectional Timing Parameters
Symbol
-1 Speed Grade
Min Max
-2 Speed Grade
Min Max
-3 Speed Grade
Min Max
Unit
t
t
t
t
t
t
t
t
t
t
(1)
2.6
0.0
2.0
2.7
0.0
2.0
2.9
0.0
2.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
INSUBIDIR
(1)
INHBIDIR
OUTCOBIDIR
(1)
5.5
6.3
6.3
6.0
7.6
7.6
6.6
9.7
9.7
(1)
(1)
XZBIDIR
ZXBIDIR
(2)
1.9
0.0
0.5
2.0
0.0
0.5
–
–
–
INSUBIDIR
(2)
INHBIDIR
(2)
2.6
3.3
3.3
2.9
4.1
4.1
–
–
–
OUTCOBIDIR
(2)
(2)
XZBIDIR
ZXBIDIR
Notes to tables:
(1) This parameter is measured without using ClockLock or ClockBoost circuits.
(2) This parameter is measured using ClockLock or ClockBoost circuits.
Altera Corporation
87
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
Table 61. EP20K1000E External Timing Parameters
Symbol
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Unit
Min
Max
Min
Max
Min
Max
t
t
t
t
t
t
(1)
2.7
0.0
2.0
1.6
0.0
0.5
2.8
0.0
2.0
1.7
0.0
0.5
3.0
0.0
2.0
–
ns
ns
ns
ns
ns
ns
INSU
(1)
INH
OUTCO
(1)
(2)
5.8
2.3
6.3
2.5
6.9
–
(2)
INSU
(2)
–
INH
–
OUTCO
Table 62. EP20K1000E External Bidirectional Timing Parameters
Symbol
-1 Speed Grade
Min Max
-2 Speed Grade
Min Max
-3 Speed Grade
Unit
Min
Max
t
t
t
t
t
t
t
t
t
t
(1)
2.7
0.0
2.0
2.8
0.0
2.0
3.0
0.0
2.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
INSUBIDIR
(1)
INHBIDIR
OUTCOBIDIR
(1)
5.8
6.6
6.6
6.3
7.9
7.9
6.9
9.7
9.7
(1)
(1)
XZBIDIR
ZXBIDIR
(2)
3.8
0.0
0.5
5.2
0.0
0.5
–
–
–
INSUBIDIR
(2)
INHBIDIR
(2)
2.3
3.3
3.3
2.5
4.1
4.1
–
–
–
OUTCOBIDIR
(2)
(2)
XZBIDIR
ZXBIDIR
Notes to tables:
(1) This parameter is measured without using ClockLock or ClockBoost circuits.
(2) This parameter is measured using ClockLock or ClockBoost circuits. ClockShift was not used in this measurement.
ClockShift can be used to adjust the setup and clock-to-output times to achieve the desired results.
Tables 63 and 64 show selectable I/O standard input and output delays
for APEX 20KE devices. If you select an I/O standard input or output
delay other than LVCMOS, add or subtract the selected speed grade to or
from the LVCMOS value.
88
Altera Corporation
Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
Table 63. Selectable I/O Standard Input Delays
Symbol
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Unit
Min
Min
Max
Min
Max
Min
Max
LVCMOS
0.0
0.0
0.0
0.0
0.0
0.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LVTTL
2.5 V
0.1
0.2
0.2
1.8 V
0.5
0.6
0.8
PCI
0.4
0.5
0.7
GTL+
–0.3
–0.4
–0.4
–0.3
–0.3
–0.2
–0.3
0.0
–0.4
–0.5
–0.5
–0.3
–0.3
–0.3
–0.3
0.1
–0.5
–0.6
–0.6
–0.4
–0.4
–0.4
–0.4
0.1
SSTL-3 Class I
SSTL-3 Class II
SSTL-2 Class I
SSTL-2 Class II
LVDS
CTT
AGP
Table 64. Selectable I/O Standard Output Delays
Symbol -1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Unit
Min
Min
Max
Min
Max
Min
Max
LVCMOS
0.0
0.0
0.0
0.0
0.0
0.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LVTTL
2.5 V
0.5
0.6
0.7
1.8 V
1.7
2.2
2.7
PCI
–0.2
–0.4
–0.1
–0.6
0.0
–0.3
–0.5
–0.2
–0.8
0.0
–0.4
–0.6
–0.2
–1.0
0.0
GTL+
SSTL-3 Class I
SSTL-3 Class II
SSTL-2 Class I
SSTL-2 Class II
LVDS
–0.4
–0.8
–0.2
–0.4
–0.5
–1.0
–0.3
–0.5
–0.6
–1.2
–0.4
–0.7
CTT
AGP
Altera Corporation
89
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
To estimate device power consumption, use the interactive power
estimator on the Altera web site at http://www.altera.com.
Power
Consumption
The APEX 20K architecture supports several configuration schemes. This
section summarizes the device operating modes and available device
configuration schemes.
Configuration &
Operation
Operating Modes
The APEX architecture uses SRAM configuration elements that require
configuration data to be loaded each time the circuit powers up. The
process of physically loading the SRAM data into the device is called
configuration. During initialization, which occurs immediately after
configuration, the device resets registers, enables I/O pins, and begins to
operate as a logic device. The I/O pins are tri-stated during power-up,
and before and during configuration. Together, the configuration and
initialization processes are called command mode; normal device operation
is called user mode.
Before and during device configuration, all I/O pins are pulled to V
by a built-in weak pull-up resistor.
CCIO
SRAM configuration elements allow APEX 20K devices to be
reconfigured in-circuit by loading new configuration data into the device.
Real-time reconfiguration is performed by forcing the device into
command mode with a device pin, loading different configuration data,
reinitializing the device, and resuming user-mode operation. In-field
upgrades can be performed by distributing new configuration files.
Configuration Schemes
The configuration data for an APEX 20K device can be loaded with one of
five configuration schemes (see Table 65), chosen on the basis of the target
application. An EPC2 configuration device, intelligent controller, or the
JTAG port can be used to control the configuration of an APEX 20K
device. When an EPC2 configuration device is used, the system can
configure automatically at system power-up.
90
Altera Corporation
Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
Multiple APEX 20K devices can be configured in any of five configuration
schemes by connecting the configuration enable (nCE) and configuration
enable output (nCEO) pins on each device.
Table 65. Data Sources for Configuration
Configuration Scheme
Data Source
Configuration device
EPC2 configuration device
Passive serial (PS)
MasterBlaster or ByteBlasterMV download cable or serial data source
Parallel data source
Passive parallel asynchronous (PPA)
Passive parallel synchronous (PPS)
JTAG
Parallel data source
MasterBlaster or ByteBlasterMV download cable or a microprocessor
with a Jam or JBC File
For more information on configuration, see Application Note 116
(Configuring APEX 20K, FLEX 10K, & FLEX 6000 Devices.)
f
See the Altera web site (http://www.altera.com) or the Altera Digital
Library for pin-out information.
Device Pin-
Outs
The information contained in the APEX 20K Programmable Logic Device
Family Data Sheet version 3.2 supersedes information published in
previous versions.
Revision
History
Version 3.2 Changes
Version 3.2 of the APEX 20K Programmable Logic Device Family Data Sheet
contains the following change: updated Tables 45, 46, 48, 49, 50, 52, 54, 55,
56, 58, 60, and 62
Version 3.1 Changes
Version 3.1 of the APEX 20K Programmable Logic Device Family Data Sheet
contains the following change: updated Figures 25 and 26.
Altera Corporation
91
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
®
Copyright 2000 Altera Corporation. All rights reserved. AMMP, Altera, APEX, APEX 20K, APEX 20KE,
ClockBoost, ClockLock, ClockShift, EP20K30E, EP20K60E, EP20K100, EP20K100E, EP20K160E, EP20K200,
EP20K200E, EP20K300, EP20K400, EP20K400E, EP20K600E, EP20K1000E, EP20K1500E, FastTrack, FineLine
BGA, MegaCore, MultiCore, MultiVolt, NativeLink, Quartus, SignalTap and Turbo Bit are trademarks and/or
service marks of Altera Corporation in the United States and other countries. Altera acknowledges the
trademarks of other organizations for their respective products or services mentioned in this document. Altera
products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights,
and copyrights. Altera warrants performance of its semiconductor products to current
specifications in accordance with Altera’s standard warranty, but reserves the right to
make changes to any products and services at any time without notice. Altera assumes no
responsibility or liability arising out of the application or use of any information, product,
or service described herein except as expressly agreed to in writing by Altera Corporation.
Altera customers are advised to obtain the latest version of device specifications before
relying on any published information and before placing orders for products or services.
101 Innovation Drive
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(408) 544-7000
http://www.altera.com
Applications Hotline:
(800) 800-EPLD
Customer Marketing:
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Literature Services:
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92
Altera Corporation
Printed on Recycled Paper.
APEX 20K Device Family Overview
484-Pin FineLine BGA
Package
23 x 23
376
376
376
652-Pin BGA
45 x 45
488
488
488
508
488
508
488
808
672-Pin FineLine BGA
Package
27 x 27
1,020-Pin FineLine BGA
Package"F33"
588
708
33 x 33
Table 2. APEX 20KE Device Overview (1.8 V) (part 1 of 2)
Device
EP20K30E EP20K60E EP20K100E EP20K160E EP20K200E
Typical Gates
30,000
122,704
1,200
24,576
2
60,000
161,792
2,560
32,768
2
100,000
262,912
4,160
53,248
2
160,000
404,480
6,400
81,920
2
200,000
525,824
8,320
Maximum System Gates
Logic Elements
Maximum RAM Bits
Phase-Locked Loops (PLLs)
106,496
2
Speed Grades(1)
-3, -2, -1
128
-3, -2, -1
196
-3, -2, -1
246
-3, -2, -1
316
-3, -2, -1
376
Maximum User I/O Pins
Package
mm
Maximum User I/O Pins
144-Pin TQFP
20 x 20 (2)
92
93
92
93
92
93
88
144-Pin FineLine BGA Package
20 x 20
208-Pin PQFP
28 x 28 (2)
125
148
151
143
175
136
168
208-Pin RQFP
28 x 28 (2)
240-Pin PQFP
32 x 32
151
196
151
240-Pin RQFP
32 x 32
324-Pin FineLine BGA Package
19 x 19
128
246
246
356-Pin BGA
35 x 35 (2)
271
316
271
376
376
376
484-Pin FineLine BGA Package
23 x 23
652-Pin BGA
45 x 45
672-Pin FineLine BGA Package
27 x 27
1,020-Pin FineLine BGA Package"F33"
33 x 33
Table 3. APEX 20KE Device Overview (1.8 V) (part 2 of 2)
Device
EP20K300E EP20K400E EP20K600E EP20K1000E EP20K1500E
Typical Gates
300,000
728,064
11,520
400,000
1,051,648
16,640
600,000
1,537,024
24,320
1 million
1,771,520
38,400
1.5 million
2,391,184
51,840
Maximum System Gates
Logic Elements
http://www.altera.com/products/devices/apex/apx-overview.html (2 of 4) [3/21/2001 5:18:41 PM]
APEX 20K Device Family Overview
Maximum RAM Bits
147,456
4
212,992
4
311,296
4
327,680
4
442,368
4
Phase-Locked Loops (PLLs)
Speed Grades (1)
-3, -2, -1
408
-3, -2, -1
488
-3, -2, -1
588
-3, -2, -1
708
-3, -2, -1
808
Maximum User I/O Pins
Package
Maximum User I/O Pins
144-Pin TQFP
20 x 20 (2)
144-Pin FineLine BGA Package
20 x 20
208-Pin PQFP
28 x 28 (2)
208-Pin RQFP
28 x 28 (2)
240-Pin PQFP
32 x 32
152
240-Pin RQFP
32 x 32
324-Pin FineLine BGA Package
19 x 19
356-Pin BGA
35 x 35 (2)
484-Pin FineLine BGA Package
23 x 23
652-Pin BGA
45 x 45
408
408
488
488
488
508
588
488
488
808
672-Pin FineLine BGA Package
27 x 27
508
708
1,020-Pin FineLine BGA Package"F33"
33 x 33
Table 4. APEX 20K Device Overview (2.5 Volt)
Device
EP20K100 EP20K200 EP20K400
Maximum System Gates
Logic Elements
263,000
4,160
53,248
1
526,000
8,320
1,052,000
16,640
212,992
1
Maximum RAM bits
Phase-Locked Loops (PLLs)
Speed Grade (1)
106,496
1
-3, -2, -1
-3, -2, -1
-3, -2, -1
Maximum User I/O Pins
252
382
502
Package
mm
Maximum User I/O Pins
101
144-Pin TQFP
20 x 20
144-Pin FineLine BGA
106
159
208-Pin PQFP
28 x 28
144
174
240-Pin PQFP
28 x 28
189
252
252
324-Pin FineLine BGA Package
19 x 19
356-Pin BGA
35 x 35
277
http://www.altera.com/products/devices/apex/apx-overview.html (3 of 4) [3/21/2001 5:18:41 PM]
APEX 20K Device Family Overview
484-Pin FineLine BGA Package
382
23 x 23
652-Pin BGA
45 x 45
502
502
672-Pin FineLine BGA Package
27 x 27
Contact Us
support@altera.com
webmaster@altera.com
Give Us Feedback
Notes to Tables:
1. For APEX 20KC devices, -7 is the fastest speed grade; for APEX 20K and APEX 20KE devices -1 is the fastest
speed grade.
2. TQFP: thin quad flat pack, PQFP: plastic quad flat pack, RQFP: power quad flat pack, BGA: ball-grid array
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EP20K100
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EP20K300EFC672-3
EP20K300EFC672-2
EP20K300EFC672-2X
EP20K300EFI672-2x
X
X
C
C
C
FineLine 672
BGA
-3
-2
X
x
I
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-1
C
EP20K300EFC672-1
EP20K300EFC672-1X
EP20K300EFC672XES
EP20K300EQC240-3
EP20K300EQC240-2
EP20K300EQC240-2X
EP20K300EQC240-1
EP20K300EQC240-1X
EP20K300EQC240XES
EP20K30EFC144-3
EP20K30EFC144-2
EP20K30EFC144-2X
EP20K30EFI144-2X
EP20K30EFC144-1
EP20K30EFC144-1X
EP20K30EFC324-3
EP20K30EFC324-2
EP20K30EFC324-2X
EP20K30EFC324-1X
EP20K30EQC208-3
EP20K30EQC208-2
EP20K30EQC208-2X
EP20K30EQC208-1
EP20K30EQC208-1X
EP20K30ETC144-3
EP20K30ETC144-2
X
C
C
C
PQFP
240
-3
-2
X
X
-1
C
C
C
C
EP20K30E
FineLine 144
BGA
-3
-2
X
X
I
-1
C
X
324
-3
-2
C
C
X
X
-1
-3
-2
C
C
C
PQFP
208
X
X
-1
C
TQFP
144
-3
-2
C
C
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EP20K30ETC144-2X
EP20K30ETC144-1
EP20K30ETC144-1X
EP20K400BC652-3
EP20K400BC652-2X
EP20K400BI652-2
EP20K400BC652-1
EP20K400BC652-1X
EP20K400BC652-3V
EP20K400BC652-2XV
EP20K400FC672-3
EP20K400FC672-2
EP20K400FC672-2X
EP20K400FI672-2
X
X
X
-1
C
EP20K400
BGA
652
-3
-2
C
C
I
-1
C
X
V
C
XV
FineLine 672
BGA
-3
-2
C
C
X
V
I
EP20K400FI672-2V
EP20K400FC672-1
EP20K400FC672-1X
EP20K400FC672-3V
EP20K400FC672-2XV
EP20K400GC655-3
EP20K400GC655-2
EP20K400GC655-1
EP20K400EBC652-3
EP20K400EBC652-2
EP20K400EBC652-2X
EP20K400EBI652-2X
-1
C
C
X
V
XV
PGA
BGA
655
652
-3
-2
-1
-3
-2
C
C
C
C
C
EP20K400E
X
X
I
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-1
-2
C
C
EP20K400EBC652-1
EP20K400EBC652-1X
EP20K400EFC672-2
EP20K400EFC672-2X
EP20K400EFI672-2X
EP20K400EFC672-1
EP20K400EFC672-1X
EP20K600EBC652-3
EP20K600EBC652-2
EP20K600EBC652-2X
EP20K600EBC652-1
EP20K600EBC652-1X
EP20K600EBC652XES
EP20K600EFC33-3
X
FineLine 672
BGA
X
X
I
-1
C
X
EP20K600E
BGA
652
-3
-2
C
C
X
X
-1
C
C
C
C
FineLine
BGA
33
-3
-2
EP20K600EFC33-2
EP20K600EFC33-2X
EP20K600EFC33-1
X
-1
C
EP20K600EFC33-1X
EP20K600EFC33-2X-2
EP20K600EFC672-3
EP20K600EFC672-2
EP20K600EFC672-2X
EP20K600EFC672-1
EP20K600EFC672-1X
EP20K600EFC672XES
EP20K60EBC324-1X
X
C
C
C
X-2
672
-3
-2
X
X
X
-1
-1
C
C
C
EP20K60E
BGA
324
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356
-3
-2
C
C
EP20K60EBC356-3
EP20K60EBC356-2
EP20K60EBC356-2X
EP20K60EBC356-1
EP20K60EBC356-1X
EP20K60EFC144-3
EP20K60EFC144-2
EP20K60EFC144-2X
EP20K60EFC144-1
EP20K60EFC144-1X
EP20K60EFC324-3
EP20K60EFC324-2
EP20K60EFC324-1
EP20K60EFC324-2X
EP20K60EQC208-3
EP20K60EQC208-2
EP20K60EQC208-2X
EP20K60EQC208-1
EP20K60EQC208-1X
EP20K60EQC240-3
EP20K60EQC240-2
EP20K60EQC240-2X
EP20K60EQC240-1
EP20K60EQC240-1X
EP20K60ETC144-3
EP20K60ETC144-2
X
X
-1
C
FineLine 144
BGA
-3
-2
C
C
X
X
-1
C
324
-3
-2
-1
C
C
C
C
C
C
X
PQFP
208
240
144
-3
-2
X
X
-1
C
-3
-2
C
C
X
X
-1
C
C
C
C
TQFP
-3
-2
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-1
C
C
EP20K60ETC144-1
EP20K60ETC144-2X
EP20K60ETC144-1X-1
X
X-1
Note:
1. For an explanation of Altera ordering codes, refer to Product Ordering Codes .
2. C: device is shipped in a carrier. DX or X: device has the ClockLock and ClockBoost
features. F: device supports fixed programming algorithms for in-circuit testers. P: device is
PCI-compliant.
Enter a new search below:
Choose a device family: Choose a package:
✔
ACEX 1K
Any available package
APEX 20K
FLEX 10K
Ceramic dual in-line package (CerDIP)
Plastic dual in-line package (PDIP)
Plastic small-outline integrated circuit (SOIC)
Ceramic J-lead chip carrier (JLCC)
Plastic J-lead chip carrier (PLCC)
Thin plastic quad flat pack (TQFP)
Plastic quad flat pack (PQFP)
Power quad flat pack (RQFP)
Ceramic quad flat pack (CQFP)
Ceramic pin-grid array (PGA)
Ball-grid array (BGA)
FLEX 8000
FLEX 6000
MAX 9000
MAX 7000
MAX 3000A
Classic
Configuration EPROM
FineLine BGA
You can type options in the box below (e.g., speed grade)
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Last updated: November 28, 2000
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