EP324PC-30 [ALTERA]
OT PLD, 30ns, PAL-Type, CMOS, PDIP40, PLASTIC, DIP-40;
| 型号： | EP324PC-30 |
| 厂家： | 
ALTERA CORPORATION |
| 描述： | OT PLD, 30ns, PAL-Type, CMOS, PDIP40, PLASTIC, DIP-40 时钟 输入元件 光电二极管 可编程逻辑 |
| 文件： | 总18页 (文件大小：329K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EP312 & EP324
Classic EPLDs
®
April 1995, ver. 1
Data Sheet
■
High-performance EPLDs with 12 macrocells (EP312) or 24
macrocells (EP324)
Features
–
–
–
Combinatorial speeds as fast as 25 ns
Counter frequencies of up to 33.3 MHz
Pipelined data rates of up to 66 MHz
■
■
Multiple 20-pin PAL and GAL replacement and integration
Device erasure and reprogramming with advanced, nonvolatile
EPROM configuration elements
■
■
■
Programmable registers providing D, T, JK, and SR flipflops with
individual Clear and Clock controls
Dual feedback on all macrocells for implementing buried registers
with bidirectional I/O
Programmable-AND/allocatable-ORstructure allowing up to 16
product terms per macrocell
■
■
Two product terms on all macrocell control signals
Programmable inputs (8 in EP312, 10 in EP324) configurable as
latches, registers, or flow-through input
■
Available in windowed ceramic and one-time-programmable (OTP)
plastic packages with 24 to 44 pins:
–
24-pin ceramic and plastic dual in-line package (CerDIP and
PDIP)
–
–
–
28-pin plastic J-lead chip carrier (PLCC)
40-pin CerDIP and PDIP
44-pin PLCC
■
One global Clock pin; one global Input Latch Enable/Input
Clock/Input (ILE/ICLK/INPUT) pin
■
■
■
■
Programmable “standby” option for low-power operation
Programmable Security Bit for total protection of proprietary designs
100% generically testable to provide 100% programming yield
Software design support with the Altera PLDshell Plus software and
a wide range of third-party tools; programming support through
third-party vendors
The CMOS EPROM EP312 and EP324 devices have a versatile macrocell
structure and I/O architecture, which allow them to implement high-
performance logic functions effectively. The EP312 and EP324 input and
macrocell features are a superset of features offered by PAL/GAL
devices. Therefore, EP312 and EP324 devices can be used as an alternative
to multiple PAL/GAL devices, SSI and MSI logic devices, or low-end gate
arrays.
General
Description
Altera Corporation
1
A-DS-312/324.01
EP312 & EP324 Classic EPLDs
EP312 and EP324 devices operate in high-performance systems with
low power consumption. The programmable standby function
provides “zero” power consumption for applications where
performance can be traded for power savings.
The EP312 and EP324 architecture is based on a sum-of-products
programmable-AND/allocatable-ORstructure. EP312 and EP324
devices can implement combinatorial and sequential logic functions,
as well as combinatorial-register and register-combinatorial-register
logic forms, to easily accommodate state machine designs.
Functional
Description
Figure 1 and Figure 2 show block diagrams of the EP312 and EP324
architectures. The EP312 device contains 12 I/O macrocells and 8
programmable input structures; the EP324 device contains 24 I/O
macrocells and 10 programmable input structures. EP312 and EP324
macrocells are divided into 2 rings for product-term allocation. Both
devices have 2 additional inputs that can be programmed either as
combinatorial inputs or Clock inputs. Each input structure can be
individually configured as a latch, register, or flow-through input.
Input latches and registers can be clocked synchronously or
asynchronously.
Figure 1. EP312 Block Diagram
Global Clock
Clock/Input 1
Input/Register/Latch
1
2
3
4
5
6
Macrocell 1
Macrocell 2
Macrocell 3
Macrocell 4
Macrocell 5
Macrocell 6
Input 1
Input 2
Input 3
Input 4
Input 5
Input 6
Input 7
Input 8
Ring 1
Global
Bus
Global Clock
7
Macrocell 7
Macrocell 8
Macrocell 9
Macrocell 10
Macrocell 11
Macrocell 12
8
9
Ring 2
10
11
12
Input Latch
Enable/Input
Clock/Input 2
2
Altera Corporation
EP312 & EP324 Classic EPLDs
Figure 2. EP324 Block Diagram
Input/Register/Latch
Global Clock
Clock/Input 1
1
Macrocell 1
Input 1
Input 2
Input 3
Input 4
Input 5
Input 6
Input 7
Input 8
Input 9
Input 10
2
Macrocell 2
Macrocell 3
Macrocell 4
Macrocell 5
Macrocell 6
Macrocell 7
Macrocell 8
Macrocell 9
Macrocell 10
Macrocell 11
Macrocell 12
3
4
5
6
Ring 1
7
8
9
10
11
12
Global
Bus
Global Clock
13
14
15
16
17
18
19
20
21
22
23
24
Macrocell 13
Macrocell 14
Macrocell 15
Macrocell 16
Macrocell 17
Macrocell 18
Macrocell 19
Macrocell 20
Macrocell 21
Macrocell 22
Macrocell 23
Macrocell 24
Ring 2
Input Latch
Enable/Input
Clock/Input 2
The EP312 and EP324 architectures include the following features:
■
■
■
■
Macrocells
Product-term allocation
Programmable inputs
Power-on characteristics
Macrocells
Each EP312 and EP324 macrocell contains 16 product terms (see Figure 3).
Half of the product terms are available to support logic functions; half are
dedicated to the macrocell control signals. The inputs to the ANDarray
originate from the true and complement signals of the programmable
input structure, the dedicated inputs, and the 2 feedback paths from each
I/O macrocell to the global bus.
Altera Corporation
3
EP312 & EP324 Classic EPLDs
Figure 3. EP312 & EP324 Macrocell
to
from
Previous
Logic Array
Lower Half
Global
Clock
Previous
Macrocell Macrocell
Product Terms 1 to 4
Output Enable
Output
Multiplexer
PRN
D/T
4
Allocation
Control
Q
CLR
4
Invert
Control
Upper Half
Product Terms 1 to 4
Programmable
Register
ILE/ICLK
Clock
Multiplexer
to Next
from Next
Macrocell Macrocell
The eight product terms available for implementing logic functions are
divided into two equal groups, and can be used in other macrocells. Each
macrocell provides a dual feedback to the logic array.
The eight product terms for control functions support the following four
control signals, with two product terms each: Output Enable (OE), Preset,
Clear, and asynchronous Clock. When the global Clock (CLK) signal
synchronously clocks a macrocell register, it cannot function as an input
to the logic array. However, the global Clock can simultaneously function
as an input to the logic array and as an asynchronous, non-global Clock.
4
Altera Corporation
EP312 & EP324 Classic EPLDs
To implement registered functions, each macrocell register can be
individually programmed for D, T, JK, or SR operation. If necessary, the
register can be bypassed for combinatorial operation. The XORgate can
implement active-high or active-low logic, or use DeMorgan’s inversion
to reduce the number of product terms required to implement a function.
Registers are cleared automatically during power-up.
The macrocell output can be fed back to the logic array via two paths. Pin
feedback that is connected after the output buffer can be used to
implement bidirectional I/O; if internal feedback is used for a buried
register or logic function, the pin feedback can be used as an input.
Product-Term Allocation
In EP312 and EP324 devices, product-term resources can be taken from
one macrocell and used in another. For product-term allocation,
macrocells in both the EP312 and EP324 are divided into 2 rings. The
EP312 has 6 macrocells per ring; the EP324 has 12 macrocells per ring.
Product terms from one macrocell can be allocated to adjacent macrocells
in the same ring. Product terms are allocated in groups of 4, and a
macrocell can borrow up to 8 product terms (4 from each adjacent
macrocell).
Table 1 and Table 2 show the product-term allocation rings for the EP312
and EP324 devices, respectively. The Altera PLDshell Plus design
software automatically allocates product terms.
Altera Corporation
5
EP312 & EP324 Classic EPLDs
Table 1. EP312 Product-Term Allocation Rings
Ring 1
Ring 2
Next
Current
Next
Previous
Current
Previous
Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell
1
2
3
4
5
6
2
3
4
5
6
1
6
1
2
3
4
5
7
8
8
9
12
7
9
10
11
12
7
8
10
11
12
9
10
11
Table 2. EP324 Product-Term Allocation Rings
Ring 1
Ring 2
Next
Current
Next
Previous
Current
Previous
Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell
1
2
7
1
2
3
13
14
15
16
17
18
19
20
21
22
23
24
19
13
14
15
16
17
20
21
22
23
24
18
14
15
16
17
18
24
13
19
20
21
22
23
3
2
4
4
3
5
5
4
6
6
5
12
1
7
8
8
9
7
9
10
11
12
6
8
10
11
12
9
10
11
Programmable Inputs
Figure 4 shows a block diagram of the EP312 and EP324 input structure.
The user-programmable inputs can be individually configured to operate
in the following modes:
■
■
■
■
■
Input D register, synchronously clocked
Input D register, asynchronously clocked
Input D latch, synchronously clocked
Input D latch, asynchronously clocked
Flow-through input
6
Altera Corporation
EP312 & EP324 Classic EPLDs
Figure 4. EP312 & EP324 Input Structure
Product Term
from Logic Array
to Logic Array
INPUT
D
Q
ILE/ICLK/INPUT
Latch/Register
Select
Synchronous/
Asynchronous
Select
The ILE/ICLK/INPUTpin is a dedicated input to the logic array. For
synchronous operation, the ILE/ICLK/INPUTpin becomes a global
ILE/ICLKinput to all latch/register/input structures; for asynchronous
operation, a separate product term in the logic array is used to derive the
ILE/ICLKsignal for each input structure. Because the Clock signal for
each programmable input can be selected individually, a combination of
asynchronously and synchronously clocked inputs is available. Flow-
through operation occurs when the ILEproduct term is tied to V . Data
CC
is latched or clocked on the falling edge of ILE/ICLKin synchronous
mode.
Power-On Characteristics
EP312 and EP324 inputs and outputs respond between 6 µs and 10 µs after
power-up, or after a power-loss/power-up sequence. All macrocells
programmed as registers are set to a logic low on power-up. Input
registers are not reset on power-up and their values are indeterminate.
Input latches reflect the state of the input pins on power-up.
EP312 and EP324 devices contain a programmable Security Bit that
controls access to the data programmed into the device. When this bit is
programmed, a proprietary design implemented in the device cannot be
copied or retrieved. This feature provides a high level of design security,
since programmed data within EPROM configuration elements is
invisible. The Security Bit that controls this function, as well as all other
program data, is reset when a device is erased.
Design Security
Turbo Bit
EP312 and EP324 devices contain a programmable Turbo Bit that controls
the automatic power-down feature, which enables the low-standby-
power mode (ICC1). When the Turbo Bit is turned on, the low-standby-
power mode is disabled. All AC parameters are tested with the Turbo Bit
turned on. When the device is operating with the Turbo Bit turned off
(non-turbo mode), a non-turbo adder must be added to the appropriate
AC parameter to determine worst-case timing. The non-turbo adder is
specified in the “AC Operating Conditions” tables in this data sheet.
Altera Corporation
7
EP312 & EP324 Classic EPLDs
EP312 and EP324 devices are fully functionally tested and guaranteed.
Generic Testing
Complete testing of each programmable EPROM configuration element
and all internal logic elements ensures 100% programming yield. AC test
measurements are taken under conditions equivalent to those shown in
Figure 5.
Figure 5. EP312 & EP324 AC Test Circuits
Power-supply transients can affect AC
measurements. Simultaneous transitions
of multiple outputs should be avoided for
accurate measurement. Threshold tests
must not be performed under AC
conditions. Large-amplitude, fast ground-
current transients normally occur as the
device outputs discharge the load
capacitances. When these transients flow
through the parasitic inductance between
the device ground pin and the test-system
ground, significant reductions in
VCC
460 Ω
238 Ω
Device
Output
To Test
System
C1 (includes
JIG capacitance)
observable noise immunity can result.
Test programs are used and then erased during the early stages of a device
production flow. EPROM-based devices in one-time-programmable
packages also contain on-board logic test circuitry to allow verification of
function and AC specifications during production flow.
The EP312 and EP324 are supported by the Altera PLDshell Plus design
software and other industry-standard logic compilers (e.g., ABEL, CUPL,
PLDesigner, LOG/IC, and iPLS II). The EP312 and EP324 are supported
by third-party programming hardware.
Software &
Programming
Support
For more information on software support with PLDshell Plus, go to the
PLDshell Plus/PLDasm User’s Guide, which is available from the Altera
Literature Department; refer to the Programming Hardware Manufacturers
Data Sheet in the Altera Data Book for more information on third-party
programming hardware support.
f
8
Altera Corporation
EP312 & EP324 Classic EPLDs
Figure 6 shows the typical supply current (I ) versus frequency for
CC
EP312 and EP324 devices.
Figure 6. EP312 & EP324 I vs. Frequency
CC
EP312 EPLDs
EP324 EPLDs
120
240
100
200
Turbo
Turbo
80
60
40
20
160
120
80
VCC = 5.0 V
TA = 25° C
VCC = 5.0 V
TA = 25° C
Non-Turbo
Non-Turbo
40
10
20
30
40
10
20
30
40
Frequency (MHz)
Frequency (MHz)
Altera Corporation
9
EP312 & EP324 Classic EPLDs
Figure 7 shows the maximum output drive characteristics of EP312 and
EP324 I/O pins.
Figure 7. EP312 & EP324 Output Drive Characteristics
EP312 & EP324 EPLDs
50
40
IOL
30
VCC = 5.0 V
TA = 25° C
20
10
IOH
1
2
3
4
5
VO Output Voltage (V)
10
Altera Corporation
EP312 & EP324 Classic EPLDs
Absolute Maximum Ratings
Note (1)
Symbol Parameter
Conditions
Min
Max
Unit
VCC
Supply voltage
Note (2)
–2.0
–0.5
–65
–10
7.0
VCC + 0.5
150
V
V
VI
DC input voltage
Storage temperature
Ambient temperature
Notes (2), (3)
Note (4)
TSTG
TAMB
° C
° C
85
Recommended Operating Conditions
Symbol Parameter
Conditions
Min
Max
Unit
VCC
Supply voltage
Input voltage
Output voltage
4.75
0
5.25
VCC
VCC
70
V
V
VIN
VO
TA
TA
tR
0
V
Operating temperature
Operating temperature
Input rise time
For commercial use
For industrial use
0
° C
° C
ns
ns
–40
85
500
500
tF
Input fall time
DC Operating Conditions
Symbol
Note (5)
Parameter
Conditions
Min
Max
Unit
VIH
VIL
VOH
VOH
VOL
II
High-level input voltage
Low-level input voltage
Note (2)
2.0
–0.3
2.4
VCC + 0.3
0.8
V
V
Note (2)
High-level TTL output voltage
High-level CMOS output voltage
Low-level output voltage
IOH = –4.0 mA DC, VCC = min.
IOH = –2 mA DC, VCC = min.
IOL = 8 mA DC, VCC = min.
VCC = max., GND < VIN < VCC
VCC = max., GND < VOUT < VCC
VCC = max., VOUT = 0.5 V, Note (6)
V
3.84
V
0.45
10
V
Input leakage current
µA
µA
mA
IOZ
ISC
Tri-state output leakage current
Output short-circuit current
10
–30
–90
Capacitance
Symbol
Note (5)
Parameter
Conditions
Min
Max
Unit
CIN
Input capacitance
VIN = 0 V, f = 1.0 MHz
VOUT = 0 V, f = 1.0 MHz
VOUT = 0 V, f = 1.0 MHz
VOUT = 0 V, f = 1.0 MHz
Note (7), f = 1.0 MHz
8
15
12
15
25
pF
pF
pF
pF
pF
COUT
CCLK
CCLK
CVPP
I/O capacitance
EP312 ILE/ICLK/INPUTpin capacitance
EP324 ILE/ICLK/INPUTpin capacitance
VPP pin capacitance
Altera Corporation
11
EP312 & EP324 Classic EPLDs
I
Supply Current
Note (5)
CC
EP312
EP324
Symbol
Parameter
Conditions
Min Typ Max Min Typ Max Unit
ICC1
Standby current
VCC = max., VIN = VCC or GND, standby
mode, Note (8), (9)
100 300
150
500
µA
ICC3
VCC supply current VCC = max., VIN = VCC or GND, no load,
fIN = 1 MHz, Note (9)
10
20
mA
Notes to tables:
(1) See Operating Requirements for Altera Devices in the current Altera Data Book.
(2) Voltage with respect to ground; all over- and undershoots due to system or tester noise are included.
(3) Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to 7.0 V for
periods of less than 20 ns under no-load conditions.
(4) Under bias. Extended temperature versions are also available.
(5) Operating conditions: VCC = 5 V ± 5%, TA = 0° C to 70° C for commercial use.
V
CC = 5 V ± 10%, TA = –40° C to 80° C for industrial use.
(6) Test one output at a time; test duration should not exceed one second.
(7) For EP312 devices:
DIP packages, VPP is on pin 1
PLCC packages, VPP is on pin 2
For EP324 devices: DIP packages, VPP is on pin 18
PLCC packages, VPP is on pin 20
(8) When the Turbo Bit is not set (non-turbo mode), an EP312 or EP324 device enters standby mode if no logic
transitions occur for 100 ns after the last transition.
(9) For EP312 devices: parameter measured with device configured as one 12-bit counter.
For EP324 devices: parameter measured with device configured as two 12-bit counters.
12
Altera Corporation
EP312 & EP324 Classic EPLDs
AC Operating Conditions: EP312
Combinatorial Mode
Note (1)
EP312-25
EP312-30
Non-Turbo
Adder
Symbol
Parameter
Conditions
Min Max Min Max
Note (2)
Units
tPD1
Input to non-registered output
I/O to non-registered output
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 5 pF
25
25
25
25
25
25
30
30
30
30
30
30
20
20
20
20
20
20
ns
ns
ns
ns
ns
ns
tPD2
tPZX
Input or I/O to output enable, Note (3)
Input or I/O to output disable, Note (3)
Input or I/O to asynchronous reset
Input or I/O to asynchronous set
tPXZ
tPCLR
tPSET
C1 = 35 pF
C1 = 35 pF
EP312-25
EP312-30
Non-Turbo
Adder
Synchronous Clock Mode (Macrocells)
Symbol
Parameter
Min Max Min Max
Note (2)
Units
fMAX
fCNT1
fCNT2
tSU1
tSU1
tH
Maximum frequency (pipelined), no feedback
Maximum counter frequency, external feedback
Maximum counter frequency, internal feedback
Input or I/O setup time to global clock
Input or I/O setup time to global clock
Input or I/O hold time from global clock
Global clock to output delay
66
33.3
33.3
15
50
26.3
28.5
20
MHz
MHz
MHz
ns
20
20
0
15
20
ns
0
0
ns
tCO
15
30
18
35
0
ns
tCNT
tCL
Minimum global clock period
20
0
ns
Clock low time
7
7
9
9
ns
tCH
Clock high time
0
ns
tCP
Clock period
15
20
0
ns
EP312-25
EP312-30
Non-Turbo
Adder
Synchronous Clock (Input Structure)
Symbol
Parameter
Min Max Min Max
Note (2)
Units
fMAXI
tSUIR
tESUI
tCOI
tEOI
tHI
Maximum frequency input structure
Input register/latch setup time to ILE/ICLK
Input latch setup time to ILE, Note (4)
ICLKto combinatorial output
ILEup to combinatorial output
Input hold after falling edge of ILE/ICLK
Input hold after falling edge of ILE
ILE/ICLKhigh time
66
5
50
5
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
0
5
5
35
35
40
40
20
20
0
7
7
10
10
9
tEHI
tCHI
tCLI
0
7
0
ILE/ICLKlow time
7
9
0
tCPI
Minimum ICLKperiod
15
20
0
Altera Corporation
13
EP312 & EP324 Classic EPLDs
EP312-25
EP312-30
Non-Turbo
Adder
Asynchronous Clock Mode (Macrocells)
Symbol
Parameter
Min Max Min Max
Note (2)
Units
fAMAX
fACNT1
fACNT2
tASU1
tASU1
tAH
Maximum frequency (pipelined), no feedback
Maximum counter frequency, external feedback
Maximum counter frequency, internal feedback
Input or I/O setup time to asynchronous clock
Input or I/O setup time to asynchronous clock
Input or I/O hold time from asynchronous clock
Asynchronous clock to output delay
66
28.5
33.3
10
50
23.8
30
MHz
MHz
MHz
ns
12
20
20
0
10
12
ns
5
5
ns
tACO
25
30
30
35
20
20
20
20
20
ns
tACNT
tACL
Minimum global clock period
ns
Asynchronous clock low time
7
7
9
9
ns
tACH
Asynchronous clock high time
ns
tACP
Minimum asynchronous clock period
15
20
ns
EP312-25
EP312-30
Non-Turbo
Adder
Asynchronous Clock (Input Structure)
Symbol
Parameter
Min Max Min Max
Note (2)
Units
fAMAXI
tASUIR
tAESUI
tACOI
tAEOI
tAHI
Maximum frequency input structure
66
0
50
0
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
Input register/latch setup time to asynchronous ILE/ICLK
Input latch setup time to asynchronous ILE, Note (4)
Asynchronous ICLKto combinatorial output
Asynchronous ILEup to combinatorial output
Input hold after falling edge of asynchronous ILE/ICLK
Input hold after falling edge of asynchronous ILE
Asynchronous ILE/ICLKhigh time
0
0
0
0
48
48
55
55
20
20
20
0
20
20
7
25
25
9
tAEHI
tACHI
tACLI
tACPI
20
20
20
Asynchronous ILE/ICLKlow time
7
9
Minimum ICLKperiod
15
20
EP312-25
EP312-30
Non-Turbo
Adder
Input Clock to Macrocell Clock
Symbol
Parameter
Min Max Min Max
Note (2)
Units
tC1C2
tC1C2
tC1C2
tC1C2
Synchronous ILE/ICLKto synchronous macrocell CLK
Synchronous ILE/ICLKto asynchronous macrocell CLK
Asynchronous ILE/ICLKto synchronous macrocell CLK
Asynchronous ILE/ICLKto asynchronous macrocell CLK
25
15
35
25
30
18
40
35
20
20
20
20
ns
ns
ns
ns
Notes to tables:
(1) Operating conditions: VCC = 5 V ± 5%, TA = 0° C to 70° C for commercial use.
CC = 5 V ± 10%, TA = –40° C to 85° C for industrial use.
(2) If the device is operating in standby mode, increase the time by the amount shown.
V
(3) The tPZX and tPXZ parameters are measured at ±0.5 V from steady-state voltage that is driven by the specified output
load.
(4) This specification must be met to guarantee tEOI. If ILEgoes high before data is valid, use tPD instead of tEOI
.
14 Altera Corporation
EP312 & EP324 Classic EPLDs
AC Operating Conditions: EP324
Combinatorial Mode
Note (1)
EP324-25
EP324-30 Non-Turbo Adder
Symbol
Parameter
Conditions Min Max Min Max
Note (2)
Units
tPD1
Input to non-registered output
I/O to non-registered output,
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 5 pF
25
25
25
25
25
25
30
30
30
30
30
30
20
20
20
20
20
20
ns
ns
ns
ns
ns
ns
tPD2
tPZX
Input or I/O to output enable, Note (3)
Input or I/O to output disable, Note (3)
Input or I/O to asynchronous reset
Input or I/O to asynchronous set
tPXZ
tPCLR
tPSET
C1 = 35 pF
C1 = 35 pF
EP324-25
EP324-30 Non-Turbo Adder
Synchronous Clock Mode (Macrocells)
Symbol
Parameter
Min Max Min Max
Note (2)
Units
fMAX
fCNT1
fCNT2
tSU1
tSU1
tH
Maximum frequency (pipelined), no feedback
Maximum counter frequency, external feedback
Maximum counter frequency, internal feedback
Input or I/O setup time to global clock
Input or I/O setup time to global clock
Input or I/O hold time from global clock
Global clock to output delay
66
33.3
33.3
12.5
12
50
25
MHz
MHz
MHz
ns
28.5
20
20
20
0
20
ns
0
0
ns
tCO
17.8
30
20
35
0
ns
tCNT
tCL
Minimum global clock period
20
0
ns
Clock low time
7
7
9
9
ns
tCH
Clock high time
0
ns
tCP
Clock period
15
20
0
ns
EP324-25
EP324-30 Non-Turbo Adder
Synchronous Clock Mode (Input Structure)
Symbol
Parameter
Min Max Min Max
Note (2)
Units
fMAXI
tSUIR
tESUI
tCOI
tEOI
tHI
Maximum frequency input structure
Input register/latch setup time to ILE/ICLK
Input latch setup time to ILE, Note (4)
ICLKto combinatorial output
ILEup to combinatorial output
Input hold after falling edge of ILE/ICLK
Input hold after falling edge of ILE
ILE/ICLKhigh time
66
1
50
2.5
2.5
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
0
1
30
30
35
35
20
20
0
8
7
9
8
tEHI
tCHI
tCLI
0
7
9
0
ILE/ICLKlow time
7
9
0
tCPI
Minimum ICLKperiod
15
20
0
Altera Corporation
15
EP312 & EP324 Classic EPLDs
EP324-25
EP324-30
Non-Turbo
Adder
Asynchronous Clock Mode (Macrocells)
Symbol
Parameter
Min Max Min Max
Note (2)
Units
fAMAX
fACNT1
fACNT2
tASU1
tASU1
tAH
Maximum frequency (pipelined), no feedback
Maximum counter frequency, external feedback
Maximum counter frequency, internal feedback
Input or I/O setup time to asynchronous clock
Input or I/O setup time to asynchronous clock
Input or I/O hold time from asynchronous clock
Asynchronous clock to output delay
66
27.7
33.3
11
50
23.8
28.5
12
MHz
MHz
MHz
ns
20
20
0
11
12
ns
3
4
ns
tACO
25
30
30
35
20
20
20
20
20
ns
tACNT
tACL
Minimum global clock period
ns
Asynchronous clock low time
7
7
9
9
ns
tACH
Asynchronous clock high time
ns
tACP
Minimum asynchronous clock period
15
20
ns
EP324-25
EP324-30
Non-Turbo
Adder
Asynchronous Clock Mode (Input Structure)
Symbol
Parameter
Min Max Min Max
Note (2)
Units
fAMAXI
tASUIR
tAESUI
tACOI
tAEOI
tAHI
Maximum frequency input structure
66
50
–5
–5
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
Input register/latch setup time to asynchronous ILE/ICLK –5
0
Input latch setup time to asynchronous ILE, Note (4)
Asynchronous ICLKto combinatorial output
Asynchronous ILEup to combinatorial output
Input hold after falling edge of asynchronous ILE/ICLK
Input hold after falling edge of asynchronous ILE
Asynchronous ILE/ICLKhigh time
–5
0
30
30
35
45
20
20
20
0
15
14
7
18
17
9
tAEHI
tACHI
tACLI
tACPI
20
20
20
Asynchronous ILE/ICLKlow time
7
9
Minimum ICLKperiod
15
20
EP324-25
EP324-30
Non-Turbo
Adder
Input Clock to Macrocell Clock
Symbol
Parameter
Min Max Min Max
Note (2)
Units
tC1C2
tC1C2
tC1C2
tC1C2
Synchronous ILE/ICLKto synchronous macrocell CLK
Synchronous ILE/ICLKto asynchronous macrocell CLK
Asynchronous ILE/ICLKto synchronous macrocell CLK
Asynchronous ILE/ICLKto asynchronous macrocell CLK
20
12.5
40
25
15
45
25
20
20
20
20
ns
ns
ns
ns
20
Notes to tables:
(1) Operating conditions: VCC = 5 V ± 5%, TA = 0° C to 70° C for commercial use.
(2) If the device is operating in standby mode, increase the time by the amount shown.
(3) The tPZX and tPXZ parameters are measured at ±0.5 V from steady-state voltage that is driven by the specified output
load.
(4) This specification must be met to guarantee tEOI. If ILEgoes high before the data is valid, use tPD instead of tEOI
.
16
Altera Corporation
EP312 & EP324 Classic EPLDs
Figure 8 shows the package pin-outs for EP312 and EP324 devices.
Figure 8. EP312 & EP324 Package Pin-Outs
Package outlines not drawn to scale. Windows in ceramic packages only.
4
3
2
1
28 27 26
25
CLK/INPUT
I/O
1
24
23
22
21
20
19
18
17
16
15
14
13
VCC
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
NC
5
I/O
I/O
I/O
I/O
I/O
I/O
NC
2
I/O
6
24
23
22
21
20
19
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
I/O
3
I/O
7
4
I/O
8
5
I/O
6
I/O
9
7
I/O
10
11
EP312
8
I/O
9
I/O
12 13 14 15 16 17 18
10
11
12
I/O
I/O
GND
ILE/ICLK/INPUT
24-Pin DIP
28-Pin J-Lead
6
5
4
3
2 1 44 43 42 41 40
CLK/INPUT
INPUT
INPUT
I/O
INPUT
INPUT
INPUT
I/O
1
40
2
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
I/O
7
39
38
37
36
35
34
33
32
31
30
29
I/O
3
I/O
GND
I/O
8
I/O
4
9
VCC
I/O
I/O
I/O
5
10
11
12
13
14
15
16
17
I/O
I/O
6
I/O
I/O
I/O
I/O
7
NC
NC
I/O
GND
I/O
VCC
I/O
8
I/O
9
I/O
I/O
I/O
I/O
10
11
12
13
14
15
16
17
18
19
20
VCC
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
EP324
VCC
I/O
GND
I/O
18 19 20 21 22 23 24 25 26 27 28
I/O
I/O
I/O
I/O
I/O
I/O
INPUT
INPUT
INPUT
INPUT
INPUT
ILE/ICLK/INPUT
40-Pin DIP
44-Pin J-Lead
Altera Corporation
17
EP312 & EP324 Classic EPLDs
Refer to “Altera Device Package Outlines” in the Altera Data Book for
detailed information on packages outlines.
Package
Outlines
Table 3 gives the availability and ordering codes for EP312 and EP324
devices. Altera will accept Intel product names and ordering codes for
Intel devices until June 30, 1995, after which only Altera product names
and ordering codes will be accepted.
Product
Availability
Table 3. EP312 & EP324 Availability
Device
Temperature
Grade
Speed
Grade
Package
Altera
Ordering Code
Former Intel
Ordering Code
EP312
Commercial
temperature
(0° C to 70° C)
-25
-30
-25
-30
-25
24-pin CerDIP
24-pin CerDIP
24-pin PDIP
24-pin PDIP
28-pin PLCC
EP312DC-25
EP312DC-30
EP312PC-25
EP312PC-30
EP312LC-25
D5AC312-25
D5AC312-30
P5AC312-25
P5AC312-30
N5AC312-25
Industrial
-30
28-pin PLCC
EP312LI-30
TNAC312-30
temperature
(–40° C to 85° C)
EP324
Commercial
temperature
(0° C to 70° C)
-30
-25
-30
-25
-30
40-pin CerDIP
40-pin PDIP
40-pin PDIP
44-pin PLCC
44-pin PLCC
EP324DC-30
EP324PC-25
EP324PC-30
EP324LC-25
EP324LC-30
D5AC324-30
P5AC324-25
P5AC324-30
N5AC324-25
N5AC324-30
Altera, MAX, MAX+PLUS, and FLEX are registered trademarks of Altera Corporation. The following are
trademarks of Altera Corporation: MAX+PLUS II, AHDL, and FLEX 10K. Altera acknowledges the
trademarks of other organizations for their respective products or services mentioned in this document,
specifically: Verilog and Verilog-XL are registered trademarks of Cadence Design Systems, Inc. Mentor
Graphics is a registered trademark of Mentor Graphics Corporation. Synopsys is a registered trademark of
Synopsys, Inc. Viewlogic is a registered trademark of Viewlogic Systems, Inc. Altera products are protected
under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera
warrants performance of its semiconductor products to current specifications in accordance with Altera’s
standard warranty, but reserves the right to make changes to any products and services at any time without
notice. Altera assumes no responsibility or liability arising out of the application or use of
any information, product, or service described herein except as expressly agreed to in
writing by Altera Corporation. Altera customers are advised to obtain the latest version of
device specifications before relying on any published information and before placing
orders for products or services.
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18
Altera Corporation
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