EP4SGX110_技术文档

Section I. Stratix IV Device Datasheet

This section includes the following chapters:

■

Chapter 1, DC and Switching Characteristics

Revision History

Refer to each chapter for its own specific revision history. For information on when

each chapter was updated, refer to the Chapter Revision Dates section, which appears

in the full handbook.

Stratix IV Device Handbook, Volume 4

I–2

Section I: Stratix IV Device Datasheet

Stratix IV Device Handbook, Volume 4

1. DC and Switching Characteristics

SIV54001-2.1

Electrical Characteristics

This chapter covers the electrical characteristics for Stratix IV devices.

Operating Conditions

®

When Stratix IV devices are implemented in a system, they are rated according to a

set of defined parameters. To maintain the highest possible performance and

reliability of Stratix IV devices, system designers must consider the following

operating requirements. Stratix IV devices are offered in both commercial and

industrial grades. Commercial devices are offered in -2 (fastest), -2x, -3, and -4 speed

grades.

Absolute Maximum Ratings

Absolute maximum ratings define the maximum operating conditions for Stratix IV

devices. The values are based on experiments conducted with the devices and

theoretical modeling of breakdown and damage mechanisms. The functional

operation of the device is not implied at these conditions.

1

Conditions beyond those listed in Table 1–1 and Table 1–2 may cause permanent

damage to the device. Additionally, device operation at the absolute maximum

ratings for extended periods of time may have adverse effects on the device.

Table 1–1. Stratix IV Device Absolute Maximum Ratings

Symbol

V_CC

Description

Core voltage and periphery circuitry power supply

Power supply for programmable power technology

Configuration pins power supply

Minimum

-0.5

-40

Maximum

1.35

2.25

3.75

3.9

Unit

V

V_CCPT

V_CCPGM

V_CCAUX

V_CCBAT

V_CCPD

V_CCIO

V

Auxiliary supply for the programmable power technology

Battery back-up power supply for design security volatile key register

I/O pre-driver power supply

V

I/O power supply

V

V_{CC_CLKIN}

V_{CCD_PLL}

V_{CCA_PLL}

V_I

Differential clock input power supply

PLL digital power supply

3.75

1.35

3.75

4.0

V

PLL analog power supply

V

DC input voltage

V

T_J

Operating junction temperature

100

C

T_STG

Storage temperature (No bias)

-65

150

C

Stratix IV Device Handbook, Volume 4

Chapter 1: DC and Switching Characteristics

1–2

Electrical Characteristics

Table 1–2. Stratix IV GX Transceiver Power Supply Absolute Maximum Ratings

Symbol

Description

Transceiver high voltage power (left side)

Transceiver high voltage power (right side)

Transceiver HIP digital power (left side)

Transceiver HIP digital power (right side)

Receiver power (left side)

Minimum

—

Maximum

3.15 / 2.625

0.99

Unit

V_{CCA_L}

V_{CCA_R}

V_{CCHIP_L}

V_{CCHIP_R}

V_{CCR_L}

V_{CCR_R}

V_{CCT_L}

V_{CCT_R}

V

—

0.99

—

1.21

Receiver power (right side)

—

1.21

Transmitter power (left side)

—

1.21

Transmitter power (right side)

—

1.21

V_{CCL_GXBLn}(2)

V_{CCL_GXBRn}(2)

Transceiver clock power (left side)

Transceiver clock power (right side)

Transmitter output buffer power (left side)

Transmitter output buffer power (right side)

—

1.21

V

—

1.21

V

_{CCH_GXBLn}(2)

_{CCH_GXBRn}(2)

—

1.54 / 1.65

—

Note to Table 1–2:

(1) n=0, 1, 2, 3

Maximum Allowed Overshoot/Undershoot Voltage

During transitions, input signals may overshoot to the voltage shown in Table 1–3

and undershoot to -2.0 V for input currents less than 100 mA and periods shorter than

20 ns.

Table 1–3 lists the maximum allowed input overshoot voltage and the duration of the

overshoot voltage as a percentage of device lifetime. The maximum allowed

overshoot duration is specified as a percentage of high-time over the lifetime of the

device. A DC signal is equivalent to 100% duty cycle. For example, a signal that

overshoots to 4.3 V can only be at 4.3 V for ~5% over the lifetime of the device; for a

device lifetime of 10 years, this amounts to 5/10ths of a year.

Stratix IV Device Handbook, Volume 4

Chapter 1: DC and Switching Characteristics

1–3

Electrical Characteristics

Table 1–3. Maximum Allowed Overshoot During Transitions

Overshoot Duration as %

of High Time

Symbol

Vi (AC)

Description

Condition

4.0 V

Unit

%

AC input voltage

100.000

79.330

46.270

27.030

15.800

9.240

4.05 V

4.1 V

4.15 V

4.2 V

4.25 V

4.3 V

5.410

4.35 V

4.4 V

3.160

1.850

4.45 V

4.5 V

1.080

0.630

4.55 V

4.6 V

0.370

0.220

Recommended Operating Conditions

This section lists the functional operation limits for AC and DC parameters for

Stratix IV devices. The steady-state voltage and current values expected from

Stratix IV devices are provided in Table 1–4. All supplies must be strictly monotonic,

without plateaus.

Table 1–4. Stratix IV Device Recommended Operating Conditions (Part 1 of 2)

Symbol

V_CC

Description

Condition

Minimum

Typical

Maximum

Unit

Core voltage and periphery circuitry power

supply

—

0.87

0.90

0.93

V

V_CCPT

V_CCAUX

V_CCPD

Power supply for programmable power

technology

—

1.45

1.50

2.5

1.55

V

Auxiliary supply for the programmable

power technology

2.375

2.625

I/O pre-driver (3.0 V) power supply

I/O pre-driver (2.5 V) power supply

I/O buffers (3.0-V) power supply

—

2.85

2.375

2.85

3

2.5

3

3.15

2.625

3.15

V

V_CCIO

I/O buffers (2.5-V) power supply

2.375

1.71

2.5

1.8

1.5

1.2

3

2.625

1.89

I/O buffers (1.8-V) power supply

I/O buffers (1.5-V) power supply

1.425

1.14

1.575

1.26

I/O buffers (1.2-V) power supply

V_CCPGM

Configuration pins (3.0-V) power supply

Configuration pins (2.5-V) power supply

Configuration pins (1.8-V) power supply

PLL analog voltage regulator power supply

PLL digital voltage regulator power supply

2.85

3.15

2.375

1.71

2.5

1.8

2.5

0.90

2.625

1.89

V_{CCA_PLL}

V_{CCD_PLL}

2.375

0.87

2.625

0.93

Stratix IV Device Handbook, Volume 4

Chapter 1: DC and Switching Characteristics

1–4

Electrical Characteristics

Table 1–4. Stratix IV Device Recommended Operating Conditions (Part 2 of 2)

Symbol

V_{CC_CLKIN}

V_CCBAT

Description

Condition

Minimum

2.375

1.2

Typical

2.5

Maximum

2.625

3.3

Unit

Differential clock input power supply

—

V

Battery back-up power supply (For design

security volatile key register)

3.0

V_I

V_O

T_J

DC input voltage

—

–0.5

0

—

3.6

V_CCIO

85

V

Output voltage

—

Operating junction temperature

Commercial

Industrial

Normal POR

Fast POR (1)

0

C

–40

0.05

100

12

C

t_RAMP

Power supply ramp time

ms

Note to Table 1–4:

(1) If the PORSELpin is connected to V_CC, all supplies must ramp up within 12 ms.

Table 1–5 shows the transceiver power supply recommended operating conditions.

Table 1–5. Stratix IV GX Transceiver Power Supply Recommended Operating Conditions

Symbol

Description

Transceiver high voltage power (left side)

Transceiver high voltage power (right side)

Transceiver HIP digital power (left side)

Transceiver HIP digital power (right side)

Receiver power (left side)

Minimum

Typical

Maximum

Unit

V_{CCA_L}

V_{CCA_R}

2.85/2.375

3.0/2.5

3.15/2.625

V

_{CCHIP_L}(1)

0.855

1.045

0.9

1.1

0.945

1.155

V

_{CCHIP_R}(1)

V_{CCR_L}

V_{CCR_R}

V_{CCT_L}

V_{CCT_R}

Receiver power (right side)

Transmitter power (left side)

1.045

1.1

1.155

Transmitter power (right side)

V_{CCL_GXBLn}(2)

_{CCL_GXBRn}(2)

V_{CCH_GXBLn}(2)

_{CCH_GXBRn}(2)

Transceiver clock power (left side)

Transceiver clock power (right side)

Transmitter output buffer power (left side)

Transmitter output buffer power (right side)

1.045

1.1

1.155

V

1.33/1.425

1.4/1.5

1.47/1.575

V

Note to Table 1–5:

(1) If V_{CCHIP_L}is connected to the same power supply source as V_CC, the tighter V_CCrecommended operating conditions need to be met.

(2) n=0, 1, 2, 3

DC Characteristics

This section lists the supply current, I/O pin leakage current, input pin capacitance,

on-chip termination tolerance, and hot socketing specifications.

Supply Current

Standby current is the current the device draws after the device is configured, with no

inputs or outputs toggling and no activity in the device. Since these currents vary

largely with resources used, use the Excel-based Early Power Estimator (EPE) to get

supply current estimates for your design.

Stratix IV Device Handbook, Volume 4

Chapter 1: DC and Switching Characteristics

1–5

Electrical Characteristics

Table 1–6 lists supply current specifications for V_{CC_CLKIN}, V_CCPGM, and V_CCAUX. Use

the EPE to get supply current estimates for remaining power supplies.

Table 1–6. Supply Current Specifications for V_{CC_CLKIN}, V_CCPGM, and V_CCAUX

Symbol

Parameter

Min

Max

Unit

I_CLKIN

V_{CC_CLKIN}current

specifications

0

250

mA

I_PGM

I_AUX

V_CCPGMcurrent

specifications

0

250

mA

V_CCAUXcurrent

specification

I/O Pin Leakage Current

Table 1–7 defines the Stratix IV I/O pin leakage current specifications.

Table 1–7. Stratix IV I/O Pin Leakage Current

Symbol

Description

Input pin

Tri-stated I/O pin

Conditions

V_I= 0V to V_CCIOMAX

V_O= 0V to V_CCIOMAX

Min

-10

Typ

—

Max

10

Unit

µA

I_I

I_OZ

—

10

µA

On-Chip Termination (OCT) Specifications

Table 1–8 lists the Stratix IV series and parallel OCT calibration accuracy.

Table 1–8. On-Chip Termination With Calibration Specification for I/Os - Preliminary

Calibration Accuracy

Symbol

25-Ω R_S3.0/2.5

50-Ω R_S3.0/2.5

50-Ω R_T2.5

25-Ω R_S1.8

50-Ω R_S1.8

50-Ω R_T1.8

50-Ω R_S1.5

50-Ω R_T1.5

50-Ω R_S1.2

50-Ω R_T1.2

Description

Conditions

V_CCIO= 3.0/2.5 V

V_CCIO= 2.5 V

V_CCIO= 1.8 V

V_CCIO= 1.5 V

V_CCIO= 1.2 V

Commercial

Unit

25-Ωseries termination

50-Ωseries termination

50-Ωparallel termination

25-Ωseries termination

50-Ωseries termination

50-Ωparallel termination

50-Ωseries termination

50-Ωparallel termination

50-Ωseries termination

5

%

10

5

10

8

10

8

10

The calibration accuracy for calibrated series and parallel OCTs are applicable at the

moment of calibration. When PVT conditions change after calibration, the tolerance

may change. Table 1–9 lists the Stratix IV OCT resistance tolerance to PVT changes.

Stratix IV Device Handbook, Volume 4

Chapter 1: DC and Switching Characteristics

1–6

Electrical Characteristics

Table 1–9. I/O On-Chip Termination Resistance Tolerance - Preliminary

Resistance Tolerance

Symbol

R_{OCT_UNCAL}

R_{OCT_CAL}

Description

Commercial

Unit

Internal series/parallel OCT with calibration

Internal series/parallel OCT without calibration

5

%

30

OCT calibration is automatically performed at power-up for OCT-enabled I/Os.

Table 1–10 lists OCT variation with temperature and voltage after power-up

calibration. Use Equation 1–1 to determine the OCT variation when voltage and

temperature vary after power-up calibration.

Equation 1–1. OCT Variation Without Re-Calibration (Note 1)

dR

dT

dR

dV

⎛

⎞

⎠

------

R_OCT= R_CAL1 +

× ΔT +

× ΔV

⎝

Note to Equation 1–1:

(1) R_CALis calibrated on-chip termination at power up. ΔT andΔV are variations in temperature and voltage with respect

to temperature and V_CCIOvalues, respectively, at power up.

Table 1–10. On-Chip Termination Variation after Power-Up Calibration - Preliminary

Commercial

Industrial

Typical

Symbol

dR/dV

Description

V_CCIO(V)

3.0

Typical

0.029

0.036

0.033

0.294

0.301

0.355

0.344

0.348

Unit

Ω/V

OCT variation with voltage without re-calibration

—

2.5

1.8

1.5

1.2

dR/dT

OCT variation with temperature without

re-calibration

3.0

Ω/C

2.5

1.8

1.5

1.2

Pin Capacitance

Table 1–11 shows the Stratix IV device family pin capacitance.

Table 1–11. Stratix IV Device Capacitance (Note 1) - Preliminary (Part 1 of 2)

Symbol

C_IOTB

Description

Typical

Unit

pF

Input capacitance on top/bottom I/O pins

8

5

C_IOLR

Input capacitance on left/right I/O pins

pF

C_CLKTB

C_CLKLR

Input capacitance on top/bottom dedicated clock input pins

Input capacitance on left/right dedicated clock input pins

pF

Stratix IV Device Handbook, Volume 4

Chapter 1: DC and Switching Characteristics

1–7

Electrical Characteristics

Table 1–11. Stratix IV Device Capacitance (Note 1) - Preliminary (Part 2 of 2)

Symbol

C_OUTFB

Description

Typical

Unit

Input capacitance on dual-purpose clock output/feedback pins

8

pF

Note to Table 1–11:

(1) Pending silicon characterization.

Hot Socketing

Table 1–12 defines the hot socketing specification for Stratix IV devices.

Table 1–12. Stratix IV Hot Socketing Specifications - Preliminary

Symbol

I_IIOPIN(DC)

I_IOPIN(AC)

Description

DC current per I/O pin

AC current per I/O pin

Maximum

300 μA

8 mA for Trise > 10 ns

I/O Standard Specifications

Table 1–13 through Table 1–18 list input voltage (V_IHand V_IL), output voltage (V_OH

and V_OL), and current drive characteristics (I_OHand I_OL) for various I/O standards

supported by Stratix IV devices. These tables also show the Stratix IV device family

I/O standard specifications. Refer to the “Glossary” on page 1–34 for an explanation

of terms used in Table 1–13 through Table 1–18. V_OLand V_OHvalues are valid at the

corresponding I_OHand I_OL, respectively.

Table 1–13. Single-Ended I/O Standards

V

_CCIO(V)

V_IL(V)

Max

V_IH(V)

V_OL(V)

V_OH(V)

I/O

Standard

I_OL

(mA)

I_OH

(mA)

Min

Typ

Max

Min

Max

Min

LVTTL

LVCMOS

2.5 V

2.85

3

3.15

-0.3

0.8

0.7

1.7

V_CCIO

0.3

+

0.4

2.4

2

-2

2.85

3

3.15

-0.3

1.7

V_CCIO

0.3

0.2

V_CCIO- 0.2

0.1

-0.1

2.375

2.5

2.625

V_CCIO

0.3

0.2

0.4

2.1

2

0.1

1

-0.1

-1

0.7

1.7

2

-2

1.8 V

1.71

1.425

1.14

2.85

1.8

1.5

1.2

3

1.89

1.575

1.26

3.15

-0.3

-

0.35 *

V_CCIO

0.65 *

V_CCIO

0.3

+

0.45

V_CCIO-0.45

2

-2

1.5 V

0.35 *

V_CCIO

0.65 *

V_CCIO

0.3

0.25 *

V_CCIO

0.75 *

V_CCIO

2

-2

1.2 V

0.35 *

V_CCIO

0.65 *

V_CCIO

0.3

0.25 *

V_CCIO

0.75 *

V_CCIO

2

3.0-V PCI

0.3 *

V_CCIO

0.5 *

V_CCIO

3.6

0.1 *

V_CCIO

0.9 * V_CCIO

1.5

-0.5

3.0-V

PCI-X

3

-

0.35 *

V_CCIO

0.5 *

V_CCIO

-

0.1 *

V_CCIO

0.9 * V_CCIO

Stratix IV Device Handbook, Volume 4

Chapter 1: DC and Switching Characteristics

1–8

Electrical Characteristics

Table 1–14. Single-Ended SSTL and HSTL I/O Reference Voltage Specifications

V

_CCIO(V)

V_REF(V)

Typ

V_TT(V)

I/O Standard

Min

Typ

Max

Min

Max

Min

Typ

Max

SSTL-2 Class I,

II

2.375

2.5

2.625 0.49 * V_CCIO0.5 * V_CCIO

1.89 0.49 * V_CCIO0.5 * V_CCIO

1.575 0.49 * V_CCIO0.5 * V_CCIO

0.51 *

V_CCIO

V_REF

0.04

-

V_REF

V_REF+ 0.04

—

SSTL-18 Class

I, II

1.71

1.425

1.71

1.8

1.5

1.8

1.5

1.2

0.51 *

V_CCIO

V_REF

0.04

-

V_REF

SSTL-15 Class

I, II

0.51 *

V_CCIO

V_REF-

0.04

HSTL-18 Class

I, II

1.89

1.575

1.26

0.85

0.68

0.9

0.95

—

V

_CCIO/2

HSTL-15 Class

I, II

1.425

1.14

0.75

0.9

V

—

HSTL-12 Class

I, II

0.48 * V_CCIO0.5 * V_CCIO

0.52 *

V_CCIO

V_CCIO/2

—

Table 1–15. Single-Ended SSTL and HSTL I/O Standards Signal Specifications

V

_IL(DC)(V)

Max

V_REF

V_{IH (DC )}(V)

Min Max

V_REF

V_IL(AC)(V)

Max

V_IH(AC)(V)

Min

V_OL(V)

Max

V_OH(V)

Min

I/O Standard

Min

I_ol(mA) I_oh(mA)

SSTL-2

Class I

-0.3

-0.15

-

+

V_CCIO

0.3

+

V_REF- 0.31 V_REF+ 0.31

V_REF-0.25 V_REF+ 0.25

V_TT-

0.57

V_TT+

0.57

8.1

16.2

6.7

13.4

8

-8.1

-16.2

-6.7

-13.4

-8

0.15

V_REF

0.15

SSTL-2

Class II

V_REF

-

+

V_CCIO

0.3

V_TT-

0.76

V_TT+

0.76

0.15

SSTL-18

Class I

V_REF

-

V_REF

+

V_CCIO

0.3

V_TT-

0.475

V_TT+

0.475

0.125

SSTL-18

Class II

V_REF

-

V_REF

+

V_CCIO

0.3

0.28

V_CCIO-

0.28

0.125

SSTL-15

Class I

V

_REF-0.1

V_REF

0.1

+

V_CCIO

0.3

V_REF

-

V_REF

+

0.2 *

V_CCIO

0.8 *

V_CCIO

0.175

SSTL-15

Class II

V

V_REF

V_CCIO

0.3

V_REF

-

V_REF

+

0.2 *

V_CCIO

0.8 *

V_CCIO

16

8

-16

-8

0.1

0.175

HSTL-18

Class I

V

+

V_CCIO

0.3

V_REF-0.2

V_REF+ 0.2

0.4

V_CCIO-0.4

0.1

HSTL-18

Class II

V

V_REF

+

V_CCIO

0.3

V_REF-0.2

V_REF+ 0.2

16

8

-16

-8

0.1

HSTL-15

Class I

V

V_REF

+

V_CCIO

0.3

0.1

HSTL-15

Class II

V

V_REF

+

V_CCIO

0.3

16

8

-16

-8

0.1

HSTL-12

Class I

V_REF

-

V_REF

+

V_CCIO

V_REF-0.15 V_REF+ 0.15

0.25*

V_CCIO

0.75*

V_CCIO

0.08

0.15

HSTL-12

Class II

V_REF

-

V_REF

0.08

+

V_CCIO

0.15

+

0.25*

V_CCIO

0.75*

V_CCIO

16

-16

0.08

Stratix IV Device Handbook, Volume 4

Chapter 1: DC and Switching Characteristics

1–9

Electrical Characteristics

Table 1–16. Differential SSTL I/O Standards

V

_CCIO(V)

V_CSWING(DC)(V)

V_X(AC)(V)

V_SWING(AC)(V)

V_OX(AC)(V)

I/O

Standard

Min Typ Max Min

Max

Min

Typ

Max

Min Max

Min

Typ

Max

SSTL-2

Class I, II

2.375 2.5 2.625 0.3

V_CCIO

0.6

+

V_CCIO/2

- 0.2

—

V_CCIO/2+ 0.6 V_CCIO

0.2 0.6

+

V_CCIO/2

- 0.15

—

V_CCIO/2

+ 0.15

SSTL-18

Class I, II

1.71 1.8 1.89

0.3

V_CCIO

0.6

+

V_CCIO/2

-

0.175

—

V

_CCIO/2+ 0.5 V_CCIO

+

V_CCIO/2

-

0.125

—

V

_CCIO/2

+

0.175

0.6

0.125

SSTL-15

Class I, II

1.425 1.5 1.575 0.2

—

V

_CCIO/2

—

0.4

—

V_CCIO/2

—

Table 1–17. Differential HSTL I/O Standards

V

_CCIO(V)

Typ

V_DIF(DC)(V)

Min Max

0.2

V_X(AC)(V)

V_CM(DC)(V)

V_DIF(AC)(V)

I/O

Standard

Min

Max

Min

Typ

Max

Min

0.8

Typ

Max

Min

0.4

Max

HSTL-18 1.71

Class I

1.8

1.89

—

0.78

—

1.12

—

1.12

—

HSTL-15 1.425 1.5

Class I, II

1.575 0.2

1.26 0.2

0.68

—

0.9

—

0.7

—

0.9

0.4

0.3

—

HSTL-12 1.14

Class I, II

1.2

0.5*

V_CCIO

0.4*

V_CCIO

0.5*

V_CCIO

0.6*

V_CCIO

Table 1–18. Differential I/O Standard Specifications (Part 1 of 2) (Note 1), (2)

V

_CCIO(V)

V_ID(mV)

V_ICM(DC)(V)

V_OD(V) (3)

V_OCM(V) (3)

Min Typ Max

I/O

Standard Min Typ Max Min Condition Max Min

Conditio

n

Ma

x

Max Min Typ

2.5V

LVDS

(HIO)

2.37 2.5 2.625 100

5

V_CM=

1.25V

—

0.05

1.05

0.05

1.05

0.3

D_max<=

700Mbps

1.8

1.55

1.8

0.24

7

—

-

0.6 1.12 1.2 1.37

5

D_max

>

—

0.6

—

700Mbps

2.5V

LVDS

(VIO)

2.37 2.5 2.625 100

5

V_CM=

1.25V

D_max<=

700Mbps

0.24

7

1

1.2 1.5

5

D_max

>

1.55

1.4

—

1.5

700Mbps

RSDS

(HIO)

2.37 2.5 2.625 100

5

V_CM=

1.25V

—

0.1 0.2 0.6 0.5 1.2 1.4

0.1 0.2 0.6 0.5 1.2 1.5

RSDS

(VIO)

2.37 2.5 2.625 100

5

V_CM=

1.25V

0.3

—

1.4

Mini-

LVDS

(HIO)

2.37 2.5 2.625 200

5

—

600 0.4

1.32 0.25

5

—

0.6 0.5 1.2 1.4

0.6 0.5 1.2 1.5

Mini-

LVDS

(VIO)

2.37 2.5 2.625 200

5

—

1.32 0.25

5

Stratix IV Device Handbook, Volume 4

Chapter 1: DC and Switching Characteristics

1–10

Switching Characteristics

Table 1–18. Differential I/O Standard Specifications (Part 2 of 2) (Note 1), (2)

V

_CCIO(V)

V_ID(mV)

V_ICM(DC)(V)

V_OD(V) (3)

V_OCM(V) (3)

Min Typ Max

I/O

Standard Min Typ Max Min Condition Max Min

Conditio

n

Ma

x

Max Min Typ

LVPECL

(VIO) (4)

2.37 2.5 2.625 300

5

—

0.6

D_max<=

1.8

—

700Mbps (5)

D_max1.6

700Mbps (5)

—

0.6

>

—

Notes to Table 1–18:

(1) VIO (vertical I/O) is top and bottom I/Os; HIO (horizontal I/O) is left and right I/Os.

(2) 1.4V/1.5V PCML transceiver I/O standard specifications are described in the section “Transceiver Performance Specifications” on page 1–10.

(3) RL range: 90 <= RL <= 110 Ω.

(4) LVPECL specifications apply only to CLK input pins on column I/Os.

(5) For D_MAX> 700 Mbps, the minimum input voltage is 0.85 V; the maximum input voltage is 1.75 V. For F_MAX<=700Mbps, the minimum input voltage

is 0.45 V; the maximum input voltage is 1.95 V.

Power Consumption

®

Altera offers two ways to estimate power consumption for a design: the Excel-based

®

Early Power Estimator and the Quartus II PowerPlay Power Analyzer feature.

The interactive Excel-based Early Power Estimator is typically used prior to designing

the FPGA in order to get a magnitude estimate of the device power. The Quartus II

PowerPlay Power Analyzer provides better quality estimates based on the specifics of

the design after place-and-route is complete. The PowerPlay Power Analyzer can

apply a combination of user-entered, simulation-derived, and estimated signal

activities that, combined with detailed circuit models, can yield very accurate power

estimates.

f

For more information about power estimation tools, refer to the PowerPlay Early Power

Estimator User Guide for Stratix III and Stratix IV FPGAs and the PowerPlay Power

Analysis chapter in the Quartus II Handbook.

Switching Characteristics

This section provides performance characteristics of Stratix IV core and periphery

blocks for commercial grade devices.

These characteristics can be designated as Preliminary and Final. Preliminary

characteristics are created using simulation results, process data, and other known

parameters. Final numbers are based on actual silicon characterization and testing.

These numbers reflect the actual performance of the device under worst-case silicon

process, voltage, and junction temperature conditions. The upper-right hand corner of

a table shows the designation as “Preliminary” or “Final”.

Transceiver Performance Specifications

This sections describes transceiver performance specifications.

Table 1–19 lists Stratix IV GX transceiver specifications.

Stratix IV Device Handbook, Volume 4

Chapter 1: DC and Switching Characteristics

1–11

Switching Characteristics

Table 1–19. Stratix IV GX Transceiver Specification (Part 1 of 4)

-3

Commercial/Industrial

and

-2 Speed Commercial -2x Commercial Speed

-4 Speed Commercial

Speed Grade

Grade (1)

Symbol/

Description

Conditions

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

Reference Clock

Input frequency from

REFCLKinput pins

—

50

—

637.5

425

50

—

637.5

325

50

—

622.08 MHz

Phase frequency

detector (CMU PLL

and receiver CDR)

325

MHz

Absolute V_MAXfor a

REFCLKpin

—

1.6

1.5

—

1.6

1.5

—

1.6

1.5

—

V

Operational V_MAXfor

a REFCLKpin

Absolute V_MINfor a

-0.3

REFCLKpin

Rise/fall time

Duty cycle

—

45

—

0.2

55

—

45

—

0.2

55

—

45

—

0.2

55

UI

%

Peak-to-peak

differential input

voltage

200

1600

200

1600

200

1600

mV

Spread-spectrum

modulating clock

frequency

PCI Express

30

—

33

30

—

33

30

—

33

kHz

Spread-spectrum

downspread

—

0 to

-0.5%

100

—

0 to

-0.5%

100

—

0 to

-0.5%

100

—

On-chip termination

resistors

—

Ω

V

_ICM(AC coupled)

—

1100

—

1100

—

1100

—

mV

V_ICM(DC coupled)

HCSL I/O

250

550

250

550

250

550

standard for PCI

Express

reference clock

R_REF

—

2000

1%

—

2000

1%

—

2000

1%

—

Ω

Transceiver Clocks

Calibration block

clock frequency

—

10

—

125

—

125

—

10

—

125

—

125

—

10

—

125

—

125

—

MHz

—

fixedclkclock

frequency

PCI Express

Receiver Detect

reconfig_clk

clock frequency

Dynamic

reconfiguration 37.5

clock frequency (2)

2.5/

50

2.5/

37.5

(2)

50

2.5/

37.5

(2)

50

Stratix IV Device Handbook, Volume 4

Chapter 1: DC and Switching Characteristics

1–12

Switching Characteristics

Table 1–19. Stratix IV GX Transceiver Specification (Part 2 of 4)

-3

Commercial/Industrial

and

-2 Speed Commercial -2x Commercial Speed

-4 Speed Commercial

Speed Grade

Grade (1)

Symbol/

Description

Conditions

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

Transceiver block

minimum

—

1

—

1

—

1

—

µs

power-down pulse

width

Receiver

Data rate

—

600

—

8500

1.6

1.5

—

600

—

6500

1.6

1.5

—

600

—

5000 Mbp

s

Absolute V_MAXfor a

receiver pin (3)

—

1.6

1.5

—

V

Operational V_MAXfor a

receiver pin

—

V

Absolute V_MINfor a

receiver pin

—

-0.4

—

-0.4

—

-0.4

—

V

Maximum peak-to-

peak differential input setting

voltage V_ID(diff p-p)

V_ICM= 0.82 V

—

2.7

1.6

—

2.7

1.6

—

2.7

1.6

—

V

V_ICM=1 .1 V

setting (4)

—

V

Minimum peak-to-

peak differential input Mbps to 5 Gbps.

voltage V_ID(diff p-p)

Data Rate = 600

100

165

—

100

165

—

165

—

mV

Data Rate >

5Gbps.

—

V_ICM

V_ICM= 0.82 V

setting

820

1100

—

820

1100

—

820

1100

—

V_ICM=1 .1 V

—

setting (4)

Differential on-chip

termination resistors

85−Ωsetting

100−Ωsetting

120−Ωsetting

150-Ω setting

PCI Express

XAUI

—

85

—

85

100

120

150

—

85

—

Ω

100

120

150

100

120

150

Return loss

differential mode

50 MHz to 1.25 GHz: -10dB

100 MHz to 2.5 GHz: -10dB

100 MHz to 4.875 GHz: -8dB

(OIF) CEI

4.875 GHz to 10 GHz: 16.6 dB/decade slope

50 MHz to 1.25 GHz: -6dB

Return loss common PCI Express

mode

XAUI

100 MHz to 2.5 GHz: -6dB

(OIF) CEI

100 MHz to 4.875 GHz: -6dB

4.875 GHz to 10 GHz: 16.6 dB/decade slope

Stratix IV Device Handbook, Volume 4

Chapter 1: DC and Switching Characteristics

1–13

Switching Characteristics

Table 1–19. Stratix IV GX Transceiver Specification (Part 3 of 4)

-3

Commercial/Industrial

and

-2 Speed Commercial -2x Commercial Speed

-4 Speed Commercial

Speed Grade

Grade (1)

Symbol/

Description

Conditions

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

Programmable PPM

detector (5)

—

62.5, 100, 125, 200,

250, 300, 500, 1000

ppm

Run length

—

80

—

16

—

80

—

16

—

80

—

16

UI

Programmable

equalization

dB

Signal detect/loss

threshold

PCI Express

(PIPE) Mode

65

—

175

75

65

—

175

65

—

175

mV

CDR LTR time (6)

—

15

—

15

—

75

—

15

—

75

—

µs

CDR minimum T1b

(7)

LTD lock time (8)

—

0

100

—

4000

0

100

—

4000

0

100

—

4000

ns

Data lock time from

rx_freqlocked

(9)

—

Programmable DC

gain

DC Gain Setting

= 0

—

0

3

—

0

3

—

0

3

—

dB

DC Gain Setting

= 1

DC Gain Setting

= 2

6

DC Gain Setting

= 3

9

DC Gain Setting

= 4

12

Transmitter

Data rate

—

600

—

8500

—

600

—

6500

—

600

—

5000 Mbp

s

V_OCM

0.65 V

setting

—

650

—

mV

Differential on-chip

termination resistors

85−Ωsetting

100−Ωsetting

120−Ωsetting

150-Ω setting

PCI Express

XAUI

—

85

—

85

100

120

150

—

85

—

Ω

100

120

150

100

120

150

Return loss

differential mode

50 MHz to 1.25 GHz: -10dB

312 MHz to 625 MHz: -10dB

625 MHz to 3.125 GHz: -10dB/decade slope

100 MHz to 4.875 GHz: -8dB

(OIF) CEI

4.875 GHz to 10 GHz: 16.6 dB/decade slope

Stratix IV Device Handbook, Volume 4

Chapter 1: DC and Switching Characteristics

1–14

Switching Characteristics

Table 1–19. Stratix IV GX Transceiver Specification (Part 4 of 4)

-3

Commercial/Industrial

and

-2 Speed Commercial -2x Commercial Speed

-4 Speed Commercial

Speed Grade

Grade (1)

Symbol/

Description

Conditions

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

Return loss common PCI Express

50 MHz to 1.25 GHz: -6dB

100 MHz to 4.875 GHz: -6dB

mode

(OIF) CEI

4.875 GHz to 10 GHz: 16.6 dB/decade slope

Rise time

Fall time

—

50

—

200

15

50

—

200

15

50

—

200

15

ps

Intra differential pair

skew

Intra-transceiver

block skew

—

120

300

—

120

300

—

120

300

ps

Inter-transceiver

block skew

CMU PLL0 and CMU PLL1

CMU PLL lock time

from

CMUPLL_reset

—

25

—

100

—

100

—

100

250

μs

deassertion

PLD-Transceiver Interface

Interface speed

—

250

25

—

250

25

MHz

—

Digital reset pulse

width

Minimum is 2 parallel clock cycles

Notes to Table 1–19:

(1) The -2x speed grade is the fastest speed grade offered in the following Stratix IV GX devices: EP4SGX70DF29, EP4SGX110DF29,

EP4SGX110FF35, EP4SGX230DF29, EP4SGX110FF35, EP4SGX230DF29, EP4SGX230FF35, EP4SGX290FF35, EP4SGX290FH29,

EP4SGX360FF35, and EPSGX360FH29.

(2) The minimum reconfig_clkfrequency is 2.5 MHz if the transceiver channel is configured in transmitter only mode. The minimum

reconfig_clkfrequency is 37.5MHz if the transceiver channel is configured in receiver only or receiver and transmitter mode. For more

details, refer to the Stratix IV Dynamic Reconfiguration chapter in volume 1 of the Stratix IV Device Handbook.

(3) The device cannot tolerate prolonged operation at this absolute maximum.

(4) The 1.1-V RX V_{IC M}setting must be used if the input serial data standard is LVDS and the link is DC coupled.

(5) The rate matcher supports only up to +/-300 ppm.

(6) Time taken to rx_pll_lockedgoes high from rx_analogresetdeassertion. Refer to Figure 1–1.

(7) Time for which the CDR must be kept in lock-to-reference mode after rx_pll_lockedgoes high and before rx_locktodatais asserted

in manual mode. Refer to Figure 1–1.

(8) Time taken to recover valid data after the rx_locktodatasignal is asserted in manual mode. Refer to Figure 1–1.

(9) Time taken to recover valid data after the rx_freqlockedsignal goes high in automatic mode. Refer to Figure 1–2.

Figure 1–1 shows the lock time parameters in manual mode. Figure 1–2 shows the

lock time parameters in automatic mode.

1

LTD = Lock-To-Data LTR = Lock-To-Reference

Stratix IV Device Handbook, Volume 4

Chapter 1: DC and Switching Characteristics

1–15

Switching Characteristics

Figure 1–1. Lock Time Parameters for Manual Mode

r x_analogreset

CDR status

LTR

LTD

r x_pl

l_lock

ed

r x_locktodata

r x_dataout

Invalid Data

Valid data

CDR LTR Time

LTD lock time

CDR Minimum T1b

Figure 1–2. Lock Time Parameters for Automatic Mode

LTR

LTD

CDR status

r x_freqlocked

Valid

data

Invalid

data

r x_dataout

Data lock time from rx_freqlocked

Table 1–20 through Table 1–23 show the typical V_ODfor various differential

termination settings.

Stratix IV Device Handbook, Volume 4

Chapter 1: DC and Switching Characteristics

1–16

Switching Characteristics

Table 1–20. Typical V_ODSetting, TX Term = 85 Ω

V_ODSetting (mV)

Symbol

0

1

2

3

4

5

6

7

V_ODTypical (mV)

170

340

510

595

680

765

850

1020

Table 1–21. Typical V_ODSetting, TX Term = 100 W

V_ODSetting (mV)

Symbol

0

1

2

3

4

5

6

7

V_ODTypical (mV)

200

400

600

700

800

900

1000

1200

Table 1–22. Typical V_ODSetting, TX Term = 120 Ω

V_ODSetting (mV)

Symbol

0

1

2

3

4

5

6

V_ODTypical (mV)

240

480

720

840

960

1080

1200

Table 1–23. Typical V_ODSetting, TX Term = 150 Ω

V_ODSetting (mV)

Symbol

0

1

2

3

4

5

V_ODTypical (mV)

300

600

900

1050

1200

1350

Table 1–24 shows the Stratix IV GX transceiver block AC specifications.

Table 1–24. Stratix IV GX Transceiver Block AC Specification (Note 1), (2) (Part 1 of 8)

-3 Speed

-2 Speed

CommercialSpeed

Grade

Commercial and

Industrial Speed

Grade

-4 Speed

Commercial Speed

Grade

Symbol/

Description

Conditions

Min Typ Max Min Typ Max Min Typ Max Unit

SONET/SDH Transmit Jitter Generation (3)

Peak-to-peak jitter at 622.08

Mbps

Pattern = PRBS23

—

0.1

—

0.1

—

0.1

UI

RMS jitter at 622.08 Mbps

Pattern = PRBS23

—

0.01

0.1

—

0.01

0.1

—

0.01

0.1

UI

Peak-to-peak jitter at

2488.32 Mbps

RMS jitter at 2488.32 Mbps

Pattern = PRBS23

—

0.01

—

0.01

—

0.01

UI

SONET/SDH Receiver Jitter Tolerance (3)

Stratix IV Device Handbook, Volume 4

Chapter 1: DC and Switching Characteristics

1–17

Switching Characteristics

Table 1–24. Stratix IV GX Transceiver Block AC Specification (Note 1), (2) (Part 2 of 8)

-3 Speed

-2 Speed

CommercialSpeed

Grade

Commercial and

Industrial Speed

Grade

-4 Speed

Commercial Speed

Grade

Symbol/

Description

Conditions

Min Typ Max Min Typ Max Min Typ Max Unit

Jitter tolerance at

622.08 Mbps

Jitter frequency =

0.03 KHz

> 15

> 1.5

> 0.15

> 15

UI

Pattern = PRBS23

Jitter frequency =

25 KHZ

> 1.5

Pattern = PRBS23

Jitter frequency =

250 KHz

> 0.15

> 15

> 0.15

> 15

Pattern = PRBS23

Jitter tolerance at

2488.32 MBps

Jitter frequency =

0.06 KHz

Pattern = PRBS23

Jitter frequency =

100 KHZ

> 1.5

> 0.15

> 1.5

Pattern = PRBS23

Jitter frequency =

1 MHz

> 0.15

Pattern = PRBS23

Jitter frequency =

10 MHz

Pattern = PRBS23

Fibre Channel Transmit Jitter Generation (4), (12)

Total jitter FC-1

Pattern = CRPAT

—

0.23

0.11

0.33

0.2

—

0.23

0.11

0.33

0.2

—

0.23

0.11

0.33

0.2

UI

Deterministic jitter FC-1

Total jitter FC-2

Deterministic jitter FC-2

Total jitter FC-4

0.52

0.33

0.52

0.33

0.52

0.33

Deterministic jitter FC-4

Fibre Channel Receiver Jitter Tolerance (4), (13)

Deterministic jitter FC-1

Random jitter FC-1

Pattern = CJTPAT

Fc/25000

> 0.37

> 0.31

> 1.5

> 0.37

> 0.31

> 1.5

> 0.37

> 0.31

> 1.5

UI

Sinusoidal jitter FC-1

Fc/1667

> 0.1

Deterministic jitter FC-2

Random jitter FC-2

Pattern = CJTPAT

Fc/25000

> 0.33

> 0.29

> 1.5

> 0.33

> 0.29

> 1.5

> 0.33

> 0.29

> 1.5

Sinusoidal jitter FC-2

Fc/1667

> 0.1

Stratix IV Device Handbook, Volume 4

Chapter 1: DC and Switching Characteristics

1–18

Switching Characteristics

Table 1–24. Stratix IV GX Transceiver Block AC Specification (Note 1), (2) (Part 3 of 8)

-3 Speed

-2 Speed

CommercialSpeed

Grade

Commercial and

Industrial Speed

Grade

-4 Speed

Commercial Speed

Grade

Symbol/

Description

Conditions

Pattern = CJTPAT

Fc/25000

Min Typ Max Min Typ Max Min Typ Max Unit

Deterministic jitter FC-4

Random jitter FC-4

> 0.33

> 0.29

> 1.5

> 0.33

> 0.29

> 1.5

> 0.33

> 0.29

> 1.5

UI

Sinusoidal jitter FC-4

Fc/1667

> 0.1

XAUI Transmit Jitter Generation (5)

Total jitter at 3.125 Gbps

Pattern = CJPAT

—

0.3

—

0.3

—

0.3

UI

Deterministic jitter at

3.125 Gbps

0.17

XAUI Receiver Jitter Tolerance (5)

Total jitter

—

> 0.65

> 0.37

> 8.5

> 0.65

> 0.37

> 8.5

> 0.65

> 0.37

> 8.5

UI

Deterministic jitter

Peak-to-peak jitter

Jitter frequency =

22.1 KHz

Jitter frequency =

1.875 MHz

> 0.1

UI

Jitter frequency =

20 MHz

PCI Express Transmit Jitter Generation (6)

Total jitter at 2.5 Gbps

(Gen1)

Compliance pattern

—

0.25

—

0.25

—

0.25

—

UI

Total jitter at 5 Gbps (Gen2)

Compliance pattern

PCI Express Receiver Jitter Tolerance (6)

Total jitter at 2.5 Gbps

(Gen1)

Compliance pattern

> 0.6

—

> 0.6

—

> 0.6

—

UI

Total jitter at 2.5 Gbps

(Gen2)

Compliance pattern

—

Serial RapidIO Transmit Jitter Generation (7)

Deterministic jitter

(peak-to-peak)

Data Rate = 1.25, 2.5,

—

0.17

0.35

—

0.17

0.35

—

0.17

0.35

UI

3.125 Gbps

Pattern = CJPAT

Total jitter (peak-to-peak)

Data Rate = 1.25, 2.5,

3.125 Gbps

Pattern = CJPAT

Serial RapidIO Receiver Jitter Tolerance (7)

Deterministic jitter tolerance Data Rate = 1.25, 2.5,

> 0.37

UI

(peak-to-peak)

3.125 Gbps

Pattern = CJPAT

Stratix IV Device Handbook, Volume 4

Chapter 1: DC and Switching Characteristics

1–19

Switching Characteristics

Table 1–24. Stratix IV GX Transceiver Block AC Specification (Note 1), (2) (Part 4 of 8)

-3 Speed

-2 Speed

CommercialSpeed

Grade

Commercial and

Industrial Speed

Grade

-4 Speed

Commercial Speed

Grade

Symbol/

Description

Conditions

Min Typ Max Min Typ Max Min Typ Max Unit

Combined deterministic and Data Rate = 1.25, 2.5,

> 0.55

UI

random jitter tolerance

(peak-to-peak)

3.125 Gbps

Pattern = CJPAT

Sinusoidal jitter tolerance

(peak-to-peak)

Jitter Frequency = 22.1

KHz Data Rate = 1.25,

2.5, 3.125 Gbps

> 8.5

UI

Pattern = CJPAT

Jitter Frequency =

1.875 MHz

> 0.1

UI

Data Rate = 1.25, 2.5,

3.125 Gbps

Pattern = CJPAT

Jitter Frequency =

20 MHz

Data Rate = 1.25, 2.5,

3.125 Gbps

Pattern = CJPAT

GIGE Transmit Jitter Generation (8)

Deterministic jitter

(peak-to-peak)

Pattern = CRPAT

—

0.14

—

0.14

—

0.14

UI

Total jitter (peak-to-peak)

Pattern = CRPAT

0.279

0.279 UI

GIGE Receiver Jitter Tolerance (8)

Deterministic jitter tolerance

(peak-to-peak)

Pattern = CJPAT

> 0.4

UI

Combined deterministic and

random jitter tolerance

(peak-to-peak)

Pattern = CJPAT

> 0.66

HiGig Transmit Jitter Generation (9)

Deterministic jitter

(peak-to-peak)

Data Rate = 3.75 Gbps

—

0.17

0.35

—

UI

Pattern = CJPAT

Data Rate = 3.75 Gbps

Pattern = CJPAT

Total jitter (peak-to-peak)

HiGig Receiver Jitter Tolerance (9)

Deterministic jitter tolerance Data Rate = 3.75 Gbps

> 0.37

> 0.65

—

UI

(peak-to-peak)

Pattern = CJPAT

Combined deterministic and Data Rate = 3.75 Gbps

random jitter tolerance

(peak-to-peak)

Pattern = CJPAT

Stratix IV Device Handbook, Volume 4

Chapter 1: DC and Switching Characteristics

1–20

Switching Characteristics

Table 1–24. Stratix IV GX Transceiver Block AC Specification (Note 1), (2) (Part 5 of 8)

-3 Speed

-2 Speed

CommercialSpeed

Grade

Commercial and

Industrial Speed

Grade

-4 Speed

Commercial Speed

Grade

Symbol/

Description

Conditions

Min Typ Max Min Typ Max Min Typ Max Unit

Sinusoidal jitter tolerance

(peak-to-peak)

Jitter Frequency = 22.1

KHz

> 8.5

> 0.1

—

UI

Data Rate = 3.75 Gbps

Pattern = CJPAT

Jitter Frequency =

1.875MHz

Data Rate = 3.75 Gbps

Pattern = CJPAT

Jitter Frequency =

20 MHz

Data Rate = 3.75 Gbps

Pattern = CJPAT

(OIF) CEI Transmitter Jitter Generation (10)

Total jitter (peak-to-peak) Data Rate =

—

0.3

—

N/A

—

N/A

UI

6.375 Gbps

Pattern = PRBS15 BER

-12

= 10

(OIF) CEI Receiver Jitter Tolerance (10)

Deterministic jitter tolerance

(peak-to-peak)

Data Rate =

6.375 Gbps

> 0.675

> 0.988

N/A

—

N/A

—

UI

Pattern = PRBS31 BER

-12

= 10

Combined deterministic and

random jitter tolerance

(peak-to-peak)

Data Rate =

6.375 Gbps

Pattern=PRBS31

-12

BER = 10

Stratix IV Device Handbook, Volume 4

Chapter 1: DC and Switching Characteristics

1–21

Switching Characteristics

Table 1–24. Stratix IV GX Transceiver Block AC Specification (Note 1), (2) (Part 6 of 8)

-3 Speed

-2 Speed

CommercialSpeed

Grade

Commercial and

Industrial Speed

Grade

-4 Speed

Commercial Speed

Grade

Symbol/

Description

Conditions

Min Typ Max Min Typ Max Min Typ Max Unit

Sinusoidal jitter tolerance

(peak-to-peak)

Jitter Frequency = 38.2

KHz

> 5

N/A

—

N/A

—

UI

Data Rate =

6.375 Gbps

Pattern = PRBS31 BER

-12

= 10

Jitter Frequency = 3.82

MHz

> 0.05

Data Rate =

6.375 Gbps

Pattern = PRBS31 BER

-12

= 10

Jitter Frequency =

20 MHz

Data Rate= 6.375 Gbps

Pattern = PRBS31 BER

-12

= 10

SDI Transmitter Jitter Generation (11)

Alignment jitter

(peak-to-peak)

Data Rate =

0.2

—

0.2

0.3

—

0.2

0.3

—

UI

1.485 Gbps (HD)

Pattern = Color Bar

Low-Frequency Roll-

Off = 100 KHz

Data Rate = 2.97 Gbps 0.3

(3G) Pattern = Color

Bar Low-Frequency

Roll-Off = 100 KHz

SDI Receiver Jitter Tolerance (11)

Stratix IV Device Handbook, Volume 4

Chapter 1: DC and Switching Characteristics

1–22

Switching Characteristics

Table 1–24. Stratix IV GX Transceiver Block AC Specification (Note 1), (2) (Part 7 of 8)

-3 Speed

-2 Speed

CommercialSpeed

Grade

Commercial and

Industrial Speed

Grade

-4 Speed

Commercial Speed

Grade

Symbol/

Description

Conditions

Min Typ Max Min Typ Max Min Typ Max Unit

Sinusoidal jitter tolerance

(peak-to-peak)

Jitter Frequency =

15 KHz

> 2

UI

Data Rate = 2.97 Gbps

(3G) Pattern = Single

Line Scramble Color

Bar

Jitter Frequency =

100 KHz

> 0.3

Data Rate = 2.97 Gbps

(3G) Pattern = Single

Line Scramble Color

Bar

Jitter Frequency =

148.5 MHz

Data Rate = 2.97 Gbps

(3G) Pattern = Single

Line Scramble Color

Bar

Stratix IV Device Handbook, Volume 4

Chapter 1: DC and Switching Characteristics

1–23

Switching Characteristics

Table 1–24. Stratix IV GX Transceiver Block AC Specification (Note 1), (2) (Part 8 of 8)

-3 Speed

-2 Speed

CommercialSpeed

Grade

Commercial and

Industrial Speed

Grade

-4 Speed

Commercial Speed

Grade

Symbol/

Description

Conditions

Min Typ Max Min Typ Max Min Typ Max Unit

Sinusoidal jitter tolerance

(peak-to-peak)

Jitter Frequency =

20 KHz

> 1

UI

Data Rate =

1.485 Gbps (HD)

Pattern = 75% Color

Bar

Jitter Frequency = 100

KHz Data Rate = 1.485

Gbps (HD) Pattern =

75% Color Bar

> 0.2

UI

Jitter Frequency =

148.5 MHz

Data Rate =

1.485 Gbps (HD)

Pattern =75% Color

Bar

Notes to Table 1–24:

(1) Dedicated refclkpins were used to drive the input reference clocks.

(2) Jitter numbers specified are valid for the stated conditions only.

(3) The jitter numbers for SONET/SDH are compliant to the GR-253-CORE Issue 3 Specification.

(4) The jitter numbers for Fibre Channel are compliant to the FC-PI-4 Specification revision 6.10.

(5) The jitter numbers for XAUI are compliant to the IEEE802.3ae-2002 Specification.

(6) The jitter numbers for PCI Express are compliant to the PCIe Base Specification 2.0.

(7) The jitter numbers for Serial RapidIO are compliant to the RapidIO Specification 1.3.

(8) The jitter numbers for GIGE are compliant to the IEEE802.3-2002 Specification.

(9) The jitter numbers for HiGig are compliant to the IEEE802.3ae-2002 Specification.

(10) The jitter numbers for (OIF) CEI are compliant to the OIF-CEI-02.0 Specification.

(11) The HD-SDI and 3G-SDI jitter numbers are compliant to the SMPTE292M and SMPTE424M Specifications.

(12) The fibre channel transmitter jitter generation numbers are compliant to the specification at δ_Tinteroperability point.

(13) The fibre channel receiver jitter tolerance numbers are compliant to the specification at δ_Rinteroperability point.

Core Performance Specifications

This sections describes the clock tree, PLL, DSP, TriMatrix, and configuration and

JTAG specifications.

Clock Tree Specifications

Table 1–25 lists the clock tree specifications for Stratix IV devices.

Stratix IV Device Handbook, Volume 4

Chapter 1: DC and Switching Characteristics

1–24

Switching Characteristics

Table 1–25. Stratix IV Clock Tree Performance - Preliminary

Performance

Device

EP4SE110

-2/-2x Speed Grade

-3 Speed Grade

-4 Speed Grade

Unit

600

500

450

MHz

EP4SE230

EP4SE290

EP4SE360

EP4SE530

EP4SE680

EP4SGX70

EP4SGX110

EP4SGX230

EP4SGX290

EP4SGX360

EP4SGX530

PLL Specifications

Table 1–26 describes the Stratix IV PLL specifications when operating in both the

commercial junction temperature range (0 to 85×C) and the industrial junction

temperature range (-40 to 100×C).

Table 1–26. Stratix IV PLL Specifications - Preliminary (Part 1 of 2)

Symbol Description

Min

5

Typ

—

50

—

(4)

Max

720 (1)

325

1300

60

Unit

MHz

%

f_IN

Input clock frequency

f_INPFD

Input frequency to the PFD

5

f_{VCO (2)}

f_INDUTY

f_EINDUTY

t_INCCJ

PLL VCO operating Range

600

40

—

45

—

Input clock duty cycle

External feedback clock input duty cycle

Input clock cycle to cycle jitter

60

%

(4)

ps

f_OUT

Output frequency for internal global or regional clock

Output frequency for external clock output

Duty cycle for external clock output (when set to 50%)

Dedicated clock output period jitter

Regular I/O clock output period jitter

External feedback clock compensation time

Time required to reconfigure PLL scan chains

717 (3)

55

MHz

%

f_{OUT_EXT}

t_OUTDUTY

t_{OUTPJ_DC}

t_{OUTPJ_IO}

t_FCOMP

(4)

ps

(4)

ps

10

ns

t_CONFIGPLL

—

SCANCLK

cycles

t_CONFIGPHASE

Time required to reconfigure phase shift

1

—

1

SCANCLK

cycles

f_SCANCLK

t_LOCK

scanclk frequency

—

100

MHz

ms

Time required to lock from end of device configuration

(4)

Stratix IV Device Handbook, Volume 4

Chapter 1: DC and Switching Characteristics

1–25

Switching Characteristics

Table 1–26. Stratix IV PLL Specifications - Preliminary (Part 2 of 2)

Symbol

t_DLOCK

Description

Min

Typ

Max

Unit

Time required to lock dynamically (after switchover or

reconfiguring any non-post-scale counters/delays)

—

(4)

ms

f_{CL B W}

PLL closed-loop low bandwidth range

PLL closed-loop medium bandwidth range

PLL closed-loop high bandwidth range

Accuracy of PLL phase shift

—

10

(4)

—

MHz

ps

t_{PLL_PSERR}

t_ARESET

Minimum pulse width on areset signal

ns

Notes to Table 1–26:

(1) F_INis limited by I/O F_MAX

.

(2) The VCO frequency reported by Quartus II software is after the post scale divider (k) and may be outside the VCO min and max range.

(3) This specification is limited by the lower of the two: I/O F_MAXor F_OUTof the PLL.

(4) Pending silicon characterization.

DSP Block Specifications

Table 1–27 describes the Stratix IV DSP block performance specifications.

Table 1–27. Stratix IV DSP Block Performance Specifications (Note 1) - Preliminary

Resources

Used

Performance

-2/-2x

Speed

Grade

Number of

Multipliers

-3 Speed

Grade

-4 Speed

Grade

Mode

Unit

9×9-bit multiplier

1

4

2

1

490

550

440

490

390

440

405

455

365

405

320

365

375

420

335

375

300

335

MHz

12×12-bit multiplier

18×18-bit multiplier

36×36-bit multiplier

18×18-bit multiply accumulator

18×18-bit multiply adder

18×18-bit multiply adder-signed full precision

18×18-bit multiply adder with loopback (2)

36-bit shift (32 bit data)

Double mode

Notes to Table 1–27:

(1) Maximum is for fully pipelined block with Round and Saturation disabled.

(2) Maximum is for non-pipelined block with loopback input registers disabled and Round and Saturation disabled.

TriMatrix Memory Block Specifications

Table 1–28 describes the Stratix IV TriMatrix memory block specifications.

Stratix IV Device Handbook, Volume 4

Chapter 1: DC and Switching Characteristics

1–26

Switching Characteristics

Table 1–28. Stratix IV TriMatrix Memory Block Performance Specifications Preliminary

Resources Used

Performance

-2 /-2x

Speed

Grade

TriMatrix

Memory

-3 Speed

Grade

-4 Speed

Grade

Memory

Mode

Single port 64×10

ALUTs

Unit

MLAB

0

1

600

333

500

275

450

250

MHz

Simple dual-port 32×20 single clock

Simple dual-port 64×10 single clock

Single-port 256×36

M9K

Block

Simple dual-port 256×36 single CLK

True dual port 512×18 single CLK

Single-port 2K×72

M144K

Simple dual-port 2K×72 dual CLK

Simple dual-port 2K×64 dual CLK (with

ECC)

True dual-port 4K×36 dual CLK

0

1

600

500

450

MHz

Configuration and JTAG Specifications

Table 1–29 lists the Stratix IV configuration mode specifications.

Table 1–29. Stratix IV Configuration Mode Specifications - Preliminary

Programming Mode

DCLK Fmax

Unit

Passive serial

125

40

MHz

Fast passive parallel

Fast active serial

Remote update only in fast AS mode

10

Table 1–30 shows the JTAG timing parameters and values for Stratix IV devices.

Table 1–30. Stratix IV JTAG Timing Parameters and Values - Preliminary

Symbol

Description

TCK clock period

Min

30

14

1

Max

—

Unit

ns

t_JCP

t_JCH

t_JCL

TCK clock high time

—

TCK clock low time

—

t_{JPSU (TDI)}

t_{JPSU (TMS)}

t_JPH

TDI JTAG port setup time

TMS JTAG port setup time

JTAG port hold time

—

3

—

5

—

t_JPCO

JTAG port clock to output

JTAG port high impedance to valid output

JTAG port valid output to high impedance

—

11 (1)

14 (1)

t_JPZX

t_JPXZ

Note to Table 1–30:

(1) A 1 ns adder is required for each V_CCIOvoltage step down from 3.3 V. For example, t_JPCO= 12 ns if V_CCIOof the TDO

I/O bank = 2.5 V, or 13 ns if it equals 1.8 V.

Stratix IV Device Handbook, Volume 4

Chapter 1: DC and Switching Characteristics

1–27

Switching Characteristics

Temperature Sensing Diode Specifications

Table 1–31 lists the specifications for the Stratix IV temperature sensing diode.

Table 1–31. Temperature Sensing Diode Specifications - Preliminary

Symbol

Description

Min

Max

1.01

42

Unit

f_{TSD_INCLK}

TSD Input Clock Frequency (without CLK divider) 0.25

MHz

%

TSD Input Clock Frequency (with CLK divider)

Duty Cycle of TSD Input Clock

38

45

t_{DUTY_TSD_INCLK}

55

Periphery Performance

This section describes periphery performance including high-speed I/O, external

memory interface, and OCT calibration block specifications.

High-Speed I/O Specification

Table 1–32 shows the high-speed I/O timing for Stratix IV devices.

Table 1–32. High-Speed I/O Specifications for Fastest Speed Grade - Preliminary (Note 1), (2), (3), (4) (Part 1 of 2)

-2/-2x Speed Grade

Symbol

Conditions

Min

Typ

Max

Unit

f_IN(input reference clock

frequency) = f_HSDR/ W

Clock boost factor, W = 1 to 40

5

—

717

MHz

f_HSCLK(source synchronous

output clock frequency)

—

5 (5)

—

717

MHz

f_HSDR(data rate)

Serdes factor, J = 3 to 10

150

(6)

—

1600

1250

Mbps

Serdes factor, J = 2, Uses DDR Registers

Serdes factor, J = 1, Uses SDR Register

Serdes factor, J = 3 to 10

(6)

717 (7) Mbps

f_HSDRDPA(DPA data rate)

150

—

1600

Mbps

ps

Transmitter channel-to-channel All differential standards

skew (TCCS)

(5)

Receiver sampling window

(SW)

All differential standards

—

(5)

ps

t_{OUTJITTER_DC}

t_{OUTJITTER_IO}

—

45

—

50

—

(5)

55

(5)

ps

%

—

All differential I/O standards

Tx output clock duty cycle

—

Output t_RISE

Output t_FALL

t_DUTY

DPA run length

UI

Stratix IV Device Handbook, Volume 4

Chapter 1: DC and Switching Characteristics

1–28

Switching Characteristics

Table 1–32. High-Speed I/O Specifications for Fastest Speed Grade - Preliminary (Note 1), (2), (3), (4) (Part 2 of 2)

-2/-2x Speed Grade

Symbol

DPA jitter tolerance

Notes to Table 1–32:

Conditions

Min

Typ

Max

Unit

UI

Data channel peak-to-peak jitter tolerance

(5)

—

(1) When J = 4 to 10, the SERDES block is used.

(2) When J = 1 or 2, the SERDES block is bypassed.

(3) The input clock frequency and the W factor must satisfy the following Left/Right PLL output specification:

150 <= input clock frequency × W <= 1600 MHz.

(4) Specifications for -3 and -4 speed grades will be available after silicon characterization.

(5) Pending silicon characterization.

(6) The minimum specification is dependent on the clock source (for example, PLL or clock pin) and the clock routing resource (global, regional,

or local) utilized. The I/O differential buffer and input register does not have a minimum toggle rate.

(7) Same as device clock tree F_MAX

.

Table 1–33 shows the DPA lock time specifications for Stratix IV devices.

Table 1–33. DPA Lock Time Specifications - Preliminary

Transition

Standard

SPI-4

Training Pattern

00000000001111111111

00001111

Density

10%

25%

50%

100%

—

Min

Unit

(1) Number of repetitions

Parallel Rapid I/O

10010000

Miscellaneous

10101010

01010101

Note to Table 1–33:

(1) Pending silicon characterization.

External Memory Interface Specifications

Table 1–34 through Table 1–43 list the external memory interface specifications for the

Stratix IV device family. Use these tables for memory interface timing analysis.

Table 1–34. Stratix IV Maximum Clock Rate Support for External Memory Interfaces with Half-Rate Controller (Note 1), (2)

(Part 1 of 2)

Stratix IV GX Devices with 1152-Pin (with 24

Transceivers), 1517-Pin, and 1932-Pin Packages

Stratix IV GX Devices with 780-Pin and 1152-Pin (with

16 Transceivers) Packages

–4 Speed Grade

(MHz)

–2 Speed Grade –3 Speed Grade

(MHz) (MHz)

-2x Speed Grade -3 Speed Grade

(MHz) (MHz)

-4 Speed Grade

(MHz)

Row

I/O

Row

I/O

Row

I/O

Banks

(3)

Row

I/O

Row

Column

I/O

Banks

Column

I/O

Banks

Column RowI/O Column

Column

I/O

Banks

Column

I/O

Banks

I/O

Banks

(3)

Memory

Standards

Banks

I/O

Banks

I/O

Banks

(3)

Banks

(3)

Banks

(3)

DDR3 SDRAM (4)

DDR2 SDRAM (4)

DDR SDRAM (4)

533

400

200

333

200

400

333

200

333

200

333

200

333

200

333

200

333

200

333

200

333

200

333

200

333

200

Stratix IV Device Handbook, Volume 4

Chapter 1: DC and Switching Characteristics

1–29

Switching Characteristics

Table 1–34. Stratix IV Maximum Clock Rate Support for External Memory Interfaces with Half-Rate Controller (Note 1), (2)

(Part 2 of 2)

Stratix IV GX Devices with 1152-Pin (with 24

Transceivers), 1517-Pin, and 1932-Pin Packages

Stratix IV GX Devices with 780-Pin and 1152-Pin (with

16 Transceivers) Packages

–4 Speed Grade

(MHz)

–2 Speed Grade –3 Speed Grade

(MHz) (MHz)

-2x Speed Grade -3 Speed Grade

(MHz) (MHz)

-4 Speed Grade

(MHz)

Row

I/O

Row

I/O

Row

I/O

Banks

(3)

Row

I/O

Row

Column

I/O

Banks

Column

I/O

Banks

Column RowI/O Column

Column

I/O

Banks

Column

I/O

Banks

I/O

Banks

(3)

Memory

Standards

Banks

I/O

Banks

I/O

Banks

(3)

Banks

(3)

Banks

(3)

QDRII+SRAM (2.5

clock cycle

400

300

350

300

latency only) (5),

(6)

QDRII SRAM

(1.5-V and 1.8-V

HSTL) (6)

350

400

300

333

300

333

300

333

300

333

300

333

300

333

300

333

300

333

300

333

300

333

300

333

RLDRAM II (1.5-V

and 1.8-V HSTL)

Notes to Table 1–34:

(1) Numbers are preliminary pending characterization. The supported operating frequencies listed here are memory interface maximums for the FPGA device family.

Your design’s actual achievable performance is based on design and system-specific factors, as well as static timing analysis of the completed design.

(2) Column I/Os refer to top and bottom I/Os. Row I/Os refer to left and right I/Os.

(3) The row I/O banks do not support 1.5-V HSTL and SSTL Class II I/O standards.

(4) This applies for interfaces with both modules and components.

(5) The QDRII+ SRAM devices with 2.0 clock cycle latency are not supported due to hardware limitations.

(6) Stratix IV devices in the 780- and 1152-pin packages support ×36 QDRII+/QDRII SRAM at a lower maximum frequency as detailed in the External Memory

Interfaces in Stratix IV Devices chapter in volume 1 of the Stratix IV Device Handbook.

Table 1–35. Stratix IV Maximum Clock Rate Support for External Memory Interfaces with Full-Rate Controller (Note 1), (2),

(3)

-2/-2x Speed Grade (MHz)

-3 Speed Grade (MHz)

-4 Speed Grade (MHz)

Column I/O

Banks

Row I/O

Column I/O

Banks

Row I/O

Column I/O

Banks

Row I/O

Memory Standards

DDR2 SDRAM

Banks (4)

267

200

267

200

233

200

233

200

DDR SDRAM

Notes to Table 1–35:

(1) Numbers are preliminary until characterization is final. The supported operating frequencies listed here are memory interface maximums for

the FPGA device family. Your design’s actual achievable performance is based on design and system-specific factors, as well as static timing

analysis of the completed design.

(2) Column I/Os refer to top and bottom I/Os. Row I/Os refer to left and right I/Os.

(3) This applies for interfaces with both modules and components.

(4) The row I/O banks do not support 1.5 V HSTL and SSTL Class II I/O standards.

Stratix IV Device Handbook, Volume 4

Chapter 1: DC and Switching Characteristics

1–30

Switching Characteristics

Table 1–36. Stratix IV Maximum Clock Rate Support with the ×36 Mode Emulation (Note 1), (2), (3)

-2/-2x Speed Grade (MHz)

-3/-3x Speed Grade (MHz)

–4 Speed Grade (MHz)

Column I/O

Banks

Row I/O Banks

Column I/O

Banks

RowI/OBanks

Column I/O Row I/OBanks

Memory Standards

(4)

Banks

(4)

QDRII+SRAM (2.5

clock cycle latency

only) (4)

300

250

167

250

167

QDRII SRAM (1.5-V

and 1.8-V HSTL)

300

250

167

250

167

Notes to Table 1–36:

(1) Numbers, based on using the half-rate controller, are preliminary until characterization is final. The supported operating frequencies listed here

are memory interface maximums for the FPGA device family. Your design’s actual achievable performance is based on design and

system-specific factors as well as static timing analysis of the completed design.

(2) The performance listed in this table is lower than the performance listed in Table 1–34 due to double loading of the CQ/CQn pins. Double loading

causes degradation in the signal slew rate which affects FPGA delay. Furthermore, due to the difference in slew rate, there is a shift in the setup

and hold time window. You can perform an IBIS simulation to illustrate the shift in the clock signals.

(3) Column I/Os refer to top and bottom I/Os. Row I/Os refer to left and right I/Os.

(4) The QDRII+ SRAM devices with 2.0 clock cycle latency are not supported due to hardware limitations.

External Memory I/O Timing Specifications

Table 1–37 and Table 1–38 list Stratix IV device timing uncertainties on the read and

write data paths. Use these specifications to determine timing margins for source

synchronous paths between a Stratix IV FPGA and an external memory device.

Table 1–37. Sampling Window (SW) - Read Side - Preliminary

Sampling window (ps)

-2/-2x Speed Grade

-3 Speed Grade

-4 Speed Grade

Memory Type

DDR3

I/O Standard

Width

×4

Setup

250

181

231

261

231

261

Hold

250

306

256

286

328

256

286

Setup

300

234

284

314

284

314

Hold

300

326

276

261

291

337

261

291

Setup

374

257

307

337

307

337

Hold

374

326

276

261

291

350

261

291

1.5 SSTL

×8

DDR2 Differential

DDR2 SEIO

DDR1 SEIO

QDRII/II+

1.8 V SSTL

2.5 V SSTL

1.5 V HSTL

×4

×8

×4

×8

×4

×8

×9

×18

×36

×9

QDRII/II+ Emulation

QDRII

1.5 V HSTL

1.8 V HSTL

×18

×36

Stratix IV Device Handbook, Volume 4

Chapter 1: DC and Switching Characteristics

1–31

Switching Characteristics

Table 1–37. Sampling Window (SW) - Read Side - Preliminary

Sampling window (ps)

-3 Speed Grade

-2/-2x Speed Grade

-4 Speed Grade

Memory Type

RLDRAM II

I/O Standard

Width

×9

Setup

181

Hold

306

336

306

336

Setup

234

Hold

326

356

326

356

Setup

257

Hold

1.5 V HSTL

326

356

326

356

×18

×9

211

264

287

181

234

257

×18

211

264

287

Table 1–38. Transmitter Channel-to-Channel Skew (TCCS) - Write Side - Preliminary

TCCS (ps)

-3 Speed Grade

-2/-2x Speed Grade

-4 Speed Grade

Memory Type

DDR3

I/O Standard

Width

×4

Lead

260

229

316

313

260

290

310

229

259

260

290

229

259

Lag

260

246

168

157

248

278

298

246

276

248

278

246

276

Lead

290

230

318

315

262

292

312

230

260

262

292

230

260

Lag

290

355

239

222

358

388

408

355

385

358

388

355

385

Lead

310

250

346

343

285

315

335

250

280

285

315

250

280

Lag

310

388

260

242

391

421

441

388

418

391

421

388

418

1.5 SSTL

×8

DDR2 Differential

DDR2 SEIO

DDR1 SEIO

QDRII/II+

1.8 V SSTL

2.5 V SSTL

1.5 V HSTL

×4

×8

×4

×8

×4

×8

×9

×18

×36

×9

QDRII/II+ Emulation 1.5 V HSTL

QDRII

1.8 V HSTL

×18

×36

×9

RLDRAM II

1.5

×18

×9

×18

DLL and DQS Logic Block Specifications

Table 1–39 describes the DLL frequency range specifications for Stratix IV devices.

Stratix IV Device Handbook, Volume 4

Chapter 1: DC and Switching Characteristics

1–32

Switching Characteristics

Table 1–39. Stratix IV DLL Frequency Range Specifications - Preliminary

Frequency Range (MHz)

Frequency

Mode

-2/-2x Speed Grade

90 - 150

-3 Speed Grade

90 - 140

-4 Speed Grade

90 - 120

Resolution

0

1

2

3

4

5

6

22.5

30

120 - 200

120 - 190

150 - 230

180 - 290

240 - 350

290 - 420

360 - 530

120 - 170

150 - 200

180 - 250

240 - 310

290 - 370

360 - 460

150 - 240

36

180 - 300

45

240 - 370

30

290 - 450

36

360 - 560

45

Table 1–40 describes the DQS phase offset delay per stage for Stratix IV devices.

Table 1–40. DQS Phase Offset Delay Per Setting (Note 1), (2), (3)

Speed Grade

Min

7

Max

13

Unit

ps

-2/-2x

-3

8

14

ps

-4

8.5

15.5

ps

Notes to Table 1–40:

(1) The valid settings for phase offset are -64 to +63 for frequency mode 0 to 3 and -32 to +31 for frequency modes

4 to 6.

(2) The typical value equals the average of the minimum and maximum values.

(3) The delay settings are linear, with a cumulative delay variation of 40 ps for all speed grades. For example, when

using a -2 speed grade and applying a 10 phase offset settings to a 90° phase shift at 400 MHz, the expected

average cumulative delay is [625 ps + (10 * 10.5 ps) 20 psꢀ = 730 ps 20 ps

OCT Calibration Block Specifications

Table 1–41 describes the OCT calibration block specifications for Stratix IV devices.

Table 1–41. OCT Calibration Block Specifications — Preliminary

Symbol

OCTUSRCLK

T_OCTCAL

Description

Min

—

Typ

—

Max

20

Unit

MHz

Clock required by OCT calibration blocks

Number of OCTUSRCLK clock cycles required for OCT R_S/R_T

calibration

—

1000

—

Cycles

T_OCTSHIFT

T_{RS_RT}

Number of OCTUSRCLK clock cycles required for OCT code

to shift out

—

28

—

Cycles

ns

Time required to dynamically switch from R_Sto R_T

2.5

Duty Cycle Distortion (DCD) Specifications

Table 1–42 lists the worst case DCD for Stratix IV devices.

Stratix IV Device Handbook, Volume 4

Chapter 1: DC and Switching Characteristics

1–33

I/O Timing

Table 1–42. DCD on Stratix IV I/O Pins (Note 1), (2) — Preliminary

-2/2x Speed

Grade

-3 Speed Grade -4 Speed Grade

Unit

Symbol

Min

Max

Min

Max

Min

Max

Output Duty Cycle (2)

Notes to Table 1–42:

45

55

45

55

45

55

%

(1) Preliminary DCD specification applies to clock outputs from PLLs, global clock tree, and IOE driving dedicated and

general purpose I/O pins.

(2) Detailed DCD specifications pending silicon characterization.

I/O Timing

Altera offers two ways to determine I/O timing: the Excel-based I/O timing and the

Quartus II Timing Analyzer.

The Excel-based I/O timing provides pin timing performance for each device density

and speed grade. The data is typically used prior to designing the FPGA to get an

estimate of the timing budget as part of the link timing analysis. The Quartus II

Timing Analyzer provides a more accurate and precise I/O timing data based on the

specifics of the design after place-and-route is complete.

1

The Excel-based I/O timing spreadsheet can be downloaded from the Stratix IV

Device Literature webpage.

Programmable IOE Delay

Table 1–43 shows Stratix IV IOE programmable delay settings.

Table 1–43. Stratix IV IOE Programmable Delay

-3 Speed Grade

Parameter

Available Settings

Min Delay (ps)

Max Delay (ps)

D1

D2

16

8

150

330

155

123

118

900

700

2581

897

377

D3

8

D9

16

7

D10

Programmable Output Buffer Delay

Table 1–44 lists the delay chain settings that control the rising and falling edge delays

of the output buffer. Default delay is 0 ps.

Stratix IV Device Handbook, Volume 4

Chapter 1: DC and Switching Characteristics

1–34

Glossary

Table 1–44. Programmable Output Buffer Delay

Symbol

Parameter

Typ

0 (default)

50

Unit

ps

D_OUTBUF

Rising and/or falling edge

delay

ps

100

ps

150

ps

Glossary

Table 1–45 shows the glossary for this chapter.

Table 1–45. Glossary Table

Letter

Subject

—

Definitions

A

B

C

D

—

Differential I/O

Standards

Receiver Input Waveforms

Single-Ended Waveform

Positive Channel (p) = V

IH

V

ID

Negative Channel (n) = V

Ground

IL

V

CM

Differential Waveform

V

ID

p − n = 0 V

V

ID

Transmitter Output Waveforms

Single-Ended Waveform

Positive Channel (p) = V

OH

V

OD

Negative Channel (n) = V

OL

V

CM

Ground

Differential Waveform

V

OD

p − n = 0 V

V

OD

E

—

Stratix IV Device Handbook, Volume 4

Chapter 1: DC and Switching Characteristics

1–35

Glossary

Table 1–45. Glossary Table

Letter

Subject

Definitions

F

f_HSCLK

f_HSDR

Left/Right PLL input clock frequency.

HIGH-SPEED I/O Block: Maximum/minimum LVDS data transfer rate

(f_HSDR= 1/TUI), non-DPA.

f_HSDRDPA

HIGH-SPEED I/O Block: Maximum/minimum LVDS data transfer rate

(f_HSDRDPA= 1/TUI), DPA.

G

H

I

—

J

HIGH-SPEED I/O Block: Deserialization factor (width of parallel data bus).

JTAG Timing Specifications are in the following figure:

JTAG Timing

Specifications

TMS

TDI

t_JCP

t_JCH

t _JCL

t_JPH

t_JPSU

TCK

TDO

t_JPXZ

t_JPZX

t_JPCO

K

L

—

M

N

O

P

PLL

The block diagram shown in the following figure highlights the PLL Specification parameters:

Specifications

Diagram of PLL Specifications (1)

Switchover

CLKOUT Pins

f_{OUT_EXT}

CLK

f_IN

f_INPFD

N

GCLK

RCLK

Counters

C0..C9

f_VCO

VCO

f_OUT

PFD

CP

LF

Core Clock

M

Key

External Feedback

Reconfigurable in User Mode

Note:

(1) CoreClock can only be fed by dedicated clock input pins or PLL outputs.

Q

R

—

R_L

Receiver differential input discrete resistor (external to Stratix IV device).

Stratix IV Device Handbook, Volume 4

Chapter 1: DC and Switching Characteristics

1–36

Glossary

Table 1–45. Glossary Table

Letter

Subject

Definitions

S

SW (sampling

window)

The period of time during which the data must be valid in order to capture it correctly. The

setup and hold times determine the ideal strobe position within the sampling window as

shown in (the following figure):

Bit Time

Sampling Window

(SW)

RSKM

0.5 x TCCS

Timing Diagram

Single-ended

voltage

referenced I/O

standard

The JEDEC standard for SSTl and HSTL I/O defines both the AC and DC input signal values.

The AC values indicate the voltage levels at which the receiver must meet its timing

specifications. The DC values indicate the voltage levels at which the final logic state of the

receiver is unambiguously defined. Once the receiver input has crossed the AC value, the

receiver changes to the new logic state.

The new logic state is then maintained as long as the input stays beyond the AC threshold.

This approach is intended to provide predictable receiver timing in the presence of input

waveform ringing as shown in the following figure:

Single-Ended Voltage Referenced I/O Standard

V_CCIO

V_OH

V_{IH AC}

(

)

V_IH(DC)

V_REF

V_IL(DC)

V_IL(AC

)

V_OL

V_SS

T

t_C

High-speed receiver/transmitter input and output clock period.

The timing difference between the fastest and the slowest output edges, including t_CO

TCCS (channel-

to-channel-skew) variation and clock skew, across channels driven by the same PLL. The clock is included in

the TCCS measurement (refer to the Timing Diagram figure under S in this table)

t_DUTY

HIGH-SPEED I/O Block: Duty cycle on high-speed transmitter output clock.

Timing Unit Interval (TUI)

The timing budget allowed for skew, propagation delays, and data sampling window. (TUI =

1/(Receiver Input Clock Frequency Multiplication Factor) = t_C/w)

t_FALL

Signal high-to-low transition time (80-20%)

Cycle-to-cycle jitter tolerance on PLL clock input

Period jitter on general purpose I/O driven by a PLL

Period jitter on dedicated clock output driven by a PLL

Signal Low-to-high transition time (20-80%)

—

t_INCCJ

t_{OUTPJ_IO}

t_{OUTPJ_DC}

t_RISE

U

—

Stratix IV Device Handbook, Volume 4

Chapter 1: DC and Switching Characteristics

1–37

Documents Referenced

Table 1–45. Glossary Table

Letter

Subject

V_CM(DC)

Definitions

V

DC Common Mode Input Voltage.

V_{IC M}

V_ID

Input Common Mode Voltage: The common mode of the differential signal at the receiver.

Input differential Voltage Swing: The difference in voltage between the positive and

complementary conductors of a differential transmission at the receiver.

V_DIF(AC)

V_DIF(DC)

V_IH

AC differential Input Voltage: Minimum AC input differential voltage required for switching.

DC differential Input Voltage: Minimum DC input differential voltage required for switching.

Voltage Input High: The minimum positive voltage applied to the input which will be accepted

by the device as a logic high.

V_{IH( AC )}

V_{IH( DC)}

V_IL

High-level AC input voltage

High-level DC input voltage

Voltage Input Low: The maximum positive voltage applied to the input which will be accepted

by the device as a logic low.

V_IL(AC)

V_{IL( DC)}

V_OCM

Low-level AC input voltage

Low-level DC input voltage

Output Common Mode Voltage: The common mode of the differential signal at the

transmitter.

V_OD

Output differential Voltage Swing: The difference in voltage between the positive and

complementary conductors of a differential transmission at the transmitter.

W

X

Y

Z

W

HIGH-SPEED I/O BLOCK: Clock Boost Factor

—

Documents Referenced

This chapter references the following documents:

■

External Memory Interfaces in Stratix IV Devices chapter in volume 1 of the Stratix IV

Device Handbook

■

PowerPlay Early Power Estimator User Guide for Stratix III and Stratix IV FPGAs

PowerPlay Power Analysis chapter in the Quartus II Handbook

Stratix IV Device Handbook, Volume 4

Chapter 1: DC and Switching Characteristics

1–38

Document Revision History

Table 1–46 shows the revision history for this document.

Table 1–46. Document Revision History

Date and Document Version

Changes Made

Summary of Changes

November 2008 v2.1

November 2008 v2.0

■ Edited “I/O Timing” section

■ Minor text edits.

—

Minor text edits.

■ Updated Table 1–19, Table 1–32, Table 1–34 -

Table 1–39

August 2008 v1.1

May 2008 v1.0

■ Updated Table 1–1, Table 1–2, Table 1–4,

Minor text edits and an additional note

to Table 1–26.

Table 1–5, and Table 1–26.

■ Removed figures from “Transceiver

Performance Specifications” on page 1–10

that are repeated in the glossary.

Initial release.

—

Stratix IV Device Handbook, Volume 4


型号：	EP4SGX110
厂家：	ALTERA CORPORATION
描述：	Stratix IV Device 的Stratix IV器件
文件：	总40页 (文件大小：408K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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