EP910IDC40-12 [ALTERA]
UV PLD, 12ns, CMOS, CDIP40, WINDOWED, CERDIP-40;
| 型号： | EP910IDC40-12 |
| 厂家： | 
ALTERA CORPORATION |
| 描述： | UV PLD, 12ns, CMOS, CDIP40, WINDOWED, CERDIP-40 CD |
| 文件： | 总42页 (文件大小：719K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Classic
EPLD Family
®
May 1999, ver. 5
Data Sheet
■
■
■
■
Complete device family with logic densities of 300 to 900 usable gates
(see Table 1)
Device erasure and reprogramming with non-volatile EPROM
configuration elements
Fast pin-to-pin logic delays as low as 10 ns and counter frequencies
as high as 100 MHz
24 to 68 pins available in dual in-line package (DIP), plastic J-lead
chip carrier (PLCC), pin-grid array (PGA), and small-outline
integrated circuit (SOIC) packages
Features
■
■
■
Programmable security bit for protection of proprietary designs
100% generically tested to provide 100% programming yield
Programmable registers providing D, T, JK, and SR flipflops with
individual clear and clock controls
■
Software design support featuring the Altera® MAX+PLUS® II
development system on Windows-based PCs, as well as
Sun SPARCstation, HP 9000 Series 700/800, IBM RISC System/6000
workstations, and third-party development systems
Programming support with Altera’s Master Programming Unit
(MPU); programming hardware from Data I/O, BP Microsystems,
and other third-party programming vendors
Additional design entry and simulation support provided by EDIF,
library of parameterized modules (LPM), Verilog HDL, VHDL, and
other interfaces to popular EDA tools from manufacturers such as
Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys,
Synplicity, and VeriBest
■
■
Table 1. Classic Device Features
Feature EP610
EP910
EP910I
EP1810
EP610I
Usable gates
300
16
450
24
900
48
64
20
50
Macrocells
Maximum user I/O pins
22
38
t
f
(ns)
10
12
PD
(MHz)
100
76.9
CNT
Altera Corporation
745
A-DS-CLASSIC-05
Classic EPLD Family Data Sheet
The Altera ClassicTM device family offers a solution to high-speed, low-
power logic integration. Fabricated on advanced CMOS technology,
Classic devices also have a Turbo-only version, which is described in this
data sheet.
General
Description
Classic devices support 100% TTL emulation and can easily integrate
multiple PAL- and GAL-type devices with densities ranging from 300 to
900 usable gates. The Classic family provides pin-to-pin logic delays as
low as 10 ns and counter frequencies as high as 100 MHz. Classic devices
are available in a wide range of packages, including ceramic dual in-line
package (CerDIP), plastic dual in-line package (PDIP), plastic J-lead chip
carrier (PLCC), ceramic J-lead chip carrier (JLCC), pin-grid array (PGA),
and small-outline integrated circuit (SOIC) packages.
EPROM-based Classic devices can reduce active power consumption
without sacrificing performance. This reduced power consumption
makes the Classic family well suited for a wide range of low-power
applications.
Classic devices are 100% generically tested devices in windowed
packages and can be erased with ultra-violet (UV) light, allowing design
changes to be implemented quickly.
Classic devices use sum-of-products logic and a programmable register.
The sum-of-products logic provides a programmable-AND/fixed-OR
structure that can implement logic with up to eight product terms. The
programmable register can be individually programmed for D, T, SR, or
JK flipflop operation or can be bypassed for combinatorial operation. In
addition, macrocell registers can be individually clocked either by a global
clock or by any input or feedback path to the ANDarray. Altera’s
proprietary programmable I/O architecture allows the designer to
program output and feedback paths for combinatorial or registered
operation in both active-high and active-low modes. These features make
it possible to implement a variety of logic functions simultaneously.
Classic devices are supported by Altera’s MAX+PLUS II development
system, a single, integrated package that offers schematic, text—including
VHDL, Verilog HDL, and the Altera Hardware Description Language
(AHDL)—and waveform design entry, compilation and logic synthesis,
simulation and timing analysis, and device programming. The
MAX+PLUS II software provides EDIF 2 0 0 and 3 0 0, LPM, VHDL,
Verilog HDL, and other interfaces for additional design entry and
simulation support from other industry-standard PC- and workstation-
based EDA tools. The MAX+PLUS II software runs on Windows-based
PCs, as well as Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC
System/6000 workstations. These devices also contain on-board logic test
circuitry to allow verification of function and AC specifications during
standard production flow.
746
Altera Corporation
Classic EPLD Family Data Sheet
For more information, see the MAX+PLUS II Programmable Logic
Development System & Software Data Sheet.
f
The Classic architecture includes the following elements:
Functional
Description
■
■
■
■
Macrocells
Programmable registers
Output enable/clock select
Feedback select
Macrocells
Classic macrocells, shown in Figure 1, can be individually configured for
both sequential and combinatorial logic operation. Eight product terms
form a programmable-ANDarray that feeds an ORgate for combinatorial
logic implementation. An additional product term is used for
asynchronous clear control of the internal register; another product term
implements either an output enable or a logic-array-generated clock.
Inputs to the programmable-ANDarray come from both the true and
complement signals of the dedicated inputs, feedbacks from I/O pins that
are configured as inputs, and feedbacks from macrocell outputs. Signals
from dedicated inputs are globally routed and can feed the inputs of all
device macrocells. The feedback multiplexer controls the routing of
feedback signals from macrocells and from I/O pins. For additional
information on feedback select configurations, see Figure 3 on page 749.
Figure 1. Classic Device Macrocell
VCC
Logic Array
Output Enable/Clock Select
Global
Clock
OE
CLK
Q
CLR
Programmable
Register
Feedback
Select
To Logic Array
Input, I/O, and
Macrocell
Feedbacks
Asynchronous Clear
Altera Corporation
747
Classic EPLD Family Data Sheet
The eight product terms of the programmable-ANDarray feed the 8-input
ORgate, which then feeds one input to an XORgate. The other input to the
XORgate is connected to a programmable bit that allows the array output
to be inverted. Altera’s MAX+PLUS II software uses the XORgate to
implement either active-high or active-low logic, or De Morgan’s
inversion to reduce the number of product terms needed to implement a
function.
Programmable Registers
To implement registered functions, each macrocell register can be
individually programmed for D, T, JK, or SR operation. If necessary, the
register can be bypassed for combinatorial operation. During design
compilation, the MAX+PLUS II software selects the most efficient register
operation for each registered function to minimize the logic resources
needed by the design. Registers have an individual asynchronous clear
function that is controlled by a dedicated product term. These registers
are cleared automatically during power-up.
In addition, macrocell registers can be individually clocked by either a
global clock or any input or feedback path to the ANDarray. Altera’s
proprietary programmable I/O architecture allows the designer to
program output and feedback paths for combinatorial or registered
operation in both active-high and active-low modes. These features make
it possible to simultaneously implement a variety of logic functions.
Output Enable/Clock Select
Figure 2 shows the two operating modes (Modes 0 and 1) provided by the
output enable/clock (OE/CLK) select. The OE/CLKselect, which is
controlled by a single programmable bit, can be individually configured
for each macrocell. In Mode 0, the tri-state output buffer is controlled by
a single product term. If the output enable is high, the output buffer is
enabled. If the output enable is low, the output has a high-impedance
value. In Mode 0, the macrocell flipflop is clocked by its global clock input
signal.
In Mode 1, the output enable buffer is always enabled, and the macrocell
register can be triggered by an array clock signal generated by a product
term. This mode allows registers to be individually clocked by any signal
on the ANDarray. With both true and complement signals in the ANDarray,
the register can be configured to trigger on a rising or falling edge. This
product-term-controlled clock configuration also supports gated clock
structures.
748
Altera Corporation
Classic EPLD Family Data Sheet
Figure 2. Classic Output Enable/Clock Select
Mode 0
Output Enable/Clock
Select
VCC
Global
Clock
In Mode 0, the register
is clocked by the global
clock signal. The
OE
AND
Array
CLK
output is enabled by
the logic from the
product term.
Data
Q
OE = Product Term
CLK = Global
Macrocell
CLR
Output Buffer
Mode 1
Output Enable/Clock
Select
Global
Clock
VCC
In Mode 1, the output
is permanently enabled
and the register is
clocked by the product
term, which allows
gated clocks to be
OE
AND
Array
CLK
Data
Q
generated.
OE = Enabled
CLK = Product Term
Macrocell
CLR
Output Buffer
Feedback Select
Each macrocell in a Classic device provides feedback selection that is
controlled by the feedback multiplexer. This feedback selection allows the
designer to feed either the macrocell output or the I/O pin input
associated with the macrocell back into the ANDarray. The macrocell
output can be either the Qoutput of the programmable register or the
combinatorial output of the macrocell. Different devices have different
feedback multiplexer configurations. See Figure 3.
Figure 3. Classic Feedback Multiplexer Configurations
Global Feedback Multiplexer
Quadrant Feedback Multiplexer
Dual Feedback Multiplexer
Quadrant
Global
Q
Q
Q
Global
Quadrant
I/O
I/O
I/O
EP610
EP610I
EP910
EP910I
EP1810
EP1810
Altera Corporation
749
Classic EPLD Family Data Sheet
EP610, EP610I, EP910, and EP910I devices have a global feedback
configuration; either the macrocell output (Q) or the I/O pin input (I/O)
can feed back to the ANDarray so that it is accessible to all other
macrocells.
EP1810 macrocells can have either of two feedback configurations:
quadrant or dual. Most macrocells in EP1810 devices have a quadrant
feedback configuration; either the macrocell output or I/O pin input can
feed back to other macrocells in the same quadrant. Selected macrocells in
EP1810 devices have a dual feedback configuration: the output of the
macrocell feeds back to other macrocells in the same quadrant, and the
I/O pin input feeds back to all macrocells in the device. If the associated
I/O pin is not used, the macrocell output can optionally feed all
macrocells in the device. In this case, the output of the macrocell passes
through the tri-state buffer and uses the feedback path between the buffer
and the I/O pin.
Classic devices contain a programmable security bit that controls access to
the data programmed into the device. When this bit is programmed, a
proprietary design implemented in the device cannot be copied or
retrieved. This feature provides a high level of design security because
data within configuration elements is invisible. The security bit that
controls this function and other program data is reset only when the
device is erased.
Design Security
Timing Model
Device timing can be analyzed with the MAX+PLUS II software, with a
variety of popular industry-standard EDA simulators and timing
analyzers, or with the timing model shown in Figure 4. Devices have fixed
internal delays that allow the user to determine the worst-case timing for
any design. The MAX+PLUS II software provides timing simulation,
point-to-point delay prediction, and detailed timing analysis for system-
level performance evaluation.
Figure 4. Classic Timing Model
Global Clock
Delay
tICS
Input
Delay
tIN
Register
tSU
tH
Output
Delay
tOD
Array Clock
Delay
tIC
tXZ
tZX
Logic Array
Delay
tLAD
tCLR
I/O
Delay
tIO
Feedback
Delay
tFD
750
Altera Corporation
Classic EPLD Family Data Sheet
Timing information can be derived from the timing model and
parameters for a particular device. External timing parameters represent
pin-to-pin timing delays, and can be calculated from the sum of internal
parameters. Figure 5 shows the internal timing relationship for internal
and external delay parameters.
For more information on device timing, refer to Application Note 78
(Understanding MAX 5000 & Classic Timing) in this data book.
f
Altera Corporation
751
Classic EPLD Family Data Sheet
Figure 5. Classic Switching Waveforms
Input Mode
tPD1 = tIN + tLAD + tOD
tPD2 = tIO + tIN + tLAD + tOD
t
and t < 3 ns.
F
R
tIO
Inputs are driven at 3 V
for a logic high and
0 V for a logic low.
I/O Pin
tIN
All timing characteristics
are measured at 1.5 V.
Input Pin
tLAD
tCLR
tOD
c Array Input
Logic Array Output
Output Pin
Global Clock Mode
tR
tCH
tCL
tF
Global Clock Pin
Global Clock at Register
Data from Logic Array
tIN
tICS
tH
tSU
Array Clock Mode
tR
tACH
tACL
tF
Clock Pin
Clock into Logic Array
tIN
tIC
Clock from Logic Array
tASU
tAH
Data from Logic Array
tFD
Register Output to Logic Array
Output Mode
Clock from Logic Array
Data from Logic Array
Output Pin
tOD
tZX
tXZ
High-Impedance
Tri-State
752
Altera Corporation
Classic EPLD Family Data Sheet
Many Classic devices contain a programmable Turbo BitTM option to
control the automatic power-down feature that enables the low-standby-
power mode. When the Turbo Bit option is turned on, the low-standby-
power mode is disabled. All AC values are tested with the Turbo Bit
option turned on. When the device is operating with the Turbo Bit option
turned off (non-Turbo mode), a non-Turbo adder must be added to the
appropriate AC parameter to determine worst-case timing. The non-
Turbo adder is specified in the “AC Operating Conditions” tables for each
Classic device that supports the Turbo mode.
Turbo Bit
Option
Classic devices are fully functionally tested. Complete testing of each
programmable EPROM configuration element and all internal logic
elements before and after packaging ensures 100% programming yield.
See Figure 6 for AC test measurement conditions. These devices also
contain on-board logic test circuitry to allow verification of function and
AC specifications during standard production flow.
Generic Testing
Figure 6. AC Test Conditions
VCC
Power-supply transients can affect AC
measurements. Simultaneous transitions of
multiple outputs should be avoided for
accurate measurement. Threshold tests
must not be performed under AC
R1
885 Ω
To Test
System
Device
Output
conditions. Large-amplitude, fast ground-
current transients normally occur as the
device outputs discharge the load
capacitances. When these transients flow
R2
340 Ω
C1 (includes
JIG capacitance)
through the parasitic inductance between
the device ground pin and the test system
ground, significant reductions in observable
noise immunity can result.
Classic devices can be programmed on 486- and Pentium-based PCs with
the MAX+PLUS II Programmer, an Altera Logic Programmer card, the
MPU, and the appropriate device adapter. The MPU performs continuity
checking to ensure adequate electrical contact between the adapter and
the device.
Device
Programming
Data I/O, BP Microsystems, and other programming hardware
manufacturers also offer programming support for Altera devices. See
Programming Hardware Manufacturers for more information.
Altera Corporation
753
Notes:
EP610 EPLD
■
High-performance, 16-macrocell Classic EPLD
Features
–
–
–
Combinatorial speeds with tPD as fast as 10 ns
Counter frequencies of up to 100 MHz
Pipelined data rates of up to 125 MHz
■
■
Programmable I/O architecture with up to 20 inputs or 16 outputs
and 2 clock pins
EP610 and EP610I devices are pin-, function-, and programming
file-compatible
■
■
Programmable clock option for independent clocking of all registers
Macrocells individually programmable as D, T, JK, or SR flipflops, or
for combinatorial operation
■
Available in the following packages (see Figure 7):
–
–
24-pin small-outline integrated circuit (plastic SOIC only)
24-pin ceramic and plastic dual in-line package (CerDIP and
PDIP)
–
28-pin plastic J-lead chip carrier (PLCC)
Figure 7. EP610 Package Pin-Out Diagrams
Package outlines not drawn to scale. Windows in ceramic packages only.
1
24
23
22
21
20
19
18
17
16
15
14
13
CLK1
INPUT
I/O
VCC
INPUT
I/O
2
3
1
24
23
22
21
20
19
18
17
16
15
14
13
VCC
INPUT
I/O
CLK1
INPUT
I/O
4
3
2
1
28 27 26
25
2
4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
5
I/O
I/O
I/O
I/O
I/O
I/O
NC
3
5
I/O
I/O
6
24
23
22
21
20
19
4
I/O
I/O
6
I/O
I/O
5
I/O
7
I/O
7
I/O
I/O
6
I/O
I/O
8
8
I/O
I/O
7
I/O
I/O
EP610
9
8
I/O
I/O
I/O
9
I/O
9
I/O
I/O
10
11
12
I/O
I/O
10
11
10
11
12
I/O
I/O
INPUT
GND
INPUT
CLK2
INPUT
CLK2
INPUT
GND
12 13 14 15 16 17 18
24-Pin SOIC
EP610
24-Pin DIP
28-Pin PLCC
EP610
EP610I
EP610
EP610I
Altera Corporation
755
Classic EPLD Family Data Sheet
EP610 devices have 16 macrocells, 4 dedicated input pins, 16 I/O pins,
General
Description
and 2 global clock pins (see Figure 8). Each macrocell can access signals
from the global bus, which consists of the true and complement forms of
the dedicated inputs and the true and complement forms of either the
output of the macrocell or the I/O input. The CLK1signal is a dedicated
global clock input for the registers in macrocells 9 through 16. The CLK2
signal is a dedicated global clock input for registers in macrocells 1
through 8.
Figure 8. EP610 Block Diagram
Numbers without parentheses are for DIP and SOIC packages. Numbers in parentheses are for J-lead packages.
2
1
(3)
(2)
INPUT
CLK1
INPUT (27) 23
CLK2 (16) 13
3
(4)
(5)
Macrocell 9
Macrocell 10
Macrocell 11
Macrocell 12
Macrocell 13
Macrocell 14
Macrocell 15
Macrocell 16
(26) 22
(25) 21
(24) 20
(23) 19
(22) 18
(21) 17
(20) 16
(18) 15
Macrocell 1
Macrocell 2
Macrocell 3
Macrocell 4
Macrocell 5
Macrocell 6
Macrocell 7
Macrocell 8
4
5
6
7
8
9
(6)
Global
Bus
(7)
(8)
(9)
(10)
10 (12)
INPUT (17) 14
11 (13) INPUT
Figure 9 shows the typical supply current (I ) versus frequency of EP610
CC
devices.
Figure 9. I vs. Frequency of EP610 Devices
CC
100
Turbo
10
Typical ICC
Active (mA)
V
CC = 5.0 V
TA = 25° C
1.0
0.1
Non-Turbo
1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 80 MHz
Frequency
756
Altera Corporation
Classic EPLD Family Data Sheet
Figure 10 shows the typical output drive characteristics of EP610 devices.
Figure 10. Output Drive Characteristics of EP610 Devices
Drive characteristics may exceed shown curves.
EP610-15 & EP610-20 EPLDs
EP610-25, EP610-30 & EP610-35 EPLDs
200
80
IOL
IOL
150
100
50
60
Typical ICC
Output
Current (mA)
Typical ICC
Output
Current (mA)
VCC = 5.0 V
TA = 25° C
VCC = 5.0 V
TA = 25° C
40
IOH
20
IOH
1
2
3
4
5
0.45
0.45
1
2
3
4
5
VO Output Voltage (V)
VO Output Voltage (V)
EP610I EPLDs
100
80
IOL
60
40
20
Typical ICC
Output
Current (mA)
VCC = 5.0 V
TA = 25° C
IOH
1
2
3
4
5
VO Output Voltage (V)
Altera Corporation
757
Classic EPLD Family Data Sheet
Tables 2 through 7 provide information on absolute maximum ratings,
recommended operating conditions, operating conditions, and
capacitance for EP610 and EP610I devices.
Operating
Conditions
Table 2. EP610 & EP610I Device Absolute Maximum Ratings
Notes (1), (2)
Symbol
Parameter
Conditions
EP610
EP610I
Unit
Min
Max
Min
Max
VCC
VI
Supply voltage
With respect to ground (3)
–2.0
–2.0
–175
–25
7.0
7.0
–2.0
–0.5
7.0
V
DC input voltage
VCC + 0.5
V
IMAX
IOUT
TSTG
TAMB
TJ
DC VCC or ground current
DC output current, per pin
Storage temperature
Ambient temperature
Junction temperature
175
25
mA
mA
° C
° C
° C
No bias
–65
150
135
150
–65
–65
150
135
150
Under bias
–65
Ceramic packages, under
bias
Plastic packages, under bias
135
135
° C
Table 3. EP610 & EP610I Device Recommended Operating Conditions
Note (2)
Symbol
Parameter
Conditions
EP610
Min Max
EP610I
Unit
Min
Max
VCC
VI
Supply voltage
(4)
4.75 (4.5) 5.25 (5.5)
4.75
–0.3
0
5.25
VCC + 0.3
VCC
V
V
Input voltage
–0.3
0
VCC + 0.3
VCC
VO
TA
Output voltage
V
Operating temperature
For commercial use
0
70
0
70
° C
° C
ns
ns
For industrial use
–40
85
–40
85
tR
tF
Input rise time
Input fall time
(5)
(5)
100 (50)
100 (50)
500
500
Table 4. EP610 & EP610I Device DC Operating Conditions
Note (6)
Symbol
Parameter
Conditions
Min
Max
Unit
VIH
VIL
High-level input voltage
2.0
–0.3
2.4
VCC + 0.3
0.8
V
V
Low-level input voltage
VOH
High-level TTL output voltage
High-level CMOS output voltage
Low-level output voltage
IOH = –4 mA DC (7)
V
IOH = –0.6 mA DC (7), (8)
IOL = 4 mA DC (7)
3.84
V
VOL
II
0.45
10
V
I/O pin leakage current of dedicated input VI = VCC or ground
pins
–10
–10
µA
IOZ
Tri-state output leakage current
VO = VCC or ground
10
µA
758
Altera Corporation
Classic EPLD Family Data Sheet
Table 5. EP610 & EP610I Device Capacitance
Note (9)
Symbol
Parameter
Conditions
EP610-15 EP610-25
EP610-20 EP610-30
EP610-35
EP610I
Unit
Min Max Min Max Min Max
CIN
Input pin capacitance
I/O pin capacitance
CLK1pin capacitance
CLK2pin capacitance
VIN = 0 V, f = 1.0 MHz
VOUT = 0 V, f = 1.0 MHz
VIN = 0 V, f = 1.0 MHz
VIN = 0 V, f = 1.0 MHz
10
12
20
20
20
20
20
50
8
8
pF
pF
pF
pF
CI/O
CCLK1
CCLK2
10
12
Table 6. EP610 Device I Supply Current
Notes (2), (10)
Conditions
CC
Symbol
Parameter
Speed
Grade
EP610
Unit
Min
Typ
Max
ICC1
ICC2
ICC3
VCC supply current
VI = VCC or ground, no load
(11), (12)
20
150
µA
(non-Turbo, standby)
VCC supply current
(non-Turbo, active)
VI = VCC or ground, no load,
f = 1.0 MHz (11), (12)
5
10 (15)
mA
VCC supply current
(Turbo, active)
VI = VCC or ground, no load, -15, -20
60
45
90 (115)
60 (75)
mA
mA
f = 1.0 MHz (12)
-25, -30,
-35
Table 7. EP610I Device I Supply Current
Note (10)
CC
Symbol
Parameter
Conditions
EP610I
Unit
Min
Typ
Max
ICC1
ICC2
ICC3
VCC supply current
VI = VCC or ground, no load,
(11), (12)
20
150
µA
mA
mA
(non-Turbo, standby)
VCC supply current
(non-Turbo, active)
VI = VCC or ground, no load,
f = 1.0 MHz (11), (12)
3
8
VCC supply current
(Turbo, active)
VI = VCC or ground, no load,
f = 1.0 MHz (12)
65
105
Altera Corporation
759
Classic EPLD Family Data Sheet
Notes to tables:
(1) See the Operating Requirements for Altera Devices Data Sheet in this data book.
(2) Numbers in parentheses are for industrial-temperature-range devices.
(3) The minimum DC input is –0.3 V. During transitions, the inputs may undershoot to –2.0 V (EP610) or
–0.5 V (EP610I) or overshoot to 7.0 V (EP610) or VCC + 0.5 V (EP610I) for input currents less than 100 mA and periods
less than 20 ns.
(4) For EP610 devices, maximum VCC rise time is 50 ms. For EP610I devices, maximum VCC rise time is unlimited with
monotonic rise.
(5) For EP610-15 and EP610-20 devices: tR and tF = 40 ns.
For EP610-15 and EP610-20 clocks: tR and tF = 20 ns.
(6) These values are specified in Table 3 on page 758.
(7) The IOH parameter refers to high-level TTL or CMOS output current; the IOL parameter refers to low-level TTL
output current.
(8) This parameter does not apply to EP610I devices.
(9) The device capacitance is measured at 25° C and is sample-tested only.
(10) Typical values are for TA = 25° C and VCC = 5 V.
(11) When the Turbo Bit option is not set (non-Turbo mode), EP610 devices enter standby mode if no logic transitions
occur for 100 ns after the last transition. When the Turbo Bit option is not set, EP610I devices enter standby mode if
no logic transitions occur for 75 ns after the last transition.
(12) Measured with a device programmed as a 16-bit counter.
760
Altera Corporation
Classic EPLD Family Data Sheet
Tables 8 and 9 show the timing parameters for EP610-15 and EP610-20
devices.
Table 8. EP610-15 & EP610-20 External Timing Parameters
Notes (1), (2)
Symbol
Parameter
Conditions
EP610-15 EP610-20 Non-Turbo Unit
Adder
(3)
Min Max Min Max
tPD1
tPD2
tPZX
tPXZ
tCLR
fMAX
tSU
Input to non-registered output
I/O input to non-registered output
Input to output enable
C1 = 35 pF
15.0
17.0
15.0
15.0
15.0
20.0
22.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
0.0
ns
ns
C1 = 35 pF
C1 = 35 pF
C1 = 5 pF (4)
C1 = 35 pF
(5)
ns
Input to output disable
ns
Asynchronous output clear time
Maximum clock frequency
Global clock input setup time
Global clock input hold time
Global clock high time
ns
83.3
9.0
0.0
6.0
6.0
62.5
11.0
0.0
MHz
ns
20.0
0.0
tH
ns
tCH
8.0
0.0
ns
tCL
Global clock low time
8.0
0.0
ns
tCO1
tCNT
fCNT
Global clock to output delay
Global clock minimum period
11.0
12.0
13.0
16.0
0.0
ns
0.0
ns
Maximum internal global clock
frequency
(6)
83.3
62.5
0.0
MHz
tASU
tAH
Array clock input setup time
Array clock input hold time
Array clock high time
6.0
6.0
7.0
7.0
1.0
8.0
8.0
9.0
9.0
1.0
20.0
0.0
ns
ns
tACH
tACL
tODH
tACO1
tACNT
fACNT
0.0
ns
Array clock low time
0.0
ns
Output data hold time after clock
Array clock to output delay
Array clock minimum period
C1 = 35 pF (7)
1.0
ns
15.0
14.0
20.0
18.0
20.0
0.0
ns
ns
Array clock internal maximum
frequency
(6)
71.4
55.6
0.0
MHz
Table 9. EP610-15 & EP610-20 Internal Timing Parameters (Part 1 of 2)
Symbol
Parameter
Conditions
EP610-15 EP610-20 Unit
Min Max Min Max
tIN
Input pad and buffer delay
I/O input pad and buffer delay
Logic array delay
4.0
2.0
6.0
5.0
5.0
5.0
4.0
2.0
ns
ns
ns
ns
ns
ns
tIO
tLAD
tOD
tZX
tXZ
11.0
5.0
Output buffer and pad delay
Output buffer enable delay
Output buffer disable delay
C1 = 35 pF
C1 = 35 pF
C1 = 5 pF
5.0
5.0
Altera Corporation
761
Classic EPLD Family Data Sheet
Table 9. EP610-15 & EP610-20 Internal Timing Parameters (Part 2 of 2)
Symbol
Parameter
Conditions
EP610-15 EP610-20 Unit
Min Max Min Max
tSU
tH
Register setup time
5.0
4.0
4.0
7.0
ns
ns
ns
ns
ns
ns
Register hold time
Array clock delay
Global clock delay
Feedback delay
tIC
6.0
2.0
1.0
6.0
11.0
4.0
tICS
tFD
tCLR
1.0
Register clear time
11.0
Tables 10 and 11 show the timing parameters for EP610-25, EP610-30 and
EP610-35 devices.
Table 10. EP610-25, EP610-30 & EP610-35 External Timing Parameters
Notes (1), (2)
Symbol
Parameter
Conditions EP610-25 EP610-30 EP610-35 Non-Turbo Unit
Adder
Min Max Min Max Min Max
(3)
tPD1
tPD2
tPZX
tPXZ
tCLR
fMAX
tSU
Input to non-registered output
I/O input to non-registered output
Input to output enable
C1 = 35 pF
25.0
27.0
25.0
25.0
27.0
30.0
32.0
30.0
30.0
32.0
35.0
37.0
35.0
35.0
37.0
30.0
30.0
30.0
30.0
30.0
0.0
ns
ns
ns
Input to output disable
C1 = 5 pF (4)
C1 = 35 pF
(5)
ns
Asynchronous output clear time
Maximum frequency
ns
47.6
21.0
0.0
41.7
24.0
0.0
37.0
27.0
0.0
MHz
ns
Global clock input setup time
Global clock input hold time
Global clock high time
30.0
0.0
tH
ns
tCH
10.0
10.0
11.0
11.0
12.0
12.0
0.0
ns
tCL
Global clock low time
0.0
ns
tCO1
tCNT
fCNT
Global clock to output delay
Global clock minimum period
15.0
25.0
17.0
30.0
20.0
35.0
0.0
ns
0.0
ns
Maximum internal global clock
frequency
(6)
40.0
33.3
28.6
0.0
MHz
tASU
tAH
Array clock input setup time
Array clock input hold time
Array clock high time
8.0
8.0
12.0
11.0
11.0
1.0
8.0
12.0
12.0
12.0
1.0
30.0
0.0
0.0
0.0
ns
ns
12.0
10.0
10.0
tACH
tACL
tODH
tACO1
tACNT
fACNT
ns
Array clock low time
ns
Output data hold time after clock
Array clock to output delay
Array clock minimum period
C1 = 35 pF (7) 1.0
ns
27.0
25.0
32.0
30.0
37.0
35.0
30.0
0.0
ns
ns
Maximum internal global clock
frequency
(6)
40.0
33.3
28.6
0.0
MHz
762
Altera Corporation
Classic EPLD Family Data Sheet
Table 11. EP610-25, EP610-30 & EP610-35 Internal Timing Parameters
Unit
Symbol
Parameter
Condition
EP610-25
EP610-30
EP610-35
Min Max Min Max Min Max
tIN
Input pad and buffer delay
I/O input pad and buffer delay
Logic array delay
8.0
2.0
9.0
2.0
11.0
2.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tIO
tLAD
tOD
tZX
tXZ
tSU
tH
11.0
6.0
14.0
7.0
15.0
9.0
Output buffer and pad delay
Output buffer enable delay
Output buffer disable delay
Register setup time
C1 = 35 pF
C1 = 35 pF
C1 = 5 pF
6.0
7.0
9.0
6.0
7.0
9.0
11.0
10.0
11.0
10.0
12.0
10.0
Register hold time
tIC
Array clock delay
13.0
1.0
16.0
1.0
17.0
0.0
tICS
tFD
tCLR
Global clock delay
Feedback delay
3.0
5.0
8.0
Register clear time
13.0
16.0
17.0
Notes to tables:
(1) These values are specified in Table 3 on page 758.
(2) See Application Note 78 (Understanding MAX 5000 & Classic Timing) in this data book for information on internal
timing parameters.
(3) The non-Turbo adder must be added to this parameter when the Turbo Bit option is off.
(4) Sample-tested only for an output change of 500 mV.
(5) The fMAX values represent the highest frequency for pipelined data.
(6) Measured with a device programmed as a 16-bit counter.
(7) Sample-tested only. This parameter is a guideline based on extensive device characterization. This parameter
applies for both global and array clocking.
Altera Corporation
763
Classic EPLD Family Data Sheet
Tables 12 and 13 show the timing parameters for EP610I devices.
Table 12. EP610I External Timing Parameters
Notes (1), (2)
Symbol
Parameter
Conditions EP610I-10 EP610I-12 EP610I-15 Non-Turbo Unit
Adder
Min Max Min Max Min Max
(3)
tPD1
tPD2
tPZX
tPXZ
tCLR
fMAX
Input to non-registered output
I/O input to non-registered output
Input to output enable
C1 = 35 pF
10.0
10.0
15.0
13.0
13.0
12.0
12.0
15.0
15.0
15.0
15.0
15.0
18.0
18.0
18.0
25.0
25.0
25.0
25.0
25.0
0.0
ns
ns
ns
Input to output disable
C1 = 5 pF (4)
ns
Asynchronous output clear time C1 = 35 pF
ns
Maximum frequency
(5)
125.0
100.
0
83.3
MHz
tSU
Global clock input setup time
Global clock input hold time
Global clock high time
7.0
0.0
5.0
5.0
9.0
0.0
5.0
5.0
12.0
0.0
5.0
5.0
25
0.0
0.0
0.0
0.0
25.0
0.0
ns
ns
tH
tCH
tCL
ns
Global clock low time
ns
tCO1
tCNT
fCNT
Global clock to output delay
Global clock minimum period
6.5
8.0
8.0
ns
10.0
12.0
15.0
ns
Maximum internal global clock
frequency
(6)
100.0
83.3
66.0
MHz
tASU
tAH
Array clock input setup time
Array clock input hold time
Array clock high time
1.5
5.5
5.0
5.0
1.0
3.0
6.0
5.0
5.0
1.0
4.0
6.0
6.0
6.0
1.0
25.0
0.0
0.0
0.0
ns
ns
ns
ns
ns
tACH
tACL
tODH
Array clock low time
Output data hold time after clock C1 = 35 pF
(7)
tACO1
tACNT
fACNT
Array clock to output delay
Array clock minimum period
12.0
10.0
14.0
12.0
16.0
15.0
25.0
25.0
0.0
ns
ns
Maximum internal array clock
frequency
(6)
100.0
83.3
66.0
MHz
764
Altera Corporation
Classic EPLD Family Data Sheet
Table 13. EP610 Internal Timing Parameters
Symbol
Parameter
Conditions
EP610I-10
EP610I-12
EP610I-15 Unit
Min Max Min Max Min Max
tIN
Input pad and buffer delay
I/O input pad and buffer delay
Logic array delay
1.5
0.0
5.5
3.0
8.0
6.0
4.0
0.0
6.0
2.0
5.0
5.0
4.0
0.0
9.0
2.0
6.0
6.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tIO
tLAD
tOD
tZX
tXZ
tSU
tH
Output buffer and pad delay
Output buffer enable delay
Output buffer disable delay
Register setup time
C1 = 35 pF
C1 = 35 pF
C1 = 5 pF
3.5
3.5
5.0
4.0
5.0
7.0
Register hold time
tIC
Array clock delay
7.5
2.0
1.0
8.5
8.0
2.0
1.0
9.0
10.0
2.0
tICS
tFD
tCLR
Global clock delay
Feedback delay
1.0
Register clear time
12.0
Notes to tables:
(1) These values are specified in Table 3 on page 758.
(2) See Application Note 78 (Understanding MAX 5000 & Classic Timing) in this data book for more information on Classic
timing parameters.
(3) The non-Turbo adder must be added to this parameter when the Turbo Bit option is off.
(4) Sample-tested only for an output change of 500 mV.
(5) The fMAX values represent the highest frequency for pipelined data.
(6) Measured with a device programmed as a 16-bit counter.
(7) Sample-tested only. This parameter is a guideline based on extensive device characterization. This parameter
applies for both global and array clocking.
Altera Corporation
765
Notes:
EP910 EPLD
■
High-performance, 24-macrocell Classic EPLD
Features
–
–
–
Combinatorial speeds with tPD as fast as 12 ns
Counter frequencies of up to 76.9 MHz
Pipelined data rates of up to 125 MHz
■
■
Programmable I/O architecture with up to 36 inputs or 24 outputs
EP910 and EP910I devices are pin-, function-, and programming file-
compatible
■
■
Programmable clock option for independent clocking of all registers
Macrocells individually programmable as D, T, JK, or SR flipflops, or
for combinatorial operation
■
Available in the following packages (see Figure 11)
–
–
44-pin plastic J-lead chip carrier (PLCC)
40-pin ceramic and plastic dual in-line packages (CerDIP and
PDIP)
Figure 11. EP910 Package Pin-Out Diagrams
Package outlines are not drawn to scale. Windows in ceramic packages only.
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
INPUT
INPUT
INPUT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CLK1
INPUT
INPUT
INPUT
I/O
2
3
4
5
6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
6
5
4
3
2 1 44 43 42 41 40
7
8
7
39
38
37
36
35
34
33
32
31
30
29
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
9
8
10
11
12
13
14
15
16
17
18
19
20
9
10
11
12
13
14
15
16
17
I/O
I/O
I/O
INPUT
INPUT
INPUT
CLK2
INPUT
INPUT
INPUT
GND
18 19 20 21 22 23 24 25 26 27 28
40-Pin DIP
44-Pin PLCC
EP910
EP910I
EP910
EP910I
Altera Corporation
767
Classic EPLD Family Data Sheet
Altera EP910 devices can implement up to 450 usable gates of SSI and MSI
General
Description
logic functions. EP910 devices have 24 macrocells, 12 dedicated input
pins, 24 I/O pins, and 2 global clock pins (see Figure 12). Each macrocell
can access signals from the global bus, which consists of the true and
complement forms of the dedicated inputs and the true and complement
forms of either the output of the macrocell or the I/O input. The CLK1and
CLK2signals are the dedicated clock inputs for the registers in macrocells
13 through 24 and 1 through 12, respectively.
Figure 12. EP910 Block Diagram
Numbers without parentheses are for DIP packages. Numbers in parentheses are for J-lead packages.
2
3
4
1
(3) INPUT
(4) INPUT
(5) INPUT
(2) CLK1
INPUT (43) 39
INPUT (42) 38
INPUT (41) 37
(24) 21
CLK2
5
6
(6)
(7)
(40)
(38)
(37)
(36)
(35)
(34)
(33)
(32)
(31)
(30)
(29)
(28)
36
35
34
33
32
31
30
29
28
27
26
25
Macrocell 1
Macrocell 2
Macrocell 3
Macrocell 4
Macrocell 5
Macrocell 6
Macrocell 7
Macrocell 8
Macrocell 9
Macrocell 10
Macrocell 11
Macrocell 12
Macrocell 13
Macrocell 14
Macrocell 15
Macrocell 16
Macrocell 17
Macrocell 18
Macrocell 19
Macrocell 20
Macrocell 21
Macrocell 22
Macrocell 23
Macrocell 24
7
(8)
8
(9)
9
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(18)
Global
Bus
10
11
12
13
14
15
16
17 (19) INPUT
18 (20) INPUT
19 (21) INPUT
INPUT (27) 24
INPUT (26) 23
INPUT (25) 22
768
Altera Corporation
Classic EPLD Family Data Sheet
Figure 13 shows the typical supply current (I ) versus frequency of
CC
EP910 devices.
Figure 13. I vs. Frequency of EP910 Devices
CC
100
Turbo
10
Typical ICC
Active (mA)
VCC = 5.0 V
= 25° C
T
A
1.0
0.1
Non-Turbo
1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 40 MHz
Frequency
Figure 14 shows the typical output drive characteristics of EP910 devices.
Figure 14. Output Drive Characteristics of EP910 Devices
Drive characteristics may exceed shown curves.
EP910 EPLDs
EP910I EPLDs
120
100
80
60
50
40
30
20
10
0
IOL
IOL
Typical IO
Output
Current (mA)
Typical IO
Output
VCC = 5.0 V
TA = 25° C
60
Current (mA)
VCC = 5.0 V
TA = 25° C
40
IOH
20
IOH
0.45
1
2
3
4
5
0.45
1
2
3
4
5
V
O Output Voltage (V)
VO Output Voltage (V)
Altera Corporation
769
Classic EPLD Family Data Sheet
Tables 14 through 18 provide information on absolute maximum ratings,
recommended operating conditions, operating conditions, and
capacitance for EP910 and EP910I devices.
Operating
Conditions
Table 14. EP910 & EP910I Device Absolute Maximum Ratings
Notes (1), (2)
Symbol
Parameter
Conditions
EP910
EP910I
Unit
Min
Max
Min
Max
VCC
VI
Supply voltage
With respect to ground (3)
–2.0
–2.0
–250
–25
7.0
7.0
250
25
–2.0
–0.5
7.0
V
DC input voltage
VCC + 0.5
V
IMAX
IOUT
TSTG
TAMB
TJ
DC VCC or ground current
DC output current, per pin
Storage temperature
Ambient temperature
Junction temperature
mA
mA
° C
° C
° C
No bias
–65
150
135
150
–65
–65
150
135
150
Under bias
–65
Ceramic packages, under
bias
Plastic packages, under
bias
135
135
° C
Table 15. EP910 & EP910I Device Recommended Operating Conditions
Note (2)
Symbol
Parameter
Conditions
EP910
Min Max
EP910I
Unit
Min
Max
VCC
VI
Supply voltage
(4)
4.75 (4.5) 5.25 (5.5)
4.75
–0.3
0
5.25
VCC + 0.3
VCC
V
V
Input voltage
–0.3
0
VCC + 0.3
VCC
VO
TA
Output voltage
V
Operating temperature
For commercial use
0
70
0
70
° C
° C
ns
ns
For industrial use
–40
85
tR
tF
Input rise time
Input fall time
(5)
(5)
100 (50)
100 (50)
500
500
Table 16. EP910 & EP910I Device DC Operating Conditions
Notes (6), (7)
Symbol
Parameter
Conditions
Min
Max
Unit
VIH
VIL
High-level input voltage
2.0
–0.3
2.4
VCC + 0.3
0.8
V
V
Low-level input voltage
VOH
High-level TTL output voltage
High-level CMOS output voltage
Low-level output voltage
IOH = –4 mA DC (8)
V
IOH = –0.6 mA DC (8), (9)
IOL = 4 mA DC (8)
3.84
V
VOL
II
0.45
10
V
I/O leakage current of dedicated input pins VI = VCC or ground
Tri-state output leakage current VO = VCC or ground
–10
–10
µA
µA
IOZ
10
770
Altera Corporation
Classic EPLD Family Data Sheet
Table 17. EP910 & EP910I Device Capacitance
Note (6)
Symbol
Parameter
Conditions
EP910
Max
EP910I
Min Max
Unit
Min
CIN
Input pin capacitance
I/O pin capacitance
CLK1pin capacitance
CLK2pin capacitance
VIN = 0 V, f = 1.0 MHz
VOUT = 0 V, f = 1.0 MHz
VIN = 0 V, f = 1.0 MHz
VIN = 0 V, f = 1.0 MHz
20
20
20
60
8
8
pF
pF
pF
pF
CI/O
CCLK1
CCLK2
10
12
Table 18. EP910 & EP910I Device I Supply Current
Notes (2), (6), (7)
CC
Symbol
Parameter
Conditions
EP910
EP910I
Unit
Min Typ Max Min Typ Max
ICC1
ICC2
ICC3
VCC supply current
VI = VCC or ground, no load
(10), (11)
20
150
60
150
µA
mA
mA
(non-Turbo, standby)
VCC supply current
(non-Turbo, active)
VI = VCC or ground, no load,
f = 1.0 MHz (10), (11)
6
20
4
12
VCC supply current
(Turbo, active)
VI = VCC or ground, no load,
f = 1.0 MHz (11)
45
80
120
150
(100)
Notes to tables:
(1) See the Operating Requirements for Altera Devices Data Sheet in this data book.
(2) Numbers in parentheses are for industrial-temperature-range devices.
(3) The minimum DC input is –0.3 V. During transitions, the inputs may undershoot to –2.0 V (EP910) or
–0.5 V (EP910I) or overshoot to 7.0 V (EP910) or VCC + 0.5 V (EP910I) for input currents less than 100 mA and periods
less than 20 ns.
(4) Maximum VCC rise time for EP910 devices = 50 ms; for EP910I devices, maximum VCC rise time is unlimited with
monotonic rise.
(5) For all clocks: tR and tF = 100 ns (50 ns for the industrial-temperature-range version).
(6) These values are specified in Table 15 on page 770.
(7) The device capacitance is measured at 25° C and is sample-tested only.
(8) The IOH parameter refers to high-level TTL or CMOS output current; the IOL parameter refers to low-level TTL
output current.
(9) This parameter does not apply to EP910I devices.
(10) When the Turbo Bit option is not set (non-Turbo mode), an EP910 device will enter standby mode if no logic
transitions occur for 100 ns after the last transition, and an EP910I device will enter standby mode if no logic
transitions occur for 75 ns after the last transition.
(11) Measured with a device programmed as a 24-bit counter.
Altera Corporation
771
Classic EPLD Family Data Sheet
Tables 19 and 20 show the timing parameters for EP910 devices.
Table 19. EP910 External Timing Parameters
Notes (1), (2)
Symbol
Parameter
Conditions EP910-30 EP910-35 EP910-40
Min Max Min Max Min Max
Non-
Turbo
Adder (3)
Unit
tPD1
tPD2
tPZX
tPXZ
tCLR
fMAX
tSU
Input to non-registered output
I/O input to non-registered output
Input to output enable
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 5 pF (4)
C1 = 35 pF
(5)
30.0
33.0
30.0
30.0
33.0
35.0
38.0
35.0
35.0
38.0
40.0
43.0
40.0
40.0
43.0
30.0
30.0
30.0
30.0
30.0
0.0
ns
ns
ns
Input to output disable
ns
Asynchronous output clear time
Maximum frequency
ns
41.7
24.0
0.0
37.0
27.0
0.0
32.3
31.0
0.0
MHz
ns
Global clock input setup time
Global clock input hold time
Global clock high time
30.0
0.0
tH
ns
tCH
12.0
12.0
13.0
13.0
15.0
15.0
0.0
ns
tCL
Global clock low time
0.0
ns
tCO1
tCNT
fCNT
Global clock to output delay
C1 = 35 pF
18
21.0
35.0
24.0
40.0
0.0
ns
Global clock minimum clock period (6)
30.0
0.0
ns
Maximum internal global clock
frequency
(6)
33.3
28.6
25.0
0.0
MHz
tASU
tAH
Array clock input setup time
Array clock input hold time
Array clock high time
10.0
15.0
15.0
15.0
10.0
15.0
16.0
16.0
1.0
10.0
15.0
17.0
17.0
1.0
30.0
0.0
0.0
0.0
ns
ns
tACH
tACL
tODH
tACO1
tACNT
fACNT
ns
Array clock low time
ns
Output data hold time after clock
Array clock to output delay
Array clock minimum clock period
C1 = 35 pF (7) 1.0
C1 = 35 pF
ns
33.0
30.0
38.0
35.0
43.0
40.0
30.0
0.0
ns
ns
Maximum internal array clock
frequency
(6)
33.3
28.6
25.0
0.0
MHz
772
Altera Corporation
Classic EPLD Family Data Sheet
Table 20. EP910 Internal Timing Parameters
EP910-30
EP910-35
EP910-40 Unit
Symbol
Parameter
Condition
Min Max Min Max Min Max
tIN
Input pad and buffer delay
I/O input pad and buffer delay
Logic array delay
9.0
3.0
10.0
3.0
13.0
3.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tIO
tLAD
tOD
tZX
tXZ
tSU
tH
14.0
7.0
16.0
9.0
17.0
10.0
10.0
10.0
Output buffer and pad delay
Output buffer enable delay
Output buffer disable delay
Register setup time
C1 = 35 pF
C1 = 35 pF
C1 = 5 pF
7.0
9.0
7.0
9.0
12.0
12.0
13.0
12.0
15.0
12.0
Register hold time
tIC
Array clock delay
17.0
2.0
19.0
2.0
20.0
1.0
tICS
tFD
tCLR
Global clock delay
Feedback delay
4.0
6.0
8.0
Register clear time
17.0
19.0
20.0
Notes to tables:
(1) These values are specified in Table 15 on page 770.
(2) See Application Note 78 (Understanding MAX 5000 & Classic Timing) in this data book for more information on Classic
timing parameters.
(3) The non-Turbo adder must be added to this parameter when the Turbo Bit option is off.
(4) Sample-tested only for an output change of 500 mV.
(5) The fMAX values represent the highest frequency for pipelined data.
(6) Measured with a device programmed as a 24-bit counter.
(7) Sample-tested only. This parameter is a guideline based on extensive device characterization and applies for both
global and array clocking.
Altera Corporation
773
Classic EPLD Family Data Sheet
Tables 21 and 22 show the timing parameters for EP910I devices.
Table 21. EP910I External Timing Parameters
Notes (1), (2)
Symbol
Parameter
Conditions EP910I-12 EP910I-15 EP910I-25 Non-Turbo Unit
Adder
(3)
Min Max Min Max Min Max
tPD1
tPD2
tPZX
tPXZ
Input to non-registered output
I/O input to non-registered output
Input to output enable
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
12.0
12.0
15.0
15.0
15.0
15.0
18.0
18.0
25.0
25.0
28.0
28.0
40.0
40.0
40.0
40.0
ns
ns
ns
ns
Input to output disable
C1 = 35 pF
(4)
tCLR
fMAX
tSU
Asynchronous output clear time
Global clock maximum frequency
Global clock input setup time
Global clock input hold time
Global clock high time
C1 = 35 pF
(5)
15.0
18.0
28.0
40.0
0.0
ns
MHz
ns
125.0
8.0
100.0
11.0
0.0
62.5
16.0
0.0
40.0
0.0
tH
0.0
ns
tCH
5.0
6.0
10.0
10.0
0.0
ns
tCL
Global clock low time
5.0
6.0
0.0
ns
tCO1
tCNT
fCNT
Global clock to output delay
8.0
9.0
14.0
25.0
0.0
ns
Global clock minimum clock period C1 = 35 pF
13.0
15.0
40.0
0.0
ns
Maximum internal global clock
frequency
(6)
76.9
66.6
40.0
MHz
tASU
tAH
Array clock input setup time
Array clock input hold time
Array clock high time
3.0
6.0
6.0
6.0
1.0
4.0
7.0
7.5
7.5
1.0
8.0
8.0
40.0
ns
ns
ns
ns
ns
tACH
tACL
tODH
12.5
12.5
1.0
Array clock low time
Output data hold time after clock
C1 = 35 pF
(7)
tACO1
tACNT
fACNT
Array clock to output delay
C1 = 35 pF
16.0
13.0
18.0
15.0
22.0
25.0
40.0
40.0
ns
ns
Array clock minimum clock period
Maximum internal array clock
frequency
(6)
76.9
66.6
40.0
MHz
774
Altera Corporation
Classic EPLD Family Data Sheet
Table 22. EP910I Internal Timing Parameters
Symbol
Parameter
Condition
EP910I-12 EP910I-15 EP910I-25 Unit
Min Max Min Max Min Max
tIN
Input pad and buffer delay
I/O input pad and buffer delay
Logic array delay
2.0
0.0
8.0
2.0
5.0
5.0
3.0
0.0
9.0
3.0
6.0
6.0
2.0
0.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tIO
tLAD
tOD
tZX
tXZ
tSU
tH
17.0
6.0
Output buffer and pad delay
Output buffer enable delay
Output buffer disable delay
Register setup time
C1 = 35 pF
C1 = 35 pF
C1 = 5 pF
9.0
9.0
4.0
4.0
5.0
6.0
5.0
Register hold time
11.0
tIC
Array clock delay
12.0
4.0
12.0
3.0
14.0
6.0
tICS
tFD
tCLR
Global clock delay
Feedback delay
1.0
1.0
3.0
Register clear time
11.0
12.0
20.0
Notes to tables:
(1) These values are specified in Table 15 on page 770.
(2) See Application Note 78 (Understanding MAX 5000 & Classic Timing) in this data book for information on internal
timing parameters.
(3) The non-Turbo adder must be added to this parameter when the Turbo Bit option is off.
(4) Sample-tested only for an output change of 500 mV.
(5) The fMAX values represent the highest frequency for pipelined data.
(6) Measured with the device programmed as a 24-bit counter.
(7) Sample-tested only. This parameter is a guideline based on extensive device characterization and applies for both
global and array clocking.
Altera Corporation
775
Notes:
EP1810 EPLD
■
High-performance, 48-macrocell Classic EPLD
Features
–
–
–
Combinatorial speeds with tPD as fast as 20 ns
Counter frequencies of up to 50 MHz
Pipelined data rates of up to 62.5 MHz
■
■
■
Programmable I/O architecture with up to 64 inputs or 48 outputs
Programmable clock option for independent clocking of all registers
Macrocells individually programmable as D, T, JK, or SR flipflops, or
for combinatorial operation
■
Available in the following packages (see Figure 15)
–
–
68-pin ceramic pin-grid array (PGA)
68-pin plastic J-lead chip carrier (PLCC)
Figure 15. EP1810 Package Pin-Out Diagrams
Package outlines not drawn to scale. See Table 32 on page 785 of this data sheet for PGA package pin-out information.
Windows in ceramic packages only.
L
10
11
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
I/O
I/O
I/O
K
J
I/O
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
I/O
I/O
I/O
I/O
INPUT
INPUT
INPUT
CLK1/INPUT
VCC
INPUT
INPUT
INPUT
CLK4/INPUT
VCC
H
G
F
Bottom
View
CLK2/INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
I/O
CLK3/INPUT
INPUT
INPUT
INPUT
I/O
E
D
C
B
A
I/O
I/O
I/O
1
2
3
4
5
6
7
8
9
10 11
68-Pin PGA
EP1810
68-Pin PLCC
EP1810
Altera Corporation
777
Classic EPLD Family Data Sheet
Altera EP1810 devices offer LSI density, TTL-equivalent speed, and low-
General
Description
power consumption. EP1810 devices have 48 macrocells, 16 dedicated
input pins, and 48 I/O pins (see Figure 16). EP1810 devices are divided
into four quadrants, each containing 12 macrocells. Of the 12 macrocells
in each quadrant, 8 have quadrant feedback and are “local” macrocells
(see “Feedback Select” on page 749 of this data sheet for more
information). The remaining 4 macrocells in the quadrant are “global”
macrocells. Both local and global macrocells can access signals from the
global bus, which consists of the true and complement forms of the
dedicated inputs and the true and complement forms of the feedbacks
from the global macrocells.
EP1810 devices also have four dedicated inputs (one in each quadrant)
that can be used as quadrant clock inputs. If the dedicated input is used
as a clock pin, the input feeds the clock input of all registers in that
particular quadrant.
778
Altera Corporation
Classic EPLD Family Data Sheet
Figure 16. EP1810 Block Diagram
Pin numbers are for J-lead packages. Pin numbers in parentheses are for PGA packages.
Quadrant A
Quadrant D
Macrocell 48
(F1)
(G2)
(G1)
(E1) 68
(E2) 67
(D1) 66
(D2) 65
(C1) 64
(C2) 63
(B1) 62
(B2) 61
(A2) 60
(A3) 59
(B3) 58
(A4) 57
2
3
4
Macrocell 1
Macrocell 2
Macrocell 3
Macrocell 4
Macrocell 5
Macrocell 6
Macrocell 7
Macrocell 8
Macrocell 9
Macrocell 10
Macrocell 11
Macrocell 12
Macrocell 47
Macrocell 46
Macrocell 45
Macrocell 44
Macrocell 43
Macrocell 42
Macrocell 41
Macrocell 40
Macrocell 39
Macrocell 38
Macrocell 37
5 (H2)
6 (H1)
7 (J2)
8 (J1)
9 (K1)
10 (K2)
11 (L2)
12 (K3)
13 (L3)
(K4)
14
INPUT
INPUT
(B4) 56
(A5) 55
(B5) 54
(A6) 53
(A7) 51
(B7) 50
(A8) 49
(B8) 48
INPUT
(L4)
15
16 (K5)
INPUT
INPUT
INPUT
17
19
20
Global
Bus
(L5)
(L6)
(K7)
INPUT/CLK1
INPUT/CLK2
INPUT
INPUT/CLK4
INPUT/CLK3
INPUT
21 (L7)
(K8)
INPUT
INPUT
INPUT
22
INPUT
Quadrant B
Quadrant C
23 (L8)
24 (K9)
25 (L9)
26(L10)
27(K10)
28(K1)
29(J10)
30 (J1)
31(H10)
32(H1)
33(G10)
34(G1)
(A9) 47
Macrocell 36
Macrocell 35
Macrocell 34
Macrocell 33
Macrocell 32
Macrocell 31
Macrocell 30
Macrocell 29
Macrocell 28
Macrocell 27
Macrocell 26
Macrocell 25
Macrocell 13
Macrocell 14
Macrocell 15
Macrocell 16
Macrocell 17
Macrocell 18
Macrocell 19
Macrocell 20
Macrocell 21
Macrocell 22
Macrocell 23
Macrocell 24
(B9) 46
(A10) 45
(B10) 44
(B11) 43
(C11) 42
(C10) 41
(D11) 40
(D10) 39
(E11) 38
(E10) 37
(F11) 36
Global Macrocells
Local Macrocells
Altera Corporation
779
Classic EPLD Family Data Sheet
Figure 17 shows the typical supply current (I ) versus frequency for
CC
EP1810 EPLDs.
Figure 17. I vs. Frequency of EP1810 Devices
CC
EP1810
100
10
Typical ICC
Active (mA)
VCC = 5.0 V
= 25° C
T
A
1.0
0.1
10 kHz 100 kHz
1 MHz
10 MHz 60 MHz
Frequency
Figure 18 shows the output drive characteristics of EP1810 devices.
Figure 18. Output Drive Characteristics of EP1810 Devices
Drive characteristics may exceed shown curves.
EP1810-20 & EP1810-25 EPLDs
EP1810-35 & EP1810-45 EPLDs
200
80
IOL
150
60
IOL
Typical IO
Output
Current (mA)
Typical IO
Output
Current (mA)
VCC = 5.0 V
TA = 25° C
VCC = 5.0 V
TA = 25° C
100
50
40
IOH
20
IOH
1
2
3
4
5
1
2
3
4
5
VO Output Voltage (V)
V
O Output Voltage (V)
780
Altera Corporation
Classic EPLD Family Data Sheet
Tables 23 through 27 provide information on absolute maximum ratings,
recommended operating conditions, operating conditions, and
capacitance for EP1810 devices.
Operating
Conditions
Table 23. EP1810 Device Absolute Maximum Ratings
Notes (1), (2)
Symbol
Parameter
Conditions
Min
Max
Unit
VCC
VI
Supply voltage
With respect to ground (3)
With respect to ground (3)
–2.0 (–0.5)
–2.0 (–0.5)
–300 (–400)
–25
7.0
7.0
V
DC input voltage
V
IMAX
IOUT
TSTG
TAMB
TJ
DC VCC or ground current
DC output current, per pin
Storage temperature
Ambient temperature
Junction temperature
300 (400)
25
mA
mA
° C
° C
° C
° C
No bias
–65
150
Under bias
–65
135
Ceramic packages, under bias
Plastic packages, under bias
150
135
Table 24. EP1810 Device Recommended Operating Conditions
Note (2)
Symbol
Parameter
Conditions
Min
Max
Unit
VCC
VI
Supply voltage
(4)
4.75 (4.5)
5.25 (5.5)
V
V
Input voltage
–0.3
0
VCC + 0.3
VO
TA
Output voltage
VCC
70
V
Operating temperature
For commercial use
0
° C
° C
ns
ns
For industrial use
–40
85
tR
tF
Input rise time
Input fall time
(5)
(5)
50
50
Table 25. EP1810 Device DC Operating Conditions
Notes (6), (7)
Symbol
Parameter
Conditions
Min
Max
Unit
VIH
VIL
High-level input voltage
2.0
–0.3
2.4
VCC + 0.3
0.8
V
V
Low-level input voltage
VOH
High-level TTL output voltage
High-level CMOS output voltage
Low-level output voltage
IOH = –4 mA DC (8)
V
IOH = –0.6 mA DC (8)
IOL = 4 mA DC (8)
3.84
V
VOL
II
0.45
10
V
I/O pin leakage current of dedicated VI = VCC or ground
input pins
–10
–10
µA
IOZ
Tri-state output leakage current
VO = VCC or ground
10
µA
Altera Corporation
781
Classic EPLD Family Data Sheet
Table 26. EP1810 Device Capacitance
Note (9)
Symbol
Parameter
Conditions
Min
Max Unit
CIN
Input pin capacitance
I/O pin capacitance
VIN = 0 V, f = 1.0 MHz
VOUT = 0 V, f = 1.0 MHz
VIN = 0 V, f = 1.0 MHz
VIN = 0 V, f = 1.0 MHz
20
20
pF
pF
pF
pF
CIO
CCLK1
CCLK2
CCLK1 pin capacitance
CCLK2 pin capacitance
25
160
Table 27. EP1810 Device I Supply Current
Notes (2), (6), (7)
CC
Symbol
Parameter
Conditions
Speed Min
Grade
Typ
Max Unit
ICC1
ICC2
ICC3
VCC supply current
VI = VCC or ground, no load, -20, -25
(10)
50
35
150
150
µA
µA
(non-Turbo, standby)
VCC supply current
(non-Turbo, active)
-35, -45
VI = VCC or ground, no load, -20, -25
f = 1.0 MHz (10)
20
40
mA
mA
-35, -45
10
30 (40)
VCC supply current (Turbo, active) VI = VCC or ground, no load -20, -25
f = 1.0 MHz (10)
180
100
225 (250) mA
180 (240) mA
-35, -45
Notes to tables:
(1) See the Operating Requirements for Altera Devices Data Sheet in this data book.
(2) Numbers in parentheses are for industrial-temperature-range devices.
(3) The minimum DC input is –0.3 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to 7.0 V for
input currents less than 100 mA and periods less than 20 ns.
(4) Maximum VCC rise time is 50 ms.
(5) For EP1810 clocks: tR and tF = 100 ns (50 ns for industrial-temperature-range versions).
(6) Typical values are for TA = 25° C and VCC = 5 V.
(7) These values are specified in Table 24 on page 781.
(8) The IOH parameter refers to high-level TTL or CMOS output current; the IOL parameter refers to low-level TTL
output current.
(9) The device capacitance is measured at 25° C and is sample-tested only.
(10) Measured with a device programmed as four 12-bit counters.
782
Altera Corporation
Classic EPLD Family Data Sheet
Tables 28 through 31 show the timing parameters for EP1810-20,
EP1810-25, EP1810-35, and EP1810-45 devices.
Table 28. EP1810-20 & EP1810-25 External Timing Parameters
Note (1)
Symbol
Parameter
Conditions
EP1810-20 EP1810-25 Non-Turbo Unit
Adder
(2)
Min Max Min Max
tPD1
tPD2
tSU
Input to non-registered output
I/O input to non-registered output
Global clock setup time
C1 = 35 pF
20.0
22.0
25.0
28.0
25.0
25.0
25.0
0.0
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
C1 = 35 pF
13.0
0.0
8.0
8.0
17.0
0.0
tH
Global clock hold time
tCH
Global clock high time
10.0
10.0
0.0
tCL
Global clock low time
0.0
tCO1
tCNT
fCNT
tASU
tAH
Global clock to output delay
Minimum global clock period
Maximum internal frequency
Array clock setup time
C1 = 35 pF
15.0
20.0
18.0
25.0
0.0
(3)
(3)
0.0
50.0
8.0
40.0
10.0
10.0
0.0
25.0
0.0
Array clock hold time
8.0
tACO1
tODH
tACNT
fACNT
Array clock to output delay
Output data hold time after clock
Array clock maximum clock period
C1 = 35 pF
20.0
20.0
25.0
25.0
25.0
0.0
C1 = 35 pF (4)
1.0
1.0
(3)
(3)
0.0
Maximum internal array clock
frequency
50.0
62.5
40.0
50.0
0.0
fMAX
Maximum clock frequency
(5)
0.0
MHz
Table 29. EP1810-20 and EP1810-25 Internal Timing Parameters
Symbol
Parameter
Conditions
EP1810-20 EP1810-25 Non-Turbo Unit
Adder
(2)
Min Max Min Max
tIN
Input pad and buffer delay
I/O input pad and buffer delay
Logic array delay
5.0
2.0
9.0
6.0
6.0
6.0
7.0
3.0
0.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tIO
0.0
25.0
0.0
tLAD
tOD
tZX
tXZ
tSU
tH
12.0
6.0
Output buffer and pad delay
Output buffer enable delay
Output buffer disable delay
Register setup time
C1 = 35 pF
C1 = 35 pF
6.0
0.0
C1 = 5 pF (6)
6.0
0.0
8.0
5.0
10.0
10.0
0.0
Register hold time
0.0
tIC
Array clock delay
9.0
4.0
3.0
9.0
12.0
5.0
25.0
0.0
tICS
tFD
tCLR
Global clock delay
Feedback delay
3.0
–25.0
25.0
Register clear time
12.0
Altera Corporation
783
Classic EPLD Family Data Sheet
Table 30. EP1810-35 & EP1810-45 External Timing Parameters
Note (1)
Symbol
Parameter
Conditions
EP1810-35 EP1810-45 Non-Turbo Unit
Adder
Min Max Min Max
(2)
tPD1
tPD2
tSU
Input to non-registered output
I/O input to non-registered output
Global clock setup time
C1 = 35 pF
35.0
40.0
45.0
50.0
30.0
30.0
30.0
0.0
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
C1 = 35 pF
25.0
0.0
30.0
0.0
tH
Global clock hold time
tCH
Global clock high time
12.0
12.0
15.0
15.0
0.0
tCL
Global clock low time
0.0
tCO1
tCNT
fCNT
tASU
tAH
Global clock to output delay
Minimum global clock period
Maximum internal frequency
Array clock setup time
C1 = 35 pF
20.0
35.0
25.0
45.0
0.0
(3)
(3)
0.0
28.6
10.0
15.0
22.2
11.0
18.0
0.0
30.0
0.0
Array clock hold time
tACO1
tODH
tACNT
fACNT
Array clock to output delay
Output data hold time after clock
Array clock maximum clock period
C1 = 35 pF
35.0
35.0
45.0
45.0
30.0
C1 = 35 pF (4)
1.0
1.0
(3)
(3)
0.0
0.0
Maximum internal array clock
frequency
28.6
40
22.2
33.3
fMAX
Maximum clock frequency
(5)
0.0
MHz
Table 31. EP1810-35 & EP1810-45 Internal Timing Parameters
Non-Turbo
Adder
Symbol
Parameter
Conditions
EP1810-35 EP1810-45
Min Max Min Max
Unit
(2)
tIN
Input pad and buffer delay
I/O input pad and buffer delay
Logic array delay
7.0
5.0
6.0
5.0
0.0
0.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tIO
tLAD
tOD
tZX
tXZ
tSU
tH
19.0
9.0
28.0
11.0
11.0
11.0
30.0
0.0
Output buffer and pad delay
Output buffer enable delay
Output buffer disable delay
Register setup time
C1 = 35 pF
C1 = 35 pF
9.0
0.0
C1 = 5 pF (6)
9.0
0.0
10.0
15.0
10.0
18.0
0.0
Register hold time
0.0
tIC
Array clock delay
19.0
4.0
28.0
8.0
30.0
0.0
tICS
tFD
tCLR
Global clock delay
Feedback delay
6.0
7.0
–30.0
30.0
Register clear time
24.0
32.0
784
Altera Corporation
Classic EPLD Family Data Sheet
Notes to tables:
(1) These values are specified in Table 24 on page 781.
(2) The non-Turbo adder must be added to this parameter when the Turbo Bit option is off.
(3) Measured with a device programmed as four 12-bit counters.
(4) Sample-tested only. This parameter is a guideline based on extensive device characterization. This parameter
applies for both global and array clocking.
(5) The fMAX values represent the highest frequency for pipelined data.
(6) Sample-tested only for an output change of 500 mV.
Table 32 provides pin-out information for EP1810 devices in 68-pin PGA
packages.
Pin-Out
Information
Table 32. EP1810 PGA Pin-Outs
Pin
Function
Pin Function Pin Function Pin
Function
A2
A3
A4
A5
A6
A7
A8
A9
I/O
B9
B10
B11
C1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
F10
F11
G1
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
K4 INPUT
I/O
K5 INPUT
K6 VCC
I/O
INPUT
G2
K7 INPUT
K8 INPUT
K9 I/O
CLK4/INPUT C2
CLK3/INPUT C10
G10
G11
H1
INPUT
I/O
C11
D1
K10 I/O
H2
K11 I/O
A10 I/O
D2
H10
H11
J1
L2 I/O
B1
B2
B3
B4
B5
B6
B7
B8
I/O
D10
D11
E1
L3 I/O
I/O
L4 INPUT
L5 CLK1/INPUT
L6 CLK2/INPUT
L7 INPUT
L8 I/O
I/O
J2
INPUT
INPUT
VCC
E2
J10
J11
K1
E10
E11
F1
INPUT
INPUT
K2
L9 I/O
F2
K3
L10 I/O
Altera Corporation
785
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