EPC1064VTI32 [ALTERA]
Configuration Memory, 64KX1, MOS, PQFP32, PLASTIC, TQFP-32;
| 型号： | EPC1064VTI32 |
| 厂家： | 
ALTERA CORPORATION |
| 描述： | Configuration Memory, 64KX1, MOS, PQFP32, PLASTIC, TQFP-32 OTP只读存储器 时钟 内存集成电路 |
| 文件： | 总28页 (文件大小：380K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Configuration Devices for
ACEX, APEX, FLEX & Mercury Devices
®
March 2001, ver. 11
DataSheet
■
■
Serial device family for configuring ACEXTM, APEXTM (including
APEX 20K, APEX 20KC, and APEX 20KE), FLEX® (FLEX 10KE and
FLEX 10KA), and MercuryTM devices
Easy-to-use 4-pin interface to ACEX, APEX, FLEX, and Mercury
devices
Features
■
■
■
Low current during configuration and near-zero standby current
5.0-V and 3.3-V operation
Software design support with the Altera® QuartusTM and
MAX+PLUS® II development systems for Windows-based PCs as
well as Sun SPARCstation, and HP 9000 Series 700/ 800
Programming support with Altera’s Master Programming Unit
(MPU) and programming hardware from Data I/ O,
BP Microsystems, and other manufacturers
■
■
Available in compact plastic packages (see Figures 1 and 2)
–
–
–
8-pin plastic dual in-line package (PDIP)
20-pin plastic J-lead chip carrier (PLCC) package
32-pin plastic thin quad flat pack (TQFP) package
■
EPC2 device has reprogrammable Flash configuration memory
–
5.0-V and 3.3-V in-system programmability (ISP) through the
built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG)
interface
–
–
–
Built-in JTAG boundary-scan test (BST) circuitry compliant with
IEEE Std. 1149.1
ISP circuitry is compatible with IEEE Std. 1532 for EPC2
configuration device
Supports programming through Serial Vector Format Files
(.svf), JamTM Standard Test and Programming Language
(STAPL) Files (.jam), Jam STAPL Byte-Code Files (.jbc), and the
MAX+PLUS II software via the MasterBlasterTM
,
ByteBlasterMVTM, or BitBlasterTM download cable
– nINIT_CONFpin allows a JTAG instruction to initiate APEX,
FLEX, or Mercury device configuration
–
–
Can be programmed with Programmer Object Files (.pof) for
EPC1 and EPC1441 devices
Available in 20-pin PLCC and 32-pin TQFP packages
Altera Corporation
1
A-DS-EPROM-11
Configuration Devices for ACEX, APEX, FLEX & Mercury Devices Data Sheet
Figure 1. EPC1, EPC1441, EPC1213, EPC1064, & EPC1064V Package Pin-Out Diagrams
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
N.C.
VCC
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
DCLK
N.C.
N.C.
N.C.
N.C.
OE
24
23
22
21
20
19
18
3
2
1
20 19
18
DCLK
N.C.
N.C.
N.C.
OE
4
5
6
7
8
VCC
N.C.
N.C.
N.C.
N.C.
17
16
15
14
DATA
DCLK
OE
1
2
3
4
8
7
6
5
VCC
VCC
nCASC (1)
GND
8
17
16
nCS
N.C.
9
10 11 12 13 14 15
9
10 11 12 13
1()
32-Pin TQFP
8-Pin PDIP
20-Pin PLCC
EPC1441
EPC1064
EPC1064V
EPC1
EPC1
EPC1441
EPC1213
EPC1064
EPC1064V
EPC1441
EPC1213
EPC1064
EPC1064V
Note:
(1) The nCASCpin is available on EPC1 and EPC1213 devices. On the EPC1064, EPC1064V, and EPC1441 devices, it is
a reserved pin and should not be connected.
Figure 2. EPC2 Package Pin-Out Diagrams
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
N.C.
DCLK
VCCSEL
N.C.
24
23
22
21
20
19
18
N.C.
VPP
N.C.
N.C.
3
2
1
20 19
18
DCLK
VCCSEL
N.C.
4
5
6
7
8
VPP
N.C.
N.C.
17
16
15
14
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
OE
N.C.
VPPSEL
VPPSEL
8
17
16
N.C.
OE
9
10 11 12 13 14 15
9
10 11 12 13
32-Pin TQFP
20-Pin PLCC
2
Altera Corporation
Configuration Devices for ACEX, APEX, FLEX & Mercury Devices Data Sheet
With SRAM-based devices, configuration data must be reloaded each
time the system initializes, or when new configuration data is needed.
Altera configuration devices store configuration data for SRAM-based
ACEX, APEX, FLEX, and Mercury devices. Table 1 lists Altera
configuration devices.
Functional
Description
Table 1. Configuration Devices
Device
Description
EPC2
1,695,680 × 1-bit device with 5.0-V or 3.3-V operation
1,046,496 × 1-bit device with 5.0-V or 3.3-V operation
440,800 × 1-bit device with 5.0-V or 3.3-V operation
212,942 × 1-bit device with 5.0-V operation
EPC1
EPC1441
EPC1213
EPC1064
EPC1064V
65,536 × 1-bit device with 5.0-V operation
65,536 × 1-bit device with 3.3-V operation
Table 2 lists the configuration device used with each ACEX, APEX, FLEX
and Mercury device.
Table 2. Appropriate Configuration Device for Each ACEX, APEX, FLEX & Mercury Device (Part 1 of 2)
ACEX, APEX, FLEX & Mercury Device
Configuration Device
EP20K30E
EPC2, EPC1, or EPC1441
EPC2 or EPC1
EP20K60E
EP20K100, EP20K100E
EP20K160E
EPC2 or EPC1
EPC2
EP20K200, EP20K200E
EP20K300E
Two EPC2 devices (1)
Two EPC2 devices (1)
Three EPC2 devices (1)
Four EPC2 devices (1)
Six EPC2 devices (1)
Eight EPC2 devices (1)
EPC2, EPC1, or EPC1441
EPC2, EPC1, or EPC1441
EPC2 or EPC1
EP20K400, EP20K400E
EP20K600E
EP20K1000E
EP20K1500E
EP1K10
EP1K30
EP1K50
EP1K100
EPC2 or two EPC1 devices
EPC2, EPC1, or EPC1441
EPC2, EPC1, or EPC1441
EPC2 or EPC1
EPF10K10, EPF10K10A
EPF10K20
EPF10K30E
EPF10K30, EPF10K30A
EPF10K40
EPC2, EPC1, or EPC1441
EPC2 or EPC1
Altera Corporation
3
Configuration Devices for ACEX, APEX, FLEX & Mercury Devices Data Sheet
Table 2. Appropriate Configuration Device for Each ACEX, APEX, FLEX & Mercury Device (Part 2 of 2)
ACEX, APEX, FLEX & Mercury Device
Configuration Device
EPF10K50, EPF10K50V, EPF10K50E
EPF10K70
EPC2 or EPC1
EPC2 or EPC1
EPF10K100, EPF10K100A, EPF10K100B,
EPF10K100E
EPC2 or two EPC1 devices
EPF10K130V
EPF10K130E
EPF10K200E
EPF10K250A
EPF8282A
EPC2 or two EPC1 devices
Two EPC2 or two EPC1 devices
Two EPC2 or three EPC1 devices
Two EPC2 or four EPC1 devices
EPC1, EPC1441, or EPC1064
EPC1, EPC1441, or EPC1064V
EPC1, EPC1441, EPC1064, or EPC1213
EPC1, EPC1441, or EPC1213
EPC1, EPC1441, or EPC1213
EPC1, EPC1441, or EPC1213
EPC1 or EPC1441
EPF8282AV
EPF8452A
EPF8636A
EPF8820A
EPF81188A
EPF81500A
EPF6010A
EPC1 or EPC1441
EPF6016, EPF6016A
EPF6024A
EPC1 or EPC1441
EPC1 or EPC1441
EP1M120
EPC2 or EPC16
EP1M350
EPC16 or three EPC2 devices
Note:
(1) This device can be configured by a smaller number of EPC16 configuration devices. For more information, see the
EPC16 Configuration Device Data Sheet.
Table 3 shows which configuration devices can be used with each device
family.
Table 3. Configuration Device & PLD Compatibility
PLD
Configuration Device
EPC2
EPC1
EPC1441
EPC1213
EPC1064
EPC1064V
ACEX 1K (1)
APEX 20K (1)
FLEX 10K (1)
FLEX 10KE (1)
v
v
v
v
v
v
v
v
v
v
v
4
Altera Corporation
Configuration Devices for ACEX, APEX, FLEX & Mercury Devices Data Sheet
Table 3. Configuration Device & PLD Compatibility
PLD
Configuration Device
EPC2
EPC1
EPC1441
EPC1213
EPC1064
EPC1064V
FLEX 8000
FLEX 6000
Mercury (1)
v
v
v
v
v
v
v
v
Note to Table:
(1) EPC16 configuration devices support this device. For more information, see the
EPC16 Configuration Device Data Sheet.
Figure 3 shows the configuration device block diagram.
Altera Corporation
5
Configuration Devices for ACEX, APEX, FLEX & Mercury Devices Data Sheet
Figure 3. Configuration Device Block Diagram
ACEX 1K, APEX 20K, FLEX 10K, & FLEX 6000 Device Configuration Using an EPC2, EPC1, or EPC1441 Device
DCLK
CLK
ENA
nRESET
Oscillator
Address
Counter
Oscillator
Control
Address
Decode
Logic
nCS
nCASC (1)
Error
Detection
Circuitry
EPROM
Array
OE (2)
DATA
Shift
Register
DATA
FLEX 8000 Device Configuration Using an EPC1, EPC1441, EPC1213, EPC1064, or EPC1064V Device
CLK
ENA
nRESET
DCLK
Address
Counter
Address
Decode
Logic
nCASC (1)
nCS
OE
EPROM
Array
DATA
Shift
Register
DATA
Notes:
(1) The EPC1441, EPC1064, and EPC1064V devices do not support data cascading. The EPC2, EPC1, and EPC1213
devices support data cascading.
(2) The OEpin is a bidirectional open-drain pin.
6
Altera Corporation
Configuration Devices for ACEX, APEX, FLEX & Mercury Devices Data Sheet
The control signals for configuration devices—nCS, OE, and DCLK—
interface directly with ACEX, APEX, FLEX, and Mercury device control
signals. All ACEX, APEX, FLEX, and Mercury devices can be configured
by a configuration device without requiring an external intelligent
controller.
Device
Configuration
The configuration device’s OEand nCSpins control the tri-state buffer on
the DATAoutput pin, and enable the address counter (and the oscillator in
EPC2, EPC1, and EPC1441 devices). When OEis driven low, the
configuration device resets the address counter and tri-states its DATApin.
The nCSpin controls the output of the configuration device. If nCSis held
high after the OEreset pulse, the counter is disabled and the DATAoutput
pin is tri-stated. When nCSis driven low, the counter and DATAoutput pin
are enabled. When OEis driven low again, the address counter is reset and
the DATAoutput pin is tri-stated, regardless of the state of nCS.
1
The EPC2, EPC1, and EPC1441 devices determine the operation
mode and whether the ACEX 1K, APEX 20K, FLEX 10K,
FLEX 8000, FLEX 6000, or Mercury protocols should be used
when OEis driven high.
When the configuration device has driven out all of its data and has
driven nCASClow, the device tri-states the DATApin to avoid contention
with other configuration devices.
The EPC2 device allows the user to initiate configuration of the ACEX,
APEX, FLEX, or Mercury device via an additional pin, nINIT_CONF, that
can be tied to the nCONFIGpin of the ACEX, APEX, FLEX, or Mercury
device(s) to be configured. A JTAG instruction causes the EPC2 device to
drive nINIT_CONFlow, which in turn pulls nCONFIGlow. The EPC2
device then drives nINIT_CONFhigh to start configuration. When the
JTAG state machine exits this state, nINIT_CONFreleases nCONFIGand
configuration is initiated.
1
An EPC2 device can be programmed with a POF generated for
an EPC1 or EPC1441 device, however, an EPC2 device cannot
configure FLEX 6000 or FLEX 8000 devices. An EPC1 device can
be programmed using a POF generated for an EPC1441 device.
Altera Corporation
7
Configuration Devices for ACEX, APEX, FLEX & Mercury Devices Data Sheet
ACEX 1K, APEX 20K, FLEX 10K, FLEX 6000 & Mercury Device
Configuration
ACEX 1K, APEX 20K, FLEX 10K, and Mercury devices can be configured
with EPC2, EPC1, or EPC1441 devices. FLEX 6000 devices can be
configured with EPC1 or EPC1441 devices. The EPC2, EPC1, or EPC1441
device stores configuration data in its EPROM array and serially clocks
data out with an internal oscillator. The OE, nCS, and DCLKpins supply
the control signals for the address counter and the output tri-state buffer.
The configuration device sends a serial bitstream of configuration data to
its DATApin, which is routed to the DATA0or DATAinput pin on the
ACEX 1K, APEX 20K, FLEX 10K, FLEX 6000, or Mercury device. Figure 4
shows an ACEX 1K, APEX 20K, FLEX 10K, FLEX 6000, or Mercury device
configured with a single EPC2, EPC1, or EPC1441 device.
Figure 4. ACEX 1K, APEX 20K, FLEX 10K, FLEX 6000, or Mercury Device
Configured with an EPC2, EPC1, or EPC1441 Configuration Device
VCC
VCC
(1)
(1)
ACEX 1K, APEX 20K, FLEX 10K,
FLEX 6000, or Mercury Device (2)
Configuration
Device
(3)
(3)
DCLK
DATA
DCLK
DATA0
OE
nSTATUS
nCS
nINIT_CONF (4)
CONF_DONE
nCONFIG
MSEL0
nCE
MSEL1
GND
GND
Notes:
(1) The pull-up resistor should be connected to the same supply voltage as the
configuration device.
(2) The diagram shows an ACEX 1K, APEX 20K, FLEX 10K or Mercury device, which
has MSEL0and MSEL1tied to ground. For FLEX 6000 devices, MSELis tied to
ground, and the DATA0pin is named DATA. EPC2 cannot be used with FLEX 6000
devices. All other connections are the same for ACEX 1K, APEX 20K, FLEX 10K,
FLEX 6000 and Mercury devices.
(3) All pull-up resistors are 1 k¾. APEX 20KE pull up resistors are 10 k¾. The OE, nCS,
and nINIT_CONFpins on EPC2 devices have internal, user-configurable 1-k¾
pull-up resistors. If internal pull-up resistors are used, external pull-up resistors
should not be used on these pins.
(4) The nINIT_CONFpin is only available on EPC2 devices and has an internal pull up
of 1 k¾ that is always active. If nINIT_CONFis not available or not used, nCONFIG
must be pulled to V either directly or through a 1-k¾ resistor.
CC
Table 4 describes EPC2, EPC1, and EPC1441 pin functions during
ACEX 1K, APEX 20K, FLEX 10K, FLEX 6000, and Mercury device
configuration.
8
Altera Corporation
Configuration Devices for ACEX, APEX, FLEX & Mercury Devices Data Sheet
Table 4. EPC2, EPC1, & EPC1441 Pin Functions During ACEX 1K, APEX 20K, FLEX 10K, FLEX 6000 &
Mercury Configuration (Part 1 of 2)
Pin Name
Pin Number
Pin
Description
Type
8-Pin
20-Pin 32-Pin
PDIP (1) PLCC TQFP (2)
DATA
1
2
31
Output Serial data output. The DATApin is tri-stated before
configuration when the nCSpin is high, and after the
configuration device finishes sending its configuration
data. This operation is independent of the device’s
position in the cascade chain.
DCLK
2
4
2
I/O
DCLKis a clock output when configuring with a single
configuration device or when the configuration device is
the first device in a configuration device chain. DCLKis
a clock input for subsequent configuration devices in a
configuration device chain. Rising edges on DCLK
increment the internal address counter and present the
next bit of data to the DATApin. The counter is
incremented only if the OEinput is held high, the nCS
input is held low, and all configuration data has not
been transferred to the target device. When configuring
with the first EPC2 or EPC1 device in a configuration
device chain or with a single EPC1441 device, the
DCLKpin drives low after configuration is complete or
when OEis low.
OE(3)
3
4
8
9
7
Open- Output enable (active high) and reset (active low). A
Drain
I/O
low logic level resets the address counter. A high logic
level enables DATAand permits the address counter to
count. If this pin is low (reset) during configuration, the
internal oscillator becomes inactive and DCLKdrives
low. See “Error Detection Circuitry” on page 17.
nCS(3)
10
Input
Chip select input (active low). A low input allows DCLK
to increment the address counter and enables DATAto
drive out. If the EPC1 or EPC2 is reset with nCSlow, the
device initializes as the first device in a configuration
chain. If the EPC1 or EPC2 device is reset with nCS
high, the device initializes as the subsequent device in
the chain.
nCASC(4)
6
12
15
Output Cascade select output (active low). This output goes
low when the address counter has reached its
maximum value. In a chain of EPC1 or EPC2 devices,
the nCASCpin of one device is connected to the nCSpin
of the next device, which permits DCLKto clock data
from the next EPC1 or EPC2 device in the chain.
Altera Corporation
9
Configuration Devices for ACEX, APEX, FLEX & Mercury Devices Data Sheet
Table 4. EPC2, EPC1, & EPC1441 Pin Functions During ACEX 1K, APEX 20K, FLEX 10K, FLEX 6000 &
Mercury Configuration (Part 2 of 2)
Pin Name
Pin Number
Pin
Description
Type
8-Pin
20-Pin 32-Pin
PDIP (1) PLCC TQFP (2)
nINIT_CONF
–
13
16
Open- Allows the INIT_CONF JTAG instruction to initiate
Drain configuration. This pin is connected to the nCONFIGpin
(3), (5)
Output of the ACEX, APEX, FLEX or Mercury device to initiate
configuration from the EPC2 via a JTAG instruction. If
multiple EPC2 devices are used to configure an ACEX,
APEX, FLEX or Mercury device, only the first EPC2 has
its nINIT_CONFpin tied to the device’s nCONFIGpin.
TDI(5)
–
–
–
–
–
11
1
13
28
25
32
3
Input
JTAG data input pin. Connect this pin to V if the
CC
JTAG circuitry is not used.
TDO(5)
Output JTAG data output pin. Do not connect this pin if the
JTAG circuitry is not used.
TMS(5)
19
3
Input
Input
Input
JTAG mode select pin. Connect this pin to V if the
CC
JTAG circuitry is not used.
TCK(5)
JTAG clock pin. Connect this pin to ground if the JTAG
circuitry is not used.
VCCSEL (5)
5
Mode select for V supply. VCCSELmust be
CC
connected to ground if the device uses a 5.0-V power
supply (i.e., V = 5.0 V). VCCSELmust be connected
CC
to V if the device uses a 3.3-V power supply (i.e.,
CC
V
= 3.3 V).
CC
VPPSEL (5)
VPP (5)
–
–
14
18
17
23
Input
Mode select for VPP. VPPSELmust be connected to
ground if VPPuses a 5.0-V power supply
(i.e., VPP= 5.0 V). VPPSELmust be connected to V
if VPPuses a 3.3-V power supply (i.e, VPP= 3.3 V).
CC
Power Programming power pin. For the EPC2 device, this pin
is normally tied to V . If the EPC2 V is 3.3 V, VPP
CC
CC
can be tied to 5.0 V to improve in-system programming
times. For EPC1 and EPC1441 devices, VPPmust be
tied to V
.
CC
VCC
GND
7, 8
5
20
10
27
12
Power Power pin.
Ground Ground pin. A 0.2-µF decoupling capacitor must be
placed between the VCCand GNDpins.
Notes:
(1) This package is available for EPC1 and EPC1441 devices only.
(2) This package is available for EPC2 and EPC1441 devices only.
(3) The OE, nCS, and nINIT_CONFpins on EPC2 devices have internal, user-configurable 1-k¾ pull-up resistors. If
internal pull-up resistors are used, external pull-up resistors should not be used on these pins.
(4) The EPC1441 device does not support data cascading. EPC2 and EPC1 devices support data cascading.
(5) This pin applies to the EPC2 device only.
10
Altera Corporation
Configuration Devices for ACEX, APEX, FLEX & Mercury Devices Data Sheet
ACEX 1K, APEX 20K, FLEX 10K, FLEX 6000 & Mercury Device
Configuration with Multiple EPC2 or EPC1 Configuration Devices
When configuration data for ACEX 1K, APEX 20K, FLEX 10K, FLEX 6000,
or Mercury devices exceeds the capacity of a single EPC2 or EPC1 device,
multiple EPC2 or EPC1 devices can be cascaded together. (The EPC1441
device does not support data cascading.) If multiple EPC2 or EPC1
devices are required, the nCASCand nCSpins provide handshaking
between the devices.
When configuring ACEX 1K, APEX 20K, FLEX 10K, FLEX 6000, or
Mercury devices with cascaded EPC2 or EPC1 devices, the position of the
EPC2 or EPC1 device in the chain determines its operation. When the first
or master device in a configuration device chain is powered-up or reset
and the nCSpin is driven low, the master device controls configuration.
The master device supplies all clock pulses to one or more ACEX, APEX,
FLEX, or Mercury devices and to any subsequent slave devices during
configuration. The master EPC2 or EPC1 device also provides the first
stream of data to the ACEX, APEX, FLEX, or Mercury devices during
multi-device configuration. After the master EPC2 or EPC1 device
finishes sending configuration data, the master EPC2 or EPC1 device
drives its nCASCpin low, which drives the nCSpin of the first slave EPC2
or EPC1 device low. This action causes the slave EPC2 or EPC1 device to
send configuration data to the ACEX, APEX, FLEX, or Mercury devices.
The master EPC2 or EPC1 device clocks all subsequent slave devices until
configuration is complete. Once all configuration data is transferred and
the nCSpin on the master EPC2 or EPC1 device is driven high by the
ACEX, APEX, FLEX, or Mercury device’s CONF_DONEpin, the master
EPC2 or EPC1 device clocks 16 additional cycles to initialize the ACEX,
APEX, FLEX, or Mercury device(s). The master EPC2 or EPC1 device then
goes into zero-power (idle) state. If nCSon the master EPC2 or EPC1
device is driven high before all configuration data is transferred, or if nCS
is not driven high after all configuration data is transferred, the master
EPC2 or EPC1 device drives the ACEX, APEX, FLEX, or Mercury device’s
nSTATUSpin low, indicating a configuration error.
Configuration automatically restarts if the project is compiled with the
Auto-Restart Configuration on Frame Error option turned on in the
MAX+PLUS II software’s Global Project Device Options dialog box
(Assign menu).
Figure 5 shows an ACEX 1K, APEX 20K, FLEX 10K, FLEX 6000, or
Mercury device configured with two EPC2 or EPC1 devices. Additional
EPC2 or EPC1 devices can be added by connecting nCASCto nCSof the
subsequent slave EPC2 or EPC1 device in the chain and connecting DCLK,
DATA, and OEin parallel.
Altera Corporation
11
Configuration Devices for ACEX, APEX, FLEX & Mercury Devices Data Sheet
1
A mixture of ACEX 1K, APEX 20K, APEX 20KE, and Mercury
devices can be configured in the same chain. A mixture of
FLEX 10K, FLEX 10KA, FLEX 10KE, and 5.0-V and 3.3-V
FLEX 6000 devices can be configured in the same chain. See
“Configuration Chain with Multiple Voltage Levels” on page 19.
Figure 5. ACEX 1K, APEX 20K, FLEX 10K, FLEX 6000, or Mercury Device Configured with Two EPC2 or EPC1
Configuration Devices
VCC
(1)
VCC(1)
(3)
(3)
Configuration
Device 2
ACEX 1K, APEX 20K, FLEX 10K,
FLEX 6000, or Mercury Device (2)
Configuration
Device 1
DCLK
DATA0
nSTATUS
DCLK
DATA
OE
nCS
nINIT_CONF (4)
DCLK
DATA
nCS
CONF_DONE
nCONFIG
nCASC
OE
MSEL0
nCE
MSEL1
GND
GND
Notes:
(1) The pull-up resistor should be connected to the same supply voltage as the configuration device.
(2) The diagram shows an ACEX 1K, APEX 20K, FLEX 10K, or Mercury device, which has MSEL0and MSEL1tied to
ground. For FLEX 6000 devices, MSELis tied to ground, and the DATA0pin is named DATA. EPC2 cannot be used
with FLEX 6000 devices. All other connections are the same for ACEX 1K, APEX 20K, FLEX 10K, FLEX 6000, and
Mercury devices.
(3) All pull-up resistors are 1 k¾ (APEX 20KE pull-resistors are 10k¾). The OEand nCSpins on EPC2 devices have
internal, user-configurable 1-k¾ pull-up resistors. If internal pull-up resistors are used, external pull-up resistors
should not be used on these pins.
(4) The nINIT_CONFpin is only available on EPC2 devices and has an internal pull up of 1 k¾ that is always active. If
nINIT_CONFis not available or not used, nCONFIGmust be pulled to V either directly or through a 1-k¾ resistor.
CC
Figure 6 shows two ACEX 1K, APEX 20K, FLEX 10K, FLEX 6000, or
Mercury devices configured with two EPC2 or EPC1 devices.
12
Altera Corporation
Configuration Devices for ACEX, APEX, FLEX & Mercury Devices Data Sheet
Figure 6. Two ACEX 1K, APEX 20K, FLEX 10K, FLEX 6000, or Mercury Devices Configured with Two EPC2 or
EPC1 Configuration Devices
VCC
VCC
(1)
(1)
(2)
(2)
ACEX 1K, APEX 20K
FLEX 10K, FLEX 6000
or Mercury Device (3)
DCLK
ACEX 1K, APEX 20K, FLEX 10K,
FLEX 6000 or Mercury Device (3)
Configuration
Device 1
DCLK
DATA
OE
Configuration
Device 2
DCLK
DATA0
MSEL0
MSEL0
DATA0
DCLK
DATA
nCS
MSEL1
nSTATUS
CONF_DONE
nCONFIG
MSEL1
nSTATUS
CONF_DONE
nCONFIG
nCS
nCASC
nINIT_CONF (4)
OE
GND
GND
nCE
nCEO
nCE
GND
Notes:
(1) The pull-up resistor should be connected to the same supply voltage as the configuration device.
(2) The diagram shows an ACEX 1K, APEX 20K, FLEX 10K, or Mercury device, which has MSEL0and MSEL1tied to
ground. For FLEX 6000 devices, MSELis tied to ground, and the DATA0pin is named DATA. EPC2 cannot be used
with FLEX 6000 devices. All other connections are the same for ACEX 1K, APEX 20K, FLEX 10K, FLEX 6000, and
Mercury devices.
(3) All pull-up resistors are 1 k¾ (APEX 20KE pull-resistors are 10k¾). The OEand nCSpins on EPC2 devices have
internal, user-configurable 1-k¾ pull-up resistors. If internal pull-up resistors are used, external pull-up resistors
should not be used on these pins.
(4) The nINIT_CONFpin is only available on EPC2 devices and has an internal pull up of 1 k¾ that is always active. If
nINIT_CONFis not available or not used, nCONFIGmust be pulled to V either directly or through a 1-k¾ resistor.
CC
For more information on ACEX 1K, APEX 20K, FLEX 10K, or FLEX 6000
device configuration, see Application Note 116 (Configuring ACEX 1K,
APEX 20K, FLEX 10K & FLEX 6000 Devices).
f
FLEX 8000 Device Configuration
FLEX 8000 devices differ from ACEX 1K, APEX 20K, FLEX 10K, and
FLEX 6000 devices in that they have internal oscillators that can provide a
DCLKsignal to the configuration device. The configuration device sends
configuration data out as a serial bitstream on the DATAoutput pin. This
data is routed into the FLEX 8000 device via the DATA0input pin. The
EPC1, EPC1441, EPC1213, EPC1064, and EPC1064V configuration devices
support this type of configuration.
Altera Corporation
13
Configuration Devices for ACEX, APEX, FLEX & Mercury Devices Data Sheet
EPC1 and EPC1441 devices can replace the EPC1213, EPC1064, and
EPC1064V configuration devices. The EPC1 or EPC1441 device
automatically emulates the EPC1213, EPC1064, or EPC1064V when it is
programmed with the appropriate POF. When the EPC1 or EPC1441
device is programmed with an EPC1213, EPC1064, or EPC1064V POF, the
FLEX 8000 device drives the EPC1 or EPC1441 device’s OEpin high and
clocks the EPC1 or EPC1441 device. One EPC1 device can store more
configuration data than the EPC1064, EPC1064V, EPC1213, or EPC1441
device. Therefore, designers can use one type of configuration device for
all FLEX devices. In addition, a single EPC1 or EPC1441 device can
configure any FLEX 8000 device.
For multi-device configuration of FLEX 8000 devices, the nCASCand nCS
pins provide handshaking between multiple configuration devices,
allowing several cascaded EPC1 or EPC1213 devices to serially configure
multiple FLEX 8000 devices. The EPC1441, EPC1064, and EPC1064V do
not support data cascading. Figure 7 shows a FLEX 8000 device
configured with a single EPC1, EPC1441, EPC1213, EPC1064, or
EPC1064V configuration device.
Figure 7. FLEX 8000 Device Configured with an EPC1, EPC1441, EPC1213,
EPC1064, or EPC1064V Configuration Device
VCC(1)
VCC(1)
VCC (1)
(2)
(2)
Configuration
Device
FLEX 8000 Device
nS/P
MSEL1
MSEL0
CONF_DONE
nSTATUS
DCLK
nCS
OE
DCLK
"0"
"0"
"0"
DATA
DATA0
nCONFIG
Notes:
(1) The pull-up resistor should be connected to the same supply voltage as the
configuration device.
(2) All pull-up resistors are 1 k¾.
14
Altera Corporation
Configuration Devices for ACEX, APEX, FLEX & Mercury Devices Data Sheet
Figure 8 shows three FLEX 8000 devices configured with two EPC1 or
EPC1213 configuration devices.
Figure 8. FLEX 8000 Multi-Device Configuration with Two EPC1 or EPC1213 Configuration Devices
VCC
VCC
VCC (1)
(1)
(1)
(2)
(2)
VCC
VCC
(1)
(1)
Configuration
Device 2
Configuration
Device 1
(2)
(2)
FLEX 8000 Device 1
nS/P
MSEL1
MSEL0
CONF_DONE
nSTATUS
DCLK
nCASC
DATA
"0"
"0"
"0"
DATA
nCS
OE
nCS
OE
DCLK
DCLK
DATA0
nCONFIG
VCC (1)
(2)
FLEX 8000 Device 2
nS/P
MSEL1
MSEL0
CONF_DONE
nSTATUS
"0"
"1"
"0"
DCLK
DATA0
nCONFIG
VCC (1)
(2)
FLEX 8000 Device 3
nS/P
MSEL1
MSEL0
CONF_DONE
nSTATUS
"0"
"1"
"0"
DCLK
DATA0
nCONFIG
Notes:
(1) The pull-resistor should be connected to the same supply voltage as the confiuration device.
(2) All pull-up resistors are 1 k¾.
Altera Corporation
15
Configuration Devices for ACEX, APEX, FLEX & Mercury Devices Data Sheet
Table 5 describes the pin functions of all configuration devices during
FLEX 8000 device configuration.
Table 5. Configuration Device Pin Functions During FLEX 8000 Device Configuration
Pin Name
Pin Number
Pin
Description
Type
8-Pin
20-Pin 32-Pin
PDIP (1) PLCC TQFP (2)
DATA
1
2
Output
Input
31
Serial data output. The DATApin is tri-stated before
configuration when the nCSpin is high and after the
configuration device finishes sending its configuration
data. This operation is independent of the device’s
position in the cascade chain.
DCLK
2
4
DCLKis a clock input when using EPC1, EPC1213,
EPC1064, and EPC1064V configuration devices. Rising
edges on DCLKincrement the internal address counter
and present the next bit of data to the DATApin. The
counter is incremented only if the OEinput is held high,
the nCSinput is held low, and all configuration data has
not been transferred to the target device.
2
OE
3
8
Open-
Drain
I/O
7
Output enable (active high) and reset (active low). A low
logic level resets the address counter. A high logic level
enables DATAand permits the address counter to count.
nCS(3)
4
6
9
10
Input
Chip-select input (active low). A low input allows DCLKto
increment the address counter and enables DATA.
nCASC
12
15
Output Cascade-select output (active low). This output goes low
when the address counter has reached its maximum
value. The nCASCoutput is usually connected to the nCS
input of the next device in a configuration chain, so the
next DCLKclocks data out of the next device.
VCC
GND
7, 8
5
20
10
27
12
Power Power pin.
Ground Ground pin. A 0.2-µF decoupling capacitor must be
placed between the VCCand GNDpins.
Notes:
(1) This package is available for EPC1, EPC1441, EPC1213, EPC1064, and EPC1064V devices only.
(2) This package is available for EPC1441, EPC1064, and EPC1064V devices only.
(3) The EPC1441, EPC1064, and EPC1064V devices do not support data cascading. The EPC1 and EPC1213 devices
support data cascading for FLEX 8000 devices.
For more information on FLEX 8000 device configuration, see the
following documents:
f
■
■
Application Note 33 (Configuring FLEX 8000 Devices)
Application Note 38 (Configuring Multiple FLEX 8000 Devices)
16
Altera Corporation
Configuration Devices for ACEX, APEX, FLEX & Mercury Devices Data Sheet
This section describes Power-On Reset (POR) delay, error detection, and
3.3-V and 5.0-V operation of Altera configuration devices.
Power &
Operation
Power-On Reset
During initial power-up, a POR delay occurs to permit voltage levels to
stabilize. When configuring an ACEX 1K, APEX 20K, FLEX 10K,
FLEX 6000, or Mercury device with an EPC2, EPC1, or EPC1441 device,
the POR delay occurs inside the configuration device, and the POR delay
is a maximum of 100 ms. When configuring a FLEX 8000 device with an
EPC1213, EPC1064, or EPC1064V device, the POR delay occurs inside the
FLEX 8000 device, and the POR delay is typically 100 ms, with a
maximum of 200 ms.
Error Detection Circuitry
The EPC2, EPC1, and EPC1441 configuration devices have built-in error
detection circuitry for configuring ACEX 1K, APEX 20K, FLEX 10K,
FLEX 6000, and Mercury devices only.
Built-in error-detection circuitry uses the nCSpin of the configuration
device, which monitors the CONF_DONEpin on the ACEX 1K, APEX 20K,
FLEX 10K, FLEX 6000, or Mercury device. An error condition occurs if the
CONF_DONEpin does not go high after all the configuration data has been
sent, or if the CONF_DONEpin goes high before the configuration device
has completed sending configuration data. When an error condition
occurs, the configuration device drives its OEpin low, which drives the
ACEX 1K, APEX 20K, FLEX 10K, FLEX 6000, or Mercury device’s
nSTATUSpin low, indicating an error. After an error, configuration
automatically restarts if the Auto-Restart Configuration on Frame Error
option is turned on in the Global Project Device Options dialog box
(Assign menu) in the MAX+PLUS II software. For APEX 20K and
Mercury devices, the Quartus software provides a similar option.
In addition, if the ACEX 1K, APEX 20K, FLEX 10K, FLEX 6000, or
Mercury device detects a cyclic redundancy code (CRC) error in the
received data, it may also flag the error by driving nSTATUSlow. This low
signal on nSTATUSresets the configuration device, allowing
reconfiguration. CRC checking is performed when configuring all
ACEX 1K, APEX 20K, FLEX 10K, FLEX 6000, and Mercury devices.
Altera Corporation
17
Configuration Devices for ACEX, APEX, FLEX & Mercury Devices Data Sheet
3.3-V or 5.0-V Operation
EPC2, EPC1, and EPC1441 devices can configure 5.0-V, 3.3-V, or 2.5-V
devices. For each configuration device, an option must be set for 5.0-V or
3.3-V operation. For EPC1 and EPC1441 configuration devices, the Use
Low-Voltage Configuration EPROM option in the Global Project Device
Options dialog box (Assign menu) in the MAX+PLUS II software sets this
parameter. (For APEX 20K and Mercury devices, the Quartus software
provides a similar option.) For EPC2 devices, this option is set externally
by the VCCSELpin. In addition, the EPC2 device has an externally
controlled option, set by the VPPSELpin, to adjust the programming
voltage to 5.0 V or 3.3 V.
The functions of the VCCSELand VPPSELpins are described below.
■ VCCSELpin—For EPC2 configuration devices, 5.0-V or 3.3-V
operation is controlled by the VCCSELoption pin. The device
functions in 5.0-V mode when VCCSELis connected to GND; the
device functions in 3.3-V mode when VCCSELis connected to VCC
.
■ VPPSELpin—The EPC2 VPPprogramming power pin is normally
tied to VCC. For EPC2 devices operating with a 3.3-V supply, it is
possible to improve EPC2 in-system programming times by
providing VPPwith a 5.0-V supply. For all other devices, VPPmust be
tied to VCC. The EPC2 device’s VPPSELpin must be set in accordance
with the EPC2 VPPpin. If the VPPpin is supplied by a 5.0-V supply,
VPPSELmust be connected to GND; if the VPPpin is supplied by a
3.3-V power supply, VPPSELmust be connected to VCC
.
Table 6 describes the relationship between the VCC and VPP voltage levels
and the required logic level for VCCSELand VPPSEL(i.e., high or low
logic level).
Table 6. VCCSEL & VPPSEL Pin Functions on the EPC2
VCC Voltage Level VPP Voltage Level VCCSEL Pin Logic VPPSEL Pin Logic
(V)
(V)
Level
Level
3.3
3.3
5.0
3.3
5.0
5.0
High
High
Low
High
Low
Low
18
Altera Corporation
Configuration Devices for ACEX, APEX, FLEX & Mercury Devices Data Sheet
For EPC1 and EPC1441 configuration devices, 3.3-V or 5.0-V operation is
controlled by a programming bit in the POF. The programming bit value
is determined by the core supply voltage of the targeted device during
design compilation with the MAX+PLUS II software. For example, EPC1
devices are programmed automatically to operate in 3.3-V mode when
configuring FLEX 10KA devices, which have a VCC voltage of 3.3 V. In this
example, the EPC1 device’s VCCpin is connected to a 3.3-V power supply.
Designers may choose to set the configuration device for low voltage
when using the MultiVoltTM feature, which allows an ACEX, APEX, FLEX,
or Mercury device to bridge between systems operating with different
voltages. When compiling for 3.3-V FLEX 6000 devices, set the
configuration device for low-voltage operation. To set the EPC1 and
EPC1441 configuration devices for low-voltage operation, turn on the
Low-Voltage I/O option in the Global Project Device Options dialog box
(Assign menu) in the MAX+PLUS II software.
Configuration Chain with Multiple Voltage Levels
An EPC2 or EPC1 device can configure a device chain with multiple
voltage levels. All 3.3-V and 2.5-V ACEX, APEX, FLEX, and Mercury
devices can be driven by higher-voltage signals.
When configuring a mixed-voltage device chain, the ACEX, APEX, FLEX
and Mercury devices’ VCCINTand VCCIOpins may be connected to 2.5 V,
3.3 V, or 5.0 V, depending upon the device. The configuration device may
be powered at 3.3 V or 5.0 V. If an EPC1, EPC1441, EPC1213, EPC1064, or
EPC1064V configuration device is powered at 3.3 V, the nSTATUSand
CONF_DONEpull-up resistors must be connected to 3.3 V. If these
configuration devices are powered at 5.0 V, the nSTATUSand CONF_DONE
pull-up resistors must be connected to 3.3 V or 5.0 V.
At 3.3-V operation, all EPC2 inputs are 5.0-V tolerant, except DATA, DCLK,
and nCASC. The DATA, DCLK, and nCEOpins are used only to interface
between the EPC2 and the ACEX 1K, APEX 20K, FLEX 10K, FLEX 6000, or
Mercury device it is configuring. The voltage tolerances of all EPC2 pins
at 5.0 V and 3.3 V are listed in Table 7.
Table 7. EPC2 Input & Bidirectional Pin Voltage Tolerance
Pin
5.0-V Operation
3.3-V Operation
5.0-V
Tolerant
3.3-V
Tolerant
5.0-V
Tolerant
3.3-V
Tolerant
DATA
DCLK
v
v
v
v
v
v
Altera Corporation
19
Configuration Devices for ACEX, APEX, FLEX & Mercury Devices Data Sheet
Table 7. EPC2 Input & Bidirectional Pin Voltage Tolerance
Pin
5.0-V Operation
3.3-V Operation
5.0-V
3.3-V
5.0-V
3.3-V
Tolerant
Tolerant
Tolerant
Tolerant
nCASC
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
OE
v
v
v
v
v
v
v
v
nCS
VCCSEL
VPPSEL
nINIT_CONF
TDI
TMS
TCK
For more information on ACEX 1K, APEX 20K, FLEX 10K, FLEX 8000,
FLEX 6000, and Mercury devices, see the following documents:
f
■
■
■
■
■
■
■
ACEX 1K Programmable Logic Device Family Data Sheet
APEX 20K Programmable Logic Device Family Data Sheet
FLEX 10K Embedded Programmable Logic Family Data Sheet
FLEX 10KE Embedded Programmable Logic Family Data Sheet
FLEX 8000 Programmable Logic Device Family Data Sheet
FLEX 6000 Programmable Logic Device Family Data Sheet
Mercury Programmable Logic Device Family Data Sheet
The Quartus and MAX+PLUS II development systems provide
programming support for Altera configuration devices. The Quartus and
MAX+PLUS II software automatically generates a POF to program each
configuration device in a project. In a multi-device project, the software
can combine the programming files for multiple ACEX, APEX, FLEX, or
Mercury devices into one or more configuration devices. The software
allows you to select the appropriate configuration device to most
efficiently store the data for each ACEX, APEX, FLEX, and Mercury
device. Moreover, when compiling for ACEX 1K, FLEX 10KA,
FLEX 10KE, or Mercury devices, the MAX+PLUS II software
automatically defaults to generate the EPC1 or EPC1441 POF with the
programming bit set for 3.3-V operation.
Programming
&Configuration
File Support
All Altera configuration devices are programmable using Altera
programming hardware in conjunction with the Quartus or
MAX+PLUS II software. In addition, many manufacturers offer
programming hardware that supports other Altera configuration devices.
20
Altera Corporation
Configuration Devices for ACEX, APEX, FLEX & Mercury Devices Data Sheet
The EPC2 configuration device can be programmed in-system through its
industry-standard 4-pin JTAG interface. ISP capability in the EPC2
provides ease in prototyping and updating ACEX, APEX, FLEX, and
Mercury device functionality. The EPC2 configuration device can be
programmed in-system via test equipment using SVF Files, Jam STAPL
Files (.jam), or Jam STAPL Byte-Code Files (.jbc), embedded processors
using the Jam programming and test language, and the MAX+PLUS II
software via the MasterBlaster, ByteBlasterMV, or BitBlaster download
cables. When programming multiple EPC2 devices in a JTAG chain, the
Quartus and MAX+PLUS II software and other programming methods
employ concurrent programming to simultaneously program multiple
devices and reduce programming time. EPC2 devices can be programmed
and erased up to 100 times.
After programming an EPC2 device in-system, ACEX, APEX, FLEX, or
Mercury device configuration can be initiated by including the EPC2
JTAG configuration instruction. See Table 8 on page 21.
For more information on programming and configuration support, see the
following documents:
f
■
■
■
■
■
■
Altera Programming Hardware Data Sheet
Programming Hardware Manufacturers
MasterBlaster Serial/USB Communications Cable Data Sheet
ByteBlasterMV Parallel Port Download Cable Data Sheet
ByteBlaster Parallel Port Download Cable Data Sheet
BitBlaster Serial Download Cable Data Sheet
The EPC2 provides JTAG BST circuitry that complies with the IEEE Std.
1149.1-1990 specification. JTAG boundary-scan testing can be performed
before or after configuration, but not during configuration. The EPC2
device supports the JTAG instructions shown in Table 8.
IEEE Std.
1149.1 (JTAG)
Boundary-Scan
Testing
The ISP circuitry in EPC2 devices is compatible with tools that support the
IEEE Std. 1532. The IEEE Std. 1532 is a standard developed to allow
concurrent ISP between multiple PLD vendors.
Table 8. EPC2 JTAG Instructions
JTAG Instruction
Description
SAMPLE/PRELOAD
Allows a snapshot of a signal at the device pins to be captured and examined during
normal device operation, and permits an initial data pattern output at the device pins.
EXTEST
Allows the external circuitry and board-level interconnections to be tested by forcing a
test pattern at the output pins and capturing results at the input pins.
Altera Corporation
21
Configuration Devices for ACEX, APEX, FLEX & Mercury Devices Data Sheet
Table 8. EPC2 JTAG Instructions
JTAG Instruction
Description
BYPASS
Places the 1-bit bypass register between the TDIand TDOpins, which allows the BST
data to pass synchronously through a selected device to adjacent devices during
normal device operation.
IDCODE
Selects the device IDCODE register and places it between TDIand TDO, allowing the
device IDCODE to be serially shifted out of TDO. The device IDCODE for the EPC2 is
shown below:
0000 0001000000000010 00001101110 1
USERCODE
Selects the USERCODE register and places it between TDIand TDO, allowing the
USERCODE to be serially shifted out of TDO. The 32-bit USERCODE is a
programmable user-defined pattern.
ISP Instructions
These instructions are used when programming an EPC2 device via JTAG ports with
a MasterBlaster, ByteBlaster MV, ByteBlaster, or BitBlaster download cable, or using
a Jam STAPL File (.jam), Jam STAPL Byte-Code File (.jbc), or SVF File via an
embedded processor.
INIT_CONF
This function allows the user to initiate the APEX or FLEX configuration process by
tying nINIT_CONFto the APEX or FLEX device(s) nCONFIGpin(s). After this
instruction is updated, the nINIT_CONFpin is driven low. When the Initiate
Configuration instruction is cleared, nINIT_CONFis released, which starts the APEX
or FLEX device configuration. This instruction is used by the MAX+PLUS II software,
Jam STAPL Files, and JBC Files.
For more information, see Application Note 39 (IEEE 1149.1 (JTAG)
Boundary-Scan Testing in Altera Devices).
f
Figure 9 shows the timing requirements for the JTAG signals.
22
Altera Corporation
Configuration Devices for ACEX, APEX, FLEX & Mercury Devices Data Sheet
Figure 9. EPC2 JTAG Waveforms
TMS
TDI
tJCP
tJCH
tJCL
tJPH
tJPSU
TCK
TDO
tJPZX
tJPXZ
tJPCO
tJSSU
tJSH
Signal
to Be
Captured
tJSZX
tJSCO
tJSXZ
Signal
to Be
Driven
Table 9 shows the timing parameters and values for configuration
devices.
Table 9. JTAG Timing Parameters & Values
Symbol
Parameter
Min Max Unit
tJCP
TCKclock period
100
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tJCH
TCKclock high time
TCKclock low time
JTAG port setup time
JTAG port hold time
tJCL
50
tJPSU
tJPH
20
45
tJPCO
tJPZX
tJPXZ
tJSSU
tJSH
JTAG port clock to output
25
25
25
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Capture register setup time
20
45
Capture register hold time
tJSCO
tJSZX
tJSXZ
Update register clock to output
25
25
25
Update register high-impedance to valid output
Update register valid output to high impedance
Altera Corporation
23
Configuration Devices for ACEX, APEX, FLEX & Mercury Devices Data Sheet
Tables 10 through 17 provide information on absolute maximum ratings,
recommended operating conditions, DC operating conditions, and
capacitance for configuration devices.
Operating
Conditions
Table 10. Absolute Maximum Ratings
Note (1)
Symbol
Parameter
Conditions
Min
Max
Unit
VCC
VI
Supply voltage
With respect to ground (2)
With respect to ground (2)
–2.0
–2.0
7.0
7.0
50
V
DC input voltage
V
IMAX
IOUT
PD
DC VCC or ground current
DC output current, per pin
Power dissipation
mA
mA
mW
° C
° C
° C
–25
25
250
150
135
135
TSTG
TAMB
TJ
Storage temperature
Ambient temperature
Junction temperature
No bias
–65
–65
Under bias
Under bias
Table 11. Recommended Operating Conditions
Symbol
Parameter
Conditions
Min
Max
Unit
VCC
Supply voltage for 5.0-V operation
Supply voltage for 3.3-V operation
Input voltage
(3), (4)
(3), (4)
4.75 (4.50) 5.25 (5.50)
V
V
V
3.0 (3.0)
3.6 (3.6)
VI
With respect to ground
–0.3
VCC + 0.3
(5)
VO
TA
Output voltage
0
0
VCC
70
V
Operating temperature
For commercial use
For industrial use
° C
° C
ns
–40
85
tR
tF
Input rise time
Input fall time
20
20
ns
Table 12. DC Operating Conditions
Symbol
Parameter
Conditions
Min
Max
Unit
VIH
High-level input voltage
2.0
VCC + 0.3
V
(5)
VIL
Low-level input voltage
5.0-V mode high-level TTL output voltage IOH = –4 mA DC (6)
–0.3
2.4
0.8
V
V
V
VOH
3.3-V mode high-level CMOS output
voltage
IOH = –0.1 mA DC (6)
VCC – 0.2
VOL
II
Low-level output voltage
Input leakage current
IOL = 4 mA DC (6)
VI = VCC or ground
VO = VCC or ground
0.4
10
10
V
–10
–10
µA
µA
IOZ
Tri-state output off-state current
24
Altera Corporation
Configuration Devices for ACEX, APEX, FLEX & Mercury Devices Data Sheet
Table 13. EPC1213, EPC1064 & EPC1064V Device ICC Supply Current Values
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
ICC0
ICC1
VCC supply current (standby)
100
10
200
50
µA
VCC supply current
mA
(during configuration)
Table 14. EPC2 Device ICC Supply Current Values
Symbol
Parameter
Conditions
Min
Min
Typ
Max
Unit
ICC0
ICC1
VCC supply current (standby)
VCC = 5.0 V or 3.3 V
50
18
100
50
µA
VCC supply current (during configuration) VCC = 5.0 V or 3.3 V
mA
Table 15. EPC1 Device ICC Supply Current Values
Symbol
Parameter
Conditions
Typ
Max
Unit
ICC0
ICC1
VCC supply current (standby)
50
30
10
100
50
µA
mA
mA
VCC supply current (during configuration) VCC = 5.0 V
CC = 3.3 V
V
16.5
Table 16. EPC1441 Device ICC Supply Current Values
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
ICC0
ICC1
ICC1
VCC supply current (standby)
30
15
5
60
30
10
µA
mA
mA
VCC supply current (during configuration) VCC = 5.0 V
VCC supply current (during configuration) VCC = 3.3 V
Table 17. Capacitance
Note (7)
Symbol
Parameter
Conditions
Min
Max
Unit
CIN
Input pin capacitance
Output pin capacitance
VIN = 0 V, f = 1.0 MHz
VOUT = 0 V, f = 1.0 MHz
10
10
pF
pF
COUT
Notes to tables:
(1) See the Operating Requirements for Altera Devices Data Sheet in this data book.
(2) The minimum DC input is –0.3 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to 7.0 V for
input currents less than 100 mA and periods shorter than 20 ns under no-load conditions.
(3) Numbers in parentheses are for industrial-temperature-range devices.
(4) Maximum V rise time is 100 ms.
CC
(5) Certain EPC2 pins may be driven to 5.75 V when operated with a 3.3-V V . See Table 7 on page 19.
CC
(6) The I
parameter refers to high-level TTL or CMOS output current; the I parameter refers to low-level TTL or
OH
OL
CMOS output current.
(7) Capacitance is sample-tested only.
Altera Corporation
25
Configuration Devices for ACEX, APEX, FLEX & Mercury Devices Data Sheet
Tables 18 through 22 show the device configuration parameters for
FLEX 10K, FLEX 8000, and FLEX 6000 devices.
Table 18. ACEX 1K, FLEX 10K & FLEX 6000 Device Configuration Parameters Using EPC2 Devices at 5.0-V
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tCE
OEhigh to first clock delay
OEhigh to data output enabled
DCLKto data out delay
200
50
ns
ns
ns
ns
tOEZX
tCO
20
tMCH
DCLKhigh time for the first device in the
configuration chain
30
30
50
50
10
75
tMCL
DCLKlow time for the first device in the
configuration chain
75
ns
fCK
Clock frequency
6.7
30
30
16.7
MHz
ns
tSCH
DCLKhigh time for subsequent devices
DCLKlow time for subsequent devices
CLKrising edge to nCASC
tSCL
ns
tCASC
tCCA
fCDOE
tOEC
tNRCAS
tNRR
20
10
20
20
25
ns
nCSto nCASCcascade delay
CLKto data enable/disable
OElow to CLKdisable delay
OElow (reset) to nCASCdelay
OElow time (reset) minimum
ns
ns
ns
ns
100
ns
Table 19. ACEX 1K, APEX 20K, FLEX 10K & Mercury Device Configuration Parameters Using EPC2 Devices
at 3.3-V
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tCE
OEhigh to first clock delay
OEhigh to data output enabled
DCLKto data out delay
300
80
ns
ns
ns
ns
tOEZX
tCO
30
tMCH
DCLKhigh time for the first device in the
configuration chain
40
40
65
65
100
tMCL
DCLKlow time for the first device in the
100
ns
configuration chain
fCK
Clock frequency
5
7.7
12.5
MHz
ns
tSCH
DCLKhigh time for subsequent devices
DCLKlow time for subsequent devices
CLKrising edge to nCASC
40
40
tSCL
ns
tCASC
tCCA
fCDOE
tOEC
tNRCAS
tNRR
25
15
30
30
30
ns
nCSto nCASCcascade delay
CLKto data enable/disable
OElow to CLKdisable delay
OElow (reset) to nCASCdelay
OElow time (reset) minimum
ns
ns
ns
ns
100
ns
26
Altera Corporation
Configuration Devices for ACEX, APEX, FLEX & Mercury Devices Data Sheet
Table 20. ACEX 1K, FLEX 10K & FLEX 6000 Device Configuration Parameters Using EPC1 &
EPC1441 Devices at 5.0-V
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tCE
OEhigh to first clock delay
OEhigh to data output enabled
DCLKto data out delay
200
50
ns
ns
ns
ns
tOEZX
tCO
20
tMCH
DCLKhigh time for the first device in the
configuration chain
30
30
50
50
10
75
tMCL
DCLKlow time for the first device in the
configuration chain
75
ns
fCK
Clock frequency
6.7
30
30
16.7
MHz
ns
tSCH
DCLKhigh time for subsequent devices
DCLKlow time for subsequent devices
CLKrising edge to nCASC
tSCL
ns
tCASC
tCCA
fCDOE
tOEC
tNRCAS
tNRR
20
10
20
20
25
ns
nCSto nCASCcascade delay
CLKto data enable/disable
OElow to CLKdisable delay
OElow (reset) to nCASCdelay
OElow time (reset) minimum
ns
ns
ns
ns
100
ns
Table 21. ACEX 1K, FLEX 10K & FLEX 6000 Device Configuration Parameters Using EPC1 &
EPC1441 Devices at 3.3-V
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tCE
OEhigh to first clock delay
OEhigh to data output enabled
DCLKto data out delay
300
80
ns
ns
ns
ns
tOEZX
tCO
30
tMCH
DCLKhigh time for the first device in the
configuration chain
50
50
125
125
4
250
tMCL
DCLKlow time for the first device in the
configuration chain
250
10
ns
fCK
Clock frequency
2
MHz
ns
tSCH
DCLKhigh time for subsequent devices
DCLKlow time for subsequent devices
CLKrising edge to nCASC
50
50
tSCL
ns
tCASC
tCCA
fCDOE
tOEC
tNRCAS
tNRR
25
15
30
30
30
ns
nCSto nCASCcascade delay
CLKto data enable/disable
OElow to CLKdisable delay
OElow (reset) to nCASCdelay
OElow time (reset) minimum
ns
ns
ns
ns
100
ns
Altera Corporation
27
Configuration Devices for APEX, ACEX, FLEX & Mercury Devices Data Sheet
Table 22. FLEX 8000 Device Configuration Parameters Using EPC1, EPC1441, EPC1213, EPC1064 &
EPC1064V Devices
Symbol
Parameter
Conditions
EPC1064V EPC1064 EPC1
EPC1213 EPC1441
Unit
Min Max Min Max Min Max
tOEZX
tCSZX
tCSXZ
tCSS
tCSH
tDSU
tDH
OEhigh to DATAoutput enabled
nCSlow to DATAoutput enabled
nCShigh to DATAoutput disabled
nCSlow setup time to first DCLKrising edge
nCSlow hold time after DCLKrising edge
Data setup time before rising edge on DCLK
Data hold time after rising edge on DCLK
DCLKto DATAout delay
75
75
75
50
50
50
50
50
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
150
0
100
0
50
0
75
0
50
0
50
0
tCO
100
4
75
6
75
8
tCK
Clock period
240
160
100
fCK
Clock frequency
tCL
DCLKlow time
120
120
80
80
50
50
tCH
DCLKhigh time
tXZ
OElow or nCShigh to DATAoutput disabled
OEpulse width to guarantee counter reset
Last DCLK+ 1 to nCASClow delay
Last DCLK+ 1 to DATAtri-state delay
nCShigh to nCASChigh delay
75
50
50
tOEW
tCASC
tCKXZ
tCEOUT
150
100
100
90
75
60
50
50
50
150
100
100
®
101 Innovation Drive
San Jose, CA 95134
(408) 544-7000
http://www.altera.com
Applications Hotline:
(800) 800-EPLD
Customer Marketing:
(408) 544-7104
Literature Services:
lit_req@altera.com
Altera, ACEX, APEX, BitBlaster, ByteBlaster, FLEX, Jam, Master Blaster, MAX+PLUS II, Mercury, Quartus,
and specific device designations, are trademarks and/ or service marks of Altera Corporation in the United
States and other countries. Altera acknowledges the trademarks of other organizations for their respective
products or services mentioned in this document. Altera products are protected under numerous U.S. and
foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of
its semiconductor products to current specifications in accordance with Altera’s standard warranty, but
reserves the right to make changes to any products and services at any time without notice.
Altera assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by
Altera Corporation. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for
products or services.
28
Altera Corporation
Printed on Recycled Paper.
相关型号：
EPC1065HE1-G
DC-DC Unregulated Power Supply Module, 1 Output, Hybrid, 1.300 X 0.585 INCH, 0.375 INCH HEIGHT, PACKAGE-12
PCA
EPC1065P
DC-DC Unregulated Power Supply Module, 1 Output, Hybrid, 1.300 X 0.585 INCH, 0.375 INCH HEIGHT, PACKAGE
PCA
EPC1065PE1-G
DC-DC Unregulated Power Supply Module, 1 Output, Hybrid, 1.300 X 0.585 INCH, 0.375 INCH HEIGHT, PACKAGE-12
PCA
EPC1066H
DC-DC Regulated Power Supply Module, 1 Output, Hybrid, 1.300 X 0.585 INCH, 0.375 INCH HEIGHT, PACKAGE
PCA
EPC1066HE1-G
DC-DC Regulated Power Supply Module, 1 Output, Hybrid, 1.300 X 0.585 INCH, 0.375 INCH HEIGHT, PACKAGE-12
PCA
EPC1066PE1-G
DC-DC Regulated Power Supply Module, 1 Output, Hybrid, 1.300 X 0.585 INCH, 0.375 INCH HEIGHT, PACKAGE-12
PCA
EPC1067H
DC-DC Regulated Power Supply Module, 2 Output, Hybrid, 1.300 X 0.800 INCH, 0.530 INCH HEIGHT, PACKAGE
PCA
©2020 ICPDF网 联系我们和版权申明