EPM5128LI [ALTERA]
OT PLD, 55ns, 128-Cell, CMOS, PQCC68, PLASTIC, LCC-68;
| 型号： | EPM5128LI |
| 厂家： | 
ALTERA CORPORATION |
| 描述： | OT PLD, 55ns, 128-Cell, CMOS, PQCC68, PLASTIC, LCC-68 |
| 文件： | 总41页 (文件大小：837K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MAX 5000
Programmable Logic
Device Family
®
May 1999, ver. 5
Data Sheet
■
■
Advanced Multiple Array MatriX (MAX®) 5000 architecture
combining speed and ease-of-use of PAL devices with the density of
programmable gate arrays
Complete family of high-performance, erasable CMOS EPROM
erasable programmable logic devices (EPLDs) for designs ranging
from fast 28-pin address decoders to 100-pin LSI custom peripherals
600 to 3,750 usable gates (see Table 1)
Fast, 15-ns combinatorial delays and 76.9-MHz counter frequencies
Configurable expander product-term distribution allowing more
than 32 product terms in a single macrocell
Features...
■
■
■
■
■
28 to 100 pins available in dual in-line package (DIP), J-lead chip
carrier, pin-grid array (PGA), and quad flat pack (QFP) packages
Programmable registers providing D, T, JK, and SR flipflop
functionality with individual clear, preset, and clock controls
Programmable security bit for protection of proprietary designs
Software design support featuring the Altera® MAX+PLUS® II
development system on Windows-based PCs, as well as
Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC
System/6000 workstations
■
■
Table 1. MAX 5000 Device Features
Feature EPM5032
9
EPM5064
EPM5128
EPM5130
EPM5192
Usable gates
600
32
1,250
64
2,500
128
8
2,500
128
8
3,750
192
12
Macrocells
Logic array blocks (LABs)
Expanders
1
4
64
128
PIA
36
256
PIA
60
256
PIA
84
384
PIA
72
Routing
Global
24
Maximum user I/O pins
t
t
t
f
(ns)
15
25
25
25
25
PD
(ns)
4
4
4
4
4
ASU
(ns)
10
14
14
14
14
CO
(MHz)
76.9
50
50
50
50
CNT
Altera Corporation
709
A-DS-M5000-05
MAX 5000 Programmable Logic Device Family Data Sheet
■
■
Programming support with Altera’s Master Programming Unit
...and More
Features
(MPU) or programming hardware from third-party manufacturers
Additional design entry and simulation support provided by EDIF,
library of parameterized modules (LPM), Verilog HDL, VHDL, and
other interfaces to popular EDA tools from manufacturers such as
Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys,
Synplicity, and Viewlogic
The MAX 5000 family combines innovative architecture and advanced
process technologies to offer optimum performance, flexibility, and the
highest logic-to-pin ratio of any general-purpose programmable logic
device (PLD) family. The MAX 5000 family provides 600 to 3,750 usable
gates, pin-to-pin delays as fast as 15 ns, and counter frequencies of up to
76.9 MHz (see Table 2).
General
Description
Table 2. MAX 5000 Device Speed Grades
Device
Speed (tPD1)
15 ns
20 ns
25 ns
30 ns
35 ns
EPM5032
EPM5064
EPM5128
EPM5130
EPM5192
v
v
v
v
v
v
v
v
v
v
v
v
v
The MAX 5000 architecture supports 100% TTL emulation and
high-density integration of multiple SSI, MSI, and LSI logic functions. For
example, an EPM5192 device can replace over 100 74-series devices; it can
integrate complete subsystems into a single package, saving board area
and reducing power consumption. MAX 5000 EPLDs are available in a
wide range of packages (see Table 3), including the following:
■
■
■
■
Windowed ceramic and plastic dual in-line (CerDIP and PDIP)
Plastic J-lead chip carrier (PLCC)
Windowed ceramic pin-grid array (PGA)
Plastic quad flat pack (PQFP)
710
Altera Corporation
MAX 5000 Programmable Logic Device Family Data Sheet
Table 3. MAX 5000 Pin Count & Package Options
Device
Pin Count
PLCC
CerDIP
PDIP
PGA
PQFP
EPM5032
EPM5064
EPM5128
EPM5130
EPM5192
28
28
28
44
68
84
84
68
100
84
100
MAX 5000 EPLDs have between 32 and 192 macrocells that are combined
into groups called logic array blocks (LABs). Each macrocell has a
programmable-AND/fixed-ORarray and a configurable register that
provides D, T, JK, or SR operation with independent programmable clock,
clear, and preset functions. To build complex logic functions, each
macrocell can be supplemented with shareable expander product terms
(“shared expanders”) to provide more than 32 product terms per
macrocell.
The MAX 5000 family is supported by Altera’s MAX+PLUS II
development system, a single, integrated package that offers schematic,
text—including the Altera Hardware Description Language (AHDL)—
and waveform design entry, compilation and logic synthesis, simulation
and timing analysis, and device programming. The MAX+PLUS II system
provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other
interfaces for additional design entry and simulation support from other
industry-standard PC- and UNIX workstation-based EDA tools. The
MAX+PLUS II software runs on Windows-based PCs as well as Sun
SPARCstation, HP 9000 Series 700/800, and IBM RISC System/6000
workstations.
9
For more information on the MAX+PLUS II development system, see the
MAX+PLUS II Programmable Logic Development System & Software Data
Sheet.
f
This section provides a functional description of MAX 5000 EPLDs, which
have the following architectural features:
Functional
Description
■
■
■
■
■
■
Logic array blocks
Macrocells
Clocking options
Expander product terms
Programmable interconnect array
I/O control blocks
Altera Corporation
711
MAX 5000 Programmable Logic Device Family Data Sheet
The MAX 5000 architecture is based on the concept of linking high-
performance, flexible logic array modules called LABs. Multiple LABs are
linked via the programmable interconnect array (PIA), a global bus that is
fed by all I/O pins and macrocells. In addition to these basic elements, the
MAX 5000 architecture includes 8 to 20 dedicated inputs, each of which
can be used as a high-speed, general-purpose input. Alternatively, one of
the dedicated inputs can be used as a high-speed global clock for registers.
Logic Array Blocks
MAX 5000 EPLDs contain 1 to 12 LABs. The EPM5032 has a single LAB,
while the EPM5064, EPM5128, EPM5130, and EPM5192 contain multiple
LABs. Each LAB consists of a macrocell array and an expander product-
term array (see Figure 1). The number of macrocells and expanders in the
arrays varies with each device.
Figure 1. MAX 5000 Architecture
8 to 20
Dedicated
Inputs
16
LAB A
Macrocell
Array
LAB
Interconnect
I/O
Control
Block
4 to 16
I/O Pins
per LAB
24
PIA in
PIA
Multi-LAB
Devices Only
Expander
Product-Term
Array
Feedback from
I/O Pins to LAB
(Single-LAB
Devices Only)
To All Other LABs
712
Altera Corporation
MAX 5000 Programmable Logic Device Family Data Sheet
Macrocells are the primary resource for logic implementation. Additional
logic capability is available from expanders, which can be used to
supplement the capabilities of any macrocell. The expander product-term
array consists of a group of unallocated, inverted product terms that can
be used and shared by all macrocells in the LAB to create combinatorial
and registered logic. These flexible macrocells and shareable expanders
facilitate variable product-term designs without the inflexibility of fixed
product-term architectures. All macrocell outputs are globally routed
within an LAB via the LAB interconnect. The outputs of the macrocells
also feed the I/O control block, which consists of groups of
programmable tri-state buffers and I/O pins. In the EPM5064, EPM5128,
EPM5130, and EPM5192 devices, multiple LABs are connected by a PIA.
All macrocells feed the PIA to provide efficient routing for high-fan-in
designs.
Macrocells
The MAX 5000 macrocell consists of a programmable logic array and an
independently configurable register (see Figure 2). The register can be
programmed to emulate D, T, JK, or SR operation, as a flow-through latch,
or bypassed for combinatorial operation. Combinatorial logic is
implemented in the programmable logic array, in which three product
terms that are ORed together feed one input to an XORgate. The second
input to the XORgate is used for complex XORarithmetic logic functions
and for De Morgan’s inversion. The output of the XORgate feeds the
programmable register or bypasses it for combinatorial operation.
9
Altera Corporation
713
MAX 5000 Programmable Logic Device Family Data Sheet
Figure 2. MAX 5000 Device Macrocell
Global Clock
Logic Array
To I/O
Control
Block
(One per LAB)
Output Enable
Preset
Programmable
Register
PRN
To I/O
Control
Block
D/T
Q
CLRN
Array Clock
Clear
Macrocell Feedback
I/O Feedback
From I/O
Control
Block
24 Programmable
Interconnect Signals
(Multi-LAB Devices Only)
8 or 20
Dedicated
Inputs
32 or 64
Expander
Product Terms
Additional product terms (called secondary product terms) are used to
control the output enable, preset, clear, and clock signals. Preset and clear
product terms drive the active-low asynchronous preset and
asynchronous clear inputs to the configurable flipflop. The clock product
term allows each register to have an independent clock and supports
positive- and negative-edge-triggered operation. Macrocells that drive an
output pin can use the output enable product term to control the active-
high tri-state buffer in the I/O control block.
The MAX 5000 macrocell configurability makes it possible to efficiently
integrate complete subsystems into a single device.
Clocking Options
Each LAB supports either global or array clocking. Global clocking is
provided by a dedicated clock signal (CLK) that offers fast clock-to-output
delay times. Because each LAB has one global clock, all flipflop clocks
within the LAB can be positive-edge-triggered from the CLKpin. If the CLK
pin is not used as a global clock, it can be used as a high-speed dedicated
input.
714
Altera Corporation
MAX 5000 Programmable Logic Device Family Data Sheet
In the array clocking mode, each flipflop is clocked by a product term.
Any input pin or internal logic can be used as a clock source. Array
clocking allows each flipflop to be configured for positive- or negative-
edge-triggered operation, giving the macrocell increased flexibility.
Systems that require multiple clocks are easily integrated into MAX 5000
EPLDs.
Each flipflop in an LAB can be clocked by a different array-generated
clock; however, global and array clocking modes cannot be mixed in the
same LAB.
Expander Product Terms
While most logic functions can be implemented with the product terms
available in each macrocell, some logic functions are more complex and
require additional product terms. Although additional macrocells can be
used to supply the needed logic resources, the MAX 5000 architecture can
also use shared expander product terms that provide additional product
terms directly to any macrocell in the same LAB. These expanders help
ensure that logic is synthesized with the fewest possible logic resources to
obtain the fastest possible speed.
Each LAB has 32 shared expanders (except for EPM5032 devices, which
have 64). The expanders can be viewed as a pool of uncommitted product
terms. The expander product-term array (see Figure 3) contains
unallocated, inverted product terms that feed the macrocell array.
Expanders can be used and shared by all product terms in the LAB.
Wherever extra logic is needed (including register control functions),
expanders can be used to implement the logic. These expanders provide
the flexibility to implement register- and product-term-intensive designs
in MAX 5000 EPLDs.
9
Altera Corporation
715
MAX 5000 Programmable Logic Device Family Data Sheet
Figure 3. Expander Product Terms
To Macrocell Array
8 or 20
Dedicated
Inputs
24 Programmable
Interconnect Signals
(Multi-LAB Devices Only)
32 or 64
Expander
Product Terms
Macrocell
Feedbacks
Expanders are fed by all signals in the LAB. One expander can feed all
macrocells in the LAB or multiple product terms in the same macrocell.
Because expanders also feed the secondary product terms of each
macrocell, complex logic functions can be implemented without using
additional macrocells. A small delay (tSEXP) is incurred when shared
expanders are used.
Programmable Interconnect Array
The multi-LAB MAX 5000 devices—EPM5064, EPM5128, EPM5130, and
EPM5192 devices—use a PIA to route signals between the various LABs.
The PIA, which is fed by all macrocell and I/O pin feedbacks, routes only
the signals required for implementing logic in an LAB. While the routing
delays of segmented routing schemes in masked or field-programmable
gate arrays (FPGAs) are cumulative, variable, and path-dependent, the
MAX 5000 PIA has a fixed delay. The PIA thus eliminates skew between
signals and makes timing performance easy to predict.
I/O Control Blocks
Each LAB has an I/O control block that allows each I/O pin to be
individually configured for input, output, or bidirectional operation (see
Figure 4). The I/O control block is fed by the macrocell array. A dedicated
macrocell product term controls a tri-state buffer, which drives the I/O
pin.
716
Altera Corporation
MAX 5000 Programmable Logic Device Family Data Sheet
Figure 4. I/O Control Block
OE Control (from Macrocell Product)
From Macrocell
Macrocell Feedback
I/O Pin Feedback
The MAX 5000 architecture provides dual I/O feedback in which
macrocell and I/O pin feedbacks are independent, allowing maximum
flexibility. When an I/O pin is configured as an input, the associated
macrocell can be used for buried logic. Using an I/O pin as an input in
single-LAB devices reduces the number of available expanders by two. In
multi-LAB devices, I/O pins feed the PIA directly.
All MAX 5000 EPLDs contain a programmable security bit that controls
access to the data programmed into the device. When this bit is
programmed, a proprietary design implemented in the device cannot be
copied or retrieved. This feature provides a high level of design security,
because programmed data within EPROM cells is invisible. The security
bit that controls this function, as well as all other program data, is reset
only when the device is erased.
Design Security
Generic Testing
MAX 5000 EPLDs are fully functionally tested. Complete testing of each
programmable EPROM bit and all internal logic elements ensures 100%
programming yield. Test patterns can be used and then erased during
early stages of the device production flow. The devices also contain
on-board logic test circuitry to allow verification of function and AC
specifications during the production flow. AC test measurements are
taken under conditions equivalent to those in Figure 5.
9
Altera Corporation
717
MAX 5000 Programmable Logic Device Family Data Sheet
Figure 5. AC Test Conditions
VCC
Power supply transients can affect AC
measurements. Simultaneous transitions
of multiple outputs should be avoided for
accurate measurement. Threshold tests
must not be performed under AC
conditions. Large-amplitude, fast ground-
current transients normally occur as the
device outputs discharge the load
464 Ω
Device
Output
to Test
System
capacitances. When these transients flow
through the parasitic inductance between
the device ground pin and the test system
ground, significant reductions in
250 Ω
C1 (includes JIG
capacitance)
Device input
rise and fall
times < 3 ns
observable noise immunity can result.
All MAX 5000 EPLDs can be programmed on Windows-based PCs with
the MAX+PLUS II Programmer, an Altera Logic Programmer card, the
Master Programming Unit (MPU), and the appropriate device adapter.
The MPU checks continuity to ensure adequate electrical contact between
the adapter and the device.
Device
Programming
For more information, see the Altera Programming Hardware Data Sheet.
f
The MAX+PLUS II software can use text- or waveform-format test vectors
created with the MAX+PLUS II Text Editor or Waveform Editor to test a
programmed device. For added design verification, designers can
perform functional testing to compare the functional behavior of a
MAX 5000 EPLD with the simulation results. This feature requires a
device adapter with the “PLM-” prefix.
Data I/O, BP Microsystems, and other programming hardware
manufacturers also offer programming support for Altera devices.
For more information, see Programming Hardware Manufacturers.
f
MAX 5000 devices in 100-pin QFP packages are shipped in special plastic
carriers to protect the QFP leads. Each carrier can be used with a
prototype development socket and programming hardware available
from Altera or third-party programming manufacturers such as Data I/O
and BP Microsystems. This carrier technology makes it possible to
program, test, erase, and reprogram devices without exposing the leads to
mechanical stress.
QFP Carrier &
Development
Socket
For detailed information and carrier dimensions, refer to the QFP Carrier
& Development Socket Data Sheet and Application Note 71 (Guidelines for
Handling J-Lead & QFP Devices).
f
718
Altera Corporation
MAX 5000 Programmable Logic Device Family Data Sheet
Tables 4 through 8 provide information on absolute maximum ratings,
recommended operating conditions, operating conditions, and
capacitance for MAX 5000 devices.
Operating
Conditions
Table 4. MAX 5000 Device Absolute Maximum Ratings Note (1)
Symbol
Parameter
Conditions
Min
Max
Unit
VCC
VI
Supply voltage
With respect to ground (2)
–2.0
–2.0
–25
–65
–65
7.0
7.0
V
DC input voltage
V
IOUT
TSTG
TAMB
TJ
DC output current, per pin
Storage temperature
Ambient temperature
Junction temperature
25
mA
° C
° C
° C
° C
No bias
135
135
150
135
Under bias
Ceramic packages, under bias
Plastic packages, under bias
Table 5. MAX 5000 Device Recommended Operating Conditions
Symbol
Parameter
Conditions
Min
Max
Unit
VCC
VI
Supply voltage
(3), (4)
4.75 (4.5) 5.25 (5.5)
V
V
Input voltage
–0.3
0
VCC+0.3
VCC
70
VO
TA
Output voltage
V
Ambient temperature
For commercial use
For industrial use
0
° C
° C
ns
ns
–40
85
tR
tF
Input rise time
Input fall time
100
100
9
Table 6. MAX 5000 Device DC Operating Conditions Note (5)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIH
VIL
VOH
VOL
II
High-level input voltage
Low-level input voltage
High-level TTL output voltage
Low-level output voltage
2.0
–0.3
2.4
VCC + 0.3
0.8
V
V
IOH = –4 mA DC (6)
IOL = 8 mA DC (6)
V
0.45
10
V
Leakage current of dedicated inputs VI = VCC or ground
–10
–40
µA
µA
IOZ
I/O pin tri-state output off-state
current
VO = VCC or ground
40
Table 7. EPM5032 MAX 5000 Device Capacitance
Symbol
Parameter
Conditions
Min
Max
Unit
CIN
Input pin capacitance
I/O pin capacitance
VIN = 0 V, f = 1.0 MHz
VOUT = 0 V, f = 1.0 MHz
10
12
pF
pF
CI/O
Altera Corporation
719
MAX 5000 Programmable Logic Device Family Data Sheet
Table 8. EPM5064, EPM5128, EPM5130 & EPM5192 MAX 5000 Device Capacitance
Symbol
Parameter
Conditions
Min
Max
Unit
CIN
Input pin capacitance
I/O pin capacitance
VIN = 0 V, f = 1.0 MHz
VOUT = 0 V, f = 1.0 MHz
10
20
pF
pF
CI/O
Notes to tables:
(1) See the Operating Requirements for Altera Devices Data Sheet in this data book.
(2) Minimum DC input is –0.3 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to 7.0 V for
input currents less than 100 mA and periods shorter than 20 ns.
(3) Numbers in parentheses are for industrial-temperature-range devices.
(4) Maximum VCC rise time for MAX 5000 devices is 10 ms.
(5) Typical values are for TA = 25° C and VCC = 5.0 V.
(6) The IOH parameter refers to high-level TTL output current; the IOL parameter refers to low-level TTL output current.
Figure 6 shows typical output drive characteristics of MAX 5000 devices.
Figure 6. Output Drive Characteristics of MAX 5000 Devices
250
IOL
200
VCCINT = 5.0 V
VCCIO = 5.0 V
Room Temperature
150
Typical IO
Output
Current (mA)
100
50
IOH
2
3
3.8 4
5
1
VO Output Voltage (V)
MAX 5000 EPLD timing can be analyzed with the MAX+PLUS II
software, with a variety of other industry-standard EDA simulators and
timing analyzers, or with the timing model shown in Figure 7. MAX 5000
EPLDs have fixed internal delays that allow the designer to determine the
worst-case timing for any design. The MAX+PLUS II software provides
timing simulation, point-to-point delay prediction, and detailed timing
analysis for system-level performance evaluation.
Timing Model
720
Altera Corporation
MAX 5000 Programmable Logic Device Family Data Sheet
Figure 7. MAX 5000 Timing Model
Single-LAB EPLDs
Shared Expander
Delay
tSEXP
Logic Array
Control Delay
tLAC
Register
Delay
Input
Delay
tIN
Logic Array
Delay
tLAD
Output
Delay
tOD
tXZ
tZX
tRD
tCOMB
tLATCH
tCLR
tPRE
tSU
Global
Clock Delay
tICS
tH
I/O
Delay
tIO
Array Clock
Delay
tIC
Feedback
Delay
tFD
Multi-LAB EPLDs
Shared Expander
Delay
tSEXP
Logic Array
Control Delay
tLAC
Register
Delay
Input
Delay
tIN
Logic Array
Delay
tLAD
tRD
9
tCOMB
tLATCH
tCLR
tPRE
tSU
Output
Delay
tOD
Global Clock
Delay
tICS
tH
tXZ
tZX
Array Clock
Delay
PIA
Delay
tPIA
tIC
Feedback
Delay
tFD
I/O
Delay
tIO
Altera Corporation
721
MAX 5000 Programmable Logic Device Family Data Sheet
Timing information can be derived from the timing model and parameters
for a particular EPLD. External timing parameters are calculated with the
sum of internal parameters and represent pin-to-pin timing delays.
Figure 8 shows the internal timing relationship for internal and external
delay parameters.
See Application Note 78 (Understanding MAX 5000 & Classic Timing) for
more information on EPLD timing.
f
722
Altera Corporation
MAX 5000 Programmable Logic Device Family Data Sheet
Figure 8. Switching Waveforms
Input Mode
In multi-LAB EPLDs,
I/O pins that are used
as inputs traverse the
PIA.
tIN
Input Pin
I/O Pin
tIO
t
and t < 3 ns.
F
tSEXP
R
Inputs are driven at
3 V for a logic high
and 0 V for a logic
low.
Expander Array
Delay
tLAC, tLAD
Logic Array
Input
tCOMB
Logic Array
Output
tOD
Output Pin
Clock Pin
Array Clock Mode
tR
tACH
tACL
tF
tIN
Clock into
Logic Array
tIC
Clock from
Logic Array
tSU
tH
Data from
Logic Array
tRD, tLATCH
tCLR, tPRE
tFD
tFD
Register Output to
Local LAB Logic Array
tPIA
9
Register Output
to another LAB
Global Clock Mode
tR
tCH
tCL
tF
Global Clock Pin
tIN
tICS
Global Clock
at Register
tSU
tH
Data from
Logic Array
Output Mode
Clock from
Logic Array
tRD
tOD
Data from
Logic Array
tXZ
tZX
High-Impedance
State
Output Pin
Altera Corporation
723
MAX 5000 Programmable Logic Device Family Data Sheet
Tables 9 and 10 show EPM 5032 timing parameters.
Table 9. EPM5032 External Timing Parameters Note (1)
Symbol
Parameter
Conditions
Speed Grade
-20
Unit
-15
-25
Min Max Min Max Min Max
tPD1
tPD2
tSU
Input to non-registered output
I/O input to non-registered output
Global clock setup time
Global clock hold time
C1 = 35 pF
C1 = 35 pF
15.0
15.0
20.0
20.0
25.0
25.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
9.0
0.0
12.0
0.0
15.0
0.0
tH
tCO1
tCH
Global clock to output delay
Global clock high time
C1 = 35 pF
10.0
15.0
12.0
18.0
15.0
22.0
6.0
6.0
5.0
5.0
7.0
7.0
6.0
6.0
8.0
8.0
8.0
8.0
tCL
Global clock low time
tASU
tAH
Array clock setup time
Array clock hold time
tACO1
tACH
tACL
tODH
tCNT
fCNT
Array clock to output delay
Array clock high time
C1 = 35 pF
(2)
6.0
7.0
1.0
7.0
9.0
1.0
9.0
11.0
1.0
Array clock low time
Output data hold time after clock
Minimum global clock period
C1 = 35 pF (3)
(4)
13.0
13.0
16.0
16.0
20.0
20.0
Maximum internal global clock
frequency
76.9
62.5
50.0
tACNT
fACNT
fMAX
Minimum array clock period
ns
Maximum internal array clock frequency (4)
Maximum clock frequency (5)
76.9
83.3
62.5
71.4
50.0
62.5
MHz
MHz
724
Altera Corporation
MAX 5000 Programmable Logic Device Family Data Sheet
Table 10. EPM5032 Internal Timing Parameters
Note (6)
Symbol
Parameter
Conditions
Speed Grade
-20
Unit
-15
-25
Min Max Min Max Min Max
tIN
Input pad and buffer delay
I/O input pad and buffer delay
Expander array delay
Logic array delay
3.0
3.0
8.0
7.0
4.0
4.0
7.0
7.0
5.0
5.0
7.0
7.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tIO
tSEXP
tLAD
tLAC
tOD
tZX
10.0
10.0
4.0
15.0
13.0
4.0
Logic control array delay
Output buffer and pad delay
Output buffer enable delay
Output buffer disable delay
Register setup time
C1 = 35 pF
C1 = 35 pF
C1 = 5 pF
4.0
4.0
7.0
7.0
tXZ
7.0
7.0
tSU
4.0
5.0
4.0
8.0
5.0
tLATCH
tRD
tCOMB
tH
Flow-through latch delay
Register delay
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Combinatorial delay
Register hold time
10.0
tIC
Array clock delay
7.0
2.0
1.0
5.0
5.0
8.0
2.0
1.0
6.0
6.0
10.0
3.0
1.0
9.0
9.0
tICS
tFD
tPRE
tCLR
Global clock delay
Feedback delay
Register preset time
Register clear time
9
Altera Corporation
725
MAX 5000 Programmable Logic Device Family Data Sheet
Table 11. EPM5064, EPM5128, EPM5130 & EPM5192 External Timing Parameters
Note (1)
Symbol
Parameter
Conditions
Speed Grade (7)
-2
Unit
-1
EPM5064
EPM5128
EPM5130
EPM5192
Min Max Min Max Min Max
tPD1
tPD2
tSU
Input to non-registered output
I/O input to non-registered output
Global clock setup time
Global clock hold time
C1 = 35 pF
25.0
40.0
30.0
45.0
35.0
55.0
ns
ns
C1 = 35 pF
15.0
0.0
20.0
0.0
25.0
0.0
ns
tH
ns
tCO1
tCH
Global clock to output delay
Global clock high time
C1 = 35 pF
14.0
16.0
20.0
ns
8.0
8.0
5.0
6.0
10.0
10.0
6.0
12.5
12.5
10.0
10.0
ns
tCL
Global clock low time
ns
tASU
tAH
Array clock setup time
ns
Array clock hold time
8.0
ns
tACO1
tACH
tACL
tCNT
tODH
fCNT
tACNT
fACNT
fMAX
Array clock to output delay
Array clock high time
C1 = 35 pF
(2)
25.0
20.0
20.0
30.0
25.0
25.0
35.0
30.0
30.0
ns
11.0
9.0
14.0
11.0
16.0
14.0
ns
Array clock low time
ns
Minimum global clock period
Output data hold time after clock
ns
C1 = 35 pF (3)
2.0
2.0
2.0
ns
Maximum internal global clock frequency (4)
Minimum array clock period
50.0
40.0
33.3
MHz
ns
Maximum internal array clock frequency (4)
50.0
62.5
40.0
50.0
33.3
40.0
MHz
MHz
Maximum clock frequency
(5)
726
Altera Corporation
MAX 5000 Programmable Logic Device Family Data Sheet
Table 12. EPM5064, EPM5128, EPM5130 & EPM5192 Internal Timing Parameters
Note (6)
Symbol
Parameter
Conditions
Speed Grade (7)
-2
Unit
-1
EPM5064
EPM5128
EPM5130
EPM5192
Min Max Min Max Min Max
tIN
Input pad and buffer delay
I/O input pad and buffer delay
Expander array delay
Logic array delay
5.0
6.0
7.0
6.0
11.0
11.0
20.0
14.0
13.0
6.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tIO
tSEXP
tLAD
tLAC
tOD
tZX
12.0
12.0
10.0
5.0
14.0
14.0
12.0
5.0
Logic control array delay
Output buffer and pad delay
Output buffer enable delay
Output buffer disable delay
Register setup time
C1 = 35 pF
C1 = 35 pF
C1 = 5 pF
10.0
10.0
11.0
11.0
13.0
13.0
tXZ
tSU
6.0
4.0
8.0
6.0
12.0
8.0
tLATCH
tRD
tCOMB
tH
Flow-through latch delay
Register delay
3.0
1.0
3.0
4.0
2.0
4.0
4.0
2.0
4.0
Combinatorial delay
Register hold time
tIC
Array clock delay
14.0
3.0
16.0
2.0
16.0
1.0
tICS
tFD
Global clock delay
Feedback delay
1.0
1.0
2.0
tPRE
tCLR
tPIA
Register preset time
Register clear time
5.0
6.0
7.0
5.0
6.0
7.0
9
Programmable interconnect array
delay
14.0
16.0
20.0
Notes to tables:
(1) Operating conditions are specified in Table 5 on page 719.
(2) This parameter is measured with a positive-edge-triggered clock at the register. For negative-edge clocking, the
tACH and tACL parameters must be swapped.
(3) This parameter is a guideline that is sample-tested only. It is based on extensive device characterization and applies
to both global and array clocking.
(4) For EPM5032 devices, this parameter is measured with a 32-bit counter programmed into the device. For EPM5064,
EPM5128, EPM5130, and EPM5192 devices, this parameter is measured with a 16-bit counter programmed into each
LAB.
(5) The fMAX values represent the highest frequency for pipelined data.
(6) For information on internal timing parameters, refer to Application Note 78 (Understanding MAX 5000 & Classic
Timing) in this data book.
(7) The EPM 5064, EPM 5128, EPM 5130, and EPM 5132 are listed without speed grade designators.
Altera Corporation
727
MAX 5000 Programmable Logic Device Family Data Sheet
Figure 9 shows the typical supply current versus frequency of MAX 5000
devices.
Figure 9. I vs. Frequency for MAX 5000 Devices (Part 1 of 2)
CC
EPM5032
EPM5064
240
200
160
120
80
200
150
Typical ICC
Active (mA)
VCC = 5.0 V
Room Temperature
VCC = 5.0 V
Room Temperature
Typical ICC
Active (mA)
100
50
40
100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 76.9MHz
100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 50 MHz
Frequency
Frequency
EPM5128
EPM5130
500
400
400
300
300
Typical ICC
Active (mA)
VCC = 5.0 V
Room Temperature
V
CC = 5.0 V
Room Temperature
Typical ICC
Active (mA)
200
200
100
100
100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 50 MHz
100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 50 MHz
Frequency
Frequency
728
Altera Corporation
MAX 5000 Programmable Logic Device Family Data Sheet
Figure 9. I vs. Frequency for MAX 5000 Devices (Part 2 of 2)
CC
EPM5192
500
400
300
VCC = 5.0 V
Room Temperature
Typical ICC
Active (mA)
200
100
100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 50 MHz
Frequency
Tables 13 through 22 show the pin names and numbers for the pins in each
MAX 5000 device package.
Device
Pin-Outs
9
Altera Corporation
729
MAX 5000 Programmable Logic Device Family Data Sheet
Table 13. EPM5032 Dedicated Pin-Outs
Pin Name 28-Pin PLCC
28-Pin DIP
INPUT/CLK
9
2
INPUT
GND
6, 7, 8, 20, 21, 22, 23
1, 13, 14, 15, 16, 27, 28
15, 28
1, 14
8, 21
7, 22
VCC
Table 14. EPM5032 I/O Pin-Outs
LAB
MC
28-Pin
PLCC
28-Pin
DIP
LAB
MC
28-Pin
PLCC
28-Pin
DIP
A
1
2
3
4
5
6
7
8
9
10
3
–
4
–
5
–
6
–
9
–
B
17
24
17
–
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
–
–
11
–
25
–
18
–
12
–
26
–
19
–
13
–
27
–
20
–
16
–
2
23
–
10
11
12
13
14
15
16
–
17
–
10
–
3
24
–
–
18
–
11
–
4
25
–
–
19
–
12
–
5
26
–
–
730
Altera Corporation
MAX 5000 Programmable Logic Device Family Data Sheet
Table 15. EPM5064 Dedicated Pin-Outs
Pin Name
44-Pin PLCC
INPUT/CLK
INPUT
GND
34
9, 11, 12, 13, 31, 33, 35
10, 21, 32, 43
VCC
3, 14, 25, 36
Table 16. EPM5064 I/O Pin-Outs (Part 1 of 2)
LAB
MC
44-Pin
PLCC
LAB
MC
44-Pin
PLCC
A
1
2
4
5
6
7
8
–
–
–
–
–
–
–
–
–
–
B
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
15
16
17
18
19
20
22
23
–
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
–
–
–
–
9
–
–
–
Altera Corporation
731
MAX 5000 Programmable Logic Device Family Data Sheet
Table 16. EPM5064 I/O Pin-Outs (Part 2 of 2)
LAB
MC
44-Pin
PLCC
LAB
MC
44-Pin
PLCC
C
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
24
26
27
28
29
30
–
D
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
37
38
39
40
41
42
44
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
732
Altera Corporation
MAX 5000 Programmable Logic Device Family Data Sheet
Table 17. EPM5128 Dedicated Pin-Outs
Pin Name 68-Pin PLCC
68-Pin PGA
INPUT/CLK
1
B6
INPUT
GND
2, 32, 34, 35, 36, 66, 68
16, 33, 50, 67
A6, L4, L5, L6, K6, A8, A7
B7, E2, G10, K5
VCC
3, 20, 37, 54
B5, E10, G2, K7
Table 18. EPM5128 I/O Pin-Outs (Part 1 of 3)
LAB
MC
68-Pin 68-Pin
PLCC PGA
LAB
MC
68-Pin 68-Pin
PLCC PGA
A
1
4
5
6
7
8
9
A5
B
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
12
C2
2
B4
A4
B3
A3
A2
B2
B1
–
13
14
15
17
–
C1
D2
D1
E1
–
3
4
5
6
7
10
11
–
–
–
8
–
–
9
–
–
10
11
12
13
14
15
16
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
9
–
–
–
–
–
–
–
–
–
–
–
–
Altera Corporation
733
MAX 5000 Programmable Logic Device Family Data Sheet
Table 18. EPM5128 I/O Pin-Outs (Part 2 of 3)
LAB
MC
68-Pin 68-Pin
PLCC PGA
LAB
MC
68-Pin 68-Pin
PLCC PGA
C
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
18
F2
E
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
38
L7
19
21
22
23
–
F1
G1
H2
H1
–
39
40
41
42
43
44
45
–
K8
L8
K9
L9
L10
K10
K11
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
D
24
25
26
27
28
29
30
31
–
J2
J1
K1
K2
L2
K3
L3
K4
–
F
46
47
48
49
51
–
J10
J11
H10
H11
G11
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
734
Altera Corporation
MAX 5000 Programmable Logic Device Family Data Sheet
Table 18. EPM5128 I/O Pin-Outs (Part 3 of 3)
LAB
MC
68-Pin 68-Pin
PLCC PGA
LAB
MC
68-Pin 68-Pin
PLCC PGA
G
97
98
99
52
F10
H
113
58
C10
53
55
56
57
–
F11
E11
D10
D11
–
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
59
60
61
62
63
64
65
–
C11
B11
B10
A10
B9
A9
B8
–
100
101
102
103
104
105
106
107
108
109
110
111
112
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
9
Altera Corporation
735
MAX 5000 Programmable Logic Device Family Data Sheet
Table 19. EPM5130 Dedicated Pin-Outs
Pin Name
84-Pin PLCC
100-Pin PGA
100-Pin PQFP
INPUT/CLK
INPUT
1
C7
16
2, 5, 6, 7, 36, 37,
38, 41, 42, 43, 44, A10, B5, B7, B9,
47, 48, 49, 78, 79, C6, L7, L8, M5,
A5, A7, A8, A9,
9, 10, 11, 14, 15,
16, 17, 20, 21, 22,
59, 60, 61, 64, 65,
66, 67, 70, 71, 72
80, 83, 84
M7, M9, N4, N5,
N6, N7, N9
GND
VCC
19, 20, 39, 40, 61, B8, C8, F2, F3,
62, 81, 82
3, 4, 23, 24, 45, 46, A6, B6, F12, F13, 18, 19, 43, 44, 68,
65, 66 H1, H2, M8, N8 69, 93, 94
12, 13, 37, 38, 62,
H11, H12, L6, M6 63, 87, 88
Table 20. EPM5130 I/O Pin-Outs (Part 1 of 3)
LAB MC 84-Pin 100-Pin 100-Pin LAB MC 84-Pin 100-Pin 100-Pin
PLCC PGA PQFP PLCC PGA PQFP
A
1
8
B13
1
2
3
4
5
6
7
8
–
–
–
–
–
–
–
–
B
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
14
A4
23
2
9
C12
A13
B12
A12
B11
A11
B10
–
15
16
17
18
21
–
B4
A3
A2
B3
A1
B2
B1
–
24
25
26
27
28
29
30
–
3
10
11
12
13
–
4
5
6
7
8
–
–
9
–
–
10
11
12
13
14
15
16
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
736
Altera Corporation
MAX 5000 Programmable Logic Device Family Data Sheet
Table 20. EPM5130 I/O Pin-Outs (Part 2 of 3)
LAB MC 84-Pin 100-Pin 100-Pin LAB MC 84-Pin 100-Pin 100-Pin
PLCC PGA PQFP PLCC PGA PQFP
C
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
22
C2
31
E
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
50
M1
51
25
26
27
28
29
–
C1
D2
D1
E2
E1
F1
G2
–
32
33
34
35
36
39
40
–
51
52
53
54
55
–
L2
N1
M2
N2
M3
N3
M4
–
52
53
54
55
56
57
58
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
D
30
31
32
33
34
35
–
G3
G1
H3
J1
J2
K1
K2
L1
–
41
42
45
46
47
48
49
50
–
F
56
57
58
59
60
63
–
N10
M10
N11
N12
M11
M13
M12
M13
–
73
74
75
76
77
78
79
80
–
9
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Altera Corporation
737
MAX 5000 Programmable Logic Device Family Data Sheet
Table 20. EPM5130 I/O Pin-Outs (Part 3 of 3)
LAB MC 84-Pin 100-Pin 100-Pin LAB MC 84-Pin 100-Pin 100-Pin
PLCC PGA PQFP PLCC PGA PQFP
G
97
98
99
64
L12
81
H
113 72
G11
91
67
68
L13
K12
K13
J12
J13
H13
G12
–
82
83
84
85
86
89
90
–
114 73
115 74
116 75
117 76
118 77
G13
F11
E13
E12
D13
D12
C13
–
92
95
96
97
98
99
100
–
100 69
101 70
102 71
103
104
105
106
107
108
109
110
111
112
–
–
–
–
–
–
–
–
–
–
119
120
121
122
123
124
125
126
127
128
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
738
Altera Corporation
MAX 5000 Programmable Logic Device Family Data Sheet
Table 21. EPM5192 Dedicated Pin-Outs
Pin Name
84-Pin PLCC
84-Pin PGA
INPUT/CLK
INPUT
GND
1
A6
A5, K6, J6, J7, L7, C7, C6
18, 19, 39, 40, 60, 61, 81, 82 A7, B7, E1, E2, G10, G11, K5, L5
3, 24, 45, 66 B5, E10, G2, K7
2, 41, 42, 43, 44, 83, 84
VCC
Table 22. EPM5192 I/O Pin-Outs (Part 1 of 4)
LAB
MC
84-Pin 84-Pin
PLCC PGA
LAB
MC
84-Pin 84-Pin
PLCC PGA
A
1
4
5
6
7
8
9
C5
B
17
12
C2
2
A4
B4
A3
A2
B3
A1
B2
–
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
13
14
15
–
B1
C1
D2
–
3
4
5
6
–
–
7
10
11
–
–
–
8
–
–
9
–
–
10
11
12
13
14
15
16
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
9
–
–
–
–
–
–
–
–
–
–
–
–
Altera Corporation
739
MAX 5000 Programmable Logic Device Family Data Sheet
Table 22. EPM5192 I/O Pin-Outs (Part 2 of 4)
LAB
MC
84-Pin 84-Pin
PLCC PGA
LAB
MC
84-Pin 84-Pin
PLCC PGA
C
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
16
D1
E
65
27
H2
17
20
21
–
E3
F2
F3
–
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
28
29
30
–
J1
K1
J2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
D
22
23
25
26
–
G3
G1
F1
H1
–
F
31
32
33
34
35
36
37
38
–
L1
K2
K3
L2
L3
K4
L4
J5
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
740
Altera Corporation
MAX 5000 Programmable Logic Device Family Data Sheet
Table 22. EPM5192 I/O Pin-Outs (Part 3 of 4)
LAB
MC
84-Pin 84-Pin
PLCC PGA
LAB
MC
84-Pin 84-Pin
PLCC PGA
G
97
98
99
46
L6
I
129
58
H11
47
48
49
50
51
52
53
–
L8
K8
L9
L10
K9
L11
K10
–
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
59
62
63
–
F10
G9
F9
–
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
H
54
55
56
57
–
J10
K11
J11
H10
–
J
64
65
67
68
–
F11
E11
E9
D11
–
9
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Altera Corporation
741
MAX 5000 Programmable Logic Device Family Data Sheet
Table 22. EPM5192 I/O Pin-Outs (Part 4 of 4)
LAB
MC
84-Pin 84-Pin
PLCC PGA
LAB
MC
84-Pin 84-Pin
PLCC PGA
K
161
69
D10
L
177
73
A11
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
70
71
72
–
C11
B11
C10
–
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
74
75
76
77
78
79
80
–
B10
B9
A10
A9
B8
A8
B6
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
742
Altera Corporation
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Results For: EPM5192*
0 part numbers found and 9 obsolete part numbers found
Obsolete Part Numbers
Part Number Format
Buying Altera Devices
Part Number
EPM5192GC-2
EPM5192GC
Last Order Date Last Ship Date Replacement
Notes
9/30/96
9/30/96
1/31/96
12/31/96
12/31/96
3/31/96
EPM5192GC-1
EPM5192GC-1
ADV 9609
ADV 9609
EPM5192GM883B
(5962-9206201MYX)
No direct replacement PDN 9513
No direct replacement PDN 9513
No direct replacement PDN 9513
EPM5192GM883B-2 1/31/96
(5962-9206202MYX)
3/31/96
EPM5192GM
EPM5192JC-2
EPM5192JC
EPM5192JI
1/31/96
9/30/96
9/30/96
9/30/96
9/30/96
3/31/96
12/31/96
12/31/96
12/31/96
12/31/96
EPM5192JC-1
EPM5192JC-1
EPM5192LI
ADV 9609
ADV 9609
ADV 9609
ADV 9609
EPM5192LC-2
EPM5192LC-1
Search
EPM5192*
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Results For: EPM5064*
0 part numbers found and 4 obsolete part numbers found
Obsolete Part Numbers
Part Number Format
Buying Altera Devices
Part Number Last Order Date Last Ship Date Replacement
Notes
EPM5064JC-2 9/30/96
12/31/96
12/31/96
12/31/96
3/31/96
EPM5064JC-1
EPM5064JC-1
EPM5064LI
ADV 9609
ADV 9609
ADV 9609
EPM5064JC
EPM5064JI
EPM5064JM
9/30/96
9/30/96
1/31/96
No direct replacement PDN 9513
Search
EPM5064*
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Literature
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Results For: EPM5128*
0 part numbers found and 13 obsolete part numbers found
Obsolete Part Numbers
Part Number Format
Buying Altera Devices
Part Number
EPM5128GC-2
EPM5128GC
Last Order Date Last Ship Date Replacement
Notes
9/30/96
9/30/96
1/31/96
12/31/96
12/31/96
3/31/96
EPM5128GC-1
EPM5128GC-1
ADV 9609
ADV 9609
EPM5128GM883B
(5962-8946801XC)
No direct replacement PDN 9513
EPM5128GM883B-2 1/31/96
3/31/96
No direct replacement PDN 9513
No direct replacement PDN 9513
EPM5128GM
EPM5128JC-2
EPM5128JC
EPM5128JI-2
EPM5128JI
1/31/96
9/30/96
9/30/96
9/30/96
9/30/96
7/30/93
3/31/96
12/31/96
12/31/96
12/31/96
12/31/96
12/31/93
EPM5128JC-1
EPM5128JC-1
EPM5128LI-2
EPM5128LI-2
ADV 9609
ADV 9609
ADV 9609
ADV 9609
EPM5128JM883B
(5962-8946801)
No direct replacement -
EPM5128JM
EPM5128LI-1
EPM5128LI
1/31/96
9/30/96
9/30/96
3/31/96
No direct replacement PDN 9513
No direct replacement PDN 9610
12/31/96
12/31/96
EPM5128LI-2
Search
ADV 9609
EPM5128*
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Literature
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Results For: EPM5130*
0 part numbers found and 20 obsolete part numbers found
Obsolete Part Numbers
Part Number Format
Buying Altera Devices
Part Number
EPM5130GC-2
EPM5130GI
Last Order Date Last Ship Date Replacement
Notes
9/30/96
9/30/96
1/31/96
12/31/96
12/31/96
3/31/96
EPM5130GC-1
ADV 9609
No direct replacement PDN 9610
No direct replacement PDN 9513
EPM5130GM883B
(5962-9314401MZX)
EPM5130GM883B-2 1/31/96
(5962-9314402MZX)
3/31/96
No direct replacement PDN 9513
No direct replacement PDN 9513
EPM5130GM
EPM5130JC-2
EPM5130JI-2
EPM5130JI
1/31/96
9/30/96
9/30/96
9/30/96
1/31/96
9/30/96
9/30/96
9/30/96
9/30/96
9/30/96
9/30/96
9/30/96
9/30/96
10/31/96
3/31/96
12/31/96
12/31/96
12/31/96
3/31/96
EPM5130JC-1
ADV 9609
No direct replacement PDN 9610
No direct replacement PDN 9610
No direct replacement PDN 9513
EPM5130JM
EPM5130LC-2
EPM5130LI-2
EPM5130LI
12/31/96
12/31/96
12/31/96
12/31/96
12/31/96
12/31/96
12/31/96
12/31/96
12/31/96
EPM5130LC-1
ADV 9609
No direct replacement PDN 9610
No direct replacement PDN 9610
EPM5130QC-2
EPM5130QI
EPM5130QC-1
ADV 9609
No direct replacement PDN 9610
EPM5130WC-1
EPM5130WC-2
EPM5130WC
EPM5130QC-1
EPM5130QC-1
EPM5130QC
ADV 9609
ADV 9609
ADV 9609
EPM5130WM883B
(5962-9314401MXX)
No direct replacement PDN 9513
No direct replacement PDN 9513
EPM5130WM883B-2 10/31/96
(5962-9314402MXX)
12/31/96
12/31/96
EPM5130WM
10/31/96
No direct replacement PDN 9513
Search
EPM5130*
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Results For: EPM5032*
0 part numbers found and 19 obsolete part numbers found
Obsolete Part Numbers
Part Number Format
Buying Altera Devices
Part Number
Last Order Date Last Ship Date Replacement
Notes
EPM5032DC-17
EPM5032DC-25
EPM5032DI-25
EPM5032DM-25
9/30/96
9/30/96
9/30/96
1/31/96
12/31/96
12/31/96
12/31/96
3/31/96
3/31/96
EPM5032DC-15
EPM5032DC-20
EPM5032PI-25
ADV 9609
ADV 9609
ADV 9609
PDN 9513
PDN 9513
No direct replacement
No direct replacement
EPM5032DM883B 1/31/96
(5962-9061102XA)
EPM5032JC-17
EPM5032JC-25
EPM5032JI-20
EPM5032JI-25
EPM5032JM-25
9/30/96
9/30/96
9/30/96
9/30/96
1/31/96
12/31/96
12/31/96
12/31/96
12/31/96
3/31/96
EPM5032JC-15
ADV 9609
ADV 9609
PDN 9610
ADV 9609
PDN 9513
EPM5032JC-20
No direct replacement
EPM5032LI-25
No direct replacement
EPM5032JM883B 7/30/93
12/31/93
12/31/93
12/31/96
No direct replacement
No direct replacement
EPM5032LC-15
-
EPM5032JM
7/30/93
9/30/96
-
EPM5032LC-17
ADV 9609
EPM5032LC-25
EPM5032PC-17
EPM5032SC-15
EPM5032SC-17
9/30/96
9/30/96
6/30/97
9/30/96
12/31/96
12/31/96
12/31/97
12/31/96
EPM5032LC-20
ADV 9609
ADV 9609
PDN 9624
EPM5032PC-15
No direct replacement
Short Term EPM5032SC-15,
Long Term No direct replacement
ADV 9609
ADV 9609
ADV 9609
EPM5032SC-20
EPM5032SC-25
9/30/96
9/30/96
12/31/96
12/31/96
Short Term EPM5032SC-15,
Long Term No direct replacement
Short Term EPM5032SC-15,
Long Term No direct replacement
Search
EPM5032*
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Copyright © 1995-2004 Altera Corporation, 101 Innovation Drive, San Jose, California 95134, USA
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