EPM7128AEFC100-4 [ALTERA]
EE PLD, 4.5ns, CMOS, PBGA100;
| 型号： | EPM7128AEFC100-4 |
| 厂家： | 
ALTERA CORPORATION |
| 描述： | EE PLD, 4.5ns, CMOS, PBGA100 |
| 文件： | 总68页 (文件大小：1559K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Includes
MAX 7000AE
MAX 7000A
Programmable Logic
Device Family
®
June 1999, ver. 2.01
Data Sheet
■
■
High-performance CMOS EEPROM-based programmable logic
devices (PLDs) built on second-generation Multiple Array MatriX
(MAX®) architecture (see Table 1)
3.3-V in-system programmability (ISP) through the built-in
IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with
advanced pin-locking capability
Features...
■
■
Built-in boundary-scan test (BST) circuitry compliant with
IEEE Std. 1149.1-1990
Enhanced ISP features
Preliminary
Information
–
–
–
Enhanced ISP algorithm for faster programming (excluding
EPM7128A and EPM7256A devices)
ISP_Done bit to ensure complete programming (excluding
EPM7128A and EPM7256A devices)
Pull-up resistor on I/O pins during in-system programming
■
■
■
Pin-compatible with the popular 5.0-V MAX 7000S devices
High-density PLDs ranging from 600 to 10,000 usable gates
4.5-ns pin-to-pin logic delays with counter frequencies of up to
192.3 MHz
For information on in-system programmable 5.0-V MAX 7000 or 2.5-V
MAX 7000B devices, see the MAX 7000 Programmable Logic Device Family
Data Sheet or the MAX 7000B Programmable Logic Device Family Advance
Information Brief.
f
Table 1. MAX 7000A Device Features
Feature
EPM7032AE
EPM7064AE
EPM7128AE
EPM7128A
EPM7256AE
EPM7256A
EPM7512AE
Usable gates
Macrocells
600
32
2
1,250
64
2,500
128
8
5,000
256
16
10,000
512
Logic array blocks
4
32
Maximum user I/O
pins
36
68
100
164
212
t
t
t
t
f
(ns)
(ns)
4.5
3.0
4.5
3.0
5.0
3.2
6.0
3.7
7.5
4.9
PD
SU
(ns)
2.5
2.5
2.5
2.5
3.0
FSU
CO1
CNT
(ns)
2.8
2.8
3.0
3.3
4.5
(MHz)
192.3
192.3
181.8
156.3
119.0
Altera Corporation
595
A-DS-M7000A-02.01
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
■
■
MultiVoltTM I/O interface enabling device core to run at 3.3 V, while
I/O pins are compatible with 5.0-V, 3.3-V, and 2.5-V logic levels
Pin counts ranging from 44 to 256 in a variety of thin quad flat pack
(TQFP), plastic quad flat pack (PQFP), ball-grid array (BGA), space-
saving FineLine BGATM, and plastic J-lead chip carrier (PLCC)
packages
...and More
Features
■
■
Supports hot-socketing in MAX 7000AE devices
Programmable interconnect array (PIA) continuous routing structure
for fast, predictable performance
■
■
■
■
Peripheral component interconnect (PCI) compatible
Bus friendly architecture including programmable slew-rate control
Open-drain output option
Programmable macrocell registers with individual clear, preset,
clock, and clock enable controls
■
■
■
Programmable power-up states for macrocell registers in
MAX 7000AE devices
Programmable power-saving mode for 50% or greater power
reduction in each macrocell
Configurable expander product-term distribution, allowing up to
32 product terms per macrocell
■
■
■
■
■
Programmable security bit for protection of proprietary designs
6 to 10 pin- or logic-driven output enable signals
Two global clock signals with optional inversion
Enhanced interconnect resources for improved routability
Fast input setup times provided by a dedicated path from I/O pin to
macrocell registers
■
■
■
Programmable output slew-rate control
Programmable ground pins
Software design support and automatic place-and-route provided by
Altera’s MAX+PLUS® II development system for Windows-based
PCs and Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC
System/6000 workstations, and the QuartusTM development system
for Windows-based PCs and Sun SPARCstation and HP 9000
Series 700 workstations
■
■
Additional design entry and simulation support provided by EDIF
2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),
Verilog HDL, VHDL, and other interfaces to popular EDA tools from
manufacturers such as Cadence, Exemplar Logic, Mentor Graphics,
OrCAD, Synopsys, Synplicity, and VeriBest
Programming support with Altera’s Master Programming Unit
(MPU), BitBlasterTM serial download cable, and ByteBlasterMVTM
parallel port download cable, as well as programming hardware
from third-party manufacturers and any JamTM File (.jam),
Jam Byte-Code File (.jbc), or Serial Vector Format File- (.svf) capable
in-circuit tester
596
Altera Corporation
Preliminary Information
MAX 7000A Programmable Logic Device Family Data Sheet
MAX 7000A (including MAX 7000AE) devices are high-density, high-
performance devices based on Altera’s second-generation MAX
architecture. Fabricated with advanced CMOS technology, the EEPROM-
based MAX 7000A devices operate with a 3.3-V supply voltage and
provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns,
and counter speeds of up to 192.3 MHz. MAX 7000A devices in the -5, -6,
-7, and -10 speed grades are compatible with the timing requirements of
the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification,
Revision 2.2. See Table 2.
General
Description
Table 2. MAX 7000A Speed Grades
Device
Notes (1), (2)
Speed Grade
-4
-5
-6
-7
-10
-12
EPM7032AE
EPM7064AE
v
v
v
v
v
v
v
v
EPM7128A
v
v
v
v
v
v
v
EPM7128AE
EPM7256A
v
v
v
v
EPM7256AE
EPM7512AE
Notes:
(1) Contact Altera Applications for up-to-date information on available device speed
grades.
(2) Timing parameters for these speed grades are preliminary.
Altera Corporation
597
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
The MAX 7000A architecture supports 100% TTL emulation and high-
density integration of SSI, MSI, and LSI logic functions. It easily integrates
multiple devices ranging from PALs, GALs, and 22V10s to MACH, and
pLSI devices. MAX 7000A devices are available in a wide range of
packages, including PLCC, BGA, FineLine BGA, PQFP, and TQFP
packages. See Table 3.
Table 3. MAX 7000A Maximum User I/O Pins
Notes (1), (2)
Device
44-Pin
PLCC
44-Pin
TQFP
84-Pin 100-Pin 100-Pin 144-Pin 208-Pin 256-Pin 256-Pin
PLCC
TQFP FineLine TQFP
PQFP
BGA
FineLine
BGA (3)
BGA (3)
EPM7032AE
EPM7064AE
EPM7128A
EPM7128AE
EPM7256A
EPM7256AE
EPM7512AE
36
36
36
36
68
84
84
84
84
68
84
84
68
100
100
164
164
212
68
68
100
100
120
120
120
164
164
176
84
212
Notes:
(1) Contact Altera for up-to-date information on available device package options.
(2) When the IEEE Std. 1149.1 (JTAG) interface is used for in-system programming or boundary-scan testing, four I/O
pins become JTAG pins.
(3) All FineLine BGA packages are footprint-compatible via the SameFrame feature. Therefore, designers can design a
board to support a variety of devices, providing a flexible migration path across densities and pin counts. Device
migration is fully supported by Altera development tools. See “SameFrame Pin-Outs” on page 608 for more details.
MAX 7000A devices use CMOS EEPROM cells to implement logic
functions. The user-configurable MAX 7000A architecture accommodates
a variety of independent combinatorial and sequential logic functions.
The devices can be reprogrammed for quick and efficient iterations
during design development and debug cycles, and can be programmed
and erased up to 100 times.
MAX 7000A devices contain from 32 to 512 macrocells that are combined
into groups of 16 macrocells, called logic array blocks (LABs). Each
macrocell has a programmable-AND/fixed-ORarray and a configurable
register with independently programmable clock, clock enable, clear, and
preset functions. To build complex logic functions, each macrocell can be
supplemented with both shareable expander product terms and high-
speed parallel expander product terms to provide up to 32 product terms
per macrocell.
598
Altera Corporation
Preliminary Information
MAX 7000A Programmable Logic Device Family Data Sheet
MAX 7000A devices provide programmable speed/power optimization.
Speed-critical portions of a design can run at high speed/full power,
while the remaining portions run at reduced speed/low power. This
speed/power optimization feature enables the designer to configure one
or more macrocells to operate at 50% or lower power while adding only a
nominal timing delay. MAX 7000A devices also provide an option that
reduces the slew rate of the output buffers, minimizing noise transients
when non-speed-critical signals are switching. The output drivers of all
MAX 7000A devices can be set for 2.5 V or 3.3 V and all input pins are
2.5-V, 3.3-V, and 5.0-V tolerant, allowing MAX 7000A devices to be used
in mixed-voltage systems.
MAX 7000A devices are supported by the Quartus and MAX+PLUS II
development systems, which are integrated packages that offer
schematic, text—including VHDL, Verilog HDL, and the Altera
Hardware Description Language (AHDL)—and waveform design entry,
compilation and logic synthesis, simulation and timing analysis, and
device programming. The Quartus and MAX+PLUS II software provides
EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other interfaces for
additional design entry and simulation support from other industry-
standard PC- and UNIX-workstation-based EDA tools. The
MAX+PLUS II software runs on Windows-based PCs, as well as Sun
SPARCstation, HP 9000 Series 700/800, and IBM RISC System/6000
workstations. The Quartus software runs on Windows-based PCs, as well
as Sun SPARCstation and HP 9000 Series 700 workstations.
For more information on development tools, see the MAX+PLUS II
Programmable Logic Development System & Software Data Sheet and the
Quartus Programmable Logic Development System Data Sheet.
f
The MAX 7000A architecture includes the following elements:
Functional
Description
■
■
■
■
■
Logic array blocks (LABs)
Macrocells
Expander product terms (shareable and parallel)
Programmable interconnect array
I/O control blocks
The MAX 7000A architecture includes four dedicated inputs that can be
used as general-purpose inputs or as high-speed, global control signals
(clock, clear, and two output enable signals) for each macrocell and I/O
pin. Figure 1 shows the architecture of MAX 7000A devices.
Altera Corporation
599
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
Figure 1. MAX 7000A Device Block Diagram
INPUT/GCLK1
INPUT/OE2/GCLK2
INPUT/OE1
INPUT/GCLRn
6 or 10 Output Enables (1)
6 or 10 Output Enables (1)
LAB A
LAB B
3 to 16
3 to 16
3 to 16
3 to 16
36
36
Macrocells
1 to 16
Macrocells
17 to 32
I/O
I/O
3 to 16 I/O
Control
Block
Control
Block
3 to 16 I/O
16
16
6
3 to 16
3 to 16
6
LAB C
LAB D
3 to 16
3 to 16
PIA
3 to 16
3 to 16
36
36
Macrocells
33 to 48
Macrocells
49 to 64
I/O
Control
Block
I/O
Control
Block
3 to 16 I/O
3 to 16 I/O
16
16
6
6
3 to 16
3 to 16
Note:
(1) EPM7032AE, EPM7064AE, EPM7128A, EPM7128AE, EPM7256A, and EPM7256AE devices have six output enables.
EPM7512AE devices have 10 output enables.
Logic Array Blocks
The MAX 7000A device architecture is based on the linking of
high-performance LABs. LABs consist of 16-macrocell arrays, as shown in
Figure 1. Multiple LABs are linked together via the PIA, a global bus that
is fed by all dedicated input pins, I/O pins, and macrocells.
Each LAB is fed by the following signals:
■
■
■
36 signals from the PIA that are used for general logic inputs
Global controls that are used for secondary register functions
Direct input paths from I/O pins to the registers that are used for fast
setup times
600
Altera Corporation
Preliminary Information
MAX 7000A Programmable Logic Device Family Data Sheet
Macrocells
The MAX 7000A macrocell can be individually configured for either
sequential or combinatorial logic operation. The macrocell consists of
three functional blocks: the logic array, the product-term select matrix,
and the programmable register. Figure 2 shows the MAX 7000A
macrocell.
Figure 2. MAX 7000A Macrocell
Global Global
LAB Local Array
Clear
Clocks
From
2
I/O pin
Parallel Logic
Expanders
(from other
macrocells)
Fast Input
Select
Programmable
Register
Register
Bypass
To I/O
Control
Block
PRN
Q
D
Clock/
Enable
Select
Product-
Term
Select
Matrix
ENA
CLRN
VCC
Clear
Select
To PIA
Shared Logic
Expanders
36 Signals
from PIA
16 Expander
Product Terms
Combinatorial logic is implemented in the logic array, which provides
five product terms per macrocell. The product-term select matrix allocates
these product terms for use as either primary logic inputs (to the ORand
XORgates) to implement combinatorial functions, or as secondary inputs
to the macrocell’s register preset, clock, and clock enable control
functions.
Two kinds of expander product terms (“expanders”) are available to
supplement macrocell logic resources:
■
■
Shareable expanders, which are inverted product terms that are fed
back into the logic array
Parallel expanders, which are product terms borrowed from adjacent
macrocells
Altera Corporation
601
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
The MAX+PLUS II development system automatically optimizes
product-term allocation according to the logic requirements of the design.
For registered functions, each macrocell flipflop can be individually
programmed to implement D, T, JK, or SR operation with programmable
clock control. The flipflop can be bypassed for combinatorial operation.
During design entry, the designer specifies the desired flipflop type; the
MAX+PLUS II software then selects the most efficient flipflop operation
for each registered function to optimize resource utilization.
Each programmable register can be clocked in three different modes:
■
■
Global clock signal. This mode achieves the fastest clock-to-output
performance.
Global clock signal enabled by an active-high clock enable. A clock
enable is generated by a product term. This mode provides an enable
on each flipflop while still achieving the fast clock-to-output
performance of the global clock.
■
Array clock implemented with a product term. In this mode, the
flipflop can be clocked by signals from buried macrocells or I/O pins.
Two global clock signals are available in MAX 7000A devices. As shown
in Figure 1, these global clock signals can be the true or the complement
of either of the global clock pins, GCLK1or GCLK2.
Each register also supports asynchronous preset and clear functions. As
shown in Figure 2, the product-term select matrix allocates product terms
to control these operations. Although the product-term-driven preset and
clear from the register are active high, active-low control can be obtained
by inverting the signal within the logic array. In addition, each register
clear function can be individually driven by the active-low dedicated
global clear pin (GCLRn). Upon power-up, each register in a MAX 7000AE
device may be set to either a high or low state. This power-up state is
specified at design entry.
All MAX 7000A I/O pins have a fast input path to a macrocell register.
This dedicated path allows a signal to bypass the PIA and combinatorial
logic and be clocked to an input D flipflop with an extremely fast (as low
as 2.5 ns) input setup time.
602
Altera Corporation
Preliminary Information
MAX 7000A Programmable Logic Device Family Data Sheet
Expander Product Terms
Although most logic functions can be implemented with the five product
terms available in each macrocell, more complex logic functions require
additional product terms. Another macrocell can be used to supply the
required logic resources. However, the MAX 7000A architecture also
offers both shareable and parallel expander product terms (“expanders”)
that provide additional product terms directly to any macrocell in the
same LAB. These expanders help ensure that logic is synthesized with the
fewest possible logic resources to obtain the fastest possible speed.
Shareable Expanders
Each LAB has 16 shareable expanders that can be viewed as a pool of
uncommitted single product terms (one from each macrocell) with
inverted outputs that feed back into the logic array. Each shareable
expander can be used and shared by any or all macrocells in the LAB to
build complex logic functions. A small delay (t
) is incurred when
SEXP
shareable expanders are used. Figure 3 shows how shareable expanders
can feed multiple macrocells.
Figure 3. MAX 7000A Shareable Expanders
Shareable expanders can be shared by any or all macrocells in an LAB.
Macrocell
Product-Term
Logic
Product-Term Select Matrix
Macrocell
Product-Term
Logic
36 Signals
from PIA
16 Shared
Expanders
Altera Corporation
603
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
Parallel Expanders
Parallel expanders are unused product terms that can be allocated to a
neighboring macrocell to implement fast, complex logic functions.
Parallel expanders allow up to 20 product terms to directly feed the
macrocell ORlogic, with five product terms provided by the macrocell and
15 parallel expanders provided by neighboring macrocells in the LAB.
The MAX+PLUS II Compiler can allocate up to three sets of up to
five parallel expanders automatically to the macrocells that require
additional product terms. Each set of five parallel expanders incurs a
small, incremental timing delay (t
). For example, if a macrocell
PEXP
requires 14 product terms, the Compiler uses the five dedicated product
terms within the macrocell and allocates two sets of parallel expanders;
the first set includes five product terms and the second set includes
four product terms, increasing the total delay by 2 × t
.
PEXP
Two groups of eight macrocells within each LAB (e.g., macrocells 1
through 8 and 9 through 16) form two chains to lend or borrow parallel
expanders. A macrocell borrows parallel expanders from lower-
numbered macrocells. For example, macrocell 8 can borrow parallel
expanders from macrocell 7, from macrocells 7 and 6, or from macrocells
7, 6, and 5. Within each group of eight, the lowest-numbered macrocell
can only lend parallel expanders and the highest-numbered macrocell can
only borrow them. Figure 4 shows how parallel expanders can be
borrowed from a neighboring macrocell.
604
Altera Corporation
Preliminary Information
MAX 7000A Programmable Logic Device Family Data Sheet
Figure 4. MAX 7000A Parallel Expanders
Unused product terms in a macrocell can be allocated to a neighboring macrocell.
From
Previous
Macrocell
Preset
Product-
Term
Select
Matrix
Macrocell
Product-
Term Logic
Clock
Clear
Preset
Product-
Term
Select
Matrix
Macrocell
Product-
Term Logic
Clock
Clear
To Next
Macrocell
36 Signals 16 Shared
from PIA
Expanders
Programmable Interconnect Array
Logic is routed between LABs on the PIA. This global bus is a
programmable path that connects any signal source to any destination on
the device. All MAX 7000A dedicated inputs, I/O pins, and macrocell
outputs feed the PIA, which makes the signals available throughout the
entire device. Only the signals required by each LAB are actually routed
from the PIA into the LAB. Figure 5 shows how the PIA signals are routed
into the LAB. An EEPROM cell controls one input to a 2-input ANDgate,
which selects a PIA signal to drive into the LAB.
Altera Corporation
605
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
Figure 5. MAX 7000A PIA Routing
To LAB
PIA Signals
While the routing delays of channel-based routing schemes in masked or
field-programmable gate arrays (FPGAs) are cumulative, variable, and
path-dependent, the MAX 7000A PIA has a predictable delay. The PIA
makes a design’s timing performance easy to predict.
I/O Control Blocks
The I/O control block allows each I/O pin to be individually configured
for input, output, or bidirectional operation. All I/O pins have a tri-state
buffer that is individually controlled by one of the global output enable
signals or directly connected to ground or V . Figure 6 shows the I/O
CC
control block for MAX 7000A devices. The I/O control block has 6 or
10 global output enable signals that are driven by the true or complement
of two output enable signals, a subset of the I/O pins, or a subset of the
I/O macrocells.
606
Altera Corporation
Preliminary Information
MAX 7000A Programmable Logic Device Family Data Sheet
Figure 6. I/O Control Block of MAX 7000A Devices
6 or 10 Global
Output Enable Signals
(1)
PIA
OE Select Multiplexer
VCC
To Other I/O Pins
GND
From
Macrocell
Open-Drain Output
Slew-Rate Control
Fast Input to
Macrocell
Register
To PIA
Note:
(1) EPM7032AE, EPM7064AE, EPM7128A, EPM7128AE, EPM7256A, and EPM7256AE devices have six output enable
signals. EPM7512AE devices have 10 output enable signals.
When the tri-state buffer control is connected to ground, the output is
tri-stated (high impedance) and the I/O pin can be used as a dedicated
input. When the tri-state buffer control is connected to V , the output is
CC
enabled.
The MAX 7000A architecture provides dual I/O feedback, in which
macrocell and pin feedbacks are independent. When an I/O pin is
configured as an input, the associated macrocell can be used for buried
logic.
Altera Corporation
607
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
MAX 7000A devices support the SameFrame pin-out feature for
FineLine BGA packages. The SameFrame pin-out feature is the
SameFrame
Pin-Outs
arrangement of balls on FineLine BGA packages such that the lower-ball-
count packages form a subset of the higher-ball-count packages.
SameFrame pin-outs provide the flexibility to migrate not only from
device to device within the same package, but also from one package to
another. A given printed circuit board (PCB) layout can support multiple
device density/package combinations. For example, a single board layout
can support a range of devices from an EPM7128A device in a 256-pin
FineLine BGA package to an EPM7512AE device in a 256-pin
FineLine BGA package.
The Quartus and MAX+PLUS II software provides support to design
PCBs with SameFrame pin-out devices. Devices can be defined for present
and future use. The Quartus and MAX+PLUS II software generates
pin-outs describing how to lay out a board to take advantage of this
migration (see Figure 7).
Figure 7. SameFrame Pin-Out Example
Printed Circuit Board
Designed for 256-PinFineLine BGA Package
100-Pin
FineLine
BGA
256-Pin
FineLine
BGA
100-Pin FineLine BGA Package
(Reduced I/O Count or
256-Pin FineLine BGA Package
(Increased I/O Count or
Logic Requirements)
Logic Requirements)
608
Altera Corporation
Preliminary Information
MAX 7000A Programmable Logic Device Family Data Sheet
MAX 7000A devices can be programmed in-system via an industry-
standard 4-pin IEEE Std. 1149.1-1990 (JTAG) interface. ISP offers quick,
efficient iterations during design development and debugging cycles. The
MAX 7000A architecture internally generates the high programming
voltages required to program EEPROM cells, allowing in-system
programming with only a single 3.3-V power supply. During in-system
programming, the I/O pins are tri-stated and weakly pulled-up to
eliminate board conflicts. The pull-up value is nominally 50 kΩ.
In-System
Programma-
bility (ISP)
MAX 7000AE devices have an enhanced ISP algorithm for faster
programming. These devices also offer an ISP_Done bit that provides safe
operation when in-system programming is interrupted. This ISP_Done
bit, which is the last bit programmed, prevents all I/O pins from driving
until the bit is programmed. This feature is available in EPM7032AE,
EPM7064AE, EPM7128AE, EPM7256AE, and EPM7512AE devices only.
ISP simplifies the manufacturing flow by allowing devices to be mounted
on a printed circuit board (PCB) with standard pick-and-place equipment
before they are programmed. MAX 7000A devices can be programmed by
downloading the information via in-circuit testers, embedded processors,
the Altera BitBlaster serial download cable, and the ByteBlasterMV
parallel port download cable. Programming the devices after they are
placed on the board eliminates lead damage on high-pin-count packages
(e.g., QFP packages) due to device handling. MAX 7000A devices can be
reprogrammed after a system has already shipped to the field. For
example, product upgrades can be performed in the field via software or
modem.
In-system programming can be accomplished with either an adaptive or
constant algorithm. An adaptive algorithm reads information from the
unit and adapts subsequent programming steps to achieve the fastest
possible programming time for that unit. Because some in-circuit testers
cannot support an adaptive algorithm, Altera offers devices tested with a
constant algorithm. Devices tested to the constant algorithm contain an
“F” suffix in the ordering code and are marked with an “F” on the bottom
right-hand corner of the device.
The Jam programming and test language can be used to program
MAX 7000A devices with in-circuit testers, PCs, or embedded processors.
For more information on using the Jam language, see Application Note 88
(Using the Jam Language for ISP & ICR via an Embedded Processor).
f
Altera Corporation
609
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
MAX 7000A devices can be programmed on Windows-based PCs with an
Altera Logic Programmer card, the MPU, and the appropriate device
adapter. The MPU performs continuity checking to ensure adequate
electrical contact between the adapter and the device. For more
information, see the Altera Programming Hardware Data Sheet.
Programming
with External
Hardware
The MAX+PLUS II software can use text- or waveform-format test vectors
created with the MAX+PLUS II Text Editor or Waveform Editor to test the
programmed device. For added design verification, designers can
perform functional testing to compare the functional device behavior with
the results of simulation.
Data I/O, BP Microsystems, and other programming hardware
manufacturers provide programming support for Altera devices. For
more information, see Programming Hardware Manufacturers.
MAX 7000A devices include the JTAG BST circuitry defined by IEEE Std.
1149.1-1990. Table 4 describes the JTAG instructions supported by
MAX 7000A devices. The pin-out tables starting on page 634 of this data
sheet show the location of the JTAG control pins for each device. If the
JTAG interface is not required, the JTAG pins are available as user I/O
pins.
IEEE Std.
1149.1 (JTAG)
Boundary-Scan
Support
Table 4. MAX 7000A JTAG Instructions
JTAG Instruction
Description
SAMPLE/PRELOAD Allows a snapshot of signals at the device pins to be captured and examined during
normal device operation, and permits an initial data pattern output at the device pins.
EXTEST
Allows the external circuitry and board-level interconnections to be tested by forcing a
test pattern at the output pins and capturing test results at the input pins.
BYPASS
Places the 1-bit bypass register between the TDIand TDOpins, which allows the BST
data to pass synchronously through a selected device to adjacent devices during normal
device operation.
IDCODE
Selects the IDCODE register and places it between the TDIand TDOpins, allowing the
IDCODE to be serially shifted out of TDO.
USERCODE
Selects the 32-bit USERCODE register and places it between the TDIand TDOpins,
allowing the USERCODE value to be shifted out of TDO. USERCODE instructions are
available for MAX 7000AE devices only.
UESCODE
These instructions select the user electronic signature (UESCODE) and allow the
UESCODE to be shifted out of TDO. UESCODE instructions are available for EPM7128A
and EPM7256A devices only.
ISP Instructions
These instructions are used when programming MAX 7000A devices via the JTAG ports
with the BitBlaster, ByteBlaster, or ByteBlasterMV download cable, or using a Jam File
(.jam), Jam Byte-Code File (.jbc), or Serial Vector Format File (.svf) via an embedded
processor or test equipment.
610
Altera Corporation
Preliminary Information
MAX 7000A Programmable Logic Device Family Data Sheet
The instruction register length of MAX 7000A devices is 10 bits. The UES
register length in MAX 7000A devices is 16 bits. The MAX 7000AE
USERCODE register length is 32 bits. Tables 5 and 6 show the boundary-
scan register length and device IDCODE information for MAX 7000A
devices.
Table 5. MAX 7000A Boundary-Scan Register Length
Device
Boundary-Scan Register Length
EPM7032AE
EPM7064AE
EPM7128A
EPM7128AE
EPM7256A
EPM7256AE
EPM7512AE
96
192
288
288
480
480
624
Table 6. 32-Bit MAX 7000A Device IDCODE Note (1)
Device
IDCODE (32 bits)
Version
(4 Bits)
Part Number (16 Bits) Manufacturer’s 1 (1 Bit)
Identity (11 Bits)
(2)
EPM7032AE
EPM7064AE
EPM7128A
EPM7128AE
EPM7256A
EPM7256AE
EPM7512AE
0001
0001
0000
0001
0000
0001
0001
0111 0000 0011 0010 00001101110
0111 0000 0110 0100 00001101110
0111 0001 0010 1000 00001101110
0111 0001 0010 1000 00001101110
0111 0010 0101 0110 00001101110
0111 0010 0101 0110 00001101110
0111 0101 0001 0010 00001101110
1
1
1
1
1
1
1
Notes to tables:
(1) The most significant bit (MSB) is on the left.
(2) The least significant bit (LSB) for all JTAG IDCODEs is 1.
See Application Note 39 (IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera
Devices) for more information on JTAG BST.
f
Altera Corporation
611
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
Figure 8 shows the timing information for the JTAG signals.
Figure 8. MAX 7000A JTAG Waveforms
TMS
TDI
tJCP
tJCH
t JCL
tJPH
tJPSU
TCK
TDO
tJPXZ
tJPZX
tJPCO
tJSSU
tJSH
Signal
to Be
Captured
tJSCO
tJSZX
tJSXZ
Signal
to Be
Driven
Table 7 shows the JTAG timing parameters and values for MAX 7000A
devices.
Table 7. JTAG Timing Parameters & Values for MAX 7000A Devices
Symbol
Parameter
Min Max Unit
t
t
t
t
t
t
t
t
t
t
t
t
t
TCKclock period
TCKclock high time
TCKclock low time
100
50
50
20
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
JCP
JCH
JCL
JTAG port setup time
JPSU
JPH
JTAG port hold time
JTAG port clock to output
25
25
25
JPCO
JPZX
JPXZ
JSSU
JSH
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Capture register setup time
20
45
Capture register hold time
Update register clock to output
Update register high impedance to valid output
Update register valid output to high impedance
25
25
25
JSCO
JSZX
JSXZ
612
Altera Corporation
Preliminary Information
MAX 7000A Programmable Logic Device Family Data Sheet
MAX 7000A devices offer a power-saving mode that supports low-power
operation across user-defined signal paths or the entire device. This
feature allows total power dissipation to be reduced by 50% or more,
because most logic applications require only a small fraction of all gates to
operate at maximum frequency.
Programmable
Speed/Power
Control
The designer can program each individual macrocell in a MAX 7000A
device for either high-speed or low-power operation. As a result, speed-
critical paths in the design can run at high speed, while the remaining
paths can operate at reduced power. Macrocells that run at low power
incur a nominal timing delay adder (t
) for the t
, t
, t , t
, t
,
LPA
LAD LAC IC ACL EN
and t
parameters.
SEXP
MAX 7000A device outputs can be programmed to meet a variety of
system-level requirements.
Output
Configuration
MultiVolt I/O Interface
The MAX 7000A device architecture supports the MultiVolt I/O interface
feature, which allows MAX 7000A devices to connect to systems with
differing supply voltages. MAX 7000A devices in all packages can be set
for 2.5-V, 3.3-V, or 5.0-V I/O pin operation. These devices have one set of
V
pins for internal operation and input buffers (VCCINT), and another
CC
set for I/O output drivers (VCCIO).
The VCCIOpins can be connected to either a 3.3-V or 2.5-V power supply,
depending on the output requirements. When the VCCIOpins are
connected to a 2.5-V power supply, the output levels are compatible with
2.5-V systems. When the VCCIOpins are connected to a 3.3-V power
supply, the output high is at 3.3 V and is therefore compatible with 3.3-V
or 5.0-V systems. Devices operating with V
levels lower than 3.0 V
CCIO
incur a nominally greater timing delay of t
instead of t
. Inputs can
OD2
OD1
always be driven by 2.5-V, 3.3-V, or 5.0-V signals.
Table 8 describes the MAX 7000A MultiVolt I/O support.
Table 8. MAX 7000A MultiVolt I/O Support
V
Voltage
Input Signal (V)
3.3
Output Signal (V)
CCIO
2.5
5.0
2.5
3.3
5.0
2.5
3.3
v
v
v
v
v
v
v
v
v
Altera Corporation
613
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
Open-Drain Output Option
MAX 7000A devices provide an optional open-drain (equivalent to
open-collector) output for each I/O pin. This open-drain output enables
the device to provide system-level control signals (e.g., interrupt and
write enable signals) that can be asserted by any of several devices. It can
also provide an additional wired-ORplane.
Open-drain output pins on MAX 7000A devices (with a pull-up resistor to
the 5.0-V supply) can drive 5.0-V CMOS input pins that require a V of
IH
3.5 V. When the open-drain pin is active, it will drive low. When the pin
is inactive, the trace will be pulled up to 5.0 V by the resistor. The open-
drain pin will only drive low or tri-state; it will never drive high. The rise
time is dependent on the value of the pull-up resistor and load
impedance. The I current specification should be considered when
OL
selecting a pull-up resistor.
Programmable Ground Pins
Each unused I/O pin on MAX 7000A devices may be used as an
additional ground pin. In EPM7128A and EPM7256A devices, utilizing
unused I/O pins as additional ground pins requires using the associated
macrocell. In MAX 7000AE devices, this programmable ground feature
does not require the use of the associated macrocell; therefore, the buried
macrocell is still available for user logic.
Slew-Rate Control
The output buffer for each MAX 7000A I/O pin has an adjustable output
slew rate that can be configured for low-noise or high-speed performance.
A faster slew rate provides high-speed transitions for high-performance
systems. However, these fast transitions may introduce noise transients
into the system. A slow slew rate reduces system noise, but adds a
nominal delay of 4 to 5 ns. When the configuration cell is turned off, the
slew rate is set for low-noise performance. Each I/O pin has an individual
EEPROM bit that controls the slew rate, allowing designers to specify the
slew rate on a pin-by-pin basis. The slew rate control affects both the
rising and falling edges of the output signal.
614
Altera Corporation
Preliminary Information
MAX 7000A Programmable Logic Device Family Data Sheet
Because MAX 7000A family devices can be used in a mixed-voltage
environment, they have been designed specifically to tolerate any possible
Power
Sequencing &
Hot-Socketing
power-up sequence. The V
in any order.
and V
power planes can be powered
CCIO
CCINT
Signals can be driven into MAX 7000A devices before and during power
up without damaging the device. Additionally, MAX 7000A devices do
not drive out during power up. Once operating conditions are reached,
MAX 7000A devices operate as specified by the user.
All MAX 7000A devices contain a programmable security bit that controls
access to the data programmed into the device. When this bit is
programmed, a design implemented in the device cannot be copied or
retrieved. This feature provides a high level of design security, because
programmed data within EEPROM cells is invisible. The security bit that
controls this function, as well as all other programmed data, is reset only
when the device is reprogrammed.
Design Security
Generic Testing
MAX 7000A devices are fully functionally tested. Complete testing of
each programmable EEPROM bit and all internal logic elements ensures
100% programming yield. AC test measurements are taken under
conditions equivalent to those shown in Figure 9. Test patterns can be
used and then erased during early stages of the production flow.
Figure 9. MAX 7000A AC Test Conditions
Power supply transients can affect AC
measurements. Simultaneous transitions
VCC
of multiple outputs should be avoided for
accurate measurement. Threshold tests
must not be performed under AC
conditions. Large-amplitude, fast-ground-
current transients normally occur as the
device outputs discharge the load
703 Ω
[521 Ω]
Device
Output
To Test
System
capacitances. When these transients flow
through the parasitic inductance between
the device ground pin and the test system
ground, significant reductions in
observable noise immunity can result.
Numbers in brackets are for 2.5-V
outputs. Numbers without brackets are for
3.3-V devices or outputs.
8,060 Ω
[481 Ω]
C1 (includes JIG
capacitance)
Device input
rise and fall
times < 2 ns
Altera Corporation
615
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
Tables 9 through 12 provide information on absolute maximum ratings,
recommended operating conditions, operating conditions, and
capacitance for MAX 7000A devices.
Operating
Conditions
Table 9. MAX 7000A Device Absolute Maximum Ratings
Note (1)
Symbol Parameter Conditions
Min
Max
Unit
V
V
Supply voltage
With respect to ground (2)
–0.5
–2.0
–25
–65
–65
4.6
5.75
25
V
CC
DC input voltage
V
I
I
DC output current, per pin
Storage temperature
Ambient temperature
Junction temperature
mA
° C
° C
° C
OUT
T
T
T
No bias
150
135
135
STG
A
Under bias
FineLine BGA, PQFP, and TQFP
packages, under bias
J
Table 10. MAX 7000A Device Recommended Operating Conditions
Symbol
Parameter
Conditions
Min
Max
Unit
V
Supply voltage for internal logic (3)
and input buffers
3.0
3.6
V
CCINT
V
Supply voltage for output
drivers, 3.3-V operation
(3)
3.0
2.3
3.0
3.6
2.7
V
V
V
CCIO
Supply voltage for output
drivers, 2.5-V operation
(3)
V
Supply voltage during in-
system programming
3.6
CCISP
V
V
Input voltage
(2), (4)
–0.5
0
5.75
V
I
Output voltage
V
V
O
A
CCIO
T
Ambient temperature
For commercial use
For industrial use
For commercial use
For industrial use
0
70
° C
° C
° C
° C
ns
–40
0
85
90
T
Junction temperature
J
–40
105
40
t
t
Input rise time
Input fall time
R
40
ns
F
616
Altera Corporation
Preliminary Information
MAX 7000A Programmable Logic Device Family Data Sheet
Table 11. MAX 7000A Device DC Operating Conditions
Note (5)
Symbol
Parameter
Conditions
Min
Max
Unit
V
V
V
High-level input voltage
Low-level input voltage
1.7
–0.5
2.4
5.75
0.8
V
V
V
IH
(2)
IL
3.3-V high-level TTL output
voltage
I
= –8 mA DC, V
= 3.00 V (6)
OH
OH
CCIO
3.3-V high-level CMOS output
voltage
I
= –0.1 mA DC, V
= 3.00 V
= 2.30 V
V
– 0.2
CCIO
V
V
OH
CCIO
(6)
2.5-V high-level output voltage I = –100 µA DC, V
2.1
OH
CCIO
(6)
I
I
I
= –1 mA DC, V
= –2 mA DC, V
= 2.30 V (6)
= 2.30 V (6)
2.0
1.7
V
V
V
OH
OH
OL
CCIO
CCIO
V
3.3-V low-level TTL output
voltage
= 8 mA DC, V
= 3.00 V (7)
0.45
0.2
OL
CCIO
3.3-V low-level CMOS output
voltage
I
= 0.1 mA DC, V
= 100 µA DC, V
= 3.00 V (7)
= 2.30 V (7)
V
OL
CCIO
2.5-V low-level output voltage
Input leakage current
I
I
I
0.2
0.4
0.7
10
V
V
OL
OL
OL
CCIO
= 1 mA DC, V
= 2 mA DC, V
= 2.30 V (7)
= 2.30 V (7)
CCIO
V
CCIO
I
I
V = V or ground
CCINT
–10
–10
µA
µA
I
I
Tri-state output off-state
current
V
= V or ground
CCINT
10
OZ
O
R
Value of I/O pin pull-up resistor
during programming in-system
or during power-up
V
V
V
= 3.0 to 3.6 V (8)
= 2.3 to 2.7 V (8)
= 2.3 to 3.6 V (9)
20
30
20
50
80
74
kΩ
kΩ
kΩ
ISP
CCIO
CCIO
CCIO
Table 12. MAX 7000A Device Capacitance
Note (10)
Symbol
Parameter
Conditions
Min
Max
Unit
C
C
Input pin capacitance
I/O pin capacitance
V
V
= 0 V, f = 1.0 MHz
8
8
pF
pF
IN
IN
= 0 V, f = 1.0 MHz
I/O
OUT
Altera Corporation
617
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
Notes to tables:
(1) See the Operating Requirements for Altera Devices Data Sheet.
(2) Minimum DC input voltage is –0.5 V. During transitions, the inputs may undershoot to –2.0 V for input currents
less than 100 mA and periods shorter than 20 ns.
(3)
(4) In MAX 7000AE devices, all pins, including dedicated inputs, I/O pins, and JTAG pins, may be driven before
CCINT and VCCIO are powered.
VCC must rise monotonically.
V
(5) These values are specified in Table 10 on page 616.
(6) The parameter is measured with 50% of the outputs each sourcing the specified current. The IOH parameter refers
to high-level TTL or CMOS output current.
(7) The parameter is measured with 50% of the outputs each sinking the specified current. The IOL parameter refers to
low-level TTL or CMOS output current.
(8) For EPM7128A and EPM7256A devices, this pull-up exists while a device is programmed in-system.
(9) For MAX 7000AE devices, this pull-up exists while devices are programmed in-system and in unprogrammed
devices during power-up.
(10) Capacitance is measured at 25° C and is sample-tested only. The OE1pin (high-voltage pin during programming)
has a maximum capacitance of 20 pF.
Figure 10 shows the typical output drive characteristics of MAX 7000A
devices.
Figure 10. Output Drive Characteristics of MAX 7000A Devices
3.3 V
2.5 V
60
50
40
30
20
10
60
50
40
30
20
10
IOL
IOL
Typical IO
Output
Current (mA)
Typical IO
Output
Current (mA)
VCCINT = 3.3 V
VCCIO = 3.3 V
VCCINT = 3.3 V
VCCIO = 2.5 V
Room Temperature
Room Temperature
IOH
IOH
1
2
3
4
1
2
3
4
VO Output Voltage (V)
VO Output Voltage (V)
MAX 7000A device timing can be analyzed with the Quartus and
MAX+PLUS II software, with a variety of popular industry-standard
Timing Model
EDA simulators and timing analyzers, or with the timing model shown in
Figure 11. MAX 7000A devices have predictable internal delays that
enable the designer to determine the worst-case timing of any design. The
MAX+PLUS II software provides timing simulation, point-to-point delay
prediction, and detailed timing analysis for device-wide performance
evaluation.
618
Altera Corporation
Preliminary Information
MAX 7000A Programmable Logic Device Family Data Sheet
Figure 11. MAX 7000A Timing Model
Internal Output
Enable Delay
tIOE
Global Control
Delay
Input
Delay
t I N
Output
Delay
tGLOB
Register
Delay
tSU
Parallel
Expander Delay
tPEXP
Logic Array
Delay
t LAD
tOD1
tOD2
tOD3
tXZ
tZX1
tZX2
tZX3
PIA
Delay
tPIA
tH
tPRE
tCLR
tRD
tCOMB
tFSU
tFH
Register
Control Delay
tLAC
tIC
tEN
I/O
Delay
tIO
Shared
Expander Delay
tSEXP
Fast
Input Delay
tFIN
The timing characteristics of any signal path can be derived from the
timing model and parameters of a particular device. External timing
parameters, which represent pin-to-pin timing delays, can be calculated
as the sum of internal parameters. Figure 12 shows the timing relationship
between internal and external delay parameters.
See Application Note 94 (Understanding MAX 7000 Timing) for more
information.
f
Altera Corporation
619
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
Figure 12. MAX 7000A Switching Waveforms
t & t < 2 ns. Inputs are
Combinatorial Mode
R
F
driven at 3 V for a logic
high and 0 V for a logic
low. All timing
characteristics are
measured at 1.5 V.
tIN
Input Pin
I/O Pin
tIO
tPIA
PIA Delay
tSEXP
Shared Expander
Delay
tLAC , tLAD
Logic Array
Input
tPEXP
Parallel Expander
Delay
tCOMB
Logic Array
Output
tOD
Output Pin
Global Clock Mode
tR
tCH
tCL
tF
Global
Clock Pin
tIN
tGLOB
Global Clock
at Register
tSU
tH
Data or Enable
(Logic Array Output)
Array Clock Mode
tR
tACH
tACL
tF
Input or I/O Pin
Clock into PIA
tIN
tIO
tPIA
Clock into
Logic Array
tIC
tSU
Clock at
Register
tH
Data from
Logic Array
tRD
tPIA
tPIA
tCLR , tPRE
Register to PIA
to Logic Array
tOD
tOD
Register Output
to Pin
620
Altera Corporation
Preliminary Information
MAX 7000A Programmable Logic Device Family Data Sheet
Tables 13 through 20 show EPM7128A, EPM7256A, and MAX 7000AE
AC operating conditions.
Table 13. EPM7128A External Timing Parameters
Note (1)
Symbol
Parameter
Conditions
Speed Grade
-7 -10
Min Max Min Max Min Max Min Max
Unit
-6
-12
t
Input to non-registered
output
C1 = 35 pF
(2)
6.0
7.5
10.0
12.0 ns
PD1
t
I/O input to non-
registered output
C1 = 35 pF
(2)
6.0
7.5
10.0
12.0 ns
PD2
t
t
t
Global clock setup time (2)
4.2
0.0
2.5
5.3
0.0
3.0
7.0
0.0
3.0
8.5
0.0
3.0
ns
ns
ns
SU
Global clock hold time
(2)
H
Global clock setup time
of fast input
FSU
t
t
Global clock hold time of
fast input
0.0
0.0
1.0
0.0
1.0
0.0
1.0
ns
FH
Global clock to output
delay
C1 = 35 pF 1.0
3.7
6.0
4.6
7.5
6.1
7.3
ns
CO1
t
t
t
t
t
Global clock high time
Global clock low time
Array clock setup time
Array clock hold time
3.0
3.0
3.0
3.0
2.4
2.2
1.0
4.0
4.0
3.1
3.3
5.0
5.0
3.8
4.3
ns
ns
ns
ns
CH
CL
(2)
(2)
1.9
1.5
ASU
AH
Array clock to output
delay
C1 = 35 pF 1.0
(2)
1.0 10.0 1.0 12.0 ns
ACO1
t
t
t
Array clock high time
Array clock low time
3.0
3.0
3.0
4.0
4.0
5.0
5.0
ns
ns
ACH
ACL
CNT
3.0
Minimum global clock
period
(2)
6.9
6.9
8.6
8.6
11.5
11.5
13.8 ns
f
t
f
f
Maximum internal global (2), (3)
clock frequency
144.9
116.3
87.0
72.5
MHz
13.8 ns
MHz
CNT
Minimum array clock
period
(2)
ACNT
ACNT
MAX
Maximum internal array (2), (3)
clock frequency
144.9
166.7
116.3
166.7
87
72.5
Maximum clock
frequency
(4)
125.0
100.0
MHz
Altera Corporation
621
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
Table 14. EPM7128A Internal Timing Parameters (Part 1 of 2)
Symbol
Parameter
Conditions
Speed Grade
-7 -10
Unit
-12
-6
Min Max Min Max Min Max Min Max
t
Input pad and buffer delay
0.6
0.6
0.7
0.7
0.9
0.9
1.1
1.1
ns
ns
IN
IO
t
I/O input pad and buffer
delay
t
t
t
t
t
t
Fast input delay
2.7
2.5
0.7
2.4
2.4
0.0
3.1
3.2
0.8
3.0
3.0
0.0
3.6
4.3
1.1
4.1
4.1
0.0
3.9
5.1
1.3
4.9
4.9
0.0
ns
ns
ns
ns
ns
ns
FIN
Shared expander delay
Parallel expander delay
Logic array delay
SEXP
PEXP
LAD
LAC
IOE
Logic control array delay
Internal output enable
delay
t
t
t
t
t
t
t
Output buffer and pad
C1 = 35 pF
C1 = 35 pF
0.4
0.9
5.4
4.0
4.5
9.0
4.0
0.6
1.1
5.6
4.0
4.5
9.0
4.0
0.7
1.2
5.7
5.0
5.5
10.0
5.0
0.9
1.4
5.9
5.0
5.5
ns
ns
ns
ns
ns
OD1
OD2
OD3
ZX1
ZX2
ZX3
XZ
delay, slow slew rate = off
V
= 3.3 V
CCIO
Output buffer and pad
delay, slow slew rate = off (5)
= 2.5 V
V
CCIO
Output buffer and pad
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
delay, slow slew rate = on
V
= 2.5 V or 3.3 V
CCIO
Output buffer enable
delay, slow slew rate = off
V
= 3.3 V
CCIO
Output buffer enable
delay, slow slew rate = off (5)
= 2.5 V
V
CCIO
Output buffer enable
C1 = 35 pF
10.0 ns
delay, slow slew rate = on
V
= 3.3 V
CCIO
Output buffer disable
delay
C1 = 5 pF
5.0
ns
t
t
t
Register setup time
Register hold time
1.9
1.5
0.8
2.4
2.2
1.1
3.1
3.3
1.1
3.8
4.3
1.1
ns
ns
ns
SU
H
Register setup time of fast
input
FSU
t
Register hold time of fast
input
1.7
1.9
1.9
1.9
ns
FH
622
Altera Corporation
Preliminary Information
MAX 7000A Programmable Logic Device Family Data Sheet
Table 14. EPM7128A Internal Timing Parameters (Part 2 of 2)
Symbol
Parameter
Conditions
Speed Grade
-7 -10
Min Max Min Max Min Max Min Max
Unit
-6
-12
t
Register delay
1.7
1.7
2.4
2.4
1.0
3.1
3.1
0.9
11.0
2.1
2.1
3.0
3.0
1.2
3.9
3.9
1.1
10.0
2.8
2.8
4.1
4.1
1.7
5.2
5.2
1.5
10.0
3.3
3.3
4.9
4.9
2.0
6.2
6.2
1.8
ns
ns
ns
ns
ns
ns
ns
ns
RD
t
t
t
t
t
t
t
t
Combinatorial delay
Array clock delay
Register enable time
Global control delay
Register preset time
Register clear time
PIA delay
COMB
IC
EN
GLOB
PRE
CLR
PIA
(2)
(6)
Low-power adder
10.0 ns
LPA
Altera Corporation
623
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
Table 15. EPM7256A External Timing Parameters
Note (1)
Symbol
Parameter
Conditions
Speed Grade
-7 -10
Unit
-12
-6
Min Max Min Max Min Max Min Max
t
Input to non-registered
output
C1 = 35 pF
(2)
6.0
7.5
10.0
12.0 ns
PD1
t
I/O input to non-
registered output
C1 = 35 pF
(2)
6.0
7.5
10.0
12.0 ns
PD2
t
t
t
Global clock setup time (2)
3.7
0.0
2.5
4.6
0.0
3.0
6.2
0.0
3.0
7.4
0.0
3.0
ns
ns
ns
SU
Global clock hold time
(2)
H
Global clock setup time
of fast input
FSU
t
t
Global clock hold time of
fast input
0.0
0.0
1.0
0.0
1.0
0.0
1.0
ns
FH
Global clock to output
delay
C1 = 35 pF 1.0
3.3
6.2
4.2
7.8
5.5
6.6
ns
CO1
t
t
t
t
t
Global clock high time
Global clock low time
Array clock setup time
Array clock hold time
3.0
3.0
3.0
3.0
1.0
2.7
1.0
4.0
4.0
1.4
4.0
4.0
4.0
1.6
5.1
ns
ns
ns
ns
CH
CL
(2)
(2)
0.8
1.9
ASU
AH
Array clock to output
delay
C1 = 35 pF 1.0
(2)
1.0 10.3 1.0 12.4 ns
ACO1
t
t
t
Array clock high time
Array clock low time
3.0
3.0
3.0
4.0
4.0
4.0
4.0
ns
ns
ACH
ACL
CNT
3.0
Minimum global clock
period
(2)
6.4
6.4
8.0
8.0
10.7
10.7
12.8 ns
f
t
f
f
Maximum internal global (2), (3)
clock frequency
156.3
125.0
93.5
78.1
MHz
12.8 ns
MHz
CNT
Minimum array clock
period
(2)
ACNT
ACNT
MAX
Maximum internal array (2), (3)
clock frequency
156.3
166.7
125.0
166.7
93.5
78.1
Maximum clock
frequency
(2), (4)
125.0
125.0
MHz
624
Altera Corporation
Preliminary Information
MAX 7000A Programmable Logic Device Family Data Sheet
Table 16. EPM7256A Internal Timing Parameters (Part 1 of 2)
Symbol
Parameter
Conditions
Speed Grade
-7 -10
Min Max Min Max Min Max Min Max
Unit
-6
-12
t
Input pad and buffer delay
0.3
0.3
0.4
0.4
0.5
0.5
0.6
0.6
ns
ns
IN
IO
t
I/O input pad and buffer
delay
t
t
t
t
t
t
Fast input delay
2.4
2.8
0.5
2.5
2.5
0.2
3.0
3.5
0.6
3.1
3.1
0.3
3.4
4.7
0.8
4.2
4.2
0.4
3.8
5.6
1.0
5.0
5.0
0.5
ns
ns
ns
ns
ns
ns
FIN
Shared expander delay
Parallel expander delay
Logic array delay
SEXP
PEXP
LAD
LAC
IOE
Logic control array delay
Internal output enable
delay
t
t
t
Output buffer and pad
C1 = 35 pF
C1 = 35 pF
0.3
0.8
5.3
0.4
0.9
5.4
0.5
1.0
5.5
0.6
1.1
5.6
ns
ns
ns
OD1
OD2
OD3
delay, slow slew rate = off
V
= 3.3 V
CCIO
Output buffer and pad
delay, slow slew rate = off (5)
= 2.5 V
V
CCIO
Output buffer and pad
delay
C1 = 35 pF
slow slew rate = on
V
= 2.5 V or 3.3 V
CCIO
t
t
t
t
Output buffer enable
delay
C1 = 35 pF
4.0
4.5
9.0
4.0
4.0
4.5
9.0
4.0
5.0
5.5
5.0
5.5
ns
ns
ZX1
ZX2
ZX3
XZ
slow slew rate = off
V
= 3.3 V
CCIO
Output buffer enable
delay
C1 = 35 pF
(5)
slow slew rate = off
V
= 2.5 V
CCIO
Output buffer enable
delay
C1 = 35 pF
C1 = 5 pF
10.0
5.0
10.0 ns
slow slew rate = on
V
= 2.5 V or 3.3 V
CCIO
Output buffer disable
delay
5.0
ns
t
t
Register setup time
Register hold time
1.0
1.7
1.3
2.4
1.7
3.7
2.0
4.7
ns
ns
SU
H
Altera Corporation
625
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
Table 16. EPM7256A Internal Timing Parameters (Part 2 of 2)
Symbol
Parameter
Conditions
Speed Grade
-7 -10
Unit
-12
-6
Min Max Min Max Min Max Min Max
t
Register setup time of fast
input
1.2
1.4
1.4
1.4
ns
ns
FSU
FH
t
Register hold time of fast
input
1.3
1.6
1.6
1.6
t
t
t
t
t
t
t
t
t
Register delay
1.6
1.6
2.7
2.5
1.1
2.3
2.3
1.3
11.0
2.0
2.0
3.4
3.1
1.4
2.9
2.9
1.6
10.0
2.7
2.7
4.5
4.2
1.8
3.8
3.8
2.1
10.0
3.2
3.2
5.4
5.0
2.2
4.6
4.6
2.6
ns
ns
ns
ns
ns
ns
ns
ns
RD
Combinatorial delay
Array clock delay
Register enable time
Global control delay
Register preset time
Register clear time
PIA delay
COMB
IC
EN
GLOB
PRE
CLR
PIA
(2)
(6)
Low-power adder
10.0 ns
LPA
626
Altera Corporation
Preliminary Information
MAX 7000A Programmable Logic Device Family Data Sheet
Table 17. MAX 7000AE External Timing Parameters
Notes (1), (7)
Symbol
Parameter
Conditions
Speed Grade
-5
Unit
-4
-6
Min Max Min Max Min Max
t
Input to non-registered output
C1 = 35 pF (2)
C1 = 35 pF (2)
4.5
4.5
5.0
5.0
6.0
6.0
ns
ns
PD1
t
I/O input to non-registered
output
PD2
t
t
t
Global clock setup time
Global clock hold time
(2)
(2)
3.0
0.0
2.5
3.2
0.0
2.5
3.7
0.0
2.5
ns
ns
ns
SU
H
Global clock setup time of fast
input
FSU
t
Global clock hold time of fast
input
0.0
0.0
0.0
ns
FH
t
t
t
t
t
t
t
t
t
f
Global clock to output delay
Global clock high time
Global clock low time
C1 = 35 pF
1.0
2.0
2.0
1.4
0.8
2.8
4.4
1.0
2.0
2.0
1.0
0.8
3.0
5.2
1.0
3.0
3.0
0.8
1.9
1.0
3.0
3.0
3.3
6.2
ns
ns
CO1
CH
ns
CL
Array clock setup time
Array clock hold time
(2)
ns
ASU
AH
(2)
ns
Array clock to output delay
Array clock high time
C1 = 35 pF (2)
ns
ACO1
ACH
ACL
CNT
CNT
2.0
2.0
2.0
2.0
ns
Array clock low time
ns
Minimum global clock period
(2)
5.2
5.2
5.5
5.5
6.4
6.4
ns
Maximum internal global clock (2), (3)
frequency
192.3
181.8
156.3
MHz
t
f
Minimum array clock period
(2)
ns
ACNT
Maximum internal array clock
frequency
(2), (3)
192.3
250.0
181.8
250.0
156.3
166.7
MHz
ACNT
f
Maximum clock frequency
(4)
MHz
MAX
Table 18. MAX 7000AE Internal Timing Parameters (Part 1 of 2)
Notes (1), (7)
Symbol
Parameter
Conditions
Speed Grade
-5
Min Max Min Max Min Max
Unit
-4
-6
t
t
t
t
Input pad and buffer delay
I/O input pad and buffer delay
Fast input delay
0.3
0.3
2.6
1.9
0.3
0.3
2.6
2.4
0.3
0.3
2.4
2.8
ns
ns
ns
ns
IN
IO
FIN
SEXP
Shared expander delay
Altera Corporation
627
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
Table 18. MAX 7000AE Internal Timing Parameters (Part 2 of 2)
Notes (1), (7)
Symbol
Parameter
Conditions
Speed Grade
Unit
-4
-5
-6
Min Max Min Max Min Max
t
Parallel expander delay
Logic array delay
0.5
1.9
1.8
0.0
0.3
0.6
2.5
2.3
0.0
0.4
0.5
2.5
2.5
0.2
0.3
ns
ns
ns
ns
ns
PEXP
LAD
LAC
IOE
t
t
t
t
Logic control array delay
Internal output enable delay
Output buffer and pad delay
slow slew rate = off
C1 = 35 pF
C1 = 35 pF (5)
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF (5)
C1 = 35 pF
C1 = 5 pF
OD1
V
= 3.3 V
CCIO
t
t
t
t
t
Output buffer and pad delay
slow slew rate = off
0.8
5.3
4.0
4.5
9.0
4.0
0.9
5.4
4.0
4.5
9.0
4.0
0.8
5.3
4.0
4.5
9.0
4.0
ns
ns
ns
ns
ns
OD2
OD3
ZX1
ZX2
ZX3
V
= 2.5 V
CCIO
Output buffer and pad delay
slow slew rate = on
V
= 2.5 V or 3.3 V
CCIO
Output buffer enable delay
slow slew rate = off
V
= 3.3 V
CCIO
Output buffer enable delay
slow slew rate = off
V
= 2.5 V
CCIO
Output buffer enable delay
slow slew rate = on
V
= 2.5 V or 3.3 V
CCIO
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Output buffer disable delay
Register setup time
Register hold time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
XZ
1.4
0.8
0.9
1.6
0.8
1.0
0.8
1.7
1.0
1.7
1.2
1.3
SU
H
Register setup time of fast input
Register hold time of fast input
Register delay
FSU
FH
1.2
1.3
1.9
1.8
1.0
2.3
2.3
0.7
12.0
1.4
1.0
2.3
2.3
0.9
2.6
2.6
0.8
12.0
1.6
1.6
2.7
2.5
1.1
2.3
2.3
1.3
11.0
RD
Combinatorial delay
Array clock delay
COMB
IC
Register enable time
Global control delay
Register preset time
Register clear time
PIA delay
EN
GLOB
PRE
CLR
PIA
LPA
(2)
(6)
Low-power adder
628
Altera Corporation
Preliminary Information
MAX 7000A Programmable Logic Device Family Data Sheet
Table 19. MAX 7000AE External Timing Parameters
Notes (1), (7)
Speed Grade
-10
Symbol
Parameter
Conditions
Unit
-7
-12
Min Max Min Max Min Max
t
Input to non-registered output
C1 = 35 pF (2)
C1 = 35 pF (2)
7.5
7.5
10.0
10.0
12.0
12.0
ns
ns
PD1
t
I/O input to non-registered
output
PD2
t
t
t
Global clock setup time
Global clock hold time
(2)
(2)
4.9
0.0
3.0
6.6
0.0
3.0
7.8
0.0
3.0
ns
ns
ns
SU
H
Global clock setup time of fast
input
FSU
t
Global clock hold time of fast
input
0.0
0.0
0.0
ns
FH
t
t
t
t
t
t
t
t
t
f
Global clock to output delay
Global clock high time
Global clock low time
C1 = 35 pF
1.0
3.0
3.0
1.6
2.1
4.5
7.8
1.0
4.0
4.0
2.1
3.4
5.9
1.0
5.0
5.0
2.4
4.4
7.1
ns
ns
CO1
CH
ns
CL
Array clock setup time
Array clock hold time
(2)
ns
ASU
AH
(2)
ns
Array clock to output delay
Array clock high time
C1 = 35 pF (2)
10.4
12.5
ns
ACO1
ACH
ACL
CNT
CNT
3.0
3.0
4.0
4.0
5.0
5.0
ns
Array clock low time
ns
Minimum global clock period
(2)
8.4
8.4
11.2
11.2
13.3
13.3
ns
Maximum internal global clock (2), (3)
frequency
119.0
89.3
75.2
MHz
t
f
Minimum array clock period
(2)
ns
ACNT
Maximum internal array clock
frequency
(2), (3)
119.0
166.7
89.3
75.2
MHz
ACNT
f
Maximum clock frequency
(4)
125.0
100.0
MHz
MAX
Table 20. MAX 7000AE Internal Timing Parameters (Part 1 of 2)
Notes (1), (7)
Speed Grade
-10
Min Max Min Max Min Max
Symbol
Parameter
Conditions
Unit
-7
-12
t
t
t
t
Input pad and buffer delay
I/O input pad and buffer delay
Fast input delay
0.4
0.4
3.3
3.6
0.6
0.6
3.7
4.9
0.7
0.7
4.1
5.9
ns
ns
ns
ns
IN
IO
FIN
SEXP
Shared expander delay
Altera Corporation
629
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
Table 20. MAX 7000AE Internal Timing Parameters (Part 2 of 2)
Notes (1), (7)
Speed Grade
Symbol
Parameter
Conditions
Unit
-7
-10
-12
Min Max Min Max Min Max
t
Parallel expander delay
Logic array delay
0.8
3.7
3.4
0.0
0.6
1.1
5.0
4.6
0.0
0.7
1.3
6.0
5.6
0.0
0.9
ns
ns
ns
ns
ns
PEXP
LAD
LAC
IOE
t
t
t
t
Logic control array delay
Internal output enable delay
Output buffer and pad delay
slow slew rate = off
C1 = 35 pF
C1 = 35 pF (5)
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF (5)
C1 = 35 pF
C1 = 5 pF
OD1
V
= 3.3 V
CCIO
t
t
t
t
t
Output buffer and pad delay
slow slew rate = off
1.1
5.6
4.0
4.5
9.0
4.0
1.2
5.7
1.4
5.9
ns
ns
ns
ns
ns
OD2
OD3
ZX1
ZX2
ZX3
V
= 2.5 V
CCIO
Output buffer and pad delay
slow slew rate = on
V
= 2.5 V or 3.3 V
CCIO
Output buffer enable delay
slow slew rate = off
5.0
5.0
V
= 3.3 V
CCIO
Output buffer enable delay
slow slew rate = off
5.5
5.5
V
= 2.5 V
CCIO
Output buffer enable delay
slow slew rate = on
10.0
5.0
10.0
5.0
V
= 2.5 V or 3.3 V
CCIO
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Output buffer disable delay
Register setup time
Register hold time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
XZ
1.3
2.4
1.1
1.9
1.7
3.8
1.1
1.9
2.0
4.8
1.1
1.9
SU
H
Register setup time of fast input
Register hold time of fast input
Register delay
FSU
FH
2.1
1.5
3.4
3.4
1.4
3.9
3.9
1.3
10.0
2.8
2.0
4.6
4.6
1.8
5.2
5.2
1.7
10.0
3.3
2.4
5.6
5.6
2.2
6.2
6.2
2.0
10.0
RD
Combinatorial delay
Array clock delay
COMB
IC
Register enable time
Global control delay
Register preset time
Register clear time
PIA delay
EN
GLOB
PRE
CLR
PIA
LPA
(2)
(6)
Low-power adder
630
Altera Corporation
Preliminary Information
MAX 7000A Programmable Logic Device Family Data Sheet
Notes to tables:
(1) These values are specified in Table 10 on page 616.
(2) These values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these
devices, add an additional 0.1 ns to the PIA timing value.
(3) Measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB.
(4) The fMAX values represent the highest frequency for pipelined data.
(5) Operating conditions:
VCCIO = 2.5 ± 0.2 V for commercial and industrial use.
(6) The tLPA parameter must be added to the tLAD, tLAC, tIC, tACL, tEN, and tSEXP parameters for macrocells running in
low-power mode.
(7) MAX 7000AE timing values are preliminary.
Supply power (P) versus frequency (f
devices is calculated with the following equation:
, in MHz) for MAX 7000A
MAX
Power
Consumption
P = P + P = I × V + P
INT
IO
CCINT
CC
IO
The P value, which depends on the device output load characteristics
IO
and switching frequency, can be calculated using the guidelines given in
Application Note 74 (Evaluating Power for Altera Devices).
The I
logic. The I
value depends on the switching frequency and the application
CCINT
value is calculated with the following equation:
CCINT
I
=
CCINT
(A × MC
) + [B × (MC
– MC
)] + (C × MC
× f
× tog
)
TON
DEV
TON
USED
MAX
LC
The parameters in this equation are:
MC
=
Number of macrocells with the Turbo BitTM option turned
on, as reported in the MAX+PLUS II Report File (.rpt)
Number of macrocells in the device
Total number of macrocells in the design, as reported in
the Report File
TON
MC
MC
=
=
DEV
USED
f
tog
=
=
Highest clock frequency to the device
Average percentage of logic cells toggling at each clock
(typically 12.5%)
MAX
LC
A, B, C
=
Constants, shown in Table 21
Altera Corporation
631
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
Table 21. MAX 7000A I Equation Constants
CC
Device
A
B
C
EPM7032AE (1)
EPM7064AE (1)
EPM7128A (1)
EPM7128AE (1)
EPM7256A (1)
EPM7256AE (1)
EPM7512AE (1)
0.46
0.46
0.46
0.46
0.46
0.46
0.46
0.28
0.28
0.28
0.28
0.28
0.28
0.28
0.032
0.032
0.032
0.032
0.032
0.032
0.032
Note:
(1) Values for these devices are preliminary.
This calculation provides an I estimate based on typical conditions
CC
using a pattern of a 16-bit, loadable, enabled, up/down counter in each
LAB with no output load. Actual I should be verified during operation
CC
because this measurement is sensitive to the actual pattern in the device
and the environmental operating conditions.
632
Altera Corporation
Preliminary Information
MAX 7000A Programmable Logic Device Family Data Sheet
Figure 13 shows the typical supply current versus frequency for
MAX 7000A devices.
Figure 13. I vs. Frequency for MAX 7000A Devices (Part 1 of 2)
CC
EPM7064AE
EPM7032AE
90
45
40
35
30
VCC = 3.3 V
Room Temperature
VCC = 3.3 V
Room Temperature
192.3 MHz
80
70
60
192.3 MHz
25
20
50
40
High Speed
High Speed
Typical ICC
Active (mA)
Typical ICC
Active (mA)
58.1 MHz
58.1 MHz
15
10
5
30
20
10
Non-Turbo
Non-Turbo
0
50
100
150
0
50
100
150
200
250
200
250
Frequency (MHz)
Frequency (MHz)
EPM7128A & EPM7128AE
180
VCC = 3.3 V
Room Temperature
160
140
120
181.8 MHz
Typical ICC
Active (mA)
100
80
High Speed
56.17 MHz
60
40
20
Low Power
0
50
100
150
200
250
Frequency (MHz)
Altera Corporation
633
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
Figure 13. I vs. Frequency for MAX 7000A Devices (Part 2 of 2)
CC
EPM7512AE
EPM7256A & EPM7256AE
600
VCC = 3.3 V
Room Temperature
350
300
VCC = 3.3 V
Room Temperature
500
400
300
200
100
119 MHz
156.3 MHz
250
200
Typical ICC
Active (mA)
Typical ICC
Active (mA)
High Speed
High Speed
150
100
53.76 MHz
57.14 MHz
Low Power
Low Power
50
0
20
40
60
80
100
120
140
0
50
100
150
200
Frequency (MHz)
Frequency (MHz)
Tables 22 through 32 show the pin names and numbers for the pins in
MAX 7000A and MAX7000AE device packages.
Device
Pin-Outs
Table 22. EPM7032AE Dedicated Pin-Outs
Dedicated Pin
44-Pin PLCC
44-Pin TQFP
INPUT/GCLK1
43
1
37
39
38
40
1
INPUT/GCLRn
INPUT/OE1
INPUT/OE2/GCLK2
TDI(1)
44
2
7
TMS(1)
13
32
38
7
TCK(1)
26
32
TDO(1)
GNDINT
22, 42
10, 30
3, 23
15, 35
–
16, 36
4, 24
17, 41
9, 29
–
GNDIO
VCCINT(3.3 V)
VCCIO(2.5 V or 3.3 V)
No Connect (N.C.)
Total User I/O Pins (2)
36
36
634
Altera Corporation
Preliminary Information
MAX 7000A Programmable Logic Device Family Data Sheet
Table 23. EPM7032AE I/O Pin-Outs
LAB
MC
44-Pin
PLCC
44-Pin
TQFP
LAB
MC
44-Pin
PLCC
44-Pin
TQFP
A
1
4
5
6
42
43
44
B
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
41
40
39
35
34
33
2
3
4
7 (1)
8
1 (1)
2
38 (1)
37
32 (1)
31
5
6
9
3
36
30
7
11
12
13 (1)
14
16
17
18
19
20
21
5
34
28
8
6
33
27
9
7 (1)
8
32 (1)
31
26 (1)
25
10
11
12
13
14
15
16
10
11
12
13
14
15
29
23
28
22
27
21
26
20
25
19
24
18
Altera Corporation
635
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
Table 24. EPM7064AE Dedicated Pin-Outs
Dedicated Pin
44-Pin
PLCC
44-Pin
TQFP
100-Pin
TQFP
100-Pin
FineLine BGA
INPUT/GCLK1
43
1
37
39
38
40
1
87
89
88
90
4
A6
B5
B6
A5
A1
F3
F8
A10
INPUT/GCLRn
INPUT/OE1
INPUT/OE2/GCLK2
TDI(1)
44
2
7
TMS(1)
13
32
38
22, 42
7
15
62
73
TCK(1)
26
32
16, 36
TDO(1)
GNDINT
38, 86
C3, D6, D7, E5, F6,
G4, G5, H8
GNDIO
10, 30
4, 24
11, 26, 43, 59, 74,
95
–
VCCINT(3.3 V Only)
VCCIO(2.5 V or 3.3 V)
3, 23
17, 41
9, 29
39, 91
D5, G6
15, 35
3, 18, 34, 51, 66, 82 C8, D4, E6, F5, G7,
H3
No Connect (N.C.)
–
–
1, 2, 5, 7, 22, 24,
B1, B10, C1, C9,
27, 28, 49, 50, 53, C10, D8, E3, E4,
55, 70, 72, 77, 78
68
H1, H9, H10, J1,
J2, J10, K1, K9
Total User I/O Pins (2)
36
36
68
636
Altera Corporation
Preliminary Information
MAX 7000A Programmable Logic Device Family Data Sheet
Table 25. EPM7064AE I/O Pin-Outs (44-Pin PLCC & 44-Pin TQFP Packages)
LAB
MC
44-Pin
PLCC
44-Pin
TQFP
LAB
MC
44-Pin
PLCC
44-Pin
TQFP
A
1
12
–
6
–
5
3
2
–
–
C
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
48
59
60
61
62
63
64
24
–
18
–
2
3
11
9
25
26
27
–
19
20
21
–
4
5
8
6
–
7
–
–
–
8
7 (1)
–
1 (1)
–
28
29
–
22
23
–
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
–
–
6
44
–
–
–
–
–
–
–
–
–
–
5
43
–
31
–
25
–
–
4
42
15
–
32 (1)
33
–
26 (1)
27
–
B
21
–
D
20
19
18
–
14
13
12
–
34
36
37
–
28
30
31
–
–
–
–
–
17
16
–
11
10
–
38 (1)
39
–
32 (1)
33
–
–
–
–
–
–
–
–
–
–
–
–
–
14
–
8
40
–
34
–
–
13 (1)
7 (1)
41
35
Altera Corporation
637
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
Table 26. EPM7064AE I/O Pin-Outs (100-Pin TQFP & 100-Pin FineLine BGA Packages)
LAB
MC
100-Pin
TQFP
100-Pin
FineLine
BGA
LAB
MC
100-Pin
TQFP
100-Pin
FineLine
BGA
A
1
14
F4
C
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
48
59
60
61
62
63
64
40
K6
2
13
12
10
9
E2
E1
D2
D1
D3
C2
A1 (1)
B2
A2
A3
B3
A4
B4
C4
C5
K5
J5
41
42
44
45
46
47
48
52
54
56
57
58
60
61
62 (1)
63
64
65
67
68
69
71
73 (1)
75
76
79
80
81
83
84
85
J6
3
H6
4
K7
5
J7
6
8
H7
7
6
J8
8
4 (1)
100
99
98
97
96
94
93
92
37
36
35
33
32
31
30
29
25
23
21
20
19
17
16
15 (1)
K8
9
K10
J9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
G9
G10
G8
F9
F10
F8 (1)
F7
B
D
E9
H5
K4
J4
E10
E8
E7
H4
J3
D9
D10
A10 (1)
B9
K3
K2
H2
G2
G1
G3
F2
A9
A8
B8
A7
B7
F1
C7
F3 (1)
C6
Notes to tables:
(1) This pin may function as either a JTAG port or a user I/O pin. If the device is configured to use the JTAG ports for
in-system programming, this pin is not available as a user I/O pin.
(2) The user I/O pin count includes dedicated input pins and all I/O pins.
638
Altera Corporation
Preliminary Information
MAX 7000A Programmable Logic Device Family Data Sheet
Table 27. EPM7128A & EPM7128AE Dedicated Pin-Outs
Dedicated Pin
84-Pin 100-Pin 100-Pin 144-Pin
256-Pin
FineLine BGA
PLCC
TQFP
FineLine
BGA
TQFP
INPUT/GCLK1
INPUT/GCLRn
INPUT/OE1
83
87
A6
125
D9
E8
1
89
B5
127
126
128
4
84
88
B6
E9
INPUT/OE2/GCLK2 2
90
A5
D8
D4
J6
TDI(1)
TMS(1)
TCK(1)
TDO(1)
GNDINT
14
4
A1
23
15
F3
20
62
62
F8
89
J11
D13
71
73
A10
D6, G5
104
42, 82
38, 86
52, 57,
A8, C9, G9, K8, P9
124, 129
GNDIO
7, 19, 32, 11, 26,
47, 59, 72 43, 59,
74, 95
C3, D7,
E5, F6,
G4, H8
3, 13, 17, A3, B10, C2, D14, F6, G10, H8, J9, K7,
33, 59, 64, L11, M3, P6, P10, R2, R3, T1, T15
85, 105,
135
VCCINT
3, 43
39, 91
D5, G6
51, 58,
B9, C8, G8, K9, P8
(3.3 V only)
123, 130
VCCIO
(2.5 V or 3.3 V)
13, 26,
38, 53,
66, 78
3, 18, 34, C8, D4,
51, 66, 82 E6, F5,
G7, H3
24, 50, 73, B3, B5, C14, E15, F11, G3, G7, G15, H9,
76, 95,
J8, K10, L3, L6, M15, P14, T2, T3
115, 144
No Connect (N.C.)
–
–
–
1, 2, 12,
A1, A2, A4, A5, A6, A7, A9, A10, A11, A12,
19, 34, 35, A13, A14, A15, A16, B1, B2, B4, B6, B7,
36, 43, 46, B8, B11, B12, B13, B14, B 15, B16, C1,
47, 48, 49, C3, C4, C6, C11, C13, C15, C16, D1, D2,
66, 75, 90, D3, D15, D16, E1, E2, E3, E14, E16, F1,
103, 108, F2, F15, F16, G1, G2, G14, G16, H1, H2,
120, 121, H15, H16, J1, J2, J15, J16, K1, K2, K3,
122
K14, K15, K16, L1, L2, L15, L16, M1, M14,
M16, N1, N2, N3, N14, N15, N16, P1, P2,
P3, P4, P12, P13, P15, P16, R1, R4, R5,
R6, R7, R8, R9, R11, R12, R13, R14, R15,
R16, T4, T5, T6, T7, T8, T9, T10, T11, T12,
T13, T14, T16
Total User I/O Pins 68
(2)
84
84
100
100
Altera Corporation
639
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
Table 28. EPM7128A & EPM7128AE I/O Pin-Outs (Part 1 of 2)
LAB MC 84-Pin 100-
100-Pin 144-Pin 256-Pin LAB MC 84-Pin 100- 100-Pin
FineLine TQFP FineLine PLCC Pin FineLine
BGA BGA TQFP BGA
144-
Pin
TQFP
256-Pin
FineLine
BGA
PLCC
Pin
TQFP
A
1
–
2
C1 F4 25 K1
143
C
33
–
32
N4
–
2
–
–
–
–
–
34
–
–
–
–
3
12
–
1
B1
–
142
141
140
139
–
E4
C5
E5
D5
–
35 31
36
24
–
J1
–
31
30
29
28
–
M4
M2
L4
L5
–
4
–
–
5
11
10
–
100
99
–
B2
A2
–
37 30
38 29
23
22
–
H1
H2
–
6
7
39
–
8
9
98
97
–
A3
B3
–
138
137
–
D6
E6
–
40 28
21
20
–
G2
G1
–
27
26
–
K5
K4
–
9
–
41
42
–
–
10
11
12
13
14
15
16
–
8
96
–
A4
–
136
134
133
132
–
D7
C7
E7
F7
–
43 27
44
19
–
G3
–
25
23
22
21
–
K6
J3
J5
J4
–
–
–
6
94
93
–
B4
C4
–
45 25
46 24
17
16
–
F2
F1
–
5
–
47
–
4
92
14
–
C5
F4
–
131
18
–
F8
J7
–
48 23 (1) 15 (1) F3 (1)
20 (1) J6 (1)
B
17 22
18
19 21
20
21 20
D
49 41
50
51 40
52
53 39
37
–
K5
–
56
–
N8
–
–
–
13
–
E2
–
16
15
14
11
–
H5
H3
H4
H6
–
36
–
J5
–
55
54
53
45
–
M8
P7
L8
N7
–
–
–
12
10
–
E1
E3
–
35
33
–
H5
K4
–
22
23
–
–
54
55
–
–
24 18
25 17
9
E4
D2
–
10
9
H7
G5
–
56 37
57 36
32
31
–
J4
H4
–
44
42
–
M7
L7
–
8
26
27 16
28
29 15
–
–
–
58
59 35
60
61 34
–
7
D1
–
8
G4
F3
G6
F5
–
30
–
J3
–
41
40
39
38
–
M6
P5
N6
M5
–
–
–
7
–
6
D3
C2
–
6
29
28
–
K3
J2
–
30
31
–
–
5
5
62
63
–
–
–
–
32 14 (1) 4 (1)
A1 (1)
4 (1)
D4 (1)
64 33
27
K2
37
N5
640
Altera Corporation
Preliminary Information
MAX 7000A Programmable Logic Device Family Data Sheet
Table 28. EPM7128A & EPM7128AE I/O Pin-Outs (Part 2 of 2)
LAB MC 84-Pin 100-
100-Pin 144-Pin 256-Pin LAB MC 84-Pin 100- 100-Pin
FineLine TQFP FineLine PLCC Pin FineLine
BGA BGA TQFP BGA
144-
Pin
TQFP
256-Pin
FineLine
BGA
PLCC
Pin
TQFP
E
65 44
66
67 45
68
69 46
40
K6 N9 63 F7
60
G
97 63
98
99 64
100
101 65
91
J10
–
–
–
–
–
–
–
–
–
–
41
–
J6
–
61
62
63
65
–
M9
R10
L9
64
–
E9
–
92
93
94
96
–
H12
H14
H13
H11
–
–
–
42
44
–
H6
K7
–
65
67
–
E10
E8
–
70
71
–
–
N10
–
102
103
–
–
72 48
73 49
45
46
–
J7
H7
–
67
68
–
M10
L10
–
104 67
105 68
68
69
–
E7
D9
–
97
98
–
H10
G12
–
74
75 50
76
77 51
–
106
107 69
108
109 70
–
47
–
J8
–
69
70
71
72
–
M11
P11
N11
N12
–
70
–
D10
–
99
100
101
102
–
G13
F14
G11
F12
–
–
–
48
49
–
K8
K9
–
71
72
–
D8
C9
–
78
79
–
–
110
111
–
–
80 52
50
52
–
K10
J10
–
74
77
–
N13
M13
–
112 71 (1) 73 (1) A10 (1) 104 (1) D13 (1)
F
81
82
–
–
H
113
114
–
–
75
–
C10
–
106
–
F13
–
83 54
84
53
–
H10
–
78
79
80
81
–
L13
L14
L12
M12
–
115 73
116
76
–
B10
–
107
109
110
111
–
E13
C12
E12
D12
–
–
–
85 55
86 56
54
55
–
H9
J9
–
117 74
118 75
77
78
–
B9
A9
–
87
–
119
–
88 57
56
57
–
G9
G10
–
82
83
–
K12
K13
–
120 76
79
80
–
A8
B8
–
112
113
–
D11
E11
–
89
90
–
–
121
122
–
–
91 58
92
58
–
G8
–
84
86
87
88
–
K11
J14
J12
J13
–
123 77
124
81
–
A7
–
114
116
117
118
–
D10
C10
E10
F10
–
–
–
93 60
94 61
60
61
–
F9
F10
–
125 79
126 80
83
84
–
B7
C7
–
95
–
127
–
96 62 (1) 62 (1) F8 (1)
89 (1) J11 (1)
128 81
85
C6
119
F9
Notes to tables:
(1) This pin can function as either a JTAG port or a user I/O pin. If the device is configured to use the JTAG ports for
BST or in-system programming, this pin is not available as a user I/O pin.
(2) The user I/O pin count includes dedicated input pins and all I/O pins.
Altera Corporation
641
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
Table 29. EPM7256A & EPM7256AE Dedicated Pin-Outs
Dedicated Pin
100-Pin TQFP 144-Pin TQFP
208-Pin PQFP
256-Pin
FineLine BGA
INPUT/GCLK1
87
125
127
126
128
4
184
D9
E8
INPUT/GCLRn
INPUT/OE1
INPUT/OE2/GCLK2
TDI(1)
89
182
183
181
176
127
30
88
E9
90
D8
D4
J6
4
TMS(1)
15
20
TCK(1)
62
89
J11
D13
TDO(1)
73
104
189
GNDINT
38, 86
52, 57, 124, 129 75, 82, 180, 185 A8, C9, G9, K8, P9
GNDIO(2)
11, 26, 43, 59, 3, 13, 17, 33,
14, 32, 50, 72,
59, 64, 85, 105, 94, 116, 134,
135 152, 174, 200
A3, B10, C2, D14, F6, G10, H8,
J9, K7, L11, M3, P6, P10, R2,
R3, T1, T15
74, 95
39, 91
VCCINT(3.3 V Only)
51, 58, 123, 130 74, 83, 179, 186 B9, C8, G8, K9, P8
VCCIO(2.5 V or 3.3 V) 3, 18, 34, 51,
24, 50, 73, 76, 5, 23, 41, 63, 85, B3, B5, C14, E15, F11, G3, G7,
(2)
66, 82
–
95, 115, 144
–
107, 125, 143,
165, 191
G15, H9, J8, K10, L3, L6, M15,
P14, T2, T3
No Connect (N.C.)
1, 2, 51, 52, 53, A1, A2, A6, A12, A13, A14, A15,
54, 103, 104,
105, 106, 155,
156, 157, 158,
207, 208
A16, B1, B2, B15, B16, C1, C15,
C16, D1, D3, D15, D16, G1,
G16, H15, H16, J1, K1, L1, L2,
M1, M16, N1, N2, N14, N15,
N16, P1, P2, P15, P16, R1, R14,
R15, R16, T7, T8, T10, T11, T14,
T16
Total User I/O Pins (3) 84
120
164
164
642
Altera Corporation
Preliminary Information
MAX 7000A Programmable Logic Device Family Data Sheet
Table 30. EPM7256A & EPM7256AE I/O Pin-Outs (Part 1 of 4)
LAB MC 100-Pin 144-Pin 208-Pin 256-Pin LAB MC 100-Pin 144-Pin 208-Pin 256-Pin
TQFP
TQFP
PQFP FineLine
BGA
TQFP
TQFP
PQFP FineLine
BGA
A
1
–
–
–
–
–
–
–
2
1
–
–
–
2
–
1
153
C3
–
C
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
–
–
–
–
–
–
–
36
108
N4
–
2
–
–
–
3
154
–
C4
–
35
–
109
–
P3
–
4
5
159
160
–
E5
D5
–
34
–
110
111
–
N3
M4
–
6
143
–
7
–
8
–
161
162
–
C5
B4
–
25
24
–
32
31
–
112
113
–
M2
L4
–
9
–
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
–
100
–
142
–
163
–
A4
–
23
–
30
–
114
–
L5
–
–
141
140
–
164
166
–
A5
D6
–
22
–
29
–
115
117
–
K6
K5
–
99
–
–
–
98
–
139
–
167
141
–
C6
F5
–
21
31
–
28
44
–
118
92
–
K4
N6
–
B
D
–
–
–
10
–
142
–
F2
–
30
–
43
–
93
–
T5
–
–
–
9
144
145
–
E1
F4
–
29
28
–
42
41
–
95
96
–
M6
R5
–
–
–
–
–
8
8
146
147
–
F3
E2
–
–
40
–
97
98
–
M5
P5
–
7
7
–
–
–
–
–
6
6
148
–
D2
–
–
39
–
99
–
N5
–
–
–
–
5
5
149
150
–
E3
E4
–
–
38
–
100
101
–
T4
R4
–
–
–
–
–
–
–
–
4 (1)
4 (1)
151
D4 (1)
27
37
102
P4
Altera Corporation
643
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
Table 30. EPM7256A & EPM7256AE I/O Pin-Outs (Part 2 of 4)
LAB MC 100-Pin 144-Pin 208-Pin 256-Pin LAB MC 100-Pin 144-Pin 208-Pin 256-Pin
TQFP
TQFP
PQFP FineLine
BGA
TQFP
TQFP
PQFP FineLine
BGA
E
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
–
–
–
–
–
–
–
–
–
–
–
168
B6
–
G
97
–
–
–
–
–
–
–
–
–
119
K3
–
–
98
–
169
–
E6
–
99
27
–
120
–
K2
–
100
101
102
103
138
–
170
171
–
F7
E7
–
26
–
121
122
–
J7
H7
–
–
–
97
96
–
137
136
–
172
173
–
D7
C7
–
104 20
105 19
25
23
–
123
124
–
J5
J2
–
106
107 17
108
109 16
–
94
–
134
–
175
–
B7
–
22
–
126
–
J3
–
–
93
–
133
132
–
176 (1) A7
21
–
127 (1) J4
177
–
F8
–
110
111
–
–
128
–
H6
–
–
–
92
–
131
–
178
130
–
B8
H5
–
112 15 (1)
113 37
20 (1)
–
129
79
–
J6 (1)
M8
–
F
H
–
–
114
–
–
–
19
–
131
–
H1
–
115 36
54
–
80
–
N8
–
–
116
117
–
–
–
18
–
132
133
–
H2
H3
–
53
–
81
84
–
L8
R7
–
–
118 35
–
–
119
120
121
122
123
124
–
–
–
–
–
–
–
14
13
–
16
15
–
135
136
–
H4
G6
–
49
48
–
86
87
–
P7
N7
–
12
–
14
–
137
–
G5
–
47
–
88
–
M7
–
10
–
12
–
138
139
–
G2
G4
–
125 33
46
–
89
90
–
L7
T6
–
126
127
–
–
–
–
–
9
11
140
F1
128 32
45
91
R6
644
Altera Corporation
Preliminary Information
MAX 7000A Programmable Logic Device Family Data Sheet
Table 30. EPM7256A & EPM7256AE I/O Pin-Outs (Part 3 of 4)
LAB MC 100-Pin 144-Pin 208-Pin 256-Pin LAB MC 100-Pin 144-Pin 208-Pin 256-Pin
TQFP
TQFP
PQFP FineLine
BGA
TQFP
TQFP
PQFP FineLine
BGA
I
129 80
130
131 81
114
197
C11
–
K
161
162
–
–
–
–
38
K11
–
–
–
–
–
116
–
196
–
B11
–
163 57
82
–
37
–
K12
–
132
133
134
135
136
137
138
–
–
–
–
–
–
–
164
165
166
167
–
–
–
–
117
–
195
194
–
A11
F10
–
83
–
36
35
–
K14
K13
–
–
–
118
119
–
193
192
–
E10
A10
–
168 58
84
86
–
34
33
–
K15
K16
–
169
170
–
–
139 83
140
141 84
120
–
190
–
C10
–
171 60
172
173 61
87
–
31
–
J13
–
–
–
121
–
189 (1) D10
88
–
30 (1)
29
–
J14
J12
–
142
143
–
–
188
–
F9
–
174
175
–
–
–
–
144 85
145 63
122
–
187
27
–
A9
J15
–
176 62 (1)
89 (1)
–
28
78
–
J11 (1)
R8
–
J
L
177
178
179
180
181
182
183
–
–
–
–
–
–
–
146
147 64
148
149 65
–
–
–
90
–
26
–
J16
–
55
–
77
–
T9
–
–
91
–
25
24
–
J10
H14
–
56
–
76
73
–
R9
N9
–
150
151
152
153
154
–
–
–
–
–
–
–
92
93
–
22
21
–
H13
H12
–
184 40
185 41
60
61
–
71
70
–
M9
L9
186
187 42
188
189 44
–
–
155 67
94
–
20
–
H11
–
62
–
69
–
R10
–
156
157
158
159
–
–
–
–
–
96
–
19
18
–
H10
G11
–
63
–
68
67
–
N10
M10
–
190
191
–
–
–
–
160 68
97
17
G14
192 45
65
66
L10
Altera Corporation
645
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
Table 30. EPM7256A & EPM7256AE I/O Pin-Outs (Part 4 of 4)
LAB MC 100-Pin 144-Pin 208-Pin 256-Pin LAB MC 100-Pin 144-Pin 208-Pin 256-Pin
TQFP
TQFP
PQFP FineLine
BGA
TQFP
TQFP
PQFP FineLine
BGA
M
193
194
–
–
106
4
–
3
–
B14
–
O
225
226
227
228
229
230
231
–
–
–
–
–
–
–
–
–
49
R13
–
–
–
195 75
107
–
C13
–
74
–
48
–
P13
–
196
197
198
199
200
–
–
–
–
–
108
–
206
205
–
B13
F12
–
75
–
47
46
–
N13
M14
–
–
–
109
110
–
204
203
–
E12
D12
–
232 52
233 53
77
78
–
45
44
–
M13
L13
–
201 76
202
203 77
–
234
235 54
236
237 55
–
111
–
202
–
C12
–
79
–
43
–
L14
–
204
205
–
–
–
–
201
199
–
B12
E11
–
80
–
42
40
–
L12
L15
–
206 78
207
208 79
112
–
238
239
–
–
–
–
113
–
198
16
–
D11
G13
–
240 56
241 46
81
66
–
39
65
–
L16
R11
–
N
209
210
–
–
P
–
242
243 47
244
–
211 69
98
–
15
–
G12
–
67
–
64
–
P11
–
212
213
214
215
–
–
–
–
–
99
–
13
12
–
F16
F15
–
245 48
246 49
68
69
–
62
61
–
N11
M11
–
–
247
248
249
250
251
252
253
254
255
–
–
–
–
–
–
–
–
–
216 70
100
101
–
11
10
–
F13
F14
–
–
60
59
–
T12
R12
–
217
218
–
–
70
–
219 71
220
221 72
102
–
9
E16
–
–
58
–
M12
–
–
–
–
103
–
8
E14
E13
–
71
–
57
56
–
P12
N12
–
222
223
–
–
7
–
–
–
224 73 (1)
104 (1)
6
D13 (1)
256 50
72
55
T13
646
Altera Corporation
Preliminary Information
MAX 7000A Programmable Logic Device Family Data Sheet
Notes to tables:
(1) This pin can function as either a JTAG pin or a user I/O pin. If the device is programmed to use the JTAG ports for
BST or in-system programming, this pin is not available as a user I/O pin.
(2) EPM7512AE devices in the 208-pin PQFP package support vertical migration from EPM7256E, EPM7256S, and
EPM7256A devices. EPM7512AE devices contain additional I/O pins which are no connects on the EPM7256E,
EPM7256S, and EPM7256Adevices. To support these additional I/O pins, EPM7512AE devices have two additional
VCCIO(pins 105 and 207) and GNDIO(pins 51 and 158) pins that are no-connect pins on the EPM7256E, EPM7256S,
and EPM7256A devices. To achieve vertical migration between the EPM7256A and EPM7512AE devices, the no-
connect pins 105 and 207 may be tied to VCCIOand pins 51 and 158 may be tied to GNDIOon the EPM7256Adevices.
On the EPM7256E and EPM7256S devices, these no-connect pins must not be tied to VCCIOor GNDIO.
(3) The user I/O pin count includes dedicated input pins and all I/O pins.
Table 31. EPM7512AE Dedicated Pin-Outs
Dedicated Pin
144-Pin
TQFP
208-Pin
PQFP (1)
256-Pin
BGA
256-Pin
FineLine BGA
INPUT/GCLK1
125
127
126
128
4
184
182
183
181
176
127
30
L1
D9
E8
E9
D8
D4
J6
INPUT/GCLRn
INPUT/OE1
INPUT/OE2/GCLK2
TDI(2)
K2
K1
K3
A2
TMS(2)
20
B12
V12
Y2
TCK(2)
89
J11
TDO(2)
104
189
D13
GNDINT
52, 57, 124, 129
75, 82, 180, 185
J20, K4, K18, L2,
L17
A8, C9, G9, K8, P9
GNDIO
3, 13, 17, 33, 59, 64, 14, 32, 50, 51, 72,
A1, B2, B19, B20,
A3, B10, C2, D14,
85, 105, 135
94, 116, 134, 152,
158, 174, 200
C3, C18, D4, D17, F6, G10, H8, J9, K7,
U4, U17, V3, V18, L11, M3, P6, P10,
V19, W2, W19, Y1, R2, R3, T1, T15
Y20
VCCINT
VCCIO
51, 58, 123, 130
74, 83, 179, 186
5, 23, 41, 63, 85,
J1, J19, L4, M19,
M20
B9, C8, G8, K9, P8
24, 50, 73, 76,
95, 115, 144
C4, C17, D3, D5,
B3, B5, C14, E15,
105, 107, 125, 143, D16, D18, E4, E17, F11, G3, G7, G15,
165, 191, 207
T4, T17, U3, U5,
U16, U18, V2, V4,
V17
H9, J8, K10,L3, L6,
M15, P14, T2, T3
No Connect (N.C.)
–
–
–
–
Total User I/O Pins (3) 120
176
212
212
Altera Corporation
647
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
Table 32. EPM7512AE I/O Pin-Outs (Part 1 of 8)
LAB
MC 144-Pin 208-Pin 256-Pin 256-Pin LAB
MC 144-Pin 208-Pin 256-Pin 256-Pin
TQFP
PQFP
(1)
BGA FineLine
BGA
TQFP
PQFP
(1)
BGA FineLine
BGA
A
1
134
173
H3
D7
–
C
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
142
163
F4
E4
–
2
–
–
–
–
–
–
3
–
–
–
–
–
–
–
–
4
–
–
–
–
–
–
–
–
5
–
–
H2
–
C7
–
141
–
164
–
E3
–
C5
–
6
–
–
7
–
–
–
–
–
–
–
–
8
–
–
–
–
–
–
–
–
9
–
175
–
H1
–
B7
–
140
–
166
–
E2
–
A5
–
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
–
133
–
176 (2) J4
A7
–
–
167
–
F3
–
D5
–
–
–
–
–
–
–
–
–
–
–
–
132
–
177
–
J3
–
F8
–
139
–
168
–
E1
–
E5
–
131
–
178
169
–
J2
G4
–
B8
D6
–
–
–
F2
B3
–
E6
B2
–
B
D
2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
138
–
170
–
F1
–
C6
–
1
–
C2
–
A2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
137
–
171
–
G3
–
B6
–
–
159
–
B1
–
B4
–
–
136
–
172
–
G2
–
A6
–
–
160
–
C1
–
A4
–
–
–
–
–
–
–
–
–
–
–
–
G1
–
F7
–
–
161
–
D2
–
C4
–
–
–
–
–
–
H4
E7
143
162
D1
C3
648
Altera Corporation
Preliminary Information
MAX 7000A Programmable Logic Device Family Data Sheet
Table 32. EPM7512AE I/O Pin-Outs (Part 2 of 8)
LAB
MC 144-Pin 208-Pin 256-Pin 256-Pin LAB
MC 144-Pin 208-Pin 256-Pin 256-Pin
TQFP
PQFP
(1)
BGA FineLine
BGA
TQFP
PQFP
(1)
BGA FineLine
BGA
E
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
–
–
7
–
–
–
–
–
–
–
6
–
–
5
–
–
–
B5
E3
–
G
97
–
–
–
–
C9
H6
–
–
98
–
153
–
C5
–
C1
–
99
15
–
141
–
D9
–
G5
–
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
–
D6
–
B1
–
14
–
142
–
A8
–
G4
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
154
–
A4
–
A1
–
–
144
–
B8
–
G2
–
–
155
–
B4
–
D2
–
–
145
–
C8
–
G1
–
–
–
–
–
–
–
–
–
156
–
A3
–
D3
–
12
–
146
–
D8
–
G6
–
4 (2)
–
157
147
–
A2 (2)
B7
–
D4 (2)
F2
–
–
–
A7
A11
–
F5
J1
–
F
H
19
–
135
–
–
–
148
–
C7
–
F3
–
–
136
–
A10
–
H7
–
–
–
11
–
149
–
A6
–
F1
–
18
–
137
–
B10
–
H5
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
D7
–
F4
–
–
–
D10
–
H2
–
–
–
–
–
10
–
150
–
B6
–
E1
–
–
138
–
C10
–
H3
–
–
–
–
–
–
–
–
–
–
9
151
–
A5
–
D1
–
–
139
–
A9
–
H1
–
–
–
8
–
C6
E2
16
140
B9
H4
Altera Corporation
649
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
Table 32. EPM7512AE I/O Pin-Outs (Part 3 of 8)
LAB
MC 144-Pin 208-Pin 256-Pin 256-Pin LAB
MC 144-Pin 208-Pin 256-Pin 256-Pin
TQFP
PQFP
(1)
BGA FineLine
BGA
TQFP
PQFP
(1)
BGA FineLine
BGA
I
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
–
–
–
–
–
–
D12
K1
–
K
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
29
115
B16
N4
–
–
–
–
–
129
–
C12
–
J7
–
–
117
–
C15
–
M2
–
–
20 (2)
–
130
–
B12 (2) J6 (2)
–
118
–
A17
–
M1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
131
–
A12
–
J5
–
28
–
119
–
B15
–
M4
–
–
–
–
D11
–
J4
–
–
–
D14
–
M5
–
–
–
–
–
–
–
–
–
–
–
–
–
132
–
C11
–
J3
–
–
120
–
A16
–
L5
–
–
–
–
133
122
–
B11
C14
–
J2
L2
–
27
34
–
121
109
–
A15
A20
–
L4
R1
–
J
–
L
–
–
–
B14
–
L1
–
–
–
–
–
–
–
–
–
–
–
26
–
123
–
A14
–
K6
–
32
–
110
–
A19
–
P2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
25
–
124
–
D13
–
K5
–
–
111
–
B17
–
N3
–
–
23
–
126
–
C13
–
K4
–
–
112
–
A18
–
N2
–
–
–
–
–
–
–
–
–
–
22
–
127 (2) B13
K3
–
31
–
113
–
D15
–
P1
–
–
–
21
128
A13
K2
30
114
C16
N1
650
Altera Corporation
Preliminary Information
MAX 7000A Programmable Logic Device Family Data Sheet
Table 32. EPM7512AE I/O Pin-Outs (Part 4 of 8)
LAB
MC 144-Pin 208-Pin 256-Pin 256-Pin LAB
MC 144-Pin 208-Pin 256-Pin 256-Pin
TQFP
PQFP
(1)
BGA FineLine
BGA
TQFP
PQFP
(1)
BGA FineLine
BGA
M
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
–
–
–
–
–
–
–
–
101
E18
P5
–
O
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
47
88
H19
R7
–
–
–
–
–
–
–
–
–
46
–
89
–
H18
–
P7
–
–
–
–
102
–
D20
–
N5
–
45
–
90
–
H17
–
T7
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
37
–
103
–
D19
–
T4
–
–
91
–
G20
–
L8
–
–
–
104
–
C20
–
R4
–
44
–
92
–
G19
–
N7
–
–
–
–
–
–
–
–
–
–
36
–
106
–
C19
–
P4
–
–
–
G18
–
M7
–
–
–
35
42
–
108
95
–
B18
G17
–
P3
R6
–
43
54
–
93
79
–
F20
K20
–
L7
M9
–
N
P
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
41
–
96
–
F19
–
T6
–
–
80
–
K19
–
L9
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
40
–
97
–
E20
–
N6
–
53
–
81
–
K17
–
R8
–
39
–
98
–
F18
–
M6
–
–
84
–
J18
–
T8
–
–
–
–
–
–
–
–
–
–
–
99
–
E19
–
R5
–
49
–
86
–
J17
–
N8
–
–
38
100
F17
T5
48
87
H20
M8
Altera Corporation
651
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
Table 32. EPM7512AE I/O Pin-Outs (Part 5 of 8)
LAB
MC 144-Pin 208-Pin 256-Pin 256-Pin LAB
MC 144-Pin 208-Pin 256-Pin 256-Pin
TQFP
PQFP
(1)
BGA FineLine
BGA
TQFP
PQFP
(1)
BGA FineLine
BGA
Q
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
55
78
L20
N9
–
S
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
66
62
P17
K11
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
77
–
L19
–
T9
–
67
–
61
–
R19
–
M12
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
56
–
76
–
L18
–
R9
–
68
–
60
–
T20
–
N12
–
–
73
–
M18
–
L10
–
69
–
59
–
R18
–
T12
–
–
–
–
–
–
–
–
–
–
60
–
71
–
M17
–
M10
–
–
58
–
T19
–
R12
–
–
61
62
–
70
69
–
N20
N19
–
N10
R10
–
70
–
57
56
–
T18
R17
–
T13
P12
–
R
T
–
63
–
68
–
N18
–
T10
–
–
–
–
–
–
–
–
–
–
67
–
N17
–
M11
–
–
55
–
U20
–
T14
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
66
–
P20
–
N11
–
71
–
54
–
U19
–
P13
–
–
65
–
65
–
P19
–
P11
–
72
–
53
–
V20
–
R13
–
–
–
–
–
–
–
–
–
–
–
P18
–
R11
–
–
52
–
W20
–
R14
–
–
–
–
–
64
R20
T11
74
49
W18
R15
652
Altera Corporation
Preliminary Information
MAX 7000A Programmable Logic Device Family Data Sheet
Table 32. EPM7512AE I/O Pin-Outs (Part 6 of 8)
LAB
MC 144-Pin 208-Pin 256-Pin 256-Pin LAB
MC 144-Pin 208-Pin 256-Pin 256-Pin
TQFP
PQFP
(1)
BGA FineLine
BGA
TQFP
PQFP
(1)
BGA FineLine
BGA
U
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
75
48
Y19
P15
–
W
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
82
35
W14
L16
–
–
–
–
–
–
–
–
–
–
–
–
–
Y14
–
L13
–
–
–
–
–
–
–
–
47
–
Y18
–
N15
–
83
–
34
–
U13
–
L12
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
46
–
W17
–
T16
–
84
–
33
–
V13
–
K12
–
–
–
45
–
Y17
–
R16
–
86
–
31
–
W13
–
K14
–
–
–
–
–
–
–
–
–
–
77
–
44
–
U15
–
P16
–
87
–
30 (2)
–
Y13
–
K15
–
78
79
–
43
42
–
V16
W16
–
N14
N16
–
88
89 (2)
–
29
–
U12
K16
V
X
V12 (2) J11 (2)
–
–
–
80
–
40
–
V15
–
M14
–
–
28
–
W12
–
J12
–
–
–
39
–
Y16
–
N13
–
–
27
–
Y12
–
J13
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
81
–
38
–
W15
–
M16
–
–
26
–
V11
–
J14
–
–
–
–
U14
–
M13
–
–
–
U11
–
J15
–
–
–
–
–
–
–
–
–
–
–
–
–
–
37
–
Y15
–
L14
–
–
25
–
W11
–
K13
–
–
–
–
36
V14
L15
90
24
Y11
J16
Altera Corporation
653
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
Table 32. EPM7512AE I/O Pin-Outs (Part 7 of 8)
LAB
MC 144-Pin 208-Pin 256-Pin 256-Pin LAB
MC 144-Pin 208-Pin 256-Pin 256-Pin
TQFP
PQFP
(1)
BGA FineLine
BGA
TQFP
PQFP
(1)
BGA FineLine
BGA
Y
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
91
22
Y10
H10
–
AA
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
–
–
–
–
10
V7
F14
–
–
–
–
–
9
–
8
–
–
–
–
–
7
–
–
6
–
–
–
–
4
–
–
–
–
–
3
–
2
–
–
1
–
208
–
–
21
–
W10
H11
–
Y6
–
F15
–
–
92
–
20
–
V10
–
H12
–
98
U7
–
F16
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
U10
–
H15
–
–
W6
–
E12
–
–
–
–
–
19
–
Y9
–
H16
–
99
Y5
–
E13
–
–
–
–
–
–
–
–
–
–
–
18
–
W9
–
H14
–
100
V6
–
E14
–
–
–
93
–
17
–
V9
U9
–
H13
G12
–
101
W5
V5
–
E16
D16
–
Z
BB
–
–
–
–
–
16
–
Y8
–
G13
–
102
U6
–
C16
–
–
–
94
–
15
–
W8
–
G14
–
–
Y4
–
B16
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
96
–
13
–
V8
–
G16
–
–
W4
–
A16
–
–
–
12
–
U8
–
G11
–
103
Y3
–
D15
–
–
–
–
–
–
–
–
–
–
97
–
11
–
Y7
–
F12
–
104 (2)
–
Y2 (2)
–
D13 (2)
–
–
–
W7
F13
106
W3
C15
654
Altera Corporation
Preliminary Information
MAX 7000A Programmable Logic Device Family Data Sheet
Table 32. EPM7512AE I/O Pin-Outs (Part 8 of 8)
LAB
MC 144-Pin 208-Pin 256-Pin 256-Pin LAB
MC 144-Pin 208-Pin 256-Pin 256-Pin
TQFP
PQFP
(1)
BGA FineLine
BGA
TQFP
PQFP
(1)
BGA FineLine
BGA
CC 449
450
–
–
–
–
–
–
–
–
–
–
–
–
W1
B15
–
EE
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
–
–
–
–
196
P3
D11
–
–
–
–
451
–
–
–
–
–
452
–
–
–
–
–
453
107
–
V1
–
A15
–
113
–
195
–
P2
–
C11
–
454
455
–
–
–
–
–
–
–
456
–
–
–
–
–
–
–
457
108
–
206
–
U2
–
B14
–
114
–
194
–
P1
–
A11
–
458
459
–
205
–
U1
–
A14
–
116
–
193
–
N4
–
B11
–
460
–
461
–
–
–
–
–
–
–
–
462
–
204
–
T3
–
B13
–
117
–
–
N3
–
F10
–
463
–
–
464
109
–
203
202
–
R4
T2
–
A13
C13
–
–
–
N2
N1
–
E10
D10
–
DD 465
466
FF
118
–
192
–
–
467
–
–
–
–
–
–
–
–
468
–
–
–
–
–
–
–
–
469
110
–
201
–
R3
–
D12
–
–
–
M4
–
C10
–
470
–
–
471
–
–
–
–
–
–
–
–
472
–
–
–
–
–
–
–
–
473
111
–
199
–
T1
–
C12
–
119
–
190
–
M3
–
A10
–
474
475
–
198
–
R2
–
B12
–
120
–
189 (2) M2
J10
–
476
–
–
–
477
–
–
–
–
–
–
–
–
478
112
–
197
–
P4
–
A12
–
121
–
188
–
M1
–
F9
–
479
480
–
–
R1
E11
122
187
L3
A9
Altera Corporation
655
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
Notes to tables:
(1) The EPM7512AE device in the 208-pin PQFP package supports vertical migration from the EPM7256E, EPM7256S,
and EPM7256A devices. The EPM7512AE device contains additional I/O pins which are no connects on the
EPM7256E, EPM7256S, and EPM7256A devices. To support these additional I/O pins, the EPM7512AE device has
two additional VCCIO (pins 105 and 207) and GNDIO (pins 51 and 158) pins that are no-connect pins on the
EPM7256E, EPM7256S, and EPM7256A devices. To achieve vertical migration between the EPM7256A and
EPM7512AE devices, the no-connect pins 105 and 207 may be tied to VCCIO and pins 51 and 158 may be tied to
GNDIO on the EPM7256A devices. On the EPM7256E and EPM7256S devices, these no-connect pins must not be
tied to VCCIO or GNDIO. EPM7512AE devices have identical pin-outs.
(2) This pin may function as either a JTAG port or a user I/O pin. If the device is configured to use the JTAG ports for
in-system programming, this pin is not available as a user I/O pin.
(3) The user I/O pin count includes dedicated input pins and all I/O pins.
Figures 14 through 21 show the package pin-out diagrams for
MAX 7000A devices.
Figure 14. 44-Pin PLCC/TQFP Package Pin-Out Diagram
Package outlines not drawn to scale.
Pin 34
Pin 1
6
5
4
3
2
1 44 43 42 41 40
7
39
38
37
36
35
34
33
32
31
30
29
I/O
I/O/(TDI)
I/O
I/O/(TDI)
I/O
I/O
8
I/O/(TDO)
I/O
I/O/(TDO)
9
I/O
I/O
I/O
10
11
12
13
14
15
16
17
I/O
GND
I/O
GND
I/O
I/O
VCC
I/O
VCC
I/O
I/O
EPM7032AE
EPM7064AE
EPM7032AE
EPM7064AE
I/O
I/O
I/O/(TMS)
I/O
I/O
I/O/(TMS)
I/O
I/O/(TCK)
I/O
I/O/(TCK)
I/O
VCC
I/O
GND
I/O
VCC
I/O
I/O
GND
I/O
I/O
18 19 20 21 22 23 24 25 26 27 28
Pin 12
Pin 23
44-Pin PLCC
44-Pin TQFP
656
Altera Corporation
Preliminary Information
MAX 7000A Programmable Logic Device Family Data Sheet
Figure 15. 84-Pin PLCC Package Pin-Out Diagram
Package outline not drawn to scale.
I/O
VCCIO
I/O/TDI
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O/TMS
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
GND
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
I/O
I/O
GND
I/O/TDO
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O/TCK
I/O
I/O
GND
I/O
I/O
I/O
I/O
EPM7128A
EPM7128AE
I/O
Figure 16. 100-Pin TQFP Package Pin-Out Diagram
Package outline not drawn to scale.
Pin 1
Pin 76
EPM7064AE
EPM7128A
EPM7128AE
EPM7256A
EPM7256AE
Pin 26
Pin 51
Altera Corporation
657
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
Figure 17. 100-Pin FineLine BGA Package Pin-Out Diagram
Package outline not drawn to scale.
A1 Ball
Pad Corner
Indicates
location of
Ball A1
A
B
C
D
E
F
G
H
EPM7064AE
EPM7128A
EPM7128AE
EPM7256AE
J
K
10
9
8
7
6
5
4
3
2
1
Figure 18. 144-Pin TQFP Package Pin-Out Diagram
Package outline not drawn to scale.
Indicates location
of Pin 1
Pin 1
Pin 109
EPM7128A
EPM7128AE
EPM7256A
EPM7256AE
EPM7512AE
Pin 37
Pin 73
658
Altera Corporation
Preliminary Information
MAX 7000A Programmable Logic Device Family Data Sheet
Figure 19. 208-Pin PQFP Package Pin-Out Diagram
Package outline not drawn to scale.
Pin 1
Pin 157
EPM7256A
EPM7256AE
EPM7512AE
Pin 53
Pin 105
Altera Corporation
659
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
Figure 20. 256-Pin BGA Package Pin-Out Diagram
Package outline not drawn to scale.
A1 Ball
Pad Corner
Indicates
Location of
Ball A1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
EPM7512AE
U
V
W
X
Y
20 19 18 17 16 15 14 13 12 11 10
9 8 7 6 5 4 3 2 1
660
Altera Corporation
Preliminary Information
MAX 7000A Programmable Logic Device Family Data Sheet
Figure 21. 256-Pin FineLine BGA Package Pin-Out Diagram
Package outline not drawn to scale.
A1 Ball
Pad Corner
A
Indicates
Location of
Ball A1
B
C
D
E
F
G
H
J
EPM7128A
EPM7128AE
EPM7256A
EPM7256AE
EPM7512AE
K
L
M
N
P
R
T
16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
The information contained in the MAX 7000A Programmable Logic Device
Family Data Sheet version 2.01 supersedes information published in
previous versions. The following changes were made to MAX 7000A
Programmable Logic Device Family Data Sheet version 2.01:
Revision
History
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Note (2) on page 618 was updated.
Minor stylistic changes were made throughout the data sheet.
Altera Corporation
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