EPM7128SQC100-10FN [ALTERA]
EE PLD, 10ns, CMOS, PQFP100, PLASTIC, QFP-100;型号: | EPM7128SQC100-10FN |
厂家: | ALTERA CORPORATION |
描述: | EE PLD, 10ns, CMOS, PQFP100, PLASTIC, QFP-100 时钟 输入元件 可编程逻辑 |
文件: | 总66页 (文件大小:481K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MAX 7000
Programmable Logic
Device Family
®
September 2005, ver. 6.7
Data Sheet
■
■
High-performance, EEPROM-based programmable logic devices
(PLDs) based on second-generation MAX® architecture
5.0-V in-system programmability (ISP) through the built-in
IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in
MAX 7000S devices
Features...
–
ISP circuitry compatible with IEEE Std. 1532
■
■
■
■
■
Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S
devices
Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S
devices with 128 or more macrocells
Complete EPLD family with logic densities ranging from 600 to
5,000 usable gates (see Tables 1 and 2)
5-ns pin-to-pin logic delays with up to 175.4-MHz counter
frequencies (including interconnect)
PCI-compliant devices available
For information on in-system programmable 3.3-V MAX 7000A or 2.5-V
MAX 7000B devices, see the MAX 7000A Programmable Logic Device Family
Data Sheet or the MAX 7000B Programmable Logic Device Family Data
Sheet.
f
Table 1. MAX 7000 Device Features
Feature
EPM7032
EPM7064
EPM7096 EPM7128E EPM7160E EPM7192E EPM7256E
Usable
600
1,250
1,800
2,500
3,200
3,750
5,000
gates
Macrocells
32
2
64
4
96
6
128
8
160
10
192
12
256
16
Logic array
blocks
Maximum
36
68
76
100
104
124
164
user I/O pins
t
PD (ns)
tSU (ns)
FSU (ns)
tCO1 (ns)
CNT (MHz)
6
5
6
5
7.5
6
7.5
6
10
12
7
12
7
7
3
t
2.5
4
2.5
4
3
3
3
3
4.5
125.0
4.5
125.0
5
6
6
f
151.5
151.5
100.0
90.9
90.9
Altera Corporation
1
DS-MAX7000-6.7
MAX 7000 Programmable Logic Device Family Data Sheet
Table 2. MAX 7000S Device Features
Feature
EPM7032S
EPM7064S
EPM7128S
EPM7160S
EPM7192S
EPM7256S
Usable gates
Macrocells
600
32
2
1,250
64
2,500
128
8
3,200
160
10
3,750
192
12
5,000
256
16
Logic array
blocks
4
Maximum
36
68
100
104
124
164
user I/O pins
t
PD (ns)
SU (ns)
5
2.9
5
2.9
6
3.4
2.5
4
6
3.4
7.5
4.1
7.5
3.9
t
tFSU (ns)
CO1 (ns)
fCNT (MHz)
2.5
2.5
2.5
3
3
t
3.2
3.2
3.9
4.7
4.7
175.4
175.4
147.1
149.3
125.0
128.2
■
■
Open-drain output option in MAX 7000S devices
Programmable macrocell flipflops with individual clear, preset,
clock, and clock enable controls
Programmable power-saving mode for a reduction of over 50% in
each macrocell
Configurable expander product-term distribution, allowing up to
32 product terms per macrocell
...and More
Features
■
■
■
44 to 208 pins available in plastic J-lead chip carrier (PLCC), ceramic
pin-grid array (PGA), plastic quad flat pack (PQFP), power quad flat
pack (RQFP), and 1.0-mm thin quad flat pack (TQFP) packages
Programmable security bit for protection of proprietary designs
3.3-V or 5.0-V operation
■
■
–
MultiVoltTM I/O interface operation, allowing devices to
interface with 3.3-V or 5.0-V devices (MultiVolt I/O operation is
not available in 44-pin packages)
–
Pin compatible with low-voltage MAX 7000A and MAX 7000B
devices
■
Enhanced features available in MAX 7000E and MAX 7000S devices
–
–
–
–
Six pin- or logic-driven output enable signals
Two global clock signals with optional inversion
Enhanced interconnect resources for improved routability
Fast input setup times provided by a dedicated path from I/O
pin to macrocell registers
–
Programmable output slew-rate control
■
Software design support and automatic place-and-route provided by
Altera’s development system for Windows-based PCs and Sun
SPARCstation, and HP 9000 Series 700/800 workstations
2
Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
■
■
Additional design entry and simulation support provided by EDIF
2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),
Verilog HDL, VHDL, and other interfaces to popular EDA tools from
manufacturers such as Cadence, Exemplar Logic, Mentor Graphics,
OrCAD, Synopsys, and VeriBest
Programming support
–
Altera’s Master Programming Unit (MPU) and programming
hardware from third-party manufacturers program all
MAX 7000 devices
–
The BitBlasterTM serial download cable, ByteBlasterMVTM
parallel port download cable, and MasterBlasterTM
serial/universal serial bus (USB) download cable program MAX
7000S devices
The MAX 7000 family of high-density, high-performance PLDs is based
on Altera’s second-generation MAX architecture. Fabricated with
advanced CMOS technology, the EEPROM-based MAX 7000 family
provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns,
and counter speeds of up to 175.4 MHz. MAX 7000S devices in the -5, -6,
-7, and -10 speed grades as well as MAX 7000 and MAX 7000E devices in
-5, -6, -7, -10P, and -12P speed grades comply with the PCI Special Interest
Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. See Table 3
for available speed grades.
General
Description
Table 3. MAX 7000 Speed Grades
Device
Speed Grade
-5
-6
-7
-10P
-10
-12P
-12
-15
-15T
-20
EPM7032
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
EPM7032S
EPM7064
v
v
v
v
EPM7064S
EPM7096
v
v
v
v
v
v
v
v
v
v
v
EPM7128E
EPM7128S
EPM7160E
EPM7160S
EPM7192E
EPM7192S
EPM7256E
EPM7256S
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Altera Corporation
3
MAX 7000 Programmable Logic Device Family Data Sheet
The MAX 7000E devices—including the EPM7128E, EPM7160E,
EPM7192E, and EPM7256E devices—have several enhanced features:
additional global clocking, additional output enable controls, enhanced
interconnect resources, fast input registers, and a programmable slew
rate.
In-system programmable MAX 7000 devices—called MAX 7000S
devices—include the EPM7032S, EPM7064S, EPM7128S, EPM7160S,
EPM7192S, and EPM7256S devices. MAX 7000S devices have the
enhanced features of MAX 7000E devices as well as JTAG BST circuitry in
devices with 128 or more macrocells, ISP, and an open-drain output
option. See Table 4.
Table 4. MAX 7000 Device Features
Feature
EPM7032
EPM7064
EPM7096
All
All
MAX 7000E
Devices
MAX 7000S
Devices
ISP via JTAG interface
JTAG BST circuitry
Open-drain output option
Fast input registers
Six global output enables
Two global clocks
v
v(1)
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Slew-rate control
MultiVolt interface (2)
Programmable register
Parallel expanders
v
v
v
v
v
v
v
Shared expanders
Power-saving mode
Security bit
PCI-compliant devices available
Notes:
(1) Available only in EPM7128S, EPM7160S, EPM7192S, and EPM7256S devices only.
(2) The MultiVolt I/O interface is not available in 44-pin packages.
4
Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
The MAX 7000 architecture supports 100% TTL emulation and
high-density integration of SSI, MSI, and LSI logic functions. The
MAX 7000 architecture easily integrates multiple devices ranging from
PALs, GALs, and 22V10s to MACH and pLSI devices. MAX 7000 devices
are available in a wide range of packages, including PLCC, PGA, PQFP,
RQFP, and TQFP packages. See Table 5.
Table 5. MAX 7000 Maximum User I/O Pins
Note (1)
Device
44-
Pin
44-
Pin
44-
Pin
68-
Pin
84- 100- 100-
160-
Pin
160- 192-
208-
Pin
208-
Pin
Pin
Pin
Pin
Pin
Pin
PLCC PQFP TQFP PLCC PLCC PQFP TQFP PQFP PGA
PGA
PQFP RQFP
EPM7032
36
36
36
36
36
36
36
36
36
EPM7032S
EPM7064
52
52
68
68
64
68
68
64
64
68
EPM7064S
EPM7096
68
76
84
EPM7128E
EPM7128S
EPM7160E
EPM7160S
EPM7192E
EPM7192S
EPM7256E
EPM7256S
100
84 84 (2) 100
84
104
84 (2) 104
124
124
124
132 (2)
164
164
164 (2)
164
Notes:
(1) When the JTAG interface in MAX 7000S devices is used for either boundary-scan testing or for ISP, four I/O pins
become JTAG pins.
(2) Perform a complete thermal analysis before committing a design to this device package. For more information, see
the Operating Requirements for Altera Devices Data Sheet.
MAX 7000 devices use CMOS EEPROM cells to implement logic
functions. The user-configurable MAX 7000 architecture accommodates a
variety of independent combinatorial and sequential logic functions. The
devices can be reprogrammed for quick and efficient iterations during
design development and debug cycles, and can be programmed and
erased up to 100 times.
Altera Corporation
5
MAX 7000 Programmable Logic Device Family Data Sheet
MAX 7000 devices contain from 32 to 256 macrocells that are combined
into groups of 16 macrocells, called logic array blocks (LABs). Each
macrocell has a programmable-AND/fixed-ORarray and a configurable
register with independently programmable clock, clock enable, clear, and
preset functions. To build complex logic functions, each macrocell can be
supplemented with both shareable expander product terms and high-
speed parallel expander product terms to provide up to 32 product terms
per macrocell.
The MAX 7000 family provides programmable speed/power
optimization. Speed-critical portions of a design can run at high
speed/full power, while the remaining portions run at reduced
speed/low power. This speed/power optimization feature enables the
designer to configure one or more macrocells to operate at 50% or lower
power while adding only a nominal timing delay. MAX 7000E and
MAX 7000S devices also provide an option that reduces the slew rate of
the output buffers, minimizing noise transients when non-speed-critical
signals are switching. The output drivers of all MAX 7000 devices (except
44-pin devices) can be set for either 3.3-V or 5.0-V operation, allowing
MAX 7000 devices to be used in mixed-voltage systems.
The MAX 7000 family is supported byAltera development systems, which
are integrated packages that offer schematic, text—including VHDL,
Verilog HDL, and the Altera Hardware Description Language (AHDL)—
and waveform design entry, compilation and logic synthesis, simulation
and timing analysis, and device programming. The software provides
EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other interfaces for
additional design entry and simulation support from other industry-
standard PC- and UNIX-workstation-based EDA tools. The software runs
on Windows-based PCs, as well as Sun SPARCstation, and HP 9000 Series
700/800 workstations.
For more information on development tools, see the MAX+PLUS II
Programmable Logic Development System & Software Data Sheet and the
Quartus Programmable Logic Development System & Software Data Sheet.
f
The MAX 7000 architecture includes the following elements:
Functional
Description
■
■
■
■
■
Logic array blocks
Macrocells
Expander product terms (shareable and parallel)
Programmable interconnect array
I/O control blocks
6
Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
The MAX 7000 architecture includes four dedicated inputs that can
be used as general-purpose inputs or as high-speed, global control
signals (clock, clear, and two output enable signals) for each
macrocell and I/O pin. Figure 1 shows the architecture of EPM7032,
EPM7064, and EPM7096 devices.
Figure 1. EPM7032, EPM7064 & EPM7096 Device Block Diagram
INPUT/GLCK1
INPUT/GCLRn
INPUT/OE1
INPUT/OE2
LAB A
LAB B
8 to 16
8 to 16
36
36
Macrocells
1 to 16
Macrocells
17 to 32
I/O
Control
Block
I/O
Control
Block
8 to 16
I/O pins
8 to 16
I/O pins
16
16
8 to 16
8 to 16
LAB C
LAB D
PIA
8 to 16
8 to 16
36
36
Macrocells
33 to 48
Macrocells
49 to 64
I/O
Control
Block
I/O
Control
Block
8 to 16
I/O pins
8 to 16
I/O pins
16
16
8 to 16
8 to 16
Altera Corporation
7
MAX 7000 Programmable Logic Device Family Data Sheet
Figure 2 shows the architecture of MAX 7000E and MAX 7000S devices.
Figure 2. MAX 7000E & MAX 7000S Device Block Diagram
INPUT/GCLK1
INPUT/OE2/GCLK2
INPUT/OE1
INPUT/GCLRn
6 Output Enables
6 Output Enables
LAB B
LAB A
6 to16
6 to16
6 to16
6 to16
36
36
Macrocells
17 to 32
Macrocells
1 to 16
I/O
Control
Block
I/O
Control
Block
6 to 16 I/O Pins
6 to 16 I/O Pins
16
16
6
6 to16
6 to16
6
PIA
LAB D
LAB C
6 to16
6 to16
6 to16
6 to16
36
36
Macrocells
33 to 48
Macrocells
49 to 64
I/O
Control
Block
I/O
Control
Block
6 to 16 I/O Pins
6 to 16 I/O Pins
16
16
6
6
6 to16
6 to16
Logic Array Blocks
The MAX 7000 device architecture is based on the linking of high-
performance, flexible, logic array modules called logic array blocks
(LABs). LABs consist of 16-macrocell arrays, as shown in Figures 1 and 2.
Multiple LABs are linked together via the programmable interconnect
array (PIA), a global bus that is fed by all dedicated inputs, I/O pins, and
macrocells.
8
Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
Each LAB is fed by the following signals:
■
■
■
36 signals from the PIA that are used for general logic inputs
Global controls that are used for secondary register functions
Direct input paths from I/O pins to the registers that are used
for fast setup times for MAX 7000E and MAX 7000S devices
Macrocells
The MAX 7000 macrocell can be individually configured for either
sequential or combinatorial logic operation. The macrocell consists
of three functional blocks: the logic array, the product-term select
matrix, and the programmable register. The macrocell of EPM7032,
EPM7064, and EPM7096 devices is shown in Figure 3.
Figure 3. EPM7032, EPM7064 & EPM7096 Device Macrocell
Global Global
Logic Array
Clear
Clocks
From
2
I/O pin
Parallel Logic
Expanders
(from other
macrocells)
Fast Input Programmable
Select Register
Register
Bypass
To I/O
Control
Block
PRN
D/T
Q
Clock/
Enable
Select
Product-
Term
Select
Matrix
ENA
CLRN
VCC
Clear
Select
to PIA
Shared Logic
Expanders
36 Signals
from PIA
16 Expander
Product Terms
Altera Corporation
9
MAX 7000 Programmable Logic Device Family Data Sheet
Figure 4 shows a MAX 7000E and MAX 7000S device macrocell.
Figure 4. MAX 7000E & MAX 7000S Device Macrocell
Global Global
Logic Array
Clear
Clocks
from
2
I/O pin
Parallel Logic
Expanders
(from other
macrocells)
Fast Input Programmable
Select Register
Register
Bypass
to I/O
Control
Block
PRN
D/T
Q
Clock/
Enable
Select
Product-
Term
Select
Matrix
ENA
CLRN
VCC
Clear
Select
to PIA
Shared Logic
Expanders
36 Signals
from PIA
16 Expander
Product Terms
Combinatorial logic is implemented in the logic array, which provides
five product terms per macrocell. The product-term select matrix allocates
these product terms for use as either primary logic inputs (to the ORand
XORgates) to implement combinatorial functions, or as secondary inputs
to the macrocell’s register clear, preset, clock, and clock enable control
functions. Two kinds of expander product terms (“expanders”) are
available to supplement macrocell logic resources:
■
■
Shareable expanders, which are inverted product terms that are fed
back into the logic array
Parallel expanders, which are product terms borrowed from adjacent
macrocells
The Altera development system automatically optimizes product-term
allocation according to the logic requirements of the design.
For registered functions, each macrocell flipflop can be individually
programmed to implement D, T, JK, or SR operation with programmable
clock control. The flipflop can be bypassed for combinatorial operation.
During design entry, the designer specifies the desired flipflop type; the
Altera development software then selects the most efficient flipflop
operation for each registered function to optimize resource utilization.
10
Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
Each programmable register can be clocked in three different modes:
■
■
By a global clock signal. This mode achieves the fastest clock-to-
output performance.
By a global clock signal and enabled by an active-high clock
enable. This mode provides an enable on each flipflop while still
achieving the fast clock-to-output performance of the global
clock.
■
By an array clock implemented with a product term. In this
mode, the flipflop can be clocked by signals from buried
macrocells or I/O pins.
In EPM7032, EPM7064, and EPM7096 devices, the global clock signal
is available from a dedicated clock pin, GCLK1, as shown in Figure 1.
In MAX 7000E and MAX 7000S devices, two global clock signals are
available. As shown in Figure 2, these global clock signals can be the
true or the complement of either of the global clock pins, GCLK1or
GCLK2.
Each register also supports asynchronous preset and clear functions.
As shown in Figures 3 and 4, the product-term select matrix allocates
product terms to control these operations. Although the
product-term-driven preset and clear of the register are active high,
active-low control can be obtained by inverting the signal within the
logic array. In addition, each register clear function can be
individually driven by the active-low dedicated global clear pin
(GCLRn). Upon power-up, each register in the device will be set to a
low state.
All MAX 7000E and MAX 7000S I/O pins have a fast input path to a
macrocell register. This dedicated path allows a signal to bypass the
PIA and combinatorial logic and be driven to an input D flipflop with
an extremely fast (2.5 ns) input setup time.
Expander Product Terms
Although most logic functions can be implemented with the five
product terms available in each macrocell, the more complex logic
functions require additional product terms. Another macrocell can
be used to supply the required logic resources; however, the
MAX 7000 architecture also allows both shareable and parallel
expander product terms (“expanders”) that provide additional
product terms directly to any macrocell in the same LAB. These
expanders help ensure that logic is synthesized with the fewest
possible logic resources to obtain the fastest possible speed.
Altera Corporation
11
MAX 7000 Programmable Logic Device Family Data Sheet
Shareable Expanders
Each LAB has 16 shareable expanders that can be viewed as a pool of
uncommitted single product terms (one from each macrocell) with
inverted outputs that feed back into the logic array. Each shareable
expander can be used and shared by any or all macrocells in the LAB to
build complex logic functions. A small delay (tSEXP) is incurred when
shareable expanders are used. Figure 5 shows how shareable expanders
can feed multiple macrocells.
Figure 5. Shareable Expanders
Shareable expanders can be shared by any or all macrocells in an LAB.
Macrocell
Product-Term
Logic
Product-Term Select Matrix
Macrocell
Product-Term
Logic
36 Signals
from PIA
16 Shared
Expanders
Parallel Expanders
Parallel expanders are unused product terms that can be allocated to a
neighboring macrocell to implement fast, complex logic functions.
Parallel expanders allow up to 20 product terms to directly feed the
macrocell ORlogic, with five product terms provided by the macrocell and
15 parallel expanders provided by neighboring macrocells in the LAB.
12
Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
The compiler can allocate up to three sets of up to five parallel expanders
automatically to the macrocells that require additional product terms.
Each set of five parallel expanders incurs a small, incremental timing
delay (tPEXP). For example, if a macrocell requires 14 product terms, the
Compiler uses the five dedicated product terms within the macrocell and
allocates two sets of parallel expanders; the first set includes five product
terms and the second set includes four product terms, increasing the total
delay by 2 × tPEXP
.
Two groups of 8 macrocells within each LAB (e.g., macrocells
1 through 8 and 9 through 16) form two chains to lend or borrow parallel
expanders. A macrocell borrows parallel expanders from lower-
numbered macrocells. For example, macrocell 8 can borrow parallel
expanders from macrocell 7, from macrocells 7 and 6, or from macrocells
7, 6, and 5. Within each group of 8, the lowest-numbered macrocell can
only lend parallel expanders and the highest-numbered macrocell can
only borrow them. Figure 6 shows how parallel expanders can be
borrowed from a neighboring macrocell.
Figure 6. Parallel Expanders
Unused product terms in a macrocell can be allocated to a neighboring macrocell.
From
Previous
Macrocell
Preset
Product-
Term
Select
Matrix
Macrocell
Product-
Term Logic
Clock
Clear
Preset
Product-
Term
Select
Matrix
Macrocell
Product-
Term Logic
Clock
Clear
To Next
Macrocell
36 Signals 16 Shared
from PIA
Expanders
Altera Corporation
13
MAX 7000 Programmable Logic Device Family Data Sheet
Programmable Interconnect Array
Logic is routed between LABs via the programmable interconnect array
(PIA). This global bus is a programmable path that connects any signal
source to any destination on the device. All MAX 7000 dedicated inputs,
I/O pins, and macrocell outputs feed the PIA, which makes the signals
available throughout the entire device. Only the signals required by each
LAB are actually routed from the PIA into the LAB. Figure 7 shows how
the PIA signals are routed into the LAB. An EEPROM cell controls one
input to a 2-input ANDgate, which selects a PIA signal to drive into the
LAB.
Figure 7. PIA Routing
To LAB
PIA Signals
While the routing delays of channel-based routing schemes in masked or
FPGAs are cumulative, variable, and path-dependent, the MAX 7000 PIA
has a fixed delay. The PIA thus eliminates skew between signals and
makes timing performance easy to predict.
I/O Control Blocks
The I/O control block allows each I/O pin to be individually configured
for input, output, or bidirectional operation. All I/O pins have a tri-state
buffer that is individually controlled by one of the global output enable
signals or directly connected to ground or VCC. Figure 8 shows the I/O
control block for the MAX 7000 family. The I/O control block of EPM7032,
EPM7064, and EPM7096 devices has two global output enable signals that
are driven by two dedicated active-low output enable pins (OE1and OE2).
The I/O control block of MAX 7000E and MAX 7000S devices has six
global output enable signals that are driven by the true or complement of
two output enable signals, a subset of the I/O pins, or a subset of the I/O
macrocells.
14
Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
Figure 8. I/O Control Block of MAX 7000 Devices
EPM7032, EPM7064 & EPM7096 Devices
VCC
OE1
OE2
GND
From Macrocell
To PIA
MAX 7000E & MAX 7000S Devices
Six Global Output Enable Signals
PIA
VCC
GND
To Other I/O Pins
From
Macrocell
Open-Drain Output (1)
Slew-Rate Control
Fast Input to
Macrocell
Register
To PIA
Note:
(1) The open-drain output option is available only in MAX 7000S devices.
Altera Corporation
15
MAX 7000 Programmable Logic Device Family Data Sheet
When the tri-state buffer control is connected to ground, the output is
tri-stated (high impedance) and the I/O pin can be used as a dedicated
input. When the tri-state buffer control is connected to VCC, the output is
enabled.
The MAX 7000 architecture provides dual I/O feedback, in which
macrocell and pin feedbacks are independent. When an I/O pin is
configured as an input, the associated macrocell can be used for buried
logic.
MAX 7000S devices are in-system programmable via an
In-System
Programma-
bility (ISP)
industry-standard 4-pin Joint Test Action Group (JTAG) interface (IEEE
Std. 1149.1-1990). ISP allows quick, efficient iterations during design
development and debugging cycles. The MAX 7000S architecture
internally generates the high programming voltage required to program
EEPROM cells, allowing in-system programming with only a single 5.0 V
power supply. During in-system programming, the I/O pins are tri-stated
and pulled-up to eliminate board conflicts. The pull-up value is nominally
50 k¾.
ISP simplifies the manufacturing flow by allowing devices to be mounted
on a printed circuit board with standard in-circuit test equipment before
they are programmed. MAX 7000S devices can be programmed by
downloading the information via in-circuit testers (ICT), embedded
processors, or the Altera MasterBlaster, ByteBlasterMV, ByteBlaster,
BitBlaster download cables. (The ByteBlaster cable is obsolete and is
replaced by the ByteBlasterMV cable, which can program and configure
2.5-V, 3.3-V, and 5.0-V devices.) Programming the devices after they are
placed on the board eliminates lead damage on high-pin-count packages
(e.g., QFP packages) due to device handling and allows devices to be
reprogrammed after a system has already shipped to the field. For
example, product upgrades can be performed in the field via software or
modem.
In-system programming can be accomplished with either an adaptive or
constant algorithm. An adaptive algorithm reads information from the
unit and adapts subsequent programming steps to achieve the fastest
possible programming time for that unit. Because some in-circuit testers
cannot support an adaptive algorithm, Altera offers devices tested with a
constant algorithm. Devices tested to the constant algorithm have an “F”
suffix in the ordering code.
The JamTM Standard Test and Programming Language (STAPL) can be
used to program MAX 7000S devices with in-circuit testers, PCs, or
embedded processor.
16
Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
For more information on using the Jam language, refer to AN 122: Using
Jam STAPL for ISP & ICR via an Embedded Processor.
f
The ISP circuitry in MAX 7000S devices is compatible with IEEE Std. 1532
specification. The IEEE Std. 1532 is a standard developed to allow
concurrent ISP between multiple PLD vendors.
Programming Sequence
During in-system programming, instructions, addresses, and data are
shifted into the MAX 7000S device through the TDIinput pin. Data is
shifted out through the TDOoutput pin and compared against the
expected data.
Programming a pattern into the device requires the following six ISP
stages. A stand-alone verification of a programmed pattern involves only
stages 1, 2, 5, and 6.
1. Enter ISP. The enter ISP stage ensures that the I/O pins transition
smoothly from user mode to ISP mode. The enter ISP stage requires
1 ms.
2. Check ID. Before any program or verify process, the silicon ID is
checked. The time required to read this silicon ID is relatively small
compared to the overall programming time.
3. Bulk Erase. Erasing the device in-system involves shifting in the
instructions to erase the device and applying one erase pulse of
100 ms.
4. Program. Programming the device in-system involves shifting in the
address and data and then applying the programming pulse to
program the EEPROM cells. This process is repeated for each
EEPROM address.
5. Verify. Verifying an Altera device in-system involves shifting in
addresses, applying the read pulse to verify the EEPROM cells, and
shifting out the data for comparison. This process is repeated for
each EEPROM address.
6. Exit ISP. An exit ISP stage ensures that the I/O pins transition
smoothly from ISP mode to user mode. The exit ISP stage requires
1 ms.
Altera Corporation
17
MAX 7000 Programmable Logic Device Family Data Sheet
Programming Times
The time required to implement each of the six programming stages can
be broken into the following two elements:
■
■
A pulse time to erase, program, or read the EEPROM cells.
A shifting time based on the test clock (TCK) frequency and the
number of TCKcycles to shift instructions, address, and data into the
device.
By combining the pulse and shift times for each of the programming
stages, the program or verify time can be derived as a function of the TCK
frequency, the number of devices, and specific target device(s). Because
different ISP-capable devices have a different number of EEPROM cells,
both the total fixed and total variable times are unique for a single device.
Programming a Single MAX 7000S Device
The time required to program a single MAX 7000S device in-system can
be calculated from the following formula:
Cycle
PTCK
t
= t
+ -------------------------------
PROG
PPULSE
f
TCK
where: tPROG
= Programming time
= Sum of the fixed times to erase, program, and
verify the EEPROM cells
tPPULSE
CyclePTCK = Number of TCKcycles to program a device
fTCK = TCKfrequency
The ISP times for a stand-alone verification of a single MAX 7000S device
can be calculated from the following formula:
Cycle
VTCK
t
= t
+ --------------------------------
VER
VPULSE
f
TCK
where: tVER
tVPULSE
CycleVTCK = Number of TCKcycles to verify a device
= Verify time
= Sum of the fixed times to verify the EEPROM cells
18
Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
The programming times described in Tables 6 through 8 are associated
with the worst-case method using the enhanced ISP algorithm.
Table 6. MAX 7000S tPULSE & CycleTCK Values
Device
Programming
Stand-Alone Verification
tVPULSE (s) CycleVTCK
tPPULSE (s)
CyclePTCK
EPM7032S
EPM7064S
EPM7128S
EPM7160S
EPM7192S
EPM7256S
4.02
4.50
5.11
5.35
5.71
6.43
342,000
504,000
0.03
0.03
0.03
0.03
0.03
0.03
200,000
308,000
528,000
640,000
764,000
1,024,000
832,000
1,001,000
1,192,000
1,603,000
Tables 7 and 8 show the in-system programming and stand alone
verification times for several common test clock frequencies.
Table 7. MAX 7000S In-System Programming Times for Different Test Clock Frequencies
Device
fTCK
500 kHz 200 kHz 100 kHz 50 kHz
Units
10 MHz 5 MHz
2 MHz
1 MHz
EPM7032S
EPM7064S
EPM7128S
EPM7160S
EPM7192S
EPM7256S
4.06
4.55
5.19
5.45
5.83
6.59
4.09
4.60
5.27
5.55
5.95
6.75
4.19
4.76
5.52
5.85
6.30
7.23
4.36
5.01
5.94
6.35
6.90
8.03
4.71
5.51
6.77
7.35
8.09
9.64
5.73
7.02
7.44
9.54
10.86
14.58
21.75
25.37
29.55
38.49
s
s
s
s
s
s
9.27
13.43
15.36
17.63
22.46
10.35
11.67
14.45
Table 8. MAX 7000S Stand-Alone Verification Times for Different Test Clock Frequencies
Device
fTCK
500 kHz 200 kHz 100 kHz 50 kHz
Units
10 MHz 5 MHz
2 MHz
1 MHz
EPM7032S
EPM7064S
EPM7128S
EPM7160S
EPM7192S
EPM7256S
0.05
0.06
0.08
0.09
0.11
0.13
0.07
0.09
0.14
0.16
0.18
0.24
0.13
0.18
0.29
0.35
0.41
0.54
0.23
0.34
0.56
0.67
0.79
1.06
0.43
0.64
1.09
1.31
1.56
2.08
1.03
1.57
2.67
3.23
3.85
5.15
2.03
3.11
5.31
6.43
7.67
10.27
4.03
6.19
s
s
s
s
s
s
10.59
12.83
15.31
20.51
Altera Corporation
19
MAX 7000 Programmable Logic Device Family Data Sheet
MAX 7000 devices offer a power-saving mode that supports low-power
Programmable
Speed/Power
Control
operation across user-defined signal paths or the entire device. This
feature allows total power dissipation to be reduced by 50% or more,
because most logic applications require only a small fraction of all gates to
operate at maximum frequency.
The designer can program each individual macrocell in a MAX 7000
device for either high-speed (i.e., with the Turbo BitTM option turned on)
or low-power (i.e., with the Turbo Bit option turned off) operation. As a
result, speed-critical paths in the design can run at high speed, while the
remaining paths can operate at reduced power. Macrocells that run at low
power incur a nominal timing delay adder (tLPA) for the tLAD, tLAC, tIC
,
tEN, and tSEXP, tACL, and tCPPW parameters.
MAX 7000 device outputs can be programmed to meet a variety of
system-level requirements.
Output
Configuration
MultiVolt I/O Interface
MAX 7000 devices—except 44-pin devices—support the MultiVolt I/O
interface feature, which allows MAX 7000 devices to interface with
systems that have differing supply voltages. The 5.0-V devices in all
packages can be set for 3.3-V or 5.0-V I/O pin operation. These devices
have one set of VCCpins for internal operation and input buffers
(VCCINT), and another set for I/O output drivers (VCCIO).
The VCCINTpins must always be connected to a 5.0-V power supply.
With a 5.0-V VCCINT level, input voltage thresholds are at TTL levels, and
are therefore compatible with both 3.3-V and 5.0-V inputs.
The VCCIOpins can be connected to either a 3.3-V or a 5.0-V power
supply, depending on the output requirements. When the VCCIOpins are
connected to a 5.0-V supply, the output levels are compatible with 5.0-V
systems. When VCCIO is connected to a 3.3-V supply, the output high is
3.3 V and is therefore compatible with 3.3-V or 5.0-V systems. Devices
operating with VCCIO levels lower than 4.75 V incur a nominally greater
timing delay of tOD2 instead of tOD1
.
Open-Drain Output Option (MAX 7000S Devices Only)
MAX 7000S devices provide an optional open-drain (functionally
equivalent to open-collector) output for each I/O pin. This open-drain
output enables the device to provide system-level control signals (e.g.,
interrupt and write enable signals) that can be asserted by any of several
devices. It can also provide an additional wired-ORplane.
20
Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
By using an external 5.0-V pull-up resistor, output pins on MAX
7000S devices can be set to meet 5.0-V CMOS input voltages. When
VCCIO is 3.3 V, setting the open drain option will turn off the output
pull-up transistor, allowing the external pull-up resistor to pull the
output high enough to meet 5.0-V CMOS input voltages. When
VCCIO is 5.0 V, setting the output drain option is not necessary
because the pull-up transistor will already turn off when the pin
exceeds approximately 3.8 V, allowing the external pull-up resistor to
pull the output high enough to meet 5.0-V CMOS input voltages.
Slew-Rate Control
The output buffer for each MAX 7000E and MAX 7000S I/O pin has
an adjustable output slew rate that can be configured for low-noise
or high-speed performance. A faster slew rate provides high-speed
transitions for high-performance systems. However, these fast
transitions may introduce noise transients into the system. A slow
slew rate reduces system noise, but adds a nominal delay of 4 to 5 ns.
In MAX 7000E devices, when the Turbo Bit is turned off, the slew
rate is set for low noise performance. For MAX 7000S devices, each
I/O pin has an individual EEPROM bit that controls the slew rate,
allowing designers to specify the slew rate on a pin-by-pin basis.
MAX 7000 devices can be programmed on Windows-based PCs with
the Altera Logic Programmer card, the Master Programming Unit
(MPU), and the appropriate device adapter. The MPU performs a
continuity check to ensure adequate electrical contact between the
adapter and the device.
Programming with
External Hardware
For more information, see the Altera Programming Hardware Data
Sheet.
f
The Altera development system can use text- or waveform-format
test vectors created with the Text Editor or Waveform Editor to test
the programmed device. For added design verification, designers
can perform functional testing to compare the functional behavior of
a MAX 7000 device with the results of simulation. Moreover, Data
I/O, BP Microsystems, and other programming hardware
manufacturers also provide programming support for Altera
devices.
For more information, see the Programming Hardware Manufacturers.
f
Altera Corporation
21
MAX 7000 Programmable Logic Device Family Data Sheet
MAX 7000 devices support JTAG BST circuitry as specified by IEEE Std.
IEEE Std.
1149.1-1990. Table 9 describes the JTAG instructions supported by the
MAX 7000 family. The pin-out tables (see the Altera web site
(http://www.altera.com) or the Altera Digital Library for pin-out
information) show the location of the JTAG control pins for each device.
If the JTAG interface is not required, the JTAG pins are available as user
I/O pins.
1149.1 (JTAG)
Boundary-Scan
Support
Table 9. MAX 7000 JTAG Instructions
JTAG Instruction
Devices
Description
SAMPLE/PRELOAD
EPM7128S
EPM7160S
EPM7192S
EPM7256S
Allows a snapshot of signals at the device pins to be captured and
examined during normal device operation, and permits an initial data
pattern output at the device pins.
EXTEST
BYPASS
EPM7128S
EPM7160S
EPM7192S
EPM7256S
Allows the external circuitry and board-level interconnections to be
tested by forcing a test pattern at the output pins and capturing test
results at the input pins.
EPM7032S
EPM7064S
EPM7128S
EPM7160S
EPM7192S
EPM7256S
Places the 1-bit bypass register between the TDIand TDOpins, which
allows the BST data to pass synchronously through a selected device
to adjacent devices during normal device operation.
IDCODE
EPM7032S
EPM7064S
EPM7128S
EPM7160S
EPM7192S
EPM7256S
Selects the IDCODE register and places it between TDIand TDO,
allowing the IDCODE to be serially shifted out of TDO.
ISP Instructions
EPM7032S
EPM7064S
EPM7128S
EPM7160S
EPM7192S
EPM7256S
These instructions are used when programming MAX 7000S devices
via the JTAG ports with the MasterBlaster, ByteBlasterMV, BitBlaster
download cable, or using a Jam File (.jam), Jam Byte-Code file (.jbc),
or Serial Vector Format file (.svf) via an embedded processor or test
equipment.
22
Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
The instruction register length of MAX 7000S devices is 10 bits. Tables 10
and 11 show the boundary-scan register length and device IDCODE
information for MAX 7000S devices.
Table 10. MAX 7000S Boundary-Scan Register Length
Device
Boundary-Scan Register Length
EPM7032S
EPM7064S
EPM7128S
EPM7160S
EPM7192S
EPM7256S
1 (1)
1 (1)
288
312
360
480
Note:
(1) This device does not support JTAG boundary-scan testing. Selecting either the
EXTEST or SAMPLE/PRELOAD instruction will select the one-bit bypass register.
Table 11. 32-Bit MAX 7000 Device IDCODE
Note (1)
Device
IDCODE (32 Bits)
Part Number (16 Bits) Manufacturer’s 1 (1 Bit)
Version
(4 Bits)
Identity (11 Bits)
(2)
EPM7032S
EPM7064S
EPM7128S
EPM7160S
EPM7192S
EPM7256S
0000
0000
0000
0000
0000
0000
0111 0000 0011 0010 00001101110
0111 0000 0110 0100 00001101110
0111 0001 0010 1000 00001101110
0111 0001 0110 0000 00001101110
0111 0001 1001 0010 00001101110
0111 0010 0101 0110 00001101110
1
1
1
1
1
1
Notes:
(1) The most significant bit (MSB) is on the left.
(2) The least significant bit (LSB) for all JTAG IDCODEs is 1.
Altera Corporation
23
MAX 7000 Programmable Logic Device Family Data Sheet
Figure 9 shows the timing requirements for the JTAG signals.
Figure 9. MAX 7000 JTAG Waveforms
TMS
TDI
tJCP
tJCH
t JCL
tJPH
tJPSU
TCK
TDO
tJPXZ
tJPZX
tJPCO
tJSSU
tJSH
Signal
to Be
Captured
tJSCO
tJSZX
tJSXZ
Signal
to Be
Driven
Table 12 shows the JTAG timing parameters and values for MAX 7000S
devices.
Table 12. JTAG Timing Parameters & Values for MAX 7000S Devices
Symbol
Parameter
Min Max Unit
tJCP
tJCH
tJCL
TCKclock period
TCKclock high time
TCKclock low time
100
50
50
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tJPSU JTAG port setup time
tJPH JTAG port hold time
45
tJPCO JTAG port clock to output
25
25
25
tJPZX JTAG port high impedance to valid output
tJPXZ JTAG port valid output to high impedance
tJSSU Capture register setup time
20
45
tJSH
Capture register hold time
tJSCO Update register clock to output
25
25
25
tJSZX Update register high impedance to valid output
tJSXZ Update register valid output to high impedance
For more information, see Application Note 39 (IEEE 1149.1 (JTAG)
Boundary-Scan Testing in Altera Devices).
f
24
Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
All MAX 7000 devices contain a programmable security bit that controls
access to the data programmed into the device. When this bit is
programmed, a proprietary design implemented in the device cannot be
copied or retrieved. This feature provides a high level of design security
because programmed data within EEPROM cells is invisible. The security
bit that controls this function, as well as all other programmed data, is
reset only when the device is reprogrammed.
Design Security
Generic Testing
Each MAX 7000 device is functionally tested. Complete testing of each
programmable EEPROM bit and all internal logic elements ensures 100%
programming yield. AC test measurements are taken under conditions
equivalent to those shown in Figure 10. Test patterns can be used and then
erased during early stages of the production flow.
Figure 10. MAX 7000 AC Test Conditions
Power supply transients can affect AC
measurements. Simultaneous
transitions of multiple outputs should be
VCC
avoided for accurate measurement.
Threshold tests must not be performed
under AC conditions. Large-amplitude,
fast ground-current transients normally
occur as the device outputs discharge
the load capacitances. When these
transients flow through the parasitic
inductance between the device ground
pin and the test system ground,
464 Ω
[703 Ω]
Device
Output
To Test
System
250
Ω
C1 (includes JIG
capacitance)
[8.06
]
KΩ
significant reductions in observable
noise immunity can result. Numbers in
brackets are for 2.5-V devices and
outputs. Numbers without brackets are
for 3.3-V devices and outputs.
Device input
rise and fall
times < 3 ns
MAX 7000 and MAX 7000E devices in QFP packages with 100 or more
pins are shipped in special plastic carriers to protect the QFP leads. The
carrier is used with a prototype development socket and special
programming hardware available from Altera. This carrier technology
makes it possible to program, test, erase, and reprogram a device without
exposing the leads to mechanical stress.
QFP Carrier &
Development
Socket
For detailed information and carrier dimensions, refer to the QFP Carrier
& Development Socket Data Sheet.
f
1
MAX 7000S devices are not shipped in carriers.
Altera Corporation
25
MAX 7000 Programmable Logic Device Family Data Sheet
Tables 13 through 18 provide information about absolute maximum
ratings, recommended operating conditions, operating conditions, and
capacitance for 5.0-V MAX 7000 devices.
Operating
Conditions
Table 13. MAX 7000 5.0-V Device Absolute Maximum Ratings
Note (1)
Symbol
Parameter
Conditions
Min
Max
Unit
V
Supply voltage
With respect to ground (2)
–2.0
7.0
V
CC
V
DC input voltage
–2.0
–25
–65
–65
7.0
25
V
I
I
DC output current, per pin
Storage temperature
Ambient temperature
Junction temperature
mA
° C
° C
° C
° C
OUT
T
T
T
No bias
150
135
150
135
STG
AMB
J
Under bias
Ceramic packages, under bias
PQFP and RQFP packages, under bias
Table 14. MAX 7000 5.0-V Device Recommended Operating Conditions
Symbol
Parameter
Conditions
Min
Max
Unit
V
Supply voltage for internal logic and (3), (4), (5)
input buffers
4.75
(4.50)
5.25
(5.50)
V
V
V
CCINT
V
Supply voltage for output drivers,
5.0-V operation
(3), (4)
(3), (4), (6)
(7)
4.75
(4.50)
5.25
(5.50)
CCIO
Supply voltage for output drivers,
3.3-V operation
3.00
(3.00)
3.60
(3.60)
V
V
V
Supply voltage during ISP
Input voltage
4.75
5.25
V
V
CCISP
–0.5 (8)
V
+ 0.5
CCINT
I
Output voltage
0
0
V
V
O
A
CCIO
70
T
Ambient temperature
For commercial use
For industrial use
For commercial use
For industrial use
° C
° C
° C
° C
ns
ns
–40
0
85
90
T
Junction temperature
J
–40
105
40
t
t
Input rise time
Input fall time
R
40
F
26
Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
Table 15. MAX 7000 5.0-V Device DC Operating Conditions
Note (9)
Symbol
Parameter
Conditions
Min
Max
Unit
V
V
V
High-level input voltage
2.0
–0.5 (8)
2.4
V
+ 0.5
CCINT
V
V
V
V
V
IH
Low-level input voltage
0.8
IL
5.0-V high-level TTL output voltage
3.3-V high-level TTL output voltage
I
I
I
= –4 mA DC, V
= –4 mA DC, V
= 4.75 V (10)
= 3.00 V (10)
OH
OH
CCIO
CCIO
2.4
OH
OH
3.3-V high-level CMOS output
voltage
= –0.1 mA DC, V
= 3.0 V (10)
V
– 0.2
CCIO
CCIO
V
5.0-V low-level TTL output voltage
3.3-V low-level TTL output voltage
I
I
I
= 12 mA DC, V
= 12 mA DC, V
= 4.75 V (11)
= 3.00 V (11)
= 3.0 V(11)
0.45
0.45
0.2
V
V
V
OL
OL
CCIO
CCIO
OL
OL
3.3-V low-level CMOS output
voltage
= 0.1 mA DC, V
CCIO
I
I
Leakage current of dedicated input V = –0.5 to 5.5 V (11)
pins
–10
–40
10
40
μA
μA
I
I
I/O pin tri-state output off-state
current
V = –0.5 to 5.5 V (11), (12)
I
OZ
Table 16. MAX 7000 5.0-V Device Capacitance: EPM7032, EPM7064 & EPM7096 Devices
Note (13)
Symbol
Parameter
Conditions
Min
Min
Min
Max
Unit
C
C
Input pin capacitance
I/O pin capacitance
V
V
= 0 V, f = 1.0 MHz
12
12
pF
pF
IN
IN
= 0 V, f = 1.0 MHz
I/O
OUT
Table 17. MAX 7000 5.0-V Device Capacitance: MAX 7000E Devices Note (13)
Symbol
Parameter
Conditions
Max
Unit
C
C
Input pin capacitance
I/O pin capacitance
V
V
= 0 V, f = 1.0 MHz
15
15
pF
pF
IN
IN
= 0 V, f = 1.0 MHz
I/O
OUT
Table 18. MAX 7000 5.0-V Device Capacitance: MAX 7000S Devices
Note (13)
Symbol
Parameter
Conditions
Max
Unit
C
C
Dedicated input pin capacitance
I/O pin capacitance
V
V
= 0 V, f = 1.0 MHz
10
10
pF
pF
IN
IN
= 0 V, f = 1.0 MHz
I/O
OUT
Altera Corporation
27
MAX 7000 Programmable Logic Device Family Data Sheet
Notes to tables:
(1) See the Operating Requirements for Altera Devices Data Sheet.
(2) Minimum DC input voltage on I/O pins is –0.5 V and on 4 dedicated input pins is –0.3 V. During transitions, the
inputs may undershoot to –2.0 V or overshoot to 7.0 V for input currents less than 100 mA and periods shorter than
20 ns.
(3) Numbers in parentheses are for industrial-temperature-range devices.
(4)
V
must rise monotonically.
CC
(5) The POR time for all 7000S devices does not exceed 300 μs. The sufficient V
voltage level for POR is 4.5 V. The
CCINT
device is fully initialized within the POR time after V
reaches the sufficient POR voltage level.
CCINT
(6) 3.3-V I/O operation is not available for 44-pin packages.
(7) The V parameter applies only to MAX 7000S devices.
CCISP
(8) During in-system programming, the minimum DC input voltage is –0.3 V.
(9) These values are specified under the MAX 7000 recommended operating conditions in Table 14 on page 26.
(10) The parameter is measured with 50% of the outputs each sourcing the specified current. The I
parameter refers
OH
to high-level TTL or CMOS output current.
(11) The parameter is measured with 50% of the outputs each sinking the specified current. The I parameter refers to
OL
low-level TTL, PCI, or CMOS output current.
(12) When the JTAG interface is enabled in MAX 7000S devices, the input leakage current on the JTAG pins is typically
–60 μA.
(13) Capacitance is measured at 25° C and is sample-tested only. The OE1pin has a maximum capacitance of 20 pF.
Figure 11 shows the typical output drive characteristics of MAX 7000
devices.
Figure 11. Output Drive Characteristics of 5.0-V MAX 7000 Devices
150
120
90
150
120
90
IOL
IOL
Typical IO
Output
Current (mA)
Typical IO
Output
Current (mA)
VCCIO = 5.0 V
Room Temperature
VCCIO = 3.3 V
Room Temperature
60
60
IOH
IOH
30
30
3.3
1
2
3
4
5
1
2
3
4
5
VO Output Voltage (V)
VO Output Voltage (V)
MAX 7000 device timing can be analyzed with the Altera software, with a
variety of popular industry-standard EDA simulators and timing
analyzers, or with the timing model shown in Figure 12. MAX 7000
devices have fixed internal delays that enable the designer to determine
the worst-case timing of any design. The Altera software provides timing
simulation, point-to-point delay prediction, and detailed timing analysis
for a device-wide performance evaluation.
Timing Model
28
Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
Figure 12. MAX 7000 Timing Model
Internal Output
Enable Delay
t
IOE (1)
Global Control
Delay
Input
Delay
t I N
Output
Delay
tGLOB
Register
Delay
tSU
Parallel
Expander Delay
tPEXP
Logic Array
Delay
t LAD
tOD1
PIA
Delay
tPIA
tH
t
OD2 (2)
tOD3
tXZ
tPRE
tCLR
tRD
tCOMB
tFSU
tFH
Register
Control Delay
tLAC
tZX1
t
t
ZX2 (2)
ZX3 (1)
tIC
tEN
I/O
Delay
tIO
Shared
Expander Delay
tSEXP
Fast
Input Delay
tFIN
(1)
Notes:
(1) Only available in MAX 7000E and MAX 7000S devices.
(2) Not available in 44-pin devices.
The timing characteristics of any signal path can be derived from the
timing model and parameters of a particular device. External timing
parameters, which represent pin-to-pin timing delays, can be calculated
as the sum of internal parameters. Figure 13 shows the internal timing
relationship of internal and external delay parameters.
For more infomration, see Application Note 94 (Understanding MAX 7000
Timing).
f
Altera Corporation
29
MAX 7000 Programmable Logic Device Family Data Sheet
Figure 13. Switching Waveforms
tR & tF < 3 ns.
Combinatorial Mode
Inputs are driven at 3 V
for a logic high and 0 V
for a logic low. All timing
characteristics are
tIN
Input Pin
I/O Pin
tIO
measured at 1.5 V.
tPIA
PIA Delay
tSEXP
Shared Expander
Delay
tLAC , tLAD
Logic Array
Input
tPEXP
Parallel Expander
Delay
tCOMB
Logic Array
Output
tOD
Output Pin
Global Clock Mode
tR
tCH
tCL
tF
Global
Clock Pin
tIN
tGLOB
Global Clock
at Register
tSU
tH
Data or Enable
(Logic Array Output)
Array Clock Mode
tR
tACH
tACL
tF
Input or I/O Pin
Clock into PIA
tIN
tIO
tPIA
Clock into
Logic Array
tIC
tSU
Clock at
Register
tH
Data from
Logic Array
tRD
tPIA
tPIA
tCLR , tPRE
Register to PIA
to Logic Array
tOD
tOD
Register Output
to Pin
30
Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
Tables 19 through 26 show the MAX 7000 and MAX 7000E AC
operating conditions.
Table 19. MAX 7000 & MAX 7000E External Timing Parameters
Note (1)
Symbol
Parameter
Conditions
-6 Speed Grade
-7 Speed Grade
Unit
Min
Max
Min
Max
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Input to non-registered output
I/O input to non-registered output
Global clock setup time
C1 = 35 pF
C1 = 35 pF
6.0
6.0
7.5
7.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PD1
PD2
SU
5.0
0.0
2.5
0.5
6.0
0.0
3.0
0.5
Global clock hold time
H
Global clock setup time of fast input (2)
FSU
FH
Global clock hold time of fast input
Global clock to output delay
Global clock high time
Global clock low time
(2)
C1 = 35 pF
4.0
6.5
4.5
7.5
CO1
CH
2.5
2.5
2.5
2.0
3.0
3.0
3.0
2.0
CL
Array clock setup time
Array clock hold time
ASU
AH
Array clock to output delay
Array clock high time
C1 = 35 pF
ACO1
ACH
ACL
CPPW
3.0
3.0
3.0
3.0
3.0
3.0
Array clock low time
Minimum pulse width for clear and
preset
(3)
t
t
f
Output data hold time after clock
Minimum global clock period
C1 = 35 pF (4)
1.0
1.0
ns
ns
ODH
CNT
CNT
6.6
6.6
8.0
8.0
Maximum internal global clock
frequency
(5)
151.5
125.0
MHz
t
f
Minimum array clock period
ns
ACNT
ACNT
Maximum internal array clock
frequency
(5)
(6)
151.5
200
125.0
166.7
MHz
f
Maximum clock frequency
MHz
MAX
Altera Corporation
31
MAX 7000 Programmable Logic Device Family Data Sheet
Table 20. MAX 7000 & MAX 7000E Internal Timing Parameters
Note (1)
Symbol
Parameter
Conditions
Speed Grade -6 Speed Grade -7
Unit
Min
Max
Min
Max
t
t
t
t
t
t
t
t
t
Input pad and buffer delay
I/O input pad and buffer delay
Fast input delay
0.4
0.4
0.8
3.5
0.8
2.0
2.0
0.5
0.5
1.0
4.0
0.8
3.0
3.0
2.0
2.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
IN
IO
(2)
FIN
Shared expander delay
Parallel expander delay
Logic array delay
SEXP
PEXP
LAD
LAC
IOE
OD1
Logic control array delay
Internal output enable delay
Output buffer and pad delay
(2)
C1 = 35 pF
2.0
2.5
7.0
Slow slew rate = off, V
= 5.0 V
CCIO
t
t
Output buffer and pad delay
Slow slew rate = off, V = 3.3 V
C1 = 35 pF (7)
C1 = 35 pF (2)
2.5
7.0
ns
ns
OD2
OD3
CCIO
Output buffer and pad delay
Slow slew rate = on,
V
= 5.0 V or 3.3 V
CCIO
t
t
t
Output buffer enable delay
Slow slew rate = off, V
C1 = 35 pF
4.0
4.5
9.0
4.0
4.5
9.0
ns
ns
ns
ZX1
ZX2
ZX3
= 5.0 V
= 3.3 V
CCIO
Output buffer enable delay
Slow slew rate = off, V
C1 = 35 pF (7)
C1 = 35 pF (2)
CCIO
Output buffer enable delay
Slow slew rate = on
V
= 5.0 V or 3.3 V
CCIO
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Output buffer disable delay
Register setup time
C1 = 5 pF
4.0
4.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
XZ
3.0
1.5
2.5
0.5
3.0
2.0
3.0
0.5
SU
Register hold time
H
Register setup time of fast input
Register hold time of fast input
Register delay
(2)
(2)
FSU
FH
0.8
0.8
2.5
2.0
0.8
2.0
2.0
0.8
10.0
1.0
1.0
3.0
3.0
1.0
2.0
2.0
1.0
10.0
RD
Combinatorial delay
Array clock delay
COMB
IC
Register enable time
Global control delay
Register preset time
Register clear time
PIA delay
EN
GLOB
PRE
CLR
PIA
LPA
Low-power adder
(8)
32
Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
Table 21. MAX 7000 & MAX 7000E External Timing Parameters
Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
MAX 7000E (-10P) MAX 7000 (-10)
MAX 7000E (-10)
Min
Max
Min
Max
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Input to non-registered output
I/O input to non-registered output
Global clock setup time
C1 = 35 pF
C1 = 35 pF
10.0
10.0
10.0
10.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PD1
PD2
SU
7.0
0.0
3.0
0.5
8.0
0.0
3.0
0.5
Global clock hold time
H
Global clock setup time of fast input (2)
Global clock hold time of fast input (2)
FSU
FH
Global clock to output delay
Global clock high time
Global clock low time
Array clock setup time
Array clock hold time
Array clock to output delay
Array clock high time
Array clock low time
C1 = 35 pF
5.0
5
CO1
CH
4.0
4.0
2.0
3.0
4.0
4.0
3.0
3.0
CL
ASU
AH
C1 = 35 pF
10.0
10.0
ACO1
ACH
ACL
CPPW
4.0
4.0
4.0
4.0
4.0
4.0
Minimum pulse width for clear and (3)
preset
t
t
f
Output data hold time after clock
Minimum global clock period
C1 = 35 pF (4)
1.0
1.0
ns
ns
ODH
CNT
CNT
10.0
10.0
10.0
10.0
Maximum internal global clock
frequency
(5)
100.0
100.0
MHz
t
f
Minimum array clock period
ns
ACNT
ACNT
Maximum internal array clock
frequency
(5)
(6)
100.0
125.0
100.0
125.0
MHz
f
Maximum clock frequency
MHz
MAX
Altera Corporation
33
MAX 7000 Programmable Logic Device Family Data Sheet
Table 22. MAX 7000 & MAX 7000E Internal Timing Parameters
Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
MAX 7000E (-10P) MAX 7000 (-10)
MAX 7000E (-10)
Min
Max
Min
Max
t
t
t
t
t
t
t
t
t
Input pad and buffer delay
I/O input pad and buffer delay
Fast input delay
0.5
0.5
1.0
5.0
0.8
5.0
5.0
2.0
1.5
1.0
1.0
1.0
5.0
0.8
5.0
5.0
2.0
2.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
IN
IO
(2)
(2)
FIN
Shared expander delay
Parallel expander delay
Logic array delay
SEXP
PEXP
LAD
LAC
IOE
OD1
Logic control array delay
Internal output enable delay
Output buffer and pad delay
Slow slew rate = off
C1 = 35 pF
V
= 5.0 V
CCIO
t
t
t
t
t
Output buffer and pad delay
Slow slew rate = off
C1 = 35 pF (7)
C1 = 35 pF (2)
C1 = 35 pF
2.0
5.5
5.0
5.5
9.0
5.0
2.5
6.0
5.0
5.5
9.0
5.0
ns
ns
ns
ns
ns
OD2
OD3
ZX1
ZX2
ZX3
V
= 3.3 V
CCIO
Output buffer and pad delay
Slow slew rate = on
V
= 5.0 V or 3.3 V
CCIO
Output buffer enable delay
Slow slew rate = off
V
= 5.0 V
CCIO
Output buffer enable delay
Slow slew rate = off
C1 = 35 pF (7)
C1 = 35 pF (2)
C1 = 5 pF
V
= 3.3 V
CCIO
Output buffer enable delay
Slow slew rate = on
V
= 5.0 V or 3.3 V
CCIO
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Output buffer disable delay
Register setup time
Register hold time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
XZ
2.0
3.0
3.0
0.5
3.0
3.0
3.0
0.5
SU
H
Register setup time of fast input
Register hold time of fast input
Register delay
(2)
(2)
FSU
FH
2.0
2.0
5.0
5.0
1.0
3.0
3.0
1.0
11.0
1.0
1.0
5.0
5.0
1.0
3.0
3.0
1.0
11.0
RD
Combinatorial delay
Array clock delay
COMB
IC
Register enable time
Global control delay
Register preset time
Register clear time
PIA delay
EN
GLOB
PRE
CLR
PIA
LPA
Low-power adder
(8)
34
Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
Table 23. MAX 7000 & MAX 7000E External Timing Parameters
Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
MAX 7000E (-12P) MAX 7000 (-12)
MAX 7000E (-12)
Min
Max
Min
Max
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Input to non-registered output
I/O input to non-registered output
Global clock setup time
C1 = 35 pF
C1 = 35 pF
12.0
12.0
12.0
12.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PD1
PD2
SU
7.0
0.0
3.0
0.0
10.0
0.0
Global clock hold time
H
Global clock setup time of fast input (2)
Global clock hold time of fast input (2)
3.0
FSU
FH
0.0
Global clock to output delay
Global clock high time
Global clock low time
Array clock setup time
Array clock hold time
Array clock to output delay
Array clock high time
Array clock low time
C1 = 35 pF
6.0
6.0
CO1
CH
4.0
4.0
3.0
4.0
4.0
4.0
4.0
4.0
CL
ASU
AH
C1 = 35 pF
12.0
12.0
ACO1
ACH
ACL
CPPW
5.0
5.0
5.0
5.0
5.0
5.0
Minimum pulse width for clear and (3)
preset
t
t
f
Output data hold time after clock
Minimum global clock period
C1 = 35 pF (4)
1.0
1.0
ns
ns
ODH
CNT
CNT
11.0
11.0
11.0
11.0
Maximum internal global clock
frequency
(5)
90.9
90.9
MHz
t
f
Minimum array clock period
ns
ACNT
ACNT
Maximum internal array clock
frequency
(5)
(6)
90.9
90.9
MHz
f
Maximum clock frequency
125.0
125.0
MHz
MAX
Altera Corporation
35
MAX 7000 Programmable Logic Device Family Data Sheet
Table 24. MAX 7000 & MAX 7000E Internal Timing Parameters
Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
MAX 7000E (-12P) MAX 7000 (-12)
MAX 7000E (-12)
Min
Max
Min
Max
t
t
t
t
t
t
t
t
t
Input pad and buffer delay
I/O input pad and buffer delay
Fast input delay
1.0
1.0
1.0
7.0
1.0
7.0
5.0
2.0
1.0
2.0
2.0
1.0
7.0
1.0
5.0
5.0
2.0
3.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
IN
IO
(2)
(2)
FIN
Shared expander delay
Parallel expander delay
Logic array delay
SEXP
PEXP
LAD
LAC
IOE
OD1
Logic control array delay
Internal output enable delay
Output buffer and pad delay
Slow slew rate = off
C1 = 35 pF
V
= 5.0 V
CCIO
t
t
t
t
t
Output buffer and pad delay
Slow slew rate = off
C1 = 35 pF (7)
C1 = 35 pF (2)
C1 = 35 pF
2.0
5.0
4.0
7.0
ns
ns
ns
ns
ns
OD2
OD3
ZX1
ZX2
ZX3
V
= 3.3 V
CCIO
Output buffer and pad delay
Slow slew rate = on
V
= 5.0 V or 3.3 V
CCIO
Output buffer enable delay
Slow slew rate = off
6.0
6.0
V
= 5.0 V
CCIO
Output buffer enable delay
Slow slew rate = off
C1 = 35 pF (7)
C1 = 35 pF (2)
C1 = 5 pF
7.0
7.0
V
= 3.3 V
CCIO
Output buffer enable delay
Slow slew rate = on
10.0
6.0
10.0
6.0
V
= 5.0 V or 3.3 V
CCIO
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Output buffer disable delay
Register setup time
Register hold time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
XZ
1.0
6.0
4.0
0.0
4.0
4.0
2.0
2.0
SU
H
Register setup time of fast input
Register hold time of fast input
Register delay
(2)
(2)
FSU
FH
2.0
2.0
5.0
7.0
2.0
4.0
4.0
1.0
12.0
1.0
1.0
5.0
5.0
0.0
3.0
3.0
1.0
12.0
RD
Combinatorial delay
Array clock delay
COMB
IC
Register enable time
Global control delay
Register preset time
Register clear time
PIA delay
EN
GLOB
PRE
CLR
PIA
LPA
Low-power adder
(8)
36
Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
Table 25. MAX 7000 & MAX 7000E External Timing Parameters
Symbol Parameter Conditions
Note (1)
Speed Grade
-15T
Min Max Min Max Min Max
Unit
-15
-20
t
t
Input to non-registered output C1 = 35 pF
15.0
15.0
15.0
15.0
20.0
20.0
ns
ns
PD1
PD2
I/O input to non-registered
output
C1 = 35 pF
t
t
t
Global clock setup time
Global clock hold time
11.0
0.0
11.0
0.0
–
12.0
0.0
ns
ns
ns
SU
H
Global clock setup time of fast (2)
3.0
5.0
FSU
input
t
Global clock hold time of fast
input
(2)
0.0
–
0.0
ns
FH
t
t
t
t
t
t
t
t
t
Global clock to output delay
Global clock high time
Global clock low time
Array clock setup time
Array clock hold time
Array clock to output delay
Array clock high time
Array clock low time
C1 = 35 pF
8.0
8.0
12.0
20.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
CO1
CH
5.0
5.0
4.0
4.0
6.0
6.0
4.0
4.0
6.0
6.0
5.0
5.0
CL
ASU
AH
C1 = 35 pF
15.0
15.0
ACO1
ACH
ACL
CPPW
6.0
6.0
6.0
6.5
6.5
6.5
8.0
8.0
8.0
Minimum pulse width for clear (3)
and preset
t
Output data hold time after
clock
C1 = 35 pF (4)
1.0
1.0
1.0
ns
ODH
t
f
Minimum global clock period
13.0
13.0
13.0
13.0
16.0
16.0
ns
CNT
CNT
Maximum internal global clock (5)
frequency
76.9
76.9
62.5
MHz
t
f
Minimum array clock period
ns
ACNT
ACNT
Maximum internal array clock (5)
frequency
76.9
100
76.9
83.3
62.5
83.3
MHz
f
Maximum clock frequency
(6)
MHz
MAX
Altera Corporation
37
MAX 7000 Programmable Logic Device Family Data Sheet
Table 26. MAX 7000 & MAX 7000E Internal Timing Parameters
Note (1)
Symbol
Parameter
Conditions
Speed Grade
-15T
Min Max Min Max Min Max
Unit
-15
-20
t
t
t
t
t
t
t
t
t
Input pad and buffer delay
I/O input pad and buffer delay
Fast input delay
2.0
2.0
2.0
8.0
1.0
6.0
6.0
3.0
4.0
2.0
2.0
–
3.0
3.0
4.0
9.0
2.0
8.0
8.0
4.0
5.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
IN
IO
(2)
(2)
FIN
Shared expander delay
Parallel expander delay
Logic array delay
10.0
1.0
6.0
6.0
–
SEXP
PEXP
LAD
LAC
IOE
OD1
Logic control array delay
Internal output enable delay
Output buffer and pad delay
Slow slew rate = off
C1 = 35 pF
4.0
V
= 5.0 V
CCIO
t
t
t
t
t
Output buffer and pad delay
Slow slew rate = off
C1 = 35 pF (7)
C1 = 35 pF (2)
C1 = 35 pF
5.0
8.0
6.0
–
–
6.0
9.0
ns
ns
ns
ns
ns
OD2
OD3
ZX1
ZX2
ZX3
V
= 3.3 V
CCIO
Output buffer and pad delay
Slow slew rate = on
V
= 5.0 V or 3.3 V
CCIO
Output buffer enable delay
Slow slew rate = off
6.0
–
10.0
11.0
14.0
10.0
V
= 5.0 V
CCIO
Output buffer enable delay
Slow slew rate = off
C1 = 35 pF (7)
C1 = 35 pF (2)
C1 = 5 pF
7.0
10.0
6.0
V
= 3.3 V
CCIO
Output buffer enable delay
Slow slew rate = on
–
V
= 5.0 V or 3.3 V
CCIO
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Output buffer disable delay
Register setup time
6.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
XZ
4.0
4.0
2.0
2.0
4.0
4.0
–
4.0
5.0
4.0
3.0
SU
Register hold time
H
Register setup time of fast input (2)
Register hold time of fast input (2)
Register delay
FSU
FH
–
1.0
1.0
6.0
6.0
1.0
4.0
4.0
2.0
13.0
1.0
1.0
6.0
6.0
1.0
4.0
4.0
2.0
15.0
1.0
1.0
8.0
8.0
3.0
4.0
4.0
3.0
15.0
RD
Combinatorial delay
Array clock delay
COMB
IC
Register enable time
Global control delay
Register preset time
Register clear time
EN
GLOB
PRE
CLR
PIA
LPA
PIA delay
Low-power adder
(8)
38
Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
Notes to tables:
(1) These values are specified under the recommended operating conditions shown in Table 14. See Figure 13 for more
information on switching waveforms.
(2) This parameter applies to MAX 7000E devices only.
(3) This minimum pulse width for preset and clear applies for both global clear and array controls. The t
parameter
LPA
must be added to this minimum width if the clear or reset signal incorporates the t
parameter into the signal
LAD
path.
(4) This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This
parameter applies for both global and array clocking.
(5) These parameters are measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB.
(6) The f
(7) Operating conditions: V
values represent the highest frequency for pipelined data.
MAX
= 3.3 V ± 10% for commercial and industrial use.
CCIO
(8) The t
parameter must be added to the t
, t
, t , t , t
, t
, and t
parameters for macrocells
CPPW
LPA
LAD LAC IC EN SEXP ACL
running in the low-power mode.
Tables 27 and 28 show the EPM7032S AC operating conditions.
Table 27. EPM7032S External Timing Parameters (Part 1 of 2)
Note (1)
Symbol
Parameter
Conditions
Speed Grade
-6 -7
Min Max Min Max Min Max Min Max
Unit
-5
-10
t
t
Input to non-registered output C1 = 35 pF
5.0
5.0
6.0
6.0
7.5
7.5
10.0
10.0
ns
ns
PD1
PD2
I/O input to non-registered
output
C1 = 35 pF
t
t
t
Global clock setup time
Global clock hold time
2.9
0.0
2.5
4.0
0.0
2.5
5.0
0.0
2.5
7.0
0.0
3.0
ns
ns
ns
SU
H
Global clock setup time of fast
input
FSU
t
Global clock hold time of fast
input
0.0
0.0
0.0
0.5
ns
FH
t
t
t
t
t
t
t
t
t
Global clock to output delay
Global clock high time
Global clock low time
Array clock setup time
Array clock hold time
Array clock to output delay
Array clock high time
Array clock low time
C1 = 35 pF
3.2
5.4
3.5
6.6
4.3
8.2
5.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
CO1
CH
2.0
2.0
0.7
1.8
2.5
2.5
0.9
2.1
3.0
3.0
1.1
2.7
4.0
4.0
2.0
3.0
CL
ASU
AH
C1 = 35 pF
10.0
ACO1
ACH
ACL
CPPW
2.5
2.5
2.5
2.5
2.5
2.5
3.0
3.0
3.0
4.0
4.0
4.0
Minimum pulse width for clear (2)
and preset
t
Output data hold time after
clock
C1 = 35 pF (3) 1.0
1.0
1.0
1.0
ns
ODH
t
f
Minimum global clock period
5.7
5.7
7.0
7.0
8.6
8.6
10.0
10.0
ns
CNT
CNT
Maximum internal global clock (4)
frequency
175.4
142.9
116.3
100.0
MHz
t
Minimum array clock period
ns
ACNT
Altera Corporation
39
MAX 7000 Programmable Logic Device Family Data Sheet
Table 27. EPM7032S External Timing Parameters (Part 2 of 2)
Note (1)
Symbol
Parameter
Conditions
Speed Grade
-6 -7
Min Max Min Max Min Max Min Max
Unit
-5
-10
f
f
Maximum internal array clock (4)
frequency
175.4
142.9
116.3
100.0
MHz
MHz
ACNT
MAX
Maximum clock frequency
(5)
250.0
200.0
166.7
125.0
Table 28. EPM7032S Internal Timing Parameters
Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
-5
-6
-7
-10
Min Max Min Max Min Max Min Max
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Input pad and buffer delay
I/O input pad and buffer delay
Fast input delay
0.2
0.2
2.2
3.1
0.9
2.6
2.5
0.7
0.2
0.7
5.2
4.0
4.5
9.0
4.0
0.2
0.2
2.1
3.8
1.1
3.3
3.3
0.8
0.3
0.8
5.3
4.0
4.5
9.0
4.0
0.3
0.3
2.5
4.6
1.4
4.0
4.0
1.0
0.4
0.9
5.4
4.0
4.5
9.0
4.0
0.5
0.5
1.0
5.0
0.8
5.0
5.0
2.0
1.5
2.0
5.5
5.0
5.5
9.0
5.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
IN
IO
FIN
SEXP
PEXP
LAD
LAC
IOE
OD1
OD2
OD3
ZX1
ZX2
ZX3
XZ
Shared expander delay
Parallel expander delay
Logic array delay
Logic control array delay
Internal output enable delay
Output buffer and pad delay C1 = 35 pF
Output buffer and pad delay C1 = 35 pF (6)
Output buffer and pad delay C1 = 35 pF
Output buffer enable delay
Output buffer enable delay
Output buffer enable delay
Output buffer disable delay
Register setup time
C1 = 35 pF
C1 = 35 pF (6)
C1 = 35 pF
C1 = 5 pF
0.8
1.7
1.9
1.0
2.0
1.8
1.3
2.5
1.7
2.0
3.0
3.0
SU
Register hold time
H
Register setup time of fast
input
FSU
t
Register hold time of fast
input
0.6
0.7
0.8
0.5
ns
FH
t
t
t
t
t
t
t
Register delay
1.2
0.9
2.7
2.6
1.6
2.0
2.0
1.6
1.1
3.4
3.3
1.4
2.4
2.4
1.9
1.4
4.2
4.0
1.7
3.0
3.0
2.0
2.0
5.0
5.0
1.0
3.0
3.0
ns
ns
ns
ns
ns
ns
ns
RD
Combinatorial delay
Array clock delay
Register enable time
Global control delay
Register preset time
Register clear time
COMB
IC
EN
GLOB
PRE
CLR
40
Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
Table 28. EPM7032S Internal Timing Parameters
Symbol Parameter Conditions
Note (1)
Speed Grade
-6 -7
Min Max Min Max Min Max Min Max
Unit
-5
-10
t
PIA delay
Low-power adder
(7)
(8)
1.1
1.1
1.4
1.0
ns
ns
PIA
t
12.0
10.0
10.0
11.0
LPA
Notes to tables:
(1) These values are specified under the recommended operating conditions shown in Table 14. See Figure 13 for more
information on switching waveforms.
(2) This minimum pulse width for preset and clear applies for both global clear and array controls. The t
parameter
LPA
must be added to this minimum width if the clear or reset signal incorporates the t
parameter into the signal
LAD
path.
(3) This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This
parameter applies for both global and array clocking.
(4) These parameters are measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB.
(5) The f
(6) Operating conditions: V
values represent the highest frequency for pipelined data.
MAX
= 3.3 V ± 10% for commercial and industrial use.
CCIO
(7) For EPM7064S-5, EPM7064S-6, EPM7128S-6, EPM7160S-6, EPM7160S-7, EPM7192S-7, and EPM7256S-7 devices,
these values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these
devices, add an additional 0.1 ns to the PIA timing value.
(8) The t
parameter must be added to the t
, t
, t , t , t
, t
, and t
parameters for macrocells
LPA
LAD LAC IC EN SEXP ACL
CPPW
running in the low-power mode.
Tables 29 and 30 show the EPM7064S AC operating conditions.
Table 29. EPM7064S External Timing Parameters (Part 1 of 2)
Note (1)
Symbol
Parameter
Conditions
Speed Grade
-6 -7
Min Max Min Max Min Max Min Max
Unit
-5
-10
t
t
Input to non-registered output C1 = 35 pF
5.0
5.0
6.0
6.0
7.5
7.5
10.0
10.0
ns
ns
PD1
PD2
I/O input to non-registered
output
C1 = 35 pF
t
t
t
Global clock setup time
Global clock hold time
2.9
0.0
2.5
3.6
0.0
2.5
6.0
0.0
3.0
7.0
0.0
3.0
ns
ns
ns
SU
H
Global clock setup time of fast
input
FSU
t
Global clock hold time of fast
input
0.0
0.0
0.5
0.5
ns
FH
t
t
t
t
t
Global clock to output delay
Global clock high time
Global clock low time
Array clock setup time
Array clock hold time
C1 = 35 pF
3.2
4.0
4.5
5.0
ns
ns
ns
ns
ns
CO1
CH
2.0
2.0
0.7
1.8
2.5
2.5
0.9
2.1
3.0
3.0
3.0
2.0
4.0
4.0
2.0
3.0
CL
ASU
AH
Altera Corporation
41
MAX 7000 Programmable Logic Device Family Data Sheet
Table 29. EPM7064S External Timing Parameters (Part 2 of 2)
Note (1)
Symbol
Parameter
Conditions
Speed Grade
-6 -7
Min Max Min Max Min Max Min Max
Unit
-5
-10
t
t
t
t
Array clock to output delay
Array clock high time
Array clock low time
C1 = 35 pF
5.4
6.7
7.5
10.0
ns
ns
ns
ns
ACO1
ACH
2.5
2.5
2.5
2.5
2.5
2.5
3.0
3.0
3.0
4.0
4.0
4.0
ACL
Minimum pulse width for clear (2)
CPPW
and preset
t
Output data hold time after
clock
C1 = 35 pF (3)
1.0
1.0
1.0
1.0
ns
ODH
t
f
Minimum global clock period
5.7
5.7
7.1
7.1
8.0
8.0
10.0
10.0
ns
CNT
CNT
Maximum internal global clock (4)
frequency
175.4
140.8
125.0
100.0
MHz
t
f
Minimum array clock period
ns
ACNT
ACNT
Maximum internal array clock (4)
frequency
175.4
250.0
140.8
200.0
125.0
166.7
100.0
125.0
MHz
f
Maximum clock frequency
(5)
MHz
MAX
Table 30. EPM7064S Internal Timing Parameters (Part 1 of 2)
Note (1)
Symbol
Parameter
Conditions
Speed Grade
-6 -7
Min Max Min Max Min Max Min Max
Unit
-5
-10
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Input pad and buffer delay
I/O input pad and buffer delay
Fast input delay
0.2
0.2
2.2
3.1
0.9
2.6
2.5
0.7
0.2
0.7
5.2
4.0
4.5
9.0
4.0
0.2
0.2
2.6
3.8
1.1
3.2
3.2
0.8
0.3
0.8
5.3
4.0
4.5
9.0
4.0
0.5
0.5
1.0
4.0
0.8
3.0
3.0
2.0
2.0
2.5
7.0
4.0
4.5
9.0
4.0
0.5
0.5
1.0
5.0
0.8
5.0
5.0
2.0
1.5
2.0
5.5
5.0
5.5
9.0
5.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
IN
IO
FIN
SEXP
PEXP
LAD
LAC
IOE
OD1
OD2
OD3
ZX1
ZX2
ZX3
XZ
Shared expander delay
Parallel expander delay
Logic array delay
Logic control array delay
Internal output enable delay
Output buffer and pad delay C1 = 35 pF
Output buffer and pad delay C1 = 35 pF (6)
Output buffer and pad delay C1 = 35 pF
Output buffer enable delay
Output buffer enable delay
Output buffer enable delay
Output buffer disable delay
Register setup time
C1 = 35 pF
C1 = 35 pF (6)
C1 = 35 pF
C1 = 5 pF
0.8
1.7
1.0
2.0
3.0
2.0
2.0
3.0
SU
Register hold time
H
42
Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
Table 30. EPM7064S Internal Timing Parameters (Part 2 of 2)
Note (1)
Symbol
Parameter
Conditions
Speed Grade
-6 -7
Min Max Min Max Min Max Min Max
Unit
-5
-10
t
Register setup time of fast
input
1.9
1.8
3.0
3.0
ns
ns
FSU
t
Register hold time of fast
input
0.6
0.7
0.5
0.5
FH
t
t
t
t
t
t
t
t
t
Register delay
1.2
0.9
2.7
2.6
1.6
2.0
2.0
1.1
12.0
1.6
1.0
3.3
3.2
1.9
2.4
2.4
1.3
11.0
1.0
1.0
3.0
3.0
1.0
2.0
2.0
1.0
10.0
2.0
2.0
5.0
5.0
1.0
3.0
3.0
1.0
11.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
RD
Combinatorial delay
Array clock delay
Register enable time
Global control delay
Register preset time
Register clear time
PIA delay
COMB
IC
EN
GLOB
PRE
CLR
PIA
(7)
(8)
Low-power adder
LPA
Notes to tables:
(1) These values are specified under the recommended operating conditions shown in Table 14. See Figure 13 for more
information on switching waveforms.
(2) This minimum pulse width for preset and clear applies for both global clear and array controls. The t
parameter
LPA
must be added to this minimum width if the clear or reset signal incorporates the t
parameter into the signal
LAD
path.
(3) This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This
parameter applies for both global and array clocking.
(4) These parameters are measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB.
(5) The f
(6) Operating conditions: V
values represent the highest frequency for pipelined data.
MAX
= 3.3 V ± 10% for commercial and industrial use.
CCIO
(7) For EPM7064S-5, EPM7064S-6, EPM7128S-6, EPM7160S-6, EPM7160S-7, EPM7192S-7, and EPM7256S-7 devices,
these values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these
devices, add an additional 0.1 ns to the PIA timing value.
(8) The t
parameter must be added to the t
, t
, t , t , t
, t
, and t
parameters for macrocells
LPA
LAD LAC IC EN SEXP ACL
CPPW
running in the low-power mode.
Altera Corporation
43
MAX 7000 Programmable Logic Device Family Data Sheet
Tables 31 and 32 show the EPM7128S AC operating conditions.
Table 31. EPM7128S External Timing Parameters
Symbol Parameter Conditions
Note (1)
Speed Grade
-7 -10
Unit
-6
-15
Min Max Min Max Min Max Min Max
t
t
Input to non-registered output C1 = 35 pF
6.0
6.0
7.5
7.5
10.0
10.0
15.0
15.0
ns
ns
PD1
PD2
I/O input to non-registered
output
C1 = 35 pF
t
t
t
Global clock setup time
Global clock hold time
3.4
0.0
2.5
6.0
0.0
3.0
7.0
0.0
3.0
11.0
0.0
ns
ns
ns
SU
H
Global clock setup time of fast
input
3.0
FSU
t
Global clock hold time of fast
input
0.0
0.5
0.5
0.0
ns
FH
t
t
t
t
t
t
t
t
t
Global clock to output delay
Global clock high time
Global clock low time
Array clock setup time
Array clock hold time
Array clock to output delay
Array clock high time
Array clock low time
C1 = 35 pF
4.0
6.5
4.5
7.5
5.0
8.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
CO1
CH
3.0
3.0
0.9
1.8
3.0
3.0
3.0
2.0
4.0
4.0
2.0
5.0
5.0
5.0
4.0
4.0
CL
ASU
AH
C1 = 35 pF
10.0
15.0
ACO1
ACH
ACL
CPPW
3.0
3.0
3.0
3.0
3.0
3.0
4.0
4.0
4.0
6.0
6.0
6.0
Minimum pulse width for clear (2)
and preset
t
Output data hold time after
clock
C1 = 35 pF (3)
1.0
1.0
1.0
1.0
ns
ODH
t
f
Minimum global clock period
6.8
6.8
8.0
8.0
10.0
10.0
13.0
13.0
ns
CNT
CNT
Maximum internal global clock (4)
frequency
147.1
125.0
100.0
76.9
MHz
t
f
Minimum array clock period
ns
ACNT
ACNT
Maximum internal array clock (4)
frequency
147.1
166.7
125.0
166.7
100.0
125.0
76.9
MHz
f
Maximum clock frequency
(5)
100.0
MHz
MAX
44
Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
Table 32. EPM7128S Internal Timing Parameters
Note (1)
Symbol
Parameter
Conditions
Speed Grade
-7 -10
Min Max Min Max Min Max Min Max
Unit
-6
-15
t
Input pad and buffer delay
I/O input pad and buffer delay
Fast input delay
0.2
0.2
2.6
3.7
1.1
3.0
3.0
0.7
0.4
0.9
5.4
4.0
4.5
9.0
4.0
0.5
0.5
1.0
4.0
0.8
3.0
3.0
2.0
2.0
2.5
7.0
4.0
4.5
9.0
4.0
0.5
0.5
1.0
5.0
0.8
5.0
5.0
2.0
1.5
2.0
5.5
5.0
5.5
9.0
5.0
2.0
2.0
2.0
8.0
1.0
6.0
6.0
3.0
4.0
5.0
8.0
6.0
7.0
10.0
6.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
IN
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
IO
FIN
SEXP
PEXP
LAD
LAC
IOE
OD1
OD2
OD3
ZX1
ZX2
ZX3
XZ
Shared expander delay
Parallel expander delay
Logic array delay
Logic control array delay
Internal output enable delay
Output buffer and pad delay C1 = 35 pF
Output buffer and pad delay C1 = 35 pF (6)
Output buffer and pad delay C1 = 35 pF
Output buffer enable delay
Output buffer enable delay
Output buffer enable delay
Output buffer disable delay
Register setup time
C1 = 35 pF
C1 = 35 pF (6)
C1 = 35 pF
C1 = 5 pF
1.0
1.7
1.9
3.0
2.0
3.0
2.0
5.0
3.0
4.0
4.0
2.0
SU
Register hold time
H
Register setup time of fast
input
FSU
t
Register hold time of fast
input
0.6
0.5
0.5
1.0
ns
FH
t
t
t
t
t
t
t
t
t
Register delay
1.4
1.0
3.1
3.0
2.0
2.4
2.4
1.4
11.0
1.0
1.0
3.0
3.0
1.0
2.0
2.0
1.0
10.0
2.0
2.0
5.0
5.0
1.0
3.0
3.0
1.0
11.0
1.0
1.0
6.0
6.0
1.0
4.0
4.0
2.0
13.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
RD
Combinatorial delay
Array clock delay
Register enable time
Global control delay
Register preset time
Register clear time
PIA delay
COMB
IC
EN
GLOB
PRE
CLR
PIA
(7)
(8)
Low-power adder
LPA
Altera Corporation
45
MAX 7000 Programmable Logic Device Family Data Sheet
Notes to tables:
(1) These values are specified under the recommended operating conditions shown in Table 14. See Figure 13 for more
information on switching waveforms.
(2) This minimum pulse width for preset and clear applies for both global clear and array controls. The t
parameter
LPA
must be added to this minimum width if the clear or reset signal incorporates the t
parameter into the signal
LAD
path.
(3) This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This
parameter applies for both global and array clocking.
(4) These parameters are measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB.
(5) The f
(6) Operating conditions: V
values represent the highest frequency for pipelined data.
MAX
= 3.3 V ± 10% for commercial and industrial use.
CCIO
(7) For EPM7064S-5, EPM7064S-6, EPM7128S-6, EPM7160S-6, EPM7160S-7, EPM7192S-7, and EPM7256S-7 devices,
these values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these
devices, add an additional 0.1 ns to the PIA timing value.
(8) The t
parameter must be added to the t
, t
, t , t , t
, t
, and t
parameters for macrocells
LPA
LAD LAC IC EN SEXP ACL
CPPW
running in the low-power mode.
Tables 33 and 34 show the EPM7160S AC operating conditions.
Table 33. EPM7160S External Timing Parameters (Part 1 of 2)
Note (1)
Symbol
Parameter
Conditions
Speed Grade
-7 -10
Min Max Min Max Min Max Min Max
Unit
-6
-15
t
t
Input to non-registered output C1 = 35 pF
6.0
6.0
7.5
7.5
10.0
10.0
15.0
15.0
ns
ns
PD1
PD2
I/O input to non-registered
output
C1 = 35 pF
t
t
t
Global clock setup time
Global clock hold time
3.4
0.0
2.5
4.2
0.0
3.0
7.0
0.0
3.0
11.0
0.0
ns
ns
ns
SU
H
Global clock setup time of fast
input
3.0
FSU
t
Global clock hold time of fast
input
0.0
0.0
0.5
0.0
ns
FH
t
t
t
t
t
t
t
t
t
Global clock to output delay
Global clock high time
Global clock low time
Array clock setup time
Array clock hold time
Array clock to output delay
Array clock high time
Array clock low time
C1 = 35 pF
3.9
6.4
4.8
7.9
5
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
CO1
CH
3.0
3.0
0.9
1.7
3.0
3.0
1.1
2.1
4.0
4.0
2.0
3.0
5.0
5.0
4.0
4.0
CL
ASU
AH
C1 = 35 pF
10.0
15.0
ACO1
ACH
ACL
CPPW
3.0
3.0
2.5
3.0
3.0
3.0
4.0
4.0
4.0
6.0
6.0
6.0
Minimum pulse width for clear (2)
and preset
t
Output data hold time after
clock
C1 = 35 pF (3)
1.0
1.0
1.0
1.0
ns
ODH
t
f
Minimum global clock period
6.7
8.2
10.0
13.0
ns
CNT
CNT
Maximum internal global clock (4)
149.3
122.0
100.0
76.9
MHz
frequency
46
Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
Table 33. EPM7160S External Timing Parameters (Part 2 of 2)
Note (1)
Symbol
Parameter
Conditions
Speed Grade
-7 -10
Min Max Min Max Min Max Min Max
Unit
-6
-15
t
f
Minimum array clock period
6.7
8.2
10.0
13.0
ns
ACNT
ACNT
Maximum internal array clock (4)
frequency
149.3
166.7
122.0
166.7
100.0
125.0
76.9
MHz
f
Maximum clock frequency
(5)
100.0
MHz
MAX
Table 34. EPM7160S Internal Timing Parameters (Part 1 of 2)
Note (1)
Symbol
Parameter
Conditions
Speed Grade
-7 -10
Min Max Min Max Min Max Min Max
Unit
-6
-15
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Input pad and buffer delay
I/O input pad and buffer delay
Fast input delay
0.2
0.2
2.6
3.6
1.0
2.8
2.8
0.7
0.4
0.9
5.4
4.0
4.5
9.0
4.0
0.3
0.3
3.2
4.3
1.3
3.4
3.4
0.9
0.5
1.0
5.5
4.0
4.5
9.0
4.0
0.5
0.5
1.0
5.0
0.8
5.0
5.0
2.0
1.5
2.0
5.5
5.0
5.5
9.0
5.0
2.0
2.0
2.0
8.0
1.0
6.0
6.0
3.0
4.0
5.0
8.0
6.0
7.0
10.0
6.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
IN
IO
FIN
SEXP
PEXP
LAD
LAC
IOE
OD1
OD2
OD3
ZX1
ZX2
ZX3
XZ
Shared expander delay
Parallel expander delay
Logic array delay
Logic control array delay
Internal output enable delay
Output buffer and pad delay C1 = 35 pF
Output buffer and pad delay C1 = 35 pF (6)
Output buffer and pad delay C1 = 35 pF
Output buffer enable delay
Output buffer enable delay
Output buffer enable delay
Output buffer disable delay
Register setup time
C1 = 35 pF
C1 = 35 pF (6)
C1 = 35 pF
C1 = 5 pF
1.0
1.6
1.9
1.2
2.0
2.2
2.0
3.0
3.0
4.0
4.0
2.0
SU
Register hold time
H
Register setup time of fast
input
FSU
t
Register hold time of fast
input
0.6
0.8
0.5
1.0
ns
FH
t
t
t
t
t
t
Register delay
1.3
1.0
2.9
2.8
2.0
2.4
1.6
1.3
3.5
3.4
2.4
3.0
2.0
2.0
5.0
5.0
1.0
3.0
1.0
1.0
6.0
6.0
1.0
4.0
ns
ns
ns
ns
ns
ns
RD
Combinatorial delay
Array clock delay
Register enable time
Global control delay
Register preset time
COMB
IC
EN
GLOB
PRE
Altera Corporation
47
MAX 7000 Programmable Logic Device Family Data Sheet
Table 34. EPM7160S Internal Timing Parameters (Part 2 of 2)
Note (1)
Symbol
Parameter
Conditions
Speed Grade
-7 -10
Min Max Min Max Min Max Min Max
Unit
-6
-15
t
Register clear time
PIA delay
2.4
1.6
3.0
2.0
3.0
1.0
4.0
2.0
ns
ns
ns
CLR
t
t
(7)
(8)
PIA
Low-power adder
11.0
10.0
11.0
13.0
LPA
Notes to tables:
(1) These values are specified under the recommended operating conditions shown in Table 14. See Figure 13 for more
information on switching waveforms.
(2) This minimum pulse width for preset and clear applies for both global clear and array controls. The t
parameter
LPA
must be added to this minimum width if the clear or reset signal incorporates the t
parameter into the signal
LAD
path.
(3) This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This
parameter applies for both global and array clocking.
(4) These parameters are measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB.
(5) The f
(6) Operating conditions:
values represent the highest frequency for pipelined data.
MAX
V
= 3.3 V ± 10% for commercial and industrial use.
CCIO
(7) For EPM7064S-5, EPM7064S-6, EPM7128S-6, EPM7160S-6, EPM7160S-7, EPM7192S-7, and EPM7256S-7 devices,
these values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these
devices, add an additional 0.1 ns to the PIA timing value.
(8) The t
parameter must be added to the t
, t
, t , t , t
, t
, and t
parameters for macrocells
LPA
LAD LAC IC EN SEXP ACL
CPPW
running in the low-power mode.
Tables 35 and 36 show the EPM7192S AC operating conditions.
Table 35. EPM7192S External Timing Parameters (Part 1 of 2)
Symbol Parameter Conditions
Note (1)
Speed Grade
-10
Min Max Min Max Min Max
Unit
-7
-15
t
t
Input to non-registered output C1 = 35 pF
7.5
7.5
10.0
10.0
15.0
15.0
ns
ns
PD1
PD2
I/O input to non-registered
output
C1 = 35 pF
t
t
t
Global clock setup time
Global clock hold time
4.1
0.0
3.0
7.0
0.0
3.0
11.0
0.0
ns
ns
ns
SU
H
Global clock setup time of fast
input
3.0
FSU
t
Global clock hold time of fast
input
0.0
0.5
0.0
ns
FH
t
t
t
t
Global clock to output delay
Global clock high time
Global clock low time
Array clock setup time
C1 = 35 pF
4.7
5.0
8.0
ns
ns
ns
ns
CO1
CH
3.0
3.0
1.0
4.0
4.0
2.0
5.0
5.0
4.0
CL
ASU
48
Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
Table 35. EPM7192S External Timing Parameters (Part 2 of 2)
Note (1)
Symbol
Parameter
Conditions
Speed Grade
-10
Min Max Min Max Min Max
Unit
-7
-15
t
t
t
t
t
Array clock hold time
Array clock to output delay
Array clock high time
Array clock low time
1.8
3.0
4.0
ns
ns
ns
ns
ns
AH
C1 = 35 pF
7.8
10.0
15.0
ACO1
ACH
ACL
3.0
3.0
3.0
4.0
4.0
4.0
6.0
6.0
6.0
Minimum pulse width for clear (2)
CPPW
and preset
t
Output data hold time after
clock
C1 = 35 pF (3)
1.0
1.0
1.0
ns
ODH
t
f
Minimum global clock period
8.0
8.0
10.0
10.0
13.0
13.0
ns
CNT
CNT
Maximum internal global clock (4)
frequency
125.0
100.0
76.9
MHz
t
f
Minimum array clock period
ns
ACNT
ACNT
Maximum internal array clock (4)
frequency
125.0
166.7
100.0
125.0
76.9
MHz
f
Maximum clock frequency
(5)
100.0
MHz
MAX
Table 36. EPM7192S Internal Timing Parameters (Part 1 of 2)
Note (1)
Symbol
Parameter
Conditions
Speed Grade
-10
Unit
-7
-15
Min Max Min Max Min Max
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Input pad and buffer delay
I/O input pad and buffer delay
Fast input delay
0.3
0.3
3.2
4.2
1.2
3.1
3.1
0.9
0.5
1.0
5.5
4.0
4.5
9.0
4.0
0.5
0.5
1.0
5.0
0.8
5.0
5.0
2.0
1.5
2.0
5.5
5.0
5.5
9.0
5.0
2.0
2.0
2.0
8.0
1.0
6.0
6.0
3.0
4.0
5.0
7.0
6.0
7.0
10.0
6.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
IN
IO
FIN
Shared expander delay
Parallel expander delay
Logic array delay
SEXP
PEXP
LAD
LAC
IOE
OD1
OD2
OD3
ZX1
ZX2
ZX3
XZ
Logic control array delay
Internal output enable delay
Output buffer and pad delay C1 = 35 pF
Output buffer and pad delay C1 = 35 pF (6)
Output buffer and pad delay C1 = 35 pF
Output buffer enable delay
Output buffer enable delay
Output buffer enable delay
Output buffer disable delay
Register setup time
C1 = 35 pF
C1 = 35 pF (6)
C1 = 35 pF
C1 = 5 pF
1.1
2.0
4.0
SU
Altera Corporation
49
MAX 7000 Programmable Logic Device Family Data Sheet
Table 36. EPM7192S Internal Timing Parameters (Part 2 of 2)
Note (1)
Symbol
Parameter
Conditions
Speed Grade
-10
Min Max Min Max Min Max
Unit
-7
-15
t
Register hold time
1.7
2.3
3.0
3.0
4.0
2.0
ns
ns
H
t
Register setup time of fast
input
FSU
t
Register hold time of fast
input
0.7
0.5
1.0
ns
FH
t
t
t
t
t
t
t
t
t
Register delay
1.4
1.2
3.2
3.1
2.5
2.7
2.7
2.4
10.0
2.0
2.0
5.0
5.0
1.0
3.0
3.0
1.0
11.0
1.0
1.0
6.0
6.0
1.0
4.0
4.0
2.0
13.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
RD
Combinatorial delay
Array clock delay
Register enable time
Global control delay
Register preset time
Register clear time
PIA delay
COMB
IC
EN
GLOB
PRE
CLR
PIA
(7)
(8)
Low-power adder
LPA
Notes to tables:
(1) These values are specified under the recommended operating conditions shown in Table 14. See Figure 13 for more
information on switching waveforms.
(2) This minimum pulse width for preset and clear applies for both global clear and array controls. The t
parameter
LPA
must be added to this minimum width if the clear or reset signal incorporates the t
parameter into the signal
LAD
path.
(3) This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This
parameter applies for both global and array clocking.
(4) These parameters are measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB.
(5) The f
(6) Operating conditions: V
values represent the highest frequency for pipelined data.
MAX
= 3.3 V ± 10% for commercial and industrial use.
CCIO
(7) For EPM7064S-5, EPM7064S-6, EPM7128S-6, EPM7160S-6, EPM7160S-7, EPM7192S-7, and EPM7256S-7 devices,
these values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these
devices, add an additional 0.1 ns to the PIA timing value.
(8) The t
parameter must be added to the t
, t
, t , t , t
, t
, and t parameters for macrocells
LPA
LAD LAC IC EN SEXP ACL
CPPW
running in the low-power mode.
50
Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
Tables 37 and 38 show the EPM7256S AC operating conditions.
Table 37. EPM7256S External Timing Parameters
Symbol Parameter Conditions
Note (1)
Speed Grade
-10
Unit
-7
-15
Min Max Min Max Min Max
t
t
Input to non-registered output C1 = 35 pF
7.5
7.5
10.0
10.0
15.0
15.0
ns
ns
PD1
PD2
I/O input to non-registered
output
C1 = 35 pF
t
t
t
Global clock setup time
Global clock hold time
3.9
0.0
3.0
7.0
0.0
3.0
11.0
0.0
ns
ns
ns
SU
H
Global clock setup time of fast
input
3.0
FSU
t
Global clock hold time of fast
input
0.0
0.5
0.0
ns
FH
t
t
t
t
t
t
t
t
t
Global clock to output delay
Global clock high time
Global clock low time
Array clock setup time
Array clock hold time
Array clock to output delay
Array clock high time
Array clock low time
C1 = 35 pF
4.7
7.8
5.0
8.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
CO1
CH
3.0
3.0
0.8
1.9
4.0
4.0
2.0
3.0
5.0
5.0
4.0
4.0
CL
ASU
AH
C1 = 35 pF
10.0
15.0
ACO1
ACH
ACL
CPPW
3.0
3.0
3.0
4.0
4.0
4.0
6.0
6.0
6.0
Minimum pulse width for clear (2)
and preset
t
Output data hold time after
clock
C1 = 35 pF (3)
1.0
1.0
1.0
ns
ODH
t
f
Minimum global clock period
7.8
7.8
10.0
10.0
13.0
13.0
ns
CNT
CNT
Maximum internal global clock (4)
frequency
128.2
100.0
76.9
MHz
t
f
Minimum array clock period
ns
ACNT
ACNT
Maximum internal array clock (4)
frequency
128.2
166.7
100.0
125.0
76.9
MHz
f
Maximum clock frequency
(5)
100.0
MHz
MAX
Altera Corporation
51
MAX 7000 Programmable Logic Device Family Data Sheet
Table 38. EPM7256S Internal Timing Parameters
Note (1)
Symbol
Parameter
Conditions
Speed Grade
-10
Unit
-7
-15
Min Max Min Max Min Max
t
Input pad and buffer delay
I/O input pad and buffer delay
Fast input delay
0.3
0.3
3.4
3.9
1.1
2.6
2.6
0.8
0.5
1.0
5.5
4.0
4.5
9.0
4.0
0.5
0.5
1.0
5.0
0.8
5.0
5.0
2.0
1.5
2.0
5.5
5.0
5.5
9.0
5.0
2.0
2.0
2.0
8.0
1.0
6.0
6.0
3.0
4.0
5.0
8.0
6.0
7.0
10.0
6.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
IN
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
IO
FIN
SEXP
PEXP
LAD
LAC
IOE
OD1
OD2
OD3
ZX1
ZX2
ZX3
XZ
Shared expander delay
Parallel expander delay
Logic array delay
Logic control array delay
Internal output enable delay
Output buffer and pad delay C1 = 35 pF
Output buffer and pad delay C1 = 35 pF (6)
Output buffer and pad delay C1 = 35 pF
Output buffer enable delay
Output buffer enable delay
Output buffer enable delay
Output buffer disable delay
Register setup time
C1 = 35 pF
C1 = 35 pF (6)
C1 = 35 pF
C1 = 5 pF
1.1
1.6
2.4
2.0
3.0
3.0
4.0
4.0
2.0
SU
Register hold time
H
Register setup time of fast
input
FSU
t
Register hold time of fast
input
0.6
0.5
1.0
ns
FH
t
t
t
t
t
t
t
t
t
Register delay
1.1
1.1
2.9
2.6
2.8
2.7
2.7
3.0
10.0
2.0
2.0
5.0
5.0
1.0
3.0
3.0
1.0
11.0
1.0
1.0
6.0
6.0
1.0
4.0
4.0
2.0
13.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
RD
Combinatorial delay
Array clock delay
Register enable time
Global control delay
Register preset time
Register clear time
PIA delay
COMB
IC
EN
GLOB
PRE
CLR
PIA
(7)
(8)
Low-power adder
LPA
52
Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
Notes to tables:
(1) These values are specified under the recommended operating conditions shown in Table 14. See Figure 13 for more
information on switching waveforms.
(2) This minimum pulse width for preset and clear applies for both global clear and array controls. The t
parameter
LPA
must be added to this minimum width if the clear or reset signal incorporates the t
parameter into the signal
LAD
path.
(3) This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This
parameter applies for both global and array clocking.
(4) These parameters are measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB.
(5) The f
(6) Operating conditions: V
values represent the highest frequency for pipelined data.
MAX
= 3.3 V ± 10% for commercial and industrial use.
CCIO
(7) For EPM7064S-5, EPM7064S-6, EPM7128S-6, EPM7160S-6, EPM7160S-7, EPM7192S-7, and EPM7256S-7 devices,
these values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these
devices, add an additional 0.1 ns to the PIA timing value.
(8) The t
parameter must be added to the t
, t
, t , t , t
, t
, and t
parameters for macrocells
LPA
LAD LAC IC EN SEXP ACL
CPPW
running in the low-power mode.
Supply power (P) versus frequency (fMAX in MHz) for MAX 7000 devices
is calculated with the following equation:
Power
Consumption
P = PINT + PIO = ICCINT × VCC + PIO
The PIO value, which depends on the device output load characteristics
and switching frequency, can be calculated using the guidelines given in
Application Note 74 (Evaluating Power for Altera Devices).
The ICCINT value, which depends on the switching frequency and the
application logic, is calculated with the following equation:
ICCINT
=
A × MCTON + B × (MCDEV – MCTON) + C × MCUSED × fMAX × togLC
The parameters in this equation are shown below:
MCTON
=
Number of macrocells with the Turbo Bit option turned on,
as reported in the MAX+PLUS II Report File (.rpt)
Number of macrocells in the device
Total number of macrocells in the design, as reported
in the MAX+PLUS II Report File (.rpt)
Highest clock frequency to the device
Average ratio of logic cells toggling at each clock
(typically 0.125)
MCDEV
MCUSED
=
=
fMAX
togLC
=
=
A, B, C
=
Constants, shown in Table 39
Altera Corporation
53
MAX 7000 Programmable Logic Device Family Data Sheet
Table 39. MAX 7000 ICC Equation Constants
Device
A
B
C
EPM7032
1.87
1.63
1.63
1.17
1.17
1.17
1.17
0.93
0.93
0.93
0.93
0.93
0.93
0.52
0.74
0.74
0.54
0.54
0.54
0.54
0.40
0.40
0.40
0.40
0.40
0.40
0.144
0.144
0.144
0.096
0.096
0.096
0.096
0.040
0.040
0.040
0.040
0.040
0.040
EPM7064
EPM7096
EPM7128E
EPM7160E
EPM7192E
EPM7256E
EPM7032S
EPM7064S
EPM7128S
EPM7160S
EPM7192S
EPM7256S
This calculation provides an ICC estimate based on typical conditions
using a pattern of a 16-bit, loadable, enabled, up/down counter in each
LAB with no output load. Actual ICC values should be verified during
operation because this measurement is sensitive to the actual pattern in
the device and the environmental operating conditions.
54
Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
Figure 14 shows typical supply current versus frequency for
MAX 7000 devices.
Figure 14. ICC vs. Frequency for MAX 7000 Devices (Part 1 of 2)
EPM7064
EPM7032
VCC = 5.0 V
Room Temperature
V
CC = 5.0 V
180
140
100
60
300
200
100
151.5 MHz
Room Temperature
151.5 MHz
High Speed
High Speed
Typical ICC
Active (mA)
Typical ICC
Active (mA)
60.2 MHz
60.2 MHz
Low Power
20
0
Low Power
0
50
100
150
200
50
100
150
200
Frequency (MHz)
Frequency (MHz)
EPM7096
VCC = 5.0 V
Room Temperature
450
350
250
150
125 MHz
High Speed
Typical ICC
Active (mA)
55.5 MHz
Low Power
50
0
50
100
150
Frequency (MHz)
Altera Corporation
55
MAX 7000 Programmable Logic Device Family Data Sheet
Figure 14. ICC vs. Frequency for MAX 7000 Devices (Part 2 of 2)
EPM7128E
EPM7160E
500
400
300
500
400
300
VCC = 5.0 V
Room Temperature
VCC = 5.0 V
Room Temperature
100 MHz
125 MHz
Typical ICC
Active (mA)
Typical ICC
Active (mA)
High Speed
High Speed
200
100
200
100
47.6 MHz
55.5 MHz
Low Power
Low Power
0
50
100
150
200
0
50
100
150
200
Frequency (MHz)
Frequency (MHz)
EPM7192E
EPM7256E
500
400
300
750
600
450
VCC = 5.0 V
Room Temperature
VCC = 5.0 V
Room Temperature
90.9 MHz
90.9 MHz
High Speed
Typical ICC
Active (mA)
Typical ICC
Active (mA)
High Speed
43.5 MHz
200
100
300
150
43.4 MHz
Low Power
Low Power
0
25
50
75
100
125
0
25
50
75
100
125
Frequency (MHz)
Frequency (MHz)
56
Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
Figure 15 shows typical supply current versus frequency for MAX 7000S
devices.
Figure 15. ICC vs. Frequency for MAX 7000S Devices (Part 1 of 2)
EPM7032S
EPM7064S
VCC = 5.0 V
Room Temperature
VCC = 5.0 V
Room Temperature
60
50
120
100
175.4 MHz
142.9 MHz
40
30
20
80
60
40
Typical ICC
Active (mA)
Typical ICC
Active (mA)
High Speed
High Speed
56.5 MHz
58.8 MHz
Low Power
Low Power
10
20
0
50
100
150
0
50
100
150
200
200
Frequency (MHz)
Frequency (MHz)
EPM7160S
EPM7128S
VCC = 5.0 V
Room Temperature
VCC = 5.0 V
Room Temperature
280
240
300
240
149.3 MHz
147.1 MHz
200
160
120
80
High Speed
Typical ICC
Active (mA)
Typical ICC
Active (mA)
180
120
60
High Speed
56.5 MHz
Low Power
100
56.2 MHz
Low Power
40
0
50
150
200
0
50
100
150
200
Frequency (MHz)
Frequency (MHz)
Altera Corporation
57
MAX 7000 Programmable Logic Device Family Data Sheet
Figure 15. ICC vs. Frequency for MAX 7000S Devices (Part 2 of 2)
EPM7192S
EPM7256S
VCC = 5.0 V
V
CC = 5.0 V
Room Temperature
Room Temperature
300
240
400
300
128.2 MHz
125.0 MHz
High Speed
High Speed
Typical ICC
Active (mA)
Typical ICC
Active (mA)
180
120
60
200
100
56.2 MHz
55.6 MHz
Low Power
Low Power
0
25
50
75
100
0
25
50
75
100
125
125
Frequency (MHz)
Frequency (MHz)
See the Altera web site (http://www.altera.com) or the Altera Digital
Library for pin-out information.
Device
Pin-Outs
58
Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
Figures 16 through 22 show the package pin-out diagrams for MAX 7000
devices.
Figure 16. 44-Pin Package Pin-Out Diagram
Package outlines not drawn to scale.
1()
1()
Pin 34
Pin 1
6
5
4
3
2
1 44 43 42 41 40
7
39
38
37
36
35
34
33
32
31
30
29
I/O
(2) I/O/(TDI)
(2) I/O/(TDI)
I/O
8
I/O/(TDO) (2)
I/O
I/O
I/O
I/O/(TDO) (2)
9
I/O
I/O
I/O
10
11
12
13
14
15
16
17
I/O
GND
GND
I/O
I/O
VCC
I/O
EPM7032
EPM7032S
EPM7064
EPM7064S
VCC
I/O
I/O
I/O
I/O
I/O
(2) I/O/(TMS)
I/O
(2) I/O/(TMS)
EPM7032
I/O/(TCK) (2)
I/O
VCC
I/O
I/O/(TCK) (2)
I/O
VCC
I/O
I/O
I/O
GND
I/O
GND
I/O
I/O
I/O
18 19 20 21 22 23 24 25 26 27 28
Pin 12
Pin 23
44-Pin PLCC
44-Pin PQFP
1()
Pin 34
Pin 1
(2) I/O/(TDI)
I/O
I/O
I/O/(TDO) (2)
I/O
I/O
GND
I/O
EPM7032
I/O
VCC
EPM7032S
EPM7064
EPM7064S
I/O
I/O
I/O
(2) I/O/(TMS)
I/O/(TCK) (2)
I/O
VCC
I/O
I/O
GND
I/O
I/O
Pin 12
Pin 23
44-Pin TQFP
Notes:
(1) The pin functions shown in parenthesis are only available in MAX 7000E and MAX 7000S devices.
(2) JTAG ports are available in MAX 7000S devices only.
Altera Corporation
59
MAX 7000 Programmable Logic Device Family Data Sheet
Figure 17. 68-Pin Package Pin-Out Diagram
Package outlines not drawn to scale.
1()
I/O
VCCIO
(2) I/O/(TDI)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
I/O
I/O
GND
I/O/(TDO) (2)
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O/(TCK) (2)
I/O
GND
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
(2) I/O/(TMS)
I/O
VCCIO
I/O
I/O
I/O
EPM7064
EPM7096
I/O
GND
I/O
I/O
68-Pin PLCC
Notes:
(1) The pin functions shown in parenthesis are only available in MAX 7000E and MAX
7000S devices.
(2) JTAG ports are available in MAX 7000S devices only.
60
Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
Figure 18. 84-Pin Package Pin-Out Diagram
Package outline not drawn to scale.
2()
)
(1)
I/O
VCCIO
(3)I/O/(TDI)
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
I/O
I/O
GND
I/O/(TDO) (3)
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
EPM7064
EPM7064S
EPM7096
(3)I/O/(TMS)
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
GND
I/O/(TCK) (3)
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
EPM7128E
EPM7128S
EPM7160E
EPM7160S
)
(1)
84-Pin PLCC
Notes:
(1) Pins 6, 39, 46, and 79 are no-connect (N.C.) pins on EPM7096, EPM7160E, and EPM7160S devices.
(2) The pin functions shown in parenthesis are only available in MAX 7000E and MAX 7000S devices.
(3) JTAG ports are available in MAX 7000S devices only.
Altera Corporation
61
MAX 7000 Programmable Logic Device Family Data Sheet
Figure 19. 100-Pin Package Pin-Out Diagram
Package outline not drawn to scale.
Pin 1
Pin 81
Pin 1
Pin 76
EPM7064S
EPM7128S
EPM7160S
EPM7064
EPM7096
EPM7128E
EPM7128S
EPM7160E
Pin 31
Pin 51
Pin 26
Pin 51
100-Pin PQFP
100-Pin TQFP
Figure 20. 160-Pin Package Pin-Out Diagram
Package outline not drawn to scale.
Pin 121
Pin 1
R
P
N
M
L
K
J
EPM7128E
EPM7128S
EPM7160E
EPM7160S
EPM7192E
EPM7192S
EPM7256E
EPM7192E
Bottom
View
H
G
F
E
D
C
B
A
Pin 81
Pin 41
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
160-Pin PGA
160-Pin PQFP
62
Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
Figure 21. 192-Pin Package Pin-Out Diagram
Package outline not drawn to scale.
U
T
R
P
N
M
L
K
J
EPM7256E
Bottom
View
H
G
F
E
D
C
B
A
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17
192-Pin PGA
Figure 22. 208-Pin Package Pin-Out Diagram
Package outline not drawn to scale.
Pin 1
Pin 157
EPM7256E
EPM7256S
Pin 53
Pin 105
208-Pin PQFP/RQFP
Altera Corporation
63
MAX 7000 Programmable Logic Device Family Data Sheet
The information contained in the MAX 7000 Programmable Logic Device
Revision
History
Family Data Sheet version 6.7 supersedes information published in
previous versions. The following changes were made in the MAX 7000
Programmable Logic Device Family Data Sheet version 6.7:
Version 6.7
The following changes were made in the MAX 7000 Programmable Logic
Device Family Data Sheet version 6.7:
■
Reference to AN 88: Using the Jam Language for ISP & ICR via an
Embedded Processor has been replaced by AN 122: Using Jam STAPL for
ISP & ICR via an Embedded Processor.
Version 6.6
The following changes were made in the MAX 7000 Programmable Logic
Device Family Data Sheet version 6.6:
■
■
Added Tables 6 through 8.
Added “Programming Sequence” section on page 17 and
“Programming Times” section on page 18.
Version 6.5
The following changes were made in the MAX 7000 Programmable Logic
Device Family Data Sheet version 6.5:
■
Updated text on page 16.
Version 6.4
The following changes were made in the MAX 7000 Programmable Logic
Device Family Data Sheet version 6.4:
■
Added Note (5) on page 28.
Version 6.3
The following changes were made in the MAX 7000 Programmable Logic
Device Family Data Sheet version 6.3:
■
Updated the “Open-Drain Output Option (MAX 7000S Devices
Only)” section on page 20.
64
Altera Corporation
Notes:
Altera Corporation
65
MAX 7000 Programmable Logic Device Family Data Sheet
Copyright © 2005 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company,
the stylized Altera logo, specific device designations, and all other words and logos that are identified as
trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera
Corporation in the U.S. and other countries. All other product or service names are the property of their re-
spective holders. Altera products are protected under numerous U.S. and foreign patents and pending
applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products
to current specifications in accordance with Altera's standard warranty, but reserves the right to make chang-
es to any products and services at any time without notice. Altera assumes no responsibility or liability
arising out of the application or use of any information, product, or service described
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www.altera.com
Applications Hotline:
(800) 800-EPLD
herein except as expressly agreed to in writing by Altera Corporation. Altera customers
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Literature Services:
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66
Altera Corporation
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