HC351_技术文档

Section I. HardCopy III Device Datasheet

®

This section provides the datasheet for the HardCopy III device family. This section

includes the following chapter:

■

Chapter 1, DC and Switching Characteristics of HardCopy III Devices

Revision History

Refer to each chapter for its own specific revision history. For information on when

each chapter was updated, refer to the Chapter Revision Dates section, which appears

in the full handbook.

HardCopy III Device Handbook, Volume 3

i–2

Section I: HardCopy III Device Datasheet

HardCopy III Device Handbook, Volume 3

1. DC and Switching Characteristics of

HardCopy III Devices

HIII53001-2.0

Electrical Characteristics

This chapter provides information about the absolute maximum ratings,

recommended operating conditions, DC electrical characteristics, and other

®

specifications for HardCopy III devices. HardCopy III devices are offered in both

commercial and industrial grades.

Operating Conditions

When HardCopy III devices are implemented in a system, they are rated according to

a set of defined parameters. To maintain the highest possible performance and

reliability, you must consider the operating requirements described in this chapter.

®

HardCopy III devices are not speed binned like Stratix III devices because

HardCopy III devices are designed and built to function at a target frequency based

on timing constraints, and operate at either commercial or industrial temperatures.

Absolute Maximum Ratings

Absolute maximum ratings define the maximum operating conditions for

HardCopy III devices. The values are based on experiments conducted with the

device and theoretical modeling of breakdown and damage mechanisms. The

functional operation of the device is not implied by these conditions. Conditions

beyond those listed in Table 1–1 can cause permanent damage to the device.

Additionally, device operation at the absolute maximum ratings for extended periods

of time can have adverse effects on the device.

Table 1–1. HardCopy III Device Absolute Maximum Ratings – Preliminary (Part 1 of 2) (Note 1)

Symbol

Parameter

Core voltage power supply

I/O registers power supply

PLL digital power supply

PLL analog power supply

Minimum

–0.5

Maximum

1.35

Unit

V

V_CCL

V_CC

–0.5

1.35

V

V_{CCD_PLL}

V_{CCA_PLL}

V_CCPT(2)

–0.5

1.35

V

–0.5

3.75

V

Power supply for the temperature sensing

diode

–0.5

3.75

V

V_CCPGM

V_CCPD

Configuration pins power supply

I/O pre-driver power supply

I/O power supply

–0.5

3.9

V

V_CCIO

3.9

V_{CC_CLKIN}

Differential clock input power supply (top and

bottom I/O banks only)

3.75

V

_CCBAT(3)

Battery back-up power supply for design

security volatile key register

—

V

V_I

DC input voltage

–0.5

–55

–25

4.0

125

40

V

T_J

Operating junction temperature

DC output current, per pin

°C

I_OUT

mA

HardCopy III Device Handbook, Volume 3

1–2

Chapter 1: DC and Switching Characteristics of HardCopy III Devices

Electrical Characteristics

Table 1–1. HardCopy III Device Absolute Maximum Ratings – Preliminary (Part 2 of 2) (Note 1)

Symbol

Parameter

Minimum

Maximum

Unit

T_STG

Storage temperature (no bias)

–65

150

°C

Notes to Table 1–1:

(1) Supply voltage specifications apply to voltage readings taken at the device pins and not the power supply.

(2) In Stratix III devices, this power supply is also used for programmable power technology.

(3) In HardCopy III devices, this power supply is not used.

Maximum Allowed Overshoot and Undershoot Voltage

During transitions, input signals may overshoot to the voltage shown in Table 1–2 and

undershoot to –2.0 V for input currents less than 100 mA and periods shorter than

20 ns.

Table 1–2 lists the maximum allowed input overshoot voltage. The maximum allowed

overshoot duration is specified as the percentage of high time over the lifetime of the

device. A DC signal is equivalent to 100% duty cycle.

Table 1–2. Maximum Allowed Overshoot During Transitions – Preliminary

Overshoot

Duration as % of

Symbol

Parameter

Condition

4

High Time

100.000

79.330

46.270

27.030

15.800

9.240

Unit

%

4.05

4.1

4.15

4.2

4.25

4.3

5.410

4.35

4.4

3.160

1.850

Vi (AC)

AC Input Voltage

4.45

4.5

1.080

0.630

4.55

4.6

0.370

0.220

4.65

4.7

0.130

0.074

4.75

4.8

0.043

0.025

4.85

0.015

HardCopy III Device Handbook, Volume 3

Chapter 1: DC and Switching Characteristics of HardCopy III Devices

1–3

Electrical Characteristics

Figure 1–1 shows the methodology to determine the overshoot duration. The

overshoot voltage is displayed in red and is present at the HardCopy III pin, up to

4.1 V. From Table 1–2, for an overshoot of up to 4.1 V, the percentage of high time for

overshoot > 3.15 V can be as high as 46% over an 11.4 year period. The percentage of

high-time is calculated as (delta T/T) × 100. This 11.4 year period assumes the device

is always turned on with 100% I/O toggle rate and 50% duty cycle signal. For lower

I/O toggle rates and situations where the device is in an idle state, lifetimes are

increased.

Figure 1–1. Overshoot Duration

4.1 V

3.15 V

3.0 V

ΔT

T

Recommended Operating Conditions

This section lists the functional operation limits for AC and DC parameters for

HardCopy III devices. The steady-state voltage and current values expected from

HardCopy III devices are provided in Table 1–3. All supplies are required to

monotonically reach their full-rail values within t_RAMPmaximum. Allowed ripple on

power supplies is bounded by the minimum and maximum specifications listed in

Table 1–3.

Table 1–3. HardCopy III Device Recommended Operating Conditions – Preliminary (Part 1 of 2)

Symbol

V_CCL(1)

Parameter

Conditions

Minimum

Typical

Maximum

Unit

Core voltage power supply for

internal logic and input buffers

—

0.87

0.9

0.93

V

V_CC(1)

I/O registers power supply

PLL digital power supply

PLL analog power supply

—

0.87

0.9

2.5

0.93

V

V_{CCD_PLL}(1)

V_{CCA_PLL}

2.375

2.625

Power supply for the temperature

sensing diode

V

_CCPT(2)

Configuration pins power supply,

3.0 V

—

2.85

2.375

1.71

3.0

2.5

1.8

3.15

2.625

1.89

V

Configuration pins power supply,

2.5 V

V_CCPGM

Configuration pins power supply,

1.8 V

HardCopy III Device Handbook, Volume 3

1–4

Chapter 1: DC and Switching Characteristics of HardCopy III Devices

Electrical Characteristics

Table 1–3. HardCopy III Device Recommended Operating Conditions – Preliminary (Part 2 of 2)

Symbol

Parameter

Conditions

Minimum

2.85

Typical

3.0

Maximum

3.15

Unit

V

I/O pre-driver power supply, 3.0 V

I/O pre-driver power supply, 2.5 V

I/O power supply, 3.0 V

—

V_CCPD(3)

2.375

2.85

2.5

2.625

3.15

V

3.0

V

I/O power supply, 2.5 V

2.375

1.71

2.5

2.625

1.89

V

V_CCIO

I/O power supply, 1.8 V

1.8

V

I/O power supply, 1.5 V

1.425

1.14

1.5

1.575

1.26

V

I/O power supply, 1.2 V

1.2

V

Differential clock input power

supply (top and bottom I/O banks

only)

2.375

2.5

2.625

V

V_{CC_CLKIN}

Battery back-up power supply for

design security volatile key

register

—

V

_CCBAT(4)

V_I

DC input voltage

Output voltage

—

–0.3

0

—

3.6

V_CCIO

85

V

V_O

V

For

0

°C

commercial

use

T_J

Operating junction temperature

Power supply ramp time

For industrial

use

–40

—

100

°C

—

Normal POR

(PORSEL=0)

50 µs

300 ms

12 ms

t_RAMP

Fast POR

(PORSEL=1)

Notes to Table 1–3:

(1) In Stratix III devices, V_CCLcan also be 1.1 V, while V_CCand V_{CCD_PLL}are 1.1 V. In HardCopy III devices, all three supplies are 0.9 V.

(2) In Stratix III devices, this power supply is also used for programmable power technology.

(3) V_CCPDis either 2.5 V or 3.0 V. For a 3.0-V I/O standard, V_CCPD= 3.0 V. For a 2.5 V or lower I/O standard, V_CCPD= 2.5 V.

(4) In HardCopy III devices, this power supply is not used.

DC Characteristics

This section lists the input pin capacitances, on-chip termination tolerance, and hot

socketing specifications.

Supply Current

Standby current is the current the device draws after the device enters user mode with

no inputs/outputs toggling and no activity in the device. Since these currents vary

largely with the resources used, use the Excel-based Early Power Estimator (EPE) to

get supply current estimates for your design.

HardCopy III Device Handbook, Volume 3

Chapter 1: DC and Switching Characteristics of HardCopy III Devices

1–5

Electrical Characteristics

Table 1–4 lists supply current specifications for V_{CC_CLKIN}and V_CCPGM. Use the EPE to get

supply current estimates for the remaining power supplies.

Table 1–4. Supply Current Specifications for V_{CC_CLKIN}and V_CCPGM– Preliminary (Note 1)

Symbol

I_CLKIN

I_PGM

Parameter

Min

0

Max

TBD

Unit

mA

V_{CC_CLKIN}current specifications

V_CCPGMcurrent specifications

0

Note to Table 1–4:

(1) Pending silicon characterization.

I/O Pin Leakage Current

Table 1–5 defines HardCopy III I/O pin leakage current specifications.

Table 1–5. HardCopy III I/O Pin Leakage Current – Preliminary (Note 1), (2)

Symbol

Parameter

Conditions

Min

–10

Typ

—

Max Unit

I_I

I_OZ

Input pin leakage current

V_I= V_CCIOMAXto 0 V

V_O= V_CCIOMAXto 0 V

10

μA

Tri-stated I/O pin leakage

current

—

Notes To Table 1–5:

(1) This value is specified for normal device operation. The value may vary during power up. This applies for all V_CCIO

settings (3.0, 2.5, 1.8, 1.5, and 1.2 V).

(2) The 10 mA I/O leakage current limit is applicable when the internal clamping diode is off. A higher current is

observed when the diode is on.

On-Chip Termination (OCT) Specifications

If OCT calibration is enabled, calibration is automatically performed at power up for

I/Os connected to the calibration block. Table 1–6 lists the HardCopy III OCT

calibration block accuracy specifications.

Table 1–6. HardCopy III On-Chip Termination Calibration Accuracy Specifications – Preliminary (Part 1 of 2) (Note 1)

Calibration Accuracy

Symbol

Description

Conditions

Commercial (2) Industrial Unit

25−Ω R_S3.0/2.5 Internal series termination with calibration

(25-Ω setting)

V_CCIO= 3.0/2.5 V

TBD

—

%

50−Ω R_S3.0/2.5 Internal series termination with calibration

(50-Ω setting)

V_CCIO= 3.0/2.5 V

V_CCIO= 2.5 V

V_CCIO= 1.8 V

V_CCIO= 1.5 V

50−Ω R_T2.5

25−Ω R_S1.8

50−Ω R_S1.8

50−Ω R_T1.8

50−Ω R_S1.5

Internal parallel termination with calibration

(50-Ω setting)

Internal series termination with calibration

(25-Ω setting)

Internal series termination with calibration

(50-Ω setting)

Internal parallel termination with calibration

(50-Ω setting)

Internal series termination with calibration

(50-Ω setting)

HardCopy III Device Handbook, Volume 3

1–6

Chapter 1: DC and Switching Characteristics of HardCopy III Devices

Electrical Characteristics

Table 1–6. HardCopy III On-Chip Termination Calibration Accuracy Specifications – Preliminary (Part 2 of 2) (Note 1)

Calibration Accuracy

Symbol

Description

Conditions

Commercial (2) Industrial Unit

50−Ω R_T1.5

Internal parallel termination with calibration

(50-Ω setting)

V_CCIO= 1.5 V

TBD

—

%

50−Ω R_S1.2

Internal series termination with calibration

(50-Ω setting)

V_CCIO= 1.2 V

50−Ω R_T1.2

Internal parallel termination with calibration

(50-Ω setting)

Notes to Table 1–6:

(1) OCT calibration accuracy is valid at the time of calibration only.

(2) Pending silicon characterization.

The accuracy listed in Table 1–6 is valid at the time of calibration. If the voltage or

temperature changes, the termination resistance value varies. Table 1–7 lists the

resistance tolerance for HardCopy III on-chip termination.

Table 1–7. On-Chip Termination Resistance Tolerance Specification for I/Os – Preliminary (Note 1)

Resistance Tolerance

Symbol

R_{OCT_UNCAL}

Description

Commercial Max

Industrial Max

Unit

%

Internal series termination without calibration

Internal series termination with calibration

TBD

—

R_{OCT_CAL}

(2)

%

Notes to Table 1–7:

(1) Pending silicon characterization.

(2) For resistance tolerance after power-up calibration, refer to Table 1–8.

Table 1–8 lists OCT variation with temperature and voltage after power-up

calibration. Use Table 1–8 and Equation 1–1 to determine OCT variation without

re-calibration.

Equation 1–1.

dR

dT

dR

dV

⎛

⎞

⎠

------

R_OCT= R_CAL1 +

× ΔT +

× ΔV

⎝

1

Note that R_CALis calibrated on-chip termination at power-up. ΔT and ΔV are

variations in temperature and voltage (V_CCIO) at power-up.

HardCopy III Device Handbook, Volume 3

Chapter 1: DC and Switching Characteristics of HardCopy III Devices

1–7

Electrical Characteristics

Table 1–8. On-Chip Termination Variation after Power-up Calibration – Preliminary (Note 1), (2)

Commercial

Typical

Symbol

Description

V

_CCIO(V)

3.0

2.5

1.8

1.5

1.2

3.0

2.5

1.8

1.5

1.2

Unit

TBD

%/mV

%/°C

OCT variation with voltage without

re-calibration

dR/dV

%/°C

OCT variation with temperature without

re-calibration

dR/dT

%/°C

Note to Table 1–8:

(1) Valid for V_CCIOrange of 5% and temperature range of 0° to 85° C.

(2) Pending silicon characterization.

Pin Capacitance

Table 1–9 shows the HardCopy III device family pin capacitance.

Table 1–9. HardCopy III Device Capacitance – Preliminary (Note 1)

Symbol

Parameter

Typical Unit

C_IOTB

Input capacitance on top and bottom I/O pins

TBD

pF

C_IOLR

Input capacitance on left and right I/O pins

C_CLKTB

Input capacitance on top and bottom dedicated clock input pins

Input capacitance on left and right dedicated clock input pins

Input capacitance on dual-purpose clock output and feedback pins

Input capacitance for dedicated clock input pins

C_CLKLR

C_OUTFB

C_CLK1,C_CLK3,C_CLK8,and C_CLK10

Note to Table 1–9:

(1) Pending silicon characterization.

Hot Socketing

Table 1–10 lists the hot socketing specifications for HardCopy III devices.

Table 1–10. HardCopy III Hot Socketing Specifications – Preliminary (Note 1)

Symbol

I_IOPIN(DC)

I_IOPIN(AC)

Parameter

Maximum

300 μA

DC current per I/O pin

AC current per I/O pin

8 mA for ≤ 10 ns

Note to Table 1–10:

(1) Pending silicon characterization.

HardCopy III Device Handbook, Volume 3

1–8

Chapter 1: DC and Switching Characteristics of HardCopy III Devices

Electrical Characteristics

Internal Weak Pull-Up Resistor

Table 1–11 lists the weak pull-up resistor values for HardCopy III devices.

Table 1–11. HardCopy III Internal Weak Pull-Up Resistor – Preliminary (Note 1), (2)

Symbol

Parameter

Conditions

Min

—

Typ

25

Max

—

Unit

kΩ

V

_CCIO= 3.0 V 5% (3)

Value of I/O pin pull-up resistor

before and during user mode, if the

pull-up resistor option is enabled

V_CCIO= 2.5 V 5% (3)

V_CCIO= 1.8 V 5% (3)

V_CCIO= 1.5 V 5% (3)

V_CCIO= 1.2 V 5% (3)

—

R_PU

—

Notes to Table 1–11:

(1) Pending silicon characterization.

(2) All I/O pins have an option to enable weak pull-up except test and JTAG pins.

(3) Pin pull-up resistance values may be lower if an external source drives the pin higher than V_CCIO

.

I/O Standard Specifications

Table 1–12 through Table 1–17 list input voltage sensitivities (V_IHand V_IL), output

voltage (V_OHand V_OL), and current drive characteristics (I_OHand I_OL) for all I/O

standards supported by HardCopy III devices. Refer to Table 1–33 on page 1–21 for an

explanation of terms used in Table 1–12 through Table 1–17. V_OLand V_OHvalues are

valid at the corresponding I_OLand I_OH, respectively.

Table 1–12. Single-Ended I/O Standards Specifications — Preliminary

V_CCIO(V) V_IL(V)

Typ

V_IH(V)

V_OL(V)

V_OH(V)

I/O Standard

Min

2.85

Max

3.15

Min

–0.3

Max

0.8

Min

1.7

Max

3.6

Max

0.4

Min

I_OL(mA) I_OH(mA)

3.0-V LVTTL

3

2.4

2

–2

3.0-V

0.8

3.6

0.2

V_CCIO

–

0.1

–0.1

LVCMOS

0.2

2.1

2

2.375

2.5

1.8

2.625

1.89

–0.3

0.7

1.7

3.6

0.2

0.4

0.1

1

–0.1

–1

2.5V LVTTL/

LVCMOS

0.7

1.7

2

–2

1.8V LVTTL/

LVCMOS

1.71

0.35 × 0.65 ×

V_CCIOV_CCIO

V_CCIO

0.3

+

0.45

V_CCIO

–

2

–2

0.45

1.5 V LVTTL/ 1.425

LVCMOS

1.5

1.2

3

1.575

1.26

3.15

–0.3

—

0.35 × 0.65 ×

V_CCIOV_CCIO

V_CCIO

0.3

+

0.25 × 0.75 ×

V_CCIOV_CCIO

2

–2

1.2V LVTTL/

LVCMOS

1.14

2.85

0.35 × 0.65 ×

V_CCIO

0.3

0.25 × 0.75 ×

2

V_CCIO

0.3 ×

V_CCIO

0.5 ×

V_CCIO

3.6

0.1 ×

V_CCIO

0.9 ×

V_CCIO

1.5

–0.5

3.0-V PCI

3.0-V PCI-X

3

—

0.35 ×

V_CCIO

0.5 ×

V_CCIO

—

0.1 ×

V_CCIO

0.9 ×

V_CCIO

HardCopy III Device Handbook, Volume 3

Chapter 1: DC and Switching Characteristics of HardCopy III Devices

1–9

Electrical Characteristics

Refer to Figure 1–6 in the row “Single-Ended Voltage Referenced I/O Standard” in

Table 1–33 for an example of a voltage referenced receiver input waveform and

explanation of terms used in Table 1–13.

Table 1–13. Single-Ended SSTL and HSTL I/O Reference Voltage Specifications – Preliminary

V_CCIO(V) V_REF(V)

Typ Typ

V_TT(V)

I/O Standard

Min

Max

Min

Max

Min

Typ

Max

SSTL-2 CLASS I, II

2.375

2.5

1.8

1.5

2.625

0.49 ×

V_CCIO

0.5 ×

V_CCIO

0.51 ×

V_CCIO

V_REF

0.04

–

V_REF

V_REF+

0.04

SSTL-18 CLASS I, II

SSTL-15 CLASS I, II

1.71

1.89

0.833

0.9

0.969

V_REF

0.04

–

V_REF

V_REF+

0.04

1.425

1.575

0.47 ×

V_CCIO

0.5 ×

V_CCIO

0.53 ×

V_CCIO

0.47 ×

V_CCIO

0.53 ×

V_CCIO

HSTL-18 CLASS I, II

HSTL-15 CLASS I, II

HSTL-12 CLASS I, II

1.71

1.425

1.14

1.8

1.5

1.2

1.89

1.575

1.26

0.85

0.68

0.9

0.95

0.9

—

V_CCIO/2

—

0.75

0.47 ×

V_CCIO

0.5 ×

V_CCIO

0.53 ×

V_CCIO

Table 1–14. Single-Ended SSTL and HSTL I/O Standards Signal Specifications – Preliminary (Part 1 of 2)

V_{IL (D C)}(V)

Min Max

V_IH(DC)(V)

Min Max

V_REF

V_IL(AC)(V) V_IH(AC)(V) V_OL(V)

V_OH(V)

Min

I/O Standard

Max

Min

Max

I_OL(mA) I_OH(mA)

SSTL-2 CLASS I

–0.3

V_REF

0.15

–

+

V_CCIO

0.3

+

V_REF

0.31

–

V_REF

0.31

+

VTT –

0.57

VTT +

0.57

8.1

16.2

6.7

13.4

8

–8.1

–16.2

–6.7

–13.4

–8

0.15

SSTL-2 CLASS II

SSTL-18 CLASS I

SSTL-18 CLASS II

SSTL-15 CLASS I

SSTL-15 CLASS II

HSTL-18 CLASS I

HSTL-18 CLASS II

HSTL-15 CLASS I

HSTL-15 CLASS II

V_REF

0.15

–

V_REF

+

V_CCIO

0.3

V_REF

0.31

–

V_REF

0.31

+

VTT –

0.76

VTT +

0.76

0.15

V_REF

0.125

–

V_REF

+

V_CCIO

0.3

V_REF

0.25

–

V_REF

0.25

+

VTT –

0.475

VTT +

0.475

0.125

V_REF

0.125

–

V_REF

+

V_CCIO

0.3

V_REF

0.25

–

V_REF

0.25

+

0.28

V_CCIO–

0.28

0.125

V_REF

0.1

–

V_REF

0.1

+

V_CCIO

0.3

V_REF

0.175

–

V_REF

0.175

+

0.2 ×

V_CCIO

0.8 ×

V_CCIO

V_REF

V_CCIO

0.3

V_REF

0.175

–

V_REF

0.175

+

0.2 ×

V_CCIO

0.8 ×

V_CCIO

16

8

–16

–8

0.1

–

V_REF

+

V_CCIO

0.3

V_REF

0.2

–

V_REF

0.2

+

0.4

V_CCIO

0.4

–

0.1

V_REF

0.1

–

V_REF

+

V_CCIO

0.3

V_REF

0.2

V_REF

V_CCIO

0.4

–

16

8

–16

–8

0.1

0.2

V_REF

–

V_REF

+

V_CCIO

0.3

V_REF

0.2

–

+

V_CCIO

0.4

0.1

V_REF

0.1

0.2

V_REF

0.2

–

V_REF

+

V_CCIO

0.3

V_REF

0.2

–

+

V_CCIO

0.4

16

–16

0.1

HardCopy III Device Handbook, Volume 3

1–10

Chapter 1: DC and Switching Characteristics of HardCopy III Devices

Electrical Characteristics

Table 1–14. Single-Ended SSTL and HSTL I/O Standards Signal Specifications – Preliminary (Part 2 of 2)

V_{IL (D C)}(V)

Min Max

–0.15

V_IH(DC)(V)

Min Max

V_REFV_CCIO

V_IL(AC)(V) V_IH(AC)(V) V_OL(V)

V_OH(V)

Min

I/O Standard

Max

Min

Max

I_OL(mA) I_OH(mA)

HSTL-12 CLASS I

V_REF

–

+

V_REF

0.15

–

V_REF

0.15

+

0.25 ×

V_CCIO

0.75 ×

V_CCIO

8

–8

0.08

0.08 0.15

HSTL-12 CLASS II –0.15

V_REF

0.08

–

V_REF

0.08

+

V_CCIO

0.15

+

V_REF

0.15

–

V_REF

0.15

+

0.25 ×

V_CCIO

0.75 ×

V_CCIO

16

–16

Refer to Figure 1–2 in the row “Differential I/O Standards” in Table 1–33 for receiver

input and transmitter output waveforms, and for all differential I/O standards

(LVDS, mini-LVDS, RSDS). V_{CC_CLKIN}is the power supply for differential column clock

input pins. V_CCPDis the power supply for row I/Os and all other column I/Os.

Table 1–15. Differential SSTL I/O Standard Specifications – Preliminary

V_CCIO(V) V_{SWING (DC)}(V) V_{X (AC)}(V)

Typ Min Max

2.375 2.5 2.625 0.3

V_{SWING (AC)}(V)

V_{OX (AC)}(V)

I/O Standard

SSTL-2

Min

Max

Min

Typ

Max

Min

Max

V_CCIO

Min

Typ

Max

V_CCIO

+

V_CCIO/2

– 0.2

—

V_CCIO/2

+ 0.2

0.6

V_CCIO/2

– 0.15

—

V_CCIO/2

+ 0.15

CLASS I,

CLASS II

0.6

+ 0.6

SSTL-18

CLASS I,

CLASS II

1.71

1.8

1.89

0.3

V_CCIO

0.6

+

V_CCIO/2

–

0.175

—

V_CCIO/2

+

0.175

0.5

0.4

V_CCIO

V_CCIO/2

–

0.125

—

V_CCIO/2

+

0.125

+ 0.6

SSTL-15

CLASS I,

CLASS II

1.425 1.5 1.575 0.2

—

V_CCIO/2

—

V_CCIO/2

—

Table 1–16. Differential HSTL I/O Standards Specifications – Preliminary

V_CCIO(V)

V_DIF(DC)(V)

V_X(AC)(V)

V_CM(DC)(V)

V_DIF(AC)(V)

I/O Standard Min

Typ

Max

Min

Max

Min

Typ

Max

Min

Typ

Max

Min

Max

HSTL-18

CLASS I, II

1.71

1.425

1.14

1.8

1.89

0.2

—

0.78

—

1.12

0.9

—

0.78

—

1.12

0.4

—

HSTL-15

CLASS I, II

1.5

1.2

1.575

1.26

0.2

—

0.68

—

0.68

—

0.9

0.4

0.3

—

HSTL-12

CLASS I, II

0.16 V_CCIO

+

0.5 ×

V_CCIO

0.4 × 0.5 × 0.6 ×

V_CCIO

0.48

+

0.3

V_CCIO

Table 1–17. Differential I/O Standard Specifications – Preliminary (Part 1 of 2)

V_CCIO(V)

Typ

V_ID(mV)

V_{ICM (DC)}(V)

V_OD(V) (1)

Typ

V_OCM(V) (1)

Typ

1.125 1.25 1.375

I/O Standard

Min

Max

Min

Condition

Max

Min

Condition

Max

Min

Max

Min

Max

0.05

(2)

Dmax ≤ 700

1.8

(2)

2.375

2.5

2.625 100

—

0.247

—

0.6

V_CM= 1.25V

Mbps

2.5V LVDS

(Row I/O)

1.05

(2)

Dmax > 700

Mbps

1.55

(2)

2.375

2.5

—

HardCopy III Device Handbook, Volume 3

Chapter 1: DC and Switching Characteristics of HardCopy III Devices

1–11

Electrical Characteristics

Table 1–17. Differential I/O Standard Specifications – Preliminary (Part 2 of 2)

V_CCIO(V)

Typ

V_ID(mV)

V_{ICM (DC)}(V)

V_OD(V) (1)

Typ

V_OCM(V) (1)

I/O Standard

Min

Max

Min

Condition

Max

Min

Condition

Max

Min

Max

Min

Typ

Max

0.05

(2)

Dmax ≤ 700

1.8

(2)

2.375

2.5

2.625 100

—

0.247

—

0.6

1.0

1.25

1.5

2.5V LVDS

(Column

I/O)

V_CM= 1.25V

Mbps

1.05

(2)

Dmax > 700

Mbps

1.55

(2)

2.375

2.5

—

1.5

1.4

RSDS

(Row I/O)

2.625 100

2.625 200

0.3

0.4

—

1.4

0.1

0.2

0.6

0.5

1.2

V_CM= 1.25V

RSDS

(Column

I/O)

2.375

2.5

V_CM= 1.25V

—

0.1

0.2

—

0.6

0.5

1.2

1.5

1.4

1.5

Mini-LVDS

(Row I/O)

—

600

1.325 0.25

Mini-LVDS

(Column

I/O)

2.625

200

2.375

(4)

2.5

(4)

2.625

(4)

Dmax ≤ 700

1.8

—

300

—

0.6

—

Mbps

(5)

LVPECL (3)

Dmax ≤ 700

1.6

—

Mbps

(5)

Notes to Table 1–17:

(1) R_Lrange: 90 ≤ R_L≤ 110 Ω .

(2) For data rate: D_max> 700 Mbps, the minimum input voltage is 1.0 V, the maximum input voltage is 1.6 V. For D_max≤ 700 Mbps, the minimum input

voltage is 0 V, the maximum input voltage is 1.85 V.

(3) Column and Row I/O banks support LVPECL I/O standards for input operation only on dedicated clock input pins. Differential clock inputs in

column I/O use V_{CC_CLKIN}which should be powered by 2.5 V. Differential clock inputs in row I/Os are powered by V_CCPD

.

(4) Power supply for column I/O LVPECL differential clock input buffer is V_{CC_CLKIN.}

(5) For data rate D_max> 700 Mbps, the minimum input voltage is 0.85 V, and the maximum input voltage is 1.75 V. For data rate D_max≤ 700 Mbps, the

minimum input voltage is 0.45 V, and the maximum input voltage is 1.95 V.

Power Consumption

Altera offers two ways to estimate power for a design: the Excel-based Early Power

®

Estimator and the Quartus II PowerPlay Power Analyzer feature.

Use the interactive Excel-based Early Power Estimator prior to designing in order to

get a magnitude estimate of the device power. The Quartus II PowerPlay Power

Analyzer provides better quality estimates based on the specifics of the design after

the place-and-route is complete. The PowerPlay Power Analyzer can apply a

combination of user-entered, simulation-derived, and estimated signal activities

which, combined with detailed circuit models, can yield very accurate power

estimates.

See Table 1–4 on page 1–5 for supply current estimates for V_CCPGMand V_{CC_CLKIN}. Use

the EPE and PowerPlay Power Analyzer for current estimates of the remaining power

supplies.

f

For more information about power estimation tools, refer to the Power Play Early

Power Estimator User Guide and the PowerPlay Power Analysis chapter in volume 3 of

the Quartus II Device Handbook.

HardCopy III Device Handbook, Volume 3

1–12

Chapter 1: DC and Switching Characteristics of HardCopy III Devices

Switching Characteristics

This section provides performance characteristics of HardCopy III core and periphery

blocks for commercial grade devices. HardCopy III devices are designed to meet, at

minimum, the –3 speed grade of the Stratix III devices. Silicon characterization

determines the actual performance of the HardCopy III devices. These characteristics

can be designated as Preliminary or Final, as defined below.

■

Preliminary—Preliminary characteristics are created using simulation results,

process data, and other known parameters.

■

Final—Final numbers are based on actual silicon characterization and testing.

These numbers reflect the actual performance of the device under worst-case

silicon process, voltage, and junction temperature conditions.

Core Performance Specifications

This sections describes the clock tree, phase-locked loop (PLL), digital signal

processing (DSP), TriMatrix, configuration, and JTAG specifications.

Clock Tree Specifications

Table 1–18 lists clock tree performance specifications for the logic array, DSP blocks,

and TriMatrix Memory blocks for HardCopy III devices.

Table 1–18. HardCopy III Clock Tree Performance – Preliminary (Note 1)

Device

HC311

HC321

HC322

HC331

HC332

HC351

HC352

HC361

HC362

HC372

Commercial Grade (MHz)

Unit

MHz

500

Note to Table 1–18:

(1) Pending silicon characterization.

HardCopy III Device Handbook, Volume 3

Chapter 1: DC and Switching Characteristics of HardCopy III Devices

1–13

Switching Characteristics

PLL Specifications

Table 1–19 describes the HardCopy III PLL specifications when operating in both the

commercial junction temperature range (0° to 85° C) and the industrial junction

temperature range (–40° to 100°C). Refer to Figure 1–4in the “PLL Specifications” row

in Table 1–33 for a PLL block diagram.

Table 1–19. HardCopy III PLL Specifications – Preliminary (Part 1 of 2) (Note 1)

Symbol

f_IN

Parameter

Min

5

Typ

—

50

—

Max

717 (2)

325

Unit

Input clock frequency

MHz

f_INPFD

Input frequency to the PFD

PLL VCO operating range

5

MHz

f_VCO

600

40

—

45

—

1300

60

MHz

t_EINDUTY

f_OUT

Input clock or external feedback clock input duty cycle

Output frequency for internal global or regional clock

Output frequency for external clock output

Duty cycle for external clock output (when set to 50%)

External feedback clock compensation time

Time required to reconfigure PLL scan chain

Time required to reconfigure phase shift

%

717 (3)

55

MHz

f_{OUT_EXT}

t_OUTDUTY

t_FCOMP

MHz

%

10

ns

scanclk cycles

MHz

t_CONFIGPLL

t_CONFIGPHASE

f_SCANCLK

t_LOCK

—

scanclk frequency

100

Time required to lock from end of device power up (4)

—

ms

t_DLOCK

Time required to lock dynamically (after switchover or

reconfiguring any non-post-scale counters/delays)

—

ms

f_CLBW

PLL closed-loop low bandwidth

—

10

—

MHz

PLL closed-loop medium bandwidth

PLL closed-loop high bandwidth (5)

Accuracy of PLL phase shift

MHz

t_{PLL_PSERR}

t_ARESET

ps

Minimum pulse width on areset signal

Input clock cycle to cycle jitter (F_REF≥ 100 MHz)

Input clock cycle to cycle jitter (F_REF< 100 MHz)

ns

t_INCCJ(4)

UI (p–p)

ps (p–p)

mUI (p–p)

ps (p–p)

mUI (p–p)

ps (p–p)

mUI (p–p)

ps (p–p)

t_{OUTPJ_DC}(6) Period jitter for dedicated clock output (F_OUT≥ 100 MHz)

Period jitter for dedicate clock output (F_OUT< 100 MHz)

t_{OUTCCJ_DC}(6) Cycle to cycle jitter for dedicated clock output (F_OUT≥ 100 MHz)

Cycle to cycle jitter for dedicated clock output (F_OUT< 100 MHz)

t_{OUTPJ_IO}(6) Period jitter for clock output on regular I/O (F_OUT≥ 100 MHz)

Period jitter for clock output on regular I/O (F_OUT< 100 MHz)

t_{OUTCCJ_IO}(6) Cycle to cycle jitter for clock output on regular I/O (F_OUT

≥

100 MHz)

Cycle to cycle jitter for clock output on regular I/O (F_OUT

100 MHz)

<

—

mUI (p–p)

HardCopy III Device Handbook, Volume 3

1–14

Chapter 1: DC and Switching Characteristics of HardCopy III Devices

Switching Characteristics

Table 1–19. HardCopy III PLL Specifications – Preliminary (Part 2 of 2) (Note 1)

Symbol

f_DRIFT

Parameter

Min

Typ

Max

Unit

Frequency drift after PFDENA is disabled for duration of 100 ms

—

%

Notes to Table 1–19:

(1) Pending silicon characterization.

(2) This specification is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O

standard.

(3) This specification is limited by the lower of the two: I/O f_MAXor f_OUTof the PLL.

(4) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source, which is less

than 200 ps.

(5) High bandwidth PLL settings are not supported in external feedback mode.

(6) Peak-to-peak jitter with a probability level of 10^–12(14 sigma, 99.99999999974404% confidence level). The output jitter specification applies to

the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied.

DSP Block Specifications

Table 1–20 describes the HardCopy III DSP performance specifications.

Table 1–20. HardCopy III DSP Block Performance Specifications – Preliminary (Note 1), (2)

Mode

9 × 9-bit multiplier (a, c, e, g) (3)

9 × 9-bit multiplier (b, d, f, h) (3)

12 × 12-bit multiplier (a, e) (4)

12 × 12-bit multiplier (b, d, f, h) (4)

18 × 18-bit multiplier

Number of Multipliers Max Unit

1

2

4

2

4

1

365 MHz

410 MHz

365 MHz

410 MHz

495 MHz

365 MHz

405 MHz

390 MHz

455 MHz

390 MHz

36 × 36-bit multiplier

Double mode

18 × 18-bit multiply adder

18 × 18-bit multiply adder with loop back (5)

18 × 18-bit multiply accumulator

18 × 18-bit multiply adder with chainout

Input Cascade Independent output of 4 18 × 18 bit multiplier

36-bit shift (32 bit data)

Notes to Table 1–20:

(1) Maximum is for fully pipelined block with round and saturation disabled.

(2) Pending silicon characterization.

(3) The DSP block implements eight independent 9 × 9-bit multipliers using a, b, c, and d for the top half of the DSP

block and e, f, g, and h for the bottom DSP half block multipliers.

(4) The DSP block implements six independent 12 × 12-bit multipliers using a, b, and d for the top half of the DSP half

block and e, f, and h for the bottom DSP half block multipliers.

(5) Maximum for non-pipelined block with loopback input registers disabled with round and saturation disabled.

HardCopy III Device Handbook, Volume 3

Chapter 1: DC and Switching Characteristics of HardCopy III Devices

1–15

Switching Characteristics

TriMatrix Memory Block Specifications

Table 1–21 describes the HardCopy III TriMatrix memory block specifications.

Table 1–21. HardCopy III TriMatrix Memory Block Performance Specifications – Preliminary (Part 1 of 2) (Note 1)

Memory

TriMatrix

Memory

Block Type

Mode

Max

500

465

485

475

460

480

475

312

Unit

Single port 16 × 10

1

MHz

Simple dual-port 16 × 20 single clock

ROM 64 × 10

MLAB

ROM 32 × 20

Single-port 8K × 1

Single-port 4K × 2 or 2K × 4

Single-port 1K × 9, 512 × 18, or 256 × 36

Simple dual-port, 8K × 1 single clock

Simple dual-port, 4K × 2 or 2K × 4, single clock

Simple dual-port, 1K × 9, 512 × 18, or 256 × 36, single clock

Simple dual-port, 8K × 1, 4K × 2, or 2K × 4 single clock, with the

read-during-write option set to “Old Data”

Simple dual-port, 1K × 9, 512 × 18, or 256 × 36, single clock, with the

read-during-write option set to “Old Data”

1

312

MHz

True dual-port, 8K × 1 single clock

1

440

480

460

295

MHz

True dual-port, 4K × 2 or 2K × 4, single clock

True dual-port, 1K × 9 or 512 × 18, single clock

M9K

True dual-port, 8K × 1, 4K × 2, or 2K × 4, single clock, with the

read-during-write option set to “Old Data”

True dual-port, 1K × 9 or 512 × 18, single clock, with the read-during-write

option set to “Old Data”

1

285

485

MHz

ROM 1P, 8K × 1, 4K × 2, or 2K × 4, single clock, with the read-during-write

option set to “Old Data”

ROM 1P, 1K × 9, 512 × 18, single clock, with the read-during-write option

set to “Old Data”

ROM 2P, 8K × 1, 4K × 2, or 2K × 4

ROM 2P, 1K × 9, or 512 × 18

1

485

800

MHz

ps

Min Pulse Width (Clock High Time)

—

HardCopy III Device Handbook, Volume 3

1–16

Chapter 1: DC and Switching Characteristics of HardCopy III Devices

Switching Characteristics

Table 1–21. HardCopy III TriMatrix Memory Block Performance Specifications – Preliminary (Part 2 of 2) (Note 1)

Memory

TriMatrix

Memory

Block Type

Mode

True dual-port 16K × 9 or 8K × 18, dual clock

True dual-port 4K × 36 dual clock

Simple dual-port 16K × 9 or 8K × 18, dual clock

Simple dual-port 4K × 36 or 2K × 72, dual clock

ROM 1 Port

Max

300

430

300

470

500

450

330

500

270

Unit

MHz

1

ROM 2 Port

Single-port 16K × 9 or 8K × 18

Single-port 4K × 36

M144K

True dual-port 16K × 9, 8K × 18, or 4K × 36, dual clock with the

read-during-write option set to “Old Data”

Simple dual-port 16K × 9, 8K × 18, 4K × 36, or 2K × 72, dual clock with the

read-during-write option set to “Old Data”

1

292

MHz

Simple dual-port 2K × 64 dual clock (with ECC)

Min Pulse Width (Clock High Time)

1

210

MHz

ps

—

1000

Note to Table 1–21:

(1) Pending silicon characterization.

JTAG Specifications

Table 1–22 shows the JTAG timing parameters and values for HardCopy III devices.

Refer to Figure 1–3 in the “HIGH-SPEED I/O Block” row in Table 1–33 for JTAG

timing requirements.

Table 1–22. HardCopy III JTAG Timing Parameters and Values – Preliminary

Symbol

Parameter

Min

30

14

1

Max

—

11

14

Unit

ns

t_JCP

t_JCH

t_JCL

TCK clock period

TCK clock high time

TCK clock low time

t_JPSU(TDI)

t_JPSU(TMS)

t_JPH

JTAG port setup time for TDI

JTAG port setup time for TMS

JTAG port hold time

3

5

t_JPCO

JTAG port clock to output

—

t_JPZX

JTAG port high impedance to valid output

JTAG port valid output to high impedance

t_JPXZ

Periphery Performance

This section describes the periphery performance, including high-speed I/O, external

memory interface, and OCT calibration block specifications.

HardCopy III Device Handbook, Volume 3

Chapter 1: DC and Switching Characteristics of HardCopy III Devices

1–17

Switching Characteristics

High-Speed I/O Specifications

Refer to Table 1–33 for definitions of high-speed timing specifications.

Table 1–23 shows the high-speed I/O timing for HardCopy III devices.

Table 1–23. High Speed I/O Specifications – Preliminary (Note 1), (2), (3)

Min

Typ

Max

Unit

Symbol

Conditions

Clock boost factor W = 2 to 32 (4)

5

—

625

600

MHz

f_HSCLK(input clock frequency) Clock boost factor W = 1 (SERDES bypassed)

Clock boost factor W = 1 (SERDES used)

5

150

—

717

MHz

SERDES factor J = 3 to 10

1250

Mbps

Dedicate LVDS-f_HSDR(data

SERDES factor J = 2, uses DDR registers

rate)

TBD (5)

1250

SERDES factor J = 1, uses SDR register

—

Dedicated LVDS-f_HSDRDPA(data

rate)

—

150

LVDS_E_3R-f_HSDR

—

340

200

Mbps

LVDS_E_1R-f_HSDR(data rate)

Transmitter

t_Xjitter

Total jitter for data rate, 600 Mbps - 1.25 Gbps

Total jitter for data rate, < 600 Mbps

All differential I/O standards

—

160

0.1

ps

UI

ps

Dedicated LVDS Output t_RISE

and t_FALL

200

t_DUTY

TX output clock duty cycle

All differential I/O standards

45

—

50

—

55

%

TCCS

100

ps

DPA mode

DPA run length

—

(5)

UI

Soft CDR mode

Soft CDR jitter tolerance

Soft CDR run length

Soft-CDR PPM tolerance

—

(5)

ps

UI

PPM

Non DPA mode

Sampling window

Notes to Table 1–23:

All differential I/O standards

—

(5)

ps

(1) When J = 3 to 10, the serializer/deserializer (SERDES) block is used.

(2) When J = 1 or 2, the SERDES block is bypassed.

(3) The minimum specification is dependent on the clock source (PLL and clock pin, for example) and the clock routing resource (global, regional,

or local) utilized. The I/O differential buffer and input register do not have a minimum toggle rate.

(4) The input clock frequency and the W factor must satisfy the following Left and Right PLL output frequency specification: 150 MHz input clock

frequency × W ≤ 1250 MHz.

(5) Pending silicon characterization.

HardCopy III Device Handbook, Volume 3

1–18

Chapter 1: DC and Switching Characteristics of HardCopy III Devices

Switching Characteristics

Table 1–24. DPA Lock Time Specifications – Preliminary (Note 1)

Standard

SPI-4

Training Pattern

00000000001111111111

00001111

Transition Density

Min Typ Max

Unit

10%

25%

TBD

—

Number of repetitions

Parallel Rapid I/O

10010000

50%

Miscellaneous

10101010

100%

01010101

Note to Table 1–24:

(1) Pending silicon characterization.

External Memory Interface Specifications

Table 1–25 through Table 1–30 list the external memory interface specifications for the

HardCopy III device family. Use these tables to perform memory interface timing

analysis.

Table 1–25. HardCopy III Maximum Clock Rate Support for External Memory Interfaces with

Half-Rate Controller – Preliminary (Note 1)

(MHz)

Memory Standards

DDR3 SDRAM

Top and Bottom I/O Banks

Left and Right I/O Banks

TBD

DDR2 SDRAM

DDR SDRAM

QDRII+ SRAM

QDRII SRAM

RLDRAM II

Note to Table 1–25:

(1) Pending silicon characterization.

Table 1–26. HardCopy III Maximum Clock Rate Support for External Memory Interfaces with

Full-Rate Controller – Preliminary (Note 1)

(MHz)

Memory Standards

DDR2 SDRAM

Top and Bottom I/O Banks

Left and Right I/O Banks

TBD

DDR SDRAM

Note to Table 1–26:

(1) Pending silicon characterization.

HardCopy III Device Handbook, Volume 3

Chapter 1: DC and Switching Characteristics of HardCopy III Devices

1–19

Switching Characteristics

External Memory I/O Timing Specifications

Table 1–27 and Table 1–28 list HardCopy III device timing uncertainties on the read

and write data paths. Use these specifications to determine timing margins for source

synchronous paths between the HardCopy III FPGA and the external memory device.

Refer to Figure 1–5 in the “SW (sampling window)” row in Table 1–33.

Table 1–27. Sampling Window (SW), Read Side – Preliminary (Note 1)

Sampling Window (ps)

Location (2)

Memory Type

DDR3

Setup

TBD

Hold

TBD

VIO

DDR2

VIO

DDR1

VIO

QDRII / II +

RLDRAM II

DDR3

VIO

HIO

DDR2

HIO

DDR1

QDRII / II +

RLDRAM

HIO

Notes to Table 1–27:

(1) Pending silicon characterization.

(2) VIO (vertical I/O) refers to I/Os in the top and bottom banks; HIO (horizontal I/O) refers to I/Os in the left and right

banks.

Table 1–28. Transmitter Channel-to-Channel Skew (TCCS), Write Side – Preliminary (Note 1)

TCCS (ps)

Location (2)

Memory Type

DDR3

Lead

TBD

Lag

TBD

VIO

DDR2

VIO

DDR1

VIO

QDRII / II +

RLDRAM II

DDR3

VIO

HIO

DDR2

HIO

DDR1

QDRII / II +

RLDRAM II

HIO

Notes to Table 1–28:

(1) Pending silicon characterization.

(2) VIO (vertical I/O) refers to I/Os in the top and bottom banks; HIO (horizontal I/O) refers to I/Os in the left and right

banks.

HardCopy III Device Handbook, Volume 3

1–20

Chapter 1: DC and Switching Characteristics of HardCopy III Devices

Switching Characteristics

DLL and DQS Logic Block Specifications

Table 1–29 describes the delay-locked loop (DLL) frequency range specifications for

HardCopy III devices.

Table 1–29. HardCopy III DLL Frequency Range Specifications – Preliminary (Note 1)

Frequency Mode

Frequency Range (MHz)

Resolution (Degrees)

0

1

2

3

4

5

6

TBD

22.5

30

36

45

30

36

45

Note to Table 1–29:

(1) Pending silicon characterization.

Table 1–30 describes the DQS phase offset delay per setting for HardCopy III devices.

Table 1–30. Average DQS Phase Offset Delay per Setting – Preliminary (Note 1), (2), (3), (4)

Min

Typ

Max

Unit

7

11

15

ps

Notes to Table 1–30:

(1) The valid settings for phase offset are –64 to +63 for frequency modes 0 to 3 and –32 to +31 for frequency modes

4 to 6.

(2) The typical value equals the average of the minimum and maximum values.

(3) The delay settings are linear with a cumulative delay variation of 20ps for all speed grades.

(4) Pending silicon characterization.

OCT Calibration Block Specifications

Table 1–31 shows the on-chip termination calibration block specifications for

HardCopy III devices.

Table 1–31. On-Chip Termination Calibration Block Specification – Preliminary

Symbol

OCTUSRCLK

t_OCTCAL

Description

Min

—

Typical

—

Max

20

Unit

MHz

Clock required by OCT calibration blocks

Number of OCTUSRCLK clock cycles required for OCT RS and

—

1000

—

cycles

RT calibration

t_OCTSHIFT

t_{RS_RT}

Number of OCTUSRCLK clock cycles required for OCT code to

shift out per OCT calibration block

—

28

—

cycles

ns

Time required to dynamically switch from R_Sto R_T

2.5

HardCopy III Device Handbook, Volume 3

Chapter 1: DC and Switching Characteristics of HardCopy III Devices

1–21

I/O Timing Model

Duty Cycle Distortion (DCD) Specifications

Table 1–32 lists the worst case DCD for HardCopy III devices. Detailed information on

duty cycle distortion are published after characterization.

Table 1–32. Duty Cycle Distortion on HardCopy III I/O Pins – Preliminary (Note 1), (2)

Symbol

Min

Max

Unit

Output Duty Cycle

Notes to Table 1–32:

45

55

%

(1) Preliminary DCD specification applies to clock outputs from PLLs, global clock tree, IOE driving dedicated, and

general purpose I/O pins.

(2) Detailed DCD specifications pending silicon characterization.

I/O Timing Model

The I/O timing specifications for HardCopy III devices will be available in a future

revision of the DC and Switching Characteristics chapter in volume 3 of the HardCopy III

Device Handbook.

Glossary

Table 1–33 shows the glossary for this chapter.

Table 1–33. Glossary Table

Letter

Subject

—

Definitions

A

B

C

D

—

Differential I/O

Standards

Figure 1–2. Receiver Input Waveforms

Single-Ended Waveform

Positive Channel (p) = V

IH

V

ID

Negative Channel (n) = V

Single-Ended Waveform

IL

V

CM

Positive Channel (p) = V

OH

Ground

V

OD

Negative Channel (n) = V

OL

V

CM

Differential Waveform

Ground

V

ID

p − n = 0 V

Differential Waveform

V

ID

V

OD

p − n = 0 V

Transmitter Output Waveforms

V

OD

E

F

—

f_HSCLK

HIGH-SPEED I/O Block: High-speed receiver/transmitter input and output clock frequency.

f_HSDR

HIGH-SPEED I/O Block: Maximum/minimum LVDS data transfer rate (f_HSDR= 1/TUI),

non-DPA.

f_HSDRDPA

HIGH-SPEED I/O Block: Maximum/minimum LVDS data transfer rate (f_HSDRDPA= 1/TUI), DPA.

G

H

—

HardCopy III Device Handbook, Volume 3

1–22

Chapter 1: DC and Switching Characteristics of HardCopy III Devices

Glossary

Table 1–33. Glossary Table

Letter

Subject

Definitions

I

—

J

HIGH-SPEED I/O Block: Deserialization factor (width of parallel data bus).

JTAG Timing

Figure 1–3. JTAG Timing Specifications

Specifications

TMS

TDI

t_JCP

t_JCH

t_JCL

t_JPH

t_JPSU

TCK

TDO

t_JPZX

t_JPXZ

t_JPCO

K

L

—

M

N

O

P

PLL

The block diagram shown in the following figure highlights the PLL Specification parameters:

Specifications

Figure 1–4. Diagram of PLL Specifications (Note 1)

Switchover

CLKOUT Pins

f_{OUT_EXT}

CLK

f_IN

f_INPFD

N

GCLK

RCLK

Counters

C0..C9

f_VCO

VCO

f_OUT

PFD

CP

LF

Core Clock

M

Key

External Feedback

Reconfigurable in User Mode

Note:

(1) Core Clock can only be fed by dedicated clock input pins or PLL outputs.

Q

R

—

R_L

Receiver differential input discrete resistor (external to HardCopy III device).

HardCopy III Device Handbook, Volume 3

Chapter 1: DC and Switching Characteristics of HardCopy III Devices

1–23

Glossary

Table 1–33. Glossary Table

Letter

Subject

Definitions

S

SW (sampling

window)

The period of time during which the data must be valid in order to capture it correctly. The

setup and hold times determine the ideal strobe position within the sampling window.

Figure 1–5. Timing Diagram

Bit Time

Sampling Window

(SW)

RSKM

0.5 x TCCS

Single-ended

Voltage

Referenced I/O

Standard

The JEDEC standard for SSTl and HSTL I/O standards defines both the AC and DC input

signal values. The AC values indicate the voltage levels at which the receiver must meet its

timing specifications. The DC values indicate the voltage levels at which the final logic state

of the receiver is unambiguously defined. Once the receiver input has crossed the AC value,

the receiver is changed to the new logic state.

The new logic state is maintained as long as the input stays beyond the DC threshold. This

approach is intended to provide predictable receiver timing in the presence of input

waveform ringing.

Figure 1–6. Single-Ended Voltage Referenced I/O Standard

V_CCIO

V_OH

V_{IH AC}

(

)

V_IH(DC)

V_REF

V_IL(DC)

V_IL(AC

)

V_OL

V_SS

T

t_C

High-speed receiver and transmitter input and output clock period.

TCCS

(channel-to-

channel-skew)

The timing difference between the fastest and the slowest output edges, including t_CO

variation and clock skew, across channels driven by the same PLL. The clock is included in

the TCCS measurement (refer to Figure 1–5 under S in this table).

t_DUTY

HIGH-SPEED I/O Block: Duty cycle on high-speed transmitter output clock.

Timing Unit Interval (TUI)

The timing budget allowed for skew, propagation delays, and data sampling window. (TUI =

1/(Receiver Input Clock Frequency Multiplication Factor) = t_C/w)

t_{FA LL}

Signal high-to-low transition time (80-20%)

Cycle-to-cycle jitter tolerance on PLL clock input

Period jitter on general purpose I/O driven by a PLL

Period jitter on dedicated clock output driven by a PLL

Signal low-to-high transition time (20–80%)

—

t_INCCJ

t_{OUTPJ_IO}

t_{OUTPJ_DC}

t_RISE

U

—

HardCopy III Device Handbook, Volume 3

1–24

Chapter 1: DC and Switching Characteristics of HardCopy III Devices

Referenced Documents

Table 1–33. Glossary Table

Letter

Subject

V_CM(DC)

Definitions

V

DC common mode input voltage.

V_ICM

V_ID

Input common mode voltage: The common mode of the differential signal at the receiver.

Input differential voltage swing: The difference in voltage between the positive and

complementary conductors of a differential transmission at the receiver.

V_DIF(AC)

V_DIF(DC)

V_IH

AC differential input voltage: Minimum AC input differential voltage required for switching.

DC differential input voltage: Minimum DC input differential voltage required for switching.

Voltage input high: The minimum positive voltage applied to the input that will be accepted by

the device as a logic high.

V_IH(AC)

V_IH(DC)

V_IL

High-level AC input voltage

High-level DC input voltage

Voltage input low: The maximum positive voltage applied to the input that will be accepted by

the device as a logic low.

V_IL(AC)

V_IL(DC)

V_OCM

Low-level AC input voltage

Low-level DC input voltage

Output common mode voltage: The common mode of the differential signal at the

transmitter.

V_OD

W

Output differential voltage swing: The difference in voltage between the positive and

complementary conductors of a differential transmission at the transmitter.

W

X

Y

Z

HIGH-SPEED I/O BLOCK: Clock boost factor

—

Referenced Documents

This chapter references the following documents:

■

Power Play Early Power Estimator User Guide

PowerPlay Power Analysis chapter in volume 3 of the Quartus II Device Handbook

Document Revision History

Table 1–34 shows the revision history for this document.

Table 1–34. Document Revision History

Date and Document Version

Changes Made

■ Updated Table 1–3.

■ Updated Table 1–19.

Summary of Changes

December 2008, v2.0

—

■ Updated Table 1–23.

■ Made minor editorial changes.

Initial release.

May 2008, v1.0

—

HardCopy III Device Handbook, Volume 3


型号：	HC351
厂家：	ALTERA CORPORATION
描述：	HardCopy III Device 的HardCopy III器件
文件：	总26页 (文件大小：582K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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