440GP [AMCC]
Power PC 440GP Embedded Processor; 的Power PC 440GP嵌入式处理器
| 型号： | 440GP |
| 厂家： | 
APPLIED MICRO CIRCUITS CORPORATION |
| 描述： | Power PC 440GP Embedded Processor |
| 文件： | 总83页 (文件大小：1393K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Part Number 440GP
Revision 1.07 – October 4, 2007
Data Sheet
440GP
Power PC 440GP Embedded Processor
Features
• PowerPC® 440 processor core operating up to
500MHz with 32KB I- and D-caches
• Two Ethernet 10/100Mbps half- or full-duplex
interfaces. Operational modes supported are MII
and RMII.
• On-chip 8 KB SRAM
• Programmable Interrupt Controller supports
interrupts from a variety of sources.
• Selectable processor:bus clock ratios of 3:1, 4:1,
5:1, 5:2, 7:2
• Programmable General Purpose Timers (GPT)
• Two serial ports (16750 compatible UART)
• Two IIC interfaces
• Double Data Rate (DDR) Synchronous DRAM
(SDRAM) 32/64-bit interface operating up to
133MHz
• External Peripheral Bus for up to eight devices
with external mastering
• General Purpose I/O (GPIO) interface available
• JTAG interface for board level testing
• DMA support for external peripherals, internal
UART and memory
• Internal Processor Local Bus (PLB) runs at DDR
SDRAM interface frequency
• PCI-X V1.0a interface (32 or 64 bits, up to
133MHz) with support for conventional PCI V2.2
• Processor can boot from PCI memory
• Available in ceramic (RoHs and non-RoHS
compliant versions) and plastic packages.
Description
Designed specifically to address high-end embedded
applications, the PowerPC 440GP (PPC440GP)
provides a high-performance, low power solution that
interfaces to a wide range of peripherals by
incorporating on-chip power management features
and lower power dissipation.
Technology: CMOS SA-27E, 0.18μm (0.11 L )
eff
Packages: 25mm, 552-ball Ceramic Ball Grid Array
(CBGA) or Plastic Ball Grid Array (PBGA) in standard
or RoHS compliant versions
Power (estimated): Less than:
4.0W in normal mode
This chip contains a high-performance RISC
processor core, DDR SDRAM controller,8KB SRAM,
PCI-X bus interface, Ethernet interfaces, control for
external ROM and peripherals, DMA with scatter-
gather support, serial ports, IIC interface, and general
purpose I/O.
1.0W in sleep mode
Supply voltages required: 3.3V, 2.5V, 1.8V
AMCC
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Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Contents
Ordering and PVR Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Address Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
PowerPC 440 Processor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Internal Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
PCI-X Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
DDR SDRAM Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
On-Chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
External Peripheral Bus Controller (EBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Ethernet Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Serial Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
IIC Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
General Purpose Timers (GPT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
General Purpose IO (GPIO) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Universal Interrupt Controller (UIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Signal Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Heat Sink Mounting Information (Ceramic Package Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Spread Spectrum Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
DDR SDRAM I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
DDR SDRAM Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
DDR SDRAM Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Serial EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
2
AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Figures
PPC440GP Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
25mm, 552-Ball Ceramic (CBGA) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
25mm, 552-Ball Plastic (FC-PBGA) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Heat Sink Attached With Spring Clip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Heat Sink Attached With Adhesive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Input Setup and Hold Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Output Delay and Float Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
DDR SDRAM Simulation Signal Termination Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
DDR SDRAM Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
DDR SDRAM MemClkOut0 and Read Clock Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
DDR SDRAM Read Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
DDR SDRAM Read Cycle Timing—Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
DDR SDRAM Read Cycle Timing—Example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
DDR SDRAM Read Cycle Timing—Example 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Tables
Order Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
System Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
DCR Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Signals Listed Alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Signals Listed by Ball Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Signal Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Package Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
DC Power Supply Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Clocking Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Peripheral Interface Clock Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
I/O Specifications—All Speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
I/O Specifications—400, 466, and 500MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
DDR SDRAM Output Driver Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
I/O Timing—DDR SDRAM T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
DS
I/O Timing—DDR SDRAM T , T , and T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
HA
SK SA
I/O Timing—DDR SDRAM T and T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
SD
HD
I/O Timing—DDR SDRAM T
and T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
DIN
SIN
Strapping Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
AMCC
3
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Ordering and PVR Information
For information on the availability of the following parts, contact your local AMCC sales office.
Order Part Numbers
Product
Name
Order Part Number
(See Notes and Key drawing)
Processor
Frequency
Rev
Level
Package
PVR Value
JTAG ID
PPC440GP
PPC440GP
PPC440GP
PPC440GP
PPC440GP
PPC440GP
PPC440GP
PPC440GP
PPC440GP
PPC440GP
PPC440GP
PPC440GP
PPC440GP
PPC440GP
PPC440GP
PPC440GP
PPC440GP
PPC440GP
Notes:
PPC440GP-3CC333C
PPC440GP-3CC400C
PPC440GP-3CC400CZ
PPC440GP-3CC400E
PPC440GP-3CC400EZ
PPC440GP-3CC466C
PPC440GP-3CC466CZ
PPC440GP-3CC500C
PPC440GP-3CC500CZ
PPC440GP-3FC400C
PPC440GP-3RC333C
PPC440GP-3RC400C
PPC440GP-3RC400CZ
PPC440GP-3RC400E
PPC440GP-3RC466C
PPC440GP-3RC466CZ
PPC440GP-3RC500C
PPC440GP-3RC500CZ
333MHz
400MHz
400MHz
400MHz
400MHz
466MHz
466MHz
500MHz
500MHz
400MHz
333MHz
400MHz
400MHz
400MHz
466MHz
466MHz
500MHz
500MHz
25mm, 552 CBGA
25mm, 552 CBGA
25mm, 552 CBGA
25mm, 552 CBGA
25mm, 552 CBGA
25mm, 552 CBGA
25mm, 552 CBGA
25mm, 552 CBGA
25mm, 552 CBGA
25mm, 552 PBGA
25mm, 552 CBGA
25mm, 552 CBGA
25mm, 552 CBGA
25mm, 552 CBGA
25mm, 552 CBGA
25mm, 552 CBGA
25mm, 552 CBGA
25mm, 552 CBGA
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
0x40120481
0x40120481
0x40120481
0x40120481
0x40120481
0x40120481
0x40120481
0x40120481
0x40120481
0x40120481
0x40120481
0x40120481
0x40120481
0x40120481
0x40120481
0x40120481
0x40120481
0x40120481
0x22052049
0x22052049
0x22052049
0x22052049
0x22052049
0x22052049
0x22052049
0x22052049
0x22052049
0x22052049
0x22052049
0x22052049
0x22052049
0x22052049
0x22052049
0x22052049
0x22052049
0x22052049
1. Package code: C = leaded ceramic, F = plastic, R = reduced-lead ceramic (RoHS compliant),.
2. Case Temperature Range code: C = -40 °C to +85 °C, E = -40 °C to +105 °C for C package and -40 °C to +100 °C for F package.
3. Z at the end of the Order Part Number indicates a tape-and-reel shipping package. Otherwise, the chips are shipped in a tray.
4. Revision code: C = rev 2.1.
Each part number contains a revision code. This is the die mask revision number and is included in the part
number for identification purposes only.
The PVR (Processor Version Register) and the JTAG ID register are software accessible (read-only) and contain
information that uniquely identifies the part. Refer to the PPC440GP User’s Manual for details on accessing these
registers.
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AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Order Part Number Key
PPC440GP-3CC500Ex
Shipping Package
Part Number
Case Temperature Range
Grade 3 Reliability
Processor Speed
Revision Level
Package
AMCC
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Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
PPC440GP Functional Block Diagram
Universal
Interrupt
Controller
Clock
Control
Reset
Power
Mgmt
DCRs
Timers
MMU
UART
IIC
PPC440
Processor Core
GP
Timers
GPIO
x2
x2
DCR Bus
45 internal
13 external
Trace
JTAG
On-chip Peripheral Bus (OPB)
Arb
32KB
I-Cache
32KB
D-Cache
DMA
OPB
Bridge
SRAM
8KB
Controller
(4-Channel)
Processor Local Bus (PLB)
External
Bus
Controller
External
Bus Master
Controller
Ethernet
x2
MAL
1 MII
or
2 RMII
66MHz max
32-bit addr
32-bit data
DDR SDRAM
Controller
PCI-X
Bridge
133MHz max
133MHz max
13-bit addr
32/64-bit data
The PPC440GP is designed using the IBM® Microelectronics Blue Logic™ methodology in which major functional
blocks are integrated together to create an application-specific product (ASIC). This approach provides a
consistent way to create complex ASICs using IBM CoreConnect Bus™ Architecture.
Note: IBM CoreConnect buses provide:
• 128-bit PLB interfaces up to 133.33MHz
• 32-bit OPB interfaces up to 66.66MHz, 266MB/s
Address Maps
The PPC440GP incorporates two address maps. The first is a fixed processor system memory address map. This
address map defines the possible contents of various address regions which the processor can access. The
second address map is for Device Configuration Registers (DCRs). The DCRs are accessed by software running
on the PPC440GP processor through the use of mtdcr and mfdcr instructions.
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AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
System Memory Address Map (Sheet 1 of 2)
Function
Sub Function
Start Address
0 0000 0000
0 8000 0000
0 8000 2000
1 0000 0000
1 4000 0000
1 4000 0200
1 4000 0208
1 4000 0300
1 4000 0308
1 4000 0400
1 4000 0420
1 4000 0500
1 4000 0520
1 4000 0600
1 4000 0640
1 4000 0700
1 4000 0780
1 4000 0790
1 4000 0790
1 4000 0800
1 4000 0900
1 4000 0A00
1 4000 0B00
1 F000 0000
End Address
0 7FFF FFFF
0 8000 1FFF
0 FFFF FFFF
1 3FFF FFFF
1 4000 01FF
1 4000 0207
1 4000 02FF
1 4000 0307
1 4000 03FF
1 4000 041F
1 4000 04FF
1 4000 051F
1 4000 05FF
1 4000 063F
1 4000 06FF
1 4000 077F
1 4000 078F
1 4000 079F
1 4000 07FF
1 4000 08FF
1 4000 09FF
1 4000 0AFF
1 EFFF FFFF
1 FFDF FFFF
Size
2GB
8KB
DDR SDRAM
SRAM
Local Memory1
Reserve
EBC
1GB
8B
Reserved
UART0
Reserved
UART1
8B
Reserved
IIC0
32B
32B
64B
Reserved
IIC1
Reserved
OPB Arbiter
Reserved
GPIO Controller
Internal Peripherals
128B
16B
Ethernet PHY ZMII
Ethernet PHY GMII
Reserved
16B
Ethernet 0 Controller
Ethernet 1 Controller
General Purpose Timer
Reserved
256B
256B
256B
Expansion ROM2
Boot ROM2, 3
254MB
2MB
1 FFE0 0000
1 FFFF FFFF
AMCC
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Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
System Memory Address Map (Sheet 2 of 2)
Function
Sub Function
Start Address
2 0000 0000
2 0800 0000
2 0C00 0000
2 0EC0 0000
2 0EC0 0008
2 0EC8 0000
2 0EC8 0100
2 0ED0 0000
2 0EE0 0000
End Address
2 07FF FFFF
2 0BFF FFFF
2 0EBF FFFF
2 0EC0 0007
2 0EC7 FFFF
2 0EC8 00FF
2 0EC8 00FF
2 0EDF FFFF
F FFFF FFFF
Size
64MB
8B
Reserved
PCI-X I/O
Reserved
PCI-X External Configuration Registers
Reserved
PCI-X
PCI-X Bridge Core Configuration Registers
Reserved
256B
PCI-X Special Cycle
1MB
PCI-X Memory
55.76 GB
Notes:
1. DDR SDRAM and on-chip SRAM can be located anywhere in the Local Memory area of the memory map.
2. The Boot ROM and Expansion ROM areas of the memory map are intended for use by ROM or Flash-type devices. While locating
volatile DDR SDRAM and SRAM in this region is supported, use of these regions for this purpose is not recommended.
3. When the optional boot from PCI-X memory is selected, the PCI-X Boot ROM address space begins at 2 FFFE 0000 (128 KB).
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AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
DCR Address Map 4KB of Device Configuration Registers
Function
Total DCR Address Space1
Start Address
End Address
Size
1KW (4KB)1
000
3FF
By function:
Reserved
000
010
012
014
016
020
030
080
090
0A0
0A8
0B0
0B8
0C0
0D0
0E0
0F0
100
140
180
200
00F
011
013
015
01F
02F
07F
08F
09F
0A7
0AF
0B7
0BF
0CF
0DF
0EF
0FF
13F
17F
1FF
3FF
16W
2W
Memory Controller
External Bus Controller
External Bus Master I/F
PLB Performance Monitor
SRAM
2W
2W
10W
16W
80W
16W
16W
8W
Reserved
PLB
PLB to OPB Bridge Out
Reserved
OPB to PLB Bridge In
Power Management
Reserved
8W
8W
8W
Interrupt Controller 0
Interrupt Controller 1
Clock, Control, and Reset
Reserved
16W
16W
16W
16W
64W
64W
128W
512W
DMA Controller
Reserved
Ethernet MAL
Reserved
Notes:
1. DCR address space is addressable with up to 10 bits (1024 or 1K unique addresses). Each unique address represents a single 32-bit
(word) register. One kiloword (1024W) equals 4KB (4096 bytes).
AMCC
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Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
PowerPC 440 Processor Core
The PowerPC 440 processor core is designed for high-end applications: RAID controllers, routers, switches,
printers, set-top boxes, etc. It is the first processor core to implement the Book E PowerPC embedded architecture
and the first to use the 128-bit version of IBM’s on-chip CoreConnect Bus Architecture.
Features include:
• Up to 500MHz operation
• PowerPC Book E architecture
• 32KB I-cache, 32KB D-cache
• Three logical regions in D-cache: locked, transient, normal
• D-cache full line flush capability
• 41-bit virtual address, 36-bit (64GB) physical address
• Superscalar, out-of-order execution
• 7-stage pipeline
• 3 execution pipelines
• Dynamic branch prediction
• Memory management unit
- 64-entry, full associative, unified TLB
- Separate instruction and data micro-TLBs
- Storage attributes for write-through, cache-inhibited, guarded, and big or little endian
• Debug facilities
- Multiple instruction and data range breakpoints
- Data value compare
- Single step, branch, and trap events
- Non-invasive real-time trace interface
• 24 DSP instructions
- Single-cycle multiply and multiply-accumulate
- 32 x 32 integer multiply
- 16 x 16 -> 32-bit MAC
Internal Buses
The PowerPC 440GP features three IBM standard on-chip buses: the Processor Local Bus (PLB), the On-Chip
Peripheral Bus (OPB), and the Device Control Register Bus (DCR). The high performance, high bandwidth cores
such as the PowerPC 440 processor core, the DDR SDRAM memory controller, and the PCI-X bridge connect to
the PLB. The OPB hosts lower data rate peripherals. The daisy-chained DCR provides a lower bandwidth path for
passing status and control information between the processor core and the other on-chip cores.
Features include:
• PLB
- 128-bit implementation of the PLB architecture
- Separate and simultaneous read and write data paths
- 36-bit address
- Simultaneous control, address, and data phases
- Four levels of pipelining
- Byte enable capability supporting unaligned transfers
- 32- and 64-byte burst transfers
10
AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
- 133MHz, maximum 4.2GB/s (simultaneous read and write)
- Processor:bus clock ratios of 3:1, 4:1, 5:1, 5:2, and 7:2
• OPB
- Dynamic bus sizing 32-, 16-, and 8-bit data path
- Separate and simultaneous read and write data paths
- 36-bit address
- 66.66MHz, maximum 266MB/s
• DCR
- 32-bit data path
- 10 bit address
On-Chip SRAM
Features include:
• One physical bank of 8KB
• Memory cycles supported:
- Single beat read and write, 1 to 16 bytes
- 32- and 64-byte burst transfers
- Guarded memory accesses
• Sustainable 2.1GB/s peak bandwidth at 133MHz
PCI-X Interface
The PCI-X interface allows connection of PCI and PCI-X devices to the PowerPC processor and local memory.
This interface is designed to Version 1.0a of the PCI-X Specification and supports 32- and 64-bit PCI-X buses. PCI
32/64-bit conventional mode, compatible with PCI Version 2.2, is also supported.
Reference Specifications:
• PowerPC CoreConnect Bus (PLB) version PLB4
• PCI Specification Version 2.2
• PCI Bus Power Management Interface Specification Version 1.1
Features include:
• PCI-X 1.0a
- Split transactions
- Frequency to 133MHz
- 32- and 64-bit bus
• PCI 2.2 backward compatibility
- Frequency to 66MHz
- 32- and 64-bit bus
• Can be the PCI Host Bus Bridge or an Adapter Device's PCI interface
• Internal PCI arbitration function, supporting up to six external devices, that can be disabled for use with an
external arbiter
• Support for Message Signaled Interrupts
• Simple message passing capability
• Asynchronous to the PLB
• PCI Power Management 1.1
• PCI register set addressable both from on-chip processor and PCI device sides
AMCC
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Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
• Ability to boot from PCI-X bus memory
• Error tracking/status
• Supports initiation of transfer to the following address spaces:
- Single beat I/O reads and writes
- Single beat and burst memory reads and writes
- Single beat configuration reads and writes (type 0 and type 1)
- Single beat special cycles
DDR SDRAM Memory Controller
The Double Data Rate (DDR) SDRAM memory controller supports industry standard 184-pin DIMMs and other
discrete devices. Up to four 512MB logical banks are supported in limited configurations. Global memory timings,
address and bank sizes, and memory addressing modes are programmable.
Features include:
• Registered and non-registered industry standard DIMMs and other discrete devices
• 32- or 64-bit memory interface with optional 8-bit ECC (SEC/DED)
• Sustainable 2.1GB/s peak bandwidth at 133MHz
• SSTL_2 logic
• 1 to 4 chip selects
• CAS latencies of 2, 2.5 and 3 supported
• PC200/266 support
• Page mode accesses (up to eight open pages) with configurable paging policy
• Programmable address mapping and timing
• Hardware and software initiated self-refresh
• Power management (self-refresh, suspend, sleep)
External Peripheral Bus Controller (EBC)
Features include:
• Up to eight ROM, EPROM, SRAM, Flash memory, and slave peripheral I/O banks supported
• Up to 66.66MHz operation (266MB/s)
• Burst and non-burst devices
• 8-, 16-, 32-bit byte-addressable data bus
• 32-bit address, 4GB address space
• Peripheral Device pacing with external “Ready”
• Latch data on Ready, synchronous or asynchronous
• Programmable access timing per device
- 256 Wait States for non-burst
- 32 Burst Wait States for first access and up to 8 Wait States for subsequent accesses
- Programmable CSon, CSoff relative to address
- Programmable OEon, WEon, WEoff (1 to 4 clock cycles) relative to CS
• Programmable address mapping
12
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Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
• External master interface
- Write posting from external master
- Read prefetching on PLB for external master reads
- Bursting capable from external master
- Allows external master access to all non-EBC PLB slaves
- External master can control EBC slaves for own access and control
Ethernet Controller Interface
Ethernet support provided by the PPC440GP interfaces to the physical layer, but the PHY is not included on the
chip.
Features include:
• One or two interfaces running in full- and half-duplex modes at 10Mb/s or 100Mb/s
- One full Media Independent Interface (MII) with 4-bit parallel data transfer
- Two Reduced Media Independent Interfaces (RMII) with 2-bit parallel data transfer
DMA Controller
Features include:
• Supports the following transfers:
- Memory-to-memory transfers
- Buffered peripheral to memory transfers
- Buffered memory to peripheral transfers
• Four channels
• Scatter/Gather capability for programming multiple DMA operations
• 8-, 16-, 32-bit peripheral support (OPB and external)
• 64-bit addressing
• Address increment or decrement
• Supports internal and external peripherals
• Support for memory mapped peripherals
• Support for peripherals running on slower frequency buses
Serial Port
Features include:
• One 8-pin UART and one 4-pin UART interface provided
• Selectable internal or external serial clock to allow wide range of baud rates
• Register compatibility with 16750 register set
• Complete status reporting capability
• Fully programmable serial-interface characteristics
• Supports DMA using internal DMA engine
AMCC
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Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
IIC Bus Interface
Features include:
• Two IIC interfaces provided
2
• Support for Philips® Semiconductors I C Specification, dated 1995
• Operation at 100kHz or 400kHz
• 8-bit data
• 10- or 7-bit address
• Slave transmitter and receiver
• Master transmitter and receiver
• Multiple bus masters
• Supports fixed V IIC interface
DD
• Two independent 4 x 1 byte data buffers
• Twelve memory-mapped, fully programmable configuration registers
• One programmable interrupt request signal
• Provides full management of all IIC bus protocols
• Programmable error recovery
General Purpose Timers (GPT)
Provides a separate time base counter and additional system timers in addition to those defined in the processor
core.
• 32-bit Time Base Counter driven by the OPB bus clock
• Five 32-bit compare timers
General Purpose IO (GPIO) Controller
• Controller functions and GPIO registers are programmed and accessed via memory-mapped OPB bus master
accesses.
• 31 of the 32 GPIOs are pin-shared with other functions. DCRs control whether a particular pin that has GPIO
capabilities acts as a GPIO or is used for another purpose.
• Each GPIO output is separately programmable to emulate an open drain driver (that is, drives to zero,
tri-stated if output bit is 1).
14
AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Universal Interrupt Controller (UIC)
TwoUniversal Interrupt Controllers (UIC) are available. They provide control, status, and communications
necessary between the external and internal sources of interrupts and the on-chip PowerPC processor.
Note: Processor specific interrupts (for example, page faults) do not use UIC resources.
Features include:
• 13 external interrupts
• 45 internal interrupts
• Edge triggered or level-sensitive
• Positive or negative active
• Non-critical or critical interrupt to the on-chip processor core
• Programmable interrupt priority ordering
• Programmable critical interrupt vector for faster vector processing
JTAG
Features include:
• IEEE 1149.1 Test Access Port
• IBM RISCWatch Debugger support
• JTAG Boundary Scan Description Language (BSDL)
AMCC
15
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
25mm, 552-Ball Ceramic (CBGA) Package
Top View
Chip
A1 Corner
Part Number
Lot Number
Capacitor
Notes: 1. All dimensions are in mm.
2. RoHS compliant reduced-lead package available.
3. Reduced-lead package dimensions are in parentheses (dimension).
Bottom View
25.0 0.2
23.0
1.95 MAX
(1.98)
1.65 MIN
AD
AB
Y
V
T
1.00 TYP
(1.62)
AC
AA
W
U
R
P
25.0 0.2
N
L
8.04
M
K
H
F
D
B
J
G
E
C
A
19 21 23
1
3
5
7
9 11 13 15 17
0.8 TYP
(0.5 0.1)
8 10
6
12 14
16 18
4
22
20 24
2
3.80 MAX
(3.488)
0.8 0.04 SOLDERBALL x 552
(0.7 0.1)
16
AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
25mm, 552-Ball Plastic (FC-PBGA) Package
Top View
A1 Corner
1
24
A
®
PPC440GP
Part Number
3xCfffx
AAAAAAAA
Lot Number
AD
Note: All dimensions are in mm.
Bottom View
25.0
23.0
1.214 REF
0.3
AD
AB
Y
V
T
1.00 TYP
AC
AA
W
U
1
R
P
25.0
N
L
23.0
7.75
M
K
H
F
D
B
J
G
E
C
A
19 21 23
1
3
5
7
9 11 13 15 17
8 10
6
12 14
16 18
4
22
20 24
2
0.5 0.1
3.191 0.17
0.508 REF
0.66 0.1 SOLDERBALL x 552
AMCC
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Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signal Lists
The following table lists all the external signals in alphabetical order and shows the ball (pin) number on which the
signal appears. Multiplexed signals are shown with the default signal (following reset) not in brackets and the
alternate signal in brackets. Multiplexed signals appear alphabetically multiple times in the list—once for each
signal name on the ball. The page number listed gives the page in “Signal Functional Description” on page 48
where the signals in the indicated interface group begin. In cases where signals in the same interface group (for
example, Ethernet) have different names to distinguish variations in the mode of operation, the names are
separated by a comma with the primary name appearing first. These signals are listed only once, and appear
alphabetically by the primary name.
Signals Listed Alphabetically (Sheet 1 of 22)
Signal Name
Ball
J01
Interface Group
Page
AGND
AGND
AGND
AMVDD
J24
Power—Analog ground
54
AA11
AB11
Power—MemClkOut PLL analog voltage
Power—PCI-X PLL analog voltage
Power—SysClk PLL analog voltage
54
54
54
APVDD
ASVDD
G01
G24
AA16
AD09
AB15
W14
AD11
AD05
F14
BA0
DDR SDRAM
49
BA1
BankSel0
BankSel1
BankSel2
BankSel3
[BE0]PCIXC0
[BE1]PCIXC1
[BE2]PCIXC2
[BE3]PCIXC3
[BE4]PCIXC4
[BE5]PCIXC5
[BE6]PCIXC6
[BE7]PCIXC7
BusReq
DDR SDRAM
49
E16
C19
F20
PCI-X
48
C08
C03
G09
F09
AA24
AB05
AD17
AB10
Y09
External Master Peripheral
DDR SDRAM
51
49
CAS
ClkEn0
ClkEn1
DDR SDRAM
49
ClkEn2
ClkEn3
W09
18
AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signals Listed Alphabetically (Sheet 2 of 22)
Signal Name
Ball
T16
Interface Group
Page
DM0
DM1
AA18
AB14
P13
DM2
DM3
DM4
AA09
AA07
Y03
DDR SDRAM
49
DM5
DM6
DM7
V03
DM8
AC05
N05
DMAAck0
DMAAck1
DMAAck2
DMAAck3
DMAReq0
DMAReq1
DMAReq2
DMAReq3
DQS0
P07
External Slave Peripheral
External Slave Peripheral
50
50
P06
P11
R03
M11
N11
P01
AC20
AC16
AC14
AB13
AC11
AC09
Y04
DQS1
DQS2
DQS3
DQS4
DDR SDRAM
49
DQS5
DQS6
DQS7
T01
DQS8
AA05
L07
DrvrInh1
DrvrInh2
System
System
53
53
A05
AMCC
19
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signals Listed Alphabetically (Sheet 3 of 22)
Signal Name
Ball
AB07
AB06
AD06
W07
U09
AC03
AB04
AD04
J07
Interface Group
Page
ECC0
ECC1
ECC2
ECC3
ECC4
ECC5
ECC6
ECC7
DDR SDRAM
49
EMCCD, EMC1RxErr
EMCCrS, EMC0CrSDV
EMCMDClk
Ethernet
Ethernet
Ethernet
Ethernet
Ethernet
49
49
49
49
49
K07
J08
EMCMDIO
L05
EMCRxClk
J02
EMCRxD0, EMC0RxD0
EMCRxD1, EMC0RxD1
EMCRxD2, EMC1RxD0
EMCRxD3, EMC1RxD1
EMCRxDV, EMC1CrSDV
EMCRxErr, EMC0RxErr
EMCTxClk, EMCRefClk
EMCTxD0, EMC0TxD0
EMCTxD1, EMC0TxD1
EMCTxD2, EMC1TxD0
EMCTxD3, EMC1TxD1
EMCTxEn, EMC0TxEn
EMCTxErr, EMC1TxEn
EOT0/TC0
G03
E01
A07
H09
K01
K03
J06
Ethernet
49
Ethernet
Ethernet
Ethernet
49
49
49
L09
K05
J04
Ethernet
49
J03
L06
Ethernet
Ethernet
49
49
C05
R16
P15
P16
M16
AA22
AB23
T17
EOT1/TC1
External Slave Peripheral
50
EOT2/TC2
EOT3/TC3
ExtAck
External Master Peripheral
External Master Peripheral
External Master Peripheral
51
51
51
ExtReq
ExtReset
20
AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signals Listed Alphabetically (Sheet 4 of 22)
Signal Name
Ball
B06
B10
B13
B17
B21
D04
D08
D12
D15
D19
D23
F02
F06
F10
F13
F17
F21
H04
H08
H12
H15
H19
H23
K02
K06
K10
K13
K17
K21
M04
Interface Group
Page
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Power
54
AMCC
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Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signals Listed Alphabetically (Sheet 5 of 22)
Signal Name
Ball
M08
M12
M15
M19
M23
N02
N06
N10
N13
N17
N21
R04
R08
R12
R15
R19
R23
U02
U06
U10
U13
U17
U21
W04
W08
W12
W15
W19
W23
Interface Group
Page
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Power
54
22
AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signals Listed Alphabetically (Sheet 6 of 22)
Signal Name
Ball
Interface Group
Page
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AA02
AA06
AA10
AA13
AA17
AA21
AC04
AC08
AC12
AC15
AC19
Power
54
AMCC
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Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signals Listed Alphabetically (Sheet 7 of 22)
Signal Name
Ball
N18
L20
P20
L18
N14
M20
M14
P18
N20
P22
V18
P14
C18
J16
Interface Group
Page
[GPIO00]IRQ00
[GPIO01]IRQ01
[GPIO02]IRQ02
[GPIO03]IRQ03
[GPIO04]IRQ04
[GPIO05]IRQ05
[GPIO06]IRQ06
[GPIO07]IRQ07
[GPIO08]IRQ08
[GPIO09]IRQ09
[GPIO10]IRQ10
GPIO11
[GPIO12]UART1_Rx
[GPIO13]UART1_Tx
[GPIO14]UART1_DSR/CTS
[GPIO15]UART1_RTS/DTR
[GPIO16]IIC1SClk
[GPIO17]IIC1SDA
[GPIO18]TrcBS0
[GPIO19]TrcBS1
[GPIO20]TrcBS2
[GPIO21]TrcES0
[GPIO22]TrcES1
[GPIO23]TrcES2
[GPIO24]TrcES3
[GPIO25]TrcES4
[GPIO26]TrcTS0
[GPIO27]TrcTS1
[GPIO28]TrcTS2
[GPIO29]TrcTS3
[GPIO30]TrcTS4
[GPIO31]TrcTS5
Halt
G06
E05
H11
H14
N16
P17
T20
T21
P23
N09
P08
T05
T04
P03
R07
P09
R09
T06
V05
Y21
System
53
System
53
51
HoldAck
External Master Peripheral
24
AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signals Listed Alphabetically (Sheet 8 of 22)
Signal Name
Ball
Y23
G11
G13
H11
H14
N18
L20
Interface Group
External Master Peripheral
Page
51
HoldReq
IIC0SClk
IIC0SDA
IIC Peripheral
IIC Peripheral
IIC Peripheral
IIC Peripheral
52
52
IIC1SClk[GPIO16]
IIC1SDA[GPIO17]
IRQ00[GPIO00]
IRQ01[GPIO01]
IRQ02[GPIO02]
IRQ03[GPIO03]
IRQ04[GPIO04]
IRQ05[GPIO05]
IRQ06[GPIO06]
IRQ07[GPIO07]
IRQ08[GPIO08]
IRQ09[GPIO09]
IRQ10[GPIO10]
[IRQ11]PCIReq1
[IRQ12]PCIGnt1
MemAddr00
52
52
P20
L18
N14
M20
M14
P18
N20
P22
V18
E21
C22
Y19
AD20
Y20
AB20
AD18
AD16
AB18
Y14
V13
V11
W16
Y11
V10
V09
V08
Interrupts
52
MemAddr01
MemAddr02
MemAddr03
MemAddr04
MemAddr05
MemAddr06
DDR SDRAM
49
MemAddr07
MemAddr08
MemAddr09
MemAddr10
MemAddr11
MemAddr12
MemClkOut0
MemClkOut0
DDR SDRAM
49
AMCC
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Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signals Listed Alphabetically (Sheet 9 of 22)
Signal Name
Ball
AD21
AB21
AC22
AA20
U16
Interface Group
Page
MemData00
MemData01
MemData02
MemData03
MemData04
MemData05
MemData06
MemData07
MemData08
MemData09
MemData10
MemData11
MemData12
MemData13
MemData14
MemData15
MemData16
MemData17
MemData18
MemData19
MemData20
MemData21
MemData22
MemData23
MemData24
MemData25
MemData26
MemData27
MemData28
MemData29
MemData30
MemData31
V17
AD19
AB19
W18
V16
Y17
AB16
AC18
Y18
R14
AB17
AA14
AD15
T15
DDR SDRAM
49
V15
Y16
U14
T13
Y15
AD13
AD14
V14
Y13
P12
AB12
Y12
V12
26
AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signals Listed Alphabetically (Sheet 10 of 22)
Signal Name
Ball
W11
AD12
Y10
Interface Group
Page
MemData32
MemData33
MemData34
MemData35
MemData36
MemData37
MemData38
MemData39
MemData40
MemData41
MemData42
MemData43
MemData44
MemData45
MemData46
MemData47
MemData48
MemData49
MemData50
MemData51
MemData52
MemData53
MemData54
MemData55
MemData56
MemData57
MemData58
MemData59
MemData60
MemData61
MemData62
MemData63
MemVRef1
MemVRef2
T12
U11
T11
T10
AD10
AB08
AD08
R11
Y07
AC07
AB09
Y06
Y08
DDR SDRAM
49
AA01
AA03
AB02
Y01
AB03
Y02
V07
V01
T08
U07
W01
W03
V06
T07
W05
U05
T14
DDR SDRAM
49
T09
AMCC
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Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signals Listed Alphabetically (Sheet 11 of 22)
Signal Name
Ball
A01
Interface Group
Page
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
A02
A03
A22
A23
A24
B01
B02
B23
B24
C01
C24
A physical ball does not exist at these ball coordinates.
NA
AB01
AB24
AC01
AC02
AC23
AC24
AD01
AD02
AD03
AD22
AD23
AD24
28
AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signals Listed Alphabetically (Sheet 12 of 22)
Signal Name
Ball
B04
B12
B19
D02
D10
D17
F08
F15
F23
H06
H10
H13
H21
K04
K08
K19
M02
M17
N08
N23
R06
R17
R21
U04
U19
W02
Interface Group
Page
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
Power
54
AA23
G08
D09
PCIX133Cap
PCIXAck64
PCI-X
PCI-X
48
48
AMCC
29
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signals Listed Alphabetically (Sheet 13 of 22)
Signal Name
Ball
C17
B09
G10
E10
C10
A10
F11
G12
G14
A15
C15
E15
G15
B16
C16
D16
E18
E19
F18
G18
D20
A20
A21
C21
F22
B22
G21
E23
C23
F24
D22
D24
Interface Group
Page
PCIXAD00
PCIXAD01
PCIXAD02
PCIXAD03
PCIXAD04
PCIXAD05
PCIXAD06
PCIXAD07
PCIXAD08
PCIXAD09
PCIXAD10
PCIXAD11
PCIXAD12
PCIXAD13
PCIXAD14
PCIXAD15
PCIXAD16
PCIXAD17
PCIXAD18
PCIXAD19
PCIXAD20
PCIXAD21
PCIXAD22
PCIXAD23
PCIXAD24
PCIXAD25
PCIXAD26
PCIXAD27
PCIXAD28
PCIXAD29
PCIXAD30
PCIXAD31
PCI-X
48
30
AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signals Listed Alphabetically (Sheet 14 of 22)
Signal Name
Ball
H03
H01
L08
F01
D01
J05
Interface Group
Page
PCIXAD32
PCIXAD33
PCIXAD34
PCIXAD35
PCIXAD36
PCIXAD37
PCIXAD38
PCIXAD39
PCIXAD40
PCIXAD41
PCIXAD42
PCIXAD43
PCIXAD44
PCIXAD45
PCIXAD46
PCIXAD47
PCIXAD48
PCIXAD49
PCIXAD50
PCIXAD51
PCIXAD52
PCIXAD53
PCIXAD54
PCIXAD55
PCIXAD56
PCIXAD57
PCIXAD58
PCIXAD59
PCIXAD60
PCIXAD61
PCIXAD62
PCIXAD63
H05
G02
E02
C02
A08
G05
F03
D03
B03
H07
G04
E04
C04
A04
F05
D05
B05
C09
E06
C06
A06
F07
E07
D07
B07
E08
PCI-X
48
AMCC
31
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signals Listed Alphabetically (Sheet 15 of 22)
Signal Name
Ball
F14
E16
C19
F20
C08
C03
G09
F09
L23
E03
E13
A11
E22
C22
N22
M18
R22
P19
G07
M07
E12
A14
L04
F16
A17
E24
E21
E20
R20
G23
R18
E09
M24
A18
Interface Group
Page
PCIXC0[BE0]
PCIXC1[BE1]
PCIXC2[BE2]
PCIXC3[BE3]
PCIXC4[BE4]
PCIXC5[BE5]
PCIXC6[BE6]
PCIXC7[BE7]
PCIXCap
PCI-X
48
PCI-X
PCI-X
PCI-X
PCI-X
48
48
48
48
PCIXClk
PCIXDevSel
PCIXFrame
PCIXGnt0
PCIXGnt1[IRQ12]
PCIXGnt2
PCI-X
48
PCIXGnt3
PCIXGnt4
PCIXGnt5
PCIXIDSel
PCIXINT
PCI-X
PCI-X
PCI-X
PCI-X
PCI-X
PCI-X
PCI-X
48
48
48
48
48
48
48
PCIXIRDY
PCIXM66En
PCIXParHigh
PCIXParLow
PCIXPErr
PCIXReq0
PCIXReq1[IRQ11]
PCIXReq2
PCIXReq3
PCIXReq4
PCIXReq5
PCIXReq64
PCIXReset
PCIXSErr
PCI-X
48
PCI-X
PCI-X
PCI-X
48
48
48
32
AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signals Listed Alphabetically (Sheet 16 of 22)
Signal Name
Ball
L12
C12
D11
C11
B11
A12
A19
D18
E11
M03
N01
E14
C20
A16
A13
B14
C14
D14
B20
L15
L21
L22
M22
M01
L24
P24
T19
R24
U22
U24
N03
V20
V23
V21
Interface Group
Page
48
PCIXStop
PCIXTRDY
PerAddr00
PerAddr01
PerAddr02
PerAddr03
PerAddr04
PerAddr05
PerAddr06
PerAddr07
PerAddr08
PerAddr09
PerAddr10
PerAddr11
PerAddr12
PerAddr13
PerAddr14
PerAddr15
PerAddr16
PerAddr17
PerAddr18
PerAddr19
PerAddr20
PerAddr21
PerAddr22
PerAddr23
PerAddr24
PerAddr25
PerAddr26
PerAddr27
PerAddr28
PerAddr29
PerAddr30
PerAddr31
PCI-X
PCI-X
48
External Slave Peripheral
Note: PerAddr00 is the most significant bit (msb) on this bus.
50
AMCC
33
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signals Listed Alphabetically (Sheet 17 of 22)
Signal Name
Ball
C07
U18
E17
L10
V04
T24
L03
T03
L13
U03
Interface Group
Page
50
PerBLast
PerClk
External Slave Peripheral
External Master Peripheral
51
PerCS0
PerCS1
PerCS2
PerCS3
PerCS4
PerCS5
PerCS6
PerCS7
External Slave Peripheral
50
34
AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signals Listed Alphabetically (Sheet 18 of 22)
Signal Name
Ball
H24
H22
H20
G20
G19
H18
J23
J22
J21
J20
J19
J18
J17
J15
J14
J13
J12
J11
J10
J09
L14
K24
K22
K20
K18
K16
K14
K11
K09
L19
L17
L16
P21
M09
Interface Group
Page
PerData00
PerData01
PerData02
PerData03
PerData04
PerData05
PerData06
PerData07
PerData08
PerData09
PerData10
PerData11
PerData12
PerData13
PerData14
PerData15
PerData16
PerData17
PerData18
PerData19
PerData20
PerData21
PerData22
PerData23
PerData24
PerData25
PerData26
PerData27
PerData28
PerData29
PerData30
PerData31
PerErr
External Slave Peripheral
Note: PerData00 is the most significant bit (msb) on this bus.
50
External Master Peripheral
External Slave Peripheral
51
50
PerOE
AMCC
35
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signals Listed Alphabetically (Sheet 19 of 22)
Signal Name
Ball
T23
T22
W20
U20
N07
P05
T18
V19
W22
W24
P02
AD07
N07
L02
Interface Group
Page
PerPar0
PerPar1
PerPar2
PerPar3
External Slave Peripheral
50
PerReady[RcvrInh]
PerR/W
External Slave Peripheral
External Slave Peripheral
50
50
PerWBE0
PerWBE1
PerWBE2
PerWBE3
PerWE
External Slave Peripheral
50
External Slave Peripheral
DDR SDRAM
System
50
49
53
53
RAS
[RcvrInh]PerReady
RefVEn
System
Reserved
Reserved
SVDD
L01
Reserved
54
P04
U12
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
U15
W10
W17
AA08
AA15
AC06
AC13
Power
54
AC21
G22
T02
SysClk
SysErr
SysReset
TCK
System
System
System
JTAG
53
53
53
52
52
52
53
53
P10
V22
Y24
Y22
M05
U01
TDI
JTAG
TDO
JTAG
TestEn
TmrClk
System
System
36
AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signals Listed Alphabetically (Sheet 20 of 22)
Signal Name
Ball
AB22
N16
P17
T20
R05
T21
P23
N09
P08
T05
T04
P03
R07
P09
R09
T06
R01
N24
C13
Interface Group
Page
TMS
JTAG
Trace
Trace
52
TrcBS0[GPIO18]
TrcBS1[GPIO19]
TrcBS2[GPIO20]
TrcClk
54
54
TrcES0[GPIO21]
TrcES1[GPIO22]
TrcES2[GPIO23]
TrcES3[GPIO24]
TrcES4[GPIO25]
TrcTS0[GPIO26]
TrcTS1[GPIO27]
TrcTS2[GPIO28]
TrcTS3[GPIO29]
TrcTS4[GPIO30]
TrcTS5[GPIO31]
TrcTS6
Trace
54
Trace
54
54
54
54
54
54
54
52
51
Trace
Trace
Trace
Trace
Trace
Trace
TRST
JTAG
UART0_CTS
UART Peripheral
UART Peripheral
Note: Used as initialization strapping input.
UART0_DCD
UART0_DSR
V24
V02
51
51
UART Peripheral
Note: Used as initialization strapping input.
UART0_DTR
B18
H16
G16
G17
L11
G06
E05
C18
J16
UART Peripheral
UART Peripheral
UART Peripheral
UART Peripheral
UART Peripheral
UART Peripheral
UART Peripheral
UART Peripheral
UART Peripheral
51
51
51
51
51
51
51
51
51
UART0_RI
UART0_RTS
UART0_Rx
UART0_Tx
UART1_DSR/CTS[GPIO14]
UART1_RTS/DTR[GPIO15]
UART1_Rx[GPIO12]
UART1_Tx[GPIO13]
AMCC
37
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signals Listed Alphabetically (Sheet 21 of 22)
Signal Name
Ball
A09
B08
Interface Group
Page
UARTSerClk
VDD
UART Peripheral
51
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
B15
D06
D13
D21
F04
F12
F19
H02
H17
K12
K15
K23
M06
M10
M13
M21
N04
N12
N15
Power
54
38
AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signals Listed Alphabetically (Sheet 22 of 22)
Signal Name
Ball
N19
Interface Group
Page
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
WE
R02
R10
R13
U08
U23
W06
W13
W21
AA04
AA12
AA19
AC10
AC17
Y05
Power
54
DDR SDRAM
49
AMCC
39
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
In the following table, only the primary (default) signal name is shown for each pin. Multiplexed or multifunction
signals are marked with an asterisk (*). To determine what signals or functions are multiplexed on those pins, look
up the primary signal name in “Signals Listed Alphabetically” on page 18.
Signals Listed by Ball Assignment (Sheet 1 of 6)
Ball
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
Signal Name
Ball
B01
B02
B03
B04
B05
B06
B07
B08
B09
B10
B11
B12
Signal Name
Ball
C01
C02
C03
C04
C05
C06
C07
C08
C09
C10
C11
C12
Signal Name
No ball
Ball
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
Signal Name
PCIXAD36
No ball
No ball
OVDD
No ball
No ball
PCIXAD41
PCIXC5 *
No ball
PCIXAD46
OVDD
PCIXAD45
GND
PCIXAD51
DrvrInh2
PCIXAD50
EMCTxErr *
PCIXAD57
PerBLast
PCIXAD54
GND
PCIXAD53
VDD
PCIXAD58
EMCRxD2 *
PCIXAD42
UARTSerClk
PCIXAD05
PCIXFrame
PerAddr03
PCIXAD62
VDD
PCIXAD61
GND
PCIXC4 *
PCIXAD01
GND
PCIXAD55
PCIXAD04
PerAddr01
PCIXTRDY
PCIXAck64
OVDD
PerAddr02
OVDD
PerAddr00
GND
VDD
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
PerAddr12
PCIXM66En
PCIXAD09
PerAddr11
PCIXPErr
PCIXSErr
PerAddr04
PCIXAD21
PCIXAD22
No ball
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
GND
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
UART0_CTS
PerAddr14
PCIXAD10
PCIXAD14
PCIXAD00
UART1_Rx *
PCIXC2 *
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
PerAddr13
VDD
PerAddr15
GND
PCIXAD13
GND
PCIXAD15
OVDD
UART0_DTR
OVDD
PerAddr05
GND
PerAddr16
GND
PerAddr10
PCIXAD23
PCIXGnt1 *
PCIXAD28
No ball
PCIXAD20
VDD
PCIXAD25
No ball
PCIXAD30
GND
No ball
No ball
No ball
PCIXAD31
40
AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signals Listed by Ball Assignment (Sheet 2 of 6)
Ball
E01
E02
E03
E04
E05
E06
E07
E08
E09
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
Signal Name
Ball
F01
F02
F03
F04
F05
F06
F07
F08
F09
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
Signal Name
Ball
G01
G02
G03
G04
G05
G06
G07
G08
G09
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
G23
G24
Signal Name
Ball
H01
H02
H03
H04
H05
H06
H07
H08
H09
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
H23
H24
Signal Name
PCIXAD33
APVDD for PCI PLL
EMCRxD1 *
PCIXAD35
VDD
PCIXAD40
PCIXClk
GND
PCIXAD39
EMCRxD0 *
PCIXAD48
PCIXAD43
UART1_DSR/CTS *
PCIXIDSel
PCIX133Cap
PCIXC6 *
PCIXAD44
VDD
PCIXAD32
GND
PCIXAD49
UART1_RTS/DTR *
PCIXAD56
PCIXAD60
PCIXAD63
PCIXReq64
PCIXAD03
PerAddr06
PCIXIRDY
PCIXDevSel
PerAdd09
PCIXAD52
GND
PCIXAD38
OVDD
PCIXAD59
OVDD
PCIXAD47
GND
PCIXC7 *
GND
EMCRxD3 *
OVDD
PCIXAD02
IIC0SClk
PCIXAD06
VDD
IIC1SClk *
GND
PCIXAD07
IIC0SDA
OVDD
GND
PCIXC0 *
OVDD
PCIXAD08
PCIXAD12
UART0_RTS
UART0_Rx
PCIXAD19
PerData04
PerData03
PCIXAD26
SysClk
IIC1SDA *
GND
PCIXAD11
PCIXC1 *
PCIXParLow
GND
UART0_RI
VDD
PerCS0
PCIXAD16
PCIXAD17
PCIXReq2
PCIXReq1 *
PCIXGnt0
PCIXAD27
PCIXReq0
PCIXAD18
VDD
PerData05
GND
PCIXC3 *
GND
PerData02
OVDD
PCIXAD24
OVDD
PerData01
GND
PCIXReq4
ASVDD for SysClk PLL
PCIXAD29
PerData00
AMCC
41
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signals Listed by Ball Assignment (Sheet 3 of 6)
Ball
J01
J02
J03
J04
J05
J06
J07
J08
J09
J10
J11
J12
Signal Name
Ball
K01
K02
K03
K04
K05
K06
K07
K08
K09
K10
K11
K12
Signal Name
Ball
L01
L02
L03
L04
L05
L06
L07
L08
L09
L10
L11
L12
Signal Name
Reserved
Ball
M01
M02
M03
M04
M05
M06
M07
M08
M09
M10
M11
M12
Signal Name
PerAddr21
AGND
EMCRxDV *
OVDD
EMCRxClk
EMCTxD3 *
EMCTxD2 *
PCIXAD37
EMCTxClk *
EMCCD *
EMCMDClk
PerData19
PerData18
PerData17
PerData16
PerData15
PerData14
PerData13
UART1_Tx *
PerData12
PerData11
PerData10
PerData9
GND
RefVEn
EMCRxErr *
OVDD
PerCS4
PerAddr07
GND
PCIXParHigh
EMCMDIO
EMCTxEn *
DrvrInh1
EMCTxD1 *
GND
TestEn
VDD
EMCCrS *
OVDD
PCIXINT
GND
PCIXAD34
EMCTxD0 *
PerCS1
PerData28
GND
PerOE
VDD
PerData27
VDD
UART0_Tx
PCIXStop
PerCS6
DMAReq1
GND
VDD
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
J23
J24
K13
K14
K15
K16
K17
K18
K19
K20
K21
K22
K23
K24
GND
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
L23
L24
M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
M23
M24
PerData26
VDD
PerData20
PerAddr17
PerData31
PerData30
IRQ03 *
IRQ06 *
GND
PerData25
GND
EOT3/TC3
OVDD
PerData24
OVDD
PCIXGnt3
GND
PerData29
IRQ01 *
PerData23
GND
IRQ05 *
VDD
PerData8
PerAddr18
PerAddr19
PCIXCap
PerAddr22
PerData7
PerData22
VDD
PerAddr20
GND
PerData6
AGND
PerData21
PCIXReset
42
AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signals Listed by Ball Assignment (Sheet 4 of 6)
Ball
N01
N02
N03
N04
N05
N06
N07
N08
N09
N10
N11
N12
Signal Name
Ball
P01
P02
P03
P04
P05
P06
P07
P08
P09
P10
P11
P12
Signal Name
Ball
R01
R02
R03
R04
R05
R06
R07
R08
R09
R10
R11
R12
Signal Name
TrcTS6
Ball
T01
T02
T03
T04
T05
T06
T07
T08
T09
T10
T11
T12
Signal Name
DQS7
PerAddr08
DMAReq3
VDD
GND
PerWE
SysErr
PerAddr28
VDD
TrcTS1 *
Reserved
PerR/W
DMAReq0
GND
PerCS5
TrcTS0 *
DMAAck0
GND
TrcClk
OVDD
TrcES4 *
TrcTS5 *
DMAAck2
DMAAck1
TrcES3 *
TrcTS3 *
SysReset
DMAAck3
MemData28
DM3
PerReady *
OVDD
TrcTS2 *
GND
MemData61
MemData56
MemVRef2
MemData38
MemData37
MemData35
MemData22
MemVRef1
MemData18
DM0
TrcES2 *
GND
TrcTS4 *
VDD
DMAReq2
VDD
MemData42
GND
VDD
N13
N14
N15
N16
N17
N18
N19
N20
N21
N22
N23
N24
GND
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
IRQ04 *
VDD
GPIO11
MemData14
GND
EOT1/TC1
EOT2/TC2
TrcBS1 *
IRQ07 *
TrcBS0 *
GND
EOT0/TC0
OVDD
ExtReset
PerWBE0
PerAddr24
TrcBS2 *
TrcES0 *
PerPar1
IRQ00 *
VDD
PCIXReq5
GND
PCIXGnt5
IRQ02 *
IRQ08 *
GND
PCIXReq3
OVDD
PerErr
PCIXGnt2
OVDD
IRQ09 *
PCIXGnt4
GND
TrcES1 *
PerAddr23
PerPar0
TRST
PerAddr25
PerCS3
AMCC
43
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signals Listed by Ball Assignment (Sheet 5 of 6)
Ball
U01
U02
U03
U04
U05
U06
U07
U08
U09
U10
U11
U12
Signal Name
Ball
V01
V02
V03
V04
V05
V06
V07
V08
V09
V10
V11
V12
Signal Name
Ball
W01
W02
W03
W04
W05
W06
W07
W08
W09
W10
W11
W12
Signal Name
MemData58
Ball
Y01
Y02
Y03
Y04
Y05
Y06
Y07
Y08
Y09
Y10
Y11
Y12
Signal Name
MemData51
TmrClk
MemData55
OVDD
GND
UART0_DSR
DM7
MemData53
DM6
PerCS7
OVDD
MemData59
GND
PerCS2
DQS6
MemData63
GND
Halt
MemData62
VDD
WE
MemData60
MemData54
MemClkOut0
MemClkOut0
MemAddr12
MemAddr9
MemData31
MemAddr8
MemData26
MemData19
MemData09
MemData05
IRQ10 *
MemData46
MemData43
MemData47
ClkEn2
MemData57
VDD
ECC3
GND
ECC4
ClkEn3
SVDD
GND
MemData34
MemAddr11
MemData30
MemData27
MemAddr7
MemData23
MemData20
MemData10
MemData13
MemAddr00
MemAddr02
HoldAck
MemData36
SVDD
MemData32
GND
VDD
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
U23
U24
GND
V13
V14
V15
V16
V17
V18
V19
V20
V21
V22
V23
V24
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
W23
W24
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
Y24
MemData21
SVDD
BankSel1
GND
MemData04
GND
MemAddr10
SVDD
PerClk
MemData08
GND
OVDD
PerWBE1
PerAddr29
PerAddr31
TCK
PerPar3
GND
PerPar2
VDD
PerAddr26
VDD
PerWBE2
GND
TDO
PerAddr30
UART0_DCD
HoldReq
PerAddr27
PerWBE3
TDI
44
AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signals Listed by Ball Assignment (Sheet 6 of 6)
Ball
Signal Name
Ball
Signal Name
Ball
Signal Name
Ball
Signal Name
AA01 MemData48
AA02 GND
AB01 No ball
AC01 No ball
AC02 No ball
AC03 ECC5
AC04 GND
AC05 DM8
AD01 No ball
AD02 No ball
AD03 No ball
AD04 ECC7
AB02 MemData50
AB03 MemData52
AB04 ECC6
AA03 MemData49
VDD
AA04
AA05 DQS8
AA06 GND
AA07 DM5
AB05 CAS
AD05 BankSel3
AD06 ECC2
SVDD
AB06 ECC1
AC06
AB07 ECC0
AC07 MemData44
AC08 GND
AD07 RAS
SVDD
AA08
AB08 MemData40
AB09 MemData45
AB10 ClkEn1
AD08 MemData41
AD09 BA1
AA09 DM4
AA10 GND
AC09 DQS5
VDD
AC10
AD10 MemData39
AMVDD for MemClk
PLL
AA11 AGND
AB11
AC11 DQS4
AC12 GND
AD11 BankSel2
VDD
AA12
AB12 MemData29
AB13 DQS3
AD12 MemData33
AD13 MemData24
AD14 MemData25
AD15 MemData17
AD16 MemAddr5
AD17 ClkEn0
SVDD
AA13 GND
AC13
AA14 MemData16
AB14 DM2
AC14 DQS2
AC15 GND
AC16 DQS1
SVDD
AA15
AB15 BankSel0
AB16 MemData11
AB17 MemData15
AB18 MemAddr6
AB19 MemData07
AB20 MemAddr3
AB21 MemData01
AB22 TMS
AA16 BA0
AA17 GND
AA18 DM1
VDD
AC17
AC18 MemData12
AC19 GND
AD18 MemAddr4
AD19 MemData06
AD20 MemAddr01
AD21 MemData00
AD22 No ball
VDD
AA19
AA20 MemData03
AA21 GND
AC20 DQS0
SVDD
AC21
AA22 ExtAck
AC22 MemData02
AC23 No ball
OVDD
AA23
AB23 ExtReq
AD23 No ball
AA24 BusReq
AB24 No ball
AC24 No ball
AD24 No ball
AMCC
45
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signal Description
The PPC440GP embedded controller is provided in a 552-ball, ball grid array package. The following tables
describe the package level pinout.
Pin Summary
Group
Signal pins, non-multiplexed
Signal pins, multiplexed
Total Signal Pins
AxVDD
No. of Pins
347
57
404
3
AGnd
OVDD
3
27
SVDD
VDD
9
34
70
Gnd
Total Power Pins
Reserved
146
2
Total Pins
552
In the table “Signal Functional Description” on page 48, each I/O signal is listed along with a short description of its
function. Active-low signals (for example, RAS) are marked with an overline. Please see “Signals Listed
Alphabetically” on page 18 for the pin (ball) number to which each signal is assigned.
Multiplexed Signals
Some signals are multiplexed on the same pin so that the pin can be used for different functions. In most cases,
the signal names shown in this table are not accompanied by signal names that may be multiplexed on the same
pin. If you need to know what, if any, signals are multiplexed with a particular signal, look up the name in “Signals
Listed Alphabetically” on page 18. It is expected that in any single application a particular pin will always be
programmed to serve the same function. The flexibility of multiplexing allows a single chip to offer a richer pin
selection than would otherwise be possible.
Multipurpose Signals
In addition to multiplexing, some pins are also multi-purpose. For example, the EBC peripheral controller address
pins (PerAddr00:31) are used as outputs by the PPC440GP to broadcast an address to external slave devices
when the PPC440GP has control of the external bus. When during the course of normal chip operation an external
master gains ownership of the external bus, these same pins are used as inputs which are driven by the external
master and received by the EBC in the PPC440GP. In this example, the pins are also bidirectional, serving both as
inputs and outputs.
Multimode Signals
In some cases (for example, Ethernet) the function of a pin may vary with different modes of operation. When a pin
has multiple signal names assigned to distinguish different modes of operation, all of the names are shown.
46
AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Strapping Pins
One group of pins is used as strapped inputs during system reset. These pins function as strapped inputs only
during reset and are used for other functions during normal operation (see “Strapping” on page 80). Note that
these are not multiplexed pins since the function of the pins is not programmable.
AMCC
47
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signal Functional Description (Sheet 1 of 7)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V, 10kΩ to 5V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
PCI-X Interface
Description
I/O
Type
Notes
PCIXAD00:63
Address/Data bus (bidirectional).
I/O
I/O
3.3V PCI
3.3V PCI
PCIXC0:7[BE0:7]
PCI-X Command[Byte Enables].
Capable of PCI-X operation.
5V tolerant
3.3V LVTTL
PCIXCap
I
5
PCIX133Cap
PCI-X devices are 133 MHz capable.
O
3.3V PCI
3.3V PCI
Provides timing to the PCI interface for PCI transactions.
PCIXClk
I
Note:If the PCI-X interface is not being used, drive this pin with a
3.3V clock signal at a frequency between 1 and 66MHz
Indicates the driving device has decoded its address as the target
of the current access.
PCIXDevSel
PCIXFrame
I/O
I/O
3.3V PCI
3.3V PCI
4
4
Driven by the current master to indicate beginning and duration of
an access.
PCIXGnt0
PCIXGnt1
PCIXGnt2:5
Indicates that the specified agent is granted access to the bus.
Indicates that the specified agent is granted access to the bus.
Indicates that the specified agent is granted access to the bus.
I/O
I/O
O
3.3V PCI
3.3V PCI
3.3V PCI
4
4
Used as a chip select during configuration read and write
transactions.
PCIXIDSel
PCIXINT
I
3.3V PCI
3.3V PCI
3.3V PCI
5
Level sensitive PCI interrupt.
O
Indicates initiating agent’s ability to complete the current data
phase of the transaction.
PCIXIRDY
I/O
4
5
5V tolerant
3.3V LVTTL
PCIXM66En
Capable of 66MHz operation.
I
PCIXParHigh
PCIXParLow
Even parity across PCIAD32:63 and PCIXC0:3[BE4:7].
Even parity across PCIAD0:31 and PCIXC0:3[BE0:3].
I/O
I/O
3.3V PCI
3.3V PCI
Reports data parity errors during all PCI transactions except a
Special Cycle.
PCIXPErr
I/O
I/O
I
3.3V PCI
3.3V PCI
3.3V PCI
4
4
4
An indication to the PCI-X arbiter that the specified agent wishes
to use the bus.
PCIXReq0
PCIXReq1:5
An indication to the PCI-X arbiter that the specified agent wishes
to use the bus.
PCIXReq64
PCIXAck64
PCIXReset
Asserted by the current bus master, indicating a 64-bit transfer.
Indicates the target can transfer data using 64 bits.
I/O
I/O
O
3.3V PCI
3.3V PCI
3.3V PCI
4
4
Brings PCI device registers and logic to a consistent state.
Reports address parity errors, data parity errors on the Special
Cycle command, or other catastrophic system errors.
PCIXSErr
PCIXStop
PCIXTRDY
I/O
I/O
I/O
3.3V PCI
3.3V PCI
3.3V PCI
4
4
4
Indicates the current target is requesting the master to stop the
current transaction.
Indicates the target agent’s ability to complete the current data
phase of the transaction.
48
AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signal Functional Description (Sheet 2 of 7)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V, 10kΩ to 5V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
DDR SDRAM Interface
BA0:1
Description
I/O
Type
Notes
Bank Address supporting up to four internal banks.
Selects up to four external DDR SDRAM banks.
Column Address Strobe.
O
O
O
O
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
BankSel0:3
CAS
ClkEn0:3
Clock Enable. One for each bank.
Memory write data byte lane masks. MEMDM8 is the byte lane
mask for the ECC byte lane.
DM0:8
O
2.5V SSTL_2
2.5V SSTL_2
Byte lane data strobe. DQS8 is the data strobe for the ECC byte
lane.
DQS0:8
I/O
ECC0:7
ECC check bits 0:7.
Memory address bus.
I/O
O
2.5V SSTL_2
2.5V SSTL_2
MemAddr00:12
MemClkOut0
MemClkOut0
Subsystem clock.
O
I/O
I
2.5V SSTL_2
2.5V SSTL_2
MemData00:63
MemVRef1:2
Memory data bus.
Voltage Ref
Receiver
Memory reference voltage (SVREF) input.
RAS
Row Address Strobe.
Write Enable.
O
O
2.5V SSTL_2
2.5V SSTL_2
WE
Ethernet Interface
EMCCD,
MII: Collision detection
RMII 1: Receive error
5V tolerant
I/O
I/O
O
EMC1RxErr
3.3V LVTTL
EMCCrS,
EMC0CrSDV
MII: Carrier sense
RMII 0: Carrier sense data valid
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
EMCMDClk
EMCMDIO
MII and RMII: Management data clock
MII and RMII: Transfer command and status information between
MII and PHY
5V tolerant
3.3V LVTTL
I/O
EMCRxD0:3,
EMC0RxD0:1,
EMC1RxD0:1
MII: Receive data
RMII 0: Receive data
RMII 1: Receive data
5V tolerant
3.3V LVTTL
I/O
EMCRxDV,
MII: Receive data valid
5V tolerant
I
I
I
I
EMC1CrSDV
RMII 1: Carrier sense data valid
3.3V LVTTL
5V tolerant
3.3V LVTTL
EMCRxClk
MII: Receive clock
EMCRxErr,
EMC0RxErr
MII: Receive error
RMII 0: Receive error
5V tolerant
3.3V LVTTL
EMCTxClk,
EMCRefClk
MII: Transmit clock
RMII: Reference clock
5V tolerant
3.3V LVTTL
5
MII: Transmit data
RMII 0: Transmit data
RMII 1: Transmit data
EMCTxD0:3,
EMC0TxD0:1,
EMC1TxD0:1
5V tolerant
3.3V LVTTL
O
AMCC
49
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signal Functional Description (Sheet 3 of 7)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V, 10kΩ to 5V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
MII: Transmit data enabled
RMII 0: Transmit data enabled
EMCTxEn,
EMC0TxEn
5V tolerant
3.3V LVTTL
O
EMCTxErr,
EMC1TxEn
MII: Transmit error:
RMII: Transmit data enabled
5V tolerant
3.3V LVTTL
O
External Slave Peripheral Interface
Used by the PPC440GP to indicate that data transfers have
5V tolerant
DMAAck0:3
DMAReq0:3
EOT0:3/TC0:3
O
I
occurred.
3.3V LVTTL
Used by slave peripherals to indicate they are prepared to transfer
data.
5V tolerant
3.3V LVTTL
1, 5
1, 5
5V tolerant
3.3V LVTTL
End Of Transfer/Terminal Count.
I/O
Peripheral address bus used by PPC440GP when not in external
master mode, otherwise used by external master.
Note: PerAddr00 is the most significant bit (msb) on this bus.
5V tolerant
3.3V LVTTL
PerAddr00:31
I/O
1
5V tolerant
PerWBE0:3
PerBLast
External peripheral data bus byte enables.
I/O
I/O
O
1, 2
1, 4
2
3.3V LVTTL
Used by either the peripheral controller, DMA controller, or
external master to indicates the last transfer of a memory access.
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
PerCS0:7
External peripheral device select.
Peripheral data bus used by PPC440GP when not in external
master mode, otherwise used by external master.
Note: PerData00 is the most significant bit (msb) on this bus.
5V tolerant
PerData00:31
PerOE
I/O
O
1
3.3V LVTTL
Used by either peripheral controller or DMA controller depending
upon the type of transfer involved. When the PPC440GP is the
bus master, it enables the selected device to drive the bus.
5V tolerant
3.3V LVTTL
2
1
5V tolerant
3.3V LVTTL
PerPar0:3
PerReady
External peripheral data bus byte parity.
I/O
I
5V tolerant
3.3V LVTTL
Used by a peripheral slave to indicate it is ready to transfer data.
Used by the PPC440GP when not in external master mode, as
output by either the peripheral controller or DMA controller
depending upon the type of transfer involved. High indicates a
read from memory, low indicates a write to memory.
Otherwise, it used by the external master as an input to indicate
the direction of transfer.
5V tolerant
PerR/W
PerWE
I/O
O
1, 2
2
3.3V LVTTL
Write Enable. Low when any of the four PerWBE0:3 signals are
low.
5V tolerant
3.3V LVTTL
50
AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signal Functional Description (Sheet 4 of 7)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V, 10kΩ to 5V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
External Master Peripheral Interface
Bus Request. Used when the PPC440GP needs to regain control
of peripheral interface from an external master.
5V tolerant
BusReq
ExtAck
O
O
I
3.3V LVTTL
External Acknowledgement. Used by the PPC440GP to indicate
that a data transfer occurred.
5V tolerant
3.3V LVTTL
External Request. Used by an external master to indicate it is
prepared to transfer data.
5V tolerant
3.3V LVTTL
ExtReq
ExtReset
HoldAck
HoldReq
PerClk
1, 4
Peripheral Reset. Used by an external master and by
synchronous peripheral slaves.
5V tolerant
3.3V LVTTL
O
O
I
Hold Acknowledge. Used by the PPC440GP to transfer ownership
of peripheral bus to an external master.
5V tolerant
3.3V LVTTL
Hold Request. Used by an external master to request ownership
of the peripheral bus.
5V tolerant
3.3V LVTTL
1, 5
1, 5
1, 4
Peripheral Clock. Used by an external master and by synchronous
peripheral slaves.
5V tolerant
3.3V LVTTL
O
I/O
External Error. Used as an input to record external master errors
and external slave peripheral errors.
5V tolerant
3.3V LVTTL
PerErr
UART Peripheral Interface
Serial clock input that provides an alternative to the internally
generated serial clock. Used in cases where the allowable
internally generated clock rates are not satisfactory. This input can
be individually connected to either or both UART0 and UART1.
5V tolerant
3.3V LVTTL
UARTSerClk
I
5V tolerant
UART0_Rx
UART0 Receive data.
I
O
I
1, 4
4
3.3V LVTTL
5V tolerant
3.3V LVTTL
UART0_Tx
UART0 Transmit data.
UART0 Data Carrier Detect.
UART0 Data Set Ready.
UART0 Clear To Send.
UART0 Data Terminal Ready.
UART0 Request To Send.
UART0 Ring Indicator.
UART1 Receive data.
5V tolerant
3.3V LVTTL
UART0_DCD
UART0_DSR
UART0_CTS
UART0_DTR
UART0_RTS
UART0_RI
6
5V tolerant
3.3V LVTTL
I
6
5V tolerant
3.3V LVTTL
I
1, 4
4
5V tolerant
3.3V LVTTL
O
O
I
5V tolerant
3.3V LVTTL
4
5V tolerant
3.3V LVTTL
1, 4
1, 4
1, 4
1, 4
5V tolerant
3.3V LVTTL
UART1_Rx
I/O
I/O
I/O
5V tolerant
3.3V LVTTL
UART1_Tx
UART1 Transmit data.
UART1 Data Set Ready or Clear To Send. The choice is
determined by a DCR register bit setting.
5V tolerant
3.3V LVTTL
UART1_DSR/CTS
AMCC
51
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signal Functional Description (Sheet 5 of 7)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V, 10kΩ to 5V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
UART1_RTS/DTR
Description
I/O
Type
Notes
UART1 Request To Send or Data Terminal Ready. The choice is
determined by a DCR register bit setting.
5V tolerant
3.3V LVTTL
I/O
1, 4
IIC Peripheral Interface
5V tolerant
IIC0SClk
IIC0 Serial Clock.
IIC0 Serial Data.
IIC1 Serial Clock.
IIC1 Serial Data.
I/O
I/O
I/O
I/O
1, 2
1, 2
1, 2
1, 2
3.3V LVTTL
5V tolerant
3.3V LVTTL
IIC0SDA
IIC1SClk
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
IIC1SDA
Interrupts Interface
IRQ00:10
5V tolerant
External interrupt Requests 0 through 10.
External interrupt Requests 11 through 12.
I
I
1, 5
3.3V LVTTL
IRQ11:12
3.3V PCI
JTAG Interface
3.3V CMOS
w/pull-up
TCK
Test Clock.
I
1
4
3.3V CMOS
w/pull-up
TDI
Test Data In.
I
O
I
TDO
TMS
Test Data Out.
Test Mode Select.
3.3V LVTTL
3.3V CMOS
w/pull-up
1
5
Test Reset. During chip power-up, this signal must be low from the
start of VDD ramp-up until at least 16 SysClk cycles after VDD is
stable in order to initialize the JTAG controller.
3.3V CMOS
w/pull-up
TRST
I
52
AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signal Functional Description (Sheet 6 of 7)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V, 10kΩ to 5V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
System Interface
Description
I/O
Type
Notes
5V tolerant
SysClk
SysErr
Main system clock input.
Clock
O
3.3V LVTTL
5V tolerant
3.3V LVTTL
Set to 1 when a machine check is generated.
Main system reset. External logic can drive this bidirectional pin
low (minimum of 16 cycles) to initiate a system reset. A system
reset can also be initiated by software. The signal is implemented
as an open-drain output (two states; 0 or open circuit).
During chip power-up, this signal must be low from the start of VDD
ramp-up until at least 16 SysClk cycles after VDD is stable.
5V tolerant
3.3V LVTTL
SysReset
I/O
1, 2
5V tolerant
TmrClk
Halt
Processor timer external input clock.
Halt from external debugger.
I
3.3V LVTTL
5V tolerant
3.3V LVTTL
I
1, 4
General purpose I/O 0 through 10. To access these functions,
software must set DCR register bits.
5V tolerant
GPIO00:31
TestEn
I/O
3.3V LVTTL
1.8V CMOS
w/pull-down
Test Enable.
I
I
I
I
3
5V tolerant
3.3V LVTTL
RcvrInh
RefVEn
DrvrInh1:2
Receiver Inhibit. Active only when TestEn is active.
Reference Voltage Enable. Do not connect for normal operation.
Pull up for Boundary Scan Description Language (BSDL) testing.
1.8V CMOS
w/pull-down
Driver Inhibit. Used for test purposes only. Tie up for normal
operation
5V tolerant
3.3V LVTTL
2
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Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signal Functional Description (Sheet 7 of 7)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V, 10kΩ to 5V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Trace Interface
Description
I/O
Type
Notes
5V tolerant
TrcBS0:2
TrcClk
Trace branch execution status.
I/O
O
3.3V LVTTL
Trace data capture clock, runs at 1/4 the frequency of the
processor.
5V tolerant
3.3V LVTTL
Trace Execution Status is presented every fourth processor clock
cycle.
5V tolerant
TrcES0:4
TrcTS0:6
I/O
I/O
3.3V LVTTL
5V tolerant
3.3V LVTTL
Additional information on trace execution and branch status.
Power Pins
AGND
PLL (analog) voltage ground.
Ground.
na
na
na
na
GND
1.8V—Filtered voltages input for PLLs (analog circuits)
Note: A separate filter for each of the three voltages is
recommended.
AxVDD
na
na
OVDD
SVDD
VDD
3.3V supply—I/O (except DDR SDRAM)
2.5V supply—DDR SDRAM
na
na
na
na
na
na
1.8V supply—Logic voltage.
Reserved Pins
Reserved
Do not connect signals, voltage, or ground to these balls.
na
na
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Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Absolute Maximum Ratings
The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause
permanent damage to the device. None of the performance specification contained in this document are guaranteed when
operating at these maximum ratings.
Characteristic
Supply Voltage (Internal Logic)
Symbol
Value
Unit
V
Notes
VDD
0 to +1.95
0 to +3.6
0 to +1.95
0 to +2.7
0 to +3.6
0 to +5.5
-55 to +150
-40 to +120
OVDD
AxVDD
SVDD
VIN
Supply Voltage (I/O Interface, except DDR SDRAM)
PLL Supply Voltages
V
V
1
Supply Voltage (DDR SDRAM Logic)
Input Voltage (3.3V LVTTL receivers)
Input Voltage (5.0V LVTTL receivers)
Storage Temperature Range
Case Temperature under bias
Notes:
V
V
VIN
V
TSTG
TC
°C
°C
2
1. The analog voltages used for the on-chip PLLs can be derived from the logic voltage, but must be filtered before entering the
PPC440GP. A separate filter, as shown below, is recommended for each voltage:
AxVDD
VDD
L – SMT ferrite bead chip, Murata BLM31A700S or equivalent.
L
C – 0.1μF ceramic
C
2. This value is not a specification of the operational temperature range; it is a stress rating only.
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Revision 1.07 – October 4, 2007
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Data Sheet
Package Thermal Specifications
Thermal resistance values for the CBGA and PBGA packages in a convection environment are as follows:
Airflow
ft/min (m/sec)
Parameter
Symbol
Package
Unit
Notes
0 (0)
<0.1
1.2
100 (0.51)
<0.1
200 (1.02)
<0.1
Ceramic
Plastic
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
1
Junction-to-case thermal resistance
θJC
θCA
θJB
1.2
1.2
1, 3
2
Ceramic
Plastic
18.9
17.7
16.3
Case-to-ambient thermal resistance (w/o heat
sink)
20.8
2, 3
Ceramic
Plastic
Junction-to-ball (typical)
8.0
3
Notes:
1. Case temperature, TC, is measured at top center of case surface with device soldered to circuit board.
2. The case-to-ambient thermal resistance is measured in a JEDEC JESD51-6 standard environment; and may not accurately predict
thermal performance in production equipment environments. The operational case temperature must be maintained.
3. Modeled on standard JEDEC 2S2P card, 50x50mm
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440GP – Power PC 440GP Embedded Processor
Data Sheet
Heat Sink Mounting Information (Ceramic Package Only)
Proper thermal design is primarily dependent upon multiple system-level effects; that is, the effects of the heat
sink, the air flow, and the thermal interface material. To reduce the die-junction temperature, heat sinks may be
attached to the package by several methods: adhesive, spring clips to the printed-circuit board or package, or a
mounting clip and screw assembly. When attaching heat sinks, it is important to avoid placing excessive
mechanical stress on bonding of the chip to the substrate and the package to the board.
Heat Sink Attached With Spring Clip
Heat sink
Heat sink
Heat sink clip
Heat sink clip
Thermal grease
Thermal grease
CBGA
CBGA
package
package
Printed
circuit
board
Printed
circuit
board
Spring clip to package
Spring clip to board
1
Static compression (spring force)—2.27kg maximum
Static compression (spring force)—2.27kg maximum
Note 1: Force is limited by allowable compression on the die.
Allowable package compression force is 4.4kg.
Heat Sink Attached With Adhesive
Heat sink
Adhesive
Printed
circuit
board
CBGA
CBGA
package
package
Adhesive
Printed
circuit
board
Heat sink
Weight
force
Weight
force
Heat sink weight force—60g maximum
Important: All of the guidelines indicated in the above diagrams must be evaluated and adjusted to account for the
shock and vibration effects of any particular application.
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440GP – Power PC 440GP Embedded Processor
Data Sheet
Recommended DC Operating Conditions
Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended
conditions can affect device reliability.
Parameter
Symbol
Minimum
+1.7
Typical
+1.8
Maximum
+1.9
Unit
V
Notes
VDD
Logic Supply Voltage
I/O Supply Voltage
4
4
4
3
3
2
1
OVDD
SVDD
+3.0
+3.3
+3.6
V
DDR SDRAM Supply Voltage (DDR clock up to 166MHz)
PLL Supply Voltages
+2.3
+2.5
+2.7
V
AxVDD
SVREF
+1.65
+1.15
SVREF+0.18
0.5OVDD
+2.0
+1.8
+1.95
V
DDR SDRAM Reference Voltage
+1.25
+1.35
V
SVDD+0.3
OVDD+0.5
Input Logic High (2.5V SSTL)
V
Input Logic High (3.3V PCI-X)
V
VIH
Input Logic High (3.3V LVTTL, 5V tolerant receiver)
Input Logic Low (2.5V SSTL)
+5.5
V
SVREF-0.18
-0.3
V
0.35OVDD
Input Logic Low (3.3V PCI-X)
-0.5
V
1
1
1
VIL
Input Logic Low (3.3V LVTTL, 5V tolerant receiver)
Output Logic High (2.5V SSTL)
0
+0.8
V
SVDD
+1.95
0.9OVDD
V
OVDD
OVDD
Output Logic High (3.3V PCI-X)
V
VOH
Output Logic High (3.3V LVTTL, 5V tolerant receiver)
Output Logic Low (2.5V SSTL)
+2.4
0
V
0.55
V
0.1OVDD
Output Logic Low (3.3V PCI-X)
V
VOL
Output Logic Low (3.3V LVTTL, 5V tolerant receiver)
Input Leakage Current (No pull-up or pull-down)
0
0
+0.4
0
V
IIL1
IIL2
IIL3
μA
Input Leakage Current for Pull-Down
Input Leakage Current for Pull-Up
0 (LPDL)
-150 (LPDL)
200 (MPUL)
0 (MPUL)
5
5
μA
μA
Input Max Allowable Overshoot (3.3V LVTTL, 5V tolerant
receiver)
VIMAO
+5.5
V
V
V
V
Input Max Allowable Undershoot (3.3V LVTTL, 5V tolerant
receiver)
VIMAU
-0.6
-0.6
Output Max Allowable Overshoot (3.3V LVTTL, 5V tolerant
receiver)
VOMAO
+5.5
Output Max Allowable Undershoot (3.3V LVTTL,
5V tolerant receiver)
VOMAU3
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Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Recommended DC Operating Conditions (Continued)
Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended
conditions can affect device reliability.
Parameter
Case Temperature rating for C package
Case Temperature rating E for C package
Case Temperature rating E for F package
Notes:
Symbol
Minimum
-40
Typical
Maximum
+85
Unit
°C
Notes
TC
6
6
6
TC
TC
-40
+105
°C
-40
+100
°C
1. PCI-X drivers meet PCI-X specifications.
2. SVREF = SVDD/2
3. The analog voltages used for the on-chip PLLs can be derived from the logic voltage, but must be filtered before entering the
PPC440GP. See “Absolute Maximum Ratings” on page 55.
4. During chip power-up, OVDD should begin to ramp before VDD. External voltage should not be applied to the chip I/O pins before
OVDD is applied to the chip. A power-down cycle should complete (OVDD and VDD should both be below 0.4V) before a new power-
up cycle is started.
5. LPDL is least positive down level; MPUL is most positive up level.
6. Case temperature, TC, is measured at top center of case surface with device soldered to circuit board.
Input Capacitance
Parameter
Symbol
Maximum
Unit
pF
Notes
CIN1
Group 1 (2.5V SSTL I/O)
12
12
12
9
CIN2
CIN3
CIN4
Group 2 (5V tolerant LVTTL I/O)
Group 3 (PCI-X I/O)
pF
pF
Group 4 (Receivers)
pF
DC Power Supply Loads
Parameter
Symbol
Minimum
Typical
Maximum
Unit
Notes
V
DD (1.8V) active operating current
IDD
915
125
560
33
mA
mA
mA
mA
2
2
OVDD (3.3V) active operating current
SVDD (2.5V) active operating current
AxVDD (1.8V) input current
Notes:
IODD
ISDD
IADD
2
1, 2
1. See “Absolute Maximum Ratings” on page 55 for filter recommendations.
2. The current values listed above are not guaranteed to be the highest obtainable. These values are dependent on many factors including
the type of applications running, clock rates, use of internal functional capabilities, external interface usage, case temperature, and the
power supply voltages. Your specific application can produce significantly different results. VDD (logic) current and power are primarily
dependent on the applications running and the use of internal chip functions (DMA, PCI, Ethernet, and so on). OVDD (I/O) current and
power are primarily dependent on the capacitive loading, frequency, and utilization of the external buses.
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440GP – Power PC 440GP Embedded Processor
Data Sheet
Test Conditions
Output
Pin
Clock timing and switching characteristics are specified in accordance with operating
conditions shown in the table “Recommended DC Operating Conditions.” AC
50pF
C
specifications are characterized with V = 1.8V, T = rated temperature and a 50pF
DD
C
test load as shown in the figure to the right.
Clocking Specifications
Symbol
Parameter
Minimum
Maximum
Units
Notes
SysClk Input
FC
Frequency
Period
33.33
15
66.66
30
MHz
ns
TC
TCS
TCH
TCL
Edge stability (cycle-to-cycle jitter)
–
0.15
ns
High time
Low time
40% of nominal period
40% of nominal period
60% of nominal period
60% of nominal period
ns
ns
Note:Input slew rate ≥ 1V/ns
PLL VCO
FC
TC
Frequency
Period
500
1
1000
2
MHz
ns
Processor Clock (CPU Clock)
FC
TC
Frequency
Period
–
2
500
–
MHz
ns
1
MemClkOut
FC
Frequency
Period
100
7.5
133.33
10
MHz
ns
TC
TCH
High time
35% of nominal period
65% of nominal period
ns
Notes:
1. The maximum supported processor clock frequency for any part is specified in the part number (see “Ordering and PVR Information”
on page 4).
Timing Waveform
2.0V
1.5V
0.8V
T
T
CL
CH
T
C
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Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Spread Spectrum Clocking
Care must be taken when using a spread spectrum clock generator (SSCG) with the PPC440GP. This controller
uses a PLL for clock generation inside the chip. The accuracy with which the PLL follows the SSCG is referred to
as tracking skew. The PLL bandwidth and phase angle determine how much tracking skew there is between the
SSCG and the PLL for a given frequency deviation and modulation frequency. When using an SSCG with the
PPC440GP the following conditions must be met:
• The frequency deviation must not violate the minimum clock cycle time. Therefore, when operating the
PPC440GP with one or more internal clocks at their maximum supported frequency, the SSCG can only lower
the frequency.
• The maximum frequency deviation cannot exceed −3%, and the modulation frequency cannot exceed 40kHz.
In some cases, on-board PPC440GP peripherals impose more stringent requirements.
• Use the Peripheral Bus Clock for logic that is synchronous to the peripheral bus since this clock tracks the
modulation.
• Use the DDR SDRAM MemClkOut since it also tracks the modulation.
Notes:
1. The serial port baud rates are synchronous to the modulated clock. The serial port has a tolerance of
approximately 1.5% on baud rate before framing errors begin to occur. The 1.5% tolerance assumes that
the connected device is running at precise baud rates.
2. Ethernet operation is unaffected.
3. IIC operation is unaffected.
Important: It is up to the system designer to ensure that any SSCG used with the PPC440GP meets the above
requirements and does not adversely affect other aspects of the system.
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440GP – Power PC 440GP Embedded Processor
Data Sheet
Peripheral Interface Clock Timings
Parameter
PCIXClk input frequency (asynchronous mode)
PCIXClk period (asynchronous mode)
PCIXClk input high time
Min
Max
Units
MHz
ns
Notes
–
133.33
2
7.5
–
40% of nominal period
60% of nominal period
ns
PCIXClk input low time
40% of nominal period
60% of nominal period
ns
EMCMDClk output frequency
EMCMDClk period
–
2.5
MHz
ns
400
–
EMCMDClk output high time
EMCMDClk output low time
EMCTxClk input frequency MII(RMII)
EMCTxClk period MII(RMII)
EMCTxClk input high time
160
–
ns
160
–
ns
2.5(5)
25(50)
MHz
ns
40(20)
35% of nominal period
35% of nominal period
2.5(5)
400(200)
–
ns
EMCTxClk input low time
–
ns
EMCRxClk input frequency MII(RMII)
EMCRxClk period MII(RMII)
EMCRxClk input high time
EMCRxClk input low time
25(50)
MHz
ns
40(20)
400(200)
35% of nominal period
35% of nominal period
–
–
–
ns
ns
EMCRefClk input frequency
EMCRefClk period
50
MHz
ns
20
EMCRefClk input high time
EMCRefClk input low time
PerClk output frequency (for ext. master or sync. slaves)
PerClk period
45% of nominal period
45% of nominal period
–
55% of nominal period
55% of nominal period
66.66
ns
ns
MHz
ns
15
–
PerClk output high time
50% of nominal period
33% of nominal period
66% of nominal period
50% of nominal period
ns
PerClk output low time
ns
1000/(2TOPB1+2ns)
UARTSerClk input frequency
UARTSerClk period
–
MHz
ns
1
1
1
1
2TOPB+2
TOPB+1
–
–
–
UARTSerClk input high time
UARTSerClk input low time
ns
T
OPB+1
ns
62
AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Peripheral Interface Clock Timings (Continued)
Parameter
Min
Max
Units
MHz
ns
Notes
TmrClk input frequency
TmrClk period
–
100
10
–
TmrClk input high time
TmrClk input low time
Notes:
40% of nominal period
40% of nominal period
60% of nominal period
60% of nominal period
ns
ns
1. TOPB is the period in ns of the OPB clock. The internal OPB clock runs at 1/2the frequency of the PLB clock. The maxi-
mum OPB clock frequency is 66.66 MHz.
2. When the PCI-X interface is used to support a legacy PCI interface, the maximum PCIXClk frequency is 66.66MHz.
AMCC
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Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Input Setup and Hold Waveform
Clock
T
min
IS
T
min
IH
Inputs
Valid
Output Delay and Float Timing Waveform
Clock
max
min
max
max
min
T
T
T
OV
OV
OV
T
T
min
T
OH
Outputs
OH
OH
High (Drive)
Float (High-Z)
Valid
Valid
Low (Drive)
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Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
I/O Specifications—All Speeds (Sheet 1 of 4)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
2. PCI-X timings are for asynchronous operation up to 133MHz. PCI-X input setup time requirement is 1.2ns for 133MHz and
1.7ns for 66MHz. PCI timings (in parentheses) are for asynchronous operation up to 66MHz. PCI output hold time
requirement is 1ns for 66MHz and 2ns for 33MHz.
3. The clock frequency for RMII operation is 50MHz 100ppm.
Input (ns)
Output (ns)
Output Current (mA)
Signal
Clock
Notes
Setup Time
(TIS min)
Hold Time
(TIH min)
Valid Delay
(TOV max)
Hold Time
(TOH min)
I/O H
(minimum)
I/O L
(minimum)
PCI-X Interface
PCIXAD00:63
PCIXC3:0[BE3:0]
PCIXParLow
PCIParHigh
PCIXFrame
PCIXINT
Note 2 (3)
Note 2 (3)
Note 2 (3)
Note 2 (3)
Note 2 (3)
na
0.5 (0)
0.5 (0)
0.5 (0)
0.5 (0)
0.5 (0)
na
3.8 (6)
3.8 (6)
3.8 (6)
3.8 (6)
3.8 (6)
dc
0.7 (Note 2)
0.7 (Note 2)
0.7 (Note 2)
0.7 (Note 2)
0.7 (Note 2)
dc
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
na
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
na
PCIXClk
PCIXClk
PCIXClk
PCIXClk
PCIXClk
PCIXClk
PCIXClk
PCIXClk
PCIXClk
PCIXClk
PCIXClk
PCIXClk
PCIXClk
2
2
2
2
2
async
PCIXIRDY
Note 2 (3)
Note 2 (3)
Note 2 (3
Note 2 (3)
Note 2 (3)
Note 2 (3)
Note 2 (3)
dc
0.5 (0)
0.5 (0)
0.5 (0)
0.5 (0)
0.5 (0)
0.5 (0)
0.5 (0)
dc
3.8 (6)
3.8 (6)
3.8 (6)
3.8 (6)
na
0.7 (Note 2)
0.7 (Note 2)
0.7 (Note 2)
0.7 (Note 2)
na
2
PCIXTRDY
PCIXStop
2
2
PCIXDevSel
PCIXIDSel
PCIXPErr
2
2
2
3.8 (6)
3.8 (6)
na
0.7 (Note 2)
0.7 (Note 2)
na
0.5
0.5
na
1.5
1.5
na
PCIXSErr
2
PCIXClk
async
PCIXReset
PCIXReq64
PCIXAck64
PCIXCap
na
na
na
na
na
na
PCIXClk
PCIXClk
PCIXClk
PCIXClk
PCIXClk
PCIXClk
PCIXClk
PCIXClk
Note 2 (3)
Note 2 (3)
Note 2 (3)
0.5 (0)
0.5 (0)
0.5 (0)
3.8 (6)
3.8 (6)
na
0.7 (Note 2)
0.7 (Note 2)
na
0.5
0.5
na
1.5
1.5
na
2
2
2
2
2
2
2
PCIX133Cap
PCIXM66En
PCIXReq0:5
PCIXGnt0:5
3.8
0.7
0.5
na
1.5
na
Note 2 (3)
Note 2 (3)
na)
0.5 (0)
0.5 (0)
na
na
na
na
na
na
na
3.8 (6)
0.7 (Note 2)
0.5
1.5
AMCC
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Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
I/O Specifications—All Speeds (Sheet 2 of 4)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
2. PCI-X timings are for asynchronous operation up to 133MHz. PCI-X input setup time requirement is 1.2ns for 133MHz and
1.7ns for 66MHz. PCI timings (in parentheses) are for asynchronous operation up to 66MHz. PCI output hold time
requirement is 1ns for 66MHz and 2ns for 33MHz.
3. The clock frequency for RMII operation is 50MHz 100ppm.
Input (ns)
Output (ns)
Output Current (mA)
Signal
Clock
Notes
Setup Time
(TIS min)
Hold Time
(TIH min)
Valid Delay
(TOV max)
Hold Time
(TOH min)
I/O H
(minimum)
I/O L
(minimum)
Ethernet MII Interface
EMCRxD0:3
4
4
1
1
na
na
na
na
n/a
n/a
n/a
n/a
EMCRxClk
EMCRxClk
1
1
EMCRxDV
1,
async
EMCRxClk
na
na
na
na
n/a
n/a
EMCRxErr
EMCTxD0:3
EMCTxEn
4
1
na
15
15
na
2
n/a
n/a
7.1
7.1
EMCRxClk
EMCTxClk
EMCTxClk
1
1
1
na
na
na
na
10.3
10.3
2
1,
EMCTxClk
EMCTxErr
EMCCrS
na
na
na
na
na
15
na
na
2
na
10.3
n/a
na
7.1
n/a
async
EMCTxClk
EMCMDClk
1
1,
async
na
1,
async
EMCCD
na
na
n/a
n/a
7.1
7.1
EMCMDIO
EMCMDClk
10.3
10.3
1
1,
async
na
na
na
na
Ethernet RMII Interface
EMC0RxD0:1
EMC0RxErr
2
2
1
1
na
na
na
11
11
na
na
na
11
na
na
na
2
n/a
n/a
n/a
n/a
n/a
7.1
7.1
7.1
n/a
n/a
7.1
EMCRxClk
EMCRxClk
EMCRxClk
EMCTxClk
EMCTxClk
EMCRxClk
EMCRxClk
EMCRxClk
EMCTxClk
EMC0CrSDV
EMC0TxD0:1
EMC0:1TxEn
EMC1RxD0:1
EMC1RxErr
n/a
na
na
na
na
10.3
10.3
10.3
n/a
2
na
na
na
2
EMC1CrSDV
EMC1TxD0:1
n/a
na
na
na
na
10.3
3,
async
EMCRefClk
na
na
10.3
7.1
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Data Sheet
I/O Specifications—All Speeds (Sheet 3 of 4)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
2. PCI-X timings are for asynchronous operation up to 133MHz. PCI-X input setup time requirement is 1.2ns for 133MHz and
1.7ns for 66MHz. PCI timings (in parentheses) are for asynchronous operation up to 66MHz. PCI output hold time
requirement is 1ns for 66MHz and 2ns for 33MHz.
3. The clock frequency for RMII operation is 50MHz 100ppm.
Input (ns)
Output (ns)
Output Current (mA)
Signal
Clock
Notes
Setup Time
(TIS min)
Hold Time
(TIH min)
Valid Delay
(TOV max)
Hold Time
(TOH min)
I/O H
(minimum)
I/O L
(minimum)
Internal Peripheral Interface
IICxSClk
na
na
na
na
na
na
15.3
15.3
na
10.2
10.2
na
IICxSDA
UARTSerClk
UART0_Rx
UART0_Tx
UART0_DCD
UART0_DSR
UART0_CTS
UART0_DTR
UART0_RI
UART0_RTS
UART1_Rx
UART1_Tx
UART1_DSR/CTS
UART1_RTS/DTR
Interrupts Interface
IRQ00:12
na
na
na
na
na
na
na
na
10.3
na
7.1
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
10.3
na
7.1
na
na
na
na
na
na
na
10.3
na
7.1
na
10.3
na
7.1
na
10.3
7.1
na
na
JTAG Interface
TDI
na
na
na
na
async
async
async
async
async
TMS
TDO
15.3
na
10.2
na
TCK
TRST
na
na
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Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
I/O Specifications—All Speeds (Sheet 4 of 4)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
2. PCI-X timings are for asynchronous operation up to 133MHz. PCI-X input setup time requirement is 1.2ns for 133MHz and
1.7ns for 66MHz. PCI timings (in parentheses) are for asynchronous operation up to 66MHz. PCI output hold time
requirement is 1ns for 66MHz and 2ns for 33MHz.
3. The clock frequency for RMII operation is 50MHz 100ppm.
Input (ns)
Output (ns)
Output Current (mA)
Signal
Clock
Notes
Setup Time
(TIS min)
Hold Time
(TIH min)
Valid Delay
(TOV max)
Hold Time
(TOH min)
I/O H
(minimum)
I/O L
(minimum)
System Interface
SysClk
na
na
na
na
na
na
na
na
na
na
7.1
na
na
7.1
TmrClk
async
async
async
async
async
SysReset
Halt
na
na
na
na
SysErr
na
na
10.3
na
TestEn
na
na
na
na
DrvrInh1:2
GPIO00:31
Trace Interface
TrcClk
na
10.3
na
na
10.3
10.3
10.3
10.3
7.1
7.1
7.1
7.1
TrcBS0:2
TrcES0:4
TrcTS0:6
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Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
I/O Specifications—400, 466, and 500MHz
Notes:
1. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 1.3ns.
Input (ns)
Output (ns)
Output Current (mA)
Setup
Signal
Clock
Notes
Hold Time
(TIH min)
Valid Delay
(TOV max)
Hold Time
(TOH min)
I/O H
(minimum)
I/O L
(minimum)
Time
(TIS min)
External Slave Peripheral Interface
PerData00:31
PerAddr00:31
PerPar0:3
3
3
1
1
9
7.6
8.4
6.5
6
0
0
15.3
15.3
15.3
15.3
15.3
15.3
15.3
15.3
na
10.2
10.2
10.2
10.2
10.2
10.2
10.2
10.2
na
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
4
1
0
PerWBE0:3
PerCS0:7
2.5
na
na
na
2.5
5
1
0
na
na
na
1
0
PerOE
6
0
PerWE
7
0
PerBLast
5
na
na
na
na
0
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerReady[RcvrInh]
PerR/W
1
na
5.6
na
7
2.5
dc
na
dc
1
15.3
na
10.2
na
DMAReq0:3
DMAAck0:3
EOT0:3/TC0:3
dc
na
dc
15.3
15.3
10.2
10.2
6.8
0
External Master Peripheral Interface
PerClk
na
na
na
na
1
na
6.2
na
na
0
15.3
15.3
na
10.2
10.2
na
PLB Clk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
1
ExtReset
HoldReq
HoldAck
ExtReq
ExtAck
3.5
na
na
0
na
1
6.4
na
15.3
na
10.2
na
2.5
na
na
0
na
na
1
6.2
6.2
na
15.3
15.3
15.3
10.2
10.2
10.2
BusReq
PerErr
na
0
4.5
na
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Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
DDR SDRAM I/O Specifications
The DDR SDRAM controller times its operation with internal PLB clock signals and generates MemClkOut0 from
the PLB clock. The PLB clock is an internal signal that cannot be directly observed. However MemClkOut0 is the
same frequency as the PLB clock signal and is in phase with the PLB clock signal.
Note: MemClkOut0 can be advanced with respect to the PLB clock by means of the SDRAM0_CLKTR program-
ming register. In a typical system, users advance MemClkOut by 90°. This depends on the specific applica-
tion and requires a thorough understanding of the memory system in general (refer to the DDR SDRAM
controller chapter in the PowerPC 440GP User’s Manual).
In the following sections, the label MemClkOut0(0) refers to MemClkOut0 when it has not been phase-shifted, and
MemClkOut0(90) refers to MemClkOut0 when it has been phase-advanced 90°. Advancing MemClkOut0 by 90°
creates a 3/4 cycle setup time and 1/4 cycle hold time for the address and control signals in relation to
MemClkOut0(90). The rising edge of MemClkOut0(90) aligns with the first rising edge of the DQS signal.
The following DDR data is generated by means of simulation and includes logic, driver, package RLC, and lengths.
Values are calculated over best case and worst case processes with speed, temperature, and voltage as follows:
Best Case = Fast process, -40°C, +1.9V
Worst Case = Slow process, +85°C, +1.7V
Note: In all the following DDR tables and timing diagrams, the maximum values are measured under worst case
conditions. The minimum values (best case) are estimates based on comparable timing in a similar chip of a differ-
ent technology.
The signals are terminated as indicated in the figure below for the DDR timing data in the following sections.
DDR SDRAM Simulation Signal Termination Model
MemClkOut0
10pF
120Ω
10pF
MemClkOut0
V
= SV /2
DD
TT
PPC440GP
50Ω
Addr/Ctrl/Data/DQS
10pF
Note: This diagram illustrates the model of the DDR SDRAM interface used when generating simulation timing data.
It is not a recommended physical circuit design for this interface. An actual interface design will depend on many
factors, including the type of memory used and the board layout.
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Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
DDR SDRAM Output Driver Specifications
Output Current (mA)
Signal Path
I/O H (maximum)
I/O L (minimum)
Write Data
MemData00:07
MemData08:15
MemData16:23
MemData24:31
MemData32:39
MemData40:47
MemData48:55
MemData56:63
ECC0:7
15.2
15.2
15.2
15.2
15.2
15.2
15.2
15.2
15.2
15.2
15.2
15.2
15.2
15.2
15.2
15.2
15.2
15.2
15.2
15.2
15.2
15.2
15.2
15.2
15.2
15.2
15.2
15.2
15.2
15.2
15.2
15.2
15.2
15.2
15.2
15.2
15.2
15.2
DM0:8
MemClkOut0
MemAddr00:12
BA0:1
RAS
CAS
WE
BankSel0:3
ClkEn0:3
DQS0:8
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Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
DDR SDRAM Write Operation
The following diagram illustrates the relationship among the signals involved with a DDR write operation.
DDR SDRAM Write Cycle Timing
PLB Clk
MemClkOut0
MemClkOut0(90)
T
SA
Addr/Cmd
T
DS
T
T
SK
DS
T
HA
DQS
T
SD
T
SD
MemData
T
HD
T
HD
T
= Delay from rising edge of MemClkOut0(0) to rising/falling edge of signal (skew)
= Setup time for address and command signals to MemClkOut0(90)
SK
T
SA
T
T
T
T
= Hold time for address and command signals from MemClkOut0(90)
HA
SD
HD
DS
= Setup time for data signals (minimum time data is valid before rising/falling edge of DSQ)
= Hold time for data signals (minimum time data is valid after rising/falling edge of DSQ)
= Delay from rising/falling edge of clock to the rising/falling edge of DQS
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Data Sheet
I/O Timing—DDR SDRAM T
DS
Notes:
1. All of the DQS signals are referenced to MemClkOut0(0).
2. The TDS values in the table include 3/4 of a cycle at the indicated clock speed.
3. To obtain adjusted values for lower clock frequencies, subtract 5.625 ns from the values in the table and add 3/4 of the cycle
time for the lower clock frequency (TDS - 5.625 + 0.75TCYC).
TDS (ns)
Clock Speed (MHz)
Signal Name
Minimum
Maximum
6.25
133
133
133
133
133
133
133
133
133
DQS0
na
na
na
na
na
na
na
na
na
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
6.25
6.25
6.25
6.25
6.25
6.25
6.25
6.25
I/O Timing—DDR SDRAM T , T , and T
SK SA
HA
Notes:
1. TSK is referenced to MemClkOut0(0). TSA and THA are referenced to MemClkOut0(90).
2. To obtain adjusted TSA values for lower clock frequencies, use 3/4 of the cycle time for the lower clock frequency and
subtract TSK maximum (0.75TCYC - TSKmax).
3. To obtain adjusted THA values for lower clock frequencies, use 1/4 of the cycle time for the lower clock frequency and add
TSK minimum (0.25TCYC + TSKmin).
TSK (ns)
TSA (ns)
THA (ns)
Clock Speed (MHz)
Signal Name
Minimum
0.4
Maximum
1.2
Minimum
4.425
4.425
4.425
4.425
4.425
4.425
4.425
Minimum
2.275
2.275
2.275
2.275
2.275
2.275
2.275
133
133
133
133
133
133
133
MemAddr00:12
BA0:1
0.4
1.2
BankSel0:3
ClkEn0:3
CAS
0.4
1.2
0.4
1.2
0.4
1.2
RAS
0.4
1.2
WE
0.4
1.2
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Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
I/O Timing—DDR SDRAM T and T
SD
HD
Notes:
1. TSD and THD are measured under worst case conditions.
2. The time values in the table include 1/4 of a cycle at the indicated clock speed.
3. To obtain adjusted TSD and THD values for lower clock frequencies, subtract 1.875 ns from the values in the table and add
1/4 of the cycle time for the lower clock frequency (e.g., TSD - 1.875 + 0.25TCYC).
TSD (ns)
THD (ns)
Clock Speed (MHz)
Signal Names
Reference Signal
DQS0
133
133
133
133
133
133
133
133
133
MemData00:07, DM0
MemData08:15, DM1
MemData16:23, DM2
MemData24:31, DM3
MemData32:39, DM4
MemData40:47, DM5
MemData48:55, DM6
MemData56:63, DM7
ECC0:7, DM8
1.375
1.375
1.375
1.375
1.375
1.375
1.375
1.375
1.375
1.375
1.375
1.375
1.375
1.375
1.375
1.375
1.375
1.375
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
DDR SDRAM Read Operation
The following examples of timing for DDR SDRAM read operations are based on the relationship between the
incoming data and the PLB clock signal. Since the PLB clock cannot be directly observed, the delay of
MemClkOut(0) relative to the PLB clock (T ) is provided.
MD
The internal Read Clock signal, like MemClkOut0, is derived from the PLB clock and can be delayed relative to the
PLB clock by programming the RDCT and RDCD fields in the SDRAM0_TR1 register. The delay can be
programmed from 0 to 1/2 cycle in steps using RDCT. Setting RDCD results in a 1/2 cycle delay plus the value set
in RDCT. The delay of Read Clock relative to the PLB clock (T ) shown below assumes the programmable Read
RD
Clock delay is set to zero.
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Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
DDR SDRAM MemClkOut0 and Read Clock Delay
PLB Clk
MemClkOut0(0)
T
MD
T
min = 850ps
MD
T
max =
2600ps
MD
Read Clock
T
RD
T
min =
0ps
RD
T
max =
300ps
RD
In operation, following the receipt of an address and read command from the PPC440GP, the SDRAM generates
data and the DQS signals coincident with MemClkOut0. The data is latched into the PPC440GP using a DQS
signal that is delayed 1/4 of a cycle. In order to accommodate timing variations introduced by the system designs
using this chip, the three-stage data path shown below is used to eliminate metastability and allow data sampling to
be adjusted for minimum latency. This adjustment requires programming the Read Clock delay and the selection of
Stage 1, Stage 2, or Stage 3 data for sampling at RDSP.
DDR SDRAM Read Data Path
Mux
RDSP
FF
Package pins
Q
D
PLB bus
ECC
Stage 3
Stage 1
Stage 2
Q
D
Q
D
D
Q
C
FF,
XL
FF
FF
Data
C
C
C
Read Select
(SDRAM0_TR1)
1/4
Cycle
Delay
Programmed
Read Clock
Delay
DQS
PLB Clock
FF Timing:
T
T
T
= Input setup time = 0.2ns
= Input hold time = 0.1ns
= Propagation delay (D to Q or C to Q) =
FF: Flip-Flop
XL: Transparent Latch
IS
IH
0.6ns maximum
P
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Revision 1.07 – October 4, 2007
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Data Sheet
I/O Timing—DDR SDRAM T
and T
DIN
SIN
Notes:
1. TSIN = Delay from DQS at package pin to C on Stage 1 FF.
2. TDIN = Delay from data at package pin to D on Stage 1 FF.
3. The time values for TSIN include 1/4 of a cycle at the indicated clock speed.
TSIN (ns)
minimum
TSIN (ns)
maximum
TDIN (ns)
minimum
TDIN (ns)
maximum
Clock Speed (MHz)
Signal Name
Signal Name
133
133
133
133
133
133
133
133
133
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
2.775
2.775
2.775
2.775
2.775
2.775
2.775
2.775
2.775
3.775
3.775
3.775
3.775
3.775
3.775
3.775
3.775
3.775
MemData00:07
MemData08:15
MemData16:23
MemData24:31
MemData32:39
MemData40:47
MemData48:55
MemData56:63
ECC0:7
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
In the following examples, the data strobes (DQS) and the data are shown to be coincident. There is actually a
slight skew as specified by the SDRAM specifications, and there can be additional skew due to loading and signal
routing. It is recommended that the signal length for all of the eight DQS signals be matched.
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Revision 1.07 – October 4, 2007
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Data Sheet
Example 1:
If the data-to-PLB clock timing is as shown in the example below, then the read clock is not delayed and the Stage
1 data is sampled at (1). Except for small, low frequency memory systems with the memory located physically
close to the PPC440GP, it is unlikely that Stage 1 data can be sampled. When the data comes later, it is necessary
to sample Stage 2 or Stage 3 data. (see Examples 2 and 3). Another way to get the desired data-to-PLB timing to
allow Stage 1 sampling is to buffer MemClkOut0 and skew it enough to guarantee the timing. In this example
T = 1.5ns at worst case conditions.
T
DDR SDRAM Read Cycle Timing—Example 1
DQS at pin
Data at pin
D0
D1
D3
D2
T
SIN
DQS Stage 1 C
Data in Stage 1 D
D0
D1
D3
D2
T
DIN
T
P
T
P
High
Low
D0
D1
D2
D3
Data out Stage 1
D0
D2
High
Low
D0
D1
D2
D3
Data in at RDSP
with no ECC
D2
D0
T
T
PLB Clock
High
Low
D0
D1
D2
D3
Data out RDSP
(1)
T
= Delay from DQS at package pin to C on Stage 1 FF.
= Propagation delay through FFs
SIN
T
P
T
= Delay from data at package pin to D on Stage 1 FF.
DIN
T = Propagation delay, Stage 1 input to RDSP input w/o ECC
T
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Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Example 2:
In this example Read Clock is delayed almost 1/2 cycle. Without ECC, Stage 2 data can be sampled at (2). If ECC
is enabled, Stage 3 data must be sampled (see Example 3). In this example, T = 1.5ns and T = 4.3ns at worst
T
TE
case conditions.
DDR SDRAM Read Cycle Timing—Example 2
DQS at pin
Data at pin
D0
D1
D3
D2
T
SIN
DQS Stage 1 C
Data in Stage 1 D
D0
D1
D3
D2
T
DIN
T
P
High
Low
D0
D1
D2
D3
Data out Stage 1
D0
D2
PLB Clock
Read Clock Delayed
T
P
D0
D1
High
D2
D3
Data out Stage 2
Low
High
Low
D2
D3
D0
D1
Data in at RDSP
without ECC
T
T
T
TE
High
Low
D0
D1
D2
D3
Data in at RDSP
with ECC
High
Low
D0
D1
D2
D3
Data out at RDSP
without ECC
(2)
T = Propagation delay from Stage 2 input to RDSP input w/o ECC
T
T
= Propagation delay from Stage 2 input to RDSP input with ECC
TE
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Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Example 3:
In this example, ECC is enabled. This requires that Stage 3 data be sampled at (3). If ECC is disabled, the system
will still work, but there will be more latency before the data is sampled into RDSP. Again, T = 1.5ns and T
=
T
TE
4.3ns at worst case conditions.
DDR SDRAM Read Cycle Timing—Example 3
DQS at pin
Data at pin
D0
D1
D3
D2
T
SIN
DQS Stage 1 C
Data in Stage 1 D
D0
D1
D3
D2
T
DIN
T
P
High
Low
D0
D1
D2
D3
Data out Stage 1
D0
D2
PLB Clock
Read Clock Delayed
T
P
D0
D1
High
D2
D3
Data out Stage 2
Low
High
Low
D2
D3
D0
D1
Data out Stage 3
with ECC
T
TE
High
Low
D0
D1
D2
D3
Data in at RDSP
with ECC
High
Low
D0
D1
D2
D3
Data out RDSP
with ECC
(3)
T = Propagation delay from Stage 2 input to RDSP input w/o ECC
T
T
= Propagation delay from Stage 2 input to RDSP input with ECC
TE
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Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Initialization
The PPC440GP provides the option for setting initial parameters based on default values or by reading them from
a slave PROM attached to the IIC0 bus (see “Serial EEPROM” below). Some of the default values can be altered
by strapping on external pins (see “Strapping” below).
Strapping
While the SysReset input pin is low (system reset), the state of certain I/O pins is read to enable certain default
initial conditions prior to PPC440GP start-up. The actual capture instant is the nearest reference clock edge before
the deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-down (logical 0)
resistors to select the desired default conditions. They are used for strap functions only during reset. Following
reset they are used for normal functions.
The following table lists the strapping pins along with their functions and strapping options:
Strapping Pin Assignments
Function
Option
Ball Strapping
V24
(UART0_DCD)
Disabled
Enabled
0
1
Bootstrap controller
V02
(UART0_DSR)
0x54
0x50
0
1
IIC0 slave address that will respond with boot data
Serial EEPROM
During reset, initial conditions other than those obtained from the strapping pins can be read from a ROM device
connected to the IIC0 port. At the de-assertion of reset, if the bootstrap controller is enabled, the PPC440GP
sequentially reads 16 bytes from the ROM device on the IIC0 port and sets the SYS0and SYS1 registers
accordingly. Otherwise, the default values set in the STRP0 and STRP1 registers are used for initialization.
The initialization settings and their default values are covered in detail in the PowerPC 440GP Embedded
Processor User’s Manual.
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Data Sheet
Revision Log
Date
Contents of Modification
08/07/2002
08/30/2002
09/11/2002
10/22/2002
11/20/2002
01/07/2003
01/22/2003
03/25/2003
06/16/2003
08/22/2003
01/21/2004
02/12/2004
05/12/2004
07/8/2004
Add revision log.
Change EMC0:1TxD0:1 and EMC0:1TxEn TOV from 15 to 11 ns.
Update for 466 and 500 MHz parts
Add heat sink mounting information and additional part numbers for E temperature range.
Update I/O timing data.
Update PCI-X I/O voltage specification.
Correct description of SysReset signal.
Update DDR SDRAM timing.
Change PCI setup specification from 2 to 3ns.
Remove references to 2xPLB in DDR SDRAM timing section.
Update DDR SDRAM timing section to be consistent 440GX presentation.
Restore VDD/OVDD voltage sequence restriction.
Add plastic package data and update part number list.
Update supported part numbers.
Add information on minimum SysClk and TRST duration during power-on reset.
Remove power sequence restrictions note from Absolute Maximum Rating table.
Restate power sequencing restrictions in Recommended DC Operating Conditions table.
Convert to AMCC format.
11/01/2004
12/09/2004
06/07/2005
10/17/2005
Remove references to Ethernet SMII mode.
Add reduced-lead part numbers.
Clarify DDR SDRAM interface diagram.
Remove metal-layer specification from technology description.
Add logo and number nomenclature to package drawing.
11/07/2005
08/30/2007
Change the technical support telephone and fax number.
AMCC
81
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Printed in the United States of America, Thursday, October 04, 2007
The following are trademarks of AMCC in the United States, or other countries, or both:
AMCC
Other company, product, and service names may be trademarks or service marks of others.
The information contained in this document is subject to change or withdrawal at any time without notice
and is being provided on an "AS IS" basis without warranty or indemnity of any kind, whether express or
implied, including without limitation, the implied warranties of non-infringement, merchantability, or fitness
for a particular purpose. Any products, services, or programs discussed in this document are sold or
licensed under AMCC's standard terms and conditions, copies of which may be obtained from your local
AMCC representative. Nothing in this document shall operate as an express or implied license or indemnity
under the intellectual property rights of AMCC or third parties.
Without limiting the generality of the foregoing, any performance data contained in this document was
determined in a specific or controlled environment and not submitted to any formal AMCC test. Therefore,
the results obtained in other operating environments may vary significantly. Under no circumstances will
AMCC be liable for any damages whatsoever arising out of or resulting from any use of the document or the
information contained herein.
82
AMCC
Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Applied Micro Circuits Corporation
215 Moffett Park Drive, Sunnyvale, CA 94089
Phone: (408) 542-8600 — (800) 840-6055 — Fax: (408) 542-8601
http://www.amcc.com
AMCC reserves the right to make changes to its products, its data sheets, or related documentation, without notice and war-
rants its products solely pursuant to its terms and conditions of sale, only to substantially comply with the latest available data
sheet. Please consult AMCC’s Term and Conditions of Sale for its warranties and other terms, conditions and limitations.
AMCC may discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest
version of relevant information to verify, before placing orders, that the information is current. AMCC does not assume any lia-
bility arising out of the application or use of any product or circuit described herein, neither does it convey any license under
its patent rights nor the rights of others. AMCC reserves the right to ship devices of higher grade in place of those of lower
grade.
AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE
SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL
APPLICATIONS.
AMCC is a registered Trademark of Applied Micro Circuits Corporation. Copyright © 2007 Applied Micro Circuits Corporation.
AMCC
83
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