概述
数据手册CS4811 概述
Multi Protocol Termination for 2047 Channels 多协议终止的2047频道
CS4811 数据手册
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PDF下载FINALProduct Brief
TIGRIS
Part Number S4811, Rev. 2.4 July 2006
OC-48 Multi Protocol Termination for 2047 Channels
TIGRIS is a high density data-termination device supporting 2047 channels operating at an aggregate rate of 2.488Gbps. The
device aggregates and terminates both ATM cells and HDLC frames, enabling ATM services such as Cell Relay, IMA, AAL2/5, and
frame based services, such as PPP, Frame Relay, and Multi-link PPP and Multi-link Frame Relay. The 2047 individually assignable
channels can be configured for Frame Relay, HDLC, PPP, and or ATM services for DS0, NxDS0, DS1/E1, DS3/E3, STS-1c, STS-3c
and STS-12c rates.
TIGRIS supports up to 48 channels of subrate DS3 services interoperating with major CSU/DSU vendors protocols and can be com-
bined with AMCC’s nP3700 to provide AAL2/5, IMA, and Multilink services for all 2047 channels.
• An Eexpaannssiioonn mode allows multiple TIGRIS devices to share
a single FTI interface (allows up to 8K channels).
Data sSeerrvvicceess aanndd pPeerrffoorrmmaanncceemMoonnitoorrinngg
• Store and forward architecture with extensive buffering using
external DDR SDRAM.
• Glueless interface to up to four AMCC Evros framers.
System Interface
• 2047 bi-directional ATM/HDLC channels that can be
assigned to tributaries from STS-12 to DS0.
• SPI-3 32bit @ 104MHz for cells/packets and error status.
• Bit synchronousHDLCsupportall channels (DS3 and lower
rate).
• The SPI-3 supports four interleaved channels (four logical
PHY ports).
• Byte synchronous HDLC support for all channels (STS-1 and
higher rate).
• Pre-pended packet tag for channel ID, length, error status,
TX queue priority, and TX per packet loopback.
• Direct Map ATM support.
Device Specifications
• G.832 E3 ATM support.
• 899 PBGA (31x31mm with 1mm ball pitch) package with
• Support for up to 48 DS3 PLCP ATM mapped channels.
• Support for up to 48 sub-rateDS3channels.
Green/RoHS compliant option
• 1.2V core, 2.5V I/O
FTI-2 LineInterface
• Four independent STS-12 capable interfaces selectable from
four serial 622 MHz LVDS Flexible Tributary interfaces (FTI-
2) or one Parallel FTI 8-bit x 78MHz Interface. Parallel
Interface is compatible with standard Telecom Bus interfaces.
• 6.0W maximum power consumption
Figure 1: Block Diagram
SERIAL
ATI
INTERFACES
EXTERNAL
SDRAM
(RX Frame storage)
EXTERNAL
SDRAM
(TX Frame storage)
12
24
PARALLEL 8 BIT @77Mhz
INTERFACE
TDAT[0:31]
TSX
LTX_DATA[7:0]]
TSOP
TPRTY
TMOD[1:0]
TERR
EXTERNAL MEMORY I/F
LTX_CONTROL_SIGNALS
LRX_DATA[7:0]]
TRANSMIT
4X FTI
FRAMER
TRANSMIT
FIFO
ATI SERIAL CLK and
DATA I/F
TEOP
TENB
LRX_CONTROL_SIGNALS
MEMORY
MANAGER
TFCLK
RSA[3:0]
STPA
SUBRATE
DS3
/ DS3
PLCP
FRAMER
4 x 622Mhz LVDS
SERIAL INTERFACES
SCLK
PTPA
HDLC / ATM
Processor
DTPA[3:0]
TADR[1:0]
LTX_DATA622[3:0]
LTX_CLK622[3:0]
RFCLK
RSX
QUEUE MANAGER
LTX_CONTROL622[3:0]
RSOP
RPRTY
RMOD[1:0]
RERR
LRX_DATA622[3:0]
LRX_CLK622[3:0]
RECEIVE
4X FTI
FRAMER
RECEIVE
FIFO
REOP
PMON
RENB
LRX_CONTROL622[3:0]
RVAL
JTAG PORT
MICROPROCESSOR I/F
RDAT[0:31]
FINAL Information - The information contained in this document is
about a product that has been fully tested, characterized, and is produc-
tion released. All features described herein are supported. Contact
AMCC for updates to this document and the latest product status.
Empowering Intelligent Optical Networks
FINAL Product Brief
TIGRIS
OC-48 Multi Protocol Termination for 2047 Channels
Part Number S4811, Rev. 2.4 July 2006
• Frame Relay switches and multiplexors.
Applications
• ATM or SMDS switches, multiplexors, and routers.
• Internet/Intranet termination equipment.
• Supports Frame Relay, PPP, HDLC as well as ATM
protocols within one device to allow easy software
scalable solutions.
• Frame Relay inter-networking service for ATM switches
and multiplexors.
• Dense channelization of fiber connections to client
tributaries (DS1/E1/J1 and DS3/E3) and termination for
data applications in multi-service switches and
Aggregation routers.
• Multiservice platforms supporting a combination of Frame
Relay, Multi Link Frame Relay, Multi Link PPP, IMA, AAL2,
AAL3/4 and AAL5 ATM protocols.
• Packet Over SONET application.
• ATM mapping into SONET applications.
• Packet and cell based DSLAM equipment.
Figure 2: OC-48/4xOC-12/16xOC-3/12xDS3/E3 Channelized Data Termination
Example shows a channelized OC-48 .
The AMCC EVROS can accept any
combination of up to 12x DS3/E3 LIU interface,
4xOC-3 optical interface or a single OC-12
optical interface over Primary and Protection
Line interface with built in STS-1 granularity
switching
AMCC Flexible Tributary Interface (FTI)
622MHz BW Supports any valid
combination or mix of the following:
1xSTS12c, 4xSTS3c, 12xSTS1
12DS3/E3, 336DS1/VT1.5, 252E1/VT2
Industry standard
SPI-3 interface for
Cells and packets
transfer
Industry standard
SPI-4.2 interface
for Cells and
DS3/E3
STS-1
LIU
EVROS
S1208
packets transfer
x12
x12
12 XDS3/E3
EVROS
S1208
S3455
DANUBE
S4805
TIGRIS
S4811
NP3700
OC-48
EVROS
S1208
Byte interleaver and
STS-1 pointer processor
1xOC-48
HDLC/ATM controller
2047 channels
of cells or packets
from 56K to 622Mb/s
Supports fractional DS3
Network Processor
Supported Services
- Multilink PPP/FR
- IMA
4xOC-12
16xOC-3
- AAL5
EVROS
4xOC12
or
16xOC3
S1208
S1212
x4
SONET to PDH framer mapper
1xOC-12/ 4XOC-3 or 12x DS3/E3
336DS1/VT1.5
252E1/VT2
2
Empowering Intelligent Optical Networks
FINAL Product Brief
TIGRIS
OC-48 Multi Protocol Termination for 2047 Channels
Part Number S4811, Rev. 2.4 July 2006
receive and the transmit direction.
FUNCTIONAL BLOCKS OVERVIEW
• Optional pre format (X43+1) frame scrambling and post
de-format scrambling support on channels 0 to 47.
FTI Interface
• Provides a high-speed interconnection between a
SONET/SDH physical layer device and a Link layer
device, or a SONET/SDH physical layer device and one
or more PDH physical layer devices.
• Octet Alignment checking.
• Min/Max frame length checking.
• Abort sequence checking.
• 56Kb/s support with Idle bit control.
• Inter-frame fill control.
• High bandwidth interface, capable of carrying an STS-12
bandwidth carrying 1xSTS-12c, 4xSTS-3c, 12xSTS-
1,12xDS3, 12xE3, 336xDS1/VT1.5/TU11 or 252xE1/
VT2/TU12 payloads, or any valid mix of the above.
• Data Inversion control.
• The Parallel version runs at a 77.76 MHz speed,
transferring 8-bits of data on every clock cycle and is
compatible with standard Telecom bus.
• Force bad CRC for diagnostics.
• Optional pass/discard errored frames per RX channel.
• Extensive Per channel statistics that include:
• The serial version transfers data bits in a 622.08 Mb/s
across a LVDS serial link.
• Good Frame/Byte counts on both TX and RX.
• FCS/CRC error counts on RX.
• Octet alignment error counts on RX.
• Frame length violations on RX.
• Received frame aborts counts.
• RX overrun events count.
• Supports byte floating (byte aligned) tributary bytes
aligned to system boundaries.
• Support both asynchronous (DS3/E3/DS1/E1) and
synchronous(VT1.5/VT2/TU11/TU12) payloads time
division multiplexed into the system frame.
• TX aborts sent count.
• Support synchronous SONET mappings (STS-1/STS-3c/
STS-12c/VT1.5/VT2 synchronous payload envelopes).
ATM Processor
• 2047 user assignable channels.
SPI-3 Interface
• Supports direct ATM cell mappings for STS12c, STS3c,
STS1c, DS3, DS1, E1, DS0, and NxDS0.
• Industry standard variable length packet interface
supporting transmit and receive data transfers at rates
independent of the line bit rate.
• Supports G.832 ATM cell mapping for E3.
• Supports PLCP ATM cell mapping for DS3.
• Defines both byte-level and packet-level transfer control
in the transmit and receive direction.
• Generates TX HEC and allows pass through of HEC
when configured for 56B cell mode on SPI-3.
• Support SPI-3 direct mode transfers.
• Optional TX Idle cell insertion.
• Support 52 byte and 56 byte cell formats transferred as
packets.
• Configurable Idle cell format for inserted TX Idle cells.
• Performs RX cell delineation.
• 25MHz to 104MHz operation supported
HDLC Processor
• Optional RX HEC checking.
• 2047 user assignable channels.
• Optional RX HEC single bit correction.
• HDLC frame structure is configurable to support POS/
PPP, HDLC, and direct map modes of operation.
• Optional payload scrambling using X43+1 polynomial.
• Optional RX Idle and/or Unassigned cell removal.
• Configurable Unassigned cell format for RX removal.
• Optional pass/discard error cells per channel in RX.
• Bit/Byte synchronization and byte alignment together
with bit/byte stuffing and destuffing.
• RFC1662 standards compliant framing.
• Optional insertion and removal of PPP address and
control bytes.
• Optional generation and deletion of 16/32 bit frame
check sequence field (FCS).
• Payload transparency processing support in both the
Empowering Intelligent Optical Networks
3
FINAL Product Brief
TIGRIS
OC-48 Multi Protocol Termination for 2047 Channels
Part Number S4811, Rev. 2.4 July 2006
• Extensive per channel statistics that include:
• Good RX cells.
• Good TX cells.
• RX loss of cell delineation events.
• RX HEC errors single bit corrected.
• RX HEC errors uncorrected.
• RX PLCP BIP errors.
• RX PLCP Remote Alarm Detected indicator.
• RX PLCP OOF indication.
• Global count of TX HEC errors received over SPI-3 in 56B
mode.
Queue Management
• On chip queue management.
• Multiple RX High/Low priority queues with programmable
service priority arbitration.
• Per channel TX High/Low priority queues with
programmable watermarks and optional discard at high
threshold.
• Full “out of band” access to on chip queue threshold
status via a 15 pin Queue Access Bus interface. Useful for
Figure 3: TIGRIS Expansion Mode used for a 2 x OC-12 solution with 4k channels
monitoring the fill level of TX and RX queues for flow
control operation.
AMCC Flexible Tributary Interface (FTI)
622MHz BW Supports any valid combination
of the following:
• Per
syn
Industry standard
SPI-3 interface
for Cells and
Industry standard
SPI-4.2 interface
for Cells and
packets transfer
packets transfer
Buffe
1xSTS12c, 4xSTS3c, 12xSTS1
• Man12DS3/E3,336DS1/VT1.5, 252E1/VT2
SDR
• On-
1xOC12
or
• Sup
4xOC3
• Con
S1212
TIGRIS
S4811
EVROS
• BuffS1208
larg
1xOC12
NP3700
or
• RX
4xOC3
frag
on t
TIGRIS
S4811
S1212
EVROS
full
S1208
HDLC/ATM controllers
4094 packet/cell channels
Supports fractional DS3
SONET to PDH framer/mapper
1xOC-12, 4XOC-3 , 12xDS3/E3
336DS1/VT1.5
252E1/VT2
4
Empowering Intelligent Optical Networks
FINAL Product Brief
TIGRIS
OC-48 Multi Protocol Termination for 2047 Channels
Part Number S4811, Rev. 2.4 July 2006
External Memory Support
Loopbacks
• Wire Level FTI loopback.
• Industry standard DDR333 SDRAM support.
• Separate 64b DRAM memory banks for Transmit and
Receive frame storage.
• DS0 loopback on FTI interfaces.
• Packet level loopbacks per channel for packets received/
transmitted on FTI, ATI, and SPI interfaces.
• Supports 256Mb, 512Mb, and 1Gb DRAM technology.
• Supports x16 discrete.
• All packet level loopbacks occur at internal queueing
points in the on chip MMU (Memory Management Unit).
Sub Rate DS3 Support
External CPU Interface
• Subrate Services supported for all 48 DS3 payloads.
• Interoperates with the following subrate DS3 protocols:
• General purpose 16-bit microprocessor interface for
device initialization, control and monitoring. The interface
supports both Intel and Motorola type microprocessors.
• Quick Eagle (formerly Digital Link)
• ADC/Kentrox
• Larscom
• Adtran
• Verilink
• Supports processor-based packet/cell injection and
retrieval to/from the line interface as well as to/from the
system interface.
• Operation up to 66 Mhz.
• Maskable interrupt support for errors and statistics
counter threshold events.
AMCC reserves the right to make changes to its products, its datasheets, or related documentation, without notice and warrants its products solely
pursuant to its terms and conditions of sale, only to substantially comply with the latest available datasheet. Please consult AMCC’s Term and Con-
ditions of Sale for its warranties and other terms, conditions and limitations. AMCC may discontinue any semiconductor product or service without
notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information is current.
AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it convey any
license under its patent rights nor the rights of others. AMCC reserves the right to ship devices of higher grade in place of those of lower grade.
AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN
LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
AMCC is a registered Trademark of Applied Micro Circuits Corporation. Copyright © 2004 Applied Micro Circuits Corporation.
215 Moffett Park Drive, Sunnyvale, CA 94089• Tel: 408-542-8600 • Fax: 408-542-8601 • http://www.amcc.com
for technical support, please call 800 840-6055 or email support@amcc.com
Empowering Intelligent Optical Networks
5
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