CS5320 [AMCC]
PCI Match Maker, 3.3V; PCI匹配制造商， 3.3V
| 型号： | CS5320 |
| 厂家： | 
APPLIED MICRO CIRCUITS CORPORATION |
| 描述： | PCI Match Maker, 3.3V |
| 文件： | 总160页 (文件大小：1544K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Part Number S5320
Revision 5.03 – June 14, 2006
Data Sheet
S5320
PCI Match Maker, 3.3V
S5320
PCI Match Maker
AMCC Confidential and Proprietary
DS1656
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Revision 5.03 – June 14, 2006
S5320 – PCI Match Maker, 3.3V
Data Sheet
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AMCC Confidential and Proprietary
Part Number S5320
Revision 5.03 – June 14, 2006
Data Sheet
S5320
PCI Match Maker
FEATURES
APPLICATIONS
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Full 132 Mbytes/sec Transfer Rate
PCI Bus Operation to 33 MHz
PCI 2.2 Compliant Target Device
3.3V Power Supply
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ISA Conversions
Multimedia
I/O Ports
Data Storage
5V Tolerant I/Os
CODEC5
Add-On Bus up to 40 MHz
General Purpose PCI Bus Interfacing
Programmable Prefetch and Wait States
8/16/32-Bit Add-On Bus
ARCHITECTURAL OVERVIEW
The AMCC S5320 was developed to provide the
designer with a single multi-function device offering a
flexible and easy way to connect to the PCI bus. By
using the S5320, the designer eliminates the task of
assuring PCI bus specification compliance and the
necessity of understanding PCI bus timing require-
ments when interfacing a new application. The S5320
was designed for 3.3V environment but its inputs/out-
puts are tolerant to 5V signaling.
Four Definable Pass-Thru Regions
Two 32-Byte Burstable FIFOs
Active/Passive Add-On Bus Operation
Mailbox Registers/w Byte Level Status
Direct Mailbox Data Strobe/Int Pin
Mailbox Read/Write Interrupts
Direct PCI and Add-On Interrupt Pins
Plug-N-Play Compatible
The complex 33 MHz PCI bus signals are converted
through the S5320 into an easy-to-use 8/16/32-bit
user bus referred to as the user Add-On bus. The Add-
On bus allows user add-on designs bus clock speed
independent operation to 40 MHz.
Two-wire Serial Bus nvRAM Support
Optional External BIOS capability
176-Pin Low Profile LQFP
Environmental Friendly Lead-free Package
Option
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S5320 – PCI Match Maker
Data Sheet
Figure 1. S5320 Block Diagram
User
Application
S5320
ISA
Card
PCI
Configuration
Registers
Design
ADD-ON
32
Pass-
Thru
Byte
FIFO
ISDN
FDDI
ATM
2.1PCI
Local Bus
Interface
Logic
AMCC
ADD-ON
Local Bus
Interface
Logic
32
By te
FIFO
PCI
Pass-
Thru
Graphics/
MPEG/
Grabber
Mux/
Demux
Mux/
Demux
Activ e
R/WLogic
Buf f ers
Pass-Thru
Address Register
Audio
Design
Data
Buf fer
Mailboxes/Status
s
Serial
Read/Write
Control
Serial
Read/Write
Control
Operation/
StatusRegisters
I/O
Controller
Conf igurationSpace
ExpansionBIOS
SerialNVRAM
SerialBus
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Revision 5.03 – June 14, 2006
S5320 – PCI Match Maker
Data Sheet
TABLE OF CONTENTS
FEATURES .............................................................................................................................................................. 3
APPLICATIONS ...................................................................................................................................................... 3
ARCHITECTURAL OVERVIEW .............................................................................................................................. 3
ARCHITECTURAL OVERVIEW S5320 ................................................................................................................. 15
S5320 REGISTER ARCHITECTURE .................................................................................................................... 15
PCI Configuration Registers ............................................................................................................................ 15
PCI Bus Accessible Registers ......................................................................................................................... 15
Add-On Bus Accessible Registers ................................................................................................................... 15
SERIAL NON-VOLATILE INTERFACE ................................................................................................................ 15
MAILBOX OPERATION ........................................................................................................................................ 17
PASS-THRU OPERATION .................................................................................................................................... 17
PCI BUS SIGNALS ............................................................................................................................................... 21
ADD-ON BUS AND S5320 CONTROL SIGNALS ................................................................................................ 23
USER ADD-ON BUS PIN DESCRIPTIONS .......................................................................................................... 24
PCI CONFIGURATIONS REGISTERS .................................................................................................................. 29
Vendor Identification Register (VID) ................................................................................................................ 29
Device Identification Register (DID) ................................................................................................................ 30
PCI Command Register (PCICMD) ................................................................................................................. 31
PCI Status Register (PCISTS) ......................................................................................................................... 33
Revision Identification Register (RID) .............................................................................................................. 35
Class Code Register (CLCD) .......................................................................................................................... 36
Cache Line Size Register (CALN) ................................................................................................................... 41
Latency Timer Register (LAT) ......................................................................................................................... 42
Header Type Register (HDR) .......................................................................................................................... 43
Built-In Self-Test Register (BIST) .................................................................................................................... 44
Base Address Register (BADR) ...................................................................................................................... 45
Determining Base Address Size ...................................................................................................................... 45
Assigning the Base Address ............................................................................................................................ 45
Subsystem Vendor Identification Register (SVID) ........................................................................................... 50
Subsystem ID Register (SID) .......................................................................................................................... 51
Expansion ROM Base Address Register (XROM) .......................................................................................... 52
Interrupt Line Register (INTLN) ....................................................................................................................... 54
Interrupt Pin Register (INTPIN) ...................................................................................................................... 55
Minimum Grant Register (MINGNT) ................................................................................................................ 56
Maximum Latency Register (MAXLAT) ........................................................................................................... 57
OPERATION REGISTERS .................................................................................................................................... 59
PCI BUS OPERATION REGISTERS .................................................................................................................... 59
PCI Outgoing Mailbox Register (OMB) ............................................................................................................ 60
PCI Incoming Mailbox Register (IMB) ............................................................................................................. 61
PCI Mailbox Empty/full Status Register (MBEF) ............................................................................................. 62
PCI Interrupt Control/Status Register (INTCSR) ............................................................................................. 63
PCI Reset Control Register (RCR) .................................................................................................................. 65
PCI Pass-Thru Configuration Register (PTCR) ............................................................................................... 67
ADD-ON BUS OPERATION REGISTERS ............................................................................................................ 69
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Data Sheet
TABLE OF CONTENTS
Add-On Incoming Mailbox Register (AIMB) ..................................................................................................... 70
Add-On Outgoing Mailbox Register (AOMB) ................................................................................................... 70
Add-On Pass-Thru Address Register (APTA) ................................................................................................. 70
Add-On Pass-Thru Data Register (APTD) ....................................................................................................... 70
Add-On Mailbox Empty/full Status Register (AMBEF) ..................................................................................... 71
Add-On Interrupt Control/status Register (AINT) ............................................................................................. 73
Add-On Reset Control Register (ARCR) ......................................................................................................... 75
Add-On Pass-thru Configuration Register (APTCR) ....................................................................................... 77
INITIALIZATION .................................................................................................................................................... 79
PCI RESET ............................................................................................................................................................ 79
LOADING THE SERIAL NV MEMORY ................................................................................................................. 79
NON-VOLATILE MEMORY INTERFACE ............................................................................................................. 83
NVRAM READ/WRITE DESCRIPTION ................................................................................................................. 83
PCI BUS CONFIGURATION CYCLES .................................................................................................................. 86
EXPANSION BIOS ROMS .................................................................................................................................... 87
PCI BUS INTERFACE ........................................................................................................................................... 91
PCI BUS TRANSACTIONS ................................................................................................................................... 91
PCI BURST TRANSFERS ..................................................................................................................................... 92
PCI READ TRANSFERS ....................................................................................................................................... 93
PCI WRITE TRANSFERS ..................................................................................................................................... 93
Target-Initiated Termination ............................................................................................................................ 94
Target Disconnects .......................................................................................................................................... 94
Target Requested Retries ............................................................................................................................... 94
Target Aborts ................................................................................................................................................... 95
Target Latency ................................................................................................................................................. 95
Target Locking ................................................................................................................................................. 95
PCI Bus Access Latency Components ............................................................................................................ 95
PCI BUS INTERRUPTS ........................................................................................................................................ 97
PCI BUS PARITY ERRORS .................................................................................................................................. 97
MAILBOX OVERVIEW ........................................................................................................................................ 100
FUNCTIONAL DESCRIPTION ............................................................................................................................ 100
Mailbox Empty/Full Conditions ...................................................................................................................... 101
Mailbox Interrupts .......................................................................................................................................... 101
Add-On Outgoing Mailbox, Byte 3 Access .................................................................................................... 102
BUS INTERFACE ................................................................................................................................................ 102
PCI Bus Interface .......................................................................................................................................... 102
Add-On Bus Interface .................................................................................................................................... 102
8-Bit and 16-Bit Add-On Interfaces ................................................................................................................ 103
CONFIGURATION ............................................................................................................................................... 103
Mailbox Status ............................................................................................................................................... 103
Writing the PCI Outgoing Mailbox: ................................................................................................................ 104
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S5320 – PCI Match Maker
Data Sheet
TABLE OF CONTENTS
Reading an Add-On Incoming Mailbox: ......................................................................................................... 104
Writing an Add-On Outgoing Mailbox: ........................................................................................................... 104
Mailbox Interrupts .......................................................................................................................................... 105
Servicing a PCI Mailbox Interrupt (INTA# Asserted): .................................................................................... 106
Servicing the Add-On mailbox interrupt (IRQ# Asserted): ............................................................................. 106
ADD-ON LOCAL BUS INTERFACE ................................................................................................................... 108
ADD-ON INTERFACE SIGNALS ........................................................................................................................ 108
SYSTEM SIGNALS ............................................................................................................................................. 108
ADD-ON S5320 REGISTER ACCESSES ........................................................................................................... 108
Register Access Signals ................................................................................................................................ 108
S5320 General Register Accesses ................................................................................................................ 108
S5320 16-bit Mode Register Accesses ......................................................................................................... 109
MAILBOX OVERVIEW ........................................................................................................................................ 111
PASS-THRU OVERVIEW .................................................................................................................................... 111
WRITE FIFO OVERVIEW .................................................................................................................................... 111
READ FIFO OVERVIEW ..................................................................................................................................... 111
FUNCTIONAL DESCRIPTION ............................................................................................................................ 111
Pass-Thru Transfers ...................................................................................................................................... 111
Pass-Thru Status/Control Signals ................................................................................................................. 112
BUS INTERFACE ................................................................................................................................................ 112
PCI Bus Interface .......................................................................................................................................... 112
PCI Pass-Thru Single Cycle Accesses .......................................................................................................... 113
PCI Pass-Thru Burst Accesses ..................................................................................................................... 113
PCI Disconnect Conditions ............................................................................................................................ 113
PCI Write Disconnect .................................................................................................................................... 114
PCI Read Disconnect .................................................................................................................................... 114
S5320 PASSIVE MODE OPERATION ................................................................................................................ 115
Single-Cycle PCI to Pass-Thru Write ............................................................................................................ 115
Single-Cycle PCI to Pass-Thru Read ............................................................................................................ 116
PCI to Pass-Thru Burst Writes ...................................................................................................................... 117
Pass-Thru Burst Reads ................................................................................................................................. 122
Using PTRDY# to assert Wait-States ............................................................................................................ 123
8-Bit and 16-Bit Pass-Thru Add-On Bus Interface in Passive Mode ............................................................. 124
Endian Conversion ........................................................................................................................................ 128
Active Operation ............................................................................................................................................ 128
Active mode Programmable Wait States ....................................................................................................... 131
PTRDY#/PTWAIT# ........................................................................................................................................ 131
DXFR# ........................................................................................................................................................... 132
Active Mode Figures and Descriptions .......................................................................................................... 132
Active mode Burst cycles .............................................................................................................................. 132
Clock by Clock description of Figure 75 ........................................................................................................ 133
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Data Sheet
TABLE OF CONTENTS
Clock by Clock description of Figure 76 ........................................................................................................ 134
Active Mode with 16/8-bit data buses ............................................................................................................ 136
CONFIGURATION ............................................................................................................................................... 137
S5320 Base Address Register Definition ...................................................................................................... 138
Creating a Pass-Thru Region ........................................................................................................................ 138
Accessing a Pass-Thru Region ..................................................................................................................... 139
Special Programming Features ..................................................................................................................... 139
ABSOLUTE MAXIMUM STRESS RATINGS ...................................................................................................... 141
RECOMMENDED OPERATING CONDITIONS .................................................................................................. 141
PCI Signal DC Characteristics ....................................................................................................................... 142
Add-On Signal DC Characteristics ................................................................................................................ 143
nvRAM Memory Interface Signals ................................................................................................................. 143
TIMING SPECIFICATION .................................................................................................................................... 144
PCI Clock Specification ................................................................................................................................. 144
Add-On Signal Timings .................................................................................................................................. 146
PACKAGE INFORMATION ................................................................................................................................. 153
S5320 Pin Assignment - 176 LQFP ............................................................................................................... 155
DOCUMENT REVISION HISTORY ..................................................................................................................... 158
ORDERING INFORM ATION .............................................................................................................................. 159
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S5320 – PCI Match Maker
Data Sheet
LIST OF FIGURES
Figure 1. S5320 Block Diagram ............................................................................................................................... 4
Figure 2. S5320 Pinout .......................................................................................................................................... 16
Figure 3. Mailbox Block Diagram ........................................................................................................................... 17
Figure 4. Pass-Thru Block Diagram ....................................................................................................................... 18
Figure 5. S5320 Signal Assignment ....................................................................................................................... 20
Figure 6. Vendor Identification Register ................................................................................................................. 29
Figure 7. Device Identification Register ................................................................................................................. 30
Figure 8. PCI Command Register .......................................................................................................................... 31
Figure 9. PCI Status Register ................................................................................................................................ 33
Figure 10. Revision Identification Register ............................................................................................................ 35
Figure 11. Class Code Register ............................................................................................................................. 36
Figure 12. Cache Line Size Register ..................................................................................................................... 41
Figure 13. Latency Timer Register ......................................................................................................................... 42
Figure 14. Header Type Register ........................................................................................................................... 43
Figure 15. Built-In Self-Test Register ..................................................................................................................... 44
Figure 16. Base Address Register - Memory ......................................................................................................... 46
Figure 17. Base Address Register - I/O ................................................................................................................. 47
Figure 18. Subsystem Vendor Identification Register ............................................................................................ 50
Figure 19. Subsystem Identification Register ........................................................................................................ 51
Figure 20. Expansion ROM Base Address Register .............................................................................................. 52
Figure 21. Interrupt Line Register .......................................................................................................................... 54
Figure 22. Interrupt Pin Register ............................................................................................................................ 55
Figure 23. Minimum Grant Register ....................................................................................................................... 56
Figure 24. Maximum Latency Register .................................................................................................................. 57
Figure 25. Outgoing Mailbox .................................................................................................................................. 60
Figure 26. Incoming Mailbox .................................................................................................................................. 61
Figure 27. Mailbox Empty/Full Status Register (MBEF) ......................................................................................... 62
Figure 28. Interrupt Control Status Register .......................................................................................................... 63
Figure 29. FIFO Control/Status Register ............................................................................................................... 65
Figure 30. Pass-Thru Configuration Register ........................................................................................................ 67
Figure 31. Mailbox Empty/Full Status Register ...................................................................................................... 71
Figure 32. Add-On Interrupt Control Status Register ............................................................................................. 73
Figure 33. Add-On General Control/Status Register ............................................................................................. 75
Figure 34. Pass-Thru Configuration Register ........................................................................................................ 77
Figure 35. S5320 to nvRAM Interface .................................................................................................................... 81
Figure 36. Serial Interface Definition of Start and Stop .......................................................................................... 81
Figure 37. Serial Interface Clock Data Relationship .............................................................................................. 81
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Data Sheet
LIST OF FIGURES
Figure 38. Serial Interface Byte Access-Write ....................................................................................................... 82
Figure 39. Serial Interface Byte Access-Read ....................................................................................................... 82
Figure 40. Serial Byte Access- Sequential Read ................................................................................................... 82
Figure 41. PCI AD Bus Definition Type 0 Configuration Access ............................................................................ 86
Figure 42. Type 0 Configuration Read Cycles ....................................................................................................... 86
Figure 43. Type 0 Configuration Write Cycles ....................................................................................................... 87
Figure 44. Single Data Phase PCI Bus Read of S5320 Registers or Expansion ROM ......................................... 93
Figure 45. Burst PCI Bus Read Attempt to S5320 Registers or Expansion ROM ................................................. 94
Figure 46. Burst PCI Bus Write of S5320 Registers .............................................................................................. 94
Figure 47. Target Disconnect Example 1 ............................................................................................................... 94
Figure 48. Target Disconnect Example 2 ............................................................................................................... 95
Figure 49. Target-Initiated Retry ............................................................................................................................ 95
Figure 50. Engaging the LOCK# Signal ................................................................................................................. 96
Figure 51. Access to a Locked Target by its Owner .............................................................................................. 98
Figure 52. Access Attempt to a Locked Target ...................................................................................................... 98
Figure 53. Error Reporting Signal .......................................................................................................................... 98
Figure 54. PCI to Add-On Mailbox Register ......................................................................................................... 100
Figure 55. Add-On to PCI Mailbox Register ......................................................................................................... 101
Figure 56. Input/Output Mode (MDMODE=0) ...................................................................................................... 103
Figure 57. Input Mode (MDMODE=1) .................................................................................................................. 103
Figure 58. Read Operation Register .................................................................................................................... 109
Figure 59. Write Operation Register .................................................................................................................... 109
Figure 60. 16 Bit Mode Operation Register DWORD Write/Read ........................................................................ 110
Figure 61. PCI To Add-On Passive Write ............................................................................................................ 116
Figure 62. PCI To Add-On Passive Write w/Pass-Thru Address ......................................................................... 116
Figure 63. PCI To Add-On Passive Read ............................................................................................................ 117
Figure 64. PCI to Add-On Passive Burst Write .................................................................................................... 118
Figure 65. PCI to Add-On Passive Burst Write Using PTRDY# to assert Wait-States ........................................ 120
Figure 66. PCI to Add-On Passive Burst Read Access ....................................................................................... 120
Figure 67. PCI to Add-On Passive Burst Read .................................................................................................... 122
Figure 68. PCI to Add-On Passive Write to an 8-bit ............................................................................................ 127
Figure 69. PCI to Add-On Passive Read to an 16-bit Add-On Device ................................................................. 129
Figure 70. Active mode PCI Read (Zero Programmed Wait States) with PTADR# ............................................. 130
Figure 71. Active Mode PCI Read without PTADR# ............................................................................................ 130
Figure 72. Active Mode PCI Write without PTADR# ............................................................................................ 130
Figure 73. Active Mode PCI Write with Add-On Initiated Wait States Using PTWAIT# ....................................... 131
Figure 74. Active Mode 32-Bit PCI Write ............................................................................................................. 131
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S5320 – PCI Match Maker
Data Sheet
LIST OF FIGURES
Figure 75. Active Mode 32-Bit PCI Write w/PTWAIT# ......................................................................................... 133
Figure 76. Active Mode PCI Write Showing a One Wait State Programmed Delay ............................................. 134
Figure 77. 16-Bit Active Mode PCI Read w/ Programmed Wait States ............................................................... 135
Figure 78. Active Mode PCI Read w/ Programmed Wait States .......................................................................... 136
Figure 79. Active Mode PCI Read ....................................................................................................................... 137
Figure 80. Active Mode PCI Write ........................................................................................................................ 137
Figure 81. 8-Bit Active Mode PCI Write ............................................................................................................... 138
Figure 82. PCI Clock Timing ................................................................................................................................ 144
Figure 83. PCI Signal Output Timing ................................................................................................................... 145
Figure 84. PCI Signal Input Timing ...................................................................................................................... 145
Figure 85. Add-On Clock Timing .......................................................................................................................... 148
Figure 86. Pass-Thru Clock Relationship to PCI Clock ........................................................................................ 148
Figure 87. PTADR Timing .................................................................................................................................... 148
Figure 88. Passive Mode Pass-Thru Operation ................................................................................................... 149
Figure 89. Active Mode Pass-Thru Write Operation ............................................................................................ 151
Figure 90. Mailbox Data (Setup/Hold timing) ....................................................................................................... 152
Figure 91. Mailbox Data (Float/Active timing) ...................................................................................................... 152
Figure 92. S5320 Pinout and Pin Assignment ..................................................................................................... 153
Figure 93. 176 Pin Low Profile Quad Flat Pack (LQFP), 24 mm x 24 mm ........................................................... 154
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Data Sheet
LIST OF FIGURES
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S5320 – PCI Match Maker
Data Sheet
LIST OF TABLES
Table 1. PCI Bus Address and Data Signal ........................................................................................................... 21
Table 2. PCI Bus System Signals .......................................................................................................................... 22
Table 3. PCI Bus Data Transfer Control Signals ................................................................................................... 22
Table 4. PCI Bus Error Reporting Signals ............................................................................................................. 22
Table 5. Serial nvRAM Interface Signals ............................................................................................................... 23
Table 6. Direct Mailbox Access Signals ................................................................................................................. 23
Table 7. Pass-Thru Data Channel Pins ................................................................................................................. 24
Table 8. S5320 Add-On Bus Register Access Pins ............................................................................................... 25
Table 9. Add-On Bus General Pins ........................................................................................................................ 26
Table 10. Configuration Registers ......................................................................................................................... 27
Table 11. Defined Base Class Codes .................................................................................................................... 37
Table 12. Base Class Code 00h: Early, Pre-2.0 Specification Devices ................................................................. 37
Table 13. Base Class Code 01h: Mass Storage Controllers .................................................................................. 37
Table 14. Base Class Code 02h: Network Controllers ........................................................................................... 37
Table 15. Base Class Code 03h: Display Controllers ............................................................................................ 38
Table 16. Base Class Code 04h: Multimedia Devices ........................................................................................... 38
Table 17. Base Class Code 05h: Memory Controllers ........................................................................................... 38
Table 18. Base Class Code 06h: Bridge Devices .................................................................................................. 39
Table 19. Base Class Code 07h: Simple Communications Controllers ................................................................. 39
Table 20. Base Class Code 08h: Base System Peripherals .................................................................................. 39
Table 21. Base Class Code 09h: Input Devices .................................................................................................... 40
Table 22. Base Class Code 0Ah: Docking Stations ............................................................................................... 40
Table 23. Base Class Code 0Bh: Processors ........................................................................................................ 40
Table 24. Base Class Code 0Ch: Serial Bus Controllers ....................................................................................... 40
Table 25. Base Address Register Response (Memory Assigned) to All-Ones Write Operation ............................ 48
Table 26. Read Response (I/O Assigned) to an All-Ones Write Operation to a Base Address Register ............... 49
Table 27. Read Response to Expansion ROM Base Address Register (after all ones written) ............................. 53
Table 28. Operation Registers - PCI Bus ............................................................................................................... 59
Table 29. Mailbox Empty/Full Status Register ....................................................................................................... 62
Table 30. Interrupt Control Status Register ........................................................................................................... 64
Table 31. Reset Control Register ........................................................................................................................... 66
Table 32. Pass-Thru Configuration Register .......................................................................................................... 68
Table 33. Operation Registers - Add-On Interface ................................................................................................ 69
Table 34. Mailbox Empty/Full Status Register ....................................................................................................... 72
Table 35. Interrupt Control Status Register ........................................................................................................... 74
Table 36. Reset General Control/Status Register .................................................................................................. 76
Table 37. Pass-thru Configuration Register ........................................................................................................... 78
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Data Sheet
LIST OF TABLES
Table 38. Valid External Boot Memory Contents ................................................................................................... 80
Table 39. PC Compatible Expansion ROM ............................................................................................................ 87
Table 40. PCI Data Structure ................................................................................................................................. 89
Table 41. PCI Bus Commands .............................................................................................................................. 92
Table 42. Target Termination Type ........................................................................................................................ 96
Table 43. Byte Lane Steering for PCI Write (Add-On Read) ................................................................................ 125
Table 44. Byte Lane Steering for PCI Read (Add-On Write) ................................................................................ 125
Table 45. Showing Big Endian Conversion for 32-bit .......................................................................................... 129
Table 46. Big Endian conversion for a 16-bit bus. The S5320 drives D[15:0] only .............................................. 129
Table 47. Big Endian conversion for an 8-bit bus. The S5320 drives D[7:0] only ................................................ 129
Table 48. Absolute Maximum Stress Ratings ...................................................................................................... 141
Table 49. Recommended Operating Conditions .................................................................................................. 141
Table 50. PCI Signal DC Characteristics (V = 3.3V ± 5%, 0°C to 70°C, 50 pF load on outputs) ..................... 142
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Table 51. Add-On Operating Characteristics (V = 3.3V ± 5%, 0°C to 70°C, 50 pF load on outputs) ............... 143
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Table 52. Functional Operation Range
(V = 3.3V ± 5%, 0°C to 70°C, 50 pF load on outputs for MAX, 0 pF load for MIN) ................................... 144
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Table 53. Add-On Timings, Functional Operation Range
(V = 3.3V ± 5%, 0°C to 70°C, 50 pF load on outputs for MAX, 0 pF load for MIN) ................................... 146
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Table 54. Add-On Timings
Functional Operation Range (V = 3.3V ± 5%, 0°C to 70°C, 50 pF load on outputs for MAX,
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0 pF load for MIN) .......................................................................................................................................... 150
Table 55. Mailbox Timings
Functional Operation Range (V = 3.3V ± 5%, 0°C to 70°C, 50 pF load on outputs) ................................. 152
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S5320 – PCI Match Maker: Architectural Overview
Data Sheet
and Add-On Operation Registers. All of these registers
are user configurable through their associated buses
and from the external nvRAM. The following sections
provide a brief overview of each register group and the
nvRAM interface.
ARCHITECTURAL OVERVIEW S5320
Since the S5320 is a PCI Target or Slave device only,
its cost is significantly less than PCI Bus Master solu-
tions. The S5320 is PCI purposed 2.2 compliant and
can support data transfer rates up to 132 Mbytes/sec.
Burst transfers and single data transfers are both sup-
ported. Figure 1 shows the block diagram for the
S5320.
PCI Configuration Registers
All PCI compliant devices are required to provide a
group of PCI configuration registers. These registers
are polled by the host BIOS system during power-up
initialization. They contain specific device and product
information such as Vendor ID, Device ID, Subsystem
Vendor ID, memory requirements, etc. These registers
are located in the S5320 and are either initialized with
predefined default values or user customized defini-
tions contained in the external nvRAM.
Many additional S5320 features offer the user easier
hardware and software implementation. Up to four
memory or I/O size definable blocks, referred to as
Pass-Thru regions, are provided for multiple device
configurations. Data transfers via a Pass-Thru region
can be performed either direct to the Add-On bus or
through two 32-Byte burstable FIFOs. Added read
prefetch and programmable FIFO wait state features
allow the user to tune system performance. The Pass-
Thru data channel also supports an active/passive
mode bus interface. Passive mode requires the
designer to transfer data by externally driving the Add-
On bus. Active mode minimizes design components
by enabling internal logic to drive or acquire the Add-
On bus to read or write data independently. Active
mode provides programmable wait state generation
for slower Add-On designs.
PCI Bus Accessible Registers
The second group of registers are the PCI Operation
Registers. This group of registers is accessible to the
PCI Bus. These are the primary registers through
which the PCI Host configures the S5320 operation
and communicates with the Add-On Bus. These regis-
ters encompass the PCI bus mailboxes, Pass-Thru/
FIFO data channel and Status/ Control registers.
Add-On Bus Accessible Registers
Two 32-bit mailbox registers are implemented for addi-
tional data or user-defined status/command transfers.
Each mailbox may be examined for empty or full, at
the byte level, through a mailbox status register. Mail-
box transfers can be either register style or hardware
direct. Dedicated external mailbox data and strobe
pins are provided for direct hardware read/writes and
allow Add-On to PCI interrupt capabilities. A direct
Add-On to a PCI bus interrupt pin is incorporated, add-
ing design flexibility.
The last register group consists of the Add-On Opera-
tion Registers. This group of registers is accessible via
the Add-On Bus. These are the primary registers
through which the Add-On application configures
S5320 operation and communicates with the PCI Bus.
These registers encompass the Add-On bus mail-
boxes, Pass-Thru/FIFO Registers and Status/Control
Registers.
SERIAL NON-VOLATILE INTERFACE
The S5320 supports a two-wire serial nvRAM. This
allows the designer to customize the device configura-
tion to be loaded during power-up initialization. An
expansion BIOS may also be contained in the nvRAM.
Previously indicated, the S5320 contains the required
set of PCI Configuration Registers. These registers
can be initialized with default values or with custom-
ized values contained in an external nvRAM. The
nvRAM allows Add-On card manufacturers to initialize
the S5320 with their specific Vendor ID values, along
with other desired S5320 operation characteristics.
S5320 REGISTER ARCHITECTURE
S5320 communications, control and configuration is
performed through three primary groups of registers:
PCI Configuration Registers, PCI Operation Registers
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S5320 – PCI Match Maker: Architectural Overview
Data Sheet
Figure 2. S5320 Pinout
S5320
PCLK
BPCLK
ADCLK
SYSRST#
IRQ#
INTA#
RST#
Add-OnBus
Timing/Interrupts
AD[31:0]
ADDINT#
DQ[31:0]
C/BE[3:0]#
Add-OnDataBus
SELECT#
ADR[6:1]
S5320Data
AccessControl
FRAME#
DEVSEL#
BE[3:0]#
RD#
WR#
IRDY#
TRDY#
IDSEL#
PTATN#
PTBURST#
PTNUM[1:0]
PTBE[3:0]#
STOP#
LOCK#
Pass-Thru
Control/
Access
PTADR#
PTWR
PAR
PTRDY#/WAIT#
PERR#
SERR#
DXFER#
PTMODE
DQMODE
Add-OnBus
Control
S5320
Control
FLT#
MD[7:0]
LOAD#
Mai l Box
Access/Control
MDMODE
SDA
SCL
SerialBus
Config/BIOSOpt.
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S5320 – PCI Match Maker: Architectural Overview
Data Sheet
MAILBOX OPERATION
PASS-THRU OPERATION
The mailbox registers are divided into two 4-byte sets.
Each set is dedicated to one bus for data transfer to
the other bus. Figure 3 shows a block diagram of the
mailbox section of the S5320. The provision of mailbox
registers provides data or user defined command/sta-
tus transfer capability between two buses. An empty/
full indication for each mailbox register, at the byte
level, is determined by polling a status register acces-
sible to both the PCI and Add-On buses. Providing
mailbox byte level full indications allows greater flexi-
bility in 8-, 16-or 32-bit designs; i.e., transferring a
single byte in 8-bit Add-On bus without requiring the
assembly or disassembly of 32-bit data.
Pass-Thru region accesses can execute PCI bus
cycles in real time or through an internal FIFO. Real
time operation allows the PCI bus to directly read or
write to Add-On bus resources. The S5320 allows the
designer to declare up to four individual Pass-Thru
regions. Each region may be defined as 8, 16 or 32
bits wide, mapped into memory or I/O system space
and may be up to 512 MB in size. Figure 4 shows a
basic block diagram of the S5320 Pass-Thru
architecture.
Host communications to the Pass-Thru data channel
utilizes dedicated Add-On bus pins to signal that a PCI
read or write has been requested. User logic decodes
these signals to determine if it must read or write data
to the S5320 to satisfy the PCI request. Information
decoded includes: PCI read/write transaction request,
the byte lanes involved, the specific Pass-Thru region
accessed and whether the request is a burst or single
cycle access.
A mailbox byte level interrupt feature for PCI or Add-
On buses is provided. Bit locations configured within
the S5320 operation registers can select which mail-
box byte is to generate an interrupt when the mailbox
is written to. Interrupts can be generated to the PCI or
Add-On buses. PCI bus interrupts may also be gener-
ated from direct hardware interfacing due to a unique
S5320 feature. The Add-On mailbox is hardware
accessible via a set of dedicated device pins. A single
load pulse latches data into the mailbox generating an
interrupt, if enabled.
Pass-Thru operation supports single PCI data cycles
and PCI data bursts. During PCI burst operations, the
S5320 is capable of transferring data at the full PCI
bandwidth. Should slower Add-On logic be imple-
mented, the S5320 will issue a PCI bus retry until the
requested transfer is completed.
Figure 3. Mailbox Block Diagram
8
8
8
8
Mailbox Mailbox Mailbox Mailbox
Byte0 Byte1 Byte2 Byte3
32
PCI
Decode
Control
Add-On
Decode
Control
32
MailboxStatus
Register
Mailbox Mailbox Mailbox Mailbox
Byte0
Byte1
Byte2
Byte3
8
8
8
8
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S5320 – PCI Match Maker: Architectural Overview
Data Sheet
To increase data throughput, the Pass-Thru channel
incorporates two 32-byte FIFOs. One FIFO is dedi-
cated to PCI read data while the other is dedicated to
PCI write data. Enabling the write FIFO allows the
S5320 to accept zero wait state bursts from the PCI
bus regardless of the Add-On bus application design
speed. Figure 4 illustrates the Pass-Thru block.
states since data has been prefetched into the FIFO.
Either of the write/read FIFOs can be disabled or
enabled to tune system performance.
The Add-On bus can be operated in two different
modes: active or passive. The passive mode of opera-
tion mimics that of the S5335 Add-On bus operation.
The user design drives S5320 pins to read or write
data. In active mode, the Add-On bus is driven from an
S5320 internal state machine. This reduces compo-
nent count in cost-sensitive designs. Active mode also
incorporates programmable wait states from 0 to 7.
Enabling the read FIFO allows data to be optionally
prefetched from the Add-On Bus. This can greatly
improve performance of slow Add-On bus designs.
PCI read cycles can be performed with zero wait
Figure 4. Pass-Thru Block Diagram
32
Endian
Conv.
32-Byte
FIFO
Pass-Thru Register
32
PCI
Decode
Control
Add-On
Decode
Control
Status/CTRL Register
32
32
32-Byte
FIFO
Endian
Conv.
Pass-Thru Register
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S5320 – PCI Match Maker: Signal Description
Data Sheet
Signal Type Definitions
The following signal types are taken from the PCI Bus Specification.
in
Input is a standard input-only signal.
out
t/s
Totem Pole Output is a standard active driver.
Tri-State ®is a bi-directional, tri-state input/output pin.
s/t/s
Sustained Tri-State is an active low tri-state signal owned and driven by one and only one agent at a time. The
agent that drives an s/t/s pin low must drive it high for at least one clock before letting it float. A new agent cannot
start driving an s/t/s signal any sooner than one clock after the previous owner tri-states it. A pull-up is required to
sustain the inactive state until another agent drives it, and must be provided by the central source.
o/d
Open Drain allows multiple devices to share as a wire-OR.
Each signal that assumes the logic low state when asserted is followed by the pound sign (#). Example: TRDY# signal is
asserted low when the target is ready to complete a data transfer. Signals that are not followed by the pound sign are
asserted when they assume the logic high state.
The following designations are used throughout this book when referring to the size of data objects:
A BYTE is an 8-bit object.
A WORD is a 16-bit, or 2-byte object.
A DWORD is a double word and is a 32-bit or 4-byte object.
All hex numbers are followed by an “h”. Examples:
9A4Fh
0110h
All binary numbers are followed by an “b”. Examples:
1010b
0110b
All decimal numbers are followed by an “d”. Examples:
4356d
1101d
Note: Tri-State® is a Registered Trademark of National Semiconductor.
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S5320 – PCI Match Maker: Signal Description
Data Sheet
Figure 5. S5320 Signal Assignment
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
Data
Bus
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
DQ29
DQ30
DQ31
BPCLK
ADCLK
IRQ#
Bus
CLK
ADDINT#
SYSRST#
DXFR#
Controls
RST#
INTA#
C/BE0#
C/BE1#
C/BE2#
C/BE3#
ADR2
ADR3
ADR4
ADR5
ADR6
FRAME#
DEVSEL#
IRDY#
BE0#
BE1#
Register Access
Controls
BE#2
TRDY#
BE3#/ADR1
IDSEL
SELECT#
WR#
STOP#
LOCK#
RD#
PTNUM0
PTNUM1
PAR
PERR#
SERR#
PTBE0#
PTBE1#
PTBE2#
PTBE3#
DQMODE
FLT#
PTATN#
PTBURST#
PTADR#
RSVD3
Pass-Thru Data
Controls
S5320
Controls
RSVD4
RSVD2
PTWR
RSVD5
RSVD1
PTRDY#/WAIT#
PTMODE
MD0
MD1
GND
GND
GND
GND
GND
GND
MD2
MD3
MD4
Mail Box
Bus
MD5
MD6
GND
GND
GND
GND
GND
GND
GND
GND
MD7
LOAD#
MDMODE
SDA
SCL
NVRAM
Bus
VCC
VCC
Ground
GND
GND
GND
VCC
VCC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Power
VCC
VCC
VCC
VCC
VCC
VCC
VCC
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S5320 – PCI Match Maker: Signal Description
PCI BUS SIGNALS
Data Sheet
The following sets of signals represent the interface pins available for the S5320 to PCI bus.
Table 1. PCI Bus Address and Data Signal
Signal
Type
Description
AD[31:0]
t/s
Address/Data. Address and data are multiplexed on the same PCI bus pins. A PCI bus transaction
consists of an address phase followed by one or more data phases. An address phase occurs on the
PCLK cycle in which FRAME# is asserted. A data phase occurs on the PCLK cycles in which IRDY#
and TRDY# are both asserted.
C/BE[3:0]#
in
Command/Byte Enable. Bus commands and byte enables are multiplexed on the same pins. These
pins define the current bus command during an address phase. During a data phase, these pins are
used as Byte Enables, with C/BE[0]# enabling byte 0 (LSB) and C/BE[3]# enabling byte 3 (MSB).
C/BE[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
Command Type
Interrupt Acknowledge
Special Cycle
I/O Read
I/O Write
Reserved
Reserved
Memory Read
Memory Write
1000
1001
1010
1011
1100
1101
1110
Reserved
Reserved
Configuration Read
Configuration Write
Memory Read Multiple
Dual Address Cycle
Memory Read Line
Memory Write and Invalidate
1111
PAR
t/s
Parity. Parity is always driven as even from all AD[31:0] and C/BE[3:0]# signals. The parity is valid dur-
ing the clock following the address phase and is driven by the bus master. During a data phase for
write transactions, the bus master sources this signal on the clock following IRDY# active; during a
data phase for read transactions, this signal is driven by the target and is valid on the clock following
TRDY# active. The PAR signal has the same timing as AD[31:0], delayed by one clock.
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S5320 – PCI Match Maker: Signal Description
Data Sheet
Table 2. PCI Bus System Signals
Signal Type
Description
PCLK
in
PCI Clock. The rising edge of this signal is the reference upon which all other signals are based except for
RST# and INTA#. The maximum PCLK frequency for the S5320 is 33 MHz and the minimum is DC (0 Hz).
RST#
in
Reset brings the S5320 to a known state:
- All PCI bus output signals tri-stated.
- All open drain signals (i.e., SERR#) floated.
- All registers set to their factory defaults.
- Pass-Thru is returned to an idle state.
- All FIFOs emptied.
Table 3. PCI Bus Data Transfer Control Signals
Signal
Type
Description
FRAME#
in
Frame. This signal is driven by the current bus master to indicate the beginning and duration of a bus
transaction. When FRAME# is first asserted, it indicates a bus transaction is beginning with a valid
addresses and bus command present on AD[31:0] and C/BE[3:0]. Data transfers continue while
FRAME# is asserted. FRAME# de-assertion indicates the transaction is in a final data phase or has
completed.
IRDY#
in
Initiator Ready. This signal is always driven by the bus master to indicate its ability to complete the cur-
rent data phase. During write transactions, it indicates AD[31:0] contains valid data.
TRDY#
s/t/s
Target Ready. This signal is driven by the selected target to indicate the target is able to complete the
current data phase. During read transactions, it indicates AD[31:0] contains valid data. Wait states
occur until both TRDY# and IRDY# are asserted together.
STOP#
LOCK#
IDSEL
s/t/s
in
Stop. The Stop signal is driven by a selected target and conveys a request to the bus master to stop the
current transaction.
Lock. The lock signal provides for the exclusive use of a resource. The S5320 may be locked by one
master at a time.
in
Initialization Device Select. This pin is used as a chip select during configuration read or write transac-
tions.
DEVSEL#
INTA#
s/t/s
o/d
Device Select. This signal is driven by a target decoding and recognizing its bus address. This signal
informs a bus master whether an agent has decoded a current bus cycle.
Interrupt A. This signal is defined as optional and level sensitive. Driving it low will interrupt to the host.
The INTA# interrupt is to be used for any single function device requiring an interrupt capability.
Table 4. PCI Bus Error Reporting Signals
Signal
Type
Description
PERR#
s/t/s
Parity Error. Only for reporting data parity errors for all bus transactions except for Special Cycles. It is
driven by the agent receiving data two clock cycles after the parity was detected as an error. This signal is
driven inactive (high) for one clock cycle prior to returning to the tri-state condition.
SERR#
o/d
System Error. Used to report address and data parity errors on Special Cycle commands and any other
error condition having a catastrophic system impact. Special Cycle commands are not supported by the
S5320.
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S5320 – PCI Match Maker: Signal Description
ADD-ON BUS AND S5320 CONTROL SIGNALS
Data Sheet
The following sets of signals represent the interface signals available for the user Add-On bus and S5320 control.
Table 5. Serial nvRAM Interface Signals
Signal
Type
Description
SCL
o/d-out Serial Clock. This clock provides timing for all transactions on the two-wire serial bus. The S5320 drives
this signal when performing as a serial bus master. SCL operates at the maximum allowable clock
speed and enters the high Z state when FLT# is asserted or the serial bus is inactive.
SDA
o/d
Serial Data/Address. This bi-directional signal carries serial address and data information between
nvRAMs and the S5320. This pin enters high Z state when FLT# is asserted or the serial bus is inactive.
Table 6. Direct Mailbox Access Signals
Signal
Type
Description
MDMODE
in
Mailbox Data Mode. The MD[7:0] signal pins are always inputs when this signal is high. The MD[7:0]
signal pins are defined as inputs and outputs under LOAD# control when MDMODE is low. This pin is
provided for software compatibility with the S5335. New designs should permanently connect this sig-
nal low. This signal is connected to an internal 50k Ohm pull-up.
LOAD#
MD[7:0]
in
MD[7:0] is defined as an input bus when this signal is low. The next rising edge of the ADCLK will latch
MD[7:0] data into byte three of the Add-On outgoing mailbox. When LOAD# is high and MDMODE is
low, MD[7:0] are defined as outputs displaying byte three of the PCI outgoing mailbox. This signal is
connected to an internal 50k Ohm pull-up.
t/s
Mailbox Data bus. The mailbox data registers can be directly accessed using the LOAD# and
MDMODE signals. When configured as an input, data byte three of the PCI incoming mailbox is directly
written to from these pins. When configured as an output, data byte three of the PCI outgoing mailbox
is output to these pins. All MD[7:0] signals have an internal 50k Ohm pull-up.
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S5320 – PCI Match Maker: Signal Description
USER ADD-ON BUS PIN DESCRIPTIONS
Data Sheet
The following sets of signals represent the interface pins available for the Add-On bus. The following defines three
signal groups: S5320 register access signals, Pass-Thru channel signals, and general Add-On bus signals.
Table 7. Pass-Thru Data Channel Pins
Signal
Type
Description
PTMODE
in
Pass-Thru Mode. Configures the Pass-Thru data channel operation. High configures the S5320
in Passive mode allowing other devices to read/write data bus data. Low configures the S5320 in
Active mode. This mode allows the S5320 to actively drive signals and data onto the data bus.
This signal is connected to an internal 50k Ohm pull-up.
PTATN#
PTBURST#
out
out
in
Pass-Thru Attention. Signals a decoded PCI to Pass-Thru region bus cycle. PTATN# is gener-
ated to signal that Add-On logic Pass-Thru data must be read from or written to the S5320.
Pass-Thru Burst. Informs the Add-On bus that the current Pass-Thru region decoded PCI bus
cycle is a burst access.
PTRDY#/WAIT#
Pass-Thru Ready/Pass-Thru Wait. During passive mode, the signal is referred to as PTRDY#
and is asserted low to indicate Add-On logic has read/written data in response to a PTATN# sig-
nal. During active mode operation, the signal is referred to as WAIT# and can be driven low to
insert wait states or hold the S5320 from clocking data onto the data bus. PTRDY# or WAIT# is
synchronous to ADCLK.
PTNUM[1:0]
PTBE[3:0]#
PTADR#
out
out
t/s
Pass-Thru Number. Identifies which of the four Pass-Thru regions the PTATN# read/write is
requesting. Only valid for the duration of PTATN# active. 00 = Base Address Register 1, 01 =
Base Address Register 2, 10 = Base Address Register 3, 11 = Base Address Register 4.
Pass-Thru Byte Enables. During a PCI to Pass-Thru read, PTBE[3:0] indicate which bytes of a
DWORD are to be written into. During a PCI to Pass-Thru write, these pins indicate which bytes
of a DWORD are valid to read. PTBE[3:0]# are only valid while PTATN# is asserted.
Pass-Thru Address. Is an input when in passive mode. When asserted, the 32-bit Pass-Thru
address register contents are driven onto the DQ[31:0] bus. All other Add-On control signals
must be inactive during the assertion of PTADR# in passive mode. In active mode, becomes an
output and indicates a Pass-Thru address is on the DQ bus. The DQMODE signal does not affect
DQ bus width while the Pass-Thru address is driven.
PTWR
out
out
Pass-Thru Write. This signal indicates whether the current PCI to Pass-Thru bus transaction is a
read or write cycle. Valid only when PTATN# is active.
DXFER#
ACTIVE Transfer complete. When in ACTIVE mode, this output is asserted at the end of every 8-
16- or 32-bit data transfer cycle. This signal is not used in Passive mode.
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S5320 – PCI Match Maker: Signal Description
Data Sheet
Table 8. S5320 Add-On Bus Register Access Pins
Signal
Type
Description
DQ[31:0]
t/s
Address/Data bus. The 32-bit Add-On data bus. The DQMODE signal configures the bus width for
either 32 or 16 bits. All DQ[31:0] signals have an internal 50k Ohm pull-ups.
ADR[6:2]
in
Address [6:2]. These inputs select which S5320 register is to be read from or written to. To be used
in conjunction with SELECT#, BE[3:0]# and WR# or RD#. The register addresses are as follows:
ADR[6:2]
0 0 0 1 1
0 0 1 1 1
0 1 0 1 0
0 1 0 1 1
0 1 1 0 1
0 1 1 1 0
0 1 1 1 1
1 0 0 0 0
Register Name
Add-On Incoming Mailbox Register
Add-On Outgoing Mailbox Register
Add-On Pass-Thru Address Register
Add-On Pass-Thru Data Register
Add-On Mailbox Status Register
Add-On Interrupt Control Register
Add-On Reset ControlRegister
Pass-Thru/FIFO Configuration Register
Note: ADR[6:2] bits begin at bit position two. All references to an address, in hex, adds bits 0 and 1
as zeros. Example: The Add-On incoming mailbox register is referenced as 0Ch.
BE[2:0]#
in
in
Byte Enable 2 through 0. Provides individual read/write byte enabling during register read or write
transactions. BE2# enables activity over DQ[23:16], BE1# enables DQ[15:8], and BE0# enables
DQ[7:0]. During read transactions, these pins enable the output driver for each byte lane; for write
transactions, they serve as an input enable to perform the write to each byte lane.
BE3# / ADR1
Byte Enable [3] for a 32-bit bus width / Address [1] for a 16-bit bus width. BE3#, enables DQ[31:24]
input drivers for writing data to registers identified by ADR[6:2] and enables DQ[31:24] output driv-
ers to read registers identified by ADR[6:2]. To be used in conjunction with SELECT# and RD# or
WR#. ADR1, selects the upper or lower WORD of a DWORD when a 16-bit-wide bus is selected. 1
= upper, 0 = lower.
SELECT#
WR#
in
in
in
in
Select. Enables internal S5320 logic to decode WR#, RD# and ADR[6:2] when reading or writing to
any Add-On register.
Write Enable. Asserting this signal writes DQ bus data byte(s) selected by BE[3:0]# into the S5320
register defined by SELECT# and ADR[6:2].
RD#
Read Enable. Asserting this signal drives data byte(s) selected by BE[3:0]# from the S5320 register
defined by SELECT# and ADR[6:2] onto the DQ bus.
DQMODE
DQ Mode. Defines the DQ bus width when accessing data using WR#, RD#, SELECT# and
ADR[6:2]#. Low = 32-bit wide DQ bus. High = 16-bit wide DQ bus. When high, the signal BE3# is re-
assigned to the ADR1 signal and only DQ[15:0] is active.
Note: This pin only affects DQ Bus Width for S5320 Data Registers. This pin has no effect on
accesses DQ Bus Width. For the Pass-Thru data register (APTD, ADR = 2Ch). The width of the DQ
bus is determined by the region-size bits in the corresponding Base Address Register. In addition,
DQMODE has no effect when using the direct-access pin PTADR#. When PTADR# is asserted, all
32 bits of the Pass-Thru address are provided.
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S5320 – PCI Match Maker: Signal Description
Data Sheet
Table 9. Add-On Bus General Pins
Signal
Type
Description
SYSRST#
out
System Reset. An active-low buffered PCI bus RST# output signal. The signal is asynchro-
nous and can be asserted through software from the PCI host interface.
BPCLK
ADCLK
IRQ#
out
in
Buffered PCI Clock. This output is a buffered form of the PCI bus clock and has all of the
behavioral characteristics of the PCI clock (i.e., DC-to-33 MHz capability).
Add-On Clock. All internal S5320 Add-On bus logic is synchronous to this clock. The clock
is asynchronous to the PCI bus logic unless connected to the BPCLK signal.
out
in
Interrupt Request. This output signals to Add-On logic that a significant event has occurred
as a result of activity within the S5320.
ADDINT#
Add-On interrupt. When enabled and asserted, this input will cause a PCI bus interrupt by
driving INTA# low. The input is level sensitive and can be driven by multiple sources. This
signal is connected to an internal 50k Ohm pull-up.
FLT#
in
Float. Floats all S5320 output signals when asserted. This signal is connected to an internal
50k Ohm pull-up
Pin 125
Pin 139
Pin 140
Pin 156
Pin 134
X
X
X
X
X
For factory use only. Must be left open. (RSVD1)
For factory use only. Must be left open. (RSVD2)
For factory use only. Must be left open. (RSVD3)
For factory use only. Must be left open. (RSVD4)
For factory use only. Must be left open. (RSVD5)
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S5320 – PCI Match Maker: PCI Configuration Registers
Data Sheet
Each PCI bus device contains a unique 256-byte region called its configuration header space. Portions of this con-
figuration header are mandatory in order for a PCI agent to be in full compliance with the PCI specification. This
section describes each of the configuration space fields—its address, default values, initialization options, and bit
definitions—and also provides an explanation of its intended usage.
Table 10. Configuration Registers
Address Offset
00h–01h
02h–03h
04h–05h
06h–07h
8h0
Abbreviation
VID
Register Name
Vendor Identification Register
DID
Device Identification Register
Command Register
PCICMD
PCISTS
RID
Status Register
Revision Identification Register
Class Code Register
09h–0Bh
0Ch
CLCD
CALN
LAT
Cache Line Size Register
Latency Timer Register
Header Type Register
Built-in Self-test Register
Base Address Registers (0-5)1
Reserved
0Dh
0Eh
HDR
0Fh
BIST
10h–27h
28h–2Bh
2Ch–2Dh
2Eh–2Fh
30h–33h
34h–3Bh
3Ch
BADR0-BADR5
–
SVID
Subsystem Vendor Identification Register
Subsystem Identification Register
Expansion ROM Base Address Register
Reserved
SID
XROM
–
INTLN
INTPIN
MINGNT
MAXLAT
–
Interrupt Line Register
Interrupt Pin Register
3Dh
3Eh
Minimum Grant Register
Maximum Latency Register
Not used
3Fh
40h–FFh
1. BADR 5 is not implemented in the S5320.
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S5320 – PCI Match Maker: PCI Configuration Registers
Data Sheet
PCI Configuration Space Header
31
24 23
16 15
8 7
00
DEVICE ID
VENDOR ID
00
04
08
STATUS
COMMAND
REV ID
CACHE LINE SIZE
CLASS CODE
HEADER TYPE
BIST
LATENCY TIMER
0C
10
14
18
1C
20
BASE ADDRESS REGISTER #0
BASE ADDRESS REGISTER #1
BASE ADDRESS REGISTER #2
BASE ADDRESS REGISTER #3
BASE ADDRESS REGISTER #4
BASE ADDRESS REGISTER #5
24
28
2C
RESERVED = 0's
SUBSYSTEM ID
SUBSYSTEM VENDOR ID
EXPANSION ROM BASE ADDRESS
RESERVED = 0's
30
34
38
3C
RESERVED = 0's
MAX_LAT
MIN_GNT
INTERRUPT PIN
INTERRUPT LINE
LEGEND
EPROM IS DATA SOURCE (READ ONLY)
CONTROL FUNCTION
EPROM INITIALIZED RAM (CAN BE ALTERED FROM PCI PORT)
EPROM INITIALIZED RAM (CAN BE ALTERED FROM ADD-ON PORT)
HARD-WIRED TO ZEROES
Note: Some registers are a combination of the above. See individual sections
for full description.
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This register is reserved for the manufacturer’s device
identification number (VID). VID numbers are
assigned to each PCI device manufacturer by an inter-
national organization known as the PCI Special
Interest Group (SIG). This ensures PCI device unique-
ness among all manufacturers. This register defaults
to AMCC's VID during power-on initialization. The
default value can be changed to another valid VID
when an external non-volatile device is used for boot
loading.
PCI CONFIGURATIONS REGISTERS
Vendor Identification Register (VID)
Vendor Identification
00h-01h
Register Name:
Address Offset:
Power-up value:
Boot-load:
10E8h (AMCC’s)
External nvRAM offset 040h-41h
Read Only
Attribute:
16 Bits
Size:
Figure 6. Vendor Identification Register
15
0
10E8h
Vendor Identification Register (RO)
Bit
Description
Vendor Identification Number: AMCC’s 16-bit value is 10E8h
15.0
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Data Sheet
Device Identification Register (DID)
This register is reserved for the manufacturer’s device
identification number (DID). DID numbers are main-
tained and issued by the registered owner of the VID
number programmed into a PCI device. AMCC will
issue a DID number to manufacturers using the AMCC
VID. This maintains PCI device uniqueness among all
manufacturers. to be in compliance. This register
defaults to AMCC's DID during power-on initialization.
The default value can be changed to another valid DID
when an external nonvolatile device is used for boot
loading.
Device Identification
Register Name:
Address Offset:
Power-up value:
Boot-load:
02h-03h
5920h
External nvRAM offset 042h-43h
Read Only
16 bits
Attribute:
Size:
Figure 7. Device Identification Register
15
0
5920h
DeviceIdentificationRegister
(RO)
Bit
Description
Device Identification Number: AMCC’s temporary end user value 5920h
15.0
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Data Sheet
PCI Command Register (PCICMD)
This 16-bit register provides basic control over a
device’s ability to respond to or perform PCI accesses.
This register is defined by the PCI specification and its
implementation is required of all PCI devices. Four of
the ten implemented bits are required by the S5320;
those which are not required are hardwired to 0. The
definitions for all the fields are provided here for
completeness.
PCI Command
04h-05h
Register Name:
Address Offset:
Power-up value:
Boot-load:
0000h
not used
Read/Write (R/W on 4 bits, R/O for
all others)
Attribute:
Size:
16 bits
Figure 8. PCI Command Register
15
9
0
8
X
7
0
6
X
5
0
4
0
3
0
2
0
1
X
0
X
Reserved = 00
Fast Back-to-Back
SERR# Enable
Wait Cycle Enable
PERR# Enable
Palette Snoop Enable
Memory Write and Invalidate Enable
Special Cycle Enable
Bus Master Enable
Memory Access Enable
I/O Access Enable
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Data Sheet
Bit
15:10
9
Description
Reserved. Hardwired to 0.
Fast Back-to-Back Enable. This bit enables fast back-to-back capability for bus master transaction. The S5320
is a target-only device and hardwires this bit to a 0.
8
System Error Enable. Setting this bit to a 1 allows the S5320 to drive the SERR# signal. Setting to a 0 will dis-
able the output driver. The assertion of RESET# will set this bit to a 0. The SERR# pin driven active normally
signifies a parity error occurred during a PCI address phase.
7
6
Wait Cycle Enable. Controls whether a device implements address/data stepping. This bit is hardwired to 0 as
the S5320 does not uses stepping.
Parity Error Enable. This bit allows the S5320 to drive the PERR# and to generate a SERR# signal. A one
allows the parity generation and a 0 will disable generation of a parity error indication. This bit is set to 0 when
RESET# is asserted.
5
4
Palette Snoop Enable. Enables VGA compatible devices to perform palette snooping. This bit is hardwired to a
0 as the S5320 is not a PCI-based VGA device.
Memory Write and Invalidate Enable. This bit enables bus masters to generate Memory Write and Invalidate
PCI bus commands when set to a 1. When set to 0, bus masters generate memory write commands instead.
The S5320 is a PCI target only and therefore hardwires this bit to 0.
3
2
1
Special Cycle Enable. Setting this bit to one enables devices monitoring of PCI special cycles. The S5320 does
not monitor (or generate) special cycles and hardwires this bit to 0.
Bus Master Enable. This bit allows a PCI device to function as a Bus Master. The S5320 is a PCI target device
only and hardwires his bit to 0.
Memory Space Enable. This bit enables S5320 memory region decodes to any of the five defined base address
register memory regions and the Expansion ROM Base Address Register. This bit is cleared to 0 when RESET#
is asserted.
0
I/O Space Enable. This bit enables S5320 I/O region decodes to any of the five defined base address register I/
O regions. This bit is cleared to 0 when RESET# is asserted.
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PCI Status Register (PCISTS)
This register contains PCI device status information.
This register is defined by the PCI specification and its
implementation is required of all PCI devices. Only
applicable bits are used by the S5320; those which are
not used are hardwired to 0. Status bits within this reg-
ister are designated as “write one clear,” meaning that
in order to clear a given bit, a 1 must be written. All R/
W/C bits written with a 0 are left unchanged. These
bits are identified in Figure 9 as (R/WC). Those which
are Read Only are shown as (RO).
PCI Status
Register Name:
Address Offset:
Power-up value:
Boot-load:
06h-07h
0200h
not used
Read Only Read/Write Clear
16 bits
Attribute:
Size:
Figure 9. PCI Status Register
15 14 13 12 11 10
9
1
8
0
7
1
6
0
54
0
0
X
X
0
0
0
0
Reserved = 00's
Reserved (RO)
66 Mhz Capable
UDF Supported
Fast Back-to-Back Capable
(RO)
Data Parity Reported (RO)
DEVSEL# Timing Status
00 = Fast
01 = Medium
10 = Slow
11 = Reserved
Signaled Target Abort (R/WC)
Received Target Abort (RO)
Received Master Abort (RO)
Signaled System Error (R/WC)
Detected Parity Error (R/WC)
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Data Sheet
Bit
Description
15
Detected Parity Error. This bit is set whenever the S5320 detects a parity error. It is set independent of the state
of Command Register Bit 6. The bit is cleared by writing a 1.
14
13
12
11
10:9
8
Signaled System Error. This bit is set whenever the S5320 generates the SERR# signal. This bit can be reset by
writing a 1.
Received Master Abort. Bus master devices set this bit to indicate a bus master transaction has been termi-
nated due to a master abort. The S5320 is a target device and hardwires this to 0.
Received Target Abort. This bit is set by a bus master when its transaction is terminated by a target abort from
the currently addressed target device. This bit is required for bus masters and is hardwired to 0 in the S5320.
Signaled Target Abort. This bit is set the target device whenever it terminates a transaction with a target abort.
The S5320 does not issue target aborts and hardwires this bit to 0.
Device Select Timing. These bits are read-only and define the DEVSEL# timing for a target device. The S5320
is a medium PCI device.
Data Parity Reported. Only implemented by bus mastering devices to notify a parity error has been detected.
This is not applicable to the S5320 and is hardwired to 0.
7
Fast Back-to-back Capable. This read-only bit indicates if a target device supports fast back-to-back transac-
tions. The S5320 supports this feature and hardwires the bit to 1.
6
UDF Supported. 1 = device supports user-definable features. 0 = device does not support user- definable fea-
tures. The S5320 implements definable memory regions and hardwires this bit to 0.
5
66 MHz Capable. 1 = device is capable of running at 66 MHz. 0 = device is capable of running at 33 MHz. This
bit is hardwired to 0.
4:0
Reserved. Hardwired to zero.
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Data Sheet
Revision Identification Register (RID)
This register is reserved for AMCC’s S5320 silicon
revision identification number. The register defaults to
that value after power up. Write operations from the
PCI interface have no effect on the register. User-
defined values can be boot-loaded from an optional
external non-volatile. AMCC does not recommend
changing the register value. The Sub-system Vendor
ID and/or Subsystem ID are intended for end user
information.
Revision Identification
Register Name:
Address Offset:
Power-up value:
Boot-load:
08h
00h
External nvRAM/EPROM offset 048h
R/W
Attribute:
8 Bits
Size:
Figure 10. Revision Identification Register
7
0
00h
Revision Identification Number (RO)
Bit
Description
Revision Identification Number: Initialized to the S5320 silicon revision.
7:0
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Data Sheet
Class Code Register (CLCD)
This 24-bit, read-only register is divided into three one-
byte fields: the base class byte at location 0Bh, the
sub-class byte at 0Ah, and the programming interface
byte at 09h. The default setting for the base class is
FFh, which indicates that the device does not fit into
the thirteen base classes defined in the PCI Bus Spec-
ification. It is possible, however, through use of the
external non-volatile memory to change the value of
this register. Refer to the PCI specification for details.
Class Code
Register Name:
Address Offset:
Power-up value:
Boot-load:
09h-0Bh
FF0000h
External nvRAM offset 049h-4Bh
Read Only
24 Bits
Attribute:
Size:
Figure 11. Class Code Register
@0Ah
@09h
@0Bh
7
7
0
07
0
Base Class
Sub-Class
Prog I/F
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Table 11. Defined Base Class Codes
Base-Class
00h
Description
Early, pre-2.0 PCI specification devices
Mass storage controller
Network controller
01h
02h
03h
Display controllers
04h
Multimedia devices
05h
Memory controllers
06h
Bridge devices
07h
Simple communication controllers
Generic system peripherals
Input devices
08h
09h
0Ah
Docking stations
0Bh
Processors
0Ch
Serial bus controllers
Reserved
0D-FEh
FFh
Device does not fit defined class codes (default)
Table 12. Base Class Code 00h: Early, Pre-2.0 Specification Devices
Sub-Class
00h
Prog I/F
00h
Description
All currently implemented devices except VGA-compatible devices
VGA-compatible devices
01h
00h
Table 13. Base Class Code 01h: Mass Storage Controllers
Sub-Class
00h
Prog I/F
00h
Description
SCSI controller
01h
xxh
IDE controller
02h
00h
Floppy disk controller
IPI controller
03h
00h
04h
00h
RAID controller
80h
00h
Other mass storage controller
Table 14. Base Class Code 02h: Network Controllers
Sub-Class
Prog I/F
Description
00h
00h
Ethernet controller
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Data Sheet
Table 14. Base Class Code 02h: Network Controllers
Sub-Class
01h
Prog I/F
00h
Description
Token ring controller
FDDI controller
02h
00h
03h
00h
ATM controller
80h
00h
Other network controller
Table 15. Base Class Code 03h: Display Controllers
Sub-Class
00h
Prog I/F
00h
Description
RAM memory controller
Flash memory controller
Other memory controller
01h
00h
80h
00h
Table 16. Base Class Code 04h: Multimedia Devices
Sub-Class
00h
Prog I/F
00h
Description
VGA-compatible controller
8514 compatible controller
XGA controller
00h
01h
01h
00h
80h
00h
Other display controller
Table 17. Base Class Code 05h: Memory Controllers
Sub-Class
00h
Prog I/F
00h
Description
Video device
01h
00h
Audio device
80h
00h
Other multimedia device
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Table 18. Base Class Code 06h: Bridge Devices
Sub-Class
00h
Prog I/F
00h
Description
Host/PCI bridge
PCI/ISA bridge
01h
00h
02h
00h
PCI/EISA bridge
PCI/Micro Channel bridge
PCI/PCI bridge
03h
00h
04h
00h
05h
00h
PCI/PCMCIA bridge
NuBus bridge
06h
00h
07h
00h
CardBus bridge
Other bridge type
80h
00h
Table 19. Base Class Code 07h: Simple Communications Controllers
Sub-Class
Prog I/F
Description
Generic XT compatible serial controller
16450 compatible serial controller
16550 compatible serial controller
00h
00h
01h
02h
01h
80h
00h
01h
02h
Parallel port
Bidirectional parallel port
ECP 1.X compliant parallel port
00h
Other communications device
Table 20. Base Class Code 08h: Base System Peripherals
Sub-Class
Prog I/F
Description
00h
00h
01h
02h
Generic 8259 PIC
ISA PIC
EISA PIC
01h
02h
00h
01h
02h
Generic 8237 DMA controller
ISA DMA controller
EISA DMA controller
00h
01h
02h
Generic 8254 system timer
ISA system timer
EISA system timers (2 timers)
03h
80h
00h
01h
Generic RTC controller
ISA RTC controller
00h
Other system peripheral
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Data Sheet
Table 21. Base Class Code 09h: Input Devices
Sub-Class
00h
Prog I/F
00h
Description
Keyboard controller
Digitizer (Pen)
01h
00h
02h
00h
Mouse controller
Other input controller
80h
00h
Table 22. Base Class Code 0Ah: Docking Stations
Sub-Class
00h
Prog I/F
00h
Description
Intel386™
Intel486™
Pentium™
Alpha™
01h
00h
02h
00h
10h
00h
40h
00h
Co-processor
Table 23. Base Class Code 0Bh: Processors
Sub-Class
00
Prog I/F
Description
00h
00h
00h
00h
00h
FireWire™ (IEEE 1394)
ACCESS.bus
01h
02h
SSA
03h
Universal Serial Bus
Fibre Channel
04h
Table 24. Base Class Code 0Ch: Serial Bus Controllers
Sub-Class
00h
Prog I/F
00h
Description
Generic docking station
80h
00h
Other type of docking station
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Data Sheet
Cache Line Size Register (CALN)
The cache line configuration register is used by bus
masters implementing memory write and invalidate
commands. The register defines the cache line size in
double word (64-bit) increments. The S5320 is a target
device not requiring cache. The register is hardwired
to 0.
Cache Line Size
0Ch
Register Name:
Address Offset:
Power-up value:
Boot-load:
00h, hardwired
not used
Read Only
8 bits
Attribute:
Size:
Figure 12. Cache Line Size Register
7
0
00h
Cache Line Size (RO)
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Data Sheet
Latency Timer Register (LAT)
The latency timer defines the minimum amount of time
that a bus master can retain ownership of the PCI bus.
The S5320 is a target device requiring zero bus own-
ership time. The register is hardwired to zero.
Latency Timer
0Dh
Register Name:
Address Offset:
Power-up value:
Boot-load:
00h
not used
Read Only
8 bits
Attribute:
Size:
Figure 13. Latency Timer Register
7
0
00h
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S5320 – PCI Match Maker: PCI Configuration Registers
Data Sheet
Header Type Register (HDR)
This register consists of two fields: Bits 6:0 define the
format of double words 4d through 15d of the device’s
configuration header. Bit 7 defines whether the device
is a single function or a multi-function PCI bus agent.
The S5320 is defined as a single function PCI device.
Header Type Address Offset 0Eh
Register Name:
Power-up value:
00h, Hardwired Boot-load: External
nvRAM offset 04Eh
Read Only
8 bits
Attribute:
Size:
Figure 14. Header Type Register
6
7
0
0
00h
Configuration header format
0 = single function device
1= multi function device
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Data Sheet
Built-In Self-Test Register (BIST)
The Built-In Self-Test (BIST) Register permits the
implementation of custom, user-specific diagnostics.
This register has four fields shown in Figure 15. Bit 7
defines S5320's support of a built-in self test. When bit
7 is set, writing a 1 to bit 6 produce an interrupt signal
on the Add-On bus. Bit 6 remains set until cleared by a
write operation to this register from the Add-On bus
interface. When bit 6 is reset, it is interpreted as com-
pletion of the self-test and an error is indicated by a
non-zero value for the completion code (bits 3:0).
Built-in Self-Test Address Offset 0Fh
Register Name:
Power-up value:
00h
External nvRAM/EPROM offset
04Fh
Boot-load:
D7, D5-0 Read Only, D6 as PCI bus
write only
Attribute:
Size:
8 bits
Figure 15. Built-In Self-Test Register
7
X
6
0
5
4
3
0
00
X
Completion Code (RO)
Reserved (RO)
Start BIST (R/WS)
BIST Capable (RO)
Bit
Description
7
BIST Capable. This bit indicates the Add-On device supports a built-in self-test when a 1 is returned. A 0 should
be returned if this self-test feature is not required. This field is read only from the PCI interface.
6
Start BIST. Writing a 1 to this bit indicates that the self-test should start. This bit can only be written if bit 7 is one.
When bit 6 is set, an interrupt is issued to the Add-On interface. Other than through a reset, Bit 6 can only be
cleared by a write to this element from the Add-On bus interface. The PCI bus specification requires that this bit
be cleared within 2 seconds after being set, or the device will be failed. This bit is read/write set (R/WS).
5:4
3:0
Reserved. These bits are reserved and are hardwired to 0.
Completion Code. This field provides a method for detailing a device-specific error. It is considered valid when
the start BIST (bit 6) changes from 1 to 0. An all-zero value for the completion code indicates successful com-
pletion.
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Base Address Register (BADR)
Determining Base Address Size
The address space defined by a given base address
register is determined by writing all 1s to a given base
address register from the PCI bus and then reading
that register back. The number of 0s returned starting
from D4 for memory space and D2 for I/O space
toward the high-order bits reveals the amount of
address space desired. Tables 25 and 26 list the pos-
sible returned values and their corresponding size for
both memory and I/O, respectively.
Base Address
Register Name:
Address Offset:
10h, 14h, 18h, 1Ch, 20h
FFFFFF81h for offset 10h;
00000000h for all others
Power-up value:
Boot-load:
External nvRAM offset 050h, 54h,
58h, 5Ch, 60h (BADR0-4)
high bits Read/Write; low bits Read
Only
Included in the tables are the nvRAM/EPROM boot
values which correspond to a given assigned size. A
register returning all 0s indicates the region is
disabled.
Attribute:
Size:
32 bits
Assigning the Base Address
Base address registers are used by the system BIOS
to determine how much memory or I/O address space
a region requires in host space. The actual memory or
I/O location(s) of the space is determined by interro-
gating these registers after BIOS power-up
initialization. Bit zero of each field is used to select
whether the space required is to be decoded as mem-
ory (bit 0 = 0) or I/O (bit 0 = 1). Since this PCI device
has internal operating registers, the Base Address
Register at offset 10h is assigned to them. The
remaining four base address registers can only be
used by boot-loading them from the external nvRAM
interface.
After a base address has been sized, the BIOS can
physically locate it in memory (or I/O) space. The base
address value must be on a natural binary boundary
for the required size. For example, if the first base
address register returns FFFFFF81h indicating an I/O
space (D0=1) of size 80h. This means that the 5920’s
internal registers can be selected for I/O addresses
between 00000300h through 0000037Fh, in this
example. (example 300h, 380h etc.; 338h, 340h would
not be allowable).
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Data Sheet
Figure 16. Base Address Register - Memory
0
0
Bit
31
x
30
x
29
4
3
0
2
0
1
0
Value
Base Address
Memory Space
Indicator (RO)
Type (RO)
00 = Locate
Anywhere (32)
01 = Below 1 MB
10 = Locate Anywhere (64)
11 = Reserved
Prefetchable (RO)
Programmable (RO)
D31 D30 Add-On Bus Width
0
0
1
1
0
1
0
1
Region Disable
8 bits
16 bits
32 bits
Bit
Description
31:4
Base Address Location. These bits locate the decoded region in memory space. Only bits which return a 1 after
being written as 1 are usable for this purpose. Except for Base Address Register 0, these bits are individually
enabled by the contents sourced from the external boot memory.
3
Prefetchable. When set as a 1, this bit signifies that this region of memory can be cached. Cacheable regions
can only be located within the region altered through PCI bus memory writes. This bit, when set, also implies
that all read operations will return the data associated for all bytes regardless of the Byte Enables. Memory
space which cannot support this behavior should leave this bit in the zero state. this bit is set by the reset pin
and later initialized by the external boot memory option. Base Address Register 0 always has this bit set to 0.
This bit is read only from the PCI interface. This bit has no implementation in the S5320 other than providing it
during a configuration read cycle.
2:1
Memory Type. These bits define whether the memory space is 32 or 64 bits wide and if the space location is
restricted to be within the first megabyte of memory space. The encoding is as follows:
Description
Bits
2
0
0
1
1
0
Region is 32-bits wide and can be located anywhere in 32-bit memory space.
1
0
Region is 32 bits wide and must be mapped below the first Mbytes of memory space.
Region is 64 bits wide and can be mapped anywhere within 64-bit memory space. (Not supported
by this device.)
1
1
Reserved.
2
0
Note: The 64-bit memory space is not supported by this device. Bit 2 is hardwired to 0. Options are restricted to
desired to memory space anywhere within 32-bit memory space or located in the first megabyte. For Base
Addresses 1 through 4, this bit is cleared by the reset pin and later initialized by the external boot memory
option.
Space Indicator = 0. When set to 0, this bit defines a base address region as memory space and the remaining
bits in the base address register are defined as shown in Figure 16.
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Data Sheet
Figure 17. Base Address Register - I/O
0
1
Bit
31
2
1
0
Value
Base Address
I/O Space
Indicator (RO)
Reserved (RO)
Programmable (R/W)
Bit
Description
31:2
Base Address Location. These bits are used to position the decoded region in I/O space. Only bits which return
a 1 after being written as 1 are usable for this purpose. Except for Base Address 0, these bits are individually
enabled by the contents sourced from the external nvRAM.
1
0
Reserved. This bit should be 0. (Note: disabled Base Address Registers will return all 0s for the entire register
location, bits 31 through 0).
Space Indicator = 1. When 1, this bit identifies a base address region as an I/O space and the remaining bits in
the base address register have the definition as shown in Figure 17.
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Data Sheet
Table 25. Base Address Register Response (Memory Assigned) to All-Ones Write Operation
Response Size in Bytes
00000000h
nvRAM boot value1
00000000h or BIOS missing2
none - disabled
FFFFFFF0h
FFFFFFE0h
FFFFFFC0h
FFFFFF80h
FFFFFF00h
FFFFFE00h
FFFFFC00h
FFFFF800h
FFFFF000h
FFFFE000h
FFFFC000h
FFFF8000h
FFFF0000h
FFFE0000h
FFFC0000h
FFF80000h
FFF00000h
FFE00000h
FFC00000h
FF800000h
FF000000h
FE000000h
FC000000h
F8000000h
F0000000h
E0000000h
16 bytes (4 DWORDs)
FFFFFFF0h
FFFFFFE0h
FFFFFFC0h
FFFFFF80h
FFFFFF00h
FFFFFE00h
FFFFFC00h
FFFFF800h
FFFFF000h
FFFFE000h
FFFFC000h
FFFF8000h
FFFF0000h
FFFE0000h
FFFC0000h
FFF80000h
FFF00000h
FFE00000h
FFC00000h
FF800000h
FF000000h
FE000000h
FC000000h
F8000000h
F0000000h
E0000000h
32 bytes (8 DWORDs)
64 bytes (16 DWORDs)
128 bytes (32 DWORDs)
256 bytes (64 DWORDs)
512 bytes (128 DWORDs)
1K bytes (256 DWORDs)
2K bytes (512 DWORDs)
4K bytes (1K DWORDs)
8K bytes (2K DWORDs)
16K bytes (4K DWORDs)
32K bytes (8K DWORDs)
64K bytes (16K DWORDs)
128K bytes (32K DWORDs)
256K bytes (64K DWORDs)
512K bytes (128K DWORDs)
1M bytes (256K DWORDs)
2M bytes (512K DWORDs)
4M bytes (1M DWORDs)
8M bytes (2M DWORDs)
16M bytes (4M DWORDs)
32M bytes (8M DWORDs)
64M bytes (16M DWORDs)
128M bytes (32M DWORDs)
256M bytes (64M DWORDs)
512M bytes (128M DWORDs)
1. The two most significant bits define bus width for BADR1:4 in Pass-Thru operation. (See S5320 Base Address Register Definition.)
2. Bits D3, D2 and D1 may be set to indicate other attributes for the memory space.
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Table 26. Read Response (I/O Assigned) to an All-Ones Write Operation to a Base Address Register
Response
00000000h
Size in Bytes
nvRAM boot value
00000000h or BIOS missing
none - disabled
FFFFFFFDh
FFFFFFF9h
FFFFFFF1h
FFFFFFE1h
FFFFFFC1h
FFFFFF81h
FFFFFF01h
4 bytes (1 DWORDs)
8 bytes (2 DWORDs)
16 bytes (4 DWORDs)
32 bytes (8 DWORDs)
64 bytes (16 DWORDs)
128 bytes (32 DWORDs)
256 bytes (64 DWORDs)
FFFFFFFDh
FFFFFFF9h
FFFFFFF1h
FFFFFFE1h
FFFFFFC1h
FFFFFF81h 1
FFFFFF01h
1. Base Address Register 0, at offset 10h, powers up as FFFFFF81h. This default assignment allows usage without an external boot memory.
Should an nvRAM be used, the base address can be boot loaded to become a memory space (FFFFFF80h or FFFFFF82h).
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Data Sheet
Subsystem Vendor Identification Register (SVID)
This register is used to uniquely identify the user board
or subsystem. It provides a mechanism for add-in card
vendors to distinguish devices with the same Vendor
ID and Device ID. Implementation of this register is
mandatory for 2.2 compliance and an all-zero value
indicates that the device does not support subsystem
identification. Subsystem Vendor IDs may be obtained
directly from the PCI SIG by the user and it is loaded
by the S5320 from the external nvRAM at power up.
Subsystem Vendor ID
2Ch-2Dh
Register Name:
Address Offset:
Power-up value:
Boot-load:
0000h
External nvRAM offset 6Ch-6Dh
Read Only (RO)
16 bits
Attribute:
Size:
Figure 18. Subsystem Vendor Identification Register
15
0
0000h
Subsystem Vendor Identification Register (RO)
Bit
Description
15:0
Subsystem Vendor Identification Number.
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Subsystem ID Register (SID)
This register is used to further identify the add-in board
or subsystem. It provides a mechanism for add-in card
vendors to distinguish devices with the same Vendor
ID and Device ID. Implementation of this register is
mandatory for 2.2 compliance and an all-zero value
indicates that the device does not support subsystem
identification. Subsystem ID is vendor-specific. It is
loaded by the S5320 from the external nvRAM at
power up.
Subsystem Identification
Register Name:
Address Offset:
Power-up value:
Boot-load:
2Eh-2Fh
0000h
External nvRAM offset 6Eh-6Fh
Read Only (RO)
Attribute:
16 bit
Size:
Figure 19. Subsystem Identification Register
15
0
0000h
Subsystem Identification Register (RO)
Bit
Description
15:0
Subsystem Identification Number.
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Data Sheet
Expansion ROM Base Address Register (XROM)
The Expansion ROM Base Address Register provides
a mechanism for assigning a space within physical
memory for a BIOS expansion ROM. Access from the
PCI bus to the memory space defined by this register
will cause one or more accesses to the S5320 external
nvRAM interface. Since PCI bus accesses to the ROM
may be 32 bits wide, repeated read operations to the
ROM are generated, and the wider data is assembled
internal to the S5320 controller. The data is then trans-
ferred to the PCI bus by the S5320. Only memory read
cycles should be performed to this location.
Expansion ROM Base Address
30h
Register Name:
Address Offset:
Power-up value:
Boot-load:
00000000h
External nvRAM offset 70h
bits 31:11, bit 0 Read/Write; bits 10:1
Read Only
Attribute:
Size:
32 bits
Figure 20. Expansion ROM Base Address Register
Bit
31
11 10
1
0
0
Value
0
Address Decode
Enable (RW)
0 = Disabled
1 = Enabled
Reserved (RO)
Programmable (R/W)
Bit
Description
31:11
Expansion ROM Base Address Location. These bits are used to position the decoded region in memory space.
Only bits which return a 1 after being written as 1 are usable for this purpose. These bits are individually enabled
by the contents sourced from the external boot memory (nvRAM). The desired size for the ROM memory is
determined by writing all ones to this register and then reading back the contents. The number of bits returned
as zeros, in order from least significant to most significant bit, indicates the size of the expansion ROM. This
controller limits the expansion ROM area to 2K bytes (due to the serial nvRAM’s limit of 11 bits of address). The
allowable returned values after all ones are written to this register are shown in Table 27.
10:1
0
Reserved. All zeros.
Address Decode Enable. The Expansion ROM address decoder is enabled or disabled with this bit. When this
bit is set, the decoder is enabled. When this bit is cleared, the decoder is disabled. It is required the PCI com-
mand register (PCICMD) also have the memory decode bit enabled for this bit to have any effect. In addition,
the corresponding bit must be set in the external nvRAM (see page 80, Table 38). If not set, the PCI host cannot
enable/disable this Address Decode bit.
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Table 27. Read Response to Expansion ROM Base Address Register (after all ones written)
Response
00000000h
FFFFF801h
Size in Bytes
none - disabled
nvRAM boot value
00000000h or BIOS missing 1
FFFFF801h
2K bytes (512 DWORDs)
1. The Expansion ROM Base Address Register nvRAM boot value is internally hardwired to FFFFF80Xh, where X = 000xb (i.e., only the least-
significant bit, or Address Decode Enable bit, is programmable). This defines both the minimum and maximum expansion ROM size sup-
ported by the S5320 (2K bytes). The Address Decode Enable bit in the nvRAM (the LSB) must be set to enable this region. If not set, a PCI
Configuration read of this region will always respond with 00000000h.
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Data Sheet
Interrupt Line Register (INTLN)
This register indicates the interrupt routing for the
S5320 controller. The ultimate value for this register is
system-architecture specific. For x86 based PCs, the
values in this register correspond with the established
interrupt numbers associated with the dual 8259 con-
trollers used in those machines. In x86-based PC
systems, the values of 0 to 15 correspond with the IRQ
numbers 0 through 15, and the values from 16 to 254
are reserved. The value of 255 (the controller’s default
power-up value) signifies either “unknown” or “no con-
nection” for the system interrupt. This register is boot-
loaded from the external boot memory or may be writ-
ten by the PCI interface.
Interrupt Line
Register Name:
Address Offset:
Power-up value:
Boot-load:
3Ch
FFh
External nvRAM offset 7Ch
Read/Write
Attribute:
8 bits
Size:
Figure 21. Interrupt Line Register
7
0
FFh
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Interrupt Pin Register (INTPIN)
This register identifies which PCI interrupt, if any, is
connected to the controller’s PCI interrupt pins. The
allowable values are 0 (no interrupts), 1 (INTA#), 2
(INTB#), 3 (INTC#), and 4 (INTD#). The default power-
up value assumes INTA#.
Interrupt Pin
Register Name:
Address Offset:
Power-up value:
Boot-load:
3Dh
01h
External nvRAM offset 7Dh
Read Only
Attribute:
8 bits
Size:
Figure 22. Interrupt Pin Register
Bit
7
3
2
1
0
Value
00h
X
X
X
Pin Number
000 None
001 INTA#
010 INTB#
011 INTC#
100 INTD#
101 Reserved
11X Reserved
Reserved
(All Zeros - RO)
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Data Sheet
Minimum Grant Register (MINGNT)
This register may be optionally used by bus masters to
specify how long a burst period the device needs. A
value of zero indicates that the bus master has no
stringent requirement. The units defined by the least
significant bit are in 250 ns increments. This register is
treated as “information only” since the S5320 is a PCI
target device only.
Minimum Grant
3Eh
Register Name:
Address Offset:
Power-up value:
Boot-load:
00h, hardwired
not used
Read Only
8 bits
Attribute:
Size:
Figure 23. Minimum Grant Register
Bit
7
0
Value
00h
Value x 250ns (RO)
00 - No Requirement
01 - FFh
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Maximum Latency Register (MAXLAT)
This register may be optionally used by bus masters to
specify how often this device needs PCI bus access. A
value of zero indicates that the bus master has no
stringent requirement. The units defined by the least
significant bit are in 250 ns increments. Since the
S5320 is a PCI target device only, this register is
treated as “information only” and has no further imple-
mentation within this device.
Maximum Latency
3Fh
Register Name:
Address Offset:
Power-up value:
Boot-load:
00h, hardwired
not used
Read Only
8 bits
Attribute:
Size:
Figure 24. Maximum Latency Register
Bit
7
0
Value
00h
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S5320 – PCI Match Maker: Operation Registers
OPERATION REGISTERS
Data Sheet
PCI BUS OPERATION REGISTERS
All S5320 control and communications are performed
through two register groups: PCI Operation Registers
Add-On Operation Registers. Some registers in both
groups are accessible from both buses. This chapter
describes the PCI Operation Register set first and then
the Add-On Operation Register set for easier under-
standing. An access to a register common to both
buses at the same time is not allowed. Unpredictable
behavior may occur.
The PCI bus operation registers are mapped as 6
DWORD registers located at the address space (I/O or
memory) specified by Base Address Register 0. These
locations are the primary method of communication
between the PCI and Add-On buses. It is NOT recom-
mended to read or write from an undefined address.
The read results and write effects cannot be guaran-
teed. Table 28 lists the PCI Bus Operation Registers.
Table 28. Operation Registers - PCI Bus
Address Offset
Abbreviation
OMB
Register Name
Outgoing Mailbox Register
0Ch
1Ch
34h
38h
3Ch
60h
IMB
Incoming Mailbox Register
MBEF
Mailbox Empty/Full Status Register
Interrupt Control/Status Register
Reset Control Register
INTCSR
RCR
PTCR
Pass-Thru Configuration Register
Note: Absolute register address locations are acquired by adding BADR0 to the “address offset” listed above.
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Data Sheet
PCI Outgoing Mailbox Register (OMB)
This DWORD register provides a method for sending
command or parameter data to the Add-On bus. PCI
bus transactions to this register may be of any width
(byte, word, or DWORD). Writing to this register can
be a source for Add-On bus interrupts by enabling
interrupt generation through the use of the Add-on’s
Interrupt Control/Status Register. This is also called
the Add-On Incoming Mailbox Register (AIMB). Read-
ing from this register will not affect interrupts or the
MBEF status register.
Outgoing Mailbox
0Ch
Register Names:
PCI Address Offset:
Power-up value:
PCI Attribute:
Size:
Undefined
Read/Write
32 bits
Figure 25. Outgoing Mailbox
31
24 23
16 15
8
7
0
Byte 3
Byte 2
Byte 1
Byte 0
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PCI Incoming Mailbox Register (IMB)
This DWORD register provides a method for receiving
user-defined status or parameter data from the Add-
On bus. PCI bus transactions to this register may be of
any width (byte, word, or DWORD). Only read opera-
tions are supported from this register. Reading from
this register can be a source for Add-On bus interrupt
by enabling interrupt generation through the use of the
Add-On Interrupt Control/Status Register. Byte 3 of
this mailbox can also be controlled via external hard-
ware from the Add-On bus. This register is also
referred to as the Add-On Outgoing Mailbox Register
AOMB).
Incoming Mailbox
1Ch
Register Names:
PCI Address Offset:
Power-up value:
PCI Attribute:
Size:
Undefined
Read Only
32 bits
Figure 26. Incoming Mailbox
31
24 23
16 15
8
7
0
Byte 3
Byte 2
Byte 1
Byte 0
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Data Sheet
PCI Mailbox Empty/full Status Register (MBEF)
This register provides empty/full visibility for each byte
within the mailboxes. The empty/full status for the PCI
Outgoing mailbox is displayed on bits 15 to 12 and the
empty/full status for the PCI Incoming mailbox is pre-
sented on bits 31 to 28. A value of 1 signifies that a
given mailbox has been written by one bus interface
but has not yet been read by the corresponding desti-
nation interface. The PCI bus incoming mailbox
transfers data from the Add-On bus to the PCI bus,
and the PCI outgoing mailbox transfers data from the
PCI bus to the Add-On bus. This register is also
referred to as the Add-On Mailbox Empty/Full Status
Register (AMBEF).
Mailbox Empty/Full Status
Register Name:
PCI Address Offset:
Power-up value:
PCI Attribute:
Size:
34h
00000000h
Read Only
32 bits
Figure 27. Mailbox Empty/Full Status Register (MBEF)
31
28 27
16 15
12 11
0
0000
0000
Reserved
Reserved
PCI Outgoing
Mailbox Status (RO)
PCI Incoming
Mailbox Status (RO)
Table 29. Mailbox Empty/Full Status Register
Bit
Description
31:28
PCI Incoming Mailbox Status. This field indicates which byte of the incoming mailbox register has been written
by the Add-On interface but has not been read by the PCI bus. Each bit location corresponds to a specific byte
within the incoming mailbox. A value of one for each bit signifies that the specified mailbox byte is full, and a
value of 0 signifies empty. The mapping of these status bits to bytes within the mailbox is as follows:
Bit 31 = Incoming mailbox byte 3
Bit 30 = Incoming mailbox byte 2
Bit 29 = Incoming mailbox byte 1
Bit 28 = Incoming mailbox byte 0
15:12
PCI Outgoing Mailbox Status. This field indicates which byte of the outgoing mailbox register has been written
by the PCI bus interface but has not yet been read by the Add-On bus. Each bit location corresponds to a spe-
cific byte within the outgoing mailbox. A value of one for each bit signifies that the specified mailbox byte is full,
and a value of 0 signifies empty. The mapping of these status bits to bytes is as follows:
Bit 15 = Outgoing mailbox byte 3
Bit 14 = Outgoing mailbox byte 2
Bit 13 = Outgoing mailbox byte 1
Bit 12 = Outgoing mailbox byte 0
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PCI Interrupt Control/Status Register (INTCSR)
This register configures the conditions which will pro-
duce an interrupt on the PCI bus interface, a method
for viewing the cause of the interrupt, and a method for
acknowledging (removing) the interrupt’s assertion.
Interrupt Control and Status
Register Name:
PCI Address Offset:
Power-up value:
PCI Attribute:
Size:
38h
Interrupt sources:
00000C0Ch
•
•
•
The Outgoing mailbox becomes empty.
The Incoming mailbox becomes full.
Add-On interrupt pin enable and flag.
Read/Write, Read/Write Clear
32 bits
Figure 28. Interrupt Control Status Register
Actual Interrupt
Interrupt Selection
3
1
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9
8 75
432
X 1
1
0
X X 0
0
0
0
X X 0
0
X X 1
1
XX
000
1
XX
00000000
Interrupt Asserted (RO)
Interrupt Source (R/W)
Enable & Selection
Add-On Interrupt Pin
(ADDINT#) Status (RO)
D4 - D0 PCI Outgoing Mailbox
(Becomes Empty)
D4 = Enable Interrupt
D1 - D0 = Byte Number
00 = Byte 0
Incoming Mailbox
Interrupt (R/WC)
Outgoing Mailbox
Interrupt (R/WC)
01 = Byte 1
D8 - D12 PCI Incoming Mailbox
D12 = Enable Interrupt
D9 - D8 = Byte Number
00 = Byte 0
10 = Byte 2
11 = Byte 3
Add-On Interrupt Pin
(ADDINT#) Enable
(R/W)
01 = Byte 1
10 = Byte 2
11 = Byte 3
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Table 30. Interrupt Control Status Register
Bit
31:24
23
Description
Reserved. Always zero.
Interrupt Asserted. This read only status bit indicates that one or more of the three possible interrupt conditions
are present. This bit is the OR of the mailbox interrupt conditions described by Bits 17 and 16, as well as the OR
of the Add-On interrupt described in Bit 22 (if the Add-On Interrupt is Enabled with Bit 13). No PCI interrupt is
generated, nor is this bit ever set, for an Add-On Interrupt without the Add-On Interrupt Enable set.
22
Add-On Interrupt. This bit is set when the ADDINT# input pin is driven low by an Add-On bus device. A high bit
indicates an Add-On device is requesting service. In addition, if the ADDINT# Enable bit is set, the S5320 will
assert a PCI interrupt (INTA# driven low). The source driving ADDINT# must deassert this input before the PCI
interrupt (INTA#) is driven to a false state. Host software must clear the Add-On interrupt source before exiting
its interrupt handler routine.
21:18
17
Reserved. Always zero.
PCI Incoming Mailbox Interrupt. This bit can be set when the mailbox is written by the Add-On interface. This bit
operates as read or write one clear. A write to this bit with the data of "one" will cause this bit to be reset; a write
to this bit with the data of ‘0’ will not change the state of this bit.
16
PCI Outgoing Mailbox Interrupt. This bit can be set when the mailbox is read by the Add-On interface. This bit
operates as read or write one clear. A write to this bit with the data of "one" will cause this bit to be reset; a write
to this bit with the data of ‘0’ will not change the state of this bit.
15:14
13
Reserved. Always zero.
ADDINT# Enable. If this bit is high, the S5320 will allow the Add-On interrupt request to drive the INTA# pin. It
has no effect on the assertion of the Add-On Interrupt Bit 22.
12
Enable Incoming Mailbox interrupt. This bit allows a write from the incoming mailbox register byte identified by
bits 9 and 8 to produce a PCI interface interrupt. This bit is read/write.
11:10
9:8
Hardwired to 1. Reserved.
Incoming Mailbox Byte Interrupt Select. This field selects which byte of the mailbox is to actually cause the inter-
rupt. [00]b selects byte 0, [01]b selects byte 1, [10]b selects byte 2, and [11]b selects byte 3. This field is read/
write.
7:5
4
Reserved. Always zero.
Enable Outgoing Mailbox Interrupt. This bit allows a read by the Add-On of the outgoing mailbox register byte
identified by bits 1 and 0 to produce a PCI interface interrupt. This bit is read/write.
3:2
1:0
Hardwired to 1. Reserved.
Outgoing Mailbox Byte Interrupt Select. This field selects which byte of the mailbox is to actually cause the inter-
rupt. [00]b selects byte 0, [01]b selects byte 1, [10]b selects byte 2, and [11]b selects byte 3. This field is read/
write.
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PCI Reset Control Register (RCR)
This register provides a method to perform software
resets. It will also control nvRAM accesses. The fol-
lowing controls are available:
Reset Control Register
Register Name:
•
•
•
•
Assert reset to Add-On
PCI Address
Offset:
3Ch
Reset mailbox empty full status flags
Write/Read external non-volatile memory
Reset Pass-Thru Read FIFO
00000000h
Power-up value:
Attribute:
Size:
Read/Write, Read Only, Write
Only
32 bits
Figure 29. FIFO Control/Status Register
2
8
2
7
2
6
2
5
2
4
31
29
23
16 15
0
0
0 0 0 0 0 0 0 0 0 0 0
nvRAM Operation
Address/Data (R/W)
Add-On Reset (R/W)
Read FIFO Reset (WO)
Mailbox Flags Reset (WO)
nvRAM Access Failed (RO)
nvRAM Access Control
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Table 31. Reset Control Register
Bit
Description
31:29
nvRAM Access Control. This field provides a method for access to the optional external non-volatile memory.
Write operations are achieved by a sequence of byte operations involving these bits and the 8-bit field of bits 23
through 16. The sequence requires that the low-order address, high-order address, and then a data byte are
loaded in order. Bit 31 of this field acts as a combined enable and ready for the access to the external memory.
D31 must be written to a 1 before an access can begin, and subsequent accesses must wait for bit D31 to
become 0 (ready).
D31 D30 D29 W/R
0
1
1
1
1
0
1
X
0
0
1
1
X
X
X
0
1
0
1
X
X
W
W
W
W
W
R
Inactive
Load low address byte
Load high address byte
Begin write
Begin read
Ready
R
Busy
Cautionary note: The nonvolatile memory interface is also available for access by the Add-On interface. While
simultaneous accesses to the nv memory by both the Add-On and PCI are supported (via arbitration logic), soft-
ware must be designed to prevent the possibility of data corruption within the memory and to provide for accu-
rate data retrieval.
28
27
nvRAM Access Failed. Indicate the last nvRAM access failed. This flag is cleared automatically upon the start of
the next read/write operation.
Mailbox Flag Reset. Writing a one to this bit causes all mailbox status flags to become reset (EMPTY). It is not
necessary to write this bit to 0 afterwards because it is used internally to produce a reset pulse. Since reading
this bit will always return a 0, this bit is write only.
26
25
Reserved. Always zero.
Read FIFO Reset. Writing a one to this bit causes the read FIFO to reset (empty). It is not necessary to write a 0
to this bit. This bit is write only. This feature is intended for test only. However, it can be used during operation if
several PCI idle cycles are inserted following the assertion of this command.
24
Add-On Pin Reset. Writing a one to this bit causes the reset output pin to become active (SYSRST#). Clearing
this bit is necessary in order to remove the assertion of reset. This bit is read/write.
23:16
Non-volatile Memory Address/Data Port. This 8-bit field is used in conjunction with bits 31, 30 and 29 of this reg-
ister to access the external non-volatile memory. The contents written are either low address, high address, or
data as defined by bits 30 and 29. This register will contain the external non-volatile memory data when the
proper read sequence for bits 31 through 29 is performed.
15:0
Reserved. Always zero.
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PCI Pass-Thru Configuration Register (PTCR)
This register controls the configuration for Pass-Thru
Regions 1-4:
Pass-Thru Configuration Register
Register Name:
PCI Address Offset:
Power-up value:
PCI Attribute:
Size:
Byte 0 Controls Pass-Thru Region 1
Byte 1 Controls Pass-Thru Region 2
Byte 2 Controls Pass-Thru Region 3
Byte 3 Controls Pass-Thru Region 4
60h
80808080h
Read/Write
32 bits
IMPORTANT NOTE: This register (PTCR) is physi-
cally the same as the Add-On Pass-Thru
Configuration Register (APTCR). It is intended that
either the PCI system or local Add-On interface will
write to this register, but not both. However, in the
event that both the PCI and Add-On must write to this
register, whichever side wrote last will update its value.
Also, Pass-Thru operation cannot be guaranteed if this
register is updated while a Pass-Thru operation is
already in progress.
Figure 30. Pass-Thru Configuration Register
31
24 23
16 15
8 7
0
Region 4
Region 3
Region 2
Region 1
Active Mode Wait States
D2 D1 D0
D7 Pass-Thru Mode
0 - PTADR# Not Driven
1 - PTADR# Driven
000 - 0 Wait States
001 - 1 Wait States
010 - 2 Wait States
011 - 3 Wait States
100 - 4 Wait States
101 - 5 Wait States
110 - 6 Wait States
111 - 7 Wait States
D6 Endian Conversion
0 - No Conversion
1 - Big Endian Conversion
D5 Write FIFO
0 - Enabled
1 - Disabled
Prefetch
D4 D3
00 - Disabled
01 - Small
10 - Medium
11 - Large
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Data Sheet
Table 32 describes one of the four configuration registers. All four region configuration registers are exactly the
same.
Table 32. Pass-Thru Configuration Register
Bit
Description
7
PTADR# mode. This bit is only valid in Active mode. If this bit is 0, PTADR# is not driven at the beginning of an
active cycle. If this bit is set to 1 (default state), the S5320 will assert PTADR# for one clock cycle after PTATN#
is asserted. The Pass-Thru address is also driven while PTADR# is low. This bit is a don’t care if the device is
operating in Passive mode.
6
5
Endian conversion. If this bit is set to one, the S5320 will convert the Add-On bus from the default little endian
format to a big endian format. Reference Chapter 9 for more details.
Write FIFO disabled. If this bit is set to 1, the S5320 will not accept the next piece of data (on a PCI write) until
the Add-On has accepted the previous piece of data. If this bit is set to 0, the S5320 will accept data from the
PCI until the Pass-Thru write FIFO is full.
4:3
2:0
Prefetch. These bits control the number of DWORDs the S5320 will prefetch after the current PCI Pass-Thru
read completes. The actual amount of data prefetched depends upon any number of different scenarios. The
prefetch values of “small”, “medium” and “large” are available to tune the system to achieve best overall perfor-
mance (i.e., optimize PCI bus transfers or optimize Add-On bus transfers). The Pass-Thru read FIFO can be
enabled to prefetch in either Active mode or Passive mode.
Wait states. In Active mode, the user can program the number of wait states required by the Add-On bus to com-
plete a transaction. Up to 7 wait states can be programmed (per region). The S5320 will count the number of
clocks programmed into this register before finishing the current data transaction if PTWAIT# is high. If
PTWAIT# is driven low, additional wait states may be inserted. Bits 2, 1 and 0 are don’t care if operating in Pas-
sive mode.
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ADD-ON BUS OPERATION REGISTERS
Data Sheet
This register group represents the primary method for
communication between the Add-On and PCI buses
as viewed by the Add-On. The flexibility of this
arrangement allows a number of user-defined soft-
ware protocols to be built. One should NOT read/write
from any undefined address, or the read results and
write effects cannot be guaranteed. Table 33 lists the
Add-On Bus Operation Registers.
The Add-On bus interface provides access to 8
DWORDs of data, control and status information. All of
these locations are accessed by asserting the Add-On
bus chip select pin (SELECT#) and the byte-enable
pins (BE[3:0]), in conjunction with either the read or
write control enables (signal pin RD# or WR#). All reg-
isters are accessed with signals synchronous to the
Add-On clock.
Table 33. Operation Registers - Add-On Interface
Address
0Ch
1Ch
28h
Abbreviation
AIMB
Register Name
Add-On Incoming Mailbox Register
AOMB
APTA
Add-On Outgoing Mailbox Register
Add-On Pass-Thru Address Register
Add-On Pass-Thru Data Register
2Ch
34h
APTD
AMBEF
AINT
Add-On Mailbox Empty/Full Status Register
Add-On Interrupt Control/Status Register
Add-On Reset Control Register
38h
3Ch
60h
ARCR
APTCR
Add-On Pass-Thru Configuration Register
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Data Sheet
Add-On Incoming Mailbox Register (AIMB)
This DWORD register provides a method for receiving user-defined status or
parameter data from the PCI system. Add-On bus read operations to this register
may be of any width (byte, word, or DWORD). Only read operations are sup-
ported. Reading from this register can optionally cause a PCI bus interrupt (if
desired) by enabling interrupt generation through the use of the PCI’s Interrupt
Control/Status Register. This register is also referred to as the PCI Outgoing Mail-
box Register.
Incoming Mailbox
0Ch
Register Names:
Add-On Address:
Power-up value:
Add-On Attribute:
Size:
XXXXXXXXh
Read Only
32 bits
Add-On Outgoing Mailbox Register (AOMB)
This DWORD register provides a method for sending command or parameter
Outgoing Mailbox
1Ch
Register Names:
Add-On Address:
Power-up value:
Add-On Attribute:
Size:
data to the PCI interface. Add-On bus operations to this register may be of any
width (byte, word, or DWORD). Writing to this register can be a source for PCI
bus interrupts (if desired) by enabling interrupt generation through the use of the
PCI’s Interrupt Control/Status Register. This is also called the PCI Incoming Mail-
box Register (IMB). Byte 3 of this mailbox can also be controlled via the external
mailbox port. Reading from this register will not affect interrupts or the AMBEF
Status Register. (OMB).
XXXXXXXXh
Read/Write
32 bits
Add-On Pass-Thru Address Register (APTA)
This register stores the address of any active Pass-Thru PCI bus cycle
that has been accepted by the S5320. When one of the base address
decode registers 1-4 encounters a PCI bus cycle which selects the
region defined by it, this register stores that current cycle’s active
address. This address is incremented after every 32-bit Pass-Thru data
transfer.
Add-On Pass-Thru Address
Register Name:
Add-On Address:
Power-up value:
Add-On Attribute:
Size:
28h
XXXXXXXXh
Read Only
32 bits
Add-On Pass-Thru Data Register (APTD)
This register, along with APTA register, is used to perform Pass-Thru trans-
fers. When one of the base address decode registers 1-4 encounters a PCI
bus cycle which selects the region defined by it, the APTA register will con-
tain that current cycle’s active address and the APTD will contain the data
(PCI bus writes) or must be written with data (PCI bus reads). Wait states
are generated on the PCI bus until this register is read (PCI bus writes) or
this register is written (PCI bus reads) when in Passive mode.
Add-On Pass-Thru Data
2Ch
Register Name:
Add-On Address:
Power-up value:
Add-On Attribute:
Size:
XXXXXXXXh
Read/Write
32 bits
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Add-On Mailbox Empty/full Status Register
(AMBEF)
This register provides empty/full visibility for each byte
within the mailboxes. The empty/full status for the
Add-On Incoming mailbox is displayed on bits 15 to 12
and the empty/full status for the Add-On Out-going
mailbox is presented on bits 31 to 28. A value of 1 sig-
nifies that a given mailbox has been written by one bus
interface but has not yet been read by the correspond-
ing destination interface. The Add-On bus incoming
mailbox is used to transfer data from the PCI bus to
the Add-On bus, and the Add-On outgoing mailbox is
used to transfer data from the Add-On bus to the PCI
bus. This register is also referred to as the PCI Mail-
box Empty/Full Status Register (MBEF).
Mailbox Empty/Full Status
Register Name:
Add-On Address:
Power-up value:
Add-On Attribute:
Size:
34h
00000000h
Read Only
32 bits
Figure 31. Mailbox Empty/Full Status Register
31
28 27
16 15
12 11
0
0000
0000
Reserved
Reserved
Add-On Incoming Mailbox Status
(RO)
Add-On Outgoing Mailbox Status
(RO)
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Data Sheet
Table 34. Mailbox Empty/Full Status Register
Bit
Description
31:28
Add-On Outgoing Mailbox Status. This field indicates which byte of the outgoing mailbox register has been writ-
ten by the Add-On interface but has not yet been read by the PCI bus. Each bit location corresponds to a spe-
cific byte within the outgoing mailbox. A value of 1 for each bit signifies that the specified mailbox byte is full, and
a value of 0 signifies empty. The mapping of these status bits to bytes within the mailbox is as follows:
Bit 31 = Outgoing mailbox byte 3
Bit 30 = Outgoing mailbox byte 2
Bit 29 = Outgoing mailbox byte 1
Bit 28 = Outgoing mailbox byte 0
15:12
Add-On Incoming Mailbox Status. This field indicates which byte of the incoming mailbox register has been writ-
ten by the PCI bus interface but has not yet been read by the Add-On bus. Each bit location corresponds to a
specific byte within the incoming mailbox. A value of 1 for each bit signifies that the specified mailbox byte is full,
and a value of 0 signifies empty. The mapping of these status bits to bytes is as follows:
Bit 15 = Incoming mailbox byte 3
Bit 14 = Incoming mailbox byte 2
Bit 13 = Incoming mailbox byte 1
Bit 12 = Incoming mailbox byte 0
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Data Sheet
Add-On Interrupt Control/status Register (AINT)
This register provides the method for choosing which
conditions are to produce an interrupt on the Add-On
bus interface, a method for viewing the cause for the
interrupt, and a method for acknowledging (removing)
the interrupt’s assertion.
Add-On Interrupt Control and Status
Register Name:
Add-On Address:
Power-up value:
Attribute:
38h
00000C0Ch
Interrupt sources:
•
•
•
Incoming mailbox becomes full
Outgoing mailbox becomes empty
Built-in self test issued
Read/Write, Read/Write Clear
32 bits
Size:
Figure 32. Add-On Interrupt Control Status Register
Interrupt Status
Interrupt Selection
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
31
24
8
4 3 2
1
0
X 0
0
X 0
0
X X 0
0
0
1
1
XX
0 0 0 X 1
XX
0 0 0 0
Add-On IMB
(Becomes full)
R/W
D4 = Enable Interrupt
D1 - D0 = Byte Number
00 = Byte 0
01 = Byte 1
10 = Byte 2
11 = Byte 3
Interrupt Asserted (RO)
BIST (R/WC)
Outgoing Mailbox
Interrupt (R/WC)
Add-On OMB (Becomes Empty)
R/W
D12 = Enable Interrupt
D9 - D8 = Byte Number
00 = Byte 0
Incoming Mailbox
Interrupt (R/WC)
01 = Byte 1
10 = Byte 2
11 = Byte 3
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Data Sheet
Table 35. Interrupt Control Status Register
Bit
31:24
23
Description
Reserved. Always zero.
Interrupt Asserted. This read-only status bit indicates that one or more interrupt conditions are present. This bit
is the OR of the interrupt sources described by bits 20, 17 and 16 of this register.
22:21
20
Reserved. Always zero.
BIST. Built-In Self-Test Interrupt. This interrupt occurs when a self test is initiated by the PCI interface by writing
to the PCI configuration register BIST. This bit will stay set until cleared by writing a 1 to this location. Self test
completion codes may be passed to the PCI BIST register by writing to the ARCR register.
19:18
17
Reserved. Always zero.
Outgoing Mailbox Interrupt. This bit can be set when the mailbox is read by the PCI interface. This bit operates
as read or write 1 clear. A write with the data as 1 will cause this bit to be reset; a write with the data as 0 will not
change the state of this bit.
16
Incoming Mailbox Interrupt. This bit can be set when the mailbox is written by the PCI interface. This bit oper-
ates as read or write 1 clear. A write with the data as 1 will cause this bit to be reset; a write with the data as 0
will not change the state of this bit.
15:13
12
Reserved. Always zero.
Enable Outgoing Mailbox Interrupt. This bit allows a PCI read of the outgoing mailbox register to produce an
Add-On interrupt. This bit is read/write.
11:10
9:8
Hardwired to 11.
Outgoing Mailbox Byte Interrupt Select. This field selects which byte of the mailbox is to cause the interrupt.
[00]b selects byte 0, [01]b selects byte 1, [10]b selects byte 2, and [11]b selects byte 3. This field is read/write.
7:5
4
Reserved. Always zero.
Enable Incoming Mailbox Interrupt. This bit allows a write from the PCI bus to the incoming mailbox register to
produce an Add-On interrupt. This bit is read/write.
3:2
1:0
Hardwired to 1.
Incoming Mailbox Byte Interrupt Select. This field selects which byte of the mailbox is to cause the interrupt. 00b
selects byte 0, 01b selects byte 2, and 11b selects byte 3. This field is read/write.
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Data Sheet
Add-On Reset Control Register (ARCR)
This register provides a method to perform software
resets and nvRAM accesses. The following Add-On
controls are provided:
Add-On Reset Control and Status
Register Name:
Add-On Address:
Power-up value:
Attribute:
•
•
•
Reset mailbox empty full status flags
Reset Pass-Thru read FIFO
3Ch
00h
Read/Write external non-volatile memory
Read/Write, Read Only, Write Only
32 bits
Size:
Figure 33. Add-On General Control/Status Register
2
8
2
7
2
6
2
5
2
4
1
1
31
29
23
16 15 12 10
0
Reserved
BIST Condition Code (R/W)
nvRAM Operation
Address/Data (R/W)
Read FIFO Reset (WO)
Mailbox Flags Reset (WO)
nvRAM Access Failed
(RO)
nvRAM Access Control
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Table 36. Reset General Control/Status Register
Bit
Description
31:29
nvRAM Access Control. This field provides a method for access to the optional external non-volatile memory.
Write operations are achieved by a sequence of byte operations involving these bits and the 8-bit field of bits 23
through 16. The sequence requires that the low-order address, high-order address, and then a data byte are
loaded in order. Bit 31 of this field acts as a combined enable and ready for the access to the external memory.
D31 must be set to a 1 before an access can begin, and subsequent accesses must wait for bit D31 to become
0 (ready).
D31 D30 D29 W/R
0
1
1
1
1
0
1
X
0
0
1
1
X
X
X
0
1
0
1
X
X
W
W
W
W
W
R
Inactive
Load low address byte
Load high address
Begin write
Begin read
Ready
R
Busy
Cautionary note: The non-volatile memory interface is also available for access by the Add-On interface. While
simultaneous accesses to the nv memory by both the Add-On and PCI are supported, via arbitration logic, soft-
ware must be designed to prevent the possibility of data corruption within the memory and to provide for accu-
rate data retrieval.
28
27
nvRAM Access Failed. It will indicate that the last nvRAM access has failed. This flag is cleared automatically
upon the start of the next read/write operation.
Mailbox Flag Reset. Writing a one to this bit causes all mailbox status flags to become reset (EMPTY). It is not
necessary to write this bit to 0 afterwards because it is used internally to produce a reset pulse. Since reading
this bit will always return a 0, this bit is write only.
26
25
Reserved. Always zero.
Read FIFO Reset. Writing a one to this bit causes the read FIFO to reset (empty). It is not necessary to write a 0
to this bit. This bit is write only. This feature is intended for test only. It can only be asserted when the PCI is not
performing any Pass-Thru accesses.
24
Reserved. Always zero.
23:16
Non-volatile Memory Address/Data Port. This 8-bit field is used in conjunction with bits 31, 30 and 29 of this reg-
ister to access the external non-volatile memory. The contents written are either low address, high address, or
data as defined by bits 30 and 29. This register will contain the external non-volatile memory data when the
proper read sequence for bits 31 through 29 is performed.
15:12
11:0
BIST Condition Code. This field is directly connected to the PCI configuration self-test register. Bit 15 through 12
maps with the BIST register bits 3 through 0, respectively.
Reserved. Always zero.
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Data Sheet
Add-On Pass-thru Configuration Register (APTCR)
This register controls the configuration for Pass-Thru
Regions 1-4.
Pass-Thru Configuration Register
Register Name:
Add-On Address:
Power-up value:
Add-On Attribute:
Size:
Byte 0 Controls Pass-Thru Region 1
Byte 1 Controls Pass-Thru Region 2
Byte 2 Controls Pass-Thru Region 3
Byte 3 Controls Pass-Thru Region 4
60h
80808080h
Read/Write
32 bits
IMPORTANT NOTE: This register (APTCR) is physi-
cally the same as the PCI Pass-Thru configuration
register (PTCR). It is intended that either the PCI sys-
tem or local Add-On interface will write to this register,
but not both. However, in the event that both the PCI
and Add-On write to this register, whichever side wrote
last wins. This register is also intended to be initialized
once, prior to any PCI bus operations. Pass-Thru
operation cannot be guaranteed if this register is
updated while a Pass-Thru transaction is being
performed.
Figure 34. Pass-Thru Configuration Register
31
24 23
16 15
8 7
0
Region 4
Region 3
Region 2
Region 1
Active Mode Wait States
D2 D1 D0
D7 Pass-Thru Mode
0 - PTADR# Not Driven
1 - PTADR# Driven
000 - 0 Wait States
001 - 1 Wait States
010 - 2 Wait States
011 - 3 Wait States
100 - 4 Wait States
101 - 5 Wait States
110 - 6 Wait States
111 - 7 Wait States
D6 Endian Conversion
0 - No Conversion
1 - Big Endian Conversion
D5 Write FIFO
0 - Enabled
1 - Disabled
Prefetch
D4 D3
00 - Disabled
01 - Small
10 - Medium
11 - Large
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Data Sheet
The following describes one of the four configuration registers. All four region configuration registers are exactly
the same.
Table 37. Pass-thru Configuration Register
Bit
Description
7
PTADR# mode. This bit is only valid in Active mode. If this bit is 0, PTADR# is not driven at the beginning of a
Active cycle. If this bit is set to 1 (default state), the S5320 will assert PTADR# for one clock cycle after PTATN#
is asserted. The Pass-Thru address is also driven while PTADR# is low. This bit is a don’t care if the device is
operating in Passive mode
6
5
Endian conversion. If this bit is set to one, the S5320 will convert the Add-On bus from the default little endian
format to a big endian format.
Write FIFO disabled. If this bit is set to 1, the S5320 will not accept the next piece of data (on a PCI write) until
the Add-On has accepted the previous piece of data. If this bit is set to 0, the S5320 will accept data from the
PCI until the Pass-Thru write FIFO is full.
4:3
2:0
Prefetch. These bits control the number of DWORDs that the S5320 will prefetch after the current PCI Pass-
Thru read completes. The actual amount of data prefetched depends upon any number of different scenarios.
The prefetch values of “small”, “medium” and “large” are available to tune the system to achieve best overall
performance (i.e. optimize PCI bus transfers or optimize Add-On bus transfers). The Pass-Thru read FIFO can
be enabled to prefetch in either Active mode or Passive mode.
Wait states. In Active mode, the user can program the number of wait states required by the Add-On bus to com-
plete a transaction. Up to 7 wait states can be programmed (per region). The S5320 will count the number of
clocks programmed into this register before finishing the current data transaction if PTRDY# is high. If PTRDY#
is driven low, additional wait states may be inserted. Bits 2, 1 and 0 are don’t care if operating in Passive mode.
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S5320 – PCI Match Maker: Initialization
INITIALIZATION
Data Sheet
LOADING THE SERIAL NV MEMORY
All PCI bus agents and bridges are required to imple-
ment PCI Configuration Registers. When multiple PCI
devices are present, these registers must be unique to
each device in the system. The specified PCI proce-
dure for uniquely selecting a device’s configuration
space involves a dedicated signal, called IDSEL, con-
nected to each motherboard PCI bus device and PCI
slot.
Serial nv memory data transfers are performed
through a two-wire, bi-directional data transfer protocol
as defined by commercial serial EEPROM offerings.
These devices have the advantages of low pin counts,
small package size, and economical price.
A serial nv memory is initially considered valid if the
first serial accesses contain the correct per-byte
acknowledgments (see Figure 39. If the serial per-byte
acknowledgment is not observed, the S5320 deter-
mines that no external serial nv memory is present
and the AMCC default Configuration Register values
specified in the PCI Configuration Register Chapter
are used. Please note that the Pass-Thru interface will
not operate unless a valid nv memory has been read.
After reset, the host executes configuration cycles to
each device on the PCI bus. The configuration regis-
ters provide information on PCI agent operation and
memory or I/O space requirements. These allow the
PCI BIOS to enable the device and locate it within sys-
tem memory or I/O space.
After a PCI reset, the S5320 can be configured for a
specific application by downloading device setup infor-
mation from an external non-volatile memory into the
device Configuration Registers. In order to use the
Pass-Thru regions, the S5320 must be used with an
external nvRAM boot device If no nvRAM is used, the
Base-Address Regions are disabled. However, the
mailboxes and other PCI/Add-on Operation Registers
can still be used (as Base-Address Region #0 comes
up in its default state, defining a 128-byte I/O region).
The serial nvRAM is first accessed at location 0040h
followed by a read to location 0041h. If either of these
accesses contain anything other than FFh, the next
four accesses are to locations 0050h, 0051h, 0052h
and 0053h. At these locations, the data must be 80h
(or 81h or 82h), FFh, E8h, and 10h, respectively, for
the external nv memory to be considered valid. Once a
valid external nv memory has been recognized, it is
read, sequentially from location 040h to 07Fh. The
data is loaded into the appropriate PCI configuration
register. Some of the boot device data is not down-
loaded into the Configuration Registers, but is used
instead to initialize some S5320 modes of operation
(location 0045h, for instance). Upon completion of this
sequence, the boot load terminates and PCI configu-
ration accesses to the S5320 are acknowledged with
the PCI Target Ready (TRDY#) output.
To configure the S5320, 64 bytes of setup information
are required. The rest of the boot device can be used
to implement an expansion BIOS, if desired. Some of
the setup information is used to initialize the S5320
PCI Configuration Registers, while other information is
used to define S5320 special operating modes.
PCI RESET
Table 38 lists the required nv memory contents for a
valid configuration nv memory device.
Immediately following the assertion of the PCI RST#
signal, the Add-On reset output SYSRST# is asserted.
The Add-On reset output (SYSRST#) can be used to
initialize external state machines, reset Add-On micro-
processors, or other Add-On logic devices.
Two pins are used to transfer data between the S5320
PCI controller and the external serial memory: a serial
clock pin, SCL, and a serial data pin, SDA. The serial
clock pin is an open drain output from the S5320, and
the serial data pin is open drain bi-directional. The
serial clock is derived by dividing the PCI bus clock by
293. This means the frequency of the serial clock is
approximately 114 KHz for a 33 MHz PCI bus clock.
All S5320 Operation Registers and Configuration Reg-
isters are initialized to their default states at reset. The
default values for the Configuration Registers will be
overwritten by the contents of the external nv boot
memory during device initialization. Configuration
accesses by the host CPU while the S5320 is loading
configuration will produce PCI bus retries until one of
the following events occurs:
Note in Figure 35, a 4.7k pull-up is required on the
SDA and SCL lines. During boot-up, the S5320 will
only communicate with an EEPROM that has its
address pins set to 0 (A[2:0] = “000). When not
accessing the external nvRAM, the S5320 will tri-state
the SCL and SDA signals so other two-wire serial
devices can use the bus. The system designer must
guarantee that the two-wire serial bus is idle whenever
the S5320 wants to start an access. The S5320 does
•
The S5320 identifies that there is no valid boot
memory (and default Configuration Register
values are used).
•
The S5320 finishes downloading all configura-
tion information from a valid boot memory.
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Data Sheet
NOT perform two-wire serial arbitration. It assumes
that it is the only master on the bus.
of the S5320, this corresponds to one byte of data
transferred approximately every 0.25 milliseconds.
Read accesses can be either random or sequential.
During boot-up, all accesses from address 40h to 7Fh
are sequential. As a result, it is important the nvRAM
used supports the nvRAM sequential read accesses
as indicated in Figure 40. Figure 39 shows the
sequence for a random byte read.
Communications with the serial memory involve sev-
eral clock transitions. A start event signals the
beginning of a transaction and is immediately followed
by an address transfer. Each address/data transfer
consists of 8 bits of information followed by a 1-bit
acknowledgment. When the exchange is complete, a
stop event is issued. Figure 36 shows the unique rela-
tionship defining both a start and stop event. Figure 37
shows the required timing for address/data with
respect to the serial clock.
To initialize the S5320 controller’s PCI Configuration
Registers, the smallest serial device necessary is a
128 x 8 organization. Although the S5320 controller
only requires 64 bytes, these configuration bytes must
begin at the 64-byte address offset (40h through 7Fh).
This offset constraint permits the configuration image
to be shared with a memory containing expansion
BIOS code and the necessary preamble to identify an
expansion BIOS. The largest serial device which can
be used is 2 Kbytes.
For random accesses, the sequence involves one
clock to define the start of the sequence, eight clocks
to send the slave address and read/write command,
followed by a one-clock acknowledge, and so on. Fig-
ure 38 shows the sequence for a random write access
requiring 29 serial clock transitions. At the clock speed
Table 38. Valid External Boot Memory Contents
Address
Data
Notes
0040h-0041h
not FFFFh
This is the location that the S5320 will load a customized vendor ID. (FFFFh is an
illegal vendor ID.)
0050h
82h - registers to I/O
81h - memory space
80h - memory below
1 Mbytes
This is the least significant byte of the region which initializes the S5320 configura-
tion register BADR0. A value of 81h assigns the 32 DWORD locations of the PCI
operations registers into I/O space, a value of 80h defines memory space, and a
value of 82h defines memory space below 1 Mbytes.
0051h
0052h
0053h
FFh
E8h
10h
Required
Required
Required
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Data Sheet
Figure 35. S5320 to nvRAM Interface
Vcc
4.7K
S5320
Vcc
SCL
4.7K
SDA
24C02 256x8
24C04 512x8
24C08 1Kx8
24C16 2K8
Serial
nvRAM
A0
A1
A2
Figure 36. Serial Interface Definition of Start and Stop
SCL
SDA
START BIT
STOP BIT
Figure 37. Serial Interface Clock Data Relationship
SCL
SDA
DATA STABLE
DATA CHANGE DATA STABLE
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Figure 38. Serial Interface Byte Access-Write
S
T
A
R
T
R/W
S
T
O
P
SLAVE
ADDRESS
WORD
ADDRESS
DATA
1 0 1 0
0
A
C
K
A
C
K
A
C
K
Figure 39. Serial Interface Byte Access-Read
S
S
T
A
R
T
R/W
R/W
S
T
O
P
WOR
T
A
R
T
SLAVE
ADDRESS
SLAVE
ADDRESS
DAT
A
D
ADDRESS
1 0 1 0
0
1 0 1 0
1
A
C
K
A
C
K
A
C
K
A
C
K
Figure 40. Serial Byte Access- Sequential Read
S
T
O
P
Slave Address Word Address Slave Address
Data
Data
.......
Data
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NON-VOLATILE MEMORY INTERFACE
Data Sheet
the PCI address. For example, if the EXROM Base
Address is programmed with 100000h, and the PCI
performs a read to address 100040h, this will initiate a
read from address 40h of the nvRAM. Once addresses
40h, 41h, 42h and 43h have been read and stored in
the nvRAM interface, the S5320 is ready to provide
the data to the original PCI device requesting the data.
Once the original master comes back to read the data
(which it should, as it received a Retry to its initial
read), it will get a TRDY# along with the 4 bytes of
data that were read from the nvRAM. If the master
comes back to retry the read, but the nvRAM interface
is not finished with its accesses, the master will again
be greeted with a Retry. If a master attempts to read
from a different EXROM address, it will also be
greeted with a Retry. Only a read with the original
address (in our example, a read to address 100040h)
will allow the transaction to complete. As a result, if the
original master never comes back to Retry the read,
the EXROM interface will be hung. Only other EXROM
accesses will be hung, as the nvRAM interface will still
be operational via the PCI’s RCR and the Add-On’s
ARCR.
The nv memory, can be accessed through the PCI
interface or the Add-On interface. Accesses to the nv
memory from the PCI interface are through the Reset
Control Register (RCR). Accesses to the nv memory
from the Add-On interface are through the Add-On
Reset Control Register (ARCR).
Some nv memories can contain Expansion ROM BIOS
code for use by the host CPU. During initialization, the
Expansion BIOS is located within system memory. The
starting location of the nv memory is stored in the
Expansion ROM Base Address Register in the S5320
PCI Configuration Registers. A PCI read from this
region results in the S5320 performing four consecu-
tive byte-wide access to the nv memory device, thus
assembling a complete DWORD. Writes to the nv
memory are not allowed through the expansion ROM
base address region. Any attempt to do so will result in
data being accepted by the S5320, but simply
discarded.
In the RCR and ARCR registers, bits D31:29 are com-
mand/status bits and bits D23:16 are address/data
bits. These operation registers occupy the same offset
(3Ch-3Fh) on their respective interfaces (Add-On or
PCI). The sequence used to access the nv memory is
the same in either case.
Accesses to the nvRAM via the PCI’s Reset Control
Register (RCR) are a bit more involved for the pro-
grammer. There are 12 bits of this register that perform
both reads and writes. Bits 23-16 to provide Address/
Data information, bits 31-29 are used to provide con-
trol information, and bit 28 indicates whether the
nvRAM access was successful or not. The control bits
31-29 are assigned as follows (where W/R indicates
the type of PCI access to the RCR):
nvRAM READ/WRITE DESCRIPTION
There are four different mechanisms to access the
external nvRAM:
1. During boot-up (RST# deasserted), the S5320
will automatically read out the nvRAM addresses
40h - 7Fh.
D31 D30 D29 W/R nvRAM Interface Function
0
1
1
1
1
0
1
X
0
0
1
1
X
X
X
0
1
0
1
X
X
W
W
W
W
W
R
Inactive
2. Via the PCI Configuration Expansion ROM Base
Address Register (EXROM). This is READ-ONLY.
Load low address byte
Load high address byte
Begin write
3. Via the PCI Reset Control Register (RCR). This is
READ/WRITE.
Begin read
Ready
4. Via the Add-On Reset Control Register (ARCR).
This is READ/WRITE.
R
Busy
The boot-up sequence is a built-in function, and is
affected by the contents of the nvRAM. The Expansion
ROM Base Address Register is used if expansion
BIOS is stored in the external nvRAM. This register
can be enabled for a 2K memory size, and is mapped
to access the contents of the nvRAM. When a read is
performed to an address in the range of the EXROM
base address, a read sequence is started to the
nvRAM. As this sequence is extremely slow, the PCI
will be greeted with a Retry. Mean-while, the nvRAM
interface circuitry will be performing four sequential
byte accesses to the nvRAM at the offset indicated by
These control bits are used along with the Address/
Data bits 23-16 to configure the type of nvRAM opera-
tion (read or write), the address being accessed, and a
place to store the write data or the data read from the
nvRAM. One can interface with this register in either
byte-wide or word-wide fashion. For a word-wide
access, the command (bits 31-29) and Address/Data
(bits 23-16) are written to the RCR with one PCI write.
For a byte-wide access, the command (bits 31-29) is
written first, followed by the Address/Data (bits 23-16).
This takes two PCI transfers.
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When performing a byte-wide RCR access, users
need to write the command indicating how the data is
to be used, followed by the data. These commands will
assert the internal signals LOAD_LOW_ADDR,
LOAD_HIGH_ADDR or LOAD_WR_DATA. Only one
signal is asserted at any time: once one is asserted,
the others are deasserted.
5. Write to RCR(23:16) with the high address byte.
Since signal LOAD_HIGH_ADDR is asserted, the
data
will
be
written
to
register
NVRAM_HIGH_ADDR. Note that as the nvRAM
address is limited to 11 bits, only the 3 lsbs of this
write data is actually used. As long as
LOAD_HIGH_ADDR is asserted, a write to
RCR(23:16) will continue to overwrite register
NVRAM_HIGH_ADDR.
The final read/write interface to the external nvRAM is
via the Add-On Reset and Control Register (ARCR).
This mechanism is identical to that used for the PCI’s
RCR, except that the Add-On interface is used to
access the nvRAM via the ARCR. The latency is a bit
longer as well, due to the synchronization that must be
performed between the Add-On clock and the PCI
clock.
6. Write to RCR(31:29) = “000”, a dummy command
to deassert either LOAD_LOW_ADDR or
LOAD_HIGH_ADDR (whichever occurred last),
and to assert internal signal LOAD_WR_DATA.
This signal is used to enable the loading of the
write data register. LOAD_WR_DATA will remain
asserted until another command is issued (load
low/high address, begin read/write). As long as
LOAD_WR_DATA is asserted, a write to
RCR(23:16) will continue to overwrite the write
data register.
While on-chip arbitration logic allows simultaneous
accesses to the nvRAM via the PCI’s RCR and Add-
On’s ARCR (by queuing up the commands), there is
no logic to prevent each interface from overwriting
nvRAM contents. If an interface writes to a memory
location that the other interface has already has writ-
ten to, the value at that location will be overwritten.
7. Write to RCR(23:16) the byte to be written. Since
the signal LOAD_WR_DATA is asserted, the data
will be written to the write data register.
What follows are the sequence of steps required to
access the nvRAM via the RCR. All the scenarios
assume that the RCR is being controlled via PCI bus
transactions. By replacing RCR with ARCR in the
examples below, the operations are identical for an
Add-On device.
8. Write to RCR(31:29) = “110”, the command to
start the nvRAM write operation. This will lead to
the deassertion of LOAD_WR_DATA and will set
the busy bit, RCR(31). The nvRAM interface con-
troller will now initiate a write operation with the
external nvRAM.
The following sequence is used to perform nvRAM
writes when accessing the RCR/ARCR in a byte-
wide fashion:
9. Poll the busy bit until it is no longer set. Once
cleared, it is now safe to perform another write/
read operation to the external nvRAM. The
XFER_FAIL flag (bit 28) can be used to deter-
mine whether the transfer was successful or not.
If XFER_FAIL is asserted, this indicates that a
transfer to the nvRAM did not receive an
ACKNOWLEDGE, and the write transfer should
not be considered successful. This flag remains
set until the start of the next read/write operation.
1. Verify that busy bit, RCR(31), is not set by read-
ing RCR(31). If set, hold off starting the write
sequence (repeat step 1 until this bit clears).
2. Write to RCR(31:29) = “100”, the command to
load the low address byte. This will assert the
internal signal LOAD_LOW_ADDR, which is used
to enable the loading of the low-address register
(NVRAM_LOW_ADDR).
The busy bit will remain set until the nvRAM interface
has completed writing the data byte to the external
nvRAM, and has verified that the write sequence is fin-
ished. The nvRAM “shuts down” during a write and will
not accept any new commands (does not generate an
ACKNOWLEDGE) until it finishes the write operation.
The S5320 will continue to send commands to the
nvRAM until it responds with an ACKNOWLEDGE,
after which it clears the busy bit, indicating that the
write operation is truly complete. If the busy bit were to
be cleared after the nvRAM interface finished the
write, but before the external nvRAM was actually fin-
ished, a scenario exists where a successive write
would be ignored. In this case, the software driver
3. Write to RCR(23:16) with the low address byte.
Since signal LOAD_LOW_ADDR is asserted, the
data
will
be
written
to
register
long as
NVRAM_LOW_ADDR.
As
LOAD_LOW_ADDR is asserted, a write to
RCR(23:16) will continue to overwrite register
NVRAM_LOW_ADDR.
4. Write to RCR(31:29) = “101”, the command to
load the high address byte. This will assert the
internal signal LOAD_HIGH_ADDR, which is
used to enable the loading of the high-address
register (NVRAM_HIGH_ADDR).
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could not use the busy bit to determine when to start a
new write, but would need to insert a delay (deter-
mined by the “shut down” time of the nvRAM, between
5-10 ms). Fortunately, the S5320 implements the
Acknowledge Polling scheme described above, which
will not take away the busy bit until the write is truly fin-
ished, and the external nvRAM is available for
accesses.
the read data in RCR(32:16) may not be valid.
This flag remains set until the start of the next
read/write operation.
When performing a word/double-word RCR
access, you can combine the data and control in
the same command. The following is the sequence
for a write:
1. Verify that busy bit, RCR(31), is not set by read-
ing RCR(31). If set, hold off starting the write
sequence (repeat step 1 until the bit clears).
The following sequence is used to perform nvRAM
writes when accessing the RCR/ARCR in a byte-
wide fashion:
2. Write to RCR(31:29) = “100” and RCR(23:16)
with the low address byte. This will directly load
NVRAM_LOW_ADDR with RCR(23:16).
1. Verify that busy bit, RCR(31), is not set by read-
ing RCR(31). If set, hold off starting the read
sequence (repeat step 1 until this bit clears).
3. Write to RCR(31:29) = “101” and RCR(23:16)
with the high address byte. This will directly load
NVRAM_HIGH_ADDR with RCR(23:16).
2. Write to RCR(31:29) = “100”, the command to
load the low address byte. This will assert the
internal signal LOAD_LOW_ADDR, which is used
to enable the loading of the low-address register
(NVRAM_LOW_ADDR).
4. Write to RCR(31:29) = “110” and RCR(23:16)
with the write data. This will directly load the write
data register with RCR(23:16). This will also set
the busy bit, RCR(31). The nvRAM interface con-
troller will now initiate a write operation to the
external nvRAM.
3. Write to RCR(23:16) with the low address byte.
Since signal LOAD_LOW_ADDR is asserted, the
data will be written to the register
NVRAM_LOW_ADDR.
As
long
as
5. Poll the busy bit until it is no longer set. Once
cleared, it is now safe to perform another write/
read operation to the external nvRAM. In addi-
tion, evaluate the XFER_FAIL flag (bit 28) to
determine whether the transfer was successful or
not. If XFER_FAIL is asserted, this indicates that
a transfer to the nvRAM did not receive an
ACKNOWLEDGE. The write should not be con-
sidered successful. This flag remains set until the
start of the next read/write operation.
LOAD_LOW_ADDR is asserted, a write to
RCR(23:16) will continue to overwrite register
NVRAM_LOW_ADDR.
4. Write to RCR(31:29) = “101”, the command to
load the high address byte. This will assert the
internal signal LOAD_HIGH_ADDR, which is
used to enable the loading of the high-address
register (NVRAM_HIGH_ADDR).
5. Write to RCR(23:16) with the high address byte.
Since signal LOAD_HIGH_ADDR is asserted, the
data will be written to the register
NVRAM_HIGH_ADDR. Note that as the nvRAM
address is limited to 11-bits, only the 3-lsb’s of
this write data is actually used. As long as
LOAD_HIGH_ADDR is asserted, a write to
RCR(23:16) will continue to overwrite register
NVRAM_HIGH_ADDR.
The following sequence is used for a read:
1. Verify that the busy bit, RCR(31), is not set by
reading RCR(31). If set, hold off starting the read
sequence (repeat step 1 until the bit clears).
2. Write to RCR(31:29) = “100” and RCR(23:16)
with the low address byte. This will directly load
NVRAM_LOW_ADDR with RCR(23:16).
6. Write to RCR(31:29) = “111”, the command to
start the nvRAM read operation. This will set the
busy bit, RCR(31). The nvRAM interface control-
ler will now initiate a read operation to the
external nvRAM.
3. Write to RCR(31:29) = “101” and RCR(23:16)
with the high address byte. This will directly load
NVRAM_HIGH_ADDR with RCR(23:16).
4. Write to RCR(31:29) = “111”. This will set the
busy bit, RCR(31). The nvRAM interface control-
ler will now initiate a read operation with the
external nvRAM.
7. Poll the busy bit until it is no longer set. Once
cleared, the read data will be located in
RCR(23:16). In addition, evaluate the
XFER_FAIL flag (bit 28) to determine whether the
transfer was successful or not. If XFER_FAIL is
asserted, this indicates that a transfer to the
nvRAM did not receive an ACKNOWLEDGE, and
5. Poll the busy bit until it is no longer set. Once
cleared, the read data will be located in
RCR(23:16). In addition, evaluate the
XFER_FAIL flag (bit 28) to determine whether the
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Data Sheet
transfer was successful or not. If XFER_FAIL is
asserted, this indicates that a transfer to the
nvRAM did not receive an ACKNOWLEDGE. The
read data in RCR(32:16) should not be consid-
ered valid. This flag remains set until the start of
the next read/write operation.
access is a Type 0 configuration cycle or a Type 1 con-
figuration cycle. Type 0 cycles have AD0 and AD1
equal to 0 and are used to access PCI bus agents.
Type 1 configuration cycles are intended only for
bridge devices and have AD0 as a 1 with AD1 as a 0
during the address phase.
The S5320 PCI device is a bus agent (not a bridge)
and responds only to a Type 0 configuration accesses.
Figure 41 depicts the state of the AD bus during the
address phase of a Type 0 configuration access. The
S5320 controller does not support the multiple function
numbers field (AD[10:8]) and only responds to the all-0
function number value.
PCI BUS CONFIGURATION CYCLES
Cycles beginning with the assertion IDSEL and
FRAME# along with the two configuration command
states for C/BE[3:0] (configuration read or write)
access the selected device’s configuration space. Dur-
ing the address phase of the configuration cycle just
described, the values of AD0 and AD1 identify if the
Figure 41. PCI AD Bus Definition Type 0 Configuration Access
31
11 10
8 7
2 1 0
0 0
00h
000
FUNCTION
NUMBER
REGISTER
NUMBER
RESERVED
TYPE 0
XXXXXXXX - INTERNAL REGISTER
ADDRESS
(DEVICE ID, ETC.)
The configuration registers for the S5320 PCI control-
ler can only be accessed under the following
conditions:
Figure 42. Type 0 Configuration Read Cycles
0
1
2
3
4
5
PCI CLK
FRAME#
AD[31:0]
C/BE[3:0]#
IRDY#
•
IDSEL high (PCI slot unique signal which iden-
tifies access to configuration registers) along
with FRAME# low.
ADD
1010
DATA
•
•
•
Address bits A0 and A1 are 0 (Identifies a Type
0 configuration access).
BYTE EN
Address bits A8, A9, and A10 are 0 (Function
number field of 0 supported).
Command bits, C/BE[3:0]# must identify a con-
figuration cycle command (101X).
TRDY#
IDSEL
Figure 42 describes the signal timing relationships for
configuration read cycles. Figure 43 describes config-
uration write cycles.
DEVSEL#
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Figure 43. Type 0 Configuration Write Cycles
EXPANSION BIOS ROMS
This section provides an example of a typical PC-com-
patible expansion BIOS ROM. Address offsets 040h
through 07Fh represent the portion of the external nv
memory used to boot-load the S5320 controller.
0
1
2
3
4
5
PCI CLK
FRAME#
AD[31:0]
C/BE[3:0]#
IRDY#
Whether the expansion ROM is intended to be execut-
able code is determined by the contents of the first
three locations (starting at offset 0h) and a byte check-
sum over the defined length. The defined length is
specified in the byte at address offset 0002h. Table 39
lists each field location by its address offset, its length,
its value, and description.
DATA
ADD
1011
BYTE EN
TRDY#
IDSEL
The following represents the boot-load image for the
S5320 controller’s PCI configuration register:
DEVSEL#
Table 39. PC Compatible Expansion ROM
Byte Offset
0h
Byte Length (decimal)
Binary Value
55h
Description
BIOS ROM signature byte 1
BIOS ROM signature byte 2
Length in multiples of 512 bytes
Entry point for INIT function.
Reserved (application unique data)
Pointer to PCI Data Structure
user-defined
Example
55h
1
1
1h
AAh
AAh
2h
1
variable
variable
variable
variable
variable
Vendor ID
Device ID
not used
01h
3h
4
7h-17h
18h-19h
1Ah-3Fh
40h
17
2
38
2
(see page 2-23)
10E8h
5920h
xxh
42h
2
(see page 2-24)
44h
1
45h
1
S5320 Special
Modes
01h
(see page 2-89 and 2-129)
46h
48h
49h
4Ch
4Dh
4Eh
2
1
3
1
1
1
not used
Revision ID
class code
not used
xxxxh
00h
(see page 2-29)
(see page 2-30)
FF0000h
xxh
not used
xxh
your header
type
00h
(see page 2-37)
(see page 2-38)
4Fh
1
self-test, if
desired
80h or 00h
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Table 39. PC Compatible Expansion ROM (Continued)
Byte Offset
Byte Length (decimal)
Binary Value
Description
Example
50h
1
80h, 81h or 82h (required, see page 2-39, and page 2-74,
Table 38)
80h, 81h or
82h
51h
52h
53h
54h
58h
5Ch
60h
64h
68h
6Ch
6Eh
70h
1
1
1
4
4
4
4
4
8
2
2
4
FFh
E8h
(required per Table 38)
(required per Table 38)
(required per Table 38)
(see page 2-39)
FFh
E8h
10h
10h
base addr. #1
base addr. #2
base addr. #3
base addr. #4
not used
not used
SVID
00000000h
00000000h
00000000h
00000000h
00000000h
XXh
(see page 2-39)
(see page 2-39)
(see page 2-39)
(see page 2-44)
5555h
SID
(see page 2-45)
3333h
[Expansion ROM base addr.]
FFFFF801h
(see page 2-46)
(exampleshows
2K bytes)
74h
7Ch
8
1
1
1
1
not used
Interrupt line
Interrupt pin
not used
XXh
0Ch
01h
xxh
xxh
(see page 2-48)
(see page 2-49)
(see page 2-48)
(see page 2-49)
application specific
7Dh
7Eh
7Fh
not used
80h Ñ
1FFh,
2FFh
3FFh etc.
Byte checksum, location dependent on
value for length field at offset 0002h.
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A 16-bit pointer at location 18h of the PC expansion
ROM identifies the start offset of the PCI data struc-
ture. The PCI data structure is shown in Table 40 and
contains various vendor, product, and program
descriptions. This structure is provided here for refer-
ence only - the user should refer to the PCI BIOS
specification for complete details.
Note: The access time for large serial devices should
be considered, since it may cause a lengthy system
delay during initialization. For example, a 2 Kbytes
serial device will take about 1 second to be read. Many
systems, even when BIOS ROMs are ultimately shad-
owed into system RAM, may read this memory space
twice (once to validate its size and checksum, and
once to move it into RAM).
Table 40. PCI Data Structure
Byte Length
(decimal)
Byte Offset
Binary Value
Description
0h
4
“PCIR”
Signature, the ASCII string “PCIR” where “P” is at offset 0, “C” at offset 1,
and so on
4h
6h
2
2
2
2
1
3
2
2
2
1
2
variable
variable
variable
variable
variable
variable
variable
variable
variable
variable
0000h
Vendor Identification
Device Identification
8h
Pointer to Vital Product Data
PCI Data Structure Length (starts with signature field)
PCI Data Structure Revision (=0 for this definition)
Class Code
Ah
Ch
Dh
10h
12h
14h
15h
16h
Image Length
Revision Level
Code Type
Indicator (bit D7=1 signifies “last image”)
Reserved
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PCI BUS INTERFACE
Data Sheet
tiator-target pair. A data phase consists of at least one
PCI clock. FRAME# is deasserted to indicate that the
final data phase of a PCI cycle is occurring. Wait
states may be added to any data phase (each wait
state is one PCI clock).
This section details various events which may occur
on the S5320 PCI bus interface. Since the S5320
functions as a target or slave device, signal timing
details are given for target transactions only.
The PCI bus command presented on the C/BE[3:0]#
pins during the address phase can represent 16 possi-
ble states. Table 41 lists the PCI commands and those
which are supported by the S5320. A “Yes” in the
“Supported by S5320” column in Table 41 indicates
that the S5320 device will assert the signal DEVSEL#
when that particular command is issued along with the
appropriate PCI address.
PCI BUS TRANSACTIONS
Because the PCI bus utilizes multiplexed address/data
pins (AD[31:0]), every PCI bus transaction consists of
an address phase followed by a data phase. An
address phase is defined as the clock period in which
FRAME# transitions from inactive to active. During the
address phase, a bus command is driven by the initia-
tor on the C/BE[3:0]# signal pins. If the command
indicates a PCI read, the clock cycle following the
address phase is used to perform a “bus turn-around”
cycle. A turn-around cycle is a clock period in which
the address/data bus is not driven by an initiator or a
target device. This is used to avoid PCI bus conten-
tion. For a write command, a turn-around cycle is not
needed, and the bus goes directly from an address
phase to a data phase.
The completion or termination of a PCI cycle can be
signaled in several ways. In most cases, the comple-
tion of the final data phase is indicated by the
assertion of the ready signals from both the target
(TRDY#) and initiator (IRDY#) while FRAME# is inac-
tive. In some cases, the target is not able to continue
or support a burst transfer and will assert a STOP#
signal. This is referred to as a target disconnect. There
is also the case where an addressed device does not
exist, and the signal DEVSEL# is not driven. In this
case, the initiator is responsible for ending the cycle.
This is referred to as a master abort. The bus is
returned to the idle phase when both FRAME# and
IRDY# are deasserted.
All PCI bus transactions consist of an address phase
followed by one or more data phases. During the one-
PCI-clock-long address phase, the bus address and
command information is latched into the S5320. The
number of data phases depends on how many data
transfers are desired or are possible within a given ini-
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Data Sheet
Table 41. PCI Bus Commands
C/BE[3:0]#
0000
0001
0010
0011
0100
0101
0110
0111
Command Type
Supported
No
Interrupt Acknowledge
Special Cycle
No
I/O Read
Yes
I/O Write
Yes
Reserved
No
Reserved
No
Memory Read
Memory Write
Reserved
Yes
Yes
1000
1001
1010
1011
1100
1101
1110
No
Reserved
No
Configuration Read
Configuration Write
Memory Read Multiple
Reserved
Yes
Yes
Yes 1
No
Memory Read Line
Memory Write and Invalidate
Yes 1
Yes 2
1111
1. Memory Read Multiple and Memory Read Line are executed as a Memory Read.
2. Memory Write and Invalidate is executed as a Memory Write.
cates that the next access needs to be a completely
new cycle.
PCI BURST TRANSFERS
The PCI bus, by default, expects burst transfers to be
executed. To successfully perform a burst transfer,
both the initiator and target must order their burst
address sequence in an identical fashion. There are
two different ordering schemes: linear address incre-
menting and 80486 cache line fill sequencing.
Some accesses to the S5320 controller do not support
burst transfers. For example, the S5320 does not
allow burst transfers when accesses are made to the
configuration or operation registers. Attempts to per-
form burst transfers to these regions will cause a
disconnect on the PCI bus, as described above.
Expansion ROM accesses also do not support bursts,
and will respond in the same way. Accesses to mem-
ory or I/O regions defined by the Base Address
Registers 1-4 may be bursts, if desired.
The S5320 supports only linear burst ordering.
Attempts to perform burst transfers with a scheme
other than this will cause the STOP# signal to be
asserted during the first data phase, thus issuing a dis-
connect to the initiator. The S5320 completes the initial
data phase successfully, but asserting STOP# indi-
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PCI READ TRANSFERS
Data Sheet
When burst read transfers are attempted to the S5320
operation registers, configuration registers or expan-
sion ROM, STOP# is asserted during the first data
transfer to indicate to the initiator that no further trans-
fers (data phases) are possible. This is a target-
initiated termination where the target disconnects after
the first data phase. Figure 45 shows the signal rela-
tionships during a burst read attempt to the S5320
operation registers.
The S5320 responds to PCI bus memory or I/O read
transfers when it is selected as a target.
PCI targets may drive DEVSEL# and TRDY# after the
end of the address phase. TRDY# is not driven until
the target can provide valid data for the PCI read.
Read accesses from the S5320 operation registers
are shown in Figure 44. The S5320 conditionally
asserts STOP# in clock period 3 if the initiator keeps
FRAME# asserted during clock period 2 with IRDY#
asserted (indicating a burst is being attempted). Wait
states may be added by the initiator by not asserting
the signal IRDY# during clock 3 and beyond. If
FRAME# remains asserted, but IRDY# is not
asserted, the initiator is just adding wait states, not
necessarily attempting a burst.
For 32-bit configuration, it is recommended that the
read operation should be performed in the DWORD
boundary with the offset address increment by 4 bytes.
The starting DWORD read address should be 0, 4, 8,
C, . . . Similarly with 16-bit configuration, the starting
read WORD boundary with the offset address incre-
ment by 2 bytes. The starting WORD read address
should be 0, 2, 4, 6, . . .
PCI WRITE TRANSFERS
Figure 44. Single Data Phase PCI Bus Read of S5320
Registers or Expansion ROM
Write transfers on the PCI bus are one clock period
shorter than read transfers. This is because the
AD[31:0] bus does not require a turn-around cycle
between the address and data phases.
1
2
3
4
5
PCLK
Write accesses to the S5320 operation registers are
shown in Figure 46. Here, the S5320 asserts the sig-
nal STOP# in clock period 3. STOP# is asserted
because the S5320 does not support burst writes to
operation registers. Wait states may be added by the
initiator by not asserting the signal IRDY# during clock
2 and beyond. There is only one condition where
writes to S5320 internal registers do not return TRDY#
(but do assert STOP#). This is called a target-initiated
termination or target disconnect. This occurs when a
write attempt is made to a full Pass-Thru FIFO. The
assertion of STOP# without the assertion of TRDY#
indicates that the initiator should retry the operation
later. The S5320 will sustain a burst as long as the
FIFO is not full.
FRAME#
AD[31:0]
C/BE[3:0]#
IRDY#
(T)
(I)
Address
Data
Bus Cmd
Byte Enables
TRDY#
DEVSEL#
STOP#
(I) Driven by Initiator
(T) Driven by Target
There are only two conditions where accesses to the
S5320 do not return TRDY#, but assert STOP#
instead. This condition is called a target-initiated termi-
nation or target disconnect. This can occur when a
read attempt is made to an empty Pass-Thru FIFO.
The second condition may occur when read accesses
to the expansion ROM generate a retry if the nvRAM
interface has not finished reading 4 bytes.
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Data Sheet
Figure 45. Burst PCI Bus Read Attempt to S5320 Reg-
isters or Expansion ROM
Target Disconnects
There are many situations where a target may discon-
nect. Slow responding targets may disconnect to
permit more efficient (faster) devices to be accessed
while they prepare for the next data phase. Or a target
may disconnect if it recognizes that the next data
phase in a burst transfer is out of its address range. A
target disconnects by asserting STOP#, TRDY#, and
DEVSEL# as shown in Figures 47 and 48. The initiator
in Figure 47 responds to the disconnect condition by
deasserting FRAME# on the following clock but does
not complete the data transfer until IRDY# is asserted.
The timing diagram in Figure 48 also applies to the
S5320.
1
2
3
4
5
PCLK
FRAME#
AD[31:0]
C/BE[3:0]#
IRDY#
(T)
(I)
Address
Data
Bus
Cmd
Byte
Enables
TRDY#
DEVSEL#
STOP#
The S5320 performs a target disconnect if a burst
access is attempted to any of its PCI Operation/Con-
figuration Registers, or to the Expansion ROM.
Target Requested Retries
(I) Driven by Initiator
(T) Driven by Target
The S5320 initiates a retry for Pass-Thru writes when
the Write FIFO is full, and for Pass-Thru reads when
the Add-On cannot supply data within 16 PCI clocks
from the assertion of FRAME# (for the first data phase
of a burst). A retry is requested by a target by assert-
ing both STOP# and DEVSEL# while TRDY# is
deasserted. Figure 49 shows the behavior of the
S5320 when performing a target-initiated retry.
Figure 46. Burst PCI Bus Write of S5320 Registers
1
2
3
4
5
PCLK
(I)
(I)
FRAME#
AD[31:0]
C/BE[3:0]#
IRDY#
Figure 47. Target Disconnect Example 1
Address
Data 1
BE 1
Data 2
1
2
3
4
5
Bus
Cmd
BE 2
(I)
(I)
PCLK
(I)
FRAME#
IRDY#
(T)
(T)
(T)
TRDY#
DEVSEL#
STOP#
(I)
(T)
(T)
(T)
TRDY#
DEVSEL#
STOP#
Data
Transfered
(I) Driven by Initiator
(T) Driven by Target
No Data
Transfered
(I) Driven by Initiator
(T) Driven by Target
Target
Disconnect
Identified
Target-Initiated Termination
Data
Transfered
There are situations where the target may end a trans-
fer prematurely. This is called “target-initiated
termination.” Target termination falls into three catego-
ries: disconnect, retry, and target abort. Only the
disconnect termination completes a data transfer.
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Data Sheet
Figure 48. Target Disconnect Example 2
Target Locking
It is possible for a PCI bus master to obtain exclusive
access to a target (“locking”) through use of the PCI
bus signal LOCK#. LOCK# is different from the other
PCI bus signals because its ownership may belong to
any bus master, even if it does not currently have own-
ership of the PCI bus. The ownership of LOCK#, if not
already claimed by another master, may be achieved
by the current PCI bus master on the clock period fol-
lowing the initial assertion of FRAME#. Figure 50
describes the signal relationship for establishing a
lock. The ownership of LOCK#, once established, per-
sists even while other bus masters control the bus.
Ownership can only be relinquished by the master
which originally established the lock.
1
2
3
4
5
PCLK
(I)
FRAME#
IRDY#
(I)
(T)
(T)
(T)
TRDY#
DEVSEL#
STOP#
Target
(I) Driven by Initiator
(T) Driven by Target
Disconnect
Single Data
Transferred
Data
Transfered
PCI Bus Access Latency Components
Target Aborts
Bus Access Latency
A target abort termination represents an error condi-
tion when no number of retries will produce a
successful target access. A target abort is uniquely
identified by the target deasserting DEVSEL# and
TRDY# while STOP# is asserted. When a target per-
forms an abort, it must also set bit 11 of its PCI Status
register (PCISTS). The S5320 never responds with a
target abort when accessed. Target termination types
are summarized in Table 42.
TRDY#
GNT#
FRAME#
Asserted
REQ#
Asserted
Asserted
Asserted
--Arbitration Latency-- --Bus Acquisition-- --Target Latency--
Latency
Figure 49. Target-Initiated Retry
1
2
3
4
5
Target Latency
PCLK
The PCI specification requires that a selected target
relinquish the bus should an access to that target
require more than eight PCI clock periods (16 clocks
for the first data phase, 8 clocks for each subsequent
data phase). This prevents slow target devices from
potentially monopolizing the PCI bus and also allows
more accurate estimations for bus access latency.
(I)
FRAME#
IRDY#
TRDY#
(I)
(T)
DEVSEL# (T)
Note that a special mode is available to the user which
will allow for this mechanism to be disabled, thus vio-
lating the PCI 2.1 Specification. If a value of 0 is
programmed into the serial nvRAM location 45h, bit 0,
target latency is ignored. In this case, the S5320 will
never issue a retry/disconnect in the event of a slow
Add-On device. This programmable bit is only pro-
vided for flexibility, and most users should leave this bit
set to 1.
(T)
STOP#
Initiator
Sequences IRDY#
+ FRAME# to return
to IDLE state
(I) Driven by Initiator
(T) Driven by Target
Target Retry
Signaled
nvRAM Location 45h, bit 0 = 0: No disconnect for slow
Add-On device.
nvRAM Location 45h, bit 0 = 1: PCI 2.1 compliant
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Data Sheet
Figure 50. Engaging the LOCK# Signal
1
2
3
4
5
PCLK
(I)
FRAME#
LOCK#
AD[31:0]
(T
(I)
(I)
)
Address
Data
IRDY#
(T)
TRDY#
DEVSEL#
(T)
LOCK
MECHANISM
AVAILABLE
UPON FIRST
ACCESS
TARGET
BECOMES
LOCKED
(I) Driven by Initiator
(T) Driven by Target
BUS
IDLE
LOCK MECHANISM
AVAILABLE
LOCK
ESTABLISHED
LOCK
MAINTAINED
Table 42. Target Termination Type
Termination
Disconnect
Retry
DEVSEL#
STOP#
TRDY#
on
Comment
on
on
off
on
on
on
Data is transferred. Transaction needs to be re-initiated to complete.
Data was not transferred. Transaction should be tried later.
Data was not transferred. Fatal error.
off
Abort
off
Targets selected with LOCK# deasserted during the
assertion of FRAME# (clock period 1 of Figure 50),
which encounter the assertion of LOCK# during the
following clock (clock period 2 of Figure 50) are there-
after considered “locked.” A target, once locked,
requires that subsequent accesses to it deassert
LOCK# while FRAME# is asserted. Figure 51 shows a
subsequent access to a locked target by the master
which locked it. Because LOCK# is owned by a single
master, only that master is able to deassert it at the
beginning of a transaction (assuming successful
access to the locked target). A locked target can only
be unlocked during the clock period following the last
data transfer of a transaction when the LOCK# signal
is deasserted.
An unlocked target ignores LOCK# when it observes
that LOCK# is already asserted during the first clock
period of a transaction. This allows other masters to
access other (unlocked) targets. If an access to a
locked target is attempted by a master other than the
one that locked it, the target responds with a retry
request, as shown in Figure 52.
The S5320 responds to and supports bus masters
which lock it as a target.
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PCI BUS INTERRUPTS
Data Sheet
The S5320 asserts SERR# if it detects odd parity dur-
ing an address phase, if enabled. The SERR# enable
bit is bit 8 in the S5320 PCI Command Register
(PCICMD). The odd parity error condition involves the
state of signals AD[31:0] and C/BE[3:0]# when
FRAME# is first asserted and the PAR signal during
the following clock. If an error is detected, the S5320
asserts SERR# on the following (after PAR valid)
clock. Since many targets may observe an error on an
address phase, the SERR# signal is an open-drain
multi-sourced, wire-ORed signal on the PCI bus. The
S5320 drives SERR# low for one clock period when
an address phase error is detected. Once an SERR#
error is detected by the S5320, the PCI Status register
bit 14, System Error, is set and remains set until
cleared through software or a hardware reset.
The S5320 controller is able to generate PCI bus inter-
rupts by asserting the PCI bus interrupt signal (INTA#).
INTA# is a multi-sourced, wire-ORed signal on the PCI
bus and is driven by an open drain output on the
S5320. The assertion and deassertion of INTA# have
no fixed timing relationship with respect to the PCI bus
clock. Once the S5320 asserts INTA#, it remains
asserted until the interrupt source is cleared by a write
to the Interrupt Control/Status Register (INTCSR). In
the case of the external Add-On Interrupt, INTA# will
remain set as long as the ADDINT# pin is driven low
by an Add-On device(s). The source(s) driving ADD-
INT# must deassert this input before the PCI interrupt
(INTA#) is driven to the false state. It is the responsibil-
ity host software to clear the Add-On interrupt source
before exiting its interrupt handler routine.
The PERR# signal is similar to the SERR# with two
differences: it reports errors for the data phase and is
only asserted by the device receiving the data. The
S5320 drives this signal (removed from tri-state) when
it is the selected target for write transactions. The par-
ity error conditions are only reflected by the PERR#
pin if the Parity Error Enable bit (bit 6) of the PCI Com-
mand Register is set. Upon the detection of a data
parity error, the Detected Parity Error bit (bit 15) of the
PCI Status Register is set (PCISTS). Unlike the
PERR# signal pin, this Status bit is set regardless of
the state of the PCI Command Register's Parity Error
Enable bit.
PCI BUS PARITY ERRORS
The PCI specification defines two error-reporting sig-
nals, PERR# and SERR#. These signals indicate a
parity error condition on the signals AD[31:0], C/
BE[3:0]#, and PAR. The validity of the PAR signal is
delayed one clock period from its corresponding
AD[31:0] and C/BE[3:0]# signals. Even parity is sup-
ported by PCI: when the total number of ones in the
group of signals AD[31:0] and C/BE[3:0]# is equal to
an even number the parity bit will be deasserted. If an
odd number of ones is seen, the parity bit will be
asserted.
The assertion of PERR# occurs two clock periods fol-
lowing the data transfer. This two-clock delay occurs
because the PAR signal does not become valid until
the clock following the transfer, and an additional clock
is provided to generate and assert PERR# once an
error is detected. PERR# is only asserted for one
clock cycle for each error sensed. The S5320 only
qualifies the parity error detection during the actual
data transfer portion of a data phase (when both
IRDY# and TRDY# are asserted).
PERR# is the error-reporting mechanism for parity
errors that occur during the data phase for all but PCI
Special Cycle commands. SERR# is the error-report-
ing mechanism for parity errors that occur during the
address phase.
The timing diagram in Figure 53 shows the timing rela-
tionships between the signals AD[31:0], C/BE[3:0]#,
PAR, PERR# and SERR#.
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Data Sheet
Figure 51. Access to a Locked Target by its Owner
Figure 52. Access Attempt to a Locked Target
1
2
3
4
5
1
2
3
4
5
PCLK
PCLK
(I)
(I)
FRAME#
LOCK#
AD[31:0]
FRAME# (I)
LOCK#
(I)
Address
Data
Data
AD[31:0]
Address
Data
(I)
IRDY#
(I)
(T)
(T)
IRDY#
(T)
(T)
TRDY#
DEVSEL#
TRDY#
DEVSEL#
LOCKED
TARGET
IDENTIFIES
CONDITION
WHICH
UNLOCKS
TARGET
(T)
STOP#
(I)Driven byInitiator
(T)DrivenbyTarget
OWNER
LOCKED TARGET
(I) Driven by Initiator
(T) Driven by Target
IDENTIFIES THAT BUS
MASTER ISNOT ITS
OWNER
CAUSESTARGET
RETRYTERMINATION
Figure 53. Error Reporting Signal
1
2
3
4
5
6
7
8
9
PCLK
(I)
(I)
FRAME#
AD[31:0]
C/BE[3:0]
(T)
(I)
(I)
Address
Address
DataA
DataB
A
B
CMDA
BE's A
CMDB
BE'sB
(I)
(T)
(I)
(I)
PAR
GOOD
ERROR
GOOD
ERROR
(T)
(T)
SERR#
PERR#
GOOD
ERROR
GOOD
ERROR
A
B
READ
TRANSACTION
WRITE
TRANSACTION
(I)Driv en by Initiator
(T) Driven by Target
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Data Sheet
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S5320 – PCI Match Maker: Mailbox Overview
MAILBOX OVERVIEW
Data Sheet
FUNCTIONAL DESCRIPTION
The S5320 has two 32-bit mailbox registers. These
mailboxes are useful for passing command and status
information between the Add-On and the PCI bus. The
PCI interface has one incoming mailbox (Add-On to
PCI) and one outgoing mailbox (PCI to Add-On). The
Add-On interface has one incoming mailbox (PCI to
Add-On) and one outgoing mailbox (Add-On to PCI).
The PCI incoming and Add-On outgoing mailboxes
are the same, internally. The Add-On incoming and
PCI outgoing mailboxes are also the same, internally.
Figure 54 shows a block diagram of the PCI to Add-On
mailbox registers. Add-On incoming mailbox read
accesses pass through an output interlock register.
This prevents a PCI bus write to a PCI outgoing mail-
box from corrupting data being read by the Add-On.
Figure 55 shows a block diagram of the Add-On to PCI
mailbox registers. PCI incoming mailbox reads also
pass through an interlocking mechanism. This pre-
vents an Add-On write to an outgoing mailbox from
corrupting data being read by the PCI bus. The follow-
ing sections describe the mailbox flag functionality and
the mailbox interrupt capabilities.
The mailbox status may be monitored in two ways.
The PCI and Add-On interfaces each have a mailbox
status register to indicate the empty/full status of data
bytes within the mailboxes. The mailboxes may also
be configured to generate interrupts to the PCI and/or
Add-On interface. The outgoing and the incoming
mailbox on each interface can be configured to gener-
ate interrupts.
Figure 54. PCI to Add-On Mailbox Register
OUTPUT
INTERLOCK
REGISTER
MAILBOX
REGISTER
PCI BUS
DQ
EN
DQ
EN
ADD-ON BUS
LOAD ENABLE
ADCLK
PCI CLK
RD#
SELECT#
ADR -MB
D
Q
VDD
ADCLK
R
S
DQ
PCI CLK
MAILBOX
FULL
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Data Sheet
Figure 55. Add-On to PCI Mailbox Register
PCI
INCOMMING
MAILBOX
OUTPUT
INTERLOCK
REGISTER
MAILBOX
REGISTER
Q
D
Q
D
PCI BUS
ADD-ON BUS
EN
EN
PCI CLK
PCI READ
ADCLK
WR#
SELECT#
ADR -MB
VDD
R
S
D
Q
ADCLK
MAILBOX
FULL
D
Q
ADCLK
Mailbox Empty/Full Conditions
13 are set. These bits indicate that outgoing mailbox
bytes 0 and 1 are full. Reading the Add-On Mailbox
Empty/Full Status Register (AMBEF) shows that bits
12 and 13 in this register are also set, indicating the
Add-On incoming mailbox bytes 0 and 1 are full. An
Add-On read of the incoming mailbox, bytes 0 and 1,
clears the status bits in both the MBEF and AMBEF
status registers.
The PCI and Add-On interfaces each have a mailbox
status register. The PCI Mailbox Empty/Full Status
(MBEF) and Add-On Mailbox Empty/Full Status
(AMBEF) registers indicate the status of all bytes
within the mailbox registers. A write to an outgoing
mailbox sets the status bits for that mailbox. The byte
enables determine which bytes within the mailbox
become full (and which status bits are set).
The read-only status flags in the MBEF and AMBEF
registers are reset when the corresponding byte is
read from the incoming mailbox. Alternately, these
flags can be globally reset from either the PCI inter-
face or the Add-On interface. The PCI Bus Reset
Control Register (RCR) and the Add-On Reset Control
Register (ARCR) each have a bit to reset all of the
mailbox status flags.
An outgoing mailbox for one interface is an incoming
mailbox for the other. Therefore, incoming mailbox sta-
tus bits on one interface are identical to the
corresponding outgoing mailbox status bits on the
other interface. The following list shows the relation-
ship between the mailbox registers on the PCI and
Add-On interfaces.
Mailbox Interrupts
PCI Interface
Add-On Interface
Incoming Mailbox
Outgoing Mailbox
The designer has the option to generate interrupts to
the PCI and Add-On interfaces when specific mailbox
events occur. The PCI and Add-On interfaces can
each define two conditions where interrupts may be
generated. An interrupt can be generated when the
incoming mailbox becomes full and/or when the outgo-
ing mailbox becomes empty. A specific byte within a
specific mailbox is selected to generate the interrupt.
The conditions defined to generate interrupts to the
PCI interface do not have to be the same as the condi-
tions defined for the Add-On interface.
Outgoing Mailbox
Incoming Mailbox
=
=
PCI Mailbox Empty/
Full
Add-On Mailbox Empty/
Full
=
A write to an outgoing mailbox also writes data into the
incoming mailbox on the other interface. It also sets
the status bits for the outgoing mailbox and the status
bits for the incoming mailbox on the other interface.
Reading the incoming mailbox clears the correspond-
ing status bit(s) in the Add-On and PCI mailbox status
registers (AMBEF and MBEF).
For the incoming mailbox interrupts, when the speci-
fied byte becomes full, an interrupt is generated. The
interrupt might be used to indicate command or status
information has been provided, and must be read. For
For example, a PCI write is performed to the PCI out-
going mailbox, writing bytes 0 and 1 (CBE0# and
CBE1# asserted). Reading the PCI Mailbox Empty/
Full Status Register (MBEF) indicates that bits 12 and
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Data Sheet
PCI incoming mailbox interrupts, the S5320 asserts
the PCI interrupt, INTA#. For Add-On incoming mail-
box interrupts, the S5320 asserts the Add-On
interrupt, IRQ#.
When the MD[7:0] bus is set up for I/O mode and
LOAD# is high (deasserted), the MD[7:0] bus is an
active output, driving the contents of the PCI outgoing
mailbox, byte 3 (OMB[3]). In this case, the MD[7:0]
bus will be updated anytime the PCI writes to mailbox
OMB[3]. As a result, the MD[7:0] bus will be synchro-
nous to the PCI clock. When LOAD# is driven low, the
MD[7:0] bus is tri-stated, allowing external data to be
latched into Add-On outgoing mailbox byte 3. This is a
similar function that exists for input-only.
For the outgoing mailbox interrupts, when the speci-
fied byte becomes empty, an interrupt is generated.
The interrupt might be used to indicate that the other
interface has received the last information sent and
more may be written. For PCI outgoing mailbox inter-
rupts, the S5320 asserts the PCI interrupt, INTA#. For
Add-On outgoing mailbox interrupts, the S5320
asserts the Add-On interrupt, IRQ#.
Figures 56 and 57 show the interaction between the
MD[7:0] bus and the LOAD# input pin. Note that a
turnaround cycle is utilized when writing data to the
mailbox byte in I/O mode. This is to prevent contention
on the MD[7:0] drivers.
Add-On Outgoing Mailbox, Byte 3 Access
PCI incoming mailbox byte 3 (Add-On outgoing mail-
box, byte 3, or AOMB[3]) has been further enhanced
by the addition of a separate 8-bit interface (MD[7:0])
on the Add-On side. This interface can be used to
write to AOMB[3] instead of/or in addition to the nor-
mal method (via an Add-On Operation Register write
to AOMB[3]).
BUS INTERFACE
The mailboxes appear on the Add-On and PCI bus
interfaces as two operation registers. One is the out-
going mailbox, and the other is the incoming mailbox.
These mailboxes may be used to generate interrupts
to each of the interfaces. The following sections
describe the Add-On and PCI bus interfaces for the
mailbox registers.
The MD[7:0] bus can be configured in one of two
modes: Input mode or I/O mode. If the configuration
pin MDMODE is strapped high, the MD[7:0] bus is set
to be in input mode only. If MDMODE is strapped low,
the MD[7:0] bus will operate in a bi-directional mode. If
the MD[7:0] bus is set up for input-only mode, data will
be latched into AOMB[3] when the LOAD# input is
sampled low by the Add-On clock. The LOAD# input
pin may also be used to generate a PCI interrupt if the
appropriate interrupt is enabled in the Interrupt Con-
trol/Status Register (INTCSR). These functions are
identical to the Add-On device writing to its byte 3 out-
going mailbox via the DQ bus. As a matter of fact,
Add-On mailbox byte 3 is accessible by either the
external mailbox port or the Add-On interface. Which-
ever interface writes to it last will determine the data
that resides in that register.
PCI Bus Interface
The mailbox operation registers do not support burst
accesses by an initiator. A PCI initiator attempting to
burst to the mailbox registers causes the S5320 to
respond with a target disconnect with data. PCI writes
to a full outgoing mailbox overwrite data currently in
that mailbox. PCI reads from an empty incoming mail-
box return the data that was previously contained in
the mailbox. In this case, the data cannot be guaran-
teed. It is intended for the user to verify that a mailbox
is full before it is read.
PCI incoming and outgoing mailbox interrupts are
enabled/disabled in the INTCSR. The mailboxes can
generate a PCI interrupt (INTA#) under two conditions
(individually enabled). For an incoming mailbox full
interrupt, INTA# is asserted on the rising edge of the
PCI clock after the Add-On mailbox write completes.
For an outgoing mailbox empty interrupt, INTA# is
asserted on the rising edge of the PCI clock after the
Add-On mailbox read completes. INTA# is deasserted
one PCI clock cycle after the mailbox interrupt is ser-
viced (by writing a 1 to the proper interrupt source bit).
Signal Pin
MD0
Add-On Outgoing Mailbox
Mailbox, Bit 24
Mailbox, Bit 25
Mailbox, Bit 26
Mailbox, Bit 27
Mailbox, Bit 28
Mailbox, Bit 29
Mailbox, Bit 30
Mailbox, Bit 31
MD1
MD2
MD3
Add-On Bus Interface
MD4
The Add-On mailbox interface behaves similarly to the
PCI bus interface. Add-On writes to a full outgoing
mailbox overwrite data currently in that mailbox. PCI
reads from an empty incoming mailbox return the data
that was previously contained in the mailbox.
MD5
MD6
MD7
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Data Sheet
Add-On incoming and outgoing mailbox interrupts are
enabled/disabled in the Add-On Interrupt Control/Sta-
tus Register (AINT). The mailboxes can generate the
Add-On IRQ# interrupt under two conditions (individu-
ally enabled). For an incoming mailbox full interrupt,
IRQ# is asserted on the rising edge of the Add-On
clock after the PCI mailbox write completes. For an
outgoing mailbox empty interrupt, IRQ# is asserted on
the rising edge of the Add-On clock after the PCI mail-
box read completes. IRQ# is deasserted one Add-On
clock cycle after the mailbox interrupt is serviced (by
writing a 1 to the proper interrupt source bit).
CONFIGURATION
The PCI interface and the Add-On interface each have
one incoming mailbox (IMB or AIMB) and one outgo-
ing mailbox (OMB or AOMB) along with a single
mailbox status register (MBEF or AMBEF). The outgo-
ing mailbox is read/write, the incoming mailbox and
the mailbox status registers are read-only.
The following sections discuss the registers associ-
ated with the mailboxes and accesses required for
different modes of mailbox operation.
Mailbox Status
8-Bit and 16-Bit Add-On Interfaces
Every byte in each mailbox has a status bit in the Mail-
box Empty/Full Status Registers (MBEF and AMBEF).
Writing a particular byte into the outgoing mailbox sets
the corresponding status bit in both the MBEF and
AMBEF registers. A read of a ‘full’ byte in a mailbox
clears the status bit. The MBEF and AMBEF are read-
only. Status bits cannot be cleared by writes to the sta-
tus registers.
Some Add-On designs may implement an 8-bit or 16-
bit bus interface. The mailboxes do not require a 32-bit
Add-On interface for all the bytes to be read/written.
For 8-bit interfaces, the 8-bit data bus may be exter-
nally connected to all 4 bytes of the 32-bit Add-On
interface (DQ 31:24, 23:16, 15:8, 7:0 are all con-
nected). The Add-On device reading or writing the
mailbox registers may access all mailbox bytes by
cycling through the Add-On byte enable inputs (only
one byte enable may be active at a time). A similar
solution applies to 16-bit Add-On buses. This solution
works for Add-On designs which always use just one
bus width (8-bit or 16-bit).
The S5320 allows the mailbox status bits to be reset
through software. The PCI Bus Reset Control PCI
Operation Register (RCR) and the Add-On Reset Con-
trol Add-On Operation Register (ARCR) each have a
bit to reset mailbox status. Writing a 1 to Mailbox Flag
Reset bit in the RCR or the ARCR register immedi-
ately clears all bits in the both the MBEF and AMBEF
registers. Writing a 0 has no effect. The Mailbox Flag
Reset bit is write-only.
If the DQMODE pin is high, indicating a 16-bit Add-On
interface, the previous solution may be used to imple-
ment an 8-bit interface. The only modification needed
is that BE3(= ADR1) must be toggled after the first two
accesses to steer the S5320 internal data bus to
access the upper 16 bits of the mailboxes.
The flag bits should be monitored when transferring
data through the mailboxes. Checking the mailbox sta-
tus before performing an operation prevents data from
being lost or corrupted. The following sequences are
suggested for PCI mailbox operations using status
polling (interrupts disabled).
Figure 56. Input/Output Mode (MDMODE=0)
ADCLK
LOAD#
S5320
Driving
Turn
Around
WRITE
DATA
Turn
Around
S5320
Driving
MD[0:7]
Figure 57. Input Mode (MDMODE=1)
ADCLK
LOAD#
MD[0:7]
WRITE
DATA
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Reading the PCI Incoming Mailbox:
1. Check Mailbox Status. Read the mailbox status register to determine if any information has been passed from
the Add-On interface.
MBEF
Bits 31:28
If a bit is set, valid data is contained in the corresponding mailbox byte.
2. Read Mailbox. Read the mailbox bytes which MBEF indicates are full. This automatically resets the status bits
in the MBEF and AMBEF registers.
IMB
Bits 31:0
Mailbox data.
Writing the PCI Outgoing Mailbox:
1. Check Mailbox Status. Read the mailbox status register to determine if information previously written to the
mailbox has been read by the Add-On interface. Writes to full mailbox bytes overwrite data currently in the
mailbox (if not already read by the Add-On interface). Repeat until the byte(s) to be written are empty.
MBEF
Bits 15:12
If a bit is set, valid data is contained in the corresponding mailbox byte
and has not been read by the Add-On.
2. Write Mailbox. Write to the outgoing mailbox byte(s).
OMB Bits 31:0 Mailbox data.
Mailbox operations for the Add-On interface are functionally identical. The following sequences are suggested for
Add-On mailbox operations using status polling (interrupts disabled):
Reading an Add-On Incoming Mailbox:
1. Check Mailbox Status. Read the mailbox status register to determine if any information has been passed from
the PCI interface.
AMBEF
Bits 15:12
If a bit is set, valid data is contained in the corresponding mailbox byte.
2. Read Mailbox. Read the mailbox bytes which AMBEF indicates are full. This automatically resets the status
bits in the AMBEF and MBEF registers.
AIMB
Bits 31:0
Mailbox data.
Writing an Add-On Outgoing Mailbox:
1. Check Mailbox Status. Read the mailbox status register to determine if information previously written to the
mailbox has been read by the PCI interface. Writes to full mailbox bytes overwrite data currently in the mailbox
(if not already read by the PCI interface). Repeat until the byte(s) to be written are empty.
AMBEF
Bits 31:28
If a bit is set, valid data is contained in corresponding mailbox byte and
has not been read by the PCI bus.
2. Write Mailbox. Write to the outgoing mailbox byte(s).
AOMB Bits 31:0 Mailbox data.
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Data Sheet
Mailbox Interrupts
Although polling status is useful in some cases, polling requires continuous actions by the processor. Mailbox inter-
rupt capabilities are provided to avoid much of the processor overhead required by continuously polling status bits.
The Add-On and PCI interface can each generate interrupts on the incoming mailbox condition and/or the outgoing
mailbox condition. These can be individual enabled/disabled. A specific byte in the incoming mailbox and outgoing
mailbox is identified to generate the interrupt(s). The tasks required to setup the mailbox interrupts are as follows:
Enabling PCI Mailbox Interrupts:
1. Enable PCI outgoing mailbox interrupts. A specific byte within the outgoing mailboxes is identified to assert
INTA# when read by the Add-On interface.
INTCSR
INTCSR
Bit 4
Enable outgoing mailbox interrupts
Bits 1:0
Identify mailbox byte to generate interrupt
2. Enable PCI incoming mailbox interrupts. A specific byte within the incoming mailboxes is identified to assert
INTA# when written by the Add-On interface.
INTCSR
INTCSR
Bit 12
Enable incoming mailbox interrupts
Bits 9:8
Identify mailbox byte to generate interrupt
Enabling Add-On Mailbox Interrupts:
1. Enable Add-On outgoing mailbox interrupts. A specific byte within the outgoing mailboxes is identified to
assert IRQ# when read by the PCI interface.
AINT
AINT
Bit 12
Enable outgoing mailbox interrupts
Bits 9:8
Identify mailbox byte to generate interrupt
2. Enable Add-On incoming mailbox interrupts. A specific byte within the incoming mailboxes is identified to
assert IRQ# when written by the PCI interface.
AINT
AINT
Bit 4
Enable incoming mailbox interrupts
Bits 1:0
Identify mailbox byte to generate interrupt
With either the Add-On or PCI interface, these two steps can be performed with a single access to the appropriate
register. They are shown separately here for clarity.
Once interrupts are enabled, the interrupt service routine must access the mailboxes and clear the interrupt
source. A particular application may not require all of the steps shown. For instance, a design may only use the
incoming mailbox interrupts and not require support for the outgoing mailbox interrupts. The interrupt service rou-
tine tasks are as follows:
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Servicing a PCI Mailbox Interrupt (INTA# Asserted):
1. Identify the interrupt source(s). Multiple interrupt sources are available on the S5320. The interrupt service
routine must verify that a mailbox generated the interrupt (and not some other interrupt source).
INTCSR
INTCSR
INTCSR
Bit 23
Bit 17
Bit 16
PCI interrupt asserted
PCI incoming mailbox interrupt indicator
PCI outgoing mailbox interrupt indicator
2. Check mailbox status. The mailbox status bits indicate which mailbox bytes must be read or written.
MBEF
MBEF
Bits 31:28
Bits 15:12
Full PCI incoming mailbox bytes
Empty PCI outgoing mailbox bytes
3. Access the mailbox. Based on the contents of MBEF, mailboxes are read or written. Reading an incoming
mailbox byte clears the corresponding status bit in MBEF.
OMB
IMB
Bits 31:0
Bits 31:0
PCI outgoing mailboxes
PCI incoming mailboxes
4. Clear the interrupt source. The PCI INTA# signal is deasserted by clearing the interrupt request. The request
is cleared by writing a 1 to the appropriate bit.
INTCSR
INTCSR
Bit 17
Bit 16
Clear PCI incoming mailbox interrupt
Clear PCI outgoing mailbox interrupt
Servicing the Add-On mailbox interrupt (IRQ# Asserted):
1. Identify the interrupt source(s). Multiple interrupt sources are available on the S5320. The interrupt service
routine must verify that a mailbox generated the interrupt (and not some other interrupt source).
AINT
AINT
AINT
Bit 23
Bit 17
Bit 16
Add-On interrupt asserted
Add-On outgoing mailbox interrupt indicator
Add-On incoming mailbox interrupt indicator
2. Check mailbox status. The mailbox status bits indicate which mailbox bytes must be read or written.
AMBEF
AMBEF
Bits 31:28
Bits 15:12
Empty Add-On outgoing mailbox bytes
Full Add-On incoming mailbox bytes
3. Access the mailbox. Based on the contents of AMBEF, mailboxes are read or written. Reading the incoming
mailbox byte clears the corresponding status bit in AMBEF.
AIMB
Bits 31:0
Bits 31:0
Add-On incoming mailbox
Add-On outgoing mailbox
AOMB
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4. Clear the interrupt source. The Add-On IRQ# signal is deasserted by clearing the interrupt request. The
request is cleared by writing a 1 to the appropriate bit.
AINT
AINT
Bit 17
Bit 16
Clear Add-On outgoing mailbox interrupt
Clear Add-On incoming mailbox interrupt
NOTE: For an incoming mailbox interrupt, step 3 involves accessing the mailbox. To allow the incoming mailbox
interrupt logic to be cleared, the mailbox status bit must also be cleared. Reading an incoming mailbox clears the
status bits. Another option for clearing the status bits is to use the Mailbox Flag Reset bit in the RCR and ARCR
registers, but this clears all status bits, not just a single mailbox byte. For outgoing mailbox interrupts, the status bit
was already cleared prior to the generation of the interrupt. As a result, the mailbox does not need to be read.
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ADD-ON LOCAL BUS INTERFACE
Data Sheet
The DQMODE signal configures the data path width
for all Add-On Operation register accesses, except for
the Pass-Thru Data and Address registers. When
DQMODE is low, DQ is configured as a 32-bit data
bus. When DQMODE is high, DQ is configured as a
16-bit data bus. For 16-bit operation, BE3# is rede-
fined as ADR1, providing an extra address input, and
BE2# is unused. ADR1 selects the low or high words
of the 32-bit S5320 Add-On Operation Registers.
This chapter describes the Add-On Local bus interface
of the S5320. The S5320 is designed to support con-
nection to a variety of microprocessor buses and/or
peripheral devices. The Add-On interface controls
S5320 operation through the Add-On Operation Reg-
isters accessed through the 32 bit local bus.
The Add-On local bus interface is synchronous to
ADCLK. ADCLK is a 0-40 MHz clock input which can
be configured as asynchronous to the PCI clock or
synchronous when connected to the S5320 BPCLK
output. The following sections describe the various
interfaces to the PCI bus and how they are accessed
from the Add-On bus.
ADD-ON S5320 REGISTER ACCESSES
The S5320 Add-On bus is very similar to that of a
memory or peripheral device found in a microproces-
sor-based system. A 32-bit data bus with individual
read and write strobes, a chip select and byte enables
are provided.
ADD-ON INTERFACE SIGNALS
Register Access Signals
The Add-On bus provides a number of system signals
to allow Add-On logic to monitor PCI bus activity, to
indicate status conditions (interrupts), and to configure
the S5320 Add-On bus.
Register accesses to the S5320 Add-On Operation
Registers are synchronous to the Add-On input clock
(ADCLK). The following signals are required to com-
plete a register access to the S5320.
SYSTEM SIGNALS
BE[3:0]# Byte Enable Inputs. These signals identify
which bytes of the DQ bus are valid during Add-
On bus transactions. BE0# indicates valid
DQ[7:0], BE1# a valid DQ[15:8], etc. When DQ is
configured for 16-bit operation, BE2# is not
defined and BE3# becomes ADR1.
BPCLK is a buffered version of the PCI clock. The PCI
clock can operate from 0 MHz to 33 MHz.
SYSRST# is a buffered version of the PCI reset signal,
and may also be toggled by host application software
through bit 24 of the Reset Control Register (RCR).
ADR[6:2] Address Register Inputs. These pins
address a specific Add-On Operation Register
within the S5320. When DQ is configured for 16-
bit operation, an additional input, ADR1 is avail-
able to allow the 32-bit operation registers to be
accessed in two 16-bit cycles.
IRQ# is the PCI interrupt request output to the Add-On
bus. This signal is active low and can indicate multiple
conditions. Add-On interrupts can be generated from
the mailbox interface or to indicate start of BIST. The
conditions which will generate an IRQ# due to mailbox
activity are discussed in the mailbox chapter. The
IRQ# output is deasserted when acknowledged by
writing a 1 to the corresponding interrupt bit in the
Add-On Interrupt Control/Status Register (AINT). See
Table 30.
RD# Read Enable Input.
WR# Write Enable Input.
SELECT# Chip Select Input. This input indicates RD#,
WR#, ADR[6:2] and BE[3:0] are valid.
The PTMODE signal (Pass-Thru Mode) controls the
Pass-Thru interface only. Asserting it will configure the
Pass-Thru in Passive mode and low will configure the
Pass-Thru in Active mode.
DQ[31:0] Bi-directional Data Bus. These I/O pins are
the Add-On data bus.
S5320 General Register Accesses
ADDINT# is an Add-On interrupt input pin. When
asserted, it will cause the PCI interrupt output pin
(INTA#) to assert. The ADDINT# is a level-sensitive
input. Any number of Add-On peripheral interrupt
sources can drive this input. There must be a pull-up
resistor on the board to pull it high when inactive. This
interrupt has to be enabled by Bit 13 of the INTCSR. It
is the responsibility of the PCI host to clear the inter-
rupt source of ADDINT# in order to have the pending
interrupt deasserted.
For many Add-On applications, Add-On logic does not
operate at the PCI bus frequency. This is especially
true for Add-On designs implementing a microproces-
sor, which may be operating at a lower or higher
frequency.
The RD# and WR# inputs become enables, using
ADCLK to clock data into and out of registers. All
inputs are sampled on the rising edge of ADCLK.
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Figures 58 and 59 show basic operation register
access timing relationships. Detailed AC timings are in
Electrical and AC Characteristics. Chapter 10.
S5320 16-bit Mode Register Accesses
In the S5320 there are two methods of defining the
Add-On DQ width: one is by using the DQMODE pin
and the other is to define a Pass-Thru region size of 8,
16 or 32 bits. The DQMODE pin allows external 16-bit
devices to access S5320 Operation Registers without
additional logic. The external device is able to write
and read the S5320 32-bit registers in two 16-bit cycle
accesses. When performing an Operation Register
access with the DQMODE pin set for 16 bits
(DQMODE = 1), only the lower half (DQ[15:0]) of the
DQ bus is driven during a read or write. The S5320
internally steers the data bus and the byte enables
based on the BE3# input. It is important to note that
the DQMODE pin has no effect on accesses to the
Pass-Thru Data Register. For non 32-bit Pass-Thru
regions, the region size should be used instead. In 16-
bit mode, a 32-bit DWORD write is performed in two
cycles:
For reads (Figure 58), data is driven onto the DQ bus
on the ADCLK cycle after RD# is sampled asserted.
When RD# is not asserted, the DQ outputs float. The
address, byte enable, and RD# inputs must meet
setup and hold times relative to the rising edge of
ADCLK.
For writes (Figure 59), data is clocked into an opera-
tion register on the rising edge of ADCLK in which
WR# is sampled asserted. Address, byte enables,
WR# and data must all meet setup and hold times rel-
ative to the rising edge or ADCLK.
Figure 58. Read Operation Register
ADCLK
SELECT#
Cycle 1: DQ[15:0] is driven with the lower-WORD.
WR#, ADR and SELECT# are asserted, BE[1:0]# indi-
cates which bytes of the WORD are valid, and BE3#
(which has been redefined as ADR1 when in 16-bit
mode) is set to zero, indicating that the write is for the
lower-WORD of the DWORD transfer. DQ[15:0] will be
written to the bottom 16 bits of the internal 32-bit regis-
ter (be it a Mailbox, Pass-Thru configuration register,
etc.).
ADR[6:2]
BE[3:0]#
RD#
VALID
VALID
DQ[31:0]
VALID
Cycle 2: DQ[15:0] is driven with the upper-WORD.
WR#, ADR and SELECT# are asserted, BE[1:0]# indi-
cate which bytes of the WORD are valid, and BE3# is
set to one, indicating that the write is for the upper-
WORD of the DWORD transfer. DQ[15:0] will be writ-
ten to the upper 16-bits of the internal 32-bit register.
Figure 59. Write Operation Register
ADCLK
SELECT#
ADR[6:2]
BE[3:0]#
WR#
VALID
VALID
Transfered
DQ[31:0]
DATA
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Data Sheet
Figure 60. 16 Bit Mode Operation Register DWORD Write/Read
0
1
2
3
4
5
6
7
8
9
10
11
12
13
ADCLK
DQMODE
SELECT#
ADR[6:2]
BE3#
60h
10b
60h
00b
BE[1:0]#
WR#
00b
01b
RD#
DQ[15:0]
5678h
1234h
1234
5678h
Figure 60. 16 Bit Mode Operation Register DWORD
Write/Read Figure 60 shows an example of a DWORD
write of 12345678h using a 16 bit-mode write transfer,
and is described as follows:
Figure 60 also shows a DWORD read of 12345678h
from the same register, using a 16-bit mode read
transfer, and is described as follows:
Clock 6: ADR[6:2], SELECT# and RD# are asserted.
BE3# is high, indicating the upper WORD of the regis-
ter is to be driven onto DQ[15:0] and BE[1:0]# is 00h
indicating both bytes of the WORD are to be driven.
Clock 1: ADR[6:2], BE[3:0], SELECT# and WR# are
driven, DQ[15:0] is driven with the data to be written.
BE3# is low indicating that the DQ bus data is to be
written to the lower WORD of the register. BE[2:0]# is
00h, indicating that both bytes on the DQ[15:0] bus are
valid and should be written to the register indicated by
ADR[6:2].
Clock 7: The S5320 drives 1234h onto DQ[15:0] as a
result of the read issued during the previous cycle.
BE3# is next driven low to indicate the lower WORD of
the register is to be driven onto DQ[15:0]. BE[1:0]# is
00h indicating both bytes of the WORD should be
driven onto DQ[15:0]. Note: in the event that BE[0]#
was 1b, DQ[7:0] would NOT be driven during Clock 8,
it would remain tri-state. The only exception to this is if
ADR[6:2] indicated the Pass-Thru Data Register,
where all of DQ[15:0] would be driven, regardless of
the state of BE[1:0]#.
Clock 2: The rising edge of clock 2 writes 5678h into
the lower WORD of the register. 1234h is driven onto
the DQ[15:0] bus. BE3# is driven high, indicating the
DQ bus data is to be written to the upper WORD of the
register. BE[2:0]# is 10h indicating that the lower byte
of the WORD on DQ[15:0] bus is valid. This example
shows how the BEs function.
Clock 3: The rising edge of clock 3 writes 34h into the
lower byte of the upper WORD of the register.
BE[2:0]# is “01” indicating the upper byte on DQ[15:0]
is valid.
Clock 8: On the rising-edge, Add-On logic latches
data 1234h. The S5320 drives 5678h onto DQ[15:0]
as a result of the read issued during the previous
cycle. ADR[6:2], SELECT#, RD# and BE[3:0]# are
deasserted, completing the transfer.
Clock 4: The rising edge of clock 4 writes 12h into the
upper byte of the upper WORD of the register.
12345678h is in the register selected by ADR[6:2].
SELECT#, ADR[6:2], WR#, BE[3:0]# and DQ are
deasserted. No read or write occurs on the rising edge
of clocks 5 and 6.
Clock 9: On the rising-edge, Add-On logic latches
data 5678h. DQ[15:0] returns to tri-state as RD# was
sampled deasserted.
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MAILBOX OVERVIEW
Data Sheet
READ FIFO OVERVIEW
For a detailed description of the Mailbox interface, ref-
erence previous Mailbox Overview section.
The S5320 has an 8x32-bit Read FIFO, which allows
data to be prefetched from the add on bus. The user
can program the device to prefetch 2,4 or 8 DWORDs
for each region or disable prefetching completely. For
the first PCI read cycle, the device will request data
from the Add-On bus. As the PCI bus reads the FIFO,
and until after the PCI transfer has finished, the S5320
will prefetch the next N (2, 4 or 8) DWORDs from the
Add-On. The prefetched data is valid as long as the
PCI read addresses are sequential. If the current PCI
read address is not the previous address plus four, or
if a PCI write access occurs, the S5320 will flush the
FIFO and start a new transfer at this address. Flushing
the FIFO will incur a minimum loss of one PCI clock
cycle or possibly more if the Add-On logic has not fin-
ished its current prefetching transfer. Note that
prefetching is not performed past the upper limit of the
base address region. In fact, prefetching is disabled
when the PCI address is eight DWORDs from the end
of the region.
PASS-THRU OVERVIEW
The S5320 provides data transfers between the PCI
bus and the user local bus through the Pass-Thru data
channel. Using a handshaking protocol with Add-On
device(s), the PCI bus can directly access data on the
Add-On bus and internal S5320 Operation registers.
The Pass-Thru data channel is very flexible for user
memory access or accessing registers within peripher-
als on the Add-On bus. Pass-Thru operation in Active
or Passive mode requires an external non-volatile
memory device to define and configure the Pass-Thru
channel region sizes and bus widths.
Four user-configurable Pass-Thru regions are avail-
able in the S5320. Each region is defined by a PCI
Configuration Base Address Register (BADR1-4). A
Pass-Thru region defines a block of predefined user
space address in either host memory or I/O areas.
Memory mapped regions can be requested below 1
Mbyte (Real Mode address space for a PC). Each
region is configurable for bus widths of 8, 16 or 32 bits
for the Add-On bus interface.
Prefetch cycles are always 32 bits regardless of Add-
On bus width or the byte enables requested by the
PCI.
FUNCTIONAL DESCRIPTION
The S5320 Pass-Thru channel supports single data
transfers as well as burst transfers. When accessed
with burst transfers, the S5320 supports data transfers
at the full PCI bandwidth. The data transfer rate is only
limited by the PCI initiator performing the access and
the speed of the Add-On bus logic.
The S5320 Pass-Thru interface supports both single
cycle (one data phase) and burst accesses (multiple
data phases).
Pass-Thru Transfers
The Pass-Thru interface offers two different modes of
operation: Passive mode and Active mode. Passive
mode is configured by strapping the pin PTMODE
high, while Active mode is configured by strapping the
pin PTMODE Low.
WRITE FIFO OVERVIEW
For PCI write cycles, the S5320 has an 8x32-bit Write
FIFO to increase performance for slow Add-On
devices. When the FIFO is enabled, the S5320 will
accept data transfers from the PCI bus at zero wait
states until the FIFO is full. The device continues to fill
the FIFO as long as the transfers are sequential. The
S5320 can continue accepting sequential write PCI
transfers as long as the FIFO is not full and the bound-
ary of the Pass-Thru region defined by the Base
Address Register is not crossed. If the next data
access is for a non-sequential address, the FIFO must
first be emptied by the Add-On peripheral in order for
the next transfer to occur.
PTMODE = 1 - Passive Operation
PTMODE = 0 - Active Operation
Passive operation allows external Add-On bus periph-
erals to provide read and write control signals to the
S5320. The user drives SELECT#, RD#, WR#.
ADR[6:2] and PTRDY#. The Add-On bus logic has the
flexibility of determining when it wants to perform
reads/writes.
Some applications may require that a PCI address be
passed for Pass-Thru accesses. For example, a 4-
Kbyte Pass-Thru region on the PCI bus may corre-
spond to a 4-Kbyte block of SRAM on the Add-On
card. If a PCI initiator accesses this region, the Add-
On would need to know the offset within the memory
device to access. The Pass-Thru Address Register
(APTA) allows Add-On logic to access address infor-
The Write FIFO can be disabled, thus configuring the
FIFO to act as a single DWORD data buffer. In this
case, PCI Write Posting is not possible.
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Data Sheet
mation for the current PCI cycle. When the PCI bus
performs burst accesses, the APTA register is incre-
mented by the S5320 to reflect the address of the
current data phase. PTNUM[1:0] is used to determine
what region owns the current data access.
For PCI reads from the Add-On, the S5320 asserts the
Pass-Thru status signals to indicate to the Add-On that
data is required. The Add-On logic should write the
requested data into the Pass-Thru Read FIFO. The
S5320 will assert TRDY# to the PCI bus after the Add-
On logic has transferred data into the FIFO. As long as
data is in the FIFO, and PCI read data is still
requested, TRDY# will continue to be asserted. If the
Add-On cannot provide data quickly enough, the
S5320 signals a disconnect to the PCI bus. This
allows the PCI bus to perform other tasks, rather than
waiting for a slow target. The S5320 will prefetch data
if enabled.
For PCI writes to the Add-On, the S5320 transfers
data from the PCI bus into the Pass-Thru Write FIFO.
When the Pass-Thru write FIFO becomes not empty,
the S5320 asserts the Pass-Thru status signals to indi-
cate to the Add-On that data is present. The Add-On
logic will then read data from the FIFO. The S5320
continues accepting write data from the PCI initiator as
long as the 8x32 FIFO is not full.
Signal
Function
PTATN#
This output indicates a Pass-Thru access needs servicing.
PTBURST#
This output indicates that the current Pass-Thru access is a PCI burst transfer or a single cycle transfer.
PTBURST# is deasserted immediately after the second to last burst data has been transferred on the PCI
side. PTBURST# is also active during prefetch cycles.
PTNUM[1:0] These outputs indicate which Pass-Thru region decoded the PCI address.
PTBE[3:0]#
These outputs indicate which data bytes are valid (PCI writes), or requested (PCI reads). See timing dia-
grams for further details. PTBE0# = 0 Byte 0 is valid, PTBE1# = 0 Byte 1 is valid, PTBE# = 0 Byte 2 is valid,
PTBE3# = 0 Byte 3 is valid.
PTWR
This output indicates if the Pass-Thru access is a PCI read or a write.
PTADR#
When asserted, this pin drives the Pass-Thru Address Register contents onto the Add-On data bus. This
input enables the DQ[31:0] data bus to become active immediately. There is NO pipeline delay from PTADR#
to DQ, as there is from RD# to DQ. As result, this is an asychronous input.
PTRDY#
ADCLK
In Passive mode, this input indicates the current Pass-Thru transfer has been has been completed by the
Add-On. In Active mode, this input indicates that wait states are to be inserted for the next transfer.
Input Add-On clock (to synchronize Pass-Thru data register accesses).
Pass-Thru Status/Control Signals
ated by the PCI bus. The Pass-Thru interface is
designed to allow Add-On logic to function without
knowledge of PCI bus activity. Add-On logic only
needs to react to the Pass-Thru status signals. The
S5320 PCI device independently interacts with the
PCI initiator to control data flow between the devices.
The S5320 Pass-Thru registers are accessed using
the Add-On register access pins. The Pass-Thru
Address Register (APTA) can, optionally, be accessed
using a single, direct access input, PTADR#. Pass-
Thru cycle status indicators are provided to control
Add-On logic based on the type of Pass-Thru access
occurring (single cycle, burst, etc.). The signals in the
table above are provided for Pass-Thru operation:
The following sections describe the PCI and Add-On
bus interfaces. The PCI interface description provides
a basic overview of how the S5320 interacts with the
PCI bus, and may be useful in system debugging. The
Add-On interface description indicates functions
required by Add-On logic and details the Pass-Thru
handshaking protocol.
BUS INTERFACE
The Pass-Thru data channel allows PCI initiators to
read or write to resources on the Add-On bus. A PCI
initiator may access the Add-On with single data
phase cycles or multiple data phase bursts. The Add-
On interface implements Pass-Thru status and control
signals used by logic to complete data transfers initi-
PCI Bus Interface
The S5320 device examines all PCI bus cycle
addresses. If the address associated with the current
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cycle decodes to one of the S5320 Pass-Thru regions,
DEVSEL# is asserted. If the Pass-Thru logic is cur-
rently idle (not busy finishing a previous Pass-Thru
operation), the bus cycle type is decoded and the Add-
On Pass-Thru status outputs are set to initiate a trans-
fer on the Add-On bus. The following sections
describe the behavior of the PCI interface for Pass-
Thru accesses to the S5320. Single cycle accesses,
burst accesses, and target-initiated retries are
detailed.
burst access, the Pass-Thru status indicators notify
the Add-On logic.
For Pass-Thru burst writes, the S5320 responds
immediately (asserting TRDY#). The S5320 transfers
the first data phase of the burst into the FIFO, and
stores the PCI address in the Pass-Thru Address Reg-
ister (APTA). The S5320 can accept up to 8 DWORDs
from the PCI bus before transferring one DWORD on
the Add-On side. If the Add-On bus is slow, the device
will keep the FIFO full until the data is ready to be
transferred by the slow Add-On bus. If the Add-On bus
is fast at accepting the data, then the FIFO will con-
tinue an indefinite burst, or until the PCI master is
forced to relinquish the bus for arbitration reasons, or
the PCI bus master has gone beyond the Pass-Thru
region address space. For burst accesses, the APTA
is automatically incremented by the S5320 for each
data phase.
PCI Pass-Thru Single Cycle Accesses
A single cycle transfer is the simplest of PCI bus trans-
actions. Single cycle transfers have an address phase
and a single data phase. The PCI bus transaction
starts when an initiator drives address and command
information onto the PCI bus and asserts FRAME#.
The initiator always deasserts FRAME# before the last
data phase. For single cycle transfers, FRAME# is
only asserted during the address phase (indicating the
first data phase is also the last).
For Pass-Thru burst reads, the S5320 claims the PCI
cycle (asserting DEVSEL#). The request for data is
passed on to Add-On logic and the PCI address is
stored in the APTA register. The device will prefetch
data if the feature is enabled. The S5320 then drives
the requested data on the PCI bus and asserts TRDY#
to begin the next data phase. The APTA register is
automatically incremented by the S5320 after each
data phase.
When the S5320 sees FRAME# asserted, it samples
the address and command information to determine if
the bus transaction is intended for it. If the address is
within one of the defined Pass-Thru regions or internal
PCI Operation Register, the S5320 accepts the trans-
fer (asserts DEVSEL#), and stores the PCI address in
the Pass-Thru Address Register (APTA).
PCI Disconnect Conditions
For Pass-Thru writes, the S5320 responds immedi-
ately (asserting TRDY#) and transfers the data from
the PCI bus into the write FIFO as long as the write
FIFO is not full. The S5320 then indicates to the Add-
On interface that a Pass-Thru write is taking place and
waits for Add-On logic to complete the transfer. Once
the S5320 has captured the data from the PCI bus, the
transfer is finished from the PCI bus perspective, and
the PCI bus becomes available for other transfers.
Before discussing what causes the S5320 to issue a
disconnect on the PCI bus, it might be useful to distin-
guish between a disconnect and retry. A retry occurs
when a PCI initiator does not receive a single TRDY#,
but is issued a STOP# instead. In this case, no data is
transferred. The PCI 2.1 spec states that the initiator is
required to come back and complete this transfer. A
disconnect occurs after at least one data phase was
completed (TRDY# and IRDY# asserted simulta-
neously). This occurs when a STOP# is asserted
either with a TRDY# or after a TRDY#/IRDY# transfer.
In this case, the initiator is not required to return to
complete the transfer.
For Pass-Thru reads, the S5320 indicates to the Add-
On interface that a Pass-Thru read is taking place and
waits for Add-On logic to complete the cycle. If the
Add-On cannot complete the cycle quickly enough, the
S5320 requests a retry from the initiator. The S5320
will fetch one DWORD from the Add-On side, and
store it in the Read FIFO.
In some applications, Add-On logic may not be able to
respond to Pass-Thru accesses quickly. In this situa-
tion, the S5320 will Retry the cycle on the PCI side.
For PCI write cycles, the S5320 will accept up to 8
DWORDs without a disconnect or until the FIFO is full.
For a PCI read cycle, the first access needs to take
less than 16 PCI clocks, otherwise the device will
issue a Retry. A subsequent read transfer must take
less than 8 PCI clocks, otherwise the device will issue
a disconnect.
PCI Pass-Thru Burst Accesses
For PCI Pass-Thru burst accesses, the S5320 cap-
tures the PCI address and determines if it falls into one
of the defined Pass-Thru regions. Accesses that fall
into a Pass-Thru region or internal PCI Operation Reg-
ister are accepted by asserting DEVSEL#. The S5320
monitors FRAME# and IRDY# on the PCI bus to iden-
tify burst accesses. If the PCI initiator is performing a
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With many devices, particularly memories, the first
access takes longer than subsequent accesses
(assuming they are sequential and not random). For
this reason, the PCI specification allows 16 clocks to
respond to the first data phase of a PCI cycle and 8
clocks for subsequent data phases (in the case of a
burst) before a retry/disconnect is issued by the
S5320.
Add-On cannot complete the access within 16 clocks,
a retry is requested (STOP# asserted without data
transfer). If the Add-On manages to complete the data
transfer into the PT Read FIFO, but after a retry was
issued, the data is held in the FIFO until the original
master comes back to read it. All subsequent PCI
accesses to a Pass-Thru address other than the one
corresponding to the data in the FIFO will be termi-
nated with a PCI retry. Only a PCI access with a
matching address can access the data in the PT Read
FIFO, and thus release the Pass-Thru region for other
accesses.
The S5320 also requests a disconnect if an initiator
attempts to burst past the end of a Pass-Thru region.
The S5320 updates the Pass-Thru Address Register
(APTA) for each data phase during bursts, and if the
updated address is not within the current Pass-Thru
region, a disconnect is issued. Accesses to undefined
addresses will cause the PCI host to receive a Master
Abort cycle (no DEVSEL# is asserted by the S5320).
If the Add-On is busy performing a Pass-Thru write
operation when a PCI read occurs, the S5320
requests an immediate retry. If the Add-On is busy per-
forming a Pass-Thru read operation when another PCI
read occurs, the S5320 determines whether the read
is a retry from a previous access, and if so, attempts to
continue the read where it left off. If the address is
non-sequential, the new access is issued a retry. This
allows the PCI bus to perform other operations. S5320
PCI Operation Registers may be accessed while the
Add-On is still completing a Pass-Thru access. Only
other Pass-Thru region accesses receive retry
requests.
For example, a PCI system may map a 512 byte Pass-
Thru memory region to 0DC000h to 0DC1FFh. A PCI
initiator attempts a four DWORD burst with a starting
address of 0DC1F8h. The first and second data
phases complete (filling the DWORDs at 0DC1F8h
and 0DC1FCh), but the third data phase causes the
S5320 to issue a disconnect. This forces the initiator to
present the address 0DC200h on the PCI bus. If this
address is part of another S5320 Pass-Thru region,
the device accepts the access, but if not, a Master
Abort cycle occurs.
If the prefetch feature is enabled, the Pass-Thru inter-
face will prefetch data, which should improve the
performance on subsequent cycles to the same
region. In the event that the Add-On cannot prefetch
the first data before the S5320 issues a PCI retry, the
prefetched data will be held in the read FIFO until the
original master comes back to request it. Other PCI
read requests to the Pass-Thru region will be termi-
nated with immediate Retries.
PCI Write Disconnect
When the S5320 issues a disconnect for a PCI Pass-
Thru write, it indicates that the Add-On is still complet-
ing a previous non-sequential Pass-Thru access or the
FIFO is full. If the incoming access is a continuation of
a previous one, no disconnect is issued and the trans-
action can continue where it left off (perhaps due to a
previous disconnect or master time-out). PCI Opera-
tion Registers may be accessed while the Add-On is
still completing a Pass-Thru access. Only Pass-Thru
region accesses receive disconnect requests.
If the prefetch feature is disabled, a PCI read cycle is
not completed until the data is first transferred from the
Add-On bus into the PT Read FIFO. The device will
not prefetch, but will only request data from the Add-
On bus after the PCI bus has requested the data.
Pass-Thru bursts will not be performed in this case. In
the event that a non-prefetchable Add-On cannot pro-
vide the second (or third, or fourth...) data to the PCI
read request within the PCI Target Subsequent
Latency period (eight PCI clocks), the S5320 will issue
a PCI disconnect (STOP# asserted with data transfer).
If the Add-On manages to transfer the second (or
third, or fourth...) data to the PT Read FIFO, but after
the disconnect, the data may be held in the FIFO until
the original master comes back to read it. Depending
upon the setting of the Retry Flush Enb bit, the data is
held in the FIFO, and all other PCI read requests will
be terminated with immediate Retries.
PCI Read Disconnect
If the S5320 issues a disconnect for a PCI Pass-Thru
read, this indicates that the Add-On could not com-
plete the read in the required time (16 clocks for the
first data phase, 8 PCI clocks for the 2nd or later data
phases).
When the PCI performs a read to a Pass-Thru region,
the Add-On device must complete a Pass-Thru data
transfer by writing the appropriate data into the Pass-
Thru Data FIFO (APTD). If the Add-On can perform
this before the required time (see above), the S5320
asserts TRDY# to complete a PCI read transfer. If the
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S5320 PASSIVE MODE OPERATION
Data Sheet
Clock 2: SELECT#, ADR[6:2] and BE[3:0]# inputs are
driven to read the Pass-Thru Write FIFO at offset 2Ch.
DQ[31:0] is driven one clock after RD# and SELECT#
are asserted. PTRDY# is asserted, indicating that the
transfer is complete.
The Pass-Thru address and data registers can be
accessed as Add-On operation registers. The Pass-
Thru FIFO is updated on the rising edge of ADCLK.
For this reason, all Pass-Thru inputs must be synchro-
nous to ADCLK. In the following sections the Add-On
Pass-Thru interface is described for Pass-Thru single
cycle accesses, burst accesses, target-requested
retries, and when using 8-bit and 16-bit Add-On data
buses.
Clock 3: PTBE[3:0] will update one clock after RD# is
asserted to indicate which bytes have not yet been
read. The data is also driven on the DQ bus since RD#
was asserted a clock earlier. Since PTRDY# was sam-
pled asserted, PTATN# is deasserted and the Pass-
Thru access is complete. If the Add-On logic requires
more time to complete the read, PTRDY# can be
delayed, extending the Pass-Thru cycle.
Single-Cycle PCI to Pass-Thru Write
A single-cycle Pass-Thru write operation occurs when
a PCI initiator writes a single value to the Pass-Thru
region. PCI single cycle transfers consist of an
address phase followed by one data phase. During the
address phase of the PCI transfer, the S5320 stores
the PCI address into the Pass-Thru Address Register
(APTA). If the S5320 determines that the address is
within one of its defined Pass-Thru regions, it captures
the PCI data into the FIFO.
Clock 4: As PTATN# is deasserted, the Pass-Thru
access is complete, and the S5320 can accept new
Pass-Thru accesses starting on the next clock. The
other Pass-Thru signals can also change state (in
anticipation of a new transfer). The S5320 stops driv-
ing the DQ bus as RD# and SELECT# were not valid
on the previous cycle.
Figure 62 shows a single cycle Pass-Thru write for the
Passive Mode using the Pass-Thru address informa-
tion. This provides PCI cycle address information to
select a specific address location within an Add-On
memory or peripheral. Add-On logic may latch the
address for use during the data transfer (if PTADR#
was asserted). Typically, the entire 32-bit address is
not required. The Add-On may implement a scheme
where only the required number of address bits are
latched. It may also be useful to use the Pass-Thru
region identifiers, PTNUM[1:0], as address lines. For
example, Pass-Thru region 1 might be a 64K block of
SRAM for data, while Pass-Thru region 2 might be
64K of SRAM for code storage (downloaded from the
host during initialization). Using PTNUM0 as address
line A16 allows two unique add-on memory regions to
be defined.
Figure 61 shows a single cycle Pass-Thru write
access in the Passive Mode. The Add-On must read
the data stored in the FIFO and transfer it to its desti-
nation. If the proper SELECT#, ADR[6:2] and BE[3:0]#
signals are present, the S5320 will drive data one
clock after RD# is asserted. It will stop driving data
after the rising edge of ADCLK when RD# has been
sampled deasserted.
Clock 0: The PCI bus cycle address information is
stored in the S5320 and later stored in the Pass-Thru
Address Register. The PCI address is recognized as a
write to Pass-Thru region 1. The PCI data is stored in
the S5320 Write FIFO.
Clock 1: Pass-Thru signals PTATN#, PTBURST#,
PTNUM[1:0], PTWR and PTBE[3:0] are driven to indi-
cate what action is required by Add-On logic. These
status signals are valid only when PTATN# is active.
Add-On logic can decode status signals upon the
assertion of PTATN#.
Unlike all other Add-On operation register reads, the
Add-On PTADR# input directly accesses the Pass-
Thru Address Register and drives the contents onto
the data bus during the same clock cycle. WR# must
not be asserted the same time as PTADR#, or there
would be contention on the DQ bus! However, it is per-
mitted to assert RD# and PTADR# during the same
cycle. This is because all reads performed with RD#
are pipe-lined, while address reads with PTADR# are
not pipe-lined.
PTATN# Asserted. Indicates a Pass-Thru access is
pending
PTBURST# Deasserted. The access has a single data
phase.
PTNUM[1:0] 1h. Indicates the access is to Pass-Thru
region 1.
PTWR Asserted. The Pass-Thru access is a write.
PTBE[3:0]# 0h. Indicates the Pass-Thru access has all
bytes valid.
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Figure 61. PCI To Add-On Passive Write
PTWR and PTBE[3:0] will update on the next rising
edge of ADCLK.
0
1
2
3
4
5
Clock 1: Pass-Thru signals PTATN#, PTBURST#,
PTNUM[1:0], PTWR and PTBE[3:0] are driven to indi-
cate what action is required by Add-On logic. These
status signals are valid only when PTATN# is active.
Add-On logic can decode status signals upon the
assertion of PTATN#.
ADCLK
PTATN#
PTBURST#
PTNUM[1:0]
PTWR
1h
PTATN# Asserted. Indicates Pass-Thru access is
pending.
PTBE[3:0]
SELECT#
ADR[6:2]
BE[3:0]#
RD#
0h
Fh
PTBURST# Not asserted. The access has a single
data phase.
PTNUM[1:0] 1h. Indicates the access is to Pass-Thru
region 1.
2Ch
0h
PTWR Asserted. The Pass-Thru access is a write.
PTBE[3:0]# 0h. Indicate the Pass-Thru has all bytes
valid.
DQ[31:0]
PTRDY#
PTDATA
Clock 2: The PTADR# input is asserted to read the
Pass-Thru Address Register. The assertion of
PTADR# will immediately cause the address to be
driven on the DQ bus. RD#, SELECT#, byte enable,
and the address inputs are asserted to read the Pass-
Thru Data Register at offset 2Ch. DQ[31:0] is driven
one clock after RD# and SELECT# are asserted.
Asserting PTADR# and RD# at the same time will save
a clock cycle, since the assertion of the RD# won’t
cause the data to be driven until a clock later. The
Add-On also asserts PTRDY#, indicating that the cur-
rent transfer is complete.
Figure 62. PCI To Add-On Passive Write w/Pass-Thru
Address
0
1
2
3
4
ADCLK
PTATN#
PTBURST#
PTNUM[1:0]
PTWR
Clock 3: PTBE[3:0] are updated to indicate which
bytes have not yet been read. Data is driven on the
DQ bus because RD# was asserted a clock earlier.
The Add-On logic reads the data and deasserts
PTRDY#. As PTRDY# was sampled asserted,
PTATN# is immediately deasserted and the Pass-Thru
access is completed with the next clock. If add-on
logic requires more time to read the Pass-Thru Data
Register (slower memory or peripherals), PTRDY#
can be delayed, extending the cycle.
1h
PTBE[3:0]
SELECT#
0h
Fh
ADR[6:2]
BE[3:0]#
RD#
2Ch
0h
Clock 4: As PTATN# is deasserted, the Pass-Thru
access is complete, and the S5320 can accept new
Pass-Thru accesses starting on the next clock. The
other Pass-Thru signals can also change (in anticipa-
tion of a new transfer). The S5320 stops driving the
DQ bus as RD# and SELECT# were not valid on the
previous cycle.
DQ[31:0]
PTADR#
PTRDY#
A DDR
DATA
Single-Cycle PCI to Pass-Thru Read
Clock 0: The address is recognized as a PCI write to
Pass-Thru region 1. The PCI bus write address is
stored in the Pass-Thru Address Register. The PCI
bus write data is stored in the S5320 Write FIFO. Add-
On bus signals PTATN#, PTBURST#, PTNUM[1:0],
A single-cycle PCI to Pass-Thru read operation occurs
when a PCI initiator reads a single value from a Pass-
Thru region. PCI single cycle transfers consists of an
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address phase followed by a single data phase. If the
S5320 determines that the address is within one of its
defined Pass-Thru regions, it indicates to the Add-On
a write to the Pass-Thru Data Register (APTD) is
required.
PTBURST# Deasserted. The access has a single data
phase.
PTNUM[1:0] 2h. Indicates the access is to Pass-Thru
region 2.
PTWR Deasserted. The Pass-Thru access is a read.
Figure 63 shows a Passive Mode single cycle Pass-
Thru read access (Add-On write) using PTADR#. The
Add-On reads data from a source on the Add-On and
writes it to the APTD register.
PTBE[3:0]# 0h. Indicates the Pass-Thru access has all
bytes valid.
Clock 2: The PTADR# input is asserted to read the
Pass-Thru Address Register. The address can be
latched on the next rising-edge of ADCLK.
Figure 63. PCI To Add-On Passive Read
Clock 3: This turn-around cycle is required to avoid
contention on the DQ bus. Time must be allowed after
PTADR# is deasserted for the DQ outputs to float
before add-on logic attempts to write to the Pass-Thru
Read FIFO.
0
1
2
3
4
5
6
ADCLK
PTATN#
PTBURST#
PTNUM[1:0]
PTWR
Clock 4: WR#, SELECT#, BE[3:0]#, and ADR[6:2] are
asserted to write to the Pass-Thru Read FIFO at
address 2Ch. The Add-On logic drives the DQ bus
with the requested data. PTRDY# is also asserted,
indicating that the Add-On is finished with the transfer.
2h
PTBE[3:0]
SELECT#
ADR[6:2]
BE[3:0]#
WR#
0h
Fh
Clock 5: The data on the DQ bus is latched into the
Pass-Thru Read FIFO. As the S5320 samples
PTRDY# asserted, PTATN# is deasserted and the
Pass-Thru access is complete. PTBE[3:0] will update
one clock after WR# is asserted to indicate which
bytes have not yet been read. If add-on logic requires
more time to provide data (slower memory or peripher-
als), PTRDY# can be delayed, extending the cycle.
2Ch
0h
DQ[31:0]
PTRDY#
PTADR#
ADDR
DATA
Clock 6: As PTATN# is deasserted, the Pass-Thru
access is complete, and the S5320 can accept new
Pass-Thru accesses starting on the next clock. The
other Pass-Thru signals can also change (in anticipa-
tion of a new transfer).
PCI to Pass-Thru Burst Writes
Clock 0: The address is recognized as a PCI read of
Pass-Thru region 2. The PCI bus read address is
stored in the Pass-Thru Address Register. Add-On bus
signals PTATN#, PTBURST#, PTNUM[1:0], PTWR
and PTBE[3:0] will update on the next rising edge of
ADCLK.
A PCI to Pass-Thru burst write operation occurs when
a PCI initiator writes multiple values to a Pass-Thru
region. A PCI burst cycle consists of an address phase
followed by multiple data phases. If the S5320 deter-
mines that the requested address is within one of its
defined Pass-Thru regions, the initial PCI address is
stored into the Pass-Thru Address Register (APTA).
The data from each data-cycle is individually latched
into the Pass-Thru Data register (APTD) or Pass-Thru
Write FIFO.
Clock 1: Pass-Thru signals PTATN#, PTBURST#,
PTNUM[1:0], PTWR and PTBE[3:0] are driven to indi-
cate what action is required by Add-On logic. These
status signals are valid only when PTATN# is active.
Add-On logic can decode status signals upon the
assertion of PTATN#.
PTATN# Asserted. Indicates a Pass-Thru access is
pending.
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Figure 64. PCI to Add-On Passive Burst Write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
ADCLK
PTATN#
PTBURST#
PTNUM[1:0]
PTWR
3h
PTBE[3:0]
SELECT#
ADR[6:2]
BE[3:0]#
RD#
D1
D2
D3
D4
Fh
2Ch
0h
0h
0h
0h
DQ[31:0]
PTADR#
PTRDY#
ADDR
DATA1 DATA2 DATA3 DATA4
Figure 64 shows a Passive mode PCI to Add-On burst
write of four DWORDs. In the following example, Add-
On logic incorporates the use of PTADR# followed by
multiple data reads to the S5320. If Add-On logic does
not support burst accesses, PTADR# can be pulsed
for individual data reads. The S5320 automatically
increments the address in the APTA register during
PCI bursts. In this example PTRDY# is continually
asserted, indicating that Add-On logic is capable of
accepting one DWORD per clock cycle. In addition,
the PTBE[3:0] signals indicate a unique byte-enable
for each data transfer.
PTWR and PTBE[3:0] will update on the next rising
edge of ADCLK.
Clock 1: Pass-Thru signals PTATN#, PTBURST#,
PTNUM[1:0], PTWR and PTBE[3:0] are driven to indi-
cate what action is required by Add-On logic. These
status signals are valid only when PTATN# is active.
Add-On logic can decode status signals upon the
assertion of PTATN#.
PTATN# Asserted. Indicates Pass-Thru access is
pending.
PTBURST# Asserted. The access has multiple data
phases.
The Pass-Thru Write FIFO (or APTD) can be disabled
for bursts (do not accept PCI posted writes). In this
case, the PCI is allowed to write to only one FIFO
location and cannot continue bursting until the add-on
has read the data. PTBURST# is never asserted when
the PCI write FIFO is disabled. For this example, the
Write FIFO is enabled.
PTNUM[1:0] 3h. Indicates the access is to Pass-Thru
region 3.
PTWR Asserted. Indicates the access is a write.
PTBE[3:0]# D1. Indicates valid bytes for the first data
transfer.
Clock 2: The PTADR# input is asserted to read the
Pass-Thru Address Register. The RD#, BE#, ADR[6:2]
and SELECT# inputs are driven during this clock to
read the Pass-Thru Data Register contents onto the
DQ bus during the next clock. PTRDY# is asserted,
indicating that the first transfer is complete.
Clock 0: The address is recognized as a PCI write to
Pass-Thru region 1. The PCI bus write address is
stored in the Pass-Thru Address Register. The PCI
bus write data is stored in the S5320 write FIFO. Add-
On bus signals PTATN#, PTBURST#, PTNUM[1:0],
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Clock 3: The Add-On latches the address. Data 1 is
driven on the DQ bus as a result of the previous read.
As PTRDY# is sampled asserted, the PTBE# outputs
are updated to indicate which bytes are valid for the
second transfer. The BE[3:0]#, ADR[6:2], and
SELECT# inputs remain driven along with RD# to read
out the next data. PTRDY# remains asserted, indicat-
ing that the second transfer is complete.
On deasserts SELECT#, ADR[6:2], BE[3:0]#, RD# and
PTRDY#.
Clock 7: The Add-on logic stores DATA4 on the rising
edge of this clock. As PTATN# is deasserted, the
Pass-Thru access is complete, and the S5320 can
accept new Pass-Thru accesses starting on the next
clock. The other Pass-Thru signals can also change
state (in anticipation of a new transfer).
Clock 4: Add-On logic uses the rising edge of this
clock to store DATA1. DATA2 is driven on the DQ bus
as a result of the previous read. As PTRDY# is sam-
pled asserted, the PTBE# outputs are updated to
indicate which bytes are valid for the third transfer.
PTRDY# remains asserted, indicating that the third
transfer is complete.
Figure 65 illustrates a Passive mode transfer with a
burst of five DWORDs in a PCI to Pass-Thru burst
write with PTRDY# used to insert wait states. In some
applications, Add-On logic may not be required to
transfer data on every ADCLK and can use PTRDY#
to control the data rate transfer. In this example, Add-
On logic latches data every other clock cycle. RD# is
shown deasserted when PTRDY# is deasserted, but
could remain active during the entire Add-On burst. In
this case, the DQ would not go to tri-state between
reads, and the PTBE# outputs would lose some of
their significance (as they would transition one cycle
early as a result of the “unused” read).
Clock 5: Add-On logic uses the rising edge of this
clock to store DATA2. PTBURST# is deasserted indi-
cating that only a single data phase remains. DATA3 is
driven on the Add-On bus. The PTBE# outputs are
updated to indicate which bytes are valid for the last
transfer. PTRDY# remains asserted, indicating that the
current transfer is complete.
Clock 0: The address is recognized as a PCI write to
Pass-Thru region 0. The PCI bus write address is
stored in the Pass-Thru Address Register. The PCI
bus write data is stored in the S5320 write FIFO. Add-
On bus signals PTATN#, PTBURST#, PTNUM[1:0],
PTWR and PTBE[3:0] will update on the next rising
edge of ADCLK.
Clock 6: Add-on logic uses the rising edge of this
clock to store DATA3 from the S5320. PTRDY# sam-
pled completes the last data phase. As a result, the
S5320 deasserts PTATN#, and drives DATA4 onto the
DQ bus. As the Add-on sampled PTBURST# deas-
serted and PTATN# asserted, it recognizes that the
previous read was the last one. As a result, the Add-
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Figure 65. PCI to Add-On Passive Burst Write Using PTRDY# to assert Wait-States
0
1
2
3
4
5
6
7
8
9
10
11
12
13
ADCLK
PTATN#
PTBURST#
PTNUM[1:0]
PTWR
0h
PTBE[3:0]
SELECT#
ADR[6:2]
BE[3:0]#
RD#
D1
D2
D3
D4
D5
Fh
2Ch
0h
DQ[31:0]
PTADR#
PTRDY#
ADDR
DATA1
DATA 2
DATA 3
DATA 4
DATA 5
Figure 66. PCI to Add-On Passive Burst Read Access
0
1
2
3
4
5
6
7
8
9
ADCLK
PTATN#
PTBURST#
PTNUM[1:0]
PTWR
1h
PTBE[3:0]
SELECT#
ADR[6:2]
BE[3:0]#
WR#
D1
D2
D3
D4
Fh
2Ch
0h
DQ[31:0]
PTRDY#
PTADDR
DATA1
DATA2 DATA3 DATA4
PTADR#
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Clock 1: Pass-Thru signals PTATN#, PTBURST#,
PTNUM[1:0], PTWR and PTBE[3:0] are driven to indi-
cate what action is required by Add-On logic. These
status signals are valid only when PTATN# is active.
Add-On logic can decode status signals upon the
assertion of PTATN#.
Clock 7: Add-On logic uses the rising edge of this
clock to store DATA2. PTRDY# is sampled deas-
serted, so a wait state is activated. PTRDY# is
asserted to indicate that the Add-On is ready to accept
the next data transfer. RD# is also asserted, request-
ing DATA3 to be driven during the next clock cycle.
PTATN# Asserted. Indicates Pass-Thru access is
pending.
Clock 8: PTRDY# is sampled asserted, thus complet-
ing the current data-phase. DATA3 is driven on the DQ
bus, a result of a read during the previous cycle. The
PTBE# outputs are updated to indicate which bytes
are valid for the fourth transfer. Add-On logic is not fast
enough to store the next data, so a wait state is acti-
vated by deasserting PTRDY#. RD# is also
deasserted.
PTBURST# Asserted. The access has multiple data
phases.
PTNUM[1:0] 0h. Indicates the access is to Pass-Thru
region 3.
PTWR Asserted. Indicates the access is a write.
PTBE[3:0]# D1. Indicates valid bytes for the first data
transfer.
Clock 9: Add-On logic uses the rising edge of this
clock to store DATA3. PTRDY# is sampled deas-
serted, so a wait state is activated. PTRDY# is
asserted to indicate that the Add-On is ready to accept
the next data transfer. RD# is also asserted, request-
ing DATA4 to be driven during the next clock cycle.
Clock 2: Add-On logic samples PTATN# and
PTBURST# asserted, indicating the start of a burst.
The Add-On asserts PTADR# to read the Pass-Thru
Address Register. As it is not ready to receive any data
yet, it does not initiate a data read.
Clock 10: PTRDY# is sampled asserted, thus com-
pleting the current data-phase. PTBURST# is
deasserted, indicating that only one DWORD is left for
transfer. DATA4 is driven on the Add-On DQ bus, a
result of a read during the previous clock cycle. The
PTBE# outputs are updated to indicate which bytes
are valid for the last transfer. Add-On logic is not fast
enough to store the next data, so a wait state is acti-
vated by deasserting PTRDY#. RD# is also
deasserted.
Clock 3: Add-on logic latches the address. RD#,
BE[3:0]#, ADR[6:2], and SELECT# inputs are asserted
to select the Pass-Thru Data Register during the next
clock. PTRDY# is also asserted to indicate the com-
pletion of the first data phase.
Clock 4: As the S5320 sampled PTRDY# asserted,
the first data phase is completed DATA1 is driven on
the DQ bus, a result of the read from the previous
clock cycle. The PTBE# outputs are updated to indi-
cate which bytes are valid for the second transfer.
Add-on logic is not fast enough to store the next data,
so a wait state is activated by deasserting PTRDY#.
RD# is also deasserted.
Clock 11: Add-On logic uses the rising edge of this
clock to store DATA4. PTRDY# is sampled deas-
serted, so a wait state is activated. PTRDY# is
asserted to indicate that the add-on is ready to accept
the last data transfer. The add-on knows this is the last
transfer as it has sampled PTBURST# deasserted and
PTATN# asserted. RD# is also asserted, requesting
DATA5 to be driven during the next clock cycle.
Clock 5: Add-On logic uses the rising edge of this
clock to store DATA1. PTRDY# is sampled deas-
serted, so a wait state is activated. PTRDY# is
asserted to indicate that the Add-On is ready to accept
the next data transfer. RD# is also asserted, request-
ing DATA2 to be driven during the next clock cycle.
Clock 12: PTRDY# is sampled asserted, indicating
that the last transfer was completed. As a result,
PTATN# is deasserted. As the Add-On has also fin-
ished its transfer, it deasserts RD#, SELECT#,
BE[3:0]#. The last data, DATA5, is driven on the Add-
On DQ bus.
Clock 6: PTRDY# is sampled asserted, thus complet-
ing the current data-phase. DATA2 is driven on the DQ
bus, a result of a read during the previous clock cycle.
The PTBE# outputs are updated to indicate which
bytes are valid for the third transfer. Add-on logic is not
fast enough to store the next data, so a wait state is
activated by deasserting PTRDY#. RD# is also
deasserted.
Clock 13: Add-On logic uses the rising edge of this
clock to store DATA5. As PTATN# is deasserted, the
Pass-Thru access is complete, and the S5320 can
accept new Pass-Thru accesses starting on the next
clock. The other Pass-Thru signals can also change
state (in anticipation of a new transfer).
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Pass-Thru Burst Reads
address into the Pass-Thru Address Register (APTA).
If the S5320 determines that the address is within one
of its defined Pass-Thru regions, it indicates to the
Add-On that a write to the Pass-Thru Data Register or
Pass-Thru Read FIFO (APTD) is required.
A Pass-Thru burst read operation occurs when a PCI
initiator reads multiple DWORDs from a Pass-Thru
region. A burst transfer consists of a single address
and multiple data phases. The S5320 stores the PCI
Figure 67. PCI to Add-On Passive Burst Read
3
4
7
8
9
0
1
2
5
6
10
11
12
13
ADCLK
PTATN#
PTBURST#
PTNUM[1:0]
PTWR
0h
PTBE[3:0]#
SELECT#
ADR[6:2]
BE[3:0]#
WR#
D1
D2
D3
D4
Fh
2Ch
0h
DQ[31:0]
PTADR#
PTRDY#
ADDR
Data 1 Data 2
Data 3
Data 4
Figure 66 shows a Passive Mode Pass-Thru burst
read access (Add-On write) of four DWORDs, using
PTADR# to provide an address-phase.
PTBURST# Asserted. The access has multiple data
phases.
PTNUM[1:0] 1h. Indicates the access is to Pass-Thru
region 1.
Clock 0: PCI address information is stored in the
Pass-Thru Address Register. The address is recog-
nized as a PCI read of Pass-Thru region 1. Add-On
bus signals PTATN#, PTBURST#, PTNUM[1:0],
PTWR and PTBE[3:0] will update on the next rising
edge of ADCLK
PTWR Deasserted. Indicates the access is a read.
PTBE[3:0]# D1. Indicates valid bytes for the first data
transfer.
Clock 2: The Add-On logic has sampled PTATN# and
PTBURST# active, indicating that at least two read
data transfers are requested by the PCI. The Add-On
will start servicing the Burst Read transfer by first read-
ing the Pass-Thru Address via the PTADR# input. This
is an asynchronous read, meaning that the address
will appear on DQ after a propagation delay from the
assertion of PTADR#. In the event that the address is
not required, this cycle and the next could be skipped
(as the next clock provides a turn-around cycle).
Clock 1: Pass-Thru signals PTATN#, PTBURST#,
PTNUM[1:0], PTWR and PTBE[3:0] are driven to indi-
cate what action is required by Add-On logic. These
status signals are valid only when PTATN# is active.
Add-On logic can decode status signals upon the
assertion of PTATN#.
PTATN# Asserted. Indicates Pass-Thru access is
pending.
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Clock 3: The Add-On logic will latch the Pass-Thru
address on the rising edge of this clock. This cycle is
also required to avoid contention on the DQ bus. Time
must be allowed after PTADR# is deasserted for the
DQ outputs to float before Add-On logic attempts to
write to the Pass-Thru Read FIFO.
Add-On deasserts WR#, ADR[6:2], SELECT#,
BE[3:0]# and DQ. It also deasserts PTRDY#. Note that
in a synchronous design, the Add-On logic does not
require PTATN# in order to terminate a Pass-Thru
read operation, PTBURST# is used for this.
Clock 9: As PTATN# and PTBURST# are deasserted,
the Pass-Thru access is complete, and the S5320 can
accept new Pass-Thru accesses starting on the next
clock. The other Pass-Thru signals can also change
state (in anticipation of a new transfer).
Clock 4: The BE[3:0]#, ADR[6:2], and SELECT#
inputs are asserted. WR# and DQ are asserted, indi-
cating that DATA1 is to be written to the PT Read FIFO
on the next clock. PTRDY# is asserted, to indicate the
completion of the current data phase.
NOTE: With prefetch disabled, the performance of
Pass-Thru burst reads will be less than optimal.
Because of certain issues involving synchronizing sig-
nals across clock boundaries (ADCLK -> PCLK),
Pass-Thru burst reads will occur only in double and
single accesses. For example, a Pass-Thru burst read
of five data phases would translate to a burst-read of
two DWORDs, another burst-read of two DWORDs
followed by a single burst-read with PTATN# being
deasserted between each burst packet, losing poten-
tially valuable clock cycles. It is recommended to
enable prefetch if maximum performance is desired.
Clock 5: As the S5320 samples WR# asserted, it
writes DATA1 into the PT Read FIFO. PTRDY# is sam-
pled asserted, which completes the first data transfer
and updates the internal FIFO pointers. The PTBE#
outputs are updated to indicate which bytes are valid
for the second transfer. The Add-On logic samples
PTBURST# asserted, so it knows more data is being
requested. The Add-On keeps WR# asserted, and
drives DATA2 onto the DQ bus. PTRDY# is also
asserted to complete the current data phase.
Clock 6: As the S5320 samples WR# asserted, it
writes DATA2 into the PT Read FIFO. PTRDY# is sam-
pled asserted, which completes the second data
transfer and updates the internal FIFO pointers. The
PTBE# outputs are updated to indicate which bytes
are valid for the third transfer. The Add-On logic sam-
ples PTBURST# asserted, so it knows more data is
being requested. The Add-On keeps WR# asserted,
and drives DATA3 onto the DQ bus. PTRDY# is also
asserted to complete the current data phase.
Figure 67 also shows a Passive Mode Pass-Thru burst
read, but the Add-On logic uses PTRDY# to control
the rate at which data is transferred. In many applica-
tions, Add-On logic is not fast enough to provide data
every ADCLK. In this example, the Add-On interface
writes data every other clock cycle.
Using PTRDY# to assert Wait-States
Clock 0: PCI address information is stored in the Pass-
Thru Address Register. The address is recognized as
a PCI read of Pass-Thru region 1. Add-On bus signals
PTATN#, PTBURST#, PTNUM[1:0], PTWR and
PTBE[3:0] will update on the next rising edge of
ADCLK.
Clock 7: As the S5320 samples WR# asserted, it
writes DATA3 into the PT Read FIFO. PTRDY# is sam-
pled asserted, which completes the third data transfer
and updates the internal FIFO pointers. The PTBE#
outputs are updated to indicate which bytes are valid
for the last transfer. The S5320 deasserts PTBURST#,
indicating that the previous read was the second to
last. The next transfer from the Add-On bus will be the
last. The Add-On logic samples PTBURST# asserted,
so it knows more data is being requested. The Add-On
keeps WR# asserted, and drives DATA4 onto the DQ
bus. PTRDY# is also asserted to complete the current
data phase.
Clock 1: Pass-Thru signals PTATN#, PTBURST#,
PTNUM[1:0], PTWR and PTBE[3:0] are driven to indi-
cate what action is required by Add-On logic. These
status signals are valid only when PTATN# is active.
Add-On logic can decode status signals upon the
assertion of PTATN#.
PTATN# Asserted. Indicates Pass-Thru access is
pending.
Clock 8: As the S5320 samples WR# asserted, it
writes DATA4 into the PT Read FIFO. PTRDY# is sam-
pled asserted, which completes the final data transfer
and updates the internal FIFO pointers. The S5320
deasserts PTATN#, indicating that the final transfer
was performed. No more data is being requested from
PCI. The Add-On logic samples PTBURST# deas-
serted, so it knows that the previous data transfer was
the last, and no more data is being requested. The
PTBURST# Asserted. The access has multiple data
phases.
PTNUM[1:0] 0h.Indicates. the access is to Pass-Thru
region 0.
PTWR Deasserted. Indicates the access is a read.
PTBE[3:0]# D1. Indicates valid bytes for the first data
transfer.
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Clock 2: The Add-On logic has sampled PTATN# and
PTBURST# active, indicating that at least two read
data transfers are requested by the PCI. The Add-On
will start servicing the Burst Read transfer by first read-
ing the Pass-Thru Address via PTADR#. This is an
asynchronous read, meaning that the address will
appear on DQ after a propagation delay from the
assertion of PTADR#. In the event that the address is
not required, this cycle and the next could be skipped
(as the next clock provides a turn-around cycle).
deasserts PTBURST#, indicating that the previus read
was the second to last. The next transfer from the
Add-On will be the last. The PTBE# outputs are
updated to indicate which bytes are valid for the last
transfer. The Add-On logic samples PTBURST#
asserted, so it knows more data is being requested.
However, it is not ready to transfer data yet, so it deas-
serts PTRDY# and WR#. The data on the DQ bus is a
donÕt care, as the Add-On is not writing during this
cycle. The DQ bus could be in tri-state.
Clock 3: The Add-On logic will latch the Pass-Thru
address on the rising edge of this clock. This cycle is
also required to avoid contention on the DQ bus. Time
must be allowed after PTADR# is deasserted for the
DQ outputs to float before Add-On logic attempts to
write to the Pass-Thru Read FIFO.
Clock 9: As the S5320 samples WR# and PTRDY#
deasserted, no data was written to the PT Read FIFO
and the FIFO pointer was not updated (as the transfer
was not signaled complete via a PTRDY#). The Add-
On logic samples PTBURST# deasserted and
PTATN# asserted, so it knows that the previous data
transfer was the last, and no more data is being
requested. However, as it inserted a wait state during
the previous cycle, it still has one more transfer to
complete. As the Add-On logic is ready to complete
the transfer, it asserts WR# and drives the DQ bus
with DATA4. PTRDY# is also asserted to complete the
last data phase.
Clock 4: The BE[3:0]#, ADR[6:2], and SELECT#
inputs are asserted. WR# and DQ are asserted, indi-
cating that DATA1 is to be written to the PT Read FIFO
on the next clock. PTRDY# is asserted, to indicate the
completion of the current data phase.
Clock 5: As the S5320 samples WR# asserted, it
writes DATA1 into the PT Read FIFO. PTRDY# is sam-
pled asserted, which completes the first data transfer
and updates the internal FIFO pointers. The PTBE#
outputs are updated to indicate which bytes are valid
for the second transfer. The Add-On logic samples
PTBURST# asserted, so it knows more data is being
requested WR# remains asserted, and DATA2 is
driven onto DQ. PTRDY# is also asserted to complete
the current data phase.
Clock 10: As the S5320 samples WR# asserted, it
writes DATA4 into the PT Read FIFO. PTRDY# is sam-
pled asserted, which completes the last data transfer
and updates the internal FIFO pointers. The S5320
deasserts PTATN#, indicating that the final transfer
was performed. No more data is being requested from
PCI. Since the Add-On logic previously sampled
PTBURST# deasserted, and transferred the last data,
it knows that no more data is being requested. The
Add-On deasserts WR#, ADR[6:2], SELECT#,
BE[3:0]# and DQ. It also deasserts PTRDY#.
Clock 6: As the S5320 samples WR# asserted, it
writes DATA2 into the PT Read FIFO. PTRDY# is sam-
pled asserted, which completes the second data
transfer and updates the internal FIFO pointers. The
PTBE# outputs are updated to indicate which bytes
are valid for the third transfer. The Add-On logic sam-
ples PTBURST# asserted, so it knows more data is
being requested. However, it is not ready to transfer
data yet, so it deasserts PTRDY# and WR#, and stop
driving the DQ bus. The DQ bus could be in tri-state.
Clock 11: As PTATN# and PTBURST# are deas-
serted, the Pass-Thru access is complete, and the
S5320 can accept new Pass-Thru accesses starting
on the next clock. The other Pass-Thru signals can
also change state (in anticipation of a new transfer).
8-Bit and 16-Bit Pass-Thru Add-On Bus Interface
in Passive Mode
Clock 7: As the S5320 samples WR# and PTRDY#
deasserted, no data was written to the PT Read FIFO
and the FIFO pointer was not updated (as the transfer
was not signaled complete via a PTRDY#). The Add-
On logic is ready to continue the transfer, so it asserts
WR# and drives the DQ bus with DATA3. PTRDY# is
also asserted to complete the current data phase.
The S5320 allows a simple interface to devices with 8-
bit or 16-bit data buses. Each Pass-Thru region may
be defined as 8, 16 or 32 bits, depending on the con-
tents of the boot device which is loaded into the PCI
Base Address Configuration Registers during initial-
ization. The result of the initialization is a unique
bussize (8/16/32 bits) for each Pass-Thru region. The
Pass-Thru Add-On interface internally controls byte
lane steering to allow access to the 32-bit Pass-Thru
Data FIFO (APTD) from 8-bit or 16-bit Add-On buses.
The four DQ data bytes are internally steered depend-
Clock 8: As the S5320 samples WR# asserted, it
writes DATA3 into the PT Read FIFO. PTRDY# is sam-
pled asserted, which completes the third data transfer
and updates the internal FIFO pointers. The S5320
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Data Sheet
ing upon the bus size of the region and the values of
the Byte Enables (BE#). Note that this 8-/16-bit inter-
nal byte-lane steering is not performed for other Add-
On operation registers, just the APTD register (ADR =
2Ch).
asserted. On the Add-On interface, PTBE2# is
asserted, indicating that the PCI initiator requires data
on this byte lane. Once the Add-On writes APTD, byte
2, PTBE2# is deasserted, and the Add-On may assert
PTRDY#, completing the cycle.
Table 44 shows how the external Add-On data bus is
steered to the Pass-Thru Data Register bytes. This
mechanism is determined by the Pass-Thru region
bus width defined during initialization. The BYTEn
symbols indicate data bytes in the Pass-Thru Data
Register. For example, an 8-bit Add-On write with
BE1# asserted results in the data on DQ[7:0] being
steered into BYTE1 of the APTD register.
Table 43. Byte Lane Steering for PCI Write (Add-On
Read)
Byte
Enables
APTD Register Write Byte Lane
Steering
3
x
x
x
0
2
x
x
0
1
1
x
0
1
1
0
0
1
1
1
DQ[31:24]
BYTE3
BYTE3
BYTE3
BYTE3
DQ[23:16]
BYTE2
BYTE2
BYTE2
BYTE3
DQ[15:8]
BYTE1
BYTE1
BYTE2
BYTE3
DQ[7:0]
BYTE0
BYTE1
BYTE2
BYTE3
To write data into the APTD Register, PTBEn# and
BEn# must both be asserted. The following describes
how APTD writes are controlled:
Write BYTE3 if PTBE3# AND BE3# are asserted
Write BYTE2 if PTBE2# AND BE2# are asserted
Write BYTE1 if PTBE1# AND BE1# are asserted
Write BYTE0 if PTBE0# AND BE0# are asserted
Table 44. Byte Lane Steering for PCI Read (Add-On
Write)
After each byte is written into the Pass-Thru data reg-
ister, its corresponding PTBE[3:0]# output is
deasserted. This allows Add-On logic to monitor which
bytes have been written, and which bytes remain to be
written. When all requested bytes have been written
(all PTBE[3:0]#s are deasserted), PTRDY# is asserted
by the Add-On, completing the access.
Defined PT
Bus Width
APTD Register Write Byte Lane
Steering
BYTE3
DQ[31:24]
DQ[15:8]
DQ[7:0]
BYTE2
BYTE1
BYTE0
DQ[7:0]
DQ[7:0]
DQ[7:0]
32 Bit Data Bus
16 Bit Data Bus
8 Bit Data Bus
DQ[23:16]
DQ[7:0]
DQ[7:0]
DQ[15:8]
DQ[15:8]
DQ[7:0]
There are two methods of accessing the Add-On
Pass-Thru Address Register (APTA): by asserting the
PTADR# pin (and getting the address on DQ after
some propagation delay) or by asserting RD#,
SELECT, BE[3:0]#’s, and ADR[6:2] = 28h (and getting
the address on DQ one cycle later). When using the
PTADR# input, all 32 bits of address are driven on DQ,
regardless of the state of the DQMODE pin. When
accessing APTA via an Add-On operation register
access, all 32 bits of address are driven on DQ as long
as DQMODE indicates 32 bits. If DQMODE is set for
16 bits, it is necessary to perform two accesses: one
with BE[3]# low for the lower 16 bits, and one with
BE[3]# high for the upper 16 bits. The Pass-Thru
region bus-sizes have no effect on APTA accesses.
For Pass-Thru writes (Add-On APTD reads), Add-On
logic must read the APTD register one byte or one
word at a time (depending on the Add-On bus width).
The internal data bus is steered from the correct por-
tion of APTD using the BE[3:0]# inputs. Table 43
shows the byte lane steering mechanism used by the
S5320. The BYTEn symbols indicate data bytes in the
Pass-Thru Data Register.
When a read by the Add-On is performed with a BEn#
input asserted, the corresponding PTBEn# output is
deasserted. Add-On logic cycles through the byte
enables to read the entire APTD Register. Once all
data is read (all PTBE[3:0]#s are deasserted),
PTRDY# is asserted by the Add-On, completing the
access.
Figure 68 shows a Pass-Thru write operation for a
region defined for an 8-bit Add-On bus interface. As
the 8-bit device is connected only to DQ[7:0], the
device must access the APTD one byte at a time.
For Pass-Thru reads (Add-On APTD writes), the bytes
requested by the PCI initiator are indicated by the
PTBE[3:0]# outputs. Add-On logic uses the
PTBE[3:0]# signals to determine which bytes must be
written (and which bytes have already been written).
For example, a PCI initiator performs a byte Pass-Thru
read from an 8-bit Pass-Thru region with PCI BE2#
A PCI initiator has performed a posted burst-write of
two DWORDs to Pass-Thru region zero. Data0 =
08D49A30h and Data1 = AABBCCDDh. All byte-
enables of the DWORDs were active.
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Data Sheet
Clock 0: The address is recognized as a PCI write to
Pass-Thru region 0. The PCI bus write address is
stored in the Pass-Thru Address Register. The PCI
bus write data is stored in the S5320 write FIFO. Add-
On bus signals PTATN#, PTBURST#, PTNUM[1:0],
PTWR and PTBE[3:0] will update on the next ADCLK.
Clock 2: The Add-On sees that a burst-write is being
requested by the PCI, so starts by reading the corre-
sponding address via PTADR#. Note that all 32 bits of
the APTA are output on the DQ bus when PTADR# is
asserted. The Add-On must be capable of latching the
upper 24 bits (if needed). The Add-On begins reading
the APTD Register (asserting SELECT#, ADR[6:2],
and RD#). The Add-On logic sees that all bytes are
valid (PTBE# = 0h), so starts the read by asserting
BE0#, to indicate that BYTE0 of the APTD is to be
driven on DQ[7:0] during the next clock cycle.
Clock 1: Pass-Thru signals PTATN#, PTBURST#,
PTNUM[1:0], PTWR and PTBE[3:0] are driven to indi-
cate what action is required by Add-On logic. These
status signals are valid only when PTATN# is active.
Add-On logic can decode status signals upon the
assertion of PTATN#.
Clock 3: The Add-On logic latches the Pass-Thru
address. RD# and BE0# are sampled by the S5320,
so BYTE0 of the APTD is driven on DQ[7:0] and
PTBE0# is deasserted. The Add-On asserts RD# and
BE1#, thus requesting that BYTE1 of the APTD be
driven on the DQ bus during the next cycle.
PTATN# Asserted. Indicates Pass-Thru access is
pending.
PTBURST# Asserted. The access has multiple data
phases.
PTNUM[1:0] 0h. Indicates the access is to Pass-Thru
region 0.
Clock 4: The Add-On logic latches BYTE0. RD# and
BE1# are sampled asserted by the S5320, so BYTE1
of the APTD is driven on DQ[7:0] and PTBE1# is deas-
serted. The Add-On device asserts RD# and BE2#,
thus requesting that BYTE2 of the APTD be driven on
the DQ bus during the next cycle.
PTWR Asserted. Indicates the access is a write.
PTBE[3:0]# 0h. Indicates valid bytes for the first data
transfer.
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Figure 68. PCI to Add-On Passive Write to an 8-bit
3
4
7
8
9
0
1
2
5
6
10
11
12
13
ADCLK
PTATN#
PTBURST#
PTNUM[1:0]
PTWR
0h
PTBE[3:0]#
SELECT#
ADR[6:2]
BE[3:0]#
RD#
0h
1h
3h
7h
0h
8h
Ch
Eh
Fh
2Ch
Eh
Dh
Bh
7h
7h
Bh
Dh
Eh
ADD[7:0]
DQ[7:0]
30h
9Ah
D4h
08h
AAh
BBh
CCh
DDh
ADD[31:8]
DQ[31:8]
PTADR#
PTRDY#
Clock 5: The Add-On logic latches BYTE1. RD# and
BE2# are sampled asserted by the S5320, so BYTE2
of the APTD is driven on DQ[7:0] and PTBE2# is deas-
serted. The Add-On device asserts RD# and BE3#,
thus requesting that BYTE3 of the APTD be driven on
the DQ bus during the next cycle. PTRDY# is also
asserted, indicating that the transfer is complete.
is driven on DQ[7:0] and PTBE3# is deasserted. The
Add-On device asserts RD# and BE2#, thus request-
ing that BYTE2 of the APTD be driven on the DQ bus
during the next cycle.
Clock 8: The Add-On logic latches BYTE3 of the sec-
ond DWORD. RD# and BE2# are sampled asserted
by the S5320, so BYTE2 of the APTD is driven on
DQ[7:0] and PTBE2# is deasserted. The Add-On
asserts RD# and BE1#, thus requesting that BYTE1 of
the APTD be driven on the DQ bus during the next
cycle.
Clock 6: The Add-On logic latches BYTE2. RD# and
BE3# are sampled asserted by the S5320, so BYTE3
of the APTD is driven on DQ[7:0]. PTRDY# is sampled
asserted, so the previous transfer is complete. The
PTBE# signals are updated to indicate which bytes are
valid for the next transfer (in this case, all bytes are
valid for the second DWORD, so PTBE# = 0h). The
S5320 deasserts PTBURST#, as it only has one
DWORD left to transfer. The Add-On device asserts
RD# and BE3#, thus requesting that BYTE3 of the
second DWORD in the APTD be driven on the DQ bus
during the next cycle.
Clock 9: The Add-On logic latches BYTE2 of the sec-
ond DWORD. RD# and BE1# are sampled by the
S5320, so BYTE1 of the APTD is driven on DQ[7:0]
and PTBE1# is deasserted. The Add-On asserts RD#
and BE0#, thus requesting that BYTE0 of the APTD be
driven on the DQ bus during the next cycle. PTRDY#
is also asserted, indicating that the transfer is com-
plete. As PTBURST# is already deasserted, the Add-
On recognizes that this is the last transfer.
Clock 7: The Add-On logic latches BYTE3 of the first
DWORD. RD# and BE3# are sampled asserted by the
S5320, so BYTE3 of the second DWORD in the APTD
Clock 10: The Add-On logic latches BYTE1 of the
second DWORD. RD# and BE0# are sampled by the
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Data Sheet
S5320, so BYTE0 of the APTD is driven on DQ[7:0].
PTRDY# is sampled asserted, so the previous transfer
is complete. The PTBE# signals are updated to indi-
cate which bytes are valid for the next transfer (in this
case, there is no more valid data to transfer, so PTBE
= Fh). The S5320 deasserts PTATN#, as it has no data
left to transfer. The Add-On device deasserts RD#,
BE#, ADR[6:2], SELECT# as the data transfer is
complete.
Endian Conversion
Endian conversion can be enabled/disabled for each
Pass-Thru Region. It is controlled by bits 6, 14, 22 and
30 of the PTCR. The default endian type for the S5320
is Little Endian. For this reason, the default values in
the PTCR are for Little Endian. If Big Endian is
selected, the Pass-Thru data and byte-enable inter-
face will be converted to Big Endian type.
When the device is programmed for Big Endian trans-
lation and a 32-bit data bus, the S5320 will convert as
described in Table 45.
Clock 11: The Add-On logic latches BYTE0 of the
second DWORD. PTATN# and PTBURST# both deas-
serted indicate that the Pass-Thru transfer is
complete. The PCI can start another access on the
next clock cycle. For 16-bit peripheral devices, the
byte steering works in the same way. Because the
Add-On data bus is 16 bits wide, only two 16-bit cycles
are required to access the entire APTD Register. Two
byte enables can be asserted during each access.
Active mode is provided to simplify logic requirements
when interfacing an application to the Add-On Local
bus. Passive mode requires Add-On logic to assert
read/write signals and drive or latch data on the DQ
bus.
Strapping PTMODE low configures the S5320 for
Active mode operation. Active mode allows more
designer flexibility through programmable features.
The following is a brief description of these features.
Figure 69 shows a Pass-Thru read operation for a
region defined for a 16-bit Add-On bus interface. As
the 16-bit device is connected only to DQ[15:0], the
device must access the APTD one word at a time. The
Add-On must be capable of latching the upper 16 bits
of the APTA (if they are needed).
•
Pass-Thru address can be driven automatically
at the beginning of all transfers or can be
skipped altogether if addresses are unneeded
by Add-On logic.
The PCI initiator has requested a 32-bit burst read
from Pass-Thru region three. All PTBE#s are asserted.
•
Programmed or Add-On controlled wait states
to delay data transfers automatically or on the
fly.
Clock 1: The Add-On begins by reading the APTA
register (asserting PTADR#). All 32 bits of the address
are driven on the DQ bus.
•
•
•
Endian Conversion
Write FIFO ( Write posting )
Read FIFO ( Prefetch )
Clock 2: Turn-around cycle, preventing potential bus
contention on the DQ bus.
Active Operation
Clock 3: The Add-On initiates the write by asserting
WR#, SELECT#, BE[3:0]# = “1100”, ADR[6:2] = 2Ch
and the low word of the first DWORD to be transferred
(D0-LO).
In Active mode, a data transfer start is signaled on the
first clock edge in which PTATN# is sampled low. If
PTADR# has been programmed to be output it will go
active (low) at this time, and the data presented on the
DQ bus is the address for the current transaction. Add-
On logic may latch the address value at the rising
edge of the clock. Address cycles do not count toward
the number of wait states needed to complete data
phases. In Active mode, the PTRDY# pin is renamed
to PTWAIT#. On cycles after PTWAIT# is sampled low,
the state machine is idle. Idle cycles are also not
counted as wait states by the S5320. To control the
number of wait states on an as-needed basis only,
zero wait states should be programmed and PTWAIT#
can be driven low when wait states are to be inserted.
If PTWAIT# is low when PTATN# is asserted by the
S5320, the pending transfer cycle won’t be started
until PTWAIT# is driven high.
Clock 4: The S5320 updates the PTBE#s to indicate
that the low word was provided, and that the upper
word is still required. The Add-On drives the upper
word (D0-HI), and activates the appropriate byte
enables, BE# = 0011 The Add-On also asserts
PTRDY#, indicating that it is done with the current
DWORD, and to advance the FIFO pointer and pre-
pare for the second DWORD.
Clock 5: The PTBE#s are updated to indicate that the
next DWORD to be transferred requires all bytes. The
Add-On drives DQ[15:0] with the lower word of the
second DWORD (D1-LO), and the byte-enables indi-
cate the same, BE# = 1100. The Add-On also
deasserts PTRDY#. This process continues until the
transfer is complete and all words have been written.
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Data Sheet
Figure 69. PCI to Add-On Passive Read to an 16-bit Add-On Device
3
4
7
8
9
0
1
2
5
6
10
11
12
13
ADCLK
PTATN#
PTBURST#
PTNUM[1:0]
PTWR
3h
PTBE[3:0]#
SELECT#
ADR[6:2]
BE[3:0]#
WR#
0h
3h
0h
3h
0h
3h
Fh
2Ch
Ch
3h
Ch
3h
Ch
3h
ADDR
[31:16]
DQ[31:16]
DQ[15:0]
PTADR#
PTRDY#
ADDR
[15:0]
D1
D1
D2
D2
D3
D3
LOW
HIGH
LOW
HIGH
LOW
HIGH
Table 45. Showing Big Endian Conversion for 32-bit
Table 47. Big Endian conversion for an 8-bit bus. The
S5320 drives D[7:0] only
Byte#
PCI Byte
D7-D0
Add-On Byte
D31-D24
D23-D16
D15-D8
PCI Byte
Lane
Add-On Bus
Byte Lane
0
1
2
3
Transfer
1st XFER
2nd XFER
3rd XFER
4th XFER
Byte #
D15-D8
D23-D15
D31-D24
0
1
2
3
D7-D0
D15-D8
D23-D16
D31-D24
D7-D0
D7-D0
D7-D0
D7-D0
D7-D0
Table 46. Big Endian conversion for a 16-bit bus. The
S5320 drives D[15:0] only
In Active mode, wait states can also be programmed.
This enables easier interfacing to slow Add-On logic
whichcannot transferdataatthe fullADCLKspeed.The
S5320 inserts a turnaround cycle after the address
phase for PCI Read cycles. If one or more wait states
have been programmed, the turnaround cycle is con-
sidered the first wait state of the first data phase of that
transaction.
PCI Byte
Lane
Add-On Bus
Byte Lane
Transfer
1st XFER
1st XFER
2nd XFER
2nd XFER
Byte #
0
1
2
3
D7-D0
D15-D8
D23-D16
D31-D24
D15-D8
D7-D0
D15-D8
D7-D0
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Data Sheet
For all Active mode transfers, the DXFR# signal is
used by Add-On logic as the data transfer signal. Data
must be latched at the rising edge of ADCLK when
DXFR# is asserted for a PCI write. Conversely, for PCI
Reads, the rising edge of ADCLK when DXFR# is
asserted can be used to increment to the next data
field.
The PTADR# signal is controlled by the most signifi-
cant bit of every region control field in the PTCR
register. If this bit is zero then the PTADR# pin is not
driven at the start of an Active mode transfer. If this bit
is set to one, the PTADR# pin will be enabled and
driven active (low) for one and only one clock after
PTATN# was sampled active provided PTWAIT# was
also sampled high.
Figure 70. Active mode PCI Read (Zero Programmed
Wait States) with PTADR#
Figure 72. Active Mode PCI Write without PTADR#
1
2
3
4
5
6
7
1
2
3
4
5
6
7
ADCLK
ADCLK
PTATN#
PTBURST#
PTNUM[1:0]
PTWR
PTATN#
PTBURST#
PTNUM[1:0]
PTWR
01b
01b
PTBE[3:0]
DXFR#
0h
Fh
PTBE[3:0]
DXFR#
0h
Fh
DQ[31:0]
PTWAIT#
PTADR#
PTADDR
DATA
DQ[31:0]
PTWAIT#
PTADR#
DATA
Figure 71. Active Mode PCI Read without PTADR#
When PTADR# is active (low), the S5320 will drive the
DQ[31:0] bus with the 32-bit PCI address regardless of
the PTMODE pin. To avoid contention on the DQ[31:0]
bus during PCI read cycles, the S5320 incorporates a
turnaround cycle before starting to drive the data
(DXFR# assertion). This is needed only when
PTADR# is enabled and when zero wait states are
programmed during a Pass-Thru read cycle. The cycle
immediately following the address cycle will be a turn-
around cycle as shown in Figure 70.
1
2
3
4
5
6
7
ADCLK
PTATN#
PTBURST#
PTNUM[1:0]
PTWR
01b
0h
PTBE[3:0]
DXFR#
Fh
If PTADR# is disabled, the DXFR# output will be
driven one clock cycle after PTATN# is valid (PTATN#
is not considered active until PTATN# is low and
PTWAIT# is high) regardless of the transfer being a
read or a write. Figure 71 shows a PCI read cycle with
PTADR# disabled.
DQ[31:0]
PTWAIT#
PTADR#
DATA
Figure 72 shows a Pass-Thru write cycle with PTADR#
disabled.
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Active mode Programmable Wait States
PTRDY#/PTWAIT#
Bits 0,1,2 of the PTCR register control this feature.
Wait States are programmed on a per region basis.
For example: region one can be set for zero wait
states while other regions may have multiple wait
states programmed.
In Active mode, the PTRDY#/PTWAIT# pin takes the
PTWAIT# function, which is the opposite function of
this pin when configured for passive mode. That is, if
the part is configured to operate in Active mode,
PTWAIT# asserted low means the Add-On wishes to
insert wait states.
Wait state options are 0,1,2,...7 wait states. The S5320
will always count N wait states (N=0,1,..7) before com-
pleting the current data phase.
Add-On peripherals are allowed to insert wait state
cycles at any time during an Active mode transfer.
When PTWAIT# has been sampled low, the S5320 will
tri-state its DQ[31:0] bus in order to allow other Add-
On devices to use the bus without contention.
Figures 76, 77 and 78 show Pass-Thru transfers with
programmed wait states.
Figure 73. Active Mode PCI Write with Add-On Initiated Wait States Using PTWAIT#
3
4
7
8
9
0
1
2
5
6
10
11
12
13
ADCLK
PTATN#
PTBURST#
PTNUM[1:0]
PTWR
01b
0h
PTBE[3:0]#
DXFR#
Fh
DQ[31:0]
PTADR#
PTWAIT#
PTADDR
DATA
Figure 74. Active Mode 32-Bit PCI Write
The address phase of a Pass-Thru consists of the
cycles from PTATN# asserted through PTADR#
asserted (if PTADR# has been programmed to be dis-
abled, there is no address phase). If PTWAIT# is
asserted before the address phase, the address
phase is delayed. The address phase will occur during
the cycle after the clock edge that PTWAIT# is sam-
pled high and PTATN# is sampled low.
1
2
3
4
5
6
ADCLK
PTATN#
PTBURST#
PTNUM[1:0]
PTWR
01b
0h
The data phase(s) of a Pass-Thru consists of all the
cycles after the (possibly nonexistent) address phase.
During data phases, a wait is incurred during the cycle
after PTWAIT# is sampled asserted.
PTBE[3:0]
DXFR#
Fh
Note: If PTWAIT# is activated in order to access other
registers internal to the S5320, the user is responsible
for inserting any needed turnaround cycles in order to
avoid bus contention on the DQ bus.
PTADDR
DQ[31:0]
PTWAIT#
PTADR#
DATA
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Data Sheet
DXFR#
treats this cycle as a wait state since PTWAIT# was
active (low) at the rising edge of clock 4.
DXFR# is a signal that is active during the cycles that
a data transfer may take place. It is intended to be
used to control strobes (e.g., write enable, read
enable), and can be a flag for incrementing to the next
address during a burst.
Clock 5: This is a wait state since PTWAIT# was
active (low) at the rising edge of clock 5.
Clock 6: PTWAIT# was inactive (high) at the rising
edge of clock 6, so DXFR# is driven active (low) indi-
cating a data transfer. PTATN# is driven inactive (high)
indicating the Pass-Thru access is complete.
If wait states have been programmed, DXFR# will not
go active until after all wait states have been executed.
Note that asserting PTWAIT# to insert Add-On initi-
ated wait states causes temporary suspension of the
internal programmed wait state counter.
Clock 7: DXFR# was active (low) at the rising edge of
this clock so the Add-On device must latch the PCI
data on the rising edge of this clock. PTBE# is driven
to Fh indicating all 4 bytes have been accessed.
PTNUM and PTWR may change state since the Pass-
Thru access is complete.
Active Mode Figures and Descriptions
Figure 73 shows a programmed zero wait state trans-
fer in which the cycle start and the cycle completion
are delayed by an external device controlling
PTWAIT#.
Clock 8: PTBE# may change state.
Figure 74 shows a single data phase 32-bit Active
mode PCI Write with PTADR# enabled.
Clock 1: The S5320 drives PTATN# active (low), indi-
cating the start of a PCI to Add-On data transfer.
PTBE[3:0] and PTNUM[1:0] are driven to their appro-
priate values for this transfer. PTWR is driven high
indicating a PCI write.
Active mode Burst cycles
PTBURST# signifies to the Add-On device that the
current transfer will be contain more than one data
phase. The Add-On device detects the end of a burst
when the S5320 deasserts PTBURST#. During an
Active mode PCI burst read, PTBURST# is deasserted
when there is one more data word left to transfer. Dur-
ing an Active mode PCI burst write, PTBURST#
deasserted indicates that after the current data word is
transferred, there will be one data word left to transfer.
Figure 75 shows an Active mode PCI Burst Write with
0 programmed wait states. The Add-On device con-
trolling PTWAIT# asserts wait states in the figure on an
as-needed basis. PTADR# has been programmed to
be disabled.
Clock 2: This is a wait state since PTWAIT# was
active (low) at the rising edge of clock 2.
Clock 3: PTWAIT# was inactive (high) at the rising
edge of clock 3 so this cycle is the address phase:
PTADR# is driven active (low) and the address value
for the current transaction is driven onto the DQ bus.
Clock 4: PTADR# was active (low) at the rising edge
of this clock so the Add-On device must latch the PCI
address on the rising edge of this clock. The S5320
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Figure 75. Active Mode 32-Bit PCI Write w/PTWAIT#
3
4
7
8
9
0
1
2
5
6
10
11
12
13
ADCLK
PTATN#
PTBURST#
PTNUM[1:0]
PTWR
01b
PTBE[3:0]#
DXFR#
Data1 Data2
Data3
Data4
Data5
Fh
DQ[31:0]
PTADR#
PTWAIT#
DATA1 DATA2
DATA3
DATA4 DATA5
Clock by Clock description of Figure 75
Clock 5: No data transfer takes place at the rising
edge of clock 5 since the previous cycle was an Add-
On initiated wait state (because PTWAIT# was active
(low) at the rising edge of clock 4). The S5320 asserts
DXFR# and drives the third data onto the DQ bus
since PTWAIT# was inactive (high) at the rising edge
of clock 5. The Add-On device drives PTWAIT# active
(low) requesting a wait state on the next cycle.
Clock 1: The S5320 drives PTATN# and PTBURST#
active (low), indicating the start of a PCI to Add-On
data transfer with more than one data cycle. PTBE[3:0]
and PTNUM[1:0] are driven to their appropriate values
for this transfer. PTWR is driven high indicating a
Pass-Thru write.
Clock 2: Since this region does not have PTADR#
enabled as an output and PTWAIT# is high at the ris-
ing edge of clock 2, the first data transfer is indicated
by driving DXFR# low and the data on the data bus
DQ[31:0] .
Clock 6: DXFR# is sampled active by the Add-On
device which indicates that the Add-On device must
latch the third data word at the rising edge of this
clock. The S5320 drives DXFR# inactive and tri-states
the DQ bus since PTWAIT# was active (low) at the ris-
ing edge of clock 6. The Add-On keeps PTWAIT#
asserted indicating it wants to add a wait state on the
next cycle.
Clock 3: DXFR# is sampled active by the Add-On
device which indicates that the Add-On device must
latch the first data word at the rising edge of this clock.
Valid data is determined by decoding the PTBE[3:0]#
lines. The Add-On device drives PTWAIT# active (low)
requesting a wait state on the next cycle.
Clock 7: No data transfer takes place on the rising
edge of this clock since the previous cycle was an
Add-On initiated wait state (because PTWAIT# was
active (low) at the rising edge of clock 6).
Clock 4: DXFR# is sampled active (low) by the Add-
On device which indicates that the Add-On device
must latch the second data word at this clock edge.
The S5320 tri-states its output bus since PTWAIT#
was inactive (high) at the rising edge of clock 4. Addi-
tionally, the S5320 deasserts DXFR# indicating that no
data transfer will occur on the next clock edge (this is
because this cycle is a wait state since PTWAIT# was
active (low) at the rising edge of clock 4. The Add-On
device deasserts PTWAIT# indicating no wait state on
the next clock.
Clock 8: No data transfer takes place on the rising
edge of this clock since the previous cycle was an
Add-On-initiated wait state (because PTWAIT# was
active (low) at the rising edge of clock 7). DXFR# is
driven active (low) and the fourth data is driven onto
the DQ bus since PTWAIT# was inactive (high) at the
rising edge of clock 8. PTBURST# is driven inactive
(high) indicating that after this data word is transferred,
there is only one data word left to transfer.
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Clock 9: DXFR# is sampled active (low) by the Add-
On device which indicates that the Add-On device
must latch the fourth data word at the rising edge of
this clock. PTATN# is driven inactive (high) indicating
that this will be the last data phase.
Figure 76 shows a Pass-Thru Burst Write data transfer
in which the S5320 has been programmed to strobe
data using a one-wait state delay. The Add-On device
leaves PTWAIT# inactive (high) for all time.
Clock by Clock description of Figure 76
Clock 10: DXFR# is sampled active (low) by the Add-
On device which indicates that the Add-On device
must latch the fifth data word at the rising edge of this
clock.
Clock 1: The S5320 drives PTATN# and PTBURST#
active (low) indicating the start of a PCI to Add-On
data transfer with more than one data cycle. PTBE[3:0]
and PTNUM[1:0] are driven to their appropriate values
for this transfer. PTWR is driven high indicating a
Pass-Thru write.
DXFR# is deasserted since the access is complete.
PTBE# is driven to Fh indicating all 4 bytes have been
accessed. PTNUM and PTWR may change state
since the access is complete.
Clock 11: PTBE# may change state.
Figure 76. Active Mode PCI Write Showing a One Wait State Programmed Delay
3
4
9
0
1
2
5
6
7
8
10
11
12
13
ADCLK
PTATN#
PTBURST#
PTNUM[1:0]
PTWR
1h
PTBE[3:0]#
DXFR#
Data1
Data2
DATA2
Data3
Data4
Fh
DQ[31:0]
PTADR#
PTWAIT#
DATA1
DATA3
DATA4
PTADDR
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Figure 77. 16-Bit Active Mode PCI Read w/ Programmed Wait States
3
4
9
14
7
8
0
1
2
5
6
10
11
12
13
ADCLK
PTATN#
PTBURST#
PTNUM[1:0]
PTWR
1h
PTBE[3:0]#
DXFR#
Ch
3h
Fh
DQ[15:0]
PTADR#
PTWAIT#
PTADDR
LOW
HIGH
Clock 2: Since this region does have PTADR#
enabled as an output, it is driven active (low) and the
PCI address for the current transaction is presented
on the DQ[31:0] bus.
Clock 6: DXFR# is asserted indicating that data will be
transferred on the next rising clock edge (clock 7).
DATA2 is driven onto the DQ[31:0] bus.
Clock 7: The Add-On side device latches the second
Clock 3: The Add-On device must latch the PCI
data word (DATA2) at the rising edge of this clock.
address at the rising edge of this clock.
Clock 8: DXFR# is asserted indicating that data will be
transferred on the next rising clock edge (clock 9).
DATA3 is driven onto the DQ[31:0] bus. PTBURST# is
driven inactive indicating that after this data word is
transferred, there is only one data word left to transfer.
Clock 4: DXFR# is asserted low indicating that data
will be transferred on the next rising clock edge (clock
5). Data1 is driven onto the DQ[31:0] bus.
Clock 5: The Add-On device must latch the first data
word at the rising edge of this clock. Valid data is
determined by decoding the PTBE[3:0]# lines.
Clock 9: The Add-On side device latches the third
data word (DATA3) at this clock edge.
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Clock 10: DXFR# is asserted indicating that data will
be transferred on the next rising clock edge (clock 11).
DATA4 is driven onto the DQ[31:0] bus. PTATN# is
deasserted indicating that this will be the last data
phase.
32-bit word (“LOW” in Figures 77, 79 and 80), while
the second transfer will be for the most significant 16-
bit word (“HIGH” in Figures 77, 79 and 80). If the cur-
rent PCI access has only 2 bytes valid (PCI BE[3:0]#
encoding of Ch or 3h instead of 0h), then the S5320
will still assert a 2 cycle completion but one of them
will not contain valid data (PTBE[3:0]#=Fh). If the pro-
grammed wait states for the current Pass-Thru region
is not zero, then the S5320 will insert the programmed
wait states before the “LOW” data word and also
between the “LOW” and “HIGH” data words. Figure 77
shows a PCI read to a 16-bit Add-On region with two
programmed wait states. Note that a PCI read to an 8-
bit Add-On would be the same as Figure 77 except
that there would be 4 data transfers (one for each
byte) vice 2.
Clock 11: The final data word (DATA4) must be
latched by the Add-On device at the rising edge of this
clock. PTBE# is driven to Fh indicating all 4 bytes have
been accessed. PTNUM and PTWR may change state
since the access is complete.
Clock 12: PTBE# may change state.
Active Mode with 16/8-bit data buses
When the S5320 is programmed in Active mode and
16-bit, the DXFR# output will strobe twice for every
PCI 32-bit word that has been read/written. Each
DXFR# assertion signifies that a 16-bit word has been
transferred to the Add-On side. The first DXFR# com-
pletion will be for the least significant 16-bit word of a
As in Passive mode, in Active mode, the word read/
write order is determined by the Endian conversion
programmed into the S5320.
Figure 78. Active Mode PCI Read w/ Programmed Wait States
3
4
9
14
0
1
2
5
6
7
8
10
11
12
13
ADCLK
PTATN#
PTBURST#
PTNUM[1:0]
PTWR
1h
PTBE[3:0]#
DXFR#
Fh
Data1
Data2
Data3
DQ[31:0]
PTADR#
PTWAIT#
PTADDR
DATA1
DATA2
DATA3
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Figure 79. Active Mode PCI Read
Figure 80. Active Mode PCI Write
1
2
3
4
5
6
1
2
3
4
5
6
ADCLK
ADCLK
PTATN#
PTBURST#
PTNUM[1:0]
PTWR
PTATN#
PTBURST#
PTNUM[1:0]
PTWR
1h
1h
PTBE[3:0]
DXFR#
Ch
3h
Fh
PTBE[3:0]
DXFR#
Ch
3h
Fh
DQ[15:0]
PTWAIT#
PTADR#
LOW
HIGH
DQ[15:0]
PTWAIT#
PTADR#
LOW
HIGH
Figure 79 shows a Pass-Thru read cycle with 0 wait
states for a 16-bit region. The PTBE[3:0]# signals are
used by the Add-On device to determine validity of the
current word cycle and also, which word of a long word
is currently being driven by the S5320. PTBE[3:0]#
encoding of Ch indicates the least significant 16-bit
portion of the 32-bit PCI data word is on the DQ[15:0]
bus. PTBE[3:0]# encoding of 3h indicates the most
significant 16-bit portion of the 32-bit PCI data word is
on the DQ[15:0] bus. PTADR# is shown as disabled in
Figure 79.
Figure 81 shows a Pass-Thru write cycle with 0 wait
states for an 8-bit region. The PTBE[3:0]# signals are
used by the Add-On device to determine validity of the
current byte cycle and also, which byte of a long word
is currently being driven by the S5320. PTADR# is
enabled as an output.
CONFIGURATION
The S5320 Pass-Thru interface utilizes four Base
Address Registers (BADR1:4). Each Base Address
Register corresponds to a Pass-Thru region. The con-
tents of these registers during initialization determine
the characteristics of that particular Pass-Thru region.
Each region can be mapped to memory or I/O space.
Memory mapped devices can, optionally, be mapped
below 1 Mbyte and can be identified as prefetchable.
Both memory and I/O regions can be configured as 8,
16 or 32 bits wide.
Figure 80 shows a Pass-Thru write cycle with 0 wait
states for a 16-bit region. PTADR# is disabled.
If the Add-On bus size is 8 bits, then the S5320 will
assert DXFR# 4 times for each 32-bit PCI word The
first completion is for byte 0, the second is for byte 1,
the third is for byte 3, and the fourth DXFR# assertion
is for byte 4 of a 32-bit word. If the current PCI access
has less than four bytes valid (PCI BE[3:0]# encoding
is not 0h), then the S5320 will still assert a 4-cycle
completion but one or more of them will not contain
valid data (PTBE[3:0]# = Fh).
Base Address Registers are loaded during initializa-
tion from the external non-volatile boot device. Without
an external boot device, the default value for the
BADR registers is zero (region disabled). The Base
Address Registers are the only registers that define
Pass-Thru operation. Consequently, the Pass-Thru
interface cannot be used without an external non-vola-
tile boot device.
As in Passive mode, in Active mode, the word read/
write order is determined by the Endian conversion
programmed into the S5320.
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S5320 Base Address Register Definition
PCI BIOS will not allocate the I/O space and will prob-
ably disable the region.
Certain bits in the Base Address Register have spe-
cific functions:
Figure 81. 8-Bit Active Mode PCI Write
Memory or I/O mapping. If this bit is clear, the
region should be memory mapped. If this bit is
set, the region should be I/O mapped.
D0
1
2
3
4
5
6
7
ADCLK
PTATN#
PTBURST#
PTNUM[1:0]
PTWR
Location of a memory region. These bits
D2:1
request that the region be mapped in a particu-
lar part of memory. These bit definitions are
only used for memory mapped regions.
1h
D2
D1
Location
PTBE[3:0]
DXFR#
0
0
Anywhere in 32-bit memory
space
Eh
Dh
Bh
7h
Fh
0
1
1
1
0
1
Below 1 Mbyte in memory space
(Real Mode address space)
DQ[7:0]
PTADDR Byte0 Byte1 Byte2 Byte3
PTWAIT#
PTADR#
Anywhere in 64-bit memory
space (not valid for the S5320)
Reserved
Prefetchable. For memory mapped regions,
the region can be defined as cacheable. If set,
the region is cacheable. If this bit is clear, the
region is not.
Creating a Pass-Thru Region
D3
Section 3.11 describes the values that must be pro-
grammed into the non-volatile boot device to request
various block sizes and characteristics for Pass-Thru
regions. After reset, the S5320 downloads the con-
tents of the boot device locations 54h, 58h, 5Ch, and
60h into “masks” for the corresponding Base Address
Registers. The following are some examples for vari-
ous Pass-Thru region definitions:
Pass-Thru region bus width. These two bits are
used by the S5320 to define the data bus width
for a Pass-Thru region. Regardless of the pro-
gramming of other bits in the BADR register, if
D31:30 are zeros, the Pass-Thru region is dis-
abled.
D31:30
NV Memory Contents
Pass-Thru Region Definition
D31 D30 Add-On Bus Width
54h = BFFFF002h
Pass-Thru region 1 is a 4 Kbyte
region, mapped below 1 Mbyte
in memory space with a 16-bit
Add-On data bus. This memory
region is not cacheable.
0
0
1
1
0
1
0
1
Region disabled
8 bits
16 bits
58h = 3xxxxxxxh
5Ch = FFFFFF81h
60h = 00000000h
Pass-Thru region 2 is disabled.
(D31:30 = 00.)
32 bits
Pass-Thru region 3 is a 32-bit,
128 byte I/O-mapped region.
BADR1:4 bits D31:30 are used only by the S5320.
When the host reads the Base Address Registers dur-
ing configuration cycles, they always return the same
value as D29. If D29 is zero, D31:30 return zero, indi-
cating the region is disabled. If D29 is one, D[31:30]
return one. This operation limits each Pass-Thru
region to a maximum size of 512 Mbytes of memory.
Pass-Thru region 4 is disabled.
During the PCI bus configuration, the host CPU writes
all ones to each Base Address Register, and then
reads the contents of the registers back. The mask
downloaded from the boot device determines which
bits are read back as zeros and which are read back
as ones. The number of zeros read back indicates the
amount of memory or I/O space a particular S5320
Pass-Thru region is requesting.
For I/O mapped regions, the PCI specification allows
no more than 256 bytes per region. The S5320 allows
larger regions to be requested by the Add-On, but a
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After the host reads all Base Address Registers in the
system (as every PCI device implements from one to
six), the PCI BIOS allocates memory and I/O space to
each Base Address region. The host then writes the
start address of each region back into the Base
Address Registers. The start address of a region is
always an integer multiple of the region size. For
example, a 64-Kbyte memory region is always
mapped to begin on a 64K boundary in memory. It is
important to note that no PCI device can be absolutely
located in system memory or I/O space. All mapping is
determined by the system, not the application.
location in the external nvRAM which will contain
these custom programmed bits. These features, and
their corresponding bit at location 45h, are described
as follows:
LOC_45(h)
b = 0
Descripton
Target Latency Enb
Retry Flush Enb
Write FIFO Mode
Reserved
Default
1
0
0
x
b = 1
b = 2
PCI or Add-On Operation registers PTCR or APTCR
provide additional configuration control for each
region.
b = (7:3)
Target Latency describes the number of cycles that a
target device may respond to a PCI data transfer
request. The PCI 2.1 specification indicates that the
target device has 16 clocks to respond to an initial
request (from the assertion of FRAME#), and 8 clocks
from each subsequent data phase. If the target is not
capable of asserting TRDY# within these time frames,
it must assert a STOP#, thus initiating a disconnect.
The Target Latency programmed bit allows the user to
disable the generation of disconnects in the event of a
slow Add-On device.
Accessing a Pass-Thru Region
After the system is finished defining all Base Address
Regions within a system, each Base Address Register
contains a physical address. The application software
must now find the location in memory or I/O space of
its hardware. PCI systems provide BIOS or operating
system function calls for application software to find
particular devices on the PCI bus based on Vendor ID
and Device ID values. This allows application software
to access the device’s Configuration Registers.
If Target Latency Enb is low, target latency is ignored.
In this case, the S5320 will never issue a retry/discon-
nect in the event of a slow add-on device. Instead,
TRDY# wait states will be asserted. This might be use-
ful for an embedded system, where the S5320 can
take up as many clock cycles as necessary to com-
plete a transfer. This programmable bit is only
provided for flexibility and most users should leave this
bit set to 1. If Target Latency Enb is high, the device
will be PCI 2.1 compliant with respect to Target
Latency.
The Base Address Register values in the S5320’s
Configuration Space may then be read and stored for
use by the program to access application hardware.
The value in the Base Address Registers is the physi-
cal address of the first location of that Pass-Thru
region. Some processor architectures allow this
address to be used directly to access the PCI device.
For Intel Architecture systems, the physical address
must be changed into a Segment/Offset combination.
For Real Mode operation in an Intel Architecture sys-
tem (device mapped below 1 Mbyte in memory),
creating a Segment/Offset pair is relatively simple. To
calculate a physical address, the CPU shifts the seg-
ment register 4 bits to the left and adds the offset
(resulting in a 20 bit physical address). The value in
the Base Address Register must be read and shifted 4
bits to the right. This is the segment value and should
be stored in one of the Segment registers. An offset of
zero (stored in SI, DI or another offset register)
accesses the first location in the Pass-Thru region.
Retry Flush Enb indicates to the Pass-Thru whether to
hold prefetched data following a disconnect, or to
allow the data to be flushed out during the next PCI
read access. If low, the data will be held in the PT read
FIFO until the initiator comes back to read it out. All
subsequent PCI accesses to the S5320 from a device
other than the one who initiated the read will be
acknowledged with a retry. If the master never returns
for the data, the Pass-Thru function will be hung. Even
though the PCI 2.1 Specification does not require a
master to return for data following a disconnect, it is
unlikely that a master will terminate a read transfer
until all data has been collected.
Special Programming Features
A few additional features have been provided to the
user which will allow for optimal “tuning” of their sys-
tem. As these are not features that will be changed “on
the fly”, they have been included as part of the nvRAM
boot-up sequence. nvRAM address 45h is a memory
If Retry Flush Enb is high, the data will be flushed from
the FIFO if a subsequent PCI read access is not to the
same address. If the original master received a retry
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(disconnect, but with no data transfer), the read data is
held in the FIFO until the master comes back for it. In
this case, the Retry Flush Enb has no effect. The PCI
2.1 Specification states that the master must come
back if it receives a retry.
tiator will have to come back to complete the data
transfer, after which time the FIFO should no longer be
full. If Write FIFO Mode is high, the S5320 will deas-
sert TRDY#, and allow for either another FIFO location
to become available (as the Add-On has read a
DWORD), or wait for the Target Latency to expire (8
clocks from previous data phase), thus initiating a dis-
connect. This will allow for the Add-on device to
“catch-up” without losing the burst.
Write FIFO Mode indicates what to do in the event that
a full FIFO is detected during a PCI write transfer. If
low, the S5320 will perform an immediate disconnect,
thus freeing up the PCI bus for other transfers. The ini-
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ABSOLUTE MAXIMUM STRESS RATINGS
Data Sheet
Table 1 lists the absolute maximum S5320 device stress ratings. Stresses beyond those listed may cause perma-
nent damage to the device. These are stress ratings only; operation of the device at these or any other conditions
beyond those indicated in the Operating Characteristics section of this specification is not implied.
Table 1. Absolute Maximum Stress Ratings
Parameter
Min
-55
Max
125
4
Units
°C
Storage Temperature
Supply Voltage (V
Input Pin Voltage
)
-0.3
V
CC
-0.3
2000
200
6
-
V
V
V
ESD Voltage Rating (Human Body Model)
ESD Voltage Rating (Machine Model)
-
RECOMMENDED OPERATING CONDITIONS
Table 2 lists the S5320 operating conditions. These parameters are guaranteed by device characterization, but not
device tested. All values are maximum guaranteed values.
Table 2. Recommended Operating Conditions
Symbol
Parameter
Junction Temperature
Operating Ambient Temperature
Supply Voltage
Min
Typ
Max
Units
Conditions
T
T
-10
-
85
°C
J
0
3.0
-
-
-
70
3.6
°C
V
A
V
CC
1
36.2
45.2
mA
Add-on clock freq = 40 MHz
Add-on clock freq = 40 MHz
Add-on clock freq = 40 MHz
I
I
Supply Current (Static)
CC,static
1
-
-
50.4
113.9
410
mA
Supply Current (Dynamic)
Power Dissipation (Dynamic)
CC,dynamic
1
166.3
mW
P
D
1. Typical: 3.3V, 20pF load, 25 °C; Max: 3.6V, 50pF, 70 °C.
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PCI Signal DC Characteristics
The following table summarizes the DC characteristic parameters for all PCI signals listed below as they apply to
the S5320.
AD[31:0] (t/s), PAR (t/s), C/BE[3:0]# (in), FRAME# (in), IRDY# (in), TRDY# (s/t/s), STOP# (s/t/s), LOCK# (in),
IDSEL (in), DEVSEL# (s/t/s), PERR# (s/t/s), SERR# (o/d), INTA# (o/d), RST# (in), CLK (in).
Table 3. PCI Signal DC Characteristics (V = 3.3V ± 5%, 0°C to 70°C, 50 pF load on outputs)
CC
Symbol
Parameter
Input High Voltage
Min
Max
-
Units
Test Conditions
Notes
V
V
I
2.0
V
1
IH
-
-
0.8
V
µA
V
1
2
Input Low Voltage
IL
±10
-
Input Leakage Current
Output High Voltage
Output Low Voltage
Input Pin Capacitance
CLK Pin Capacitance
IDSEL Pin Capacitance
IL
V
2.4
-
I
= -500 µA
OUT
OH
OL
V
0.4
10
12
8
V
I
= 1500 µA
3
4
OUT
C
C
C
-
pF
pF
pF
IN
5
-
CLK
IDSEL
Notes:
1. Recommended values for all PCI signals except CLK to be V = 2.4 V Min and V = 0.4 V Max.
IH IL
2. Input leakage applies to all inputs and bi-directional buffers.
3. PCI bus signals without pull-up resistors will provide the 3 mA output current. Signals which require a pull-up resistor will provide 6 mA output
current.
4. The PCI specification limits all PCI inputs not located on the motherboard to 10 pF (the clock is allowed to be 12 pF).
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Data Sheet
Add-On Signal DC Characteristics
The following table summarizes the Add-On DC characteristic parameters for the Add-On signals listed below as
they apply to the S5320. All Add-On signal outputs listed are capable of sinking or sourcing 4 mA with the excep-
tion of BPCLK which can sink or source 8 mA.
DQ[31:0] (t/s), ADR[6:2] (in), BE[3:0]# (in), SELECT# (in), RD# (in), WR# (in), PTATN# (out), PTBE[3:0]# (out),
PTNUM[1:0] (out), PTWR (out), PTBURST# (out), PTADR# (I/O), PTRDY# (in), PTMODE (in), DXFR# (out),
SYSRST# (out), IRQ# (out), ADDINT# (in), BPCLK (out), ADCLK (in), DQMODE (in), MDMODE (in), MD[7:0] (I/O),
LOAD# (in).
Table 4. Add-On Operating Characteristics (V = 3.3V ± 5%, 0°C to 70°C, 50 pF load on outputs)
CC
Test
Conditions
Symbol
Parameter
Input High Voltage
Min
Max
-
Units
Notes
V
V
I
2.0
V
IH
IL
-
-
0.8
V
µA
V
Input Low Voltage
±10
-
Input Leakage Current
Output High Voltage
Output Low Voltage
IL
V
2.4
-
I
I
= -500 µA
OUT
OH
OL
V
0.4
V
= 1500 µA
OUT
nvRAM Memory Interface Signals
SCL 8 mA (o/d)
SDA 8 mA (bi-directional-o/d)
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Data Sheet
TIMING SPECIFICATION
PCI Clock Specification
Table 5 summarizes the A.C. characteristics for the PCI bus signals as they apply to the S5320. The figures after
Table 5 visually indicate the timing relationships.
Table 5. Functional Operation Range
(V = 3.3V ± 5%, 0°C to 70°C, 50 pF load on outputs for MAX, 0 pF load for MIN)
CC
Symbol
Parameter
Min
Max
Units
Notes
T
30
-
ns
Clock Time
cyc
t
t
t
t
11
11
1
-
-
ns
ns
CLK High Time
CLK Low Time
Rise Time (0.2V
Fall Time (0.6V
1
2
3
4
4
4
V/ns
V/ns
ns
to 0.6V
load)
CC
1
1
CC
1
to 0.2V
load)
CC
CC
CLK to Signal Valid Delay (Bused Signals)
CLK to Signal Valid Delay (Point-to-Point Signals)
2
2
11
12
t
1,2
5
t
t
t
t
2
-
-
28
-
ns
ns
ns
ns
Float to Active Delay
3
3
4
4
6
7
8
9
Active to Float Delay
7
0
Rising Edge Setup
-
Hold from PCI Clock Rising Edge
Notes:
1. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate is met across the minimum peak-to-peak portion
of the clock waveform as shown in Figure 1.
2. Minimum times are evaluated with 0 pF equivalent load; maximum times are evaluated with 50 pF equivalent load.
3. For purposes of Active/Float timing measurements, the Hi-Z or "off" state is defined to be when the total current delivered through the com-
ponent pin is less than or equal to the leakage current specification.
4. See the timing measurement conditions in Figure 3.
Figure 1. PCI Clock Timing
t1
t4
t3
0.6VCC
0.2VCC
0.6VCC
0.2VCC
VIH2
t2
TCL
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Data Sheet
Figures 2 and 3 define the conditions under which timing measurements are made. The user designs must guaran-
tee that minimum timings are met with maximum clock skew rate (fastest edge) and voltage swing.
Figure 2. PCI Signal Output Timing
PCI CLK
1.5
t5
OUTPUT
1.5
DELAY
TRI-STATE
1.5
1.5
OUTPUT
t6
t7
Figure 3. PCI Signal Input Timing
PCI CLK
INPUT
t8
t9
INPUTS VALID
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S5320 – PCI Match Maker: Electrical Characteristics
Data Sheet
Add-On Signal Timings
Table 6 summarizes the A.C. characteristics for the Add-On bus signals as they apply to the S5320. The figures
after Table 6 visually indicate the timing relationships.
Table 6. Add-On Timings, Functional Operation Range
(V = 3.3V ± 5%, 0°C to 70°C, 50 pF load on outputs for MAX, 0 pF load for MIN)
CC
Symbol
TACL
Parameter
Min
25
Max
Units
ns
Notes
ADCLK Cycle Time
ADCLK High Time
ADCLK Low Time
-
-
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
10
ns
10
11
10
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
2.5
ADCLK Rise Time (0.2V
ADCLK Fall Time (0.6V
to 0.6V
)
12
13
14
15
16
17a
17b
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
CC
CC
-
2.5
to 0.2V
)
CC
CC
-
7.1
PCICLK to BPCLK Delay, Rising
PCICLK to BPCLK Delay, Falling
-
-
6.2
13.1
1
1
1
PTADR# Low to DQ[31:0] Output Valid
PTADR# High to DQ[31:0] Output Hold
PTADR# High to DQ[31:0] Output Float
PTATN# Valid from ADCLK Rising Edge
PTATN# Hold from ADCLK Rising Edge
PTBURST# Valid from ADCLK Rising Edge
PTBURST# Hold from ADCLK Rising Edge
PTNUM[1:0] Valid from ADCLK Rising Edge
PTNUM[1:0] Hold from ADCLK Rising Edge
PTWR Valid from ADCLK Rising Edge
PTWR Hold from ADCLK Rising Edge
PTBE[3:0]# Valid from ADCLK Rising Edge
PTBE[3:0]#Hold from ADCLK Rising Edge
PTWAIT# Setup to ADCLK Rising Edge
PTWAIT# Hold from ADCLK Rising Edge
SELECT# Setup to ADCLK Rising Edge
SELECT# Hold from ADCLK Rising Edge
ADR[6:2] Setup to ADCLK Rising Edge
ADR[6:2] Hold from ADCLK Rising Edge
2
-
-
11.9
-
13.5
4
-
-
13
3.85
-
-
14.4
4
-
-
13.2
4
-
-
14.4
3
-
-
-
-
-
-
-
11
1
8.9
1
9.3
1
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Data Sheet
Table 6. Add-On Timings, Functional Operation Range
(V = 3.3V ± 5%, 0°C to 70°C, 50 pF load on outputs for MAX, 0 pF load for MIN) (Continued)
CC
Symbol
Parameter
Min
Max
Units
Notes
t
t
t
t
t
t
t
t
t
t
t
8.3
-
ns
BE[3:0]# Setup to ADCLK Rising Edge
BE[3:0]# Hold from ADCLK Rising Edge
RD# Setup to ADCLK Rising Edge
34
1
6.7
1
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
35
36
37
38
39
40
41
42
43
44
-
-
RD# Hold from ADCLK Rising Edge
-
16
2
2
2
DQ[31:0] Output Valid from ADCLK Rising Edge
DQ[31:0] Output Hold from ADCLK Rising Edge
DQ[31:0] Output Float from ADCLK Rising Edge
WR# Setup to ADCLK Rising Edge
3
-
-
15.6
-
7.4
1
-
-
-
WR# Hold from ADCLK Rising Edge
5.4
1
2
2
DQ[31:0] Input Setup to ADCLK Rising Edge
DQ[31:0] Input Hold from ADCLK Rising Edge
Notes:
1. Refers to Pass-Thru Passive mode only.
2. Refers to Pass-Thru Active and Passive modes.
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Figure 4. Add-On Clock Timing
t10
t12
t13
0.6VCC
0.6VCC
0.2VCC
V
IH
2
0.2VCC
t11
TACL
Figure 5. Pass-Thru Clock Relationship to PCI Clock
PCI CLK
t14
t15
BPCLK
Figure 6. PTADR Timing
PTADR#
t17a
t16
t17b
DQ[31:0]
ADDRESS
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Figure 7. Passive Mode Pass-Thru Operation
ADCLK
t19
PTATN#
t18
t21
PTBURST#
t20
PTNUM[1:0]
PTWR
Valid Out
Valid Out
Valid Out
t22
t24
t26
t23
t25
t27
PTBE[3:0]
PTRDY#
SELECT#
ADR[6:2]
BE[3:0]
t29
t28
t31
t30
t33
t35
t32
t34
t37
RD#
t36
t40
DQ[31:0]
WR#
Valid Out
t38
t42
t39
t41
DQ[31:0]
t43
t44
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Table 7. Add-On Timings
Functional Operation Range (V = 3.3V ± 5%, 0°C to 70°C, 50 pF load on outputs for MAX,
CC
0 pF load for MIN)
Symbol
Parameter
Min
Max
Units
Notes
t
t
t
t
t
t
t
-
12.5
ns
DXFER# Valid from ADCLK Rising Edge
DXFER# Hold from ADCLK Rising Edge
PTADR# Valid from ADCLK Rising Edge
PTADR# Hold from ADCLK Rising Edge
DQ[31:0] Address Valid from ADCLK Rising Edge
DQ[31:0] Hold from ADCLK Rising Edge
DQ[31:0] Address Float from ADCLK Rising Edge
45
3
-
-
14
-
ns
ns
ns
ns
ns
ns
46
47
48
49
50
51
3
-
17.3
-
1
1
1
3
-
16.9
Notes:
1. Refers to Pass-Thru Active mode only.
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Data Sheet
Figure 8. Active Mode Pass-Thru Write Operation
ADCLK
t19
PTATN#
t18
PTBURST#
PTNUM[1:0]
PTWR
Valid Out
Valid Out
Valid Out
t22
t23
t25
t27
t46
t24
PTBE[3:0]
DXFER#
PTWAIT#
PTADR#
DQ[31:0]
t26
t45
t28
t29
t47
t48
t40
Address
t50
Data
t49
t38
t39
t51
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Table 8. Mailbox Timings
Functional Operation Range (V = 3.3V ± 5%, 0°C to 70°C, 50 pF load on outputs)
CC
Symbol
Parameter
Min
Max
Units
Notes
t
t
t
t
t
t
4
-
ns
LOAD# Setup to ADCLK Rising Edge
LOAD# Hold from ADCLK Rising Edge
MD[7:0] Setup to ADCLK Rising Edge
MD[7:0] Hold from ADCLK Rising Edge
MD[7:0] Float from LOAD# Low
60
61
62
63
64
65
1
2.6
1
-
-
ns
ns
ns
ns
ns
1,2
1,2
2
-
-
14.9
17
-
2,3
MD[7:0] Active from ADCLK Rising Edge
Notes:
1. Applies only when external mailbox is in input mode (MDMODE = 1).
2. Applies only when external mailbox is in input/output mode (MDMODE = 0).
3. When the S5320 is driving MD[7:0] w/ Add-On incoming mailbox byte 3, the PCI can update this output synchronously to the PCI clock. As a
result, once driving, this output is asynchronous to ADCLK.
Figure 9. Mailbox Data (Setup/Hold timing)
ADCLK
t61
LOAD#
t60
t63
MD[7:0]
t62
Figure 10. Mailbox Data (Float/Active timing)
ADCLK
t60
t61
LOAD#
MD[7:0]
t64
t62
t65
5320
Driv ing
5320
Driving
Add-On Driving
t63
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Data Sheet
PACKAGE INFORMATION
Figure 11. S5320 Pinout and Pin Assignment
PTBE0#
133
88
87
86
85
84
83
82
81
DQ11
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
RSVD5
PTBE2#
INTA#
PTBE1#
VCC
RSVD2
RSVD3
SELECT#
GND
PTWR
MD4
MD3
DQ12
MD2
VCC
ADR3
ADR4
BE3#
ADR2
BE1#
BE2#
GND
DQ13
DQ26
MD1
DQ27
MD0
DQ28
DQ29
ADDINT#
VCC
VCC
DQ14
DQ30
DQ15
GND
GND
GND
DQ31
AD0
AD1
AD2
VCC
AD3
GND
AD4
AD5
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
DQ19
DQMODE
DQ1
DQ18
PTBURST#
VCC
PTATN#
LOAD#
PTNUM1
GND
GND
S5320
(176 LQFP)
GND
PTNUM0
RSVD4
DQ17
DQ0
DQ16
MDMODE
VCC
VCC
PTMODE
FLT#
PTBE3#
ADCLK
RST#
CLK
AD31
AD30
GND
AD29
AD28
VCC
AD27
AD26
AD6
AD7
C/BE0#
VCC
AD8
REVISION 1.5 (10/21/03)
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S5320 – PCI Match Maker: Electrical Characteristics
Data Sheet
Figure 12. 176 Pin Low Profile Quad Flat Pack (LQFP), 24 mm x 24 mm
Thermal Management ( TA = 70 °C)
Air Flow
Theta ja
Theta jc
0 m/sec
1 m/sec
2 m/sec
42.9 °C/W
41.3 °C/W
39.2 °C/W
11.4 °C/W
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Data Sheet
S5320 Pin Assignment - 176 LQFP
Pin#
Signal
SERR#
PAR
Type
o/d
t/s
t/s
t/s
V
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Pin#
Signal
AD25
GND
Type
t/s
V
1
C/BE1#
AD15
GND
AD14
VCC
2
3
AD24
C/BE3#
IDSEL
VCC
t/s
t/s
in
4
t/s
V
5
6
V
AD13
AD12
AD11
AD10
GND
AD9
t/s
t/s
t/s
t/s
V
7
AD23
AD22
AD21
GND
t/s
t/s
t/s
V
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
AD20
AD19
AD18
VCC
t/s
t/s
t/s
V
t/s
t/s
V
AD8
VCC
C/BE0#
AD7
t/s
t/s
t/s
V
AD17
AD16
C/BE2#
GND
t/s
t/s
t/s
V
AD6
AD5
AD4
t/s
V
FRAME#
IRDY#
TRDY
VCC
t/s
t/s
t/s
V
GND
AD3
t/s
V
VCC
AD2
t/s
t/s
t/s
t/s
V
VCC
V
AD1
DEVSEL#
GND
t/s
V
AD0
DQ31
GND
GND
GND
DQ15
DQ30
DQ14
GND
V
GND
V
V
STOP#
LOCK#
VCC
t/s
t/s
V
V
t/s
t/s
t/s
PERR#
t/s
156
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S5320 – PCI Match Maker: Electrical Characteristics
Data Sheet
Pin#
Signal
VCC
Type
V
Pin#
Signal
DQ6
Type
t/s
t/s
t/s
t/s
t/s
V
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
VCC
V
DQ23
DQ5
ADDINT#
DQ29
DQ28
MD0
out
t/s
t/s
t/s
t/s
t/s
t/s
t/s
V
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
DQ22
DQ21
GND
DQ27
MD1
WR#
in
ADR5
VCC
in
DQ26
DQ13
GND
V
VCC
V
DQ20
DQ4
t/s
t/s
t/s
t/s
t/s
t/s
V
BE2#
BE1#
ADR2
BE3#
ADR4
ADR3
VCC
in
in
MD6
in
DQ3
in
DQ2
in
MD7
in
GND
V
GND
V
MD2
t/s
t/s
t/s
t/s
out
t/s
t/s
V
GND
V
DQ12
MD3
BE0#
VCC
in
V
MD4
SYSRST#
RD#
out
in
PTWR
DQ11
DQ25
GND
BPCLK
PTADR#
GND
out
in
V
DQ10
DQ9
t/s
t/s
t/s
t/s
V
IRQ#
out
--
RSVD1
DXFER#
EWR#/SDA
VCC
DQ8
out
t/s
V
MD5
VCC
DQ7
t/s
t/s
ADR6
PTRDY#
in
DQ24
in
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S5320 – PCI Match Maker: Electrical Characteristics
Data Sheet
Pin#
131
Signal
ERD#/SCL
GND
Type
out
V
Pin#
164
Signal
FLT#
Type
in
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
165
166
167
168
169
170
171
172
173
174
175
176
PTBE3#
ADCLK
RST#
CLK
out
in
PTBE0#
RSVD5
PTBE2#
INTA#
out
—
out
out
out
V
in
in
AD31
AD30
GND
t/s
t/s
V
PTBE1#
VCC
RSVD2
RSVD3
SELECT#
GND
—
—
in
AD29
AD28
VCC
V
V
V
V
AD27
AD26
t/s
t/s
DQ19
t/s
in
DQMODE
DQ1
t/s
t/s
out
V
DQ18
PTBURST#
VCC
PTATN#
LOAD
out
in
PTNUM1
GND
out
V
GND
V
GND
V
PTNUM0
RSVD4
DQ17
out
—
t/s
t/s
t/s
in
DQ0
DQ16
MDMODE
VCC
V
VCC
V
PTMODE
in
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DOCUMENT REVISION HISTORY
Data Sheet
Revision
5.03
Date
Description
5/14/06
5/02/06
•
•
page 23, updated Table 5
5.02
page 26 updated Signal and Description columns in Table 9 (pins 125, 139, 140, 156, and
134) added RSVD1 - 5
•
page 157 - 158, updated Pin# 102, 117, and 156
5.01
5.00
11/24/04
8/20/04
•
•
page 20, Figure 5, removed pin assignment reference
page 160, added Development Kit ordering information
•
•
•
page 3updated feature list
Page 92, updated read transfers section
Pages 121 - 139,
- updated Pass-Thru Passive Mode Operation description
- added Pass-Thru Active Mode Operation description
- added Pass-Thru Configuration description
4.00
3.00
5/28/04
3/30/04
•
•
Table 2 on page 142updated T
J
page 160updated ordering information.
•
•
•
page 4updated package information.
Table 1 on page 142updated supply and input voltage, added ESD rating
Table 2 on page 142updated Icc and P , added T
D
J
•
•
•
•
•
•
•
Table 3 on page 143updated VIH, VIL, VOH, VOL
Table 4 on page 144 updated VIH, VIL, VOH, VOL
page 144updated SCL and SDA current
Table 6 on page 147updated t14, t21, and t24
Table 8 on page 153 updated t60 and t62
Table 9, Mailbox Data (Setup/Hold timing) and 10, updated
Table 12, 176 Pin Low Profile Quad Flat Pack (LQFP), 24 mm x 24 mm, updated package
spec, added thermal management data
•
page 159added document revision history
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S5320 – PCI Match Maker: Electrical Characteristics
Data Sheet
ORDERING INFORM ATION
Device Ordering Part Number
Device
Package
Package Options
Blank = Standard
AAB = Lead Free
S5320
QF = 176 Pin LQFP
SXXXX
Device
XX
XXX
Option
Package/Type
Development Kit Ordering Part Number
P/N Description
The Kit includes:
Development Kit Manual
Evaluation Board
S5320DK
Schematic, PCB, CPLD, BOM,
NVRAM Tool, Application Software
Applied Micro Circuits Corporation
6290 Sequence Dr., San Diego, CA 92121
Phone: (858) 450-9333 — (800) 755-2622 — Fax: (858) 450-9885
http://www.amcc.com
AMCC reserves the right to make changes to its products, its datasheets, or related documentation, without notice and war-
rants its products solely pursuant to its terms and conditions of sale, only to substantially comply with the latest available
datasheet. Please consult AMCC’s Term and Conditions of Sale for its warranties and other terms, conditions and limitations.
AMCC may discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest
version of relevant information to verify, before placing orders, that the information is current. AMCC does not assume any lia-
bility arising out of the application or use of any product or circuit described herein, neither does it convey any license under
its patent rights nor the rights of others. AMCC reserves the right to ship devices of higher grade in place of those of lower
grade.
AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE
SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL
APPLICATIONS.
AMCC is a registered Trademark of Applied Micro Circuits Corporation. Copyright © 2006 Applied Micro Circuits Corporation.
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