NPE405H-3JA266C_技术文档

Part Number NPe405H

Revision 1.02 – November 16, 2007

Data Sheet

NPe405H

PowerNP NPe405H Embedded Processor

- Programmable critical interrupt priority ordering

- Programmable critical interrupt vector

Programmable timers

FEATURES

™

•

PowerNP technology using an AMCC Pow-

•

®

erPC 405 32-bit RISC processor core operat-

Two serial ports (16550 compatible UART)

One IIC interface

ing up to 266 MHz

•

PC-133 synchronous DRAM (SDRAM) inter-

face

General Purpose I/O (GPIO) available

Supports JTAG for board level testing

- 32-bit interface for non-ECC applications

Internal processor local bus (PLB) runs at

SDRAM interface frequency

- 40-bit interface serves 32 bits of data plus 8

check bits for ECC applications

•

Supports PowerPC processor boot from PCI

memory

•

External bus for peripheral devices

- Flash and ROM interface

User accessible performance counters

- Direct support for 8-, or 16-, or 32-bit SRAM

and external peripherals

DESCRIPTION

- Up to 8 devices

Designed specifically to address embedded applica-

tions, the NPe405H provides a high-performance, low-

power solution that interfaces to a wide range of

peripherals by incorporating on-chip power manage-

ment features and lower power dissipation

requirements.

- External mastering supported

•

DMA support for external peripherals, internal

UARTs and memory

- Scatter-gather chaining supported

- Four channels

PCI Revision 2.2 compliant interface (32-bit, up

to 66MHz)

This chip contains a high-performance RISC proces-

sor core, SDRAM controller, PCI bus bridge, Ethernet

EMACs, HDLC controllers, external bus controller for

ROM, Flash, and peripherals, DMA with scatter-gather

support, serial ports, IIC interface, and general pur-

pose I/O.

- Asynchronous PCI bus interface

- Internal PCI bus arbiter which can be dis-

abled for use with an external arbiter

•

Four 10/100 Ethernet MACs supporting up to

four external PHYs via MII, RMII, or SMII inter-

faces

Technology: CMOS SA-12E 0.25 µm

(0.18 µm L )

Package: 35mm, 580-ball enhanced plastic ball grid

array (E-PBGA)

Power (typical): 2.3W at 133MHz, 2.9W at 200MHz,

3.4W at 266MHz

eff

HDLC interface with 32 channels through two

ports at up to 4.096 Mbps each or 8.192 Mbps

for a single port

•

HDLC interface with 8 channels through 8

ports at 2.048 Mbps maximum

Programmable interrupt controller

- Seven external and 49 internal

- Edge triggered or level-sensitive

- Positive or negative active

- Non-critical or critical interrupt to processor

core

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NPe405H – PowerNP NPe405H Embedded Processor

TABLE OF CONTENTS

Data Sheet

FEATURES .............................................................................................................................................................. 1

DESCRIPTION ........................................................................................................................................................ 1

ORDERING, PVR, AND JTAG INFORMATION ...................................................................................................... 5

AMCC Part Number Key ................................................................................................................................. 5

NPE405H EMBEDDED CONTROLLER FUNCTIONAL BLOCK DIAGRAM ......................................................... 6

ADDRESS MAP SUPPORT .................................................................................................................................... 7

SYSTEM ADDRESS MAP ....................................................................................................................................... 7

DCR ADDRESS MAP .............................................................................................................................................. 8

PLB TO PCI BRIDGE .............................................................................................................................................. 9

SDRAM MEMORY CONTROLLER ....................................................................................................................... 10

EXTERNAL BUS CONTROLLER (EBC) .............................................................................................................. 10

DMA CONTROLLER ............................................................................................................................................. 11

SERIAL INTERFACE ............................................................................................................................................ 11

IIC BUS INTERFACE ............................................................................................................................................ 11

IIC EEPROM CONTROLLER ................................................................................................................................ 11

HDLCEX INTERFACE ........................................................................................................................................... 12

HDLCMP INTERFACE .......................................................................................................................................... 12

GENERAL PURPOSE IO (GPIO) CONTROLLER ................................................................................................ 12

UNIVERSAL INTERRUPT CONTROLLER (UIC) ................................................................................................. 12

10/100 MBPS ETHERNET MAC ........................................................................................................................... 13

JTAG ..................................................................................................................................................................... 13

PERFORMANCE COUNTERS .............................................................................................................................. 13

35 MM, 580-BALL E-PBGA PACKAGE ............................................................................................................... 14

SIGNAL LISTS ...................................................................................................................................................... 15

SIGNALS LISTED ALPHABETICALLY ................................................................................................................ 15

SIGNALS LISTED BY BALL ASSIGNMENT ........................................................................................................ 32

SIGNAL DESCRIPTION ........................................................................................................................................ 41

PIN SUMMARY ..................................................................................................................................................... 41

Multiplexed Pins ............................................................................................................................................ 41

Multipurpose Pins ......................................................................................................................................... 41

Initialization Strapping .................................................................................................................................. 41

Pull-up and Pull-down Resistors ................................................................................................................. 42

Unused I/Os .................................................................................................................................................... 42

External Peripheral Bus Control Signals .................................................................................................... 42

SIGNAL FUNCTIONAL DESCRIPTION ................................................................................................................ 43

ABSOLUTE MAXIMUM RATINGS ........................................................................................................................ 52

PACKAGE THERMAL SPECIFICATIONS ........................................................................................................... 52

RECOMMENDED DC OPERATING CONDITIONS .............................................................................................. 53

5 V-TOLERANT I/O INPUT CURRENT ................................................................................................................. 54

INPUT CAPACITANCE ......................................................................................................................................... 54

DC ELECTRICAL CHARACTERISTICS ............................................................................................................... 55

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Data Sheet

TEST CONDITIONS .............................................................................................................................................. 55

CLOCKING SPECIFICATIONS ............................................................................................................................. 56

CLOCKING WAVEFORM ...................................................................................................................................... 56

SPREAD SPECTRUM CLOCKING ....................................................................................................................... 57

PERIPHERAL INTERFACE CLOCK TIMINGS ..................................................................................................... 58

INPUT SETUP AND HOLD WAVEFORM ............................................................................................................. 59

OUTPUT DELAY AND FLOAT TIMING WAVEFORM ......................................................................................... 59

I/O SPECIFICATIONS—ALL ................................................................................................................................ 60

I/O SPECIFICATIONS(A)—133 AND 200 MHZ .................................................................................................... 62

I/O SPECIFICATIONS(A)—266 MHZ .................................................................................................................... 65

INITIALIZATION .................................................................................................................................................... 68

Strapping ......................................................................................................................................................... 68

STRAPPING PIN ASSIGNMENTS ........................................................................................................................ 68

EEPROM ......................................................................................................................................................... 68

DOCUMENT REVISION HISTORY ....................................................................................................................... 69

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LIST OF FIGURES

Data Sheet

Figure 1. NPe405H Embedded Controller Functional Block Diagram ..................................................................... 6

Figure 2. 35mm, 580-Ball E-PBGA Package ......................................................................................................... 14

Figure 3. 5V-Tolerant I/O Input Current ................................................................................................................. 54

Figure 4. Clocking Waveform ................................................................................................................................. 56

Figure 5. Input Setup and Hold Waveform ............................................................................................................. 59

Figure 6. Output Delay and Float Timing Waveform .............................................................................................. 59

LIST OF TABLES

Table 1. System Address Map 4GB Total System Memory ..................................................................................... 7

Table 2. DCR Address Map 4KB Device Configuration Register ............................................................................. 8

Table 3. Signals Listed Alphabetically ................................................................................................................... 15

Table 4. Signals Listed by Ball Assignment ........................................................................................................... 32

Table 5. Pin Summary ........................................................................................................................................... 41

Table 6. Signal Functional Description .................................................................................................................. 43

Table 7. Absolute Maximum Ratings ..................................................................................................................... 52

Table 8. Package Thermal Specifications .............................................................................................................. 52

Table 9. Recommended DC Operating Conditions ................................................................................................ 53

Table 10. Input Capacitance .................................................................................................................................. 54

Table 11. DC Electrical Characteristics .................................................................................................................. 55

Table 12. Clocking Specifications .......................................................................................................................... 56

Table 13. Peripheral Interface Clock Timings ........................................................................................................ 58

Table 14. I/O Specifications—All ........................................................................................................................... 60

Table 15. I/O Specifications—133 and 200MHz .................................................................................................... 62

Table 16. I/O Specifications—266MHz .................................................................................................................. 65

Table 17. Strapping Pin Assignments .................................................................................................................... 68

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Data Sheet

ORDERING, PVR, AND JTAG INFORMATION

Processor

Rev

Level

Order Part Number¹

NPe405H-3JA200C

Product Name

Package

PVR Value

JTAG ID

Frequency

200MHz

266MHz

200MHz

266MHz

NPe405H

35mm, 580 E-PBGA

A

0x41410140

0x04267049

NPe405H-3JA200CZ

NPe405H-3JA266C

NPe405H-3JA266CZ

NPe405H-3BA200C

NPe405H-3BA200CZ

NPe405H-3BA266C

NPe405H-3BA266CZ

1. Z at the end of the Order Part Number indicates a tape and reel shipping package. Otherwise, the chips are shipped in a tray. Package

type B contains lead; package type J is lead-free.

This section provides the part numbering nomenclature for the NPe405H. For availability, contact your local AMCC

sales office.

The part number contains a part modifier. This modifier provides for identification of future enhancements (for

example, higher performance).

Each part number also contains a revision code. This refers to the die mask revision number and is specified in the

part numbering scheme for identification purposes only.

The PVR (Processor Version Register) is software accessible and contains additional information about the revi-

sion level of the part. Refer to the NPe405H User’s Manual for details on the register content.

AMCC Part Number Key

NPe405H-3xA200Cx

Shipping Package

Blank = Tray

Z = Tape and reel

AMCC Part Number

Grade 3 Reliability

Operational Case Temperature Range

(-40°C to +85°C)

Package (E-PBGA)

B = Leaded

Processor Speed

200 MHz

J = Lead Free

266 MHz

Revision Level

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Data Sheet

NPE405H EMBEDDED CONTROLLER FUNCTIONAL BLOCK DIAGRAM

Figure 1. NPe405H Embedded Controller Functional Block Diagram

Clock

Control

Reset

See Peripheral Interface

Power

Mgmt

Universal

Interrupt

Controller

x2

DCRs

Timers

MMU

GPIO

x2

UART

x2

PPC405

Processor Core

IEC

IIC

DCR Bus

Trace

ICU

JTAG

DCU

16KB

I-Cache

8KB

D-Cache

On-chip Peripheral Bus (OPB)

Arb

DMA

OPB

Bridge

Controller

(4-Channel)

Processor Local Bus (PLB)

Ethernet

x4

MAL0

MAL1

HDLCEX

External

Bus

Controller

External

SDRAM

Controller

Bus Master

PCI Bridge

MAL2

Controller

ZMII

HDLCMP

13-bit addr

32-bit data

32-bit addr

32-bit data

66 MHz max (async)

Two

32-channel

ports

8

MII, RMII,

SMII

single-channel

ports

The NPe405H is designed using the IBM Microelectronics Blue Logic™ methodology in which major functional

blocks are integrated to create an application-specific ASIC product. This approach provides a consistent way to

generate complex ASICs using IBM CoreConnect™ Bus Architecture.

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ADDRESS MAP SUPPORT

Data Sheet

The NPe405H incorporates two separate address maps. The first is a fixed processor address map that serves the

PowerPC family of processors. This address map defines the possible contents of various address regions which

the processor can access. The second address map is for Device Configuration Registers (DCRs). The DCRs are

accessed by software running on the NPe405H processor through the use of mtdcr and mfdcr commands.

SYSTEM ADDRESS MAP

Table 1. System Address Map 4GB Total System Memory

Function

Subfunction

Start Address

0x00000000

0xE8010000

0xEC000000

0xEEE00000

0xEF500000

0xEF900000

End Address

0xE7FFFFFF

0xE87FFFFF

0xEEBFFFFF

0xEF3FFFFF

0xEF5FFFFF

0xFFFFFFFF

Size

3712MB

8MB

SDRAM, External peripherals, and PCI

memory

44MB

6MB

General use

Note: Any of the address ranges listed at

right may be use for any of the above

functions.

1MB

263MB

1

0xFFE00000

0xFFFE0000

0xFFFFFFFF

2MB

External peripheral bus boot

Boot-up

PCI

2

128KB

PCI boot

PCI I/O

0xE8000000

0xE8800000

0xEEC00000

0xEED00000

0xEF400000

0xEF600300

0xEF600400

0xEF600500

0xEF600600

0xEF600700

0xEF600780

0xEF600800

0xEF600900

0xEF600A00

0xEF600B00

0xEF600C10

0xEF610000

0xEF620000

0xE800FFFF

0xEBFFFFFF

0xEEC00007

0xEED00003

0xEF40003F

0xEF600307

0xEF600407

0xEF60051F

0xEF60063F

0xEF60077F

0xEF6007FF

0xEF6008FF

0xEF6009FF

0xEF600AFF

0xEF600BFF

0xEF600C1F

0xEF61FFFF

0xEF62FFFF

64KB

56MB

8B

PCI I/O

Configuration registers

Interrupt Acknowledge and special cycle

Local configuration registers

UART0

4B

64B

8B

UART1

8B

IIC0

32B

OPB arbiter

64B

GPIO0 controller registers

GPIO1 controller registers

Ethernet MAC 0 registers

Ethernet MAC 1 registers

Ethernet MAC 2 registers

Ethernet MAC 3 registers

ZMII control registers

HDLCEX

128B

256B

16B

Internal peripherals

64KB

HDLCMP

Notes:

1. When external peripheral bus boot is selected, peripheral bank 0 is automatically configured at reset to the address range listed above.

2. If PCI boot is selected, a PLB-to-PCI mapping is automatically configured at reset to the address range listed above.

3. After the boot process, software may reassign the boot memory regions for other uses.

4. All address ranges not listed above are reserved.

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Data Sheet

DCR ADDRESS MAP

Table 2. DCR Address Map 4KB Device Configuration Register

Function

Start

End

Size

1KW (4KB)¹

1

0x000

0x3FF

DCR address space

Reserved

0x000

0x010

0x012

0x014

0x080

0x090

0x092

0x0A0

0x0A8

0x0B0

0x0B8

0x0C0

0x0D0

0x0E0

0x0F0

0x100

0x140

0x180

0x200

0x280

0x300

0x00F

0x011

0x013

0x07F

0x08F

0x091

0x09F

0x0A7

0x0AF

0x0B7

0x0BF

0x0CF

0x0DF

0x0EF

0x0FF

0x13F

0x17F

0x1FF

0x27F

0x2FF

0x3FF

16W

2W

Memory controller registers

External bus controller registers

Reserved

2W

108W

16W

2W

PLB registers

Performance counters

Reserved

14W

8W

OPB bridge-out registers

Reserved

8W

Clock, control and reset

Power management

Interrupt controller 0

Interrupt controller 1

Reserved

8W

16W

64W

128W

256W

Miscellaneous

DMA controller registers

Reserved

MAL0 registers (Ethernet)

MAL1 registers (HDLCEX)

MAL2 registers (HDLCMP)

Reserved

Notes:

1. DCR address space is addressable with up to 10 bits (1024 or 1K unique addresses). Each unique address represents a single 32-bit (word) register, or 1 kiloword (KW) (which

equals 4 KB).

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PLB TO PCI BRIDGE

Data Sheet

The PLB to PCI bridge provides a mechanism for connecting PCI devices to the processor, peripherals, and mem-

ory. This interface is PCI Specification rev 2.2 compliant.

Features include:

•

Internal PCI bus arbiter for up to six external devices at PCI bus speeds up to 66MHz. Internal arbiter use is

optional and can be disabled for systems which employ an external arbiter.

•

PCI bus frequency up to 66MHz

- Asynchronous operation from 1/8 PLB frequency to 66MHz maximum

32-bit PCI Address/Data Bus

•

Power Management:

- PCI Bus Power Management v1.1 compliant

Buffering between PLB and PCI:

•

- PCI Target 64-byte write post buffer

- PCI Target 96-byte read prefetch buffer

- PLB Slave 32-byte write post buffer

- PLB Slave 64-byte read prefetch buffer

Error tracking/status

•

Supports PCI Target side configuration

Supports processor access to all PCI address spaces:

- Single-byte PCI I/O reads and writes

- PCI memory single-beat and prefetch-burst reads and single-beat writes

- Single-byte PCI configuration reads and writes (type 0 and type 1)

- PCI interrupt acknowledge

- PCI special cycle

•

Supports PCI target access to all PLB address spaces

Supports PowerPC processor boot from PCI memory

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SDRAM MEMORY CONTROLLER

Data Sheet

The NPe405H Memory Controller provides a low latency access path to SDRAM memory. The memory controller

supports four logical banks. Up to 256MB per bank are supported, for a maximum of 1GB total. Memory access

and refresh timing, address and bank sizes, and memory addressing modes are programmable.

Features include:

•

11x8 to 13x11 row-column address modes (2- and 4-bank devices supported)

Memory bus operates at same frequency as PLB

32-bit memory interface support

Programmable address range for each bank of memory

- 4GB address space

•

Industry standard 168-pin DIMMS are supported (some configurations)

200 MHz NPe405H supports up to 100 MHz memory with PC100 support

266 MHz NPe405H supports up to 133 MHz memory with PC133 support

4MB to 256MB per bank

Programmable timing

Auto refresh

Page Mode Accesses with up to 4 open pages

Power Management (self-refresh)

Error Checking and Correction (ECC) support

- Standard single error correct, double error detect coverage

- Aligned nibble error detect

- Address error logging

EXTERNAL BUS CONTROLLER (EBC)

•

Supports eight ROM, EPROM, SRAM, Flash, and Slave Peripheral I/O banks supported

Up to 66.66MHz operation

Burst and non-burst devices

8-, 16-, 32-bit byte-addressable data bus width support

Latch data on Ready, Synchronous or Asynchronous

Programmable 2K clock-cycle time-out counter with disable for Ready

Programmable access timing per device

- 0–255 wait states for non-bursting devices

- 0 –31 Burst Wait States for first access and up to 7 Wait States for subsequent accesses

- Programmable chip select assertion/negation relative to driving address bus

- Programmable output and write-enable assertion/negation relative to assertion of chip select

Programmable address mapping

•

Peripheral device wait via “Ready”

External master interface

- Write posting from external master

- Read prefetching on PLB for external master reads

- Bursting capable from external master

- Allows external master access to all non-EBC PLB slaves

- External master can control EBC slaves for own access and control

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DMA CONTROLLER

Data Sheet

•

Supports the following transfers:

- Memory-to-memory transfers

- Buffered peripheral to memory transfers

- Buffered memory to peripheral transfers

Four channels

•

Scatter/Gather capability for programming multiple DMA operations

8-, 16-, 32-bit peripheral support (OPB and external bus attached)

32-bit addressing

Address increment or decrement

Internal 32-byte data buffering capability

Supports internal and external peripherals

Support for memory mapped peripherals

Support for peripherals running on slower frequency buses

SERIAL INTERFACE

•

Two 8-pin UART interfaces provided

Selectable internal or external serial clock to allow wide range of baud rates

Register compatibility with NS16550 register set

Complete status reporting capability

Transmitter and receiver are each buffered with 16-byte FIFOs when in FIFO mode

Fully programmable serial-interface characteristics

Supports DMA using internal DMA engine

IIC BUS INTERFACE

2

•

Compliant with Phillips® Semiconductors I C Specification, dated 1995

Operation at 100kHz or 400kHz

8-bit data

10- or 7-bit address

Slave transmitter and receiver

Master transmitter and receiver

Multiple bus masters

Supports fixed V IIC interface

DD

•

Two independent 4 x 1 byte data buffers

One programmable interrupt request signal

Provides full management of all IIC bus protocol

Programmable error recovery

IIC EEPROM CONTROLLER

Supports setting of processor configuration from serial EEPROM during system reset.

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HDLCEX INTERFACE

Data Sheet

•

32-channel HDLC controller

Two full-duplex Pulse Code Modulation (PCM) Highway ports at speeds up to 4.096 Mbps per port or 8.192

Mbps when using a single port

•

Supports HDLC protocol as well as a Transparent mode

For a single channel per port, autonomous management of I-Frames and S-Frames of the Normal

Response mode (NRM) protocol on one channel per port. U-frames are handled by software.

•

Supports software emulation of NRM on all channels

HDLCMP INTERFACE

•

HDLC controller provides eight full-duplex serial ports

Up to 2.048Mbps data rate

Supports HDLC protocol as well as a Transparent mode

Software emulation of NRM

GENERAL PURPOSE IO (GPIO) CONTROLLER

•

Two GPIO controllers

- 32-signal system GPIO (GPIO0)

- 32-signal communications GPIO (GPIO1)

•

Most GPIOs are pin-shared with other functions. Configuration registers are provided to determine whether

a particular pin that has GPIO capabilities acts as a GPIO or is used for another purpose. Both GPIO func-

tions have 32 I/Os.

Each GPIO output is separately programmable to emulate an open-drain driver (drives to zero, three-stated

if output bit is 1)

UNIVERSAL INTERRUPT CONTROLLER (UIC)

Two cascaded Universal Interrupt Controllers (UICs) provide the control, status, and communications necessary

for the interrupt sources and the PowerPC processor.

Features include:

•

Seven external and 49 internal interrupts

Edge triggered or level-sensitive

Positive or negative active

Selectable non-critical or critical interrupt requests to the PPC405 processor core

Programmable critical interrupt priority ordering

Programmable critical interrupt vector generation for reduced latency interrupt handling

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10/100 MBPS ETHERNET MAC

Data Sheet

•

Four units capable of full- and half-duplex, 10 Mbps or 100 Mbps operation

Integrated ZMII Bridge supports use of MII, SMII or RMII connections to external PHYs (PHYs not included

on chip)

- Reduced Media Independent Interface (RMII) or Serial Media Independent Interface (SMII) for one to four

PHY applications

- Media Independent Interface (MII) for single or dual PHY applications

Dedicated media access layer (MAL) provides DMA support

•

JTAG

•

IEEE 1149.1 Test Access Port

Debugger support

JTAG boundary scan support (BSDL file available)

PERFORMANCE COUNTERS

A series of software accessible PLB transaction event counters that can be used to analyze PLB performance.

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Data Sheet

35 MM, 580-BALL E-PBGA PACKAGE

Figure 2. 35mm, 580-Ball E-PBGA Package

Top View

Gold gate release

corresponds to

Note: All dimensions are in mm.

A01 ball location

0.60 nom

0.30 nom

35.0

Bottom View

1.0

AP

AN

AM

AL

AK

1.0

AJ

AH

AG

AF

AE

AD

AC

AB

AA

Y

W

V

U

T

35.0

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

19 21 23 25 27 29 31 33

01 03 05 07 09 11 13 15 17

08 10

2.65 max

06

12 14

16 18

04

22 24 26 28 30 32 34

02

20

0.60 Solder Ball

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SIGNAL LISTS

Data Sheet

The following table lists all the external signals in alphabetical order and shows the ball number on which the signal

appears. Multiplexed signals are shown with the default signal (following reset) not in brackets and the alternate

signal or signals in brackets. Multiplexed signals appear alphabetically multiple times in the list—once for each sig-

nal name on the ball. The page number listed gives the page in “Signal Functional Description” on page 43 where

the signals in the indicated interface group begin.

SIGNALS LISTED ALPHABETICALLY

Table 3. Signals Listed Alphabetically (Sheet 1 of 17)

Signal Name

Ball

Interface Group

Page

AV

P31

Power

51

DD

BA0

AN31

AM31

AL21

AP23

AM22

AN23

D01

SDRAM

46

BA1

BankSel0

BankSel1

SDRAM

PCI

BankSel2

BankSel3

[BE0]PCIC0

[BE1]PCIC1

[BE2]PCIC2

[BE3]PCIC3

BusReq

B06

43

B10

C15

H03

External Master Peripheral Bus

SDRAM

49

46

CAS

AN22

AP21

AN21

AB34

AB33

AA31

AC34

AA34

W32

ClkEn0

SDRAM

46

ClkEn1

[DMAAck0]GPIO0_13

[DMAAck1]GPIO0_14

[DMAAck2]GPIO0_15

External Slave Peripheral Bus

47

[DMAAck3]GPIO0_16[PerCS5]

[DMAReq0]GPIO0_09

[DMAReq1]GPIO0_10

External Slave Peripheral Bus

47

[DMAReq2]GPIO0_11

AA33

AA32

AN20

AN15

AP12

AN09

AM20

AP24

AN24

AM24

AN25

AP26

AM25

AN26

AL25

C21

[DMAReq3]GPIO0_12[PerCS4]

DQM0

DQM1

DQM2

DQM3

DQMCB

ECC0

SDRAM

46

ECC1

ECC2

ECC3

SDRAM

Ethernet

46

44

ECC4

ECC5

ECC6

ECC7

EMC0MDClk

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Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 2 of 17)

Signal Name

Ball

B21

D21

A24

B23

C22

A23

D21

A22

D21

A22

B30

C29

B30

C29

A28

C27

B28

D27

AF34

AE32

AF33

AE31

H02

J03

Interface Group

Page

44

EMC0MDIO

Ethernet

[EMC0Sync]EMC0TxEn[EMC0Tx0En]

EMC0TxD0[EMC0Tx0D0][EMC0Tx0D]

EMC0TxD1[EMC0Tx0D1][EMC0Tx1D]

EMC0TxD2[EMC0Tx1D0][EMC0Tx2D]

EMC0TxD3[EMC0Tx1D1][EMC0Tx3D]

EMC0TxEn[EMC0Tx0En][EMC0Sync]

EMC0TxErr[EMC0Tx1En]

44

Ethernet

44

Ethernet

44

[EMC0Tx0En]EMC0TxEn[EMC0Sync]

[EMC0Tx1En]EMC0TxErr

Ethernet

44

[EMC1TxEn][EMC1Tx2En]GPIO1_12[HDLCMPTxEn6]

[EMC1TxErr][EMC1Tx3En]GPIO1_11[HDLCMPTxData6]

[EMC1Tx2En][EMC1TxEn]GPIO1_12[HDLCMPTxEn6]

[EMC1Tx3En][EMC1TxErr]GPIO1_11[HDLCMPTxData6]

[EMC1TxD0][EMC1Tx2D0]GPIO1_04[HDLCMPRxData4]

[EMC1TxD1][EMC1Tx2D1]GPIO1_05[HDLCMPTxClk5]

[EMC1TxD2][EMC1Tx3D0]GPIO1_06[HDLCMPTxData5]

[EMC1TxD3][EMC1Tx3D1]GPIO1_07[HDLCMPTxEn5]

[EOT0/TC0]GPIO0_24

Ethernet

44

Ethernet

44

47

[EOT1/TC1]GPIO0_25

External Slave Peripheral Bus

[EOT2/TC2]GPIO0_26

[EOT3/TC3]GPIO0_27[PerCS7]

ExtAck

External Master Peripheral Bus

49

ExtReq

ExtReset

K03

16

DS2011

AMCC Proprietary

Revision 1.02 – November 16, 2007

NPe405H – PowerNP NPe405H Embedded Processor

Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 3 of 17)

Signal Name

Ball

A01

Interface Group

Page

GND

A02

A06

A10

A15

A20

A25

A29

A33

A34

B01

B02

B33

B34

C03

C32

D04

Power

D12

Note: Balls N13-N22, P13-P22, R13-R22, T13-

T22, U13-U22, V13-V22, W13-W22, Y13-

Y22, AA13-AA22, and AB13-AB22 are

also thermal balls.

D17

51

D18

D23

D31

F01

F34

K01

K34

M04

M31

N13–N22

P13–P22

R01

R13–R22

R34

T13–T22

U04

U13–U22

U31

AMCC Proprietary

DS2011

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Revision 1.02 – November 16, 2007

NPe405H – PowerNP NPe405H Embedded Processor

Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 4 of 17)

Signal Name

Ball

V04

Interface Group

Page

GND

[Gnt]PCIReq0

V13–V22

V31

W13–W22

Y13–Y22

Y01

Y34

AA13–AA22

AB13–AB22

AC04

AC31

AE01

AE34

AJ01

AJ34

AL04

AL12

AL17

Power

Note: Balls N13-N22, P13-P22, R13-R22, T13-

T22, U13-U22, V13-V22, W13-W22, Y13-Y22,

AA13-AA22, and AB13-AB22 are also thermal

balls.

AL18

51

AL23

AL31

AM03

AM17

AM32

AN01

AN02

AN33

AN34

AP01

AP02

AP06

AP10

AP15

AP20

AP25

AP29

AP33

AP34

A19

PCI

43

18

DS2011

AMCC Proprietary

Revision 1.02 – November 16, 2007

NPe405H – PowerNP NPe405H Embedded Processor

Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 5 of 17)

Signal Name

Ball

U34

Interface Group

Page

GPIO0_00

GPIO0_01[TS1E]

GPIO0_02[TS2E]

GPIO0_03[TS1O]

GPIO0_04[TS2O]

GPIO0_05[TS3]

U33

V33

V34

W34

W33

GPIO0_06[TS4]

V32

GPIO0_07[TS5]

Y33

GPIO0_08[TS6]

Y32

GPIO0_09[DMAReq0]

GPIO0_10[DMAReq1]

GPIO0_11[DMAReq2]

AA34

W32

AA33

AA32

AB34

AB33

AA31

AC34

AB32

AC33

AD34

AC32

AD33

AD32

AE33

AF34

AE32

AF33

AE31

AG34

AF32

AG33

AH34

GPIO0_12[DMAReq3][PerCS4]

GPIO0_13[DMAAck0]

GPIO0_14[DMAAck1]

GPIO0_15[DMAAck2]

GPIO0_16[DMAAck3][PerCS5]

GPIO0_17[IRQ0]

System

51

GPIO0_18[IRQ1]

GPIO0_19[IRQ2]

GPIO0_20[IRQ3]

GPIO0_21[IRQ4]

GPIO0_22[IRQ5]

GPIO0_23[IRQ6][PerCS6]

GPIO0_24[EOT0/TC0]

GPIO0_25[EOT1/TC1]

GPIO0_26[EOT2/TC2]

GPIO0_27[EOT3/TC3][PerCS7]

GPIO0_28[PerCS1]

GPIO0_29[PerCS2]

GPIO0_30[PerCS3]

GPIO0_31[TrcClk]

AMCC Proprietary

DS2011

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Revision 1.02 – November 16, 2007

NPe405H – PowerNP NPe405H Embedded Processor

Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 6 of 17)

Signal Name

GPIO1_00[HDLCMPTxClk4][PHY1RxD0][PHY1Rx2D0]

GPIO1_01[HDLCMPTxData4][PHY1RxD1][PHY1Rx2D1]

GPIO1_02[HDLCMPTxEn4][PHY1RxD2][PHY1Rx3D0]

GPIO1_03[HDLCMPRxClk4][PHY1RxD3][PHY1Rx3D1]

GPIO1_04[HDLCMPRxData4][EMC1TxD0][EMC1Tx2D0]

GPIO1_05[HDLCMPTxClk5][EMC1TxD1][EMC1Tx2D1]

GPIO1_06[HDLCMPTxData5][EMC1TxD2][EMC1Tx3D0]

GPIO1_07[HDLCMPTxEn5][EMC1TxD3][EMC1Tx3D1]

GPIO1_08[HDLCMPRxClk5][PHY1RxErr][PHY1Rx2Er]

GPIO1_09[HDLCMPRxData5][PHY1RxDV][PHY1CrS3DV]

GPIO1_10[HDLCMPTxClk6][PHY1CrS][PHY1CrS2DV]

GPIO1_11[HDLCMPTxData6][EMC1TxErr][EMC1Tx3En]

GPIO1_12[HDLCMPTxEn6][EMC1TxEn][EMC1Tx2En]

GPIO1_13[HDLCMPRxClk6][PHY1RxClk]

GPIO1_14[HDLCMPRxData6][PHY1Col][PHY1Rx3Er]

GPIO1_15[HDLCMPTxClk7]

Ball

D25

A27

C26

B27

A28

C27

B28

D27

C28

B29

A30

C29

B30

A31

B32

D29

C30

A32

B31

C31

D33

C34

E32

F31

Interface Group

Page

System

51

GPIO1_16[HDLCMPTxData7]

GPIO1_17[HDLCMPTxEn7][PHY1TxClk]

GPIO1_18[HDLCMPRxClk7]

GPIO1_19[HDLCMPRxData7]

GPIO1_20[HDLCMPTxEn0][UART1_CTS]

GPIO1_21[HDLCMPTxEn1][UART1_DSR]

GPIO1_22[HDLCMPTxEn2][UART1_DCD]

GPIO1_23[HDLCMPTxEn3][UART1_RI]

GPIO1_24[HDLCEXTxEnA][UART1_RTS]

GPIO1_25[HDLCEXTxEnB][UART1_DTR]

GPIO1_26[UART0_CTS]

C33

D34

E33

F32

GPIO1_27[UART0_DSR]

GPIO1_28[UART0_DCD]

E34

F33

GPIO1_29[UART0_RI]x

GPIO1_30[UART0_RTS]

G32

H31

N33

AJ31

AK33

AL34

AM33

AL32

AK32

AM34

C33

D34

AL33

GPIO1_31[UART0_DTR]

Halt

System

51

44

HDLCEXRxClk

HDLC 32-Channel

HDLCEXRxDataA

HDLC 32-Channel

44

HDLCEXRxDataB

HDLCEXRxFS

HDLC 32-Channel

44

HDLCEXTxClk

HDLCEXTxDataA

HDLC 32-Channel

44

HDLCEXTxDataB

[HDLCEXTxEnA]GPIO1_24[UART1_RTS]

[HDLCEXTxEnB]GPIO1_25[UART1_DTR]

HDLCEXTxFS

HDLC 32-Channel

44

20

DS2011

AMCC Proprietary

Revision 1.02 – November 16, 2007

NPe405H – PowerNP NPe405H Embedded Processor

Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 7 of 17)

Signal Name

Ball

G33

H33

H34

N34

B27

C28

A31

B31

G34

J32

Interface Group

Page

HDLCMPRxClk0

HDLCMPRxClk1

HDLCMPRxClk2

HDLCMPRxClk3

HDLC 8-Port

44

[HDLCMPRxClk4]GPIO1_03[PHY1RxD3][PHY1Rx3D1]

[HDLCMPRxClk5]GPIO1_08[PHY1RxErr][PHY1Rx2Er]

[HDLCMPRxClk6]GPIO1_13[PHY1RxClk]

[HDLCMPRxClk7]GPIO1_18]

44

HDLCMPRxData0

HDLCMPRxData1

HDLCMPRxData2

K31

P32

A28

B29

B32

C31

P33

P34

R33

T33

D25

C27

A30

D29

T32

R32

U32

T34

A27

B28

C29

C30

D33

C34

E32

F31

C26

D27

B30

A32

H01

K04

J02

HDLCMPRxData3

[HDLCMPRxData4]GPIO1_04[EMC1TxD0][EMC1Tx2D0]

[HDLCMPRxData5]GPIO1_09[PHY1RxDV][PHY1CrS3DV]

[HDLCMPRxData6]GPIO1_14[PHY1Col][PHY1Rx3Er]

[HDLCMPRxData7]GPIO1_19

HDLCMPTxClk0

HDLCMPTxClk1

HDLCMPTxClk2

HDLCMPTxClk3

[HDLCMPTxClk4]GPIO1_00[PHY1RxD0][PHY1Rx2D0]

[HDLCMPTxClk5]GPIO1_05[EMC1TxD1][EMC1Tx2D1]

[HDLCMPTxClk6]GPIO1_10[PHY1CrS][PHY1CrS2DV]

[HDLCMPTxClk7]GPIO1_15

HDLCMPTxData0

HDLCMPTxData1

HDLCMPTxData2

HDLCMPTxData3

[HDLCMPTxData4]GPIO1_01[PHY1RxD1][PHY1Rx2D1]

[HDLCMPTxData5]GPIO1_06[EMC1TxD2][EMC1Tx3D0]

[HDLCMPTxData6]GPIO1_11[EMC1TxErr][EMC1Tx3En]

[HDLCMPTxData7]GPIO1_16

[HDLCMPTxEn0]GPIO1_20[UART1_CTS]

[HDLCMPTxEn1[GPIO1_21[UART1_DSR]

[HDLCMPTxEn2]GPIO1_22[UART1_DCD]

[HDLCMPTxEn3]GPIO1_23[UART1_RI]

[HDLCMPTxEn4]GPIO1_02[PHYRx3D0]

[HDLCMPTxEn5]GPIO1_07[EMC0Tx3D1]

[HDLCMPTxEn6]GPIO1_12[EMC0Tx2En]

[HDLCMPTxEn7]GPIO1_17[PHY1TxClk]

HoldAck

HDLC 8-Port

44

HoldPri

External Master Peripheral Bus

Internal Peripheral Bus

49

HoldReq

IICSCL[IECSCL]

AK34

AJ32

IICSDA[IECSDA]

AMCC Proprietary

DS2011

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Revision 1.02 – November 16, 2007

NPe405H – PowerNP NPe405H Embedded Processor

Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 8 of 17)

Signal Name

Ball

Interface Group

Page

[IRQ0]GPIO0_17

[IRQ1]GPIO0_18

[IRQ2]GPIO0_19

[IRQ3]GPIO0_20

[IRQ4]GPIO0_21

[IRQ5]GPIO0_22

[IRQ6]GPIO0_23[PerCS6]

MemAddr00

AB32

AC33

AD34

AC32

AD33

AD32

AE33

AP27

AM26

AN27

AN28

AM28

AN29

AP30

AM29

AN30

AP31

AL29

AM30

AP32

AM27

AP28

Interrupts

50

MemAddr01

MemAddr02

MemAddr03

MemAddr04

MemAddr05

SDRAM

MemAddr06

46

Note: During a CAS cycle MemAddr00 is the

least significant bit (lsb) on this bus.

MemAddr07

MemAddr08

MemAddr09

MemAddr10

MemAddr11

MemAddr12

MemClkOut0

MemClkOut1

SDRAM

46

22

DS2011

AMCC Proprietary

Revision 1.02 – November 16, 2007

NPe405H – PowerNP NPe405H Embedded Processor

Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 9 of 17)

Signal Name

Ball

Interface Group

Page

MemData00

MemData01

MemData02

MemData03

MemData04

MemData05

MemData06

MemData07

MemData08

MemData09

MemData10

MemData11

MemData12

MemData13

MemData14

MemData15

MemData16

MemData17

MemData18

MemData19

MemData20

MemData21

MemData22

MemData23

MemData24

MemData25

MemData26

MemData27

MemData28

MemData29

MemData30

MemData31

AM18

AN19

AP19

AP18

AN18

AN17

AP16

AN16

AM15

AP14

AM16

AN14

AM14

AP13

AN13

AL14

AM13

AN12

AP11

AM12

AN11

AN10

AP09

AM10

AL10

AP08

AM09

AN08

AP07

AM08

AN07

AL08

46

SDRAM

Notes:

1. MemData00 is the most significant bit (msb).

2. MemData31 is the least significant bit (lsb)

AMCC Proprietary

DS2011

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Revision 1.02 – November 16, 2007

NPe405H – PowerNP NPe405H Embedded Processor

Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 10 of 17)

Signal Name

Ball

Interface Group

Page

OV

A11

DD

B05

B22

C08

C16

D05

D07

D09

D11

D24

D26

D28

D30

E03

E04

E31

F03

Power

51

G04

G31

J04

J31

L04

L31

L32

M32

M34

AD04

AD31

AF04

AF31

AH04

AH31

AK04

AK31

24

DS2011

AMCC Proprietary

Revision 1.02 – November 16, 2007

NPe405H – PowerNP NPe405H Embedded Processor

Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 11 of 17)

Signal Name

Ball

Interface Group

Page

OV

AL05

DD

AL07

AL09

AL11

AL24

AL26

AL27

AL28

AL30

AM06

AM11

AM19

AM23

AN32

AP17

Power

51

AMCC Proprietary

DS2011

25

Revision 1.02 – November 16, 2007

NPe405H – PowerNP NPe405H Embedded Processor

Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 12 of 17)

Signal Name

Ball

H04

G01

G02

G03

F02

F04

E01

D03

C01

C02

B03

A03

C04

A04

A05

C06

C11

C12

B12

A12

A13

B13

C14

B14

B15

B16

A16

C17

B17

C18

B18

A18

D01

B06

B10

C15

B11

A08

C10

B19

A17

D06

D10

C13

D14

A14

Interface Group

Page

PCIAD00

PCIAD01

PCIAD02

PCIAD03

PCIAD04

PCIAD05

PCIAD06

PCIAD07

PCIAD08

PCIAD09

PCIAD10

PCIAD11

PCIAD12

PCIAD13

PCIAD14

PCIAD15

PCIAD16

PCIAD17

PCIAD18

PCIAD19

PCIAD20

PCIAD21

PCIAD22

PCIAD23

PCIAD24

PCIAD25

PCIAD26

PCIAD27

PCIAD28

PCIAD29

PCIAD30

PCIAD31

PCIC0[BE0]

PCIC1[BE1]

PCIC2[BE2]

PCIC3[BE3]

PCIClk

PCI

43

Note: PCIAD31 is the most significant bit (msb) on

this bus.

PCI

43

PCI

43

PCIDevSel

PCIFrame

PCIGnt0[Req]

PCIGnt1

PCIGnt2

PCI

43

PCIGnt3

PCIGnt4

PCIGnt5

PCIIDSel

26

DS2011

AMCC Proprietary

Revision 1.02 – November 16, 2007

NPe405H – PowerNP NPe405H Embedded Processor

Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 13 of 17)

Signal Name

Ball

C05

B09

Interface Group

Page

43

PCIINT[PerWE]

PCIIRDY

PCI

43

PCIParity

B07

43

PCIPErr

A07

43

PCIReq0[Gnt]

PCIReq1

A19

D02

E02

PCIReq2

PCI

43

PCIReq3

B04

PCIReq4

C07

A09

PCIReq5

PCIReset

PCISErr

B20

PCI

43

D08

B08

PCIStop

PCITRDY

PerAddr00

PerAddr01

PerAddr02

PerAddr03

PerAddr04

PerAddr05

PerAddr06

PerAddr07

PerAddr08

PerAddr09

PerAddr10

PerAddr11

PerAddr12

PerAddr13

PerAddr14

PerAddr15

PerAddr16

PerAddr17

PerAddr18

PerAddr19

PerAddr20

PerAddr21

PerAddr22

PerAddr23

PerAddr24

PerAddr25

PerAddr26

PerAddr27

PerAddr28

PerAddr29

PerAddr30

PerAddr31

C09

AD02

AC03

AD01

AC02

AB03

AC01

AA04

AB02

AB01

AA03

AA02

W03

AA01

Y03

Y02

V03

External Slave Peripheral

47

W02

W01

V01

V02

U02

U01

T01

T02

U03

R02

R03

P01

T03

P02

P03

N01

AMCC Proprietary

DS2011

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Revision 1.02 – November 16, 2007

NPe405H – PowerNP NPe405H Embedded Processor

Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 14 of 17)

Signal Name

Ball

L03

Interface Group

External Slave Peripheral Bus

Page

47

PerBLast

PerClk

K02

47

PerCS0

M02

[PerCS1]GPIO0_28

[PerCS2]GPIO0_29

[PerCS3]GPIO0_30

AG34

AF32

AG33

AA32

AC34

AE33

AE31

AM07

AN06

AP05

AN05

AP04

AN03

AL06

AM05

AN04

AM04

AL03

AL02

AM01

AK03

AJ04

AM02

AK02

AJ03

AK01

AJ02

AH03

AG04

AH02

AG03

AG02

AF03

AG01

AE04

AF02

AE03

AF01

AE02

J01

External Slave Peripheral Bus

47

[PerCS4]GPIO0_12[DMAReq3]

[PerCS5]GPIO0_16[DMAAck3]

[PerCS6]GPIO0_23[IRQ6]

[PerCS7]GPIO0_27[EOT3/TC3]

PerData00

PerData01

PerData02

PerData03

PerData04

PerData05

PerData06

PerData07

PerData08

PerData09

PerData10

PerData11

PerData12

PerData13

PerData14

External Slave Peripheral Bus

PerData15

47

Note: PerData00 is the most significant bit

(msb) on this bus.

PerData16

PerData17

PerData18

PerData19

PerData20

PerData21

PerData22

PerData23

PerData24

PerData25

PerData26

PerData27

PerData28

PerData29

PerData30

PerData31

PerErr

External Slave Peripheral Bus

49

47

PerOE

L01

28

DS2011

AMCC Proprietary

Revision 1.02 – November 16, 2007

NPe405H – PowerNP NPe405H Embedded Processor

Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 15 of 17)

Signal Name

Ball

AP03

AL01

AH01

AD03

M03

L02

Interface Group

Page

PerPar0

PerPar1

External Slave Peripheral Bus

47

PerPar2

PerPar3

PerR/W

External Slave Peripheral Bus

47

PerReady

PerWBE0

N02

P04

M01

N03

C05

C20

A21

C23

C19

B24

B26

C25

A26

B25

C23

C24

C20

C19

B32

A30

B29

A31

B29

D25

A27

C26

B27

C28

B32

A32

AP22

B19

PerWBE1

External Slave Peripheral Bus

47

PerWBE2

PerWBE3

[PerWE]PCIINT

PHY0Col[PHY0Rx1Er]

PHY0CrS[PHY0CrS0DV]

[PHY0CrS0DV]PHY0CrS

External Slave Peripheral Bus

Ethernet

43

44

Ethernet

44

[PHY0CrS1DV]PHY0RxDV

[PHY0RefClk]PHY0TxClk

Ethernet

44

PHY0RxClk

PHY0RxD0[PHY0Rx0D0][PHY0Rx0D]

PHY0RxD1[PHY0Rx0D1][PHY0Rx1D]

PHY0RxD2[PHY0Rx1D0][PHY0Rx2D]

PHY0RxD3[PHY0Rx1D1][PHY0Rx3D]

PHY0RxDV[PHY0CrS1DV]

Ethernet

44

Ethernet

44

PHY0RxErr[PHY0Rx0Er]

[PHY0Rx0Er]PHY0RxErr

Ethernet

44

[PHY0Rx1Er]PHY0Col

PHY0TxClk[PHY0RefClk]

Ethernet

44

[PHY1Col][PHY1Rx3Er]GPIO1_14[HDLCMPRxData6]

[PHY1CrS][PHY1CrS2DV]GPIO1_10[HDLCMPTxClk6]

[PHY1CrS2DV][PHY1CrS]GPIO1_10[HDLCMPTxClk6]

[PHY1CrS3DV][PHY1RxDV]GPIO1_09[HDLCMPRxData5]

[PHY1RxClk]GPIO1_13[HDLCMPRxClk6]

[PHY1RxDV][PHY1CrS3DV]GPIO1_09[HDLCMPRxData5]

[PHY1RxD0][PHY1Rx2D0]GPIO1_00[HDLCMPTxClk4]

[PHY1RxD1][PHY1Rx2D1]GPIO1_01[HDLCMPTxData4]

[PHY1RxD2][PHY1Rx3D0]GPIO1_02[HDLCMPTxEn4]

[PHY1RxD3][PHY1Rx3D1]GPIO1_03[HDLCMPRxClk4]

[PHY1RxErr][PHY1Rx2Er]GPIO1_08[HDLCMPRxClk5]

[PHY1Rx2Er][PHY1RxErr]GPIO1_08[HDLCMPRxClk5]

[PHY1Rx3Er][PHY1Col]GPIO1_14[HDLCMPRxData6]

[PHY1TxClk]GPIO1_17[HDLCMPTxEn7]

RAS

Ethernet

44

Ethernet

44

Ethernet

SDRAM

PCI

44

46

43

51

[Req]PCIGnt0

Reserved

Other

SysClk

L33

K32

J33

System

SysErr

SysReset

AMCC Proprietary

DS2011

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Revision 1.02 – November 16, 2007

NPe405H – PowerNP NPe405H Embedded Processor

Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 16 of 17)

Signal Name

Ball

K33

Interface Group

Page

TCK

JTAG

50

[TC0/EOT0]GPIO0_24

[TC1/EOT1]GPIO0_25

[TC2/EOT2]GPIO0_26

[TC3/EOT3]GPIO0_27

TDI

AF34

AE32

AF33

AE31

N32

J34

External Slave Peripheral Bus

47

JTAG

System

JTAG

Trace

JTAG

50

51

50

51

50

TDO

TestEn

M33

D32

H32

AH34

L34

TmrClk

TMS

[TrcClk]GPIO0_31

TRST

[TS1E]GPIO0_01

[TS2E]GPIO0_02

[TS1O]GPIO0_03

[TS2O]GPIO0_04

[TS3]GPIO0_05

[TS4]GPIO0_06

[TS5]GPIO0_07

[TS6]GPIO0_08

[UART0_CTS]GPIO1_26

[UART0_DCD]GPIO1_28

[UART0_DSR]GPIO1_27

[UART0_DTR]GPIO1_31

[UART0_RI]GPIO1_29

[UART0_RTS]GPIO1_30

UART0_Rx

U33

V33

Trace

51

V34

W34

W33

V32

Trace

51

Y33

Y32

E33

Internal Peripheral

49

E34

F32

H31

F33

G32

AG32

AH33

D33

E32

UART0_Tx

[UART1_CTS]GPIO1_20[HDLCMPTxEn0]

[UART1_DCD]GPIO1_22[HDLCMPTxEn2]

[UART1_DSR]GPIO1_21[HDLCMPTxEn1]

[UART1_DTR]GPIO1_25[HDLCMPTxEnB]

[UART1_RI]GPIO1_23[HDLCMPTxEn3]

[UART1_RTS]GPIO1_24[HDLCMPTxEnA]

UART1_Rx

C34

D34

F31

C33

AH32

AJ33

AG31

UART1_Tx

UARTSerClk

30

DS2011

AMCC Proprietary

Revision 1.02 – November 16, 2007

NPe405H – PowerNP NPe405H Embedded Processor

Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 17 of 17)

Signal Name

Ball

Interface Group

Page

V

D13

DD

D15

D16

D19

D20

D22

N04

N31

R04

R31

T04

T31

Power

51

W04

W31

Y04

Y31

AB04

AB31

AL13

AL15

AL16

AL19

AL20

AL22

WE

AM21

SDRAM

46

AMCC Proprietary

DS2011

31

Revision 1.02 – November 16, 2007

NPe405H – PowerNP NPe405H Embedded Processor

Data Sheet

SIGNALS LISTED BY BALL ASSIGNMENT

Table 4. Signals Listed by Ball Assignment (Sheet 1 of 9)

Signal names followed by an asterisk (*) are multiplexed. Look up the name shown in “Signals Listed Alphabetically” on page 15

for an indication of all signals on the pin.

Ball

A01

A02

A03

A04

Signal Name

Ball

B01

B02

B03

B04

Signal Name

Ball

C01

C02

C03

C04

Signal Name

PCIAD08

Ball

D01

D02

D03

D04

Signal Name

PCIC0[BE0]

GND

PCIAD09

GND

PCIReq1

PCIAD07

GND

PCIAD11

PCIAD13

PCIAD10

PCIReq3

PCIAD12

OV

DD

OV

DD

A05

A06

A07

PCIAD14

GND

B05

B06

B07

C05

C06

C07

PCIINT[PerWE]

PCIAD15

D05

D06

D07

PCIC1[BE1]

PCIParity

PCIGnt2

OV

DD

PCIPErr

PCIReq4

OV

DD

A08

PCIDevSel

B08

PCIStop

C08

D08

PCISErr

OV

DD

A09

A10

A11

A12

A13

A14

A15

PCIReq5

GND

B09

B10

B11

B12

B13

B14

B15

PCIIRDY

PCIC2[BE2]

PCIClk

C09

C10

C11

C12

C13

C14

C15

PCITRDY

PCIFrame

PCIAD16

PCIAD17

PCIGnt4

D09

D10

D11

D12

D13

D14

D15

PCIGnt3

OV

DD

OV

DD

PCIAD19

PCIAD20

PCIIDSel

GND

PCIAD18

PCIAD21

PCIAD23

PCIAD24

GND

V

DD

PCIAD22

PCIC3[BE3]

PCIGnt5

V

DD

OV

DD

V

A16

PCIAD26

B16

PCIAD25

C16

D16

DD

A17

A18

PCIGnt1

PCIAD31

B17

B18

PCIAD28

PCIAD30

C17

C18

PCIAD27

PCIAD29

D17

D18

GND

V

A19

PCIReq0 *

B19

PCIGnt0[Req]

C19

PHY0TxClk *

D19

DD

V

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

GND

B20

B21

B22

B23

B24

B25

B26

B27

B28

B29

B30

PCIReset

C20

C21

C22

C23

C24

C25

C26

C27

C28

C29

C30

PHY0Col *

D20

D21

D22

D23

D24

D25

D26

D27

D28

D29

D30

DD

PHY0CrS *

EMC0TxErr *

EMC0TxD3 *

EMC0TxD0 *

GND

EMC0MDIO

EMC0MDClk

EMC0TxD2 *

PHY0RxDV *

PHY0RxErr *

EMC0TxEn *

OV

DD

V

DD

EMC0TxD1 *

PHY0RxClk

GND

OV

DD

GPIO1_00 *

PHY0RxD3

*

PHY0RxD1

GPIO1_02 *

GPIO1_05 *

GPIO1_08 *

GPIO1_11 *

GPIO1_16 *

*

OV

DD

PHY0RxD2 *

GPIO1_01 *

GPIO1_04 *

GND

PHY0RxD0 *

GPIO1_03 *

GPIO1_06 *

GPIO1_09 *

GPIO1_12 *

GPIO1_07 *

OV

DD

GPIO1_15 *

OV

DD

GPIO1_10 *

A31

A32

A33

A34

GPIO1_13 *

GPIO1_17 *

GND

B31

B32

B33

B34

GPIO1_18 *

GPIO1_14 *]

GND

C31

C32

C33

C34

GPIO1_19 *

GND

D31

D32

D33

D34

GND

TmrClk

GPIO1_24 *

GPIO1_21 *

GPIO1_20 *

GPIO1_25 *

GND

32

DS2011

AMCC Proprietary

Revision 1.02 – November 16, 2007

NPe405H – PowerNP NPe405H Embedded Processor

Data Sheet

Table 4. Signals Listed by Ball Assignment (Sheet 2 of 9)

Signal names followed by an asterisk (*) are multiplexed. Look up the name shown in “Signals Listed Alphabetically” on page 15

for an indication of all signals on the pin.

Ball

E01

E02

Signal Name

PCIAD06

Ball

F01

F02

Signal Name

Ball

G01

G02

Signal Name

PCIAD01

Ball

H01

H02

Signal Name

HoldAck

GND

PCIReq2

PCIAD04

PCIAD02

PCIAD03

ExtAck

OV

DD

OV

DD

E03

E04

F03

F04

G03

G04

H03

H04

BusReq

OV

DD

OV

DD

PCIAD05

PCIAD00

E05

E06

E07

E08

E09

E10

E11

E12

E13

E14

E15

E16

E17

E18

E19

E20

E21

E22

E23

E24

E25

E26

E27

E28

E29

E30

No ball

F05

F06

F07

F08

F09

F10

A11

F12

F13

F14

F15

F16

F17

F18

F19

F20

F21

F22

F23

F24

F25

F26

F27

F28

F29

F30

No ball

G05

G06

G07

G08

G09

G10

G11

G12

G13

G14

G15

G16

G17

G18

G19

G20

G21

G22

G23

G24

G25

G26

G27

G28

G29

G30

No ball

H05

H06

H07

H08

H09

H10

H11

H12

H13

H14

H15

H16

H17

H18

H19

H20

H21

H22

H23

H24

H25

H26

H27

H28

H29

H30

No ball

OV

DD

OV

DD

E31

F31

GPIO1_23 *

G31

H31

GPIO1_31 *

E32

E33

E34

GPIO1_22 *

GPIO1_26 *

GPIO1_28 *]

F32

F33

F34

GPIO1_27 *

GPIO1_29 *

GND

G32

G33

G34

GPIO1_30 *

H32

H33

H34

TMS

HDLCMPRxClk0

HDLCMPRxData0

HDLCMPRxClk1

HDLCMPRxClk2

AMCC Proprietary

DS2011

33

Revision 1.02 – November 16, 2007

NPe405H – PowerNP NPe405H Embedded Processor

Data Sheet

Table 4. Signals Listed by Ball Assignment (Sheet 3 of 9)

Signal names followed by an asterisk (*) are multiplexed. Look up the name shown in “Signals Listed Alphabetically” on page 15

for an indication of all signals on the pin.

Ball

J01

J02

J03

Signal Name

PerErr

Ball

K01

K02

K03

Signal Name

Ball

L01

L02

L03

Signal Name

PerOE

Ball

Signal Name

GND

M01 PerWBE2

M02 PerCS0

M03 PerR/W

HoldReq

ExtReq

PerClk

PerReady

PerBLast

ExtReset

OV

DD

OV

DD

J04

K04

HoldPri

L04

M04 GND

J05

J06

J07

J08

J09

J10

J11

J12

J13

J14

J15

J16

J17

J18

J19

J20

J21

J22

J23

J24

J25

J26

J27

J28

J29

J30

No ball

K05

K06

K07

K08

K09

K10

K11

K12

K13

K14

K15

K16

K17

K18

K19

K20

K21

K22

K23

K24

K25

K26

K27

K28

K29

K30

No ball

L05

L06

L07

L08

L09

L10

L11

L12

L13

L14

L15

L16

L17

L18

L19

L20

L21

L22

L23

L24

L25

L26

L27

L28

L29

L30

No ball

M05 No ball

M06 No ball

M07 No ball

M08 No ball

M09 No ball

M10 No ball

M11 No ball

M12 No ball

M13 No ball

M14 No ball

M15 No ball

M16 No ball

M17 No ball

M18 No ball

M19 No ball

M20 No ball

M21 No ball

M22 No ball

M23 No ball

M24 No ball

M25 No ball

M26 No ball

M27 No ball

M28 No ball

M29 No ball

M30 No ball

OV

DD

OV

DD

J31

K31

HDLCMPRxData2

L31

M31 GND

OV

DD

OV

DD

J32

J33

J34

HDLCMPRxData1

SysReset

K32

K33

K34

SysErr

TCK

L32

L33

L34

M32

M33 TestEn

OV

SysClk

TRST

TDO

GND

M34

DD

34

DS2011

AMCC Proprietary

Revision 1.02 – November 16, 2007

NPe405H – PowerNP NPe405H Embedded Processor

Data Sheet

Table 4. Signals Listed by Ball Assignment (Sheet 4 of 9)

Signal names followed by an asterisk (*) are multiplexed. Look up the name shown in “Signals Listed Alphabetically” on page 15

for an indication of all signals on the pin.

Ball

N01

N02

N03

Signal Name

PerAddr31

Ball

P01

P02

P03

Signal Name

PerAddr27

Ball

R01

R02

R03

Signal Name

Ball

T01

T02

T03

Signal Name

PerAddr22

GND

PerWBE0

PerWBE3

PerAddr29

PerAddr30

PerAddr25

PerAddr26

PerAddr23

PerAddr28

V

N04

P04

PerWBE1

R04

T04

DD

N05

N06

N07

N08

N09

N10

N11

N12

N13

N14

N15

N16

N17

N18

N19

N20

N21

N22

N23

N24

N25

N26

N27

N28

N29

N30

No ball

GND

P05

P06

P07

P08

P09

P10

P11

P12

P13

P14

P15

P16

P17

P18

P19

P20

P21

P22

P23

P24

P25

P26

P27

P28

P29

P30

No ball

GND

R05

R06

R07

R08

R09

R10

R11

R12

R13

R14

R15

R16

R17

R18

R19

R20

R21

R22

R23

R24

R25

R26

R27

R28

R29

R30

No ball

GND

T05

T06

T07

T08

T09

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

T21

T22

T23

T24

T25

T26

T27

T28

T29

T30

No ball

GND

No ball

V

AV

DD

V

N31

P31

R31

T31

DD

N32

N33

N34

TDI

P32

P33

P34

HDLCMPRxData3

HDLCMPTxClk0

HDLCMPTxClk1

R32

R33

R34

HDLCMPTxData1

HDLCMPTxClk2

GND

T32

T33

T34

HDLCMPTxData0

HDLCMPTxClk3

HDLCMPTxData3

Halt

HDLCMPRxClk3

AMCC Proprietary

DS2011

35

Revision 1.02 – November 16, 2007

NPe405H – PowerNP NPe405H Embedded Processor

Data Sheet

Table 4. Signals Listed by Ball Assignment (Sheet 5 of 9)

Signal names followed by an asterisk (*) are multiplexed. Look up the name shown in “Signals Listed Alphabetically” on page 15

for an indication of all signals on the pin.

Ball

U01

U02

U03

Signal Name

PerAddr21

Ball

V01

V02

V03

Signal Name

PerAddr18

Ball

Signal Name

Ball

Y01

Y02

Y03

Signal Name

W01 PerAddr17

W02 PerAddr16

W03 PerAddr11

GND

PerAddr20

PerAddr24

PerAddr19

PerAddr15

PerAddr14

PerAddr13

V

U04

GND

V04

GND

W04

Y04

DD

U05

U06

U07

U08

U09

U10

U11

U12

U13

U14

U15

U16

U17

U18

U19

U20

U21

U22

U23

U24

U25

U26

U27

U28

U29

U30

No ball

GND

V05

V06

V07

V08

V09

V10

V11

V12

V13

V14

V15

V16

V17

V18

V19

V20

V21

V22

V23

V24

V25

V26

V27

V28

V29

V30

No ball

GND

W05 No ball

W06 No ball

W07 No ball

W08 No ball

W09 No ball

W10 No ball

W11 No ball

W12 No ball

W13 GND

W14 GND

W15 GND

W16 GND

W17 GND

W18 GND

W19 GND

W20 GND

W21 GND

W22 GND

W23 No ball

W24 No ball

W25 No ball

W26 No ball

W27 No ball

W28 No ball

W29 No ball

W30 No ball

Y05

Y06

Y07

Y08

Y09

Y10

Y11

Y12

Y13

Y14

Y15

Y16

Y17

Y18

Y19

Y20

Y21

Y22

Y23

Y24

Y25

Y26

Y27

Y28

Y29

Y30

No ball

GND

No ball

V

U31

GND

V31

GND

W31

Y31

DD

U32

U33

U34

HDLCMPTxData2

GPIO0_01 *

V32

V33

V34

GPIO0_06 *

GPIO0_02 *

GPIO0_03 *

W32 GPIO0_10 *

W33 GPIO0_05 *

W34 GPIO0_04 *

Y32

Y33

Y34

GPIO0_08 *

GPIO0_07 *

GND

GPIO0_00

36

DS2011

AMCC Proprietary

Revision 1.02 – November 16, 2007

NPe405H – PowerNP NPe405H Embedded Processor

Data Sheet

Table 4. Signals Listed by Ball Assignment (Sheet 6 of 9)

Signal names followed by an asterisk (*) are multiplexed. Look up the name shown in “Signals Listed Alphabetically” on page 15

for an indication of all signals on the pin.

Ball

Signal Name

Ball

Signal Name

Ball

Signal Name

Ball

Signal Name

AA01 PerAddr12

AA02 PerAddr10

AA03 PerAddr09

AB01 PerAddr08

AB02 PerAddr07

AB03 PerAddr04

AC01 PerAddr05

AC02 PerAddr03

AC03 PerAddr01

AD01 PerAddr02

AD02 PerAddr00

AD03 PerPar3

V

OV

DD

AA04 PerAddr06

AB04

AC04 GND

AD04

DD

AA05 No ball

AA06 No ball

AA07 No ball

AA08 No ball

AA09 No ball

AA10 No ball

AA11 No ball

AA12 No ball

AA13 GND

AA14 GND

AA15 GND

AA16 GND

AA17 GND

AA18 GND

AA19 GND

AA20 GND

AA21 GND

AA22 GND

AA23 No ball

AA24 No ball

AA25 No ball

AA26 No ball

AA27 No ball

AA28 No ball

AA29 No ball

AA30 No ball

AB05 No ball

AB06 No ball

AB07 No ball

AB08 No ball

AB09 No ball

AB10 No ball

AB11 No ball

AB12 No ball

AB13 GND

AB14 GND

AB15 GND

AB16 GND

AB17 GND

AB18 GND

AB19 GND

AB20 GND

AB21 GND

AB22 GND

AB23 No ball

AB24 No ball

AB25 No ball

AB26 No ball

AB27 No ball

AB28 No ball

AB29 No ball

AB30 No ball

AC05 No ball

AC06 No ball

AC07 No ball

AC08 No ball

AC09 No ball

AC10 No ball

AC11 No ball

AC12 No ball

AC13 No ball

AC14 No ball

AC15 No ball

AC16 No ball

AC17 No ball

AC18 No ball

AC19 No ball

AC20 No ball

AC21 No ball

AC22 No ball

AC23 No ball

AC24 No ball

AC25 No ball

AC26 No ball

AC27 No ball

AC28 No ball

AC29 No ball

AC30 No ball

AD05 No ball

AD06 No ball

AD07 No ball

AD08 No ball

AD09 No ball

AD10 No ball

AD11 No ball

AD12 No ball

AD13 No ball

AD14 No ball

AD15 No ball

AD16 No ball

AD17 No ball

AD18 No ball

AD19 No ball

AD20 No ball

AD21 No ball

AD22 No ball

AD23 No ball

AD24 No ball

AD25 No ball

AD26 No ball

AD27 No ball

AD28 No ball

AD29 No ball

AD30 No ball

V

OV

DD

AA31 GPIO0_15 *

AB31

AC31 GND

AD31

DD

AA32 GPIO0_12 *

AA33 GPIO0_11 *

AA34 GPIO0_09 *

AB32 GPIO0_17 *

AB33 GPIO0_14 *

AB34 GPIO0_13 *

AC32 GPIO0_20 *

AC33 GPIO0_18 *

AC34 GPIO0_16 *

AD32 GPIO0_22 *

AD33 GPIO0_21 *

AD34 GPIO0_19 *

AMCC Proprietary

DS2011

37

Revision 1.02 – November 16, 2007

NPe405H – PowerNP NPe405H Embedded Processor

Data Sheet

Table 4. Signals Listed by Ball Assignment (Sheet 7 of 9)

Signal names followed by an asterisk (*) are multiplexed. Look up the name shown in “Signals Listed Alphabetically” on page 15

for an indication of all signals on the pin.

Ball

Signal Name

Ball

Signal Name

Ball

Signal Name

Ball

Signal Name

AE01 GND

AF01 PerData30

AF02 PerData28

AF03 PerData25

AG01 PerData26

AG02 PerData24

AG03 PerData23

AH01 PerPar2

AE02 PerData31

AE03 PerData29

AH02 PerData22

AH03 PerData20

OV

DD

AE04 PerData27

AF04

AG04 PerData21

AH04

DD

AE05 No ball

AE06 No ball

AE07 No ball

AE08 No ball

AE09 No ball

AE10 No ball

AE11 No ball

AE12 No ball

AE13 No ball

AE14 No ball

AE15 No ball

AE16 No ball

AE17 No ball

AE18 No ball

AE19 No ball

AE20 No ball

AE21 No ball

AE22 No ball

AE23 No ball

AE24 No ball

AE25 No ball

AE26 No ball

AE27 No ball

AE28 No ball

AE29 No ball

AE30 No ball

AF05 No ball

AF06 No ball

AF07 No ball

AF08 No ball

AF09 No ball

AF10 No ball

AF11 No ball

AF12 No ball

AF13 No ball

AF14 No ball

AF15 No ball

AF16 No ball

AF17 No ball

AF18 No ball

AF19 No ball

AF20 No ball

AF21 No ball

AF22 No ball

AF23 No ball

AF24 No ball

AF25 No ball

AF26 No ball

AF27 No ball

AF28 No ball

AF29 No ball

AF30 No ball

AG05 No ball

AG06 No ball

AG07 No ball

AG08 No ball

AG09 No ball

AG10 No ball

AG11 No ball

AG12 No ball

AG13 No ball

AG14 No ball

AG15 No ball

AG16 No ball

AG17 No ball

AG18 No ball

AG19 No ball

AG20 No ball

AG21 No ball

AG22 No ball

AG23 No ball

AG24 No ball

AG25 No ball

AG26 No ball

AG27 No ball

AG28 No ball

AG29 No ball

AG30 No ball

AH05 No ball

AH06 No ball

AH07 No ball

AH08 No ball

AH09 No ball

AH10 No ball

AH11 No ball

AH12 No ball

AH13 No ball

AH14 No ball

AH15 No ball

AH16 No ball

AH17 No ball

AH18 No ball

AH19 No ball

AH20 No ball

AH21 No ball

AH22 No ball

AH23 No ball

AH24 No ball

AH25 No ball

AH26 No ball

AH27 No ball

AH28 No ball

AH29 No ball

AH30 No ball

OV

DD

AE31 GPIO0_27 *

AF31

AG31 UARTSerClk

AH31

DD

AE32 GPIO0_25 *

AE33 GPIO0_23 *

AE34 GND

AF32 GPIO0_29 *

AF33 GPIO0_26 *

AF34 GPIO0_24 *

AG32 UART0_Rx

AG33 GPIO0_30 *

AG34 GPIO0_28 *

AH32 UART1_Rx

AH33 UART0_Tx

AH34 GPIO0_31 *

38

DS2011

AMCC Proprietary

Revision 1.02 – November 16, 2007

NPe405H – PowerNP NPe405H Embedded Processor

Data Sheet

Table 4. Signals Listed by Ball Assignment (Sheet 8 of 9)

Signal names followed by an asterisk (*) are multiplexed. Look up the name shown in “Signals Listed Alphabetically” on page 15

for an indication of all signals on the pin.

Ball

Signal Name

Ball

Signal Name

Ball

Signal Name

Ball

Signal Name

AJ01 GND

AK01 PerData18

AK02 PerData16

AK03 PerData13

AL01 PerPar1

AM01 PerData12

AM02 PerData15

AM03 GND

AJ02 PerData19

AJ03 PerData17

AL02 PerData11

AL03 PerData10

OV

AJ04 PerData14

AJ05 No ball

AJ06 No ball

AK04

AL04 GND

AM04 PerData09

AM05 PerData07

DD

OV

AK05 No ball

AK06 No ball

AL05

AL06 PerData06

OV

DD

OV

AM06

DD

AJ07 No ball

AJ08 No ball

AJ09 No ball

AJ10 No ball

AJ11 No ball

AJ12 No ball

AJ13 No ball

AJ14 No ball

AJ15 No ball

AK07 No ball

AK08 No ball

AK09 No ball

AK10 No ball

AK11 No ball

AK12 No ball

AK13 No ball

AK14 No ball

AK15 No ball

AL07

AL08 MemData31

OV

AM07 PerData00

AM08 MemData29

AM09 MemData26

AM10 MemData23

DD

AL09

AL10 MemData24

OV

DD

OV

AL11

AL12 GND

AM11

DD

AM12 MemData19

AM13 MemData16

AM14 MemData12

AM15 MemData08

V

AL13

AL14 MemData15

DD

V

AL15

AL16

DD

AJ16 No ball

AK16 No ball

AM16 MemData10

AJ17 No ball

AJ18 No ball

AK17 No ball

AK18 No ball

AL17 GND

AL18 GND

AM17 GND

AM18 MemData00

V

OV

DD

AJ19 No ball

AK19 No ball

AL19

AL20

AM19

DD

AJ20 No ball

AJ21 No ball

AJ22 No ball

AK20 No ball

AK21 No ball

AK22 No ball

AM20 DQMCB

AM21 WE

AL21 BankSel0

V

AL22

AL23 GND

OV

AM22 BankSel2

DD

OV

AJ23 No ball

AK23 No ball

AM23

DD

AJ24 No ball

AJ25 No ball

AJ26 No ball

AK24 No ball

AK25 No ball

AK26 No ball

AL24

AL25 ECC7

AM24 ECC2

DD

AM25 ECC5

OV

AL26

AL27

AL28

AM26 MemAddr01

DD

AJ27 No ball

AK27 No ball

AM27 MemClkOut0

AJ28 No ball

AJ29 No ball

AJ30 No ball

AK28 No ball

AK29 No ball

AK30 No ball

AM28 MemAddr04

AM29 MemAddr07

AM30 MemAddr11

AL29 MemAddr10

OV

AL30

DD

OV

AJ31 HDLCEXRxClk

AK31

AL31 GND

AM31 BA1

DD

AJ32 IICSDA[IECSDA]

AJ33 UART1_Tx

AJ34 GND

AK32 HDLCEXTxDataA

AK33 HDLCEXRxDataA

AK34 IICSCL[IECSCL]

AL32 HDLCEXTxClk

AL33 HDLCEXTxFS

AL34 HDLCEXRxDataB

AM32 GND

AM33 HDLCEXRxFS

AM34 HDLCEXTxDataB

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Data Sheet

Table 4. Signals Listed by Ball Assignment (Sheet 9 of 9)

Signal names followed by an asterisk (*) are multiplexed. Look up the name shown in “Signals Listed Alphabetically” on page 15

for an indication of all signals on the pin.

Ball

Signal Name

Ball

Signal Name

Ball

Signal Name

Ball

Signal Name

AN01 GND

AN02 GND

AP01 GND

AP02 GND

AN03 PerData05

AN04 PerData08

AN05 PerData03

AN06 PerData01

AN07 MemData30

AN08 MemData27

AN09 DQM3

AP03 PerPar0

AP04 PerData04

AP05 PerData02

AP06 GND

AP07 MemData28

AP08 MemData25

AP09 MemData22

AP10 GND

AN10 MemData21

AN11 MemData20

AN12 MemData17

AN13 MemData14

AN14 MemData11

AN15 DQM1

AP11 MemData18

AP12 DQM2

AP13 MemData13

AP14 MemData09

AP15 GND

AN16 MemData07

AP16 MemData06

OV

AN17 MemData05

AP17

DD

AN18 MemData04

AN19 MemData01

AN20 DQM0

AP18 MemData03

AP19 MemData02

AP20 GND

AN21 ClkEn1

AP21 ClkEn0

AP22 RAS

AN22 CAS

AN23 BankSel3

AN24 ECC1

AP23 BankSel1

AP24 ECC0

AN25 ECC3

AP25 GND

AN26 ECC6

AP26 ECC4

AN27 MemAddr02

AN28 MemAddr03

AN29 MemAddr05

AN30 MemAddr08

AN31 BA0

AP27 MemAddr00

AP28 MemClkOut1

AP29 GND

AP30 MemAddr06

AP31 MemAddr09

OV

DD

AN32

AP32 MemAddr12

AN33 GND

AN34 GND

AP33 GND

AP34 GND

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SIGNAL DESCRIPTION

Data Sheet

The following table provides a summary of the number of package pins (balls) associated with each functional

interface group.

PIN SUMMARY

Table 5. Pin Summary

Group

No. of Pins

Nonmultiplexed Signals

Multiplexed Signals

Total Signal Pins

256

85

341

AV

DD

1

OV

DD

49

24

V

DD

Gnd

65

100

0

Gnd (and thermal)

Reserved

Total Pins

580

Multiplexed Pins

In the table “Signal Functional Description” on page 43, each external signal is listed along with a short description

of the signal function. The signals are grouped together according to their function. Some signals are multiplexed

on the same package pin (ball) so that the pin can be used for different functions. In most cases, the signal name is

shown in this table unaccompanied by multiplexed signal names that may be associated with it. In cases where

multiplexed signals are in the same functional group, the names appear as a default signal followed by secondary

signals in square brackets (for example, EMC0TxErr[EMC0Tx1En]). Active-low signals (for example, RAS) are

marked with an overline. Any signal that is not the primary (default) signal on a multiplexed pin is shown in square

brackets.

The active signal on a multiplexed pin is controlled by programming. It is expected that in any single application, a

particular pin will always be programmed to serve the same function. The flexibility of multiplexing allows a single

chip to offer a richer pin selection than would otherwise be possible.

Multipurpose Pins

In addition to multiplexing, pins may also be multipurpose. An example of multi-purpose use occurs when the EBC

peripheral controller address pins are used as outputs by the NPe405H to broadcast an address to external slave

devices when the NPe405H has control of the external bus. However, when an external master gains ownership of

the external bus, these same pins are used as inputs which are driven by the external master and received by the

EBC in the NPe405H. In this example, the pins are also bidirectional, serving as both inputs and outputs.

Initialization Strapping

One group of pins is used as strapped inputs during system reset. These pins function as strapped inputs only dur-

ing reset and are used for other functions during normal operation (see “Initialization” on page 68). Note that the

use of these pins for strapping is not considered multiplexing since the strapping function is not programmable.

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Data Sheet

Pull-up and Pull-down Resistors

Pull-up and pull-down resistors are used for strapping during reset and to retain unused or undriven inputs in an

appropriate state. The recommended pull-up value of 3kΩ to +3.3V (10kΩ to +5V can be used on 5V tolerant I/Os)

and pull-down value of 1kΩ to GND, applies only to individually terminated signals. To prevent possible damage to

the device, I/Os capable of becoming outputs must never be tied together and terminated through a common

resistor.

If your system-level test methodology permits, input-only signals can be connected together and terminated

through either a common resistor or directly to +3.3V or GND. When a resistor is used, its value must ensure that

the grouped I/Os reach a valid logic zero or logic one state when accounting for the total input current into the

NPe405H.

Unused I/Os

Strapping of some pins may be necessary when they are unused. Although the NPe405H requires only the pull-up

and pull-down terminations as specified in the “Signal Functional Description” on page 43, good design practice is

to terminate all unused inputs or to configure I/Os such that they always drive. If unused, the peripheral, SDRAM,

and PCI buses should be configured and terminated as follows:

•

Peripheral interface—PerAddr00:31, PerData00:31, and all of the control signals are driven by default. Ter-

minate PerReady high and PerError low.

SDRAM—Program SDRAM0_CFG[EMDULR]=1 and SDRAM0_CFG[DCE]=1. This causes the NPe405H

to actively drive all of the SDRAM address, data, and control signals.

PCI—Configure the PCI controller to park on the bus and actively drive PCIAD31:0, PCIC3:0[BE3:0], and

the remaining PCI control signals by doing the following:

- Strap the NPe405H to disable the internal PCI arbiter.

- Individually connect PCISErr, PCIPErr, PCITRDY, and PCIStop through 3.3kΩ resistors to +3.3V.

- Terminate PCIReq1:5 to +3.3V.

- Terminate PCIReq0[Gnt] to GND.

External Peripheral Bus Control Signals

All external peripheral bus control signals (PerCS0:7, PerR/W, PerWBE0:3, PerOE, PerWE, PerBLast, HoldAck,

ExtAck) are set to the high-impedance state when ExtReset=0. In addition, as detailed in the PowerNP NPe405H

Embedded Processor User’s Manual, the peripheral bus controller can be programmed via EBC0_CFG to float

some of these control signals between transactions or when an external master owns the peripheral bus. As a

result, a pull-up resistor should be added to those control signals where an undriven state may affect any devices

receiving that particular signal.

The following table lists all of the I/O signals provided by the NPe405H. Please see “Signals Listed Alphabetically”

on page 15 for the pin number to which each signal is assigned. In cases where a multiplexed signal (indicated by

the square brackets) is shown without the other signals that are assigned to that pin, you can see what the other

signals are by referring to the same table.

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Data Sheet

SIGNAL FUNCTIONAL DESCRIPTION

Table 6. Signal Functional Description (Sheet 1 of 9)

Notes:

1. Receiver input has hysteresis.

2. Must pull up. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.

3. Must pull down. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.

4. If not used, must pull up.

5. If not used, must pull down.

6. Strapping input during reset; pull up or pull down as required.

7. Pull-up may be required. See “External Peripheral Bus Control Signals” on page 42.

Signal Name

Description

I/O

Type

Notes

PCI Interface

5V tolerant

3.3V PCI

PCIAD0:31

PCI Address/Data bus. Multiplexed address and data bus

PCI bus command or Byte Enable

I/O

5V tolerant

3.3V PCI

PCIC3:0[BE3:0]

PCI Parity. Parity is even across PCIAD0:31 and

PCIC0:3[BE0:3]. PCIParity is valid one cycle after either an

address or data phase. The PCI device that drove PCIAD0:31

is responsible for driving PCIParity on the next PCI bus clock.

5V tolerant

3.3V PCI

PCIParity

I/O

Driven by the current PCI bus master to indicate the

beginning and duration of a PCI access.

5V tolerant

3.3V PCI

PCIFrame

PCIIRDY

I/O

4

Driven by the current PCI bus master. Assertion of PCIIRDY

indicates that the PCI initiator is ready to transfer data.

5V tolerant

3.3V PCI

The target of the current PCI transaction drives PCITRDY.

Assertion of PCITRDY indicates that the PCI target is ready to

transfer data.

5V tolerant

3.3V PCI

PCITRDY

PCIStop

I/O

4

The target of the current PCI transaction can assert PCIStop

to indicate to the requesting PCI master that it wants to end

the current transaction.

5V tolerant

3.3V PCI

Driven by the target of the current PCI transaction. A PCI

target asserts PCIDevSel when it has decoded an address

and command encoding and claims the transaction.

5V tolerant

3.3V PCI

PCIDevSel

Used during configuration cycles to select the PCI slave

interface for configuration

5V tolerant

3.3V PCI

PCIIDSel

PCISErr

I

5

4

Used for reporting address parity errors or catastrophic

failures detected by a PCI target.

5V tolerant

3.3V PCI

I/O

Used for reporting data parity errors on PCI transactions.

PCIPErr is driven active by the device receiving PCIAD0:31,

PCIC0:3[BE0:3], and PCIParity, two PCI clocks following the

data in which bad parity is detected.

5V tolerant

3.3V PCI

PCIPErr

I/O

4

5V tolerant

3.3V PCI

PCIClk

PCIReset

PCIINT

Used as the asynchronous PCI clock.

PCI specific reset

I

5V tolerant

3.3V PCI

O

PCI Interrupt. Open-drain output (two states; 0 or open

circuit).

5V tolerant

3.3V PCI

Req0 when internal arbiter is used, or Gnt when external

arbiter is used. IF PCI bus is used, pull this signal up;

otherwise, pull down.

5V tolerant

3.3V PCI

PCIReq0[Gnt]

I

5V tolerant

3.3V PCI

PCIReq1:5

Used as PCIReq1:5 input when internal arbiter is used

I

4

Gnt0 when internal arbiter is used, or Req when external

arbiter is used

5V tolerant

3.3V PCI

PCIGnt0[Req]

O

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Data Sheet

Table 6. Signal Functional Description (Sheet 2 of 9)

Notes:

1. Receiver input has hysteresis.

2. Must pull up. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.

3. Must pull down. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.

4. If not used, must pull up.

5. If not used, must pull down.

6. Strapping input during reset; pull up or pull down as required.

7. Pull-up may be required. See “External Peripheral Bus Control Signals” on page 42.

Signal Name

Description

I/O

Type

Notes

5V tolerant

3.3V PCI

PCIGnt1:5

PCIGnt1:5 output when internal arbiter is used.

O

HDLCEX Interface

HDLCEXTxClk

HDLCEXTxFS

Transmit Clock

I

3.3V LVTTL

Transmit Frame Synchronization

Transmit Data port A

Transmit Data port B

Receive Clock

HDLCEXTxDataA

HDLCEXTxDataB

HDLCEXRxClk

HDLCEXRxFS

O

I

Receive Frame Synchronization

Receive Data port A

Receive Data port B

I

HDLCEXRxDataA

HDLCEXRxDataB

I

5V tolerant

3.3V LVTTL

[HDLCEXTxEnA]

[HDLCEXTxEnB]

Transmit Enable port A

Transmit Enable port B

O

5V tolerant

3.3V LVTTL

HDLCMP Interface

HDLCMPTxClk0:3

[HDLCMPTxClk4:7]

HDLCMPTxData0:3

[HDLCMPTxData4:7]

Transmit Clock signal that controls the transmit bit rate

Transmit Data signal

O

3.3V LVTTL

5V tolerant

3.3V LVTTL

5V tolerant

3.3V LVTTL

Transmit Data signal

Transmit Data Enable signal that controls when the external

buffer is tri-stated

5V tolerant

3.3V LVTTL

[HDLCMPTxEn0:7]

HDLCMPRxClk0:3

[HDLCMPRxClk4:7]

HDLCMPRxData0:3

[HDLCMPRxData4:7]

O

I

Receive Clock signal that controls the receive bit rate

Receive Data signal

3.3V LVTTL

5V tolerant

3.3V LVTTL

I

3.3V LVTTL

5V tolerant

3.3V LVTTL

Receive Data signal

I

Ethernet Interface

Management Data Clock. The MDClk is sourced to the PHY.

Management information is transferred synchronously with

respect to this clock (MII, RMII, and SMII).

EMC0MDClk

EMC0MDIO

O

3.3V LVTTL

Management Data Input/Output is a bidirectional signal

between the Ethernet controller and the PHY. It is used to

transfer control and status information (MII, RMII, and SMII).

5V tolerant

3.3V LVTTL

I/O

1, 4

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Data Sheet

Table 6. Signal Functional Description (Sheet 3 of 9)

Notes:

1. Receiver input has hysteresis.

2. Must pull up. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.

3. Must pull down. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.

4. If not used, must pull up.

5. If not used, must pull down.

6. Strapping input during reset; pull up or pull down as required.

7. Pull-up may be required. See “External Peripheral Bus Control Signals” on page 42.

Signal Name

Description

I/O

Type

Notes

EMC0TxD0[EMC0Tx0D0][EMC0Tx0D]

EMC0TxD1[EMC0Tx0D1][EMC0Tx1D]

EMC0TxD2[EMC0Tx1D0][EMC0Tx2D]

EMC0TxD3[EMC0Tx1D1][EMC0Tx3D]

Transmit Data. A nibble wide data bus towards the net. The

data is synchronous with PHY0TxClk (MII 0[RMII 0, 1][SMII 0,

1, 2, 3]).

O

3.3V LVTTL

[EMC1TxD0][EMC1Tx2D0]

[EMC1TxD1][EMC1Tx2D1]

[EMC1TxD2][EMC1Tx3D0]

[EMC1TxD3][EMC1Tx3D1]

5V tolerant

3.3V LVTTL

RMII Transmit Data (MII 1[RMII 2, 3]).

O

Transmit Enable. This signal is driven by EMAC2 to the PHY.

Data is valid during the active state of this signal. Deassertion

of this signal indicates end of frame transmission. This signal

is synchronous with PHYTxClk (MII 0[RMII 0]).

EMC0TxEn[EMC0Tx0En][EMC0Sync]

3.3V LVTTL

or

SMII Sync.

Transmit Error. This signal is generated by the Ethernet

controller, is connected to the PHY and is synchronous with

the PHY0TxClk. It informs the PHY that an error was detected

(MII 0).

EMC0TxErr[EMC0Tx1En]

[EMC1TxEn][EMC1Tx2En]

[EMC1TxErr][EMC1Tx3En]

O

or

Transmit Enable [RMII 1].

5V tolerant

3.3V LVTTL

Transmit Enable ([MII 1][RMII 2]).

Transmit Error. This signal is generated by the Ethernet

controller, is connected to the PHY and is synchronous with

the PHY1TxClk. It informs the PHY that an error was detected

([MII 1]).

5V tolerant

3.3V LVTTL

or

Transmit Enable [RMII 3].

Collision [receive error] signal from the PHY. This is an

asynchronous signal (MII 0).

5V tolerant

3.3V LVTTL

PHY0Col[PHY0Rx1Er]l

I

or

Receive Error ([RMII 1]).

Carrier Sense signal from the PHY. This is an asynchronous

signal (MII 0).

5V tolerant

3.3V LVTTL

PHY0CrS[PHY0CrS0DV]

PHY0RxClk

1, 5

or

Carrier sense data valid ([RMII 0]).

Receiver medium clock. This signal is generated by the PHY

(MII 0).

5V tolerant

3.3V LVTTL

I

1, 4

PHY0RxD0[PHY0Rx0D0][PHY0Rx0D]

PHY0RxD1[PHY0Rx0D1][PHY0Rx1D]

PHY0RxD2[PHY0Rx1D0][PHY0Rx2D]

PHY0RxD3[PHY0Rx1D1][PHY0Rx3D]

Received Data. This is a nibble wide bus from the PHY. The

data is synchronous with PHY0RxClk (MII 0[RMII 0, 1][SMII 0,

1, 2, 3]).

5V tolerant

3.3V LVTTL

[PHY1RxD0][PHY1Rx2D0]

[PHY1RxD1][PHY1Rx2D1]

[PHY1RxD2][PHY1Rx3D0]

[PHY1RxD3][PHY1Rx3D1]

5V tolerant

3.3V LVTTL

Receive Data (MII 1[RMII 2, 3]).

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Data Sheet

Table 6. Signal Functional Description (Sheet 4 of 9)

Notes:

1. Receiver input has hysteresis.

2. Must pull up. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.

3. Must pull down. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.

4. If not used, must pull up.

5. If not used, must pull down.

6. Strapping input during reset; pull up or pull down as required.

7. Pull-up may be required. See “External Peripheral Bus Control Signals” on page 42.

Signal Name

Description

I/O

Type

Notes

Receive Data Valid. Data on the Data Bus is valid when this

signal is activated. Deassertion of this signal indicates end of

the frame reception (MII 0).

5V tolerant

3.3V LVTTL

PHY0RxDV[PHY0CrS1DV]

I

1, 5

or

Carrier sense data valid ([RMII 1])

Receive Error. This signal comes from the PHY and is

synchronous with PHY0RxClk (MII 0 [RMII 0]).

5V tolerant

3.3V LVTTL

PHY0RxErr[PHY0Rx0Er]

PHY0TxClk[PHY0RefClk]

I

1, 5

1, 4

Transmit medium clock. This signal is generated the PHY

([MII 0]).

5V tolerant

or

3.3V LVTTL

Reference Clock [RMII and SMII].

Collision [receive error] signal from the PHY. This is an

asynchronous signal ([MII 1]).

5V tolerant

3.3V LVTTL

[PHY1Col][PHY1Rx3Er]

or

I

1, 5

1, 4

Receive Error. This signal comes from the PHY and is

synchronous with PHY1RxClk ([RMII 3]).

Carrier Sense signal from the PHY. This is an asynchronous

signal ([MII 1]).

5V tolerant

3.3V LVTTL

[PHY1CrS][PHY1CrS2DV]

or

Carrier Sense Data Valid ([RMII 2]).

Receiver medium clock. This signal is generated by the PHY

([MII 1]).

5V tolerant

3.3V LVTTL

[PHY1RxClk]

I

i

Receive Data Valid ([MII 1]).

5V tolerant

3.3V LVTTL

[PHY1RxDV][PHY1CrS3DV]

or

Carrier Sense Data Valid ([RMII 3]).

Receive Error. This signal comes from the PHY and is

synchronous with PHY1RxClk ([MII 1][RMII 2]).

5V tolerant

3.3V LVTTL

[PHY1RxErr][PHY1Rx2Er]

[PHY1TxClk]

I

Transmit medium clock. This signal is generated the PHY

([MII 1]).

5V tolerant

3.3V LVTTL

SDRAM Interface

Memory Data bus

Notes:

MemAddr00:31

MemAddr12:00

I/O

O

3.3V LVTTL

1. MemAddr00 is the most significant bit (msb).

2. MemData31 is the least significant bit (lsb).

Memory Address bus.

Notes:

1. MemAddr12 is the most significant bit (msb).

2. MemAddr00 is the least significant bit (lsb).

BA1:0

RAS

Bank Address supporting up to 4 internal banks

Row Address Strobe.

O

3.3V LVTTL

CAS

Column Address Strobe.

DQM for byte lane 0 (MemAddr00:7),

1 (MemAddr08:15),

DQM0:3

O

3.3V LVTTL

2 (MemData16:23), and

3 (MemData24:31)

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Data Sheet

Table 6. Signal Functional Description (Sheet 5 of 9)

Notes:

1. Receiver input has hysteresis.

2. Must pull up. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.

3. Must pull down. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.

4. If not used, must pull up.

5. If not used, must pull down.

6. Strapping input during reset; pull up or pull down as required.

7. Pull-up may be required. See “External Peripheral Bus Control Signals” on page 42.

Signal Name

DQMCB

ECC0:7

Description

DQM for ECC check bits.

I/O

O

Type

Notes

3.3V LVTTL

ECC check bits 0:7.

I/O

O

BankSel0:3

WE

Select up to four external SDRAM banks.

Write Enable.

O

ClkEn0:1

SDRAM Clock Enable.

O

Two copies of an SDRAM clock allows, in some cases,

glueless SDRAM attachment without requiring this signal to

be repowered by a PLL or zero-delay buffer.

MemClkOut0:1

External Slave Peripheral Bus Interface

PerData00:31

O

3.3V LVTTL

External peripheral data bus when not in external master

mode, otherwise used by external master.

5V tolerant

3.3V LVTTL

I/O

1

Note: PerData00 is the most significant bit (msb) on this bus.

External peripheral address bus when not in external master

mode, otherwise used by external master.

5V tolerant

3.3V LVTTL

PerAddr00:31

PerPar0:3

I/O

1

5V tolerant

3.3V LVTTL

External peripheral byte parity signals.

Peripheral write-byte enable. Byte-enables which are valid for

an entire cycle or write-byte-enables which are valid for each

byte on each data transfer, allowing partial word transactions.

Used by either external bus controller or DMA controller

depending upon the type of transfer involved. Used as inputs

when external bus master owns the external interface.

5V tolerant

3.3V LVTTL

PerWBE0:3

[PerWE]

I/O

1, 2, 7

Peripheral write enable. Low when any of the four PerWBE

signals are low.

5V tolerant

3.3V LVTTL

I/O

O

7

PerCS0

[PerCS1:7]

5V tolerant

3.3V LVTTL

Peripheral Chip Selects

Peripheral output enable. Used by either the external bus

controller or the DMA controller depending upon the type of

transfer involved. When the NPe405H is the bus master, it

enables the peripherals to drive the bus.

5V tolerant

3.3V LVTTL

PerOE

O

7

1

Peripheral read/write. Used when not in external master mode

by either the external bus controller or DMA controller

depending upon the type of transfer involved. High indicates a

read from memory, low indicates a write to memory.

5V tolerant

3.3V LVTTL

PerR/W

I/O

Otherwise it used by the external master as an input to

indicate the direction of transfer.

5V tolerant

3.3V LVTTL

PerReady

PerBLast

PerClk

Indicates peripheral is ready to transfer data.

I

I/O

O

I

1

Peripheral burst last. Used to indicate the last transfer of a

memory access.

5V tolerant

3.3V LVTTL

1, 7

Peripheral Clock. Used by an external master and by

synchronous peripheral slaves.

5V tolerant

3.3V LVTTL

5V tolerant

3.3V LVTTL

PerErr

Used to indicate errors from peripherals.

1, 5

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Data Sheet

Table 6. Signal Functional Description (Sheet 6 of 9)

Notes:

1. Receiver input has hysteresis.

2. Must pull up. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.

3. Must pull down. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.

4. If not used, must pull up.

5. If not used, must pull down.

6. Strapping input during reset; pull up or pull down as required.

7. Pull-up may be required. See “External Peripheral Bus Control Signals” on page 42.

Signal Name

Description

I/O

Type

Notes

DMA request. Used by peripheral slaves to request a data

transfer. Following a system reset, the default mode of the

signals is active-low. They may be programmed to active-high

using the DMA0_POL register.

5V tolerant

3.3V LVTTL

[DMAReq0:3]

I

1

DMA acknowledge. Used to indicate to peripherals that data

transfer is complete. Following a system reset, the default

mode of the signals is active-low. They may be programmed

to active-high using the DMA0_POL register.

5V tolerant

3.3V LVTTL

[DMAAck0:3]

O

End Of Transfer/Terminal Count. Indication by peripherals

that all data has been transferred, or by DMA controller that

programmed amount of data has been transferred. Following

a system reset, the default mode of the signals is active-low.

They may be programmed to active-high using the

DMA0_POL register.

5V tolerant

3.3V LVTTL

[EOT0:3/TC0:3]

I/O

1

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Data Sheet

Table 6. Signal Functional Description (Sheet 7 of 9)

Notes:

1. Receiver input has hysteresis.

2. Must pull up. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.

3. Must pull down. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.

4. If not used, must pull up.

5. If not used, must pull down.

6. Strapping input during reset; pull up or pull down as required.

7. Pull-up may be required. See “External Peripheral Bus Control Signals” on page 42.

Signal Name

Description

I/O

Type

Notes

External Master Peripheral Interface

Peripheral Reset. Used by an external master and

synchronous peripheral slaves.

5V tolerant

3.3V LVTTL

ExtReset

HoldReq

HoldAck

ExtReq

ExtAck

O

I

Hold Request. Used by an external master to request

ownership of the peripheral bus.

5V tolerant

3.3V LVTTL

1, 5

6

Hold Acknowledge. Used by the NPe405H to transfer

ownership of peripheral bus to an external master.

5V tolerant

3.3V LVTTL

O

I

External Request. Used by an external master to indicate it is

prepared to transfer data.

5V tolerant

3.3V LVTTL

1

External Acknowledgement. Used by the NPe405H to

indicate that a data transfer occurred.

5V tolerant

3.3V LVTTL

O

I

6

Hold Primary. Used by an external master to indicate the

priority of a given transfer (0 = high, 1 = low).

5V tolerant

3.3V LVTTL

HoldPri

1

Bus Request. Used when the NPe405H needs to regain

control of peripheral interface from an external Master.

5V tolerant

3.3V LVTTL

BusReq

O

Internal Peripheral Interface

Serial Clock used to provide an alternative clock to the

internally generated serial clock. Used in cases where the

allowable internally generated baud rates are not satisfactory.

This input can be individually connected to either or both

UART0 and UART1.

5V tolerant

3.3V LVTTL

UARTSerClk

I

1

5V tolerant

3.3V LVTTL

UART0_Rx

UART0_Tx

UART0 Receive data.

I

O

I

5V tolerant

3.3V LVTTL

UART0 Transmit data.

5V tolerant

3.3V LVTTL

[UART0_DCD]

[UART0_DSR]

[UART0_CTS]

[UART0_DTR]

[UART0_RTS]

[UART0_RI]

UART0 Data Carrier Detect.

UART0 Data Set Ready.

UART0 Clear To Send.

UART0 Data Terminal Ready.

UART0 Request To Send.

UART0 Ring Indicator.

1

5V tolerant

3.3V LVTTL

I

5V tolerant

3.3V LVTTL

I

5V tolerant

3.3V LVTTL

O

I

5V tolerant

3.3V LVTTL

5V tolerant

3.3V LVTTL r

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Data Sheet

Table 6. Signal Functional Description (Sheet 8 of 9)

Notes:

1. Receiver input has hysteresis.

2. Must pull up. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.

3. Must pull down. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.

4. If not used, must pull up.

5. If not used, must pull down.

6. Strapping input during reset; pull up or pull down as required.

7. Pull-up may be required. See “External Peripheral Bus Control Signals” on page 42.

Signal Name

Description

I/O

Type

Notes

5V tolerant

3.3V LVTTL

UART1_Rx

UART1 Receive data.

UART1 Transmit data.

I

1

5V tolerant

3.3V LVTTL

UART1_Tx

[UART1_DCD]

[UART1_DSR]

[UART1_CTS]

[UART1_DTR]

[UART1_RTS]

[UART1_RI]

O

I

6

5V tolerant

3.3V LVTTL

UART1 Data Carrier Detect.

UART1 Data Set Ready.

1, 4

5V tolerant

3.3V LVTTL

I

5V tolerant

3.3V LVTTL

UART1 Clear To Send.

I

5V tolerant

3.3V LVTTL

UART1 Data Terminal Ready.

UART1 Request To Send.

UART1 Ring Indicator.

O

I

5V tolerant

3.3V LVTTL

5V tolerant

3.3V LVTTL

1, 4

1, 2

5V tolerant

3.3V LVTTL

IICSCL[IECSCL]

IICSDA[IECSDA]

IIC [Initilization PROM] Serial Clock.

IIC [Initilization PROM] Serial Data.

I/O

5V tolerant

3.3V LVTTL

Interrupts Interface

5V tolerant

3.3V LVTTL

[IRQ0:6]

Interrupt Requests.

I

1

JTAG Interface

5V tolerant

3.3V LVTTL

TDI

TMS

TDO

TCK

TRST

Test Data In.

I

1, 4

5V tolerant

3.3V LVTTL

Test Mode Select.

Test Data Out.

Test Clock.

5V tolerant

3.3V LVTTL

O

I

5V tolerant

3.3V LVTTL

1, 4

5

Test Reset. TRST must be low at power-on to reset the JTAG

boundary scan state machine.

5V tolerant

3.3V LVTTL

I

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Data Sheet

Table 6. Signal Functional Description (Sheet 9 of 9)

Notes:

1. Receiver input has hysteresis.

2. Must pull up. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.

3. Must pull down. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.

4. If not used, must pull up.

5. If not used, must pull down.

6. Strapping input during reset; pull up or pull down as required.

7. Pull-up may be required. See “External Peripheral Bus Control Signals” on page 42.

Signal Name

System Interface

Description

I/O

Type

Notes

3.3V Analog

Wire w/ESD

SysClk

SysReset

SysErr

Main System Clock input.

I

I/O

O

5V tolerant

3.3V LVTTL

Main System Reset.

1, 2

5V tolerant

3.3V LVTTL

Set to 1 when a Machine Check is generated.

Halt from external debugger.

5V tolerant

3.3V LVTTL

Halt

I

1

5V tolerant

3.3V LVTTL

GPIO0_00:31

GPIO1_00:31

TestEn

System General Purpose I/O.

I/O

I

5V tolerant

3.3V LVTTL

Communications General Purpose I/O.

Test Enable. Used only for manufacturing tests. Pull down for

normal operation.

3.3V LVTTL

Rcvr w/PD

This input must toggle at a rate of less than one half the CPU

core frequency (less than 100MHz in most cases). In most

cases this input toggles much slower (in the 1MHz to 10MHz

range).

5V tolerant

3.3V LVTTL

TmrClk

I

1

Trace Interface

[TS1E]

[TS2E]

Even Trace execution status.To access this function, software

must toggle a DCR bit.

5V tolerant

3.3V LVTTL

O

[TS1O]

[TS2O]

Odd Trace execution status. To access this function, software

must toggle a DCR bit.

5V tolerant

3.3V LVTTL

Trace Status. To access this function, software must toggle a

DCR bit.

5V tolerant

3.3V LVTTL

[TS3:6]

[TrcClk]

Trace interface clock. A toggling signal that is always half of

the CPU core frequency. To access this function, software

must toggle a DCR bit.

5V tolerant

3.3V LVTTL

O

1

Power Pins

Ground

GND

I

Hardwire

Note: J09-J14, K09-K14, L09-L14, M09-M14, N09-N14, and

P09-P14 are also thermal balls.

V_DD

Logic voltage—2.5V

I

Hardwire

OV_DD

Output driver voltage—3.3V

3.3V DC

AV_DD

Filtered PLL voltage—2.5V

I

Wire w/ESD

Other Pins

Reserved

Do not connect signals, voltage, or ground to these pins.

n/a

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Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 7. Absolute Maximum Ratings

The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause

permanent damage to the device.

Characteristic

Supply Voltage (Internal Logic)

Symbol

Value

0 to +2.7

Unit

V

V_DD

OV_DD

AV_DD

V_IN

Supply Voltage (I/O Interface)

0 to +3.6

V

PLL Supply Voltage ²

0 to +2.7

V

-0.6 to (OV_DD+ 0.6)

-0.6 to (OV_DD+ 2.4)

Input Voltage (3.3V LVTTL receivers)

Input Voltage (5.0V LVTTL receivers)

Storage Temperature Range

Case temperature under bias

V

V_IN

V

T_STG

T_C

-55 to +150

-40 to +120

×C

Notes:

1. All voltages are specified with respect to ground (GND).

2. AV should be derived from V using the following circuit:

DD

L1 – 2.2

µ

H SMT inductor (equivalent to MuRata

AV

V

DD

LQH3C2R2M34) or SMT chip ferrite bead (equivalent to

MuRata BLM31A700S)

L1

C1 – 3.3

µ

F SMT tantalum

C1

C2

C3

C2 – 0.1

µ

F SMT monolithic ceramic capacitor with X7R

dielectric or equivalent

C3 – 0.01

µ

F SMT monolithic ceramic capacitor with X7R

dielectric or equivalent

PACKAGE THERMAL SPECIFICATIONS

Table 8. Package Thermal Specifications

The NPe405H is designed to operate within a case temperature range of -40°C to 85°C. Thermal resistance values for the E-

PBGA packages in a convection environment are as follows:

Airflow

ft/min (m/sec)

Symbol

Package—Thermal Resistance

Unit

0 (0)

100 (0.51)

200 (1.02)

θ

35mm, 580-balls—Junction-to-Case

2

°C/W

JC

1

θ

13

12

11

35mm, 580-balls—Case-to-Ambient

CA

Notes:

1. For a chip mounted on a JEDEC 2S2P card without a heat sink.

2. For a chip mounted on a card with at least one signal and two power planes, the following relationships exist:

a. Case temperature, T is measured at top center of case surface with device soldered to circuit board.

,

C

b. T = T ^{– P}×θ , where T is ambient temperature and P is power consumption.

CA

A

C

A

c. T_CMax= T_JMax– P×θ , where T_JMaxis maximum junction temperature and P is power consumption.

JC

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Data Sheet

RECOMMENDED DC OPERATING CONDITIONS

Table 9. Recommended DC Operating Conditions

Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended

conditions can affect device reliability.

Notes:

1. PCI drivers meet PCI specifications.

Parameter

Logic Supply Voltage

Symbol

Minimum

+2.3

Typical

+2.5

Maximum

+2.7

Unit

V

Notes

V_DD

OV_DD

AV_DD

I/O Supply Voltage

PLL Supply Voltage

+3.0

+3.3

+3.6

V

+2.3

+2.5

+2.7

V

Input Logic High (3.3V LVTTL

receivers)

V_IH

OV_DD

V_DD

+2.0

+1.7

+2.0

V

Input Logic High (2.5V CMOS

receivers)

Input Logic High (5.0V LVTTL

receivers)

+5.5

V_IL

V_OH

V_OL

Input Logic Low

Output Logic High

Output Logic Low

0

+2.4

0

+0.8

V

OV_DD

+0.4

±10

3.3V I/O input current (no pull-up or

pull-down)

I_IL1

µ

A

I_IL2

I_IL3

Input Current (with internal pull-down)

Input Current (with internal pull-up)

±10 (@ 0V)

-250 (@ 0V)

400 (@ 3.6V)

±10 (@ 3.6V)

µ

A

Input Max Allowable Overshoot (2.5V

CMOS receivers)

V

+ 0.6

V

IMAO25

DD

Input Max Allowable Overshoot (3.3V

LVTTL receivers)

V_IMAO3

OV_DD+ 0.6

+5.5

V

Input Max Allowable Overshoot (5.0V

LVTTL receivers)

V_IMAO5

Input Max Allowable Undershoot

(3.3V or 5.0V receivers)

V_IMAU

-

0.6

Output Max Allowable Overshoot

(3.3V or 5.0V receivers)

V_OMAO

OV_DD+ 0.3

Output Max Allowable Undershoot

(3.3V and 5.0V receivers)

V_OMAU3

T_C

V

0.6

40

Case Temperature

+85

×C

-

Notes:

1. See “” on page 54

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Data Sheet

5 V-TOLERANT I/O INPUT CURRENT

Figure 3. 5V-Tolerant I/O Input Current

100

0

-100

-200

-300

-400

-500

-600

-700

0.0

1.0

2.0

3.0

4.0

5.0

Input Voltage (V)

INPUT CAPACITANCE

Table 10. Input Capacitance

Parameter

Symbol

Maximum

Unit

Notes

C

3.3V LVTTL I/O)

5V tolerant LVTTL I/O

PCI I/O

2.5

3.5

pF

IN1

IN2

IN3

IN4

pF

5.0

RX only pins

0.75

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Data Sheet

DC ELECTRICAL CHARACTERISTICS

Table 11. DC Electrical Characteristics

Parameter

Symbol

Minimum

599

755

964

77

Typical

669

843

1074

89

Maximum

740

Unit

mA

Active Operating Current for V_DD@ 133MHz

I_DD

Active Operating Current for V_DD@ 200MHz

Active Operating Current for V_DD@ 266MHz

Active Operating Current for OV_DD@ 133MHz

Active Operating Current for OV_DD@ 200MHz

Active Operating Current for OV_DD@ 266MHz

Active Operating Current for AV_DD

I_DD

928

1183

99

I_ODD

I_ADD

89

102

111

6

112

97

123

5.5

6.5

1

P

Active Operating Power @ 133MHz

Active Operating Power @ 200MHz

1.6

2

2.4

3

W

DD

2.4

1

P

DD

2.9

1

P

Active Operating Power @ 266MHz

2.5

DD

3.6

Notes:

1. Maximum power is characterized at V =2.7V, OV =3.6V, T =85×C, across the silicon process (worse case to best case), while running an application designed to maximize power

DD

C

consumption. The maximum power values are measured with the following clock rate combinations:

a. CPU=133.33MHz, PLB=66.66MHz, OPB=66.66MHz, EBC=33.33MHz, PCI=33.33MHz

b. CPU=200 MHz, PLB=100MHz, OPB=50MHz, EBC=50MHz, PCI=33.33MHz

c. CPU=266.66MHz, PLB=133.33MHz, OPB=66.66MHz, EBC=66.66MHz, PCI=33.33MHz

TEST CONDITIONS

Output

Clock timing and switching characteristics are specified in accordance with

operating conditions shown in the table “Recommended DC Operating

50pF

Conditions.” AC specifications are characterized at OV = 3.00V and T =

DD

J

85°C with the 50pF test load shown in the figure at right.

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Data Sheet

CLOCKING SPECIFICATIONS

Table 12. Clocking Specifications

Symbol

SysClk Input

F_C

Parameter

Min

Max

Units

SysClk clock input frequency

25

15

66.66

40

MHz

ns

T_C

SysClk clock period

T_CS

T_CH

T_CL

Clock edge stability (phase jitter, cycle to cycle)

Clock input high time

0.15

ns

40% of nominal period

60% of nominal period

ns

Clock input low time

ns

Note:Input slew rate > 2V/ns

MemClkOut Output

F_C

T_C

MemClkOut clock output frequency–133MHz

MemClkOut clock period–133MHz

MemClkOut clock output frequency–200MHz

MemClkOut clock period–200MHz

MemClkOut clock output frequency–266MHz

MemClkOut clock period–266MHz

Clock output high time

66.66

100

MHz

ns

15

10

F_C

MHz

ns

T_C

F_C

133.33

MHz

ns

T_C

7.5

T_CH

T_CL

45% of nominal period

55% of nominal period

ns

Clock output low time

ns

Other Clocks

F_C

VCO frequency

400

800

66.66

100

MHz

F_C

PLB frequency–133MHz

PLB frequency–200MHz

PLB frequency–266MHz

OPB frequency–133MHz

OPB frequency–200MHz

OPB frequency–266MHz

133.33

50¹

50

50¹

F_C

Notes:

1. If HDLCEX is not used, the maximum OPB frequency is 66.66MHz.

CLOCKING WAVEFORM

Figure 4. Clocking Waveform

2.0V

1.5V

0.8V

T

CL

CH

T

C

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SPREAD SPECTRUM CLOCKING

Data Sheet

Care must be taken when using a spread spectrum clock generator (SSCG) with the NPe405H. This controller

uses a PLL for clock generation inside the chip. The accuracy with which the PLL follows the SSCG is referred to

as tracking skew. The PLL bandwidth and phase angle determine how much tracking skew there is between the

SSCG and the PLL for a given frequency deviation and modulation frequency. When using an SSCG with the

NPe405H the following conditions must be met:

•

The frequency deviation must not violate the minimum clock cycle time. Therefore, when operating the

NPe405H with one or more internal clocks at their maximum supported frequency, the SSCG can only

lower the frequency.

•

The maximum frequency deviation cannot exceed −3%, and the modulation frequency cannot exceed

40kHz. In some cases, on-board NPe405H peripherals impose more stringent requirements (see Note 1).

Use the peripheral bus clock (PerClk) for logic that is synchronous to the peripheral bus since this clock

tracks the modulation.

Use the SDRAM MemClkOut since it also tracks the modulation.

Please refer to the application note Using a Spread Spectrum Clock Generator with the PowerPC 405GP for addi-

tional details. This application note is available on the AMCC web site at http://www.amcc.com.

Notes:

1. The serial port baud rates are synchronous to the modulated clock. The serial port has a tolerance of approx-

imately 1.5% on baud rate before framing errors begin to occur. The 1.5% tolerance assumes that the

connected device is running at precise baud rates. If an external serial clock is used the baud rate is unaf-

fected by the modulation.

2. Ethernet operation is unaffected.

3. IIC operation is unaffected.

4. The PCI clock specification for 66MHz allows a maximum frequency deviation of −1% at a modulation

between 30kHz and 33kHz. PCI asynchronous mode is unaffected.

Caution: It is up to the system designer to ensure that any SSCG used with the NPe405H meets the above

requirements and does not adversely affect other aspects of the system.

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Data Sheet

PERIPHERAL INTERFACE CLOCK TIMINGS

Table 13. Peripheral Interface Clock Timings

Parameter

PCIClk input frequency (asynchronous mode)

PCIClk period (asynchronous mode)

Min

Note 2

15

Max

Units

MHz

ns

66

Note 2

PCIClk input high time

40% of nominal period

60% of nominal period

ns

PCIClk input low time

40% of nominal period

60% of nominal period

ns

EMC0MDClk output frequency

EMC0MDClk period

–

2.5

MHz

ns

400

–

EMC0MDClk output high time

EMC0MDClk output low time

PHY0TxClk input frequency

PHY0TxClk period

160

–

ns

160

–

ns

2.5

25

MHz

ns

40

400

PHY0TxClk input high time

PHY0TxClk input low time

PHY0RxClk input frequency

PHY0RxClk period

35% of nominal period

–

ns

35% of nominal period

–

ns

2.5

25

MHz

ns

40

400

PHY0RxClk input high time

PHY0RxClk input low time

PerClk output frequency–133MHz

PerClk period–133MHz

35% of nominal period

–

ns

35% of nominal period

–

ns

–

33.33

MHz

ns

30

–

PerClk output frequency–200MHz

PerClk period–200MHz

–

50

MHz

ns

20

–

PerClk output frequency–266MHz)

PerClk period–266MHz

–

66.66

MHz

ns

15

–

PerClk output high time

45% of nominal period

–

55% of nominal period

1000/(2T_OPB+ 2ns)

ns

PerClk output low time

ns

MHz

UARTSerClk input frequency (Note 1)

UARTSerClk period

2T_OPB+ 2

–

ns

T_OPB+ 1

UARTSerClk input high time

UARTSerClk input low time

TmrClk input frequency–133MHz

TmrClk period–133MHz

–

ns

MHz

ns

–

33.33

30

–

TmrClk input frequency–200MHz

TmrClk period–200MHz

–

50

MHz

ns

20

–

TmrClk input frequency–266MHz

TmrClk period–266MHz

–

66.66

MHz

ns

15

–

TmrClk input high time

40% of nominal period

60% of nominal period

8.192

ns

TmrClk input low time

40% of nominal period

ns

HDLCEXTxClk, HDLCEXRxClk

0

–

MHz

HDLCMPTxClk, HDLCMPRxClk

2.048

Notes:

1.

T

is the period in ns of the OPB clock. The maximum OPB clock frequency is 33.33 MHz for 133MHz parts, 50 MHz for 200MHz parts, and 66.66MHz for 266MHz parts.

OPB

2. In asynchronous PCI mode the minimum PCIClk frequency is 1/8 the PLB Clock. Refer to the NPe405H User’s Manual for more information.

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Data Sheet

INPUT SETUP AND HOLD WAVEFORM

Figure 5. Input Setup and Hold Waveform

Clock

T

min

IS

T

min

IH

Inputs

Valid

OUTPUT DELAY AND FLOAT TIMING WAVEFORM

Figure 6. Output Delay and Float Timing Waveform

Clock

max

min

max

min

max

min

T

OV

T

Outputs

OH

High (Drive)

Float (High-Z)

Valid

Low (Drive)

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I/O SPECIFICATIONS—ALL

Data Sheet

Table 14. I/O Specifications—All (Sheet 1 of 2)

Notes:

1. PCI timings are for asynchronous operation up to 66MHz. PCI output hold time requirement is 1ns for 66MHz and 2ns for

33MHz.

Input (ns)

Output (ns)

Output Current (mA)

I/O H I/O L

(maximum) (minimum)

Signal

Clock

Notes

Setup Time Hold Time Valid Delay Hold Time

(T min)

(T

OV

max)

(T min)

OH

IS

IH

PCI Interface

PCIAD00:31

PCIC0:3[BE3:0]

PCIClk

3.0

n/a

3.0

0.0

n/a

0.0

6.0

2.0

0.5

n/a

0.5

1.5

n/a

1.5

PCIClk

6

6.0

n/a

6.0

2.0

n/a

2.0

6

async

6

PCIDevSel

PCIFrame

PCIClk

6

PCIGnt0[Req]

PCIGnt1:5

n/a

6.0

2.0

0.5

1.5

PCIClk

6

PCIIDSel

3.0

n/a

3.0

0.0

n/a

0.0

n/a

6.0

n/a

2.0

n/a

0.5

n/a

1.5

PCIClk

6

PCIINT[PerWE]

PCIIRDY

async

6

PCIParity

PCIPErr

PCIReq0[Gnt]

PCIReq1:5

5.0

0.0

n/a

PCIClk

6

PCIReset

PCISErr

PCIStop

PCITRDY

n/a

3.0

n/a

0.0

6.0

2.0

0.5

1.5

PCIClk

6

Internal Peripheral Interface

IICSCL

async

n/a

async

n/a

async

n/a

async

n/a

17

11

n/a

8

IICSDA

[UART0_CTS]

[UART0_DCD]

[UART0_DSR]

[UART0_DTR]

[UART0_RI]

n/a

12

n/a

async

n/a

async

n/a

async

n/a

async

n/a

12

n/a

8

[UART0_RTS]

UART0_Rx

async

n/a

async

n/a

async

n/a

async

n/a

12

n/a

8

UART0_Tx

async

n/a

async

n/a

[UART1_CTS]

[UART1_DCD]

[UART1_DSR]

[UART1_DTR]

[UART1_RI]

async

n/a

async

n/a

12

n/a

8

n/a

async

n/a

async

n/a

async

n/a

async

n/a

12

n/a

8

[UART1_RTS]

UART1_Rx

async

n/a

async

n/a

async

n/a

async

n/a

12

n/a

8

UART1_Tx

async

n/a

async

n/a

UARTSerClk

Interrupts Interface

[IRQ0:6]

async

n/a

async

n/a

60

DS2011

AMCC Proprietary

Revision 1.02 – November 16, 2007

NPe405H – PowerNP NPe405H Embedded Processor

Data Sheet

Table 14. I/O Specifications—All (Sheet 2 of 2)

Notes:

1. PCI timings are for asynchronous operation up to 66MHz. PCI output hold time requirement is 1ns for 66MHz and 2ns for

33MHz.

Input (ns)

Output (ns)

Output Current (mA)

I/O H I/O L

(maximum) (minimum)

Signal

JTAG Interface

Clock

Notes

Setup Time Hold Time Valid Delay Hold Time

(T min)

(T

OV

max)

(T min)

OH

IS

IH

TCK

async

n/a

async

n/a

12

n/a

8

TDI

n/a

async

n/a

async

n/a

TDO

TMS

async

n/a

TRST

n/a

System Interface

GPIO0:1

Halt

na

async

n/a

na

async

n/a

na

n/a

na

n/a

12

n/a

12

8

n/a

8

SysClk

SysErr

SysReset

TestEn

TmrClk

n/a

8.6

3.7

n/a

7.4

3.3

12

8

dc

n/a

async

AMCC Proprietary

DS2011

61

Revision 1.02 – November 16, 2007

NPe405H – PowerNP NPe405H Embedded Processor

Data Sheet

I/O SPECIFICATIONS(A)—133 AND 200 MHZ

Table 15. I/O Specifications—133 and 200MHz (Sheet 1 of 3)

Notes:

1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.

2. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the

command is used by SDRAM. Output times in table are in cycle 1.

3. SDRAM I/O timings are specified relative to a MemClkOut terminated in a lumped 10pF load.

4. SDRAM interface hold times are guaranteed at the NPe405H package pin. System designers must use the NPe405H IBIS

model (available from www.amcc.com) to ensure their clock distribution topology minimizes loading and reflections, and that

the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring.

5. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.

Input (ns)

Output (ns)

Output Current (mA)

I/O H I/O L

(maximum) (minimum)

Signal

Clock

Notes

Setup Time Hold Time Valid Delay Hold Time

(T_ISmin)

(T_IHmin)

(T_OVmax)

(T_OHmin)

Ethernet Interface

EMC0MDClk

n/a

0.0

n/a

12

8

1, async

1

1 OPB clock 1 OPB Clock

period + 10ns

EMC0MDIO

100

EMC0MDClk

PHYTX

period

EMC0TxD0:3

[EMC0Tx0:1D0:1]

[EMC0Tx0:3D]

12.4

7.0

5.0

4.1

2.3

1.5

n/a

12

8

1

EMC0TxEn

[EMC0Tx0En]

[EMC0Sync]

14.4

7.0

5.0

4.3

2.3

1.5

PHYTX

1

EMC0TxErr[EMC0Tx1En]

[EMC1TxD0][EMC1Tx2D0]

[EMC1TxD1][EMC1Tx2D1]

[EMC1TxD2][EMC1Tx3D0]

[EMC1TxD3][EMC1Tx3D1]

[EMC1TxEn][EMC1Tx2En]

[EMC1TxErr][EMC1Tx3En]

PHY0Col[PHY0Rx1Er]

PHY0CrS[PHY0CrS0DV]

PHY0RxClk

n/a

13.6[7.1]

[15.0][8.2]

[15.0][8.3]

[15.1][8.2]

[15.0][8.2]

[16.4][8.2]

[16.5][8.3]

n/a

4.0[2.4]

[4.8][2.5]

n/a

12

n/a

8

n/a

8

n/a

8

n/a

8

n/a

8

n/a

8

async[1.1]

async[1.0]

n/a

async[0.9]

async[1.3]

n/a

1

n/a

1, async

PHY0RxD0:3

[PHY0Rx0:1D0:1]

[PHY0Rx0:3D]

1.7

1.1

1.6

0.9

0.2

n/a

PHYRX

1

PHY0RxDV[PHY0CRS1DV]

PHY0RxErr[PHY0Rx0Er]

PHY0TxClk[PHY0RefClk]

[PHY1RxD0][PHY1Rx2D0]

[PHY1RxD1][PHY1Rx2D1]

[PHY1RxD2][PHY1Rx3D0]

[PHY1RxD3][PHY1Rx3D1]

[PHY1Col][PHY1Rx3Er]

[PHY1CrS][PHY1CrS2DV]

[PHY1RxClk]

1.5[1.0]

1.5[1.1]

n/a

1.7[1.1]

1.6[1.0]

n/a

PHYRX

1

1, async

[1.0][1.8]

[1.3][2.2]

[1.1][2.2]

[1.0][1.9]

[1.4][2.2]

[1.3][2.1]

n/a

[3.5][0.7]

[3.0][0.3]

[3.3][0.7]

[2.2][0.3]

[2.6][0.8]

n/a

[PHY1RxDV]

[PHY1CrS3DV]

[1.0]

[2.1]

[2.6]

[0.0]

n/a

[PHY1RxErr][PHY1Rx2Er]

[PHY1TxClk]

[1.0][1.9]

n/a

[3.2][0.6]

n/a

HDLCEX Interface

HDLCEXRxClk

n/a

1.4

0.6

n/a

HDLCEXRxDataA:B

HDLCEXRxFS

27.7

24.2

62

DS2011

AMCC Proprietary

Revision 1.02 – November 16, 2007

NPe405H – PowerNP NPe405H Embedded Processor

Data Sheet

Table 15. I/O Specifications—133 and 200MHz (Sheet 2 of 3)