PPC405EX-SSC400T_技术文档

Part Number 405EX

Revision 1.23 - January 28, 2009

Data Sheet

405EX

PowerPC 405EX Embedded Processor

Features

• Two one-lane PCI Express interfaces operating up

to 2.5 Gbps

• AMCC PowerPC® 405 32-bit RISC processor

core operating from 333MHz to 600MHz including

16KB I- and D-caches with parity checking

• Two Gigabit Ethernet interfaces (half- and full-

duplex) to external PHY (GMII/RGMII)

• 128-bit processor local bus (PLB) operating up to

200MHz

• USB 2.0 OTG port configurable as either Host or

Device

• 32-bit peripheral bus (OPB) operating up to

100 MHz

• Programmable universal interrupt controller (UIC)

• General Purpose Timer (GPT)

• External 8-,16-, or 32-bit peripheral bus (EBC)

operating up to 100MHz

• Up to two serial ports (16750 compatible UART)

• External bus master (EBM) operating up to

100MHz

• Two IIC interfaces operating up to 400kHz and

supporting all standard IIC EEPROMs

• Optional Security feature with True Random

Number generation

• One SCP (SPI) synchronous full-duplex channel

operating up to 25MHz

• Eight- and 16-bit NAND Flash interface

• General purpose I/Os (GPIOs), each with

programmable interrupts and outputs

• Boot from NOR Flash on the external peripheral

bus or NAND Flash on the NAND Flash interface

• Supports JTAG for board-level testing

• DMA (4-channel) support for all on-chip slaves

and external bus, UARTs, and devices on the EBC

• System power management, low power

dissipation and small form factor

• DDR1/2 SDRAM interface operating up to 400

Mbps

• Available in a RoHS compliant (lead-free) package

Description

With speeds up to 600MHz, a flexible off-chip memory

architecture, and a diverse communications package

that includes PCI Express, USB 2.0 OTG, and

10/100/1000 Ethernet, the PowerPC 405EX

in need of performance and connectivity

improvements.

Technology: Cu-08 CMOS, 90nm

embedded processor provides a low power and small

footprint system-on-a-chip (SOC) solution for a wide

range of high performance, cost-constrained

Package: 388-ball, 27mm × 27mm, enhanced plastic

ball grid array (EPBGA), 1mm ball pitch

embedded applications. This includes wireless LAN

applications, security appliances, internet appliances,

line cards, and intelligent USB peripherals. It is an

easily programmable general purpose, 32-bit RISC

controller that offers an upgrade path for applications

Power consumption: typically less than 1.8W at

400MHz

Voltages required: 3.3V, 2.5V, 1.8V (DDR2 SDRAM

only), and 1.2V

AMCC Proprietary

1

Revision 1.23 - January 28, 2009

PPC405EX – PowerPC 405EX Embedded Processor

Table of Contents

Data Sheet

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Ordering, PVR, and JTAG Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Address Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

PowerPC 405 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Internal Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

External Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

NAND Flash Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

USB 2.0 OTG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

DDR1/2 SDRAM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Security Function (optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

IIC Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Serial Communication Port Interface (SCP/SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

General Purpose I/O (GPIO) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Universal Interrupt Controller (UIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Ethernet Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Signal Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Signal Functional Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Ratings and Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Spread Spectrum Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

DDR 1/2 SDRAM I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

PCI Express (PCI-E) I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

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AMCC Proprietary

Revision 1.23 - January 28, 2009

PPC405EX – PowerPC 405EX Embedded Processor

List of Figures

Data Sheet

Figure 1. PPC405EX Embedded Controller Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. Package 27mm, 388-Ball EPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 3. Clocking Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 4. Input Setup and Hold Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 5. Output Delay and Float Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 6. Setup and Hold Timing Waveforms for RGMII Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 7. DDR SDRAM Simulation Signal Termination Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 8. DDR SDRAM Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 9. DDR SDRAM Read Data Path for a Single Data Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 10. DDR SDRAM Memory Data and DQS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 11. DDR SDRAM Read Cycle Timing—Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

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PPC405EX – PowerPC 405EX Embedded Processor

List of Tables

Data Sheet

Table 1. System Memory Address Map (4GB System Memory) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 2. DCR Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 3. Signals Listed Alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 4. Signals Listed by Ball Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 5. Pin Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 6. Signal Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 7. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 8. Package Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 9. Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 10. I/O Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 11. Typical DC Power Supply Requirements with DDR1 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 12. Maximum DC Power Supply Requirements with DDR1 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 13. Typical DC Power Supply Requirements with DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 14. Maximum DC Power Supply Requirements with DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 15. DC Power Supply Loads with DDR1 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 16. DC Power Supply Loads with DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 17. Power Contribution of Functional Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 18. System Clocking Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 19. Peripheral Interface I/O Clock Timings (not SDRAM or PCI-E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 20. RGMII I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 21. I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 22. DDR SDRAM Output Driver Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 23. DDR SDRAM Write Operation Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 24. I/O Timing—DDR SDRAM T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

DS

Table 25. I/O Timing—DDR SDRAM T and T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

HA

SA

Table 26. I/O Timing—DDR SDRAM Write Timing T and T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

SD

HD

Table 27. I/O Timing—DDR SDRAM Read Timing T and T

SD

Table 28. PCI-E Receiver I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 29. PCI-E Reference Clock I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 30. PCI-E Transmitter I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 31. Strapping Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

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PPC405EX – PowerPC 405EX Embedded Processor

Ordering, PVR, and JTAG Information

Data Sheet

This section provides the part number nomenclature. For availability, contact your local AMCC sales office.

Order Part Number

Rev

Level

Product Name

Package

PVR Value

JTAG ID

(see Notes:)

PPC405EX

PPC405EX-SplfffT

PPC405EX-NplfffT

27mm, 388-ball, EPBGA

C

0x1291147F

0x1291147D

0x1405B1E1

Notes:

1. S = security feature present, N = security feature not present.

2. p = Package: S = lead-free (RoHS compliant), P = leaded

3. l = Chip revision level: C = revision level C

4. fff = Processor frequency:

400 = 400MHz

533 = 533MHz

600 = 600MHz

5. T = Case temperature range, -40°C to +85°C (see footnote 5. on page 49)

The part number contains a part modifier. Included in the modifier is a revision code. This refers to the die mask

revision number and is specified in the part numbering scheme for identification purposes only.

The PVR (Processor Version Register) and the JTAG ID register are software accessible (read-only) and contain

information that uniquely identifies the part. See the PPC405EX Embedded Processor User’s Manual for details

about accessing these registers.

Order Part Number Key

PPC405EX-SSC600T

AMCC Part Number

Case Temperature Range

Processor Speed (MHz)

Security

Chip Package

Revision Level

Note: The example P/N above has the security feature, is lead-free, capable of running at 600MHz,

and is shipped in a tray (tape-and-reel not available).

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PPC405EX – PowerPC 405EX Embedded Processor

Data Sheet

Block Diagram

Figure 1. PPC405EX Embedded Controller Functional Block Diagram

Clock

Control

Reset

Universal

Interrupt

Controller

Power

Mgmt

Timers

MMU

DCRs

NAND

Flash

Controller

EBC

EBM

IICx2/ SCP

BSC

UART

x2

GPIO

DCR

Bus

Power PC

405 Processor

(SPI)

Trace

16KB D-Cache 16KB I-Cache

JTAG

On-chip Peripheral Bus (OPB)

Arbiter

OPB/PLB

Bridges

GPT

PKA/

TRNG

Processor Local Bus (PLB4)—128 bits

Arbiter

PCI-E

1-lane

PCI-E

1-lane

DDR1/2

SDRAM

AHB-PLB

Bridge

EIP-94

Security

DMA

MAL/w

Interrupt Coalescing

Controller

(4-Channel)

Controller

Feature

Ethernet

MAC

1Gbit

x2

USB 2.0

OTG

Controller

HSS

ULPI

The PPC405EX is designed using the IBM Microelectronics Blue Logic^TMmethodology in which major functional

blocks are integrated together to create an ASIC (application-specific integrated circuit) product. This approach

provides a consistent way to create complex ASICs using IBM CoreConnect^TMBus Architecture.

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PPC405EX – PowerPC 405EX Embedded Processor

Address Maps

Data Sheet

The PPC405EX incorporates two address maps. The first address map defines the possible use of addressable

memory regions that the processor can access. The second address map defines Device Configuration Register

(DCR) addresses (numbers). The DCRs are accessed by software running on the PPC405EX processor through

the use of mtdcr and mfdcr instructions.

Table 1. System Memory Address Map (4GB System Memory)

Function

Local Memory

Subfunction

DDR 1/2 SDRAM

Start Address (Hex)

0 0000 0000

0 8000 0000

0 9000 0000

0 EF60 0000

0 EF60 0200

0 EF60 0208

0 EF60 0300

0 EF60 0308

0 EF60 0400

0 EF60 0420

0 EF60 0500

0 EF60 0520

0 EF60 0600

0 EF60 0606

0 EF60 0700

0 EF60 0740

0 EF60 0800

0 EF60 0880

0 EF60 0900

0 EF60 0A00

0 EF60 0B00

0 EF60 0C04

0 EF61 0000

0 EF62 0000

0 EF62 0100

0 EF6C 0000

0 EF70 0000

0 EF78 0000

0 F000 0000

0 FFE0 0000

End Address (Hex)

0 7FFF FFFF

0 8FFF FFFF

0 EF5F FFFF

0 EF60 01FF

0 EF60 0207

0 EF60 02FF

0 EF60 0307

0 EF60 03FF

0 EF60 041F

0 EF60 04FF

0 EF60 051F

0 EF60 05FF

0 EF60 0605

0 EF60 06FF

0 EF60 073F

0 EF60 07FF

0 EF60 087F

0 EF60 08FF

0 EF60 09FF

0 EF60 0AFF

0 EF60 0C03

0 EF60 FFFF

0 EF61 FFFF

0 EF62 00FF

0 EF6B FFFF

0 EF6F FFFF

0 EF77 FFFF

0 EFFF FFFF

0 FFDF FFFF

0 FFFF FFFF

Size

2GB

EBC

256MB

1.6GB

512B

8B

PCI Express

GPT

UART 0

Reserved

UART 1

248B

8B

Reserved

IIC 0

248B

32B

Reserved

IIC 1

224B

32B

Reserved

SCP

224B

6B

OPB Peripherals

Reserved

OPB Arbiter

Reserved

GPIO

250B

64B

192B

128B

256B

260B

62KB

64KB

256B

640KB

256KB

512KB

8.9MB

254MB

2MB

Reserved

Ethernet 0

Ethernet 1

RGMII Bridge

Reserved

PKA +TRNG

PCI Express Interrupt Handler

Reserved

USB OTG

Security

PLB/AHB Peripherals

Reserved

EBC Memory

EBC Memory—Boot ROM

EBC

Notes:

1. If peripheral bus boot is selected, peripheral bank 0 is automatically configured at reset to the address range listed above.

2. After the boot process, software may reassign the boot memory regions for other uses.

3. PCI Express can use PLB address range 0x1 0000 0000 to 0xF FFFF FFFF even though the CPU can not access it.

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PPC405EX – PowerPC 405EX Embedded Processor

Data Sheet

Table 2. DCR Address Map

Function

1

Start Address (Hex)

End Address (Hex)

0x3FF

Size

1KW (4KB)¹

0x000

Total DCR Address Space

Reserved

000

00C

00E

010

012

014

016

020

030

040

060

080

090

0A0

0A8

0B0

0B3

0C0

0D0

0E0

0F0

100

140

180

200

00B

00D

00F

011

013

015

01F

02F

03F

05F

07F

08F

09F

0A7

0AF

0B2

0BF

0CF

0DF

0EF

0FF

13F

17F

1FF

3FF

CPR (Clocking, Power-on Reset)

System DCRs

DDR 1/2 SDRAM Controller

External Bus Controller (EBC)

External Bus Master (EBM)

Reserved

2W

PLB4XAHB Bridge

Reserved

16W

PCI Express 0

PCI Express 1

PLB4 Arbiter

32W

16W

8W

PLB-to-OPB Bridge

OPB-to-PLB Bridge

Reserved

Power Management

Reserved

3W

UIC 0

16W

UIC 1

UIC 2

Reserved

DMA

64W

Reserved

Ethernet MAL

Reserved

128W

Notes:

1. A DCR address is 10 bits (1024 or 1K unique addresses). Each unique address represents a single 32-bit (word) register, or one kiloword

(KW) (which equals 4KB).

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Data Sheet

PowerPC 405 Processor

The PPC405 processor is a fixed-point, 32-bit RISC unit.

Features include:

• Five-stage pipeline with single-cycle execution of most instructions, including loads and stores

• Separate, configurable 16 KB D- and I-caches, both two-way set associative

• Thirty-two 32-bit general purpose registers (GPRs)

• Unaligned load/store support

• Hardware multiply/divide

• Parity detection and reporting for the instruction cache, data cache, and translation look-aside buffer (TLB)

• Double word instruction fetch from cache

• Translation of the four GB logical address space into physical addresses

• Built-in timer and debug support

• Power management

• DCR interface is 32 bits wide

• Selectable processor vs. bus clock ratios (N:1 ratio only, where N =1, 2, 3,or 4)

Internal Buses

The PPC405EX contains four internal buses: the processor local bus (PLB), the Advanced High-Performance Bus

(AHB), the on-chip peripheral bus (OPB), and the device control register (DCR) bus. High performance devices

such as the processor, the DDR SDRAM memory controller, PCI Express, the Ethernet MAL, and DMA utilize the

PLB. Lower bandwidth I/O interfaces such as communications and timer interfaces utilize the OPB. The daisy-

chained DCR bus provides a lower bandwidth path for passing status and control information between the

processor and the other on-chip peripheral functions.

PLB

The Processor Local Bus (PLB) is a high-performance on-chip bus used to connect PLB-equipped master and

slave devices to the PPC405 CPU. It provides a 128-bit data path with 64-bit addressing and operates up to

200MHz. There are bridges between the PLB and the OPB.

Features include:

• Separate and simultaneous 6.4GB/s read and write data paths

• Decoupled address and data buses

• Address pipelining

• Late master request abort capability

• Hidden (overlapped) bus request/grant protocol

• Bus arbitration-locking mechanism

• Byte-enable capability allows for unaligned half word transfers and 3-B transfers

• Support for 32- and 64-B burst transfers

• Read word address capability

• Sequential burst protocol

• Guarded and unguarded memory transfers

• Simultaneous control, address, and data phases

• DMA buffered, flyby, peripheral-to-memory, memory-to-peripheral, and DMA memory-to-memory operations

AHB

The Advanced High-Performance Bus (AHB) is dedicated to the USB OTG 2.0.

Features include:

• 32-bit data path

• 32-bit address

• Synchronous to the PLB

• From 60MHz to 100MHz.

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Data Sheet

OPB

The OPB provides 32-bit address and data interfaces, and operates up to 100MHz. There are bridges between the

OPB and the PLB.

Features include:

• Pipelined read support

• Dynamic bus sizing

• Single-cycle data transfer between masters and slaves

DCR Bus

The daisy-chained DCR bus provides a path for passing status and control information between the processor core

and the other on-chip cores. All DCRs are 32 bits in width with 10-bit addressing.

External Bus Controller

The external bus controller (EBC and EBM) transfers data between the PLB and external memory or peripheral

devices attached to the external peripheral bus. The EBC provides direct attachment of memory devices such as

ROM and SRAM, DMA device paced memory devices, and DMA peripheral devices.

Features include:

• From 33MHz to 100 MHz speed

• Data bus is 8, 16, or 32 bits with a 27-bit address bus

• Up to four chip selects

• Arbitration and multi-master supported

• Flash ROM interface

• Boot from 8- or 16-bit NOR Flash support

• Direct support for 8-,16-, or 32-bit SRAM and external peripherals

• External bus master support

NAND Flash Controller

The NAND Flash controller (NDFC) provides a simple interface between the External Bus Controller (EBC) and a

variety of NAND Flash-based storage devices.

Features include:

• Attachment as internal EBC slave device

• Eight- and 16-bit NAND Flash interface

• Up to four banks of NAND Flash supported

• Device sizes:

– 4MB and larger supported for read/write access

– 4MB to 256MB supported for boot-from-NAND flash (size supported depends on addressing mode)

• 512B + 16B or 2kB + 64B device page sizes supported

• ECC generation - hamming code, single-bit correction, double-bit detection (SEC/DED)

• Eight-bit command write, address write, and data read/write

• Interrupt on device ready (after long page write or block erase operations)

• Boot from NAND

– Executes up to 4KB of boot code out of first block

– Automatic page read accesses performed based on device configuration and read address

DMA Controller

The Direct Memory Access (DMA) controller is a Processor Local Bus (PLB) master that enables faster data

transfer between memory and peripherals than is possible under program control. The 4-channel DMA controller

handles data transfers between memory and peripherals and from memory-to-memory. Each channel has an

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Data Sheet

independent set of registers needed for data transfer: a control register, a source address register, a destination

address register, and a transfer count register.

Features include:

• Memory-to-memory transfers

• Buffered memory-to-peripheral transfers

• Buffered peripheral-to-memory transfers

• Four independent DMA channels

• Scatter/gather capability for dynamically programming multiple DMA transfers

• Programmable address increment or decrement

• Internal data buffering

• Can transfer data to/from any PLB slave, including the external bus

USB 2.0 OTG Interface

One USB 2.0 On-the-Go (OTG) controller that can be configured as either a Host or Device port.

Features include:

• Low- (Host only), Full- and High-Speed support

• Internal DMA to optimize performance and offload the CPU

• Up to two IN/OUT Endpoints in Device mode (one can be isochronous)

• Supports maximum packet size of 1024B (isochronous) and 512B (bulk)

• Support for isochronous traffic

• Three packets per microframe (24MB/s throughput)

• Eight KB buffer

• ULPI SDR interface

DDR1/2 SDRAM Controller

The Double Data Rate 1/2 (DDR1/2) SDRAM memory controller supports industry standard discrete devices that

are compatible with both the DDR1 or DDR2 specifications. The correct I/O supply voltage must be provided for the

two types of DDR devices: DDR1 devices require +2.5V and DDR2 devices require +1.8V.

Global memory timings, address and bank sizes, and memory addressing modes are programmable.

Features include:

• 16- or 32-bit memory interface

• Optional 8-bit error checking and correcting (ECC)

• 1.6-GB/s peak data rate

• Two memory banks of up to 1 GB each

• Maximum capacity of 2GB

• Support for one memory bank of 2GB with CAS latencies of 2, 2.5, or 3 for DDR1 interface, or 2, 3, 4, 5, 6, or 7

for DDR2 interface

• Clock frequencies from 133MHz (266Mbps) to 200MHz (400Mbps) supported

(Faster parts may be used, but must be clocked no faster than 200MHz)

• Page mode accesses (up to 16 open pages) with configurable paging policy

• Programmable address mapping and timing

• Software initiated self-refresh

• Power management (self-refresh, suspend)

• Two regions (two chip selects, one clock driver)

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Data Sheet

PCI Express

The PCI Express single-lane interfaces include the following features:

Features include:

• Compliant with PCI Express base specification 1.1

• Each PCI Express port can be End Point or Root Complex. (Upstream & Downstream)

– Applications compliant with MSI rules are limited to one End Point port per PPC405EX

• PCI-Express to PCI-Express opaque (Non-Transparent) bridge

• Power Management

• Supports one virtual channel (VC0) with no Traffic Class (TC) filtering

• Maximum Payload block size 256B

• Supports up to 512B maximum Read request size

• Requests supported:

– Up to two posted outbound Write requests (memory and messages)

– Up to two posted inbound Write requests

– Up to two outbound Read requests outstanding on PCI Express

– Up to two inbound Read requests outstanding on PCI Express

– Outbound I/O request as a PCI Express Root Port

– Inbound I/O request as a PCI Express End Point

• Buffering in each PCI Express Port for the following transaction types:

– 1KB Replay buffer: up to eight in flight transactions

– 512B for Outbound posted Writes

– 512B for Outbound Reads completion

– 512B for Inbound posted Writes

– 512B for Inbound Reads completion

• Parity checking on each buffer

• Programmable Outbound Memory (POM) Regions: 3 memory, 1 I/O, 1 message, 1 configuration, 1 internal

register

• Programmable Inbound Memory (PIM) Regions: 4 memory, 1 I/O, 1 expansion ROM

• INTx Interrupts support (PCI legacy):

– Up to four INTx Termination for Root Ports. A/B/C/D interrupts are wired to the UIC

– A/B/C/D INTx types Generation for Endpoints

• MSI - Message Signaled Interrupts

– MSI Generation for End Point

– MSI Termination for Root Ports

– MSI_X Termination for Root Ports

Security Function (optional)

The optional built-in security function is a cryptographic engine attached to the 128-bit PLB with built-in DMA and

interrupt controllers.

Features include:

• Federal Information Processing Standard (FIPS) 140-2 design

• Support for an unlimited number of Security Associations (SA)

• Different SA formats for each supported protocol (IPsec, SSL/TLS/DTLS, MACSec, SGT L2/L3 and sRTP)

• Internet Protocol Security (IPSec) features

– Full packet transforms (ESP & AH)

– Complete header and trailer processing (IPv4 and IPv6)

– Multi-mode automatic padding

– "Mutable bit" handler for AH, including IPv4 option and IPv6 extension headers

• Secure Socket Layer (SSL), Transport Layer Security (TLS), and Datagram Transport Layer Security (DTLS)

– Packet transforms

– One-pass hash-then-encrypt or decrypt-then-hash for SSL, TLS and DTLS packet transforms using ARC4

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Data Sheet

Stream Cipher

• Secure Real-Time Protocol (sRTP) features

– Packet transforms

– ROC removal and TAG insertion

– Variable bypass offset of header length per packet

• Media Access Control Security (MACSec) features

– Cipher suite GCM-AES-128

– Header insertion and removal

– Integrity and confidentiality with MSDU

• SGT L2 supported features:

– GCM-AES with 128-bit key.

– Integrity only and with confidentiality of MSDU

• ICV generation and validation SGT L3 supported features

– AES-GCM, AES-GMAC with 128, 192 and 256 bit key.

• IPsec/SSL security acceleration engine

• DES, 3DES, AES, ARC-4, AES-GCM, and GMAC-AES encryption/decryption

• MD-5, SHA-1, and SHA-256 hashing

• Public key acceleration for RSA, DSA and Diffie-Hellman

• Combined encryption-hash and hash-decryption with the AES-CCM algorithm.

• True or pseudo random number generators

– Non-deterministic true random numbers

– Pseudo random numbers with lengths of 8B or 16B

– ANSI X9.17 Annex C compliant using a DES algorithm

• Interrupt controller

– Fifteen programmable, maskable interrupts

– Initiate commands via an input interrupt

– Sixteen programmable interrupts indicating completion of certain operations

– All interrupts mapped to one level- or edge-sensitive programmable interrupt output

• DMA controller

– Autonomous, 4-channel

– 1024-words (32 bits/word) per DMA transfer

– Scatter/gather capability with byte aligned addressing

– Byte reverse capability on SA and descriptors

UART

The Universal Asynchronous Receiver/Transmitter (UART) interface provides four configurations:

• One 8-signal port

• Two 4-signal ports.

• Two 2-signal ports

• One 4-signal port and one 2-signal port

The UART performs serial-to-parallel conversion on data received from a peripheral device or a modem, and

parallel-to-serial conversion on data received from the processor.

Features include:

• Compatible with the16750

• All six software modem control functions (CTS, RTS, DSR, DTR, RI, DCD) on UART0

• Programmable auto flow (data flow controlled by RTS and CTS signals)

• Characters can be 5, 6, 7, or 8 bits

• Programmable start, stop, parity bit insertion

• Sixty-four byte FIFOs for buffering Tx and Rx data

• LIN sub-bus specification compliant - line break generation/detection and false start bit detection

• Programmable internal/external loopback capabilities

• Low Power and Sleep mode

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Data Sheet

• Register conformance (after reset) to configuration of the NS16450 register set

• Hold and shift registers (eliminate need for precise synchronization between processor and serial data in

character mode)

• Complete status reporting

• Full prioritized interrupt system controls

• Independently controlled transmit, receive, line status, and data set interrupts

• Programmable baud generator (divides serial clock input and generates 16x clock)

• Ability to add/delete standard asynchronous communication bits such as start, stop, and parity to/from serial

data

• Even, odd, or no-parity bit generation and detection

• Stop bit generation of 1, 1.5, or 2 bits

• Variable baud rate

• Internal diagnostic capability

• Loopback controls for isolating communications link faults

• Break, parity, overrun, framing error simulation

• OPB interface with optional DMA support

IIC Bus Interface

®

The Inter-Integrated Circuit (IIC) interface provides a Philips I²C compatible interface operating up to 400kHz

either as a master, a slave, or both with a bootstrap controller (BSC) included. During chip reset, the bootstrap

controller can read configuration data from an IIC compatible memory device (e.g., EEPROM). This data can be

used to replace the default configuration settings provided by the chip.

Features include:

• Two IIC channels

• Compliant with Philips Semiconductors I²C Specification, dated 1995

• Operation at 100kHz or 400kHz

• Byte (8-bit) data

• Addresses are 10 or 7 bits

• Slave Transmit and Receive

• Master Transmit and Receive

• Multiple bus masters supported

• Programmable as master, slave, or master/slave

• Boot parameters read from IIC attached memory (Port 0) with IIC bootstrap controller (BSC)

• OPB slave interface is 32 bits wide

Serial Communication Port Interface (SCP/SPI)

The Serial Communication Port (SCP) (also known as the Serial Peripheral Interface or SPI) is a full-duplex,

synchronous, character-oriented (byte) port that allows the exchange of data with other serial devices. The SCP is

a master on the serial port supporting a three-wire interface (receive, transmit, and clock), and is a slave on the

OPB.

Features include:

• One SCP channel, full duplex synchronous

• SCP master

• Up to 25MHz

• Programmable internal loopback capabilities

• Multi-master protocol supported

• Independent masking of all interrupts (master collision, transmit FIFO overflow, transmit FIFO empty, receive

FIFO full, receive FIFO underflow, receive FIFO overflow)

• Dynamic control of serial bit rate of data transfer (serial-master mode only)

• Data Item size for each data transfer under programmer control (4-to-16 bits)

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Data Sheet

• OPB slave interface is 32 bits wide

General Purpose I/O (GPIO) Controller

The GPIO controller enables multiplexing of module I/O pins with multiple functions within the chip. That is, a single

package pin can be assigned to multiple I/O functions. Which function the pin is assigned to is determined by

register bit settings controlled by software. This significantly reduces the number of package pins needed to

support multiple I/O groups.

Features include:

• Up to 32 GPIOs available

– GPIOs are multiplexed with alternate functions

– If not in use for dedicated functions, I/Os are available as GPIOs

• Direct control of all functions from registers programmed by means of OPB bus master accesses

• Time multiplexing of controller outputs to module outputs

• Programmable conversion of module outputs to open-drain outputs (enables sharing of active low outputs

externally)

• Time multiplexing of module inputs to controller inputs

Universal Interrupt Controller (UIC)

The Universal Interrupt Controller (UIC) provides the control, status, and communications necessary between the

various sources of interrupts and the PPC405 processor.

Features include:

• Ten external interrupt sources supported

• Generate interrupt on level (high or low) or edge (rising or falling)

• Programmable as synchronous (edge-capture or level-sensitive) or asynchronous (edge- or level-sensitive

triggering)

• Each interrupt source/bit programmable as critical or non critical

• DCR bus interface is 32 bits wide

• Optional interrupt handler vector generation

– Programmable vector base address

– Programmable vector offset size

– Programmable interrupt priority ordering

• Programmable polarity for all interrupt types

• Interrupts of the same type do not need to be in contiguous bit positions

• Status registers provide: current state of all interrupts, current state of enabled interrupts

Ethernet Controller

The Ethernet support provides two 10/100/1000 Mbps interfaces (GMII/MII/RGMII).

Features include:

• ANSI/IEEE Std. 802.3 and IEEE 802.3u supplement compliant

• Half-duplex and full-duplex support for the following:

– One Gigabit Media Independent Interface (GMII)

– One Media Independent Interface (MII)

– Two Reduced GMII interfaces (RGMII)

• Receive and transmit FIFOs are 16K bytes each with programmable thresholds

• FCS control for transmit/receive packets

• Multiple packet handling in transmit and receive FIFOs

• Unicast, multicast, broadcast, and promiscuous address filtering

• Two 256-bit hash filters for unicast and multicast frames

• Automatic retransmission of collided frames

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Data Sheet

• Runt frame rejection

• Programmable inter-frame gap

• IEEE 802.3x compliant for frame-based flow control mechanism, including self-assembled control frame

transmitting)

• Wake-on-LAN and Power-over-Internet supported

• Programmable internal/external loopback capabilities

• OPB slave (MAC) and PLB master (MAL) interfaces for control and configuration are 32 bits wide

• MAL has 128-bit PLB master interface for data path.

• Extensive error/status vector generation for each processed packet

• VLAN tag ID supported (according to IEEE Draft 802.3ac/D1.0 standard)

• Programmable automatic source address inclusion/replacement for transmit packets

• Programmable automatic Pad/FCS stripping for receive packets

• Programmable VLAN Tag inclusion/replacement for transmit packets

• Half- or full-duplex GMII/RGMII

• Jumbo frames support

• Memory Access Layer (MAL) provides DMA capability to Ethernet channel

• Interrupt coalescence support for two transmit and two receive channels

General Purpose Timer (GPT)

The GPT provides a time base counter and system timers in addition to those defined in the processor.

Features include:

• 32-bit time base counter driven by the OPB clock

• Seven 32-bit compare timers

JTAG

Features include:

• IEEE 1149.1 test access port

• JTAG Boundary Scan Description Language (BSDL)

Refer to http://www.amcc.com/Embedded/Partners for a list of AMCC partners supplying probes for use with the

JTAG interface.

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Data Sheet

Figure 2. Package 27mm, 388-Ball EPBGA

Gold Gate Release

Corresponds to

A01 Ball Location

Top View

Logo View

®

PPC405EX

Part Number

Lot Number

1YWWBZZZZZ

PCB

Substrate

Side View

Epoxy Mold

Compound

2.65 max

0.56 REF

0.5 ± 0.1

C

Seating plane

27.0 ± 0.2

25.0 REF

Bottom View

AF

1.0 Basic

AE

AC

AD

AB

Y

AA

W

U

R

N

L

V

T

27.0

P

M

K

J

H

F

G

E

D

B

Notes: 1. All dimensions are in mm.

C

A

2. Package conforms to JEDEC MS-034C

3. Package available in leaded or lead-free versions

19 21 23 25

01 03 05 07 09 11 13 15 17

08 10

06

12 14

26

22 24

04

16 18

02

20

0.60 ± 0.1 SOLDERBALL x 388

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Signal Lists

Data Sheet

The following table lists all the external signals in alphabetical order and shows the ball (pin) number on which the

signal appears. Shared signals are shown with the default signal (following reset) not in brackets and the alternate

signal in brackets. Signals that have different functions for different modes with the same function are separated by

commas.

Shared signals appear alphabetically multiple times in the list—once for each signal name on the ball. The Page

column indicates the page within the table “Signal Functional Description” on page 39 on which the signals in the

indicated interface group begin.

Table 3. Signals Listed Alphabetically (Sheet 1 of 13)

Signal Name

Ball

K01

Interface Group

Page

AGND

AHV_DD

L04

P04

R01

M04

Power

45

AHV_DD

AV_DD

R04

J03

K04

M01

N03

N04

P01

Power

T01

BA0

AD22

AF24

AE24

AF21

AE20

B03

BA1

DDR 1/2 SDRAM

43

BA2

BankSel0

BankSel1

[BusReq]GPIO27[DMAEOT3][IRQ5]

CAS

External Bus Master

DDR 1/2 SDRAM

42

43

AF20

M25

T26

DM0

DM1

DM2

AD16

AD13

Y26

DDR 1/2 SDRAM

43

DM3

DM4

[DMAAck0]PerAddr07[TS1]

[DMAAck1]GPIO31[IRQ0]

[DMAAck2]GPIO22[HoldReq]

[DMAAck3]GPIO25[ExtAck][IRQ3]

[DMAEOT0]GPIO26[PerAddr05][TS3]

[DMAEOT1]GPIO29[IRQ2]

[DMAEOT2]GPIO24[ExtReq][IRQ4]

[DMAEOT3]GPIO27[BusReq][IRQ5]

[DMAReq0]PerAddr06[TS2]

[DMAReq1]GPIO30[IRQ1]

[DMAReq2]GPIO23[HoldAck]

[DMAReq3]PerAddr08[TS0]

J26

D01

B05

DMA

42

C04

K26

D03

A03

B03

K25

D02

C05

J25

42

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Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 2 of 13)

Signal Name

Ball

M26

Interface Group

Page

DQS0

DQS1

DQS2

DQS3

DQS4

EAGND

EAV_DD

T25

AE16

AE12

Y25

DDR 1/2 SDRAM

43

AE07

AE08

V24

Power

45

43

ECC0

ECC1

ECC2

ECC3

ECC4

ECC5

ECC6

ECC7

EOV_DD

W24

AB26

AB25

V25

DDR 1/2 SDRAM

W25

AA26

AA25

D12

EOV_DD

T12

AC05

AB04

AC07

Power

45

42

AC08

C04

A03

[ExtAck]GPIO25[DMAAck3][IRQ3]

[ExtReq]GPIO24[DMAEOT2][IRQ4]

ExtReset

External Bus Master

B19

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Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 3 of 13)

Signal Name

Ball

AD04

AF04

AE04

AE03

AF02

AD07

AD09

AC11

AE10

AD10

AF09

AE09

AF07

AF06

AE06

AE05

AF05

AC06

AE01

AD02

AD01

AC03

AC02

AC01

AB03

AB02

AD05

AF03

Interface Group

Page

GMCCD, GMC1RxClk

GMCCrS, GMC1TxClk

GMCGTxClk, GMC0TxClk

GMCMDClk

GMCMDIO

GMCRefClk

GMCRxClk, GMC0RxClk

GMCRxD0, GMC0RxD0

GMCRxD1, GMC0RxD1

GMCRxD2, GMC0RxD2

GMCRxD3, GMC0RxD3

GMCRxD4, GMC1RxD0

GMCRxD5, GMC1RxD1

GMCRxD6, GMC1RxD2

GMCRxD7, GMC1RxD3

GMCRxDV, GMC0RxCtl

GMCRxEr, GMC1RxCtl

GMCTxClk

Ethernet

39

GMCTxD0, GMC0TxD0

GMCTxD1, GMC0TxD1

GMCTxD2, GMC0TxD2

GMCTxD3, GMC0TxD3

GMCTxD4, GMC1TxD0

GMCTxD5, GMC1TxD1

GMCTxD6, GMC1TxD2

GMCTxD7, GMC1TxD3

GMCTxEn, GMC0TxCtl

GMCTxEr, GMC1TxCtl

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Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 4 of 13)

Signal Name

Ball

A01

Interface Group

Page

GND

A08

A13

A19

A26

B01

B02

B25

C01

C02

C03

C24

D04

D09

D14

D18

D23

E01

E03

H01

H26

J04

Power

45

J23

K24

L11

L13

L16

M12

M13

M14

M15

N12

N13

N14

N15

N16

N26

P11

P12

P13

P14

P15

P23

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Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 5 of 13)

Signal Name

Ball

R12

Interface Group

Page

GND

R13

R14

R15

T11

T14

T16

U01

U02

V04

V23

W01

W26

AB01

AC04

AC09

AC13

AC18

AC23

AD03

AD24

AE02

AE25

AF01

AF08

AF14

AF19

AF26

Power

45

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Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 6 of 13)

Signal Name

Ball

A16

Interface Group

Page

GPIO00[PerDataPar0]

GPIO01[PerDataPar1]

GPIO02[PerDataPar2]

GPIO03[PerDataPar3]

B12

C09

B04

C13

B09

C12

D11

C20

A21

B20

H03

C11

B08

A10

B10

F04

F02

G02

G01

F03

F01

B05

C05

A03

C04

K26

B03

U03

D03

D02

D01

A02

C05

B05

AA01

Y03

AA04

AA02

GPIO04[PerData20][USB2Data4]

GPIO05[PerData21][USB2Data5]

GPIO06[PerData22][USB2Data6]

GPIO07[PerData23][USB2Data7]

GPIO08[PerCS1][NFCE1][IRQ7]

GPIO09[PerCS2][NFCE2][IRQ8]

GPIO10[PerCS3][NFCE3][IRQ9]

GPIO11[IRQ6]

GPIO12[PerData16][USB2Data0]

GPIO13[PerData17][USB2Data1]

GPIO14[PerData18][USB2Data2]

GPIO15[PerData19][USB2Data3]

GPIO16[UART0DCD][UART1CTS]

GPIO17[UART0DSR][UART1RTS]

GPIO18[UART0CTS]

System

41

GPIO19[UART0RTS]

GPIO20[UART0DTR][UART1Tx]

GPIO21[UART0RI][UART1Rx]

GPIO22[HoldReq][DMAAck2]

GPIO23[HoldAck][DMAReq2]

GPIO24[ExtReq][DMAEOT2][IRQ4]

GPIO25[ExtAck][DMAAck3][IRQ3]

GPIO26[PerAddr05][DMAEOT0][TS3]

GPIO27[BusReq][DMAEOT3][IRQ5]

GPIO28

GPIO29[DMAEOT1][IRQ2]

GPIO30[DMAReq1][IRQ1]

GPIO31[DMAAck1][IRQ0]

Halt

System

41

42

[HoldAck]GPIO23[DMAReq2]

[HoldReq]GPIO22[DMAAck2]

IIC0SData

External Bus Master

IIC0SClk

IIC

39

IIC1SData[SCPDO]

IIC1SClk[SCPClkOut]

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PPC405EX – PowerPC 405EX Embedded Processor

Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 7 of 13)

Signal Name

Ball

D01

Interface Group

Page

[IRQ0]GPIO31[DMAAck1]

[IRQ1]GPIO30[DMAReq1]

D02

[IRQ2]GPIO29[DMAEOT1]

[IRQ3]GPIO25[ExtAck][DMAAck3]

[IRQ4]GPIO24[ExtReq][DMAEOT2]

[IRQ5]GPIO27[BusReq][DMAEOT3]

[IRQ6]GPIO11

D03

C04

A03

Interrupts

40

B03

H03

[IRQ7][PerCS1][NFCE1]GPIO08

[IRQ8][PerCS2][NFCE2]GPIO09

[IRQ9][PerCS3][NFCE3]GPIO10

MemAddr00

C20

A21

B20

AE21

AD20

AF22

AE22

AF23

AD21

AC21

AE23

AE26

AD25

AD26

AC24

AB24

AC25

AC26

Y24

MemAddr01

MemAddr02

MemAddr03

MemAddr04

MemAddr05

MemAddr06

MemAddr07

DDR1/2 SDRAM

43

MemAddr08

MemAddr09

MemAddr10

MemAddr11

MemAddr12

MemAddr13

MemAddr14

MemClkEn

MemClkOut0

AA23

AA24

DDR1/2 SDRAM

43

MemClkOut0

24

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Revision 1.23 - January 28, 2009

PPC405EX – PowerPC 405EX Embedded Processor

Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 8 of 13)

Signal Name

Ball

M24

Interface Group

Page

MemData00

MemData01

MemData02

MemData03

MemData04

MemData05

MemData06

MemData07

MemData08

MemData09

MemData10

MemData11

MemData12

MemData13

MemData14

MemData15

MemData16

MemData17

MemData18

MemData19

MemData20

MemData21

MemData22

MemData23

MemData24

MemData25

MemData26

MemData27

MemData28

MemData29

MemData30

MemData31

MemFBD

N24

P25

P24

L25

L26

N25

P26

R24

T24

V26

U24

R25

R26

U26

U25

DDR1/2 SDRAM

43

AE17

AF17

AE15

AF15

AF18

AD17

AF16

AD15

AE13

AF12

AF10

AD11

AE14

AF13

AF11

AE11

AD23

AF25

AD18

AE18

MemFBR

DDR1/2 SDRAM

43

MemODT0

MemODT1

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PPC405EX – PowerPC 405EX Embedded Processor

Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 9 of 13)

Signal Name

Ball

C06

Interface Group

Page

[NFALE]PerData30

[NFCE0]PerCS0

B21

C20

A21

B20

A06

C18

B18

C17

A18

D16

B17

C16

B16

A17

B15

C15

A15

B14

A14

C14

B13

A04

A05

C08

D05

[NFCE1][PerCS1]GPIO08[IRQ7]

[NFCE2][PerCS2]GPIO09[IRQ8]

[NFCE3][PerCS3]GPIO10[IRQ9]

[NFCLE]PerData29

[NFData00]PerData00

[NFData01]PerData01

[NFData02]PerData02

[NFData03]PerData03

[NFData04]PerData04

[NFData05]PerData05

[NFData06]PerData06

[NFData07]PerData07

[NFData08]PerData08

[NFData09]PerData09

[NFData10]PerData10

[NFData11]PerData11

[NFData12]PerData12

[NFData13]PerData13

[NFData14]PerData14

[NFData15]PerData15

[NFRdyBusy]PerData31

[NFREn]PerData27

NAND Flash

43

[NFWEn]PerData28

OV_DD

D07

D08

D13

D19

D20

D22

E04

E23

G04

G23

H23

L12

Power

45

L15

M11

M16

R11

V03

W04

Y04

26

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Revision 1.23 - January 28, 2009

PPC405EX – PowerPC 405EX Embedded Processor

Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 10 of 13)

Signal Name

Ball

L03

Interface Group

Page

PCIE0ATB

PCIE0ClkC

PCIE0ClkT

PCIE0RExt

PCIE0RExtG

PCIE0Rx

L01

L02

M03

M02

J01

PCI Express 0

40

PCIE0Rx

J02

PCIE0Tx

K02

K03

R02

T02

R03

T03

T04

N01

N02

P02

P03

K26

K25

J26

PCIE0Tx

PCIE1ATB

PCIE1ClkC

PCIE1ClkT

PCIE1RExt

PCIE1RExtG

PCIE1Rx

PCI Express 1

40

PCIE1Rx

PCIE1Tx

[PerAddr05]GPIO26[TS3][DMAEOT0]

PerAddr06[DMAReq0][TS2]

PerAddr07[DMAAck0][TS1]

PerAddr08[DMAReq3][TS0]

PerAddr09[TS1E]

PerAddr10[TS0E]

PerAddr11[TS1O]

PerAddr12[TS0O]

PerAddr13

J25

H25

J24

G26

H24

G25

F26

E26

F25

G24

E25

D26

F24

C26

D25

F23

E24

C25

D24

B26

A25

B24

C23

C22

D21

A20

PerAddr14

PerAddr15

PerAddr16

PerAddr17

PerAddr18

External Peripheral

42

PerAddr19

PerAddr20

PerAddr21

PerAddr22

PerAddr23

PerAddr24

PerAddr25

PerAddr26

PerAddr27

PerAddr28

PerAddr29

PerAddr30

PerAddr31

PerBLast

External Peripheral

42

PerClk

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PPC405EX – PowerPC 405EX Embedded Processor

Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 11 of 13)

Signal Name

Ball

B21

Interface Group

Page

PerCS0[NFCE0]

[PerCS1][NFCE1]GPIO08[IRQ7]

[PerCS2][NFCE2]GPIO09[IRQ8]

[PerCS3][NFCE3]GPIO10[IRQ9]

PerData00[NFData00]

PerData01[NFData01]

PerData02[NFData02]

PerData03[NFData03]

PerData04[NFData04]

PerData05[NFData05]

PerData06[NFData06]

PerData07[NFData07]

PerData08[NFData08]

PerData09[NFData09]

PerData10[NFData10]

PerData11[NFData11]

PerData12[NFData12]

PerData13[NFData13]

PerData14[NFData14]

PerData15[NFData15]

[PerData16]GPIO12[USB2Data0]

[PerData17]GPIO13[USB2Data1]

[PerData18]GPIO14[USB2Data2]

[PerData19]GPIO15[USB2Data3]

[PerData20]GPIO04[USB2Data4]

[PerData21]GPIO05[USB2Data5]

[PerData22]GPIO06[USB2Data6]

[PerData23]GPIO07[USB2Data7]

PerData24[USB2Dir]

PerData25[USB2Stop]

PerData26[USB2Next]

PerData27[NFREn]

C20

A21

B20

C18

B18

C17

A18

D16

B17

C16

B16

A17

B15

C15

A15

B14

A14

C14

B13

C11

B08

A10

B10

C13

B09

C12

D11

A07

B07

B06

A05

C08

A06

C06

A04

A16

B12

C09

B04

C19

A24

B11

B23

A23

C21

B22

A22

External Peripheral

42

External Peripheral

42

PerData28[NFWEn]

PerData29[NFCLE]

PerData30[NFALE]

PerData31[NFRdyBusy]

[PerDataPar0]GPIO00

[PerDataPar1]GPIO01

[PerDataPar2]GPIO02

[PerDataPar3]GPIO03

PerErr

External Peripheral

42

PerOE

PerReady

PerRW

PerWBE0

PerWBE1

42

PerWBE2

PerWBE3

28

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PPC405EX – PowerPC 405EX Embedded Processor

Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 12 of 13)

Signal Name

Ball

A09

Interface Group

Page

41

PSROUser

RAS

System

AD19

AD12

A11

DDR 1/2 SDRAM

Other

43

Reserved

SAGND

SAV_DD

45

Power

45

A12

[SCPClkOut]IIC1SClk

SCPDI

AA02

AA03

AA04

N23

Serial Communication Port

44

[SCPDO]IIC1SData

SV_DD

R16

T15

W23

Y23

Power

45

AB23

AC19

AC20

AC22

AD14

AC14

T23

S

_VREF1A

_VREF1B

_VREF2A

_VREF2B

DDR1/2 SDRAM

System

43

41

AC16

L23

SysClk

SysErr

SysReset

TCK

C10

AD06

AD08

V02

W02

W03

Y02

D06

V01

L24

TDI

JTAG

40

41

TDO

TestEn

TmrClk

TMS

System

JTAG

Trace

JTAG

40

41

40

TrcClk

TRST

Y01

J25

[TS0]PerAddr08[DMAReq3]

[TS1]PerAddr07[DMAAck0]

[TS2]PerAddr06[DMAReq0]

[TS3]GPIO26[PerAddr05][DMAEOT0]

[TS0E]PerAddr10

J26

Trace

41

K25

K26

J24

[TS0O]PerAddr12

H24

H25

G26

[TS1E]PerAddr09

[TS1O]PerAddr11

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PPC405EX – PowerPC 405EX Embedded Processor

Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 13 of 13)

Signal Name

Ball

G02

Interface Group

Page

[UART0CTS]GPIO18

[UART0DCD]GPIO16[UART1CTS]

[UART0DSR]GPIO17[UART1RTS]

[UART0DTR]GPIO20[UART1Tx]

[UART0RI]GPIO21[UART1Rx]

[UART0RTS]GPIO19

F04

F02

F03

F01

G01

G03

H02

F04

F02

F01

F03

E02

C07

C11

B08

A10

B10

C13

B09

C12

D11

A07

B06

B07

D10

UART Peripheral

44

UART0Rx

UART0Tx

[UART1CTS]GPIO16[UART0DCD]

[UART1RTS]GPIO17[UART0DSR]

[UART1Rx]GPIO21[UART0RI]

[UART1Tx]GPIO20[UART0DTR]

UARTSerClk

UART Peripheral

44

UART Peripheral

USB 2.0

44

USB2Clk

[USB2Data0]GPIO12[PerData16]

[USB2Data1]GPIO13[PerData17]

[USB2Data2]GPIO14[PerData18]

[USB2Data3]GPIO15[PerData19]

[USB2Data4]GPIO04[PerData20]

[USB2Data5]GPIO05[PerData21]

[USB2Data6]GPIO06[PerData22]

[USB2Data7]GPIO07[PerData23]

[USB2Dir]PerData24

USB 2.0

44

[USB2Next]PerData26

[USB2Stop]PerData25

V_DD

WE

D15

D17

H04

K23

L14

M23

N11

P16

Power

45

R23

T13

U04

U23

AC10

AC12

AC15

AC17

AE19

DDR1/2 SDRAM

43

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AMCC Proprietary

Revision 1.23 - January 28, 2009

PPC405EX – PowerPC 405EX Embedded Processor

Data Sheet

In the following table, only the default signal name is shown for each ball. Shared balls are marked with an asterisk

(*). To determine what signals or functions are shared on those balls, look up the default signal name in “Signals

Listed Alphabetically” on page 18. The following table lists the signals by ball assignment.

Table 4. Signals Listed by Ball Assignment (Sheet 1 of 7)

Ball

A01

Signal Name

Ball

B01

Signal Name

Ball

C01

Signal Name

Ball

D01

Signal Name

GPIO31 *

GND

Halt

GND

A02

A03

A04

A05

A06

A07

B02

B03

B04

B05

B06

B07

C02

C03

C04

C05

C06

C07

D02

D03

D04

D05

D06

D07

GPIO30 *

GPIO29 *

GND

GPIO24 *

GPIO27 *

PerData31 *

PerData27 *

PerData29 *

PerData24 *

GPIO03 *

GPIO25 *

GPIO23 *

PerData30 *

USB2Clk

OV_DD

GPIO22 *

PerData26 *

PerData25 *

TmrClk

OV_DD

A08

A09

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

GND

B08

B09

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

GPIO13 *

C08

C09

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

PerData28 *

GPIO02 *

SysClk

D08

D09

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

PSROUser

GPIO14 *

SAGND

SAV_DD

GPIO05 *

GND

V_DD

GPIO15 *

PerReady

GPIO01 *

GPIO12 *

GPIO06 *

GPIO04 *

PerData14 *

PerData10 *

PerData06 *

PerData02 *

PerData00 *

PerErr

GPIO07 *

EOV_DD

OV_DD

GND

PerData15 *

PerData12 *

PerData09 *

PerData07 *

PerData05 *

PerData01 *

ExtReset

PerData13 *

PerData11 *

GPIO00 *

PerData08 *

PerData03 *

GND

V_DD

PerData04 *

V_DD

GND

OV_DD

A20

A21

A22

A23

A24

A25

A26

PerClk

B20

B21

B22

B23

B24

B25

B26

GPIO10 *

PerCS0 *

PerWBE2

PerRW

C20

C21

C22

C23

C24

C25

C26

GPIO08 *

PerWBE1

PerAddr31

PerAddr30

GND

D20

D21

D22

D23

D24

D25

D26

GPIO09 *

PerWBE3

PerWBE0

PerOE

PerBLast

OV_DD

GND

PerAddr29

GND

PerAddr26

PerAddr22

PerAddr19

PerAddr28

GND

PerAddr25

PerAddr21

PerAddr27

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PPC405EX – PowerPC 405EX Embedded Processor

Data Sheet

Table 4. Signals Listed by Ball Assignment (Sheet 2 of 7)

Ball

E01

Signal Name

Ball

F01

Signal Name

GPIO21 *

Ball

G01

Signal Name

GPIO19 *

Ball

H01

Signal Name

GND

E02

E03

E04

E05

E06

E07

E08

E09

E10

E11

E12

E13

E14

E15

E16

E17

E18

E19

E20

E21

E22

E23

E24

E25

E26

UARTSerClk

GND

F02

F03

F04

F05

F06

F07

F08

F09

F10

F11

F12

F13

F14

F15

F16

F17

F18

F19

F20

F21

F22

F23

F24

F25

F26

GPIO17 *

GPIO20 *

GPIO16 *

No ball

G02

G03

G04

G05

G06

G07

G08

G09

G10

G11

G12

G13

G14

G15

G16

G17

G18

G19

G20

G21

G22

G23

G24

G25

G26

GPIO18 *

UART0Rx *

OV_DD

H02

H03

H04

H05

H06

H07

H08

H09

H10

H11

H12

H13

H14

H15

H16

H17

H18

H19

H20

H21

H22

H23

H24

H25

H26

UART0Tx *

GPIO11 *

V_DD

OV_DD

No ball

OV_DD

No ball

OV_DD

No ball

OV_DD

No ball

PerAddr23

PerAddr20

PerAddr16

PerAddr14

PerAddr24

PerAddr18

PerAddr15

PerAddr17

PerAddr13

PerAddr11 *

PerAddr12 *

PerAddr09 *

GND

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PPC405EX – PowerPC 405EX Embedded Processor

Data Sheet

Table 4. Signals Listed by Ball Assignment (Sheet 3 of 7)

Ball

J01

Signal Name

PCIE0Rx

Ball

K01

Signal Name

AGND

Ball

L01

Signal Name

PCIE0ClkC

Ball

M01

Signal Name

AV_DD

J02

J03

PCIE0Rx

AV_DD

K02

K03

PCIE0Tx

AV_DD

L02

L03

PCIE0ClkT

PCIE0ATB

M02

M03

PCIE0RExtG

PCIE0RExt

AHV_DD

J04

J05

J06

J07

J08

J09

J10

J11

GND

K04

K05

K06

K07

K08

K09

K10

K11

L04

L05

L06

L07

L08

L09

L10

L11

AGND

No ball

GND

M04

M05

M06

M07

M08

M09

M10

M11

No ball

OV_DD

J12

J13

J14

J15

No ball

K12

K13

K14

K15

No ball

L12

L13

L14

L15

M12

M13

M14

M15

GND

OV_DD

GND

V_DD

OV_DD

J16

J17

J18

J19

J20

J21

J22

J23

J24

J25

J26

No ball

K16

K17

K18

K19

K20

K21

K22

K23

K24

K25

K26

No ball

V_DD

L16

L17

L18

L19

L20

L21

L22

L23

L24

L25

L26

GND

M16

M17

M18

M19

M20

M21

M22

M23

M24

M25

M26

No ball

S_VREF2B

No ball

V_DD

No ball

GND

PerAddr10 *

PerAddr08 *

PerAddr07 *

GND

TrcClk

MemData00

DM0

PerAddr06 *

GPIO26 *

MemData04

MemData05

DQS0

AMCC Proprietary

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PPC405EX – PowerPC 405EX Embedded Processor

Data Sheet

Table 4. Signals Listed by Ball Assignment (Sheet 4 of 7)

Ball

N01

Signal Name

PCIE1Rx

Ball

P01

Signal Name

AV_DD

Ball

R01

Signal Name

AGND

Ball

T01

Signal Name

AV_DD

N02

N03

PCIE1Rx

AV_DD

P02

P03

PCIE1Tx

R02

R03

PCIE1ATB

PCIE1ClkT

AHV_DD

T02

T03

PCIE1ClkC

PCIE1RExt

AV_DD

N04

N05

N06

N07

N08

N09

N10

N11

P04

P05

P06

P07

P08

P09

P10

P11

AGND

No ball

GND

R04

R05

R06

R07

R08

R09

R10

R11

T04

T05

T06

T07

T08

T09

T10

T11

PCIE1RExtG

No ball

GND

No ball

V_DD

No ball

OV_DD

EOV_DD

N12

N13

N14

N15

GND

P12

P13

P14

P15

GND

V_DD

R12

R13

R14

R15

GND

SV_DD

T12

T13

T14

T15

V_DD

GND

SV_DD

N16

N17

N18

N19

N20

N21

N22

N23

N24

N25

N26

GND

P16

P17

P18

P19

P20

P21

P22

P23

P24

P25

P26

R16

R17

R18

R19

R20

R21

R22

R23

R24

R25

R26

T16

T17

T18

T19

T20

T21

T22

T23

T24

T25

T26

GND

No ball

SV_DD

No ball

V_DD

No ball

S_VREF1B

No ball

GND

MemData01

MemData06

GND

MemData03

MemData02

MemData07

MemData08

MemData12

MemData13

MemData09

DQS1

DM1

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PPC405EX – PowerPC 405EX Embedded Processor

Data Sheet

Table 4. Signals Listed by Ball Assignment (Sheet 5 of 7)

Ball

U01

Signal Name

Ball

V01

Signal Name

Ball

W01

W02

W03

Signal Name

Ball

Y01

Signal Name

TRST

GND

TMS

TCK

GND

TDI

U02

U03

V02

V03

Y02

Y03

TestEn

IIC0SClk

OV_DD

GPIO28

V_DD

TDO

OV_DD

U04

U05

U06

U07

U08

U09

U10

U11

U12

U13

U14

U15

U16

U17

U18

U19

U20

U21

U22

U23

U24

U25

U26

V04

V05

V06

V07

V08

V09

V10

V11

V12

V13

V14

V15

V16

V17

V18

V19

V20

V21

V22

V23

V24

V25

V26

GND

W04

W05

W06

W07

W08

W09

W10

W11

W12

W13

W14

W15

W16

W17

W18

W19

W20

W21

W22

W23

W24

W25

W26

Y04

Y05

Y06

Y07

Y08

Y09

Y10

Y11

Y12

Y13

Y14

Y15

Y16

Y17

Y18

Y19

Y20

Y21

Y22

Y23

Y24

Y25

Y26

No ball

V_DD

No ball

GND

No ball

SV_DD

No ball

SV_DD

MemData11

MemData15

MemData14

ECC0

ECC1

ECC5

GND

MemClkEn

DQS4

ECC4

MemData10

DM4

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Data Sheet

Table 4. Signals Listed by Ball Assignment (Sheet 6 of 7)

Ball

AA01

AA02

AA03

AA04

Signal Name

IIC0SData

Ball

AB01

AB02

AB03

AB04

Signal Name

Ball

AC01

AC02

AC03

AC04

Signal Name

GMCTxD5 *

Ball

AD01

AD02

AD03

AD04

Signal Name

GMCTxD2 *

GND

IIC1SClk *

SCPDI

GMCTxD7 *

GMCTxD6 *

EOV_DD

GMCTxD4 *

GMCTxD3 *

GND

GMCTxD1 *

GND

IIC1SData *

GMCCD *

EOV_DD

AA05

AA06

AA07

AA08

AA09

AA10

AA11

AA12

AA13

AA14

AA15

AA16

AA17

AA18

AA19

AA20

AA21

AA22

No ball

AB05

AB06

AB07

AB08

AB09

AB10

AB11

AB12

AB13

AB14

AB15

AB16

AB17

AB18

AB19

AB20

AB21

AB22

No ball

SV_DD

AC05

AC06

AC07

AC08

AC09

AC10

AC11

AC12

AC13

AC14

AC15

AC16

AC17

AC18

AC19

AC20

AC21

AC22

AD05

AD06

AD07

AD08

AD09

AD10

AD11

AD12

AD13

AD14

AD15

AD16

AD17

AD18

AD19

AD20

AD21

AD22

GMCTxEn *

SysErr

GMCTxClk

EOV_DD

GMCRefClk

EOV_DD

SysReset

GMCRxClk *

GMCRxD2 *

MemData27

Reserved

DM3

GND

V_DD

GMCRxD0 *

V_DD

GND

S

_VREF1A

SV_DD

V_DD

MemData23

DM2

S

_VREF2A

V_DD

MemData21

MemODT0

RAS

GND

SV_DD

MemAddr01

MemAddr05

BA0

MemAddr06

SV_DD

AA23

AA24

AA25

AA26

MemClkOut0

ECC7

AB23

AB24

AB25

AB26

AC23

AC24

AC25

AC26

GND

AD23

AD24

AD25

AD26

MemFBD

GND

MemAddr12

ECC3

MemAddr11

MemAddr13

MemAddr14

MemAddr09

MemAddr10

ECC6

ECC2

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Data Sheet

Table 4. Signals Listed by Ball Assignment (Sheet 7 of 7)

Ball

AE01

AE02

AE03

AE04

AE05

AE06

AE07

AE08

AE09

AE10

AE11

AE12

AE13

AE14

AE15

AE16

AE17

AE18

AE19

AE20

AE21

AE22

AE23

AE24

AE25

AE26

Signal Name

GMCTxD0 *

Ball

AF01

AF02

AF03

AF04

AF05

AF06

AF07

AF08

AF09

AF10

AF11

AF12

AF13

AF14

AF15

AF16

AF17

AF18

AF19

AF20

AF21

AF22

AF23

AF24

AF25

AF26

Signal Name

Ball

Signal Name

Ball

Signal Name

GND

GMCMDIO

GMCTxEr *

GMCCrS *

GMCRxEr *

GMCRxD6 *

GMCRxD5 *

GND

GMCMDClk

GMCGTxClk *

GMCRxDV *

GMCRxD7 *

EAGND

EAV_DD

GMCRxD4 *

GMCRxD1 *

MemData31

DQS3

GMCRxD3 *

MemData26

MemData30

MemData25

MemData29

GND

MemData24

MemData28

MemData18

DQS2

MemData19

MemData22

MemData17

MemData20

GND

MemData16

MemODT1

WE

BankSel1

MemAddr00

MemAddr03

MemAddr07

BA2

CAS

BankSel0

MemAddr02

MemAddr04

BA1

GND

MemFBR

GND

MemAddr08

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Data Sheet

Pin Group List

The following table provides a summary of the number of package pins (balls) associated with each functional

interface group.

Table 5. Pin Groups

Group

Total Signal Pins

V_DD

No. of Pins

246

17

20

6

OV_DD

EOV_DD

SV_DD

10

71

7

GND

AV_DD

AHV_DD

SAV_DD

2

1

SAGND

EAV_DD

1

EAGND

AGND

1

4

Total Power Pins

Reserved

141

1

Total Pins

388

In the table “Signal Functional Description” on page 39, each external signal is listed along with a short description

of the signal function. Active-low signals (for example, Halt) are marked with an overline. See the preceding table,

“Signals Listed Alphabetically” on page 18, for the pin (ball) number to which each signal is assigned.

Shared Pins

Some signals are shared on the same package pin so that the pin can be used for different functions. In most

cases, the signal names shown in this table are not accompanied by signal names that might share the same pin.

If you need to know what, if any, signals are shared with a particular signal, look up the name in “Signals Listed

Alphabetically” on page 18. It is expected that in any single application a particular pin will always be programmed

to serve the same function. The flexibility of sharing allows a single chip to offer a richer pin selection than would

otherwise be possible.

Initialization Strapping

One group of pins is used as strapped inputs during system reset. These pins function as strapped inputs only

during reset and are used for other functions during normal operation (see “Initialization” on page 71). Note that the

use of these pins for strapping is not considered multiplexing since the strapping function is not programmable.

Pull-Up and Pull-Down Resistors

Pull-up and pull-down resistors are used for strapping during reset and to retain unused or undriven inputs in an

appropriate state. The recommended pull-up value of 3kΩ to +3.3V and pull-down value of 1kΩ to GND, applies

only to individually terminated signals. To prevent possible damage to the device, I/Os capable of becoming

outputs must never be tied together and terminated through a common resistor.

If your system-level test methodology permits, input-only signals can be connected together and terminated

through either a common resistor or directly to +3.3V or GND. When a resistor is used, its value must ensure that

the grouped I/Os reach a valid logical zero or logical one state when accounting for the total input current into the

PPC405EX.

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Data Sheet

Signal Functional Descriptions

The following table provides a description of the I/O signals on the PPC405EX.

Table 6. Signal Functional Description (Sheet 1 of 7)

Notes:

1. Receiver input has hysteresis.

2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 38 for recommended termination values.

3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 38 for recommended termination values.

4. If not used, must pull up.

5. If not used, must pull down.

6. Strapping input during reset; pull up or pull down as required.

Signal Name

Description

I/O

Type

Notes

Ethernet Interface

GMCCD,

GMC1RxClk

GMII/MII: Collision detect.

RGMII 1: Receive clock.

3.3V tolerant

2.5V CMOS

I

1, 5

1

GMCCrS,

GMC1TxClk

GMII/MII: Carrier sense.

RGMII 1: Transmit clock.

3.3V tolerant

2.5V CMOS

I/O

O

GMCGTxClk,

GMC0TxClk

GMII/MII: Transmit clock for GMII 1000Mbps.

RGMII 0: Transmit clock.

3.3V tolerant

2.5V CMOS

3.3V tolerant

2.5V CMOS

GMCMDClk

GMCMDIO

Management data clock.

Management data I/O.

O

3.3V tolerant

2.5V CMOS

I/O

3.3V tolerant

2.5V CMOS

receiver

GMCRefClk

GMII/MII, RGMII: Required 125MHz reference clock.

I

1, 5

GMCRxClk,

GMC0RxClk

GMII/MII: Receive clock.

RGMII 0: Receive clock.

3.3V tolerant

2.5V CMOS

I

1, 5

1

GMCRxD0:3,

GMC0RxD0:3

GMII/MII: Receive data.

RGMII 0: Receive data.

3.3V tolerant

2.5V CMOS

GMCRxD4:7,

GMC1RxD0:3

GMII/MII: Receive data.

RGMII 1: Receive data.

3.3V tolerant

2.5V CMOS

I

1

GMCRxDV,

GMC0RxCtl

GMII/MII: Receive data valid.

RGMII 0: Receive control.

3.3V tolerant

2.5V CMOS

I

1

GMCRxEr,

GMC1RxCtl

GMII/MII: Receive error.

RGMII 1: Receive control.

3.3V tolerant

2.5V CMOS

I

1

3.3V tolerant

2.5V CMOS

GMCTxClk

GMII/MII: Transmit clock for 10/100Mbps.

I

1, 5

GMCTxD0:3,

GMC0TxD0:3

GMII/MII: Transmit data.

RGMII 0: Transmit data.

3.3V tolerant

2.5V CMOS

O

GMCTxD4:7,

GMC1TxD0:3

GMII/MII: Transmit data.

RGMII 1: Transmit data.

3.3V tolerant

2.5V CMOS

GMCTxEn,

GMC0TxCtl

GMII/MII: Transmit enable.

RGMII 0: Transmit control.

3.3V tolerant

2.5V CMOS

GMCTxEr,

GMC1TxCtl

GMII/MII: Transmit error.

RGMII 1: Transmit control.

3.3V tolerant

2.5V CMOS

IIC Interface

IIC0SClk

IIC Serial Clock.

IIC Serial Data.

IIC Serial Clock.

IIC Serial Data.

I/O

3.3V LVTTL

1, 2

2

IIC0SData

IIC1SClk

1

IIC1SData

1

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Data Sheet

Table 6. Signal Functional Description (Sheet 2 of 7)

Notes:

1. Receiver input has hysteresis.

2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 38 for recommended termination values.

3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 38 for recommended termination values.

4. If not used, must pull up.

5. If not used, must pull down.

6. Strapping input during reset; pull up or pull down as required.

Signal Name

Description

I/O

Type

Notes

PCI Express Interface (n = 0 and 1)

PCIEnATB

Analog Test Bus for manufacturing test.

na

I

Analog

CML

PCIEnClkC

PCIEnClkT

Differential input for external reference clock.

5

External reference resistor. Attach a 1.37 kΩ, 1% resistor between

RExt and RExtG to provide the reference for both the bias currents

and the impedance calibration circuitry.

PCIEnRExt

PCIEnRExtG

na

Analog

Differential receiver for received serial data.

PCIEnRx

I

LVDS receiver

LVDS driver

Note: Input must be DC coupled and biased to 0V common mode.

Differential driver for transmitted serial data.

PCIEnTx

O

Note: Output must be AC coupled.

Interrupts Interface

IRQ0:2

External interrupt requests.

I

3.3V LVTTL

IRQ3:5

1

IRQ6

IRQ7:9

JTAG Interface

TCK

Test clock.

I

3.3V LVTTL

1

3.3V LVTTL

w/pull-up

TDI

Test data in.

1, 4

TDO

TMS

Test data out.

Test mode select.

O

I

3.3V LVTTL

w/pull-up

1

Test reset. Must be low during power-on reset to initialize the JTAG

controller and for normal operation of the chip.

3.3V LVTTL

w/pull-up

TRST

I

1, 5

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Data Sheet

Table 6. Signal Functional Description (Sheet 3 of 7)

Notes:

1. Receiver input has hysteresis.

2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 38 for recommended termination values.

3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 38 for recommended termination values.

4. If not used, must pull up.

5. If not used, must pull down.

6. Strapping input during reset; pull up or pull down as required.

Signal Name

Description

I/O

Type

Notes

System Interface

3.3V tolerant

2.5V CMOS

receiver

SysClk

System input clock.

I

1

3.3V tolerant

2.5V CMOS

SysErr

Machine check exception has occurred.

O

Main system reset. This signal may be driven by the PPC405EX to

cause a board level reset to occur.

3.3V tolerant

2.5V CMOS

SysReset

I/O

1, 2

3

3.3V LVTTL

receiver

w/pull-down

TestEn

Halt

Test enable. Reserved for manufacturing LSSD test.

External request to stop the processor.

Processor timer external input.

I

3.3V LVTTL

receiver

w/pull-up

3.3V LVTTL

receiver

TmrClk

I

w/pull-up

General purpose I/O. Most of the GPIO signals are multiplexed with

other signals. Which signal is connected to the external pin depends

on the setting of bits in the GPIO registers.

GPIO00:27

GPIO29:31

I/O

3.3V LVTTL

General purpose I/O. Most of the GPIO signals are multiplexed with

other signals. Which signal is connected to the external pin depends

on the setting of bits in the GPIO registers.

3.3V tolerant

2.5V CMOS

GPIO28

I/O

O

Performance screen ring output. Use for module characterization and

screening only.

PSROUser

3

Trace Interface

TrcClk

Trace interface clock. Operates at half the CPU core frequency.

Even trace execution status.

O

3.3V LVTTL

TS0E

TS1E

I/O

TS0O

TS1O

Odd trace execution status.

Trace status.

I/O

3.3V LVTTL

TS0:3

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Data Sheet

Table 6. Signal Functional Description (Sheet 4 of 7)

Notes:

1. Receiver input has hysteresis.

2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 38 for recommended termination values.

3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 38 for recommended termination values.

4. If not used, must pull up.

5. If not used, must pull down.

6. Strapping input during reset; pull up or pull down as required.

Signal Name

Description

I/O

Type

Notes

External Peripheral Interface

PerAddr05:31

PerClk

Address bus 5:31.

I/O

O

3.3V LVTTL

Clock output.

PerCS0

Chip selects 0.

Chip selects 1:3.

Data bus 0:31.

Data bus parity 0:3.

Output enable.

O

2

PerCS1:3

PerData00:31

PerDataPar0:3

PerOE

I/O

O

1, 2

2

3.3V LVTTL

receiver

PerReady

Slave is ready to transfer data.

I

PerBLast

PerErr

Last transfer of burst access.

External bus error.

Read/Write.

I/O

O

3.3V LVTTL

1, 4

1, 3

1, 2

PerRW

PerWBE0:3

ExtReset

Write Byte enable 0:3.

External reset.

External Bus Master Interface

BusReq

External bus request.

O

I

3.3V LVTTL

1

ExtAck

External data transfer complete.

External data transfer request.

External request for bus access.

External request acknowledge.

ExtReq

HoldReq

I

HoldAck

O

DMA Interface

DMAAck0:1

DMAAck2:3

DMAReq0:1

DMAReq2

DMAReq3

DMAEOT0:1

DMAEOT2:3

External peripheral DMA acknowledge.

External peripheral DMA request.

O

I

3.3V LVTTL

1

External peripheral DMA request.

I

External peripheral DMA request.

I

External DMA peripheral end-of-transmission.

I/O

1

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Data Sheet

Table 6. Signal Functional Description (Sheet 5 of 7)

Notes:

1. Receiver input has hysteresis.

2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 38 for recommended termination values.

3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 38 for recommended termination values.

4. If not used, must pull up.

5. If not used, must pull down.

6. Strapping input during reset; pull up or pull down as required.

Signal Name

NAND Flash Interface

NFALE

Description

I/O

Type

Notes

Address latch enable.

Chip select 0.

O

3.3V LVTTL

NFCE0

NFCE1:3

Chip selects 1:3.

Command latch enable.

Data Bus

O

1

NFCLE

O

NFData00:15

I/O

Read/Busy. If low, indicates that Read/Erase command is in process.

If high, indicates that the command is complete.

NFRdyBusy

I

3.3V LVTTL

NFRE

NFWE

Read enable.

Write enable.

O

3.3V LVTTL

DDR1/2 SDRAM Interface

2.5V (1.8V)

SSTL2 Dr/Rcv

MemData00:31

MemAddr00:14

RAS

Memory data.

I/O

O

2.5V (1.8V)

SSTL2 Dr/Rcv

Memory address.

2.5V (1.8V)

SSTL2 Dr/Rcv

Row address strobe.

O

2.5V (1.8V)

SSTL2 Dr/Rcv

CAS

Column address strobe.

Clock enable.

O

2.5V (1.8V)

SSTL2 Dr/Rcv

MemClkEn

O

MemClkOut0

2.5V (1.8V)

SSTL2 Dr/Rcv

Differential DDR SDRAM clock output.

O

Feedback driver. Connect directly to MemFBR with the minimum

trace length.

2.5V (1.8V)

SSTL2 Dr/Rcv

MemFBD

MemFBR

MemODT0:1

DM0:4

O

2.5V (1.8V)

SSTL2 Dr/Rcv

Feedback receiver. Connect externally to MemFBD.

On-die termination.

I

2.5V (1.8V)

SSTL2 Dr/Rcv

O

Write data byte lane mask. DM4 is the byte lane mask for the ECC

byte lane.

2.5V (1.8V)

SSTL2 Dr/Rcv

O

2.5V (1.8V)

SSTL2 Dr/Rcv

DQS0:4

BA0:2

Byte lane strobe. DQS4 is the strobe for the ECC lane.

Bank address for up to eight banks.

Bank select for up to two SDRAM memory banks.

ECC check bit byte.

I/O

O

2.5V (1.8V)

SSTL2 Dr/Rcv

2.5V (1.8V)

SSTL2 Dr/Rcv

BankSel0:1

ECC0:7

WE

O

2.5V (1.8V)

SSTL2 Dr/Rcv

I/O

O

2.5V (1.8V)

SSTL2 Dr/Rcv

Write enable.

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Data Sheet

Table 6. Signal Functional Description (Sheet 6 of 7)

Notes:

1. Receiver input has hysteresis.

2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 38 for recommended termination values.

3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 38 for recommended termination values.

4. If not used, must pull up.

5. If not used, must pull down.

6. Strapping input during reset; pull up or pull down as required.

Signal Name

Description

I/O

Type

Notes

DDR 1 (DDR2) Reference voltage 1 and 2 inputs:

S_VREF1A:B

S_VREF2A:B

1.25V (0.9V)

Volt ref receiver

Minimum +1.15 (+0.825)V

Nomimal +1.25 (+0.9)V

Maximum +1.35 (0.975)V

I

Serial Communication Port (SCP) Interface

SCPClkOut

SCPDI

Output clock.

Data input.

I/O

I

3.3V LVTTL

SCPDO

Data output.

O

UART Peripheral Interface

The UART interface can be configured as follows:

1. One 8-pin

2. Two 4-pin

3. Two 2-pin (pull up DCD, DSR, CTS and RTS)

4. One 4-pin and one 2-pin

3.3V LVTTL

receiver

UARTSerClk

Serial clock input.

I

w/pull-up

UARTnCTS

UARTnDCD

UARTnDSR

UARTnDTR

UARTnRI

Clear to send.

I

3.3V LVTTL

1, 6

1

Data carrier detect.

Data set ready.

Data terminal ready.

Ring indicator.

I

O

I

1

UARTnRTS

UARTnRx

Request to send.

Receive data.

O

I

1

UARTnTx

Transmit data.

O

USB 2.0 Interface

3.3V LVTTL

receiver

USB2Clk

USB clock.

I

5

USB2Data0:7

USB2Dir

Parallel data bus.

I/O

I

3.3V LVTTL

Data bus direction control.

Next data byte control. When data is being transferred to the PHY,

the next byte should be sent. When data is being received from the

PHY, the next byte is available.

USB2Next

USB2Stop

I

3.3V LVTTL

Stop output control.

O

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Data Sheet

Table 6. Signal Functional Description (Sheet 7 of 7)

Notes:

1. Receiver input has hysteresis.

2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 38 for recommended termination values.

3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 38 for recommended termination values.

4. If not used, must pull up.

5. If not used, must pull down.

6. Strapping input during reset; pull up or pull down as required.

Signal Name

Description

I/O

Type

Notes

Power

V_DD

Logic Supply (+1.2V).

I/O Supply (+3.3V).

na

OV_DD

SV_DD

EOV_DD

DDR1/2 SDRAM Supply (+2.5V or +1.8V)

Ethernet I/O Supply (+2.5V)

GND

Ground.

SAV_DD

System PLL Analog Supply (+2.5V).

System PLL Analog Ground.

SAGND

EAV_DD

Ethernet PLL Analog Supply (+2.5V).

Ethernet PLL Analog Ground.

EAGND

AV_DD

PCI-Express SerDes Analog Supply (+1.2V)

PCI-Express SerDes PLL Analog Supply (+2.5V).

PCI-Express Analog Ground (for AHV_DDand AV_DD)

AHV_DD

.

AGND

Other

Reserved

Do not connect voltages, grounds, or signals to these pins.

na

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Data Sheet

Ratings and Specifications

Table 7. Absolute Maximum Ratings

The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause

permanent damage to the device. None of the performance specification contained in this document are guaranteed when

operating at these maximum ratings.

Characteristic

Logic Supply Voltage (internal logic)

PCI-Express SerDes Analog Supply Voltage

PCI-Express SerDes PLL Analog Supply Voltage

I/O Supply Voltage

Symbol

Value

0 to +1.6

Unit

V

Notes

V_DD

AV_DD

AHV_DD

OV_DD

SV_DD

EOV_DD

SAV_DD

EAV_DD

V_IN

0 to +1.6

V

1

0 to +2.6

V

0 to +3.6

V

SDRAM DDR1[2] Supply Voltage

Ethernet I/O Supply Voltage

0 to +2.6 [+1.9]

0 to +2.6

V

System PLL Analog Supply Voltage

Ethernet PLL Analog Supply Voltage

Input voltage (3.3V LVTTL receivers)

Storage Temperature Range

0 to +2.6

V

1

0 to +2.6

V

0 to +3.6

V

T_STG

−55 to +150

−40 to +120

−40 to +125

°C

T_C

Case Temperature Range under bias

Junction Temperature Range

T_JMax

2

Notes:

1. The analog voltages can be derived from the +1.2V and +2.5V supplies, but must be filtered as shown below before entering the

PPC405EX. Use a separate filter for each voltage. This circuit can be used for AV_DD, AHV_DD, SAV_DD, and EAV_DD. Use AGND

with AV_DDand AHV_DD.Use SAGND with SAV_DD. Use EAGND with EAV_DD. These analog grounds must be brought out and

connected to the digital ground plane at the filter capacitor. Keep all wire lengths as short as possible.

V

AV

DD

L1 – Murata BLM18AG121SN1D

L1

C1

C1 – 0.1 μF ceramic

AGND

GND

2. The device meets all electrical specifications at a junction temperature, under bias, of 125ºC, but part lifetime and reliability is

reduced. It is recommended that prudent thermal management techniques be used to maximize device lifetime.

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Data Sheet

Table 8. Package Thermal Specifications

The PPC405EX is designed to operate within a case temperature range T_Cdefined in “Recommended DC Operating

Conditions” on page 48. Thermal resistance values for the EPBGA packages in a convection environment are as follows:

Airflow

ft/min (m/sec)

Parameter

Symbol

Unit

0 (0)

100 (0.51) 200 (1.02) 300 (1.52) 400 (2.02) 500 (2.53) 600 (3.03)

Junction-to-ambient

thermal resistance

without heat sink

θ_JA

18.9

16.6

12.5

15.8

11.4

15.4

10.9

15.0

10.7

14.7

10.5

14.4

10.3

°C/W

Junction-to-ambient

thermal resistance

with heat sink

15.5

Resistance Value

Junction-to-case thermal

resistance

θ_JC

θ_JB

8.96

°C/W

Junction-to-board thermal

resistance

13.74

Notes:

1. Values in the table are achieved with the following JEDEC standard board: 114.5mm x 101.6mm x 1.6mm, 4 layers.

2. For a chip mounted on a card with at least one signal and two power planes, the following relationships exist:

a. Case temperature, T_C, is measured at top center of case surface with device soldered to circuit board.

b. T_A= T_C– Pxθ_CA, where T_Ais ambient temperature and P is power consumption.

c. T_CMax= T_JMax– Pxθ_JC, where T_JMaxis maximum junction temperature and P is power consumption.

Thermal Management

The following heat sink was used in the above thermal analysis:

26.92mm x 27mm x 11.43mm

The heat sink is manufactured by:

Aavid Thermalloy, P/N 62925

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Data Sheet

Table 9. Recommended DC Operating Conditions (Sheet 1 of 2)

Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended

conditions can affect device reliability.

Parameter

Logic Supply Voltage—400MHz

Logic Supply Voltage—533MHz & 600MHz

I/O Supply Voltage

Symbol

Minimum

+1.1

Typical

+1.15

Maximum

+1.2

Unit

V

Notes

V_DD

2

V_DD

OV_DD

SV_DD

EOV_DD

+1.2

+1.25

+1.3

V

+3.15

+3.3

+3.45

V

SDRAM DDR1[2] Supply Voltage

Ethernet I/O Supply Voltage

+2.4 [+1.7]

+2.4

+2.5 [+1.8]

+2.5

+2.6 [+1.9]

+2.6

V

AHV_DD

SAV_DD

EAV_DD

PLL Analog Supply Voltage

+2.4

+2.5

+2.6

V

AV_DD

V_IL

Analog Supply Voltage—400MHz

Analog Supply Voltage—533MHz & 600MHz

I/O Input Low (3.3V LVTTL)

+1.1

+1.2

0

+1.15

+1.25

+1.2

+1.3

+0.8

+3.6

+0.4

+3.6

+0.7

+3.6

+0.4

+2.7

V

2

V_IH

I/O Input High (3.3V LVTTL)

+2.0

0

V_OL

V_OH

V_IL

I/O Output Low (3.3V LVTTL)

I/O Output High (3.3V LVTTL)

+2.4

0

I/O Input Low (3.3V tol, 2.5V CMOS)

I/O Input High (3.3V tol, 2.5V CMOS)

I/O Output Low (3.3V tol, 2.5V CMOS)

I/O Output High (3.3V tol, 2.5V CMOS)

V_IH

+1.7

0

V_OL

V_OH

+2.0

S_VREF− 0.18

V_IL

V_IH

I/O Input Low DDR1[2] (SSTL2)

I/O Input High DDR1[2] (SSTL2)

− 0.3

V

[0.125]

S_VREF+ 0.18

[0.125]

SV_DD+ 0.3

V_OL

V_OH

I/O Output Low DDR1[2] (SSTL2)

I/O Output High DDR1[2] (SSTL2)

See JESD8-9 (JESD8-15A) standard.

V

Input Leakage Current

(no pull-up or pull-down)

I_IL1

I_IL2

I_IL3

0

1

μA

Input Leakage Current

(with internal pull-down)

0 (LPDL)

200 (MPUL)

0 (MPUL)

1

Input Leakage Current

(with internal pull-up)

−150 (LPDL)

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Data Sheet

Table 9. Recommended DC Operating Conditions (Sheet 2 of 2)

Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended

conditions can affect device reliability.

Parameter

Symbol

Minimum

Typical

Maximum

Unit

Notes

I/O Maximum Allowable Overshoot

(3.3V LVTTL and 2.5V/3.3 tolerant CMOS)

V_MAO

+3.9

V

3, 4

I/O Maximum Allowable Undershoot

(3.3V LVTTL and 2.5V/3.3 tolerant CMOS)

V_MAU

T_C

−0.6

−40

0

V

3, 4

5

Case Temperature

+85

°C

Notes:

1. LPDL is least positive down level; MPUL is most positive up level.

2. Can be extended to 1.1V min., 1.2V typ., 1.3V max. with an estimated power increase of 130mW at 1.2V nom.

3. Maximum duration is 10% of the bus clock period. Bus clock is as follows:

EBC—PerClk

Ethernet—RxClk

USB—USB2Clk

4. Duration of the overshoot is time above V_IHmax. Duration of the undershoot is time below V_ILmin.

5. A 533MHz part running at 400MHz or less can operate up to a case temperature of +95°C.

Power Supply Sequence

All the PPC405EX I/O designs are power supply sequence independent. There is no requirement that the power

supplies power up in any particular order. The following items are power sequence considerations:

• If the logic power (V_DD) is applied before the I/O supply voltages, the I/Os include internal supply sequencing

circuitry that ensures the output of the receiver connected to internal chip logic is 0 until the I/O power is

applied. When the logic power supply is on and the I/O power supplies are off, the I/O logic connected to the

associated ball neither sinks or sources significant current unless influenced by an internal pull-up or pull-down

resistor. While the I/O supply is ramping, the state of the I/O balls are not predictable. This power sequence is

not destructive to the I/Os or internal logic and does not cause any functional problems.

• If the I/O power is applied before the logic power is applied, the output driver output stage (connected to the

balls) will come up in an unknown state (driving 1, driving 0, or tri-state) until the internal logic voltage is stable

within normal operating range. This power sequence is not destructive to the I/Os or internal logic and does not

cause any functional problems.

• External voltage should not be applied to the chip I/O balls before the associated I/O power supply voltage is

applied to the chip.

• A chip power down cycle must complete (all I/O supply voltages and V_DDare below +0.4V) before a new

power-up cycle is started.

• During a 405EX power-up cycle, the system reset and test reset inputs should be asserted low. System reset

and test reset should remain asserted until the system clock is stable and then at least 32 system clock times

after all power supplies are stable within normal operating range. Failure to follow this reset sequence during

the power-up cycle might result in unpredictable operation.

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Data Sheet

Table 10. I/O Input Capacitance

Parameter

Symbol

Maximum

2.3

Unit

pF

Notes

C_IN1

C_IN2

C_IN3

C_IN4

C_IN5

C_IN6

3.3V LVTTL

2.5V CMOS

2.1

2.5/1.8V SSTL2

3.2

PCI Express differential data receiver

PCI Express differential data transmitter

PCI Express differential clock receiver

1.59

1.16

0.188

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Data Sheet

Table 11. Typical DC Power Supply Requirements with DDR1 SDRAM

+1.2V nom (V_DD+AV_DD

)

+2.5V

+1.8V

(not used

with DDR1)

+3.3V

Frequency

(MHz)

(SV_DD+EOV_DD

+

Total

Unit

Notes

(OV_DD

)

AHV_DD+SAV_DD+EAV_DD

)

+1.15V

1.08

1.20

na

+1.25V

333

400

na

0.54

0.60

0.11

0.12

1.73

1.91

2.28

2.32

W

1, 2

1, 3

1, 4

1, 5

533

1.57

1.60

600

na

Notes:

1. Typical power is measured on a typical process part at a case temperature of +85°C at the specified voltages while running Linux and

test applications that exercise each function with representative traffic (2 PCI Express, 2 Gigabit Ethernet, USB, and Security).

2. DDR1 running at 333MHz., PLB running at 166MHz.

3. DDR1 running at 400MHz., PLB running at 200MHz.

4. DDR1 running at 355MHz., PLB running at 177MHz.

5. DDR1 running at 400MHz., PLB running at 200MHz.

Table 12. Maximum DC Power Supply Requirements with DDR1 SDRAM

+1.2V nom (V_DD+AV_DD

)

+2.6V

+1.8V

(not used

with DDR1)

+3.45V

Frequency

(MHz)

(SV_DD+EOV_DD

+

Total

Unit

Notes

(OV_DD

)

AHV_DD+SAV_DD+EAV_DD

)

+1.2V

2.06

2.24

na

+1.3V

na

333

400

na

0.65

0.72

0.73

0.75

0.15

0.17

2.86

3.11

3.90

4.15

W

1, 2

1, 3

1, 4

1, 5

na

533

3.00

3.23

600

na

Notes:

1. Maximum power is measured on a best-case process (worst-case power) part at a case temperature of +85°C at the specified voltages

while running Linux and test applications that exercise each function with representative traffic (2 PCI Express, 2 Gigabit Ethernet,

USB, and Security).

2. DDR1 running at 333MHz., PLB running at 166MHz.

3. DDR1 running at 400MHz., PLB running at 200MHz.

4. DDR1 running at 355MHz., PLB running at 177MHz.

5. DDR1 running at 400MHz., PLB running at 200MHz.

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Data Sheet

Table 13. Typical DC Power Supply Requirements with DDR2 SDRAM

+1.2V nom (V_DD+AV_DD

)

+2.5V

+1.8V

+3.3V

Frequency

(MHz)

(EOV_DD+AHV_DD

+

Total

Unit

Notes

(SV_DD

)

(OV_DD)

SAV_DD+EAV_DD

)

+1.15V

1.08

1.20

na

+1.25V

na

333

400

0.21

0.26

0.2

0.23]

0.23

0.24

0.25

0.10

0.11

0.12

1.62

1.79

2.13

2.23

W

1, 2

1, 3

1, 4

1, 5

na

533

1.57

1.60

600

na

0.26

Notes:

1. Typical power is measured on a typical process part at a case temperature of +85°C at the specified voltages while running Linux and

test applications that exercise each function with representative traffic (2 PCI Express, 2 Gigabit Ethernet, USB, and Security).

2. DDR2 running at 333MHz., PLB running at 166MHz.

3. DDR2 running at 400MHz., PLB running at 200MHz.

4. DDR2 running at 355MHz., PLB running at 177MHz.

5. DDR2 running at 400MHz., PLB running at 200MHz.

Table 14. Maximum DC Power Supply Requirements with DDR2 SDRAM

+1.2V nom (V_DD+AV_DD

)

+2.6V

+1.9V

+3.45V

Frequency

(MHz)

(EOV_DD+AHV_DD

+

Total

Unit

Notes

(SV_DD

)

(OV_DD)

SAV_DD+EAV_DD

)

+1.2V

2.06

2.24

na

+1.3V

na

333

400

0.21

0.22

0.23

0.30

0.26

0.28

0.15

0.17

2.68

2.87

3.66

3.97

W

1, 2

1, 3

1, 4

1, 5

na

533

3.00

3.22

600

na

Notes:

1. Maximum power is measured on a best-case process (worst-case power) part at a case temperature of +85°C at the specified voltages

while running Linux and test applications that exercise each function with representative traffic (2 PCI Express, 2 Gigabit Ethernet, USB,

and Security).

2. DDR2 running at 333MHz., PLB running at 166MHz.

3. DDR2 running at 400MHz., PLB running at 200MHz.

4. DDR2 running at 355MHz., PLB running at 177MHz.

5. DDR2 running at 400MHz., PLB running at 200MHz.

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Data Sheet

Table 15. DC Power Supply Loads with DDR1 SDRAM

Parameter

Symbol

Typical

Maximum

Unit

mA

Notes

V

_DD(+1.2V) active operating current

I_DD1.2

1280

4

2475

10

2

1

AV_DD(+1.2V) active operating current

AHV_DD(+2.5V) active operating current

OV_DD(+3.3V) active operating current

SV_DD+ EOV_DD(+2.5V) active operating current

SAV_DD(+2.5V) active operating current

EAV_DD(+2.5V) active operating current

Notes:

I_ADD

I_AHDD

I_ODD

I_DD

1

35

235

1

50

280

2

I_SADD

I_EADD

1

2

1. The maximum current values listed above are not guaranteed to be the highest obtainable. These values are dependent on many

factors including the type of applications running, clock rates, use of internal functional capabilities, external interface usage, case

temperature, and the power supply voltages. Your specific application can produce significantly different results. V_DD(logic) current and

power are primarily dependent on the applications running and the use of internal chip functions (DMA, PCI Express, Ethernet, and so

on). OV_DD(I/O) current and power are primarily dependent on the capacitive loading, frequency, and utilization of the external buses.

The information in this table provides details about the conditions under which the listed values were obtained. Maximum power is

measured on a best-case process (worst-case power) part running at 600MHz with a case temperature of +85°C and with voltages of

V

_DD= +1.30V, OV_DD= +3.45V, SV_DD= +2.6V, and EOV_DD= +2.6V while running Linux and test applications that exercise each

function with representative traffic (2 PCI Express, 2 Gigabit Ethernet, USB, Security).

Table 16. DC Power Supply Loads with DDR2 SDRAM

Parameter

Symbol

Typical

Maximum

Unit

mA

Notes

V

_DD(+1.2V) active operating current

I_DD

1280

4

2475

10

2

1

AV_DD(+1.2V) active operating current

AHV_DD(+2.5V) active operating current

OV_DD(+3.3V) active operating current

SV_DD(+1.8V) active operating current

EOV_DD(+2.5V) active operating current

SAV_DD(+2.5V) active operating current

EAV_DD(+2.5V) active operating current

Notes:

I_ADD

I_AHDD

I_ODD

1

35

145

95

1

50

155

100

2

I_SDD

I_EODD

I_SADD

I_EADD

1

2

1. The maximum current values listed above are not guaranteed to be the highest obtainable. These values are dependent on many

factors including the type of applications running, clock rates, use of internal functional capabilities, external interface usage, case

temperature, and the power supply voltages. Your specific application can produce significantly different results. V_DD(logic) current and

power are primarily dependent on the applications running and the use of internal chip functions (DMA, PCI Express, Ethernet, and so

on). OV_DD(I/O) current and power are primarily dependent on the capacitive loading, frequency, and utilization of the external buses.

The information in this table provides details about the conditions under which the listed values were obtained. Maximum power is

measured on a best-case process (worst-case power) part running at 600MHz with a case temperature of +85°C and with voltages of

V

_DD= +1.30V, OV_DD= +3.45V, SV_DD= +1.9V, and EOV_DD= +2.6V while running Linux and test applications that exercise each

function with representative traffic (2 PCI Express, 2 Gigabit Ethernet, USB, Security).

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Data Sheet

Power Control

This chip has power management control to put the following functional units to sleep if not needed. The typical

and maximum power consumption for the each of these units is:

Table 17. Power Contribution of Functional Units

Functional Unit

Typical

0.006

0.117

0.127

0.005

0.118

Maximum

0.012

Units

W

Notes

EBM/OPB

Security

Nand Flash

USB

0.230

W

0.246

W

0.008

W

EMAC

0.133

W

Test Conditions

Clock timing and switching characteristics are specified in accordance with minimum

operating conditions shown in the table “Recommended DC Operating Conditions” on

page 48. For all signals, AC specifications are characterized at T_C= +85°C with the test

load shown in the figure to the right.

Output

10pF

Table 18. System Clocking Specifications

Symbol

CPU

Parameter

Minimum

Maximum

Units

PF_C

Processor clock frequency (must be ≥ SCF_C)

333.33

600

MHz

SysClk Input

SCF_C

Frequency

33.33

na

100

±0.1

60

MHz

ns

SCT_CS

SCT_CH

SCT_CL

SC_RT

Edge stability (phase jitter, cycle-to-cycle)

High time (% of nominal period)

Low time (% of nominal period)

Rise time

40

%

40

60

%

na

1

ns

Other Clocks

VCOF_C

VCO frequency

600

133

1800

200

100

MHz

PLBF_C

OPBF_C

AHBFc

PLB and MemClkOut0 frequency

OPB frequency

66¹

60

AHB frequency

Note 1: In order to support 1Gbps Ethernet data rate, the minimum OPB clock frequency is 66.66Mhz. If an application is

limited to 100Mbps, the minimum OPB clock frequency is 33.33Mhz.

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Data Sheet

Figure 3. Clocking Waveform

Note: SysClk and GMCRefClk are 2.5V (3.3V tolerant) signals. Rise time should be measured between 0.7V and 1.7V.

1.7 (2.0) V

1.25 (1.5) V

0.7 (0.8) V

T

CL

CH

T

C

Spread Spectrum Clocking

Care must be taken if using a spread spectrum clock generator (SSCG) with the PPC405EX. This controller uses a

PLL for clock generation inside the chip. The accuracy with which the PLL follows the SSCG is called tracking

skew. The PLL bandwidth and phase angle determine how much tracking skew exists between the SSCG and the

PLL for a given frequency deviation and modulation frequency. If using an SSCG with the PPC405EX the following

conditions must be met:

• The frequency deviation must not violate the minimum clock cycle time. Therefore, when operating the

PPC405EX with one or more internal clocks at their maximum supported frequency, the SSCG can only lower

the frequency.

• The maximum frequency deviation must not exceed −3%, and the modulation frequency must not exceed

40kHz. In some cases, on-board PPC405EX peripherals impose more stringent requirements (see Note 1).

• Use the peripheral bus clock for logic that is synchronous to the peripheral bus because this clock tracks the

modulation.

Notes:

1. The serial port baud rates are synchronous to the modulated clock. The serial port has a tolerance of

approximately 1.5% on baud rate before framing errors begin to occur, assuming that the connected device is

running at precise baud rates. If an external serial clock is used, baud rate is unaffected by the modulation.

2. Ethernet operation is unaffected.

3. IIC operation is unaffected.

4. For PCI-E see the PCI Express I/O Specifications.

Caution: The system designer must ensure that any SSCG used with the PPC405EX meets these requirements

and does not adversely affect other aspects of the system.

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Data Sheet

Table 19. Peripheral Interface I/O Clock Timings (not SDRAM or PCI-E)

Clock

Minimum

Maximum

Units

MHz

ns

Notes

GMCTxClk frequency

GMCTxClk high time

GMCTxClk low time

GMCRxClk frequency

GMCRxClk high time

GMCRxClk low time

GMCGTxClk

125

45% of nominal

–

55% of nominal

–

ns

125

MHz

ns

45% of nominal

–

55% of nominal

–

ns

125

MHz

ns

GMCMDClk

2.5

25

GMCRefClk

125

GMCRefClk edge stability (phase jitter, cycle-to-cycle)

na

± 0.1

GMCRefClk rise time

GMCRefClk high time

GMCRefClk low time

GMCnRxClk

GMCnTxClk

UARTSerClk

TmrClk

na

40% of nominal

60% of nominal

125

1

ns

–

ns

–

ns

125

MHz

125

1000 / 2T_OPB+ 2ns

1

2

na

33

100

40

PerClk

TCK

na

USB2Clk (60MHz ± 0.05%)

TrcClk

57.97

66

60.03

300

Notes:

1. T_OPBis the period in ns of the OPB clock. The internal OPB clock runs at an integral divisor ratio of the frequency of the PLB clock. The

maximum OPB clock frequency is 100MHz.

2. TrcClk is 1/2 CPU Clk. The maximum CPU Clk supported by instruction trace probes is 400 MHz.

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Data Sheet

Figure 4. Input Setup and Hold Timing Waveform

1.25 (1.5)V

Clock

T

IS

IH

MIN

Inputs 1.25 (1.5)V

Valid

Figure 5. Output Delay and Float Timing Waveform

Clock

1.25 (1.5)V

T

OH

OV

MAX

MIN

Outputs 1.25 (1.5)V

Valid

MAX

T

OF

MIN

Outputs

1.25 (1.5)V

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Data Sheet

Figure 6. Setup and Hold Timing Waveforms for RGMII Signals

GMCnTxClk

TskewT

GMCnTxD/Ctl

Valid

GMCnRxClk

TskewR

GMCnRxD/Ctl

Valid

Table 20. RGMII I/O Timing

Input (ns)

Output (ns)

Output Current (mA)

Signal

Clock

Notes

TskewR

(min)

TskewR

(max)

TskewT

(min)

TskewT

(max)

I/O H

(min)

I/O L

(min)

GMCnRxClk

GMCnRxD0:3

GMCnRxCtl

GMCnTxClk

GMCnTxD0:3

GMCnTxCtl

Notes:

–

n/a

–

1.0

v

2.8

–

n/a

–

n/a

–

GMCnRxClk

–

1

n/a

5.51

7.23

n/a

-0.5

0.5

GMCnTxClk

1. Assumes GMCnRxClk is delayed either on the board or by the PHY to ensure adequate timing margin.

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Data Sheet

Table 21. I/O Specifications (Sheet 1 of 2)

Notes:

1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.

Input (ns)

Output (ns)

Output Current (mA)

Signal

Clock

Notes

Setup Time Hold Time

Valid Delay

(T_OVmax)

Hold Time

(T_OHmin)

I_OH

(min)

I_OL

(min)

(T_ISmin)

(T_IHmin)

Ethernet GMII Interface

GMCMDClk

GMCMDIO

GMCCD

na

10

na

0

na

10

na

10

5.51

na

7.23

na

Async

1

2

0

Async

GMCCrS

2

0

na

Async

GMCRxD0:7

GMCRxDV

GMCRxEr

1.85

1.95

0

na

GMCRxClk

GMCGTxClk

0

na

0

na

GMCTxD0:7

GMCTxEr

2.3

2.4

2.0

5.51

7.23

GMCTxEn

Internal Peripheral Interfaces (not SDRAM or PCI-E)

IICnSData

na

10.46

na

UARTnCTS

na

15.75

na

UARTnRTS

UARTnDSR

UARTnDCD

UARTnDTR

UARTnRI

UARTnRx

UARTnTx

SCPDI

na

15.75

na

10.46

na

SCPDO

na

10.46

na

USB2Data0:7

USB2Dir

3.9

3.7

3.5

0

6.3

6.4

2

15.75

na

USB2Clk

USB2Next

USB2Stop

DMA Interface

DMAAck0:3

DMAReq0:3

DMAEOT0:3

Interrupts Interface

IRQ0:9

na

6.4

5.2

5.3

2

15.75

10.46

1.0

15.75

na

10.46

na

PerClk

2.4

2

1

15.75

10.46

15.75

10.46

JTAG Interface

TDI

2

5.5

na

15.75

na

10.46

na

TCK

TDO

9.5

1

TMS

TCK

TRST

na

Async

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Data Sheet

Table 21. I/O Specifications (Sheet 2 of 2)

Notes:

1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.

Input (ns)

Output (ns)

Output Current (mA)

Signal

Clock

Notes

Setup Time Hold Time

Valid Delay

(T_OVmax)

Hold Time

(T_OHmin)

I_OH

(min)

I_OL

(min)

(T_ISmin)

(T_IHmin)

System Interface

GPIO00:10

GPIO11:15

GPIO16:27

GPIO28

na

11.08

5.51

11.08

15.75

11.08

na

7.37

7.23

7.37

10.46

7.37

na

GPIO29:31

Halt

SysErr

5.51

7.23

SysReset

External Peripheral Interface

PerAddr05:31

PerCS0:3

PerData00:31

PerDataPar0:3

PerOE

1.8

1

5.3

5.2

5.3

5.2

1

11.08

na

7.37

na

PerClk

2.7

1.9

1

PerReady

PerRW

2

1

1.8

1.7

2

5.3

5.1

5

1

11.08

na

7.37

na

PerWBE0:3

PerBLast

PerErr

1.9

5.3

5.1

5.2

5

ExtReset

BusReq

2.3

2

1

HoldReq

HoldAck

11.08

na

7.37

na

ExtAck

2.3

2

1

ExtReq

5.3

NFALE

1

11.08

na

7.37

na

NFCE0:3

NFCLE

NFData0:15

NFRdyBusy

NFREn

2.3

1.7

1

5.3

1

11.08

7.37

NFWEn

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DDR 1/2 SDRAM I/O Specifications

Data Sheet

The DDR SDRAM controller times its operation using the internal PLB clock signal and generates MemClkOut from

the PLB clock. The PLB clock is an internal signal that cannot be directly observed. However MemClkOut is the

same frequency as the PLB clock signal and is in phase with the PLB clock signal.

Note: MemClkOut can be advanced with respect to the PLB clock by means of the SDRAM0_CLKTR

programming register. In a typical system, users advance MemClkOut by 90°. This depends on the specific

application and requires a thorough understanding of the memory system in general (refer to the DDR

SDRAM Controller chapter in the PPC405EX Embedded Processor User’s Manual).

The signals are terminated as indicated in Figure 7 for the DDR timing data and output currents in the following

sections.

Figure 7. DDR SDRAM Simulation Signal Termination Model

MemClkOut0

10pF

120Ω

10pF

MemClkOut0

V

= SOV /2

DD

TT

PPC405EX

50

Ω

Addr/Ctrl (DDR2)

Addr/Ctrl/Data/DQS/DM (DDR1)

30pF

Note: This diagram illustrates the model of the DDR SDRAM interface used when generating simulation timing data.

It is not a recommended physical circuit design for this interface. An actual interface design depends on many

factors, including the type of memory used and the board layout.

DDR2 SDRAM On-Die Termination Impedance Setting

For all DDR2 applications, the On-Die Termination (ODT) impedance value must be set to 75Ω in the DIMM

Extended Mode Register (EMR) in order to optimize the data transmission during memory write operations.

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Data Sheet

Table 22. DDR SDRAM Output Driver Specifications

Output Current (mA)

Signal Path

I/O H (maximum)

I/O L (maximum)

Write Data

MemData00:31

ECC0:7

10

DM0:4

MemClkOut0

MemAddr00:14

BA0:2

RAS

CAS

WE

BankSel0:1

MemClkEn

DQS0:4

MemODT0:1

DDR SDRAM Write Operation

The rising edge of MemClkOut aligns with the first rising edge of the DQS signal on writes as indicated in Figure 8.

DQS rising and falling edges are centered on valid data for writes.

The data in Table 23 is generated by means of simulation and includes logic, driver, package RLC, and lengths.

Values are calculated over best case and worst case processes with speed, junction temperature, and voltage as

follows:

Table 23. DDR SDRAM Write Operation Conditions

Case

Best

Process Speed

Fast

Junction Temperature (°C)

Voltage (V)

+1.3

−40

Worst

Slow

+125

+1.1

Note: In the following tables and timing diagrams, minimum values are measured under best case conditions and

maximum values are measured under worst case conditions. The timing numbers in the following sections are

obtained using a simulation that assumes a model as shown in Figure 7.

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Data Sheet

The following diagram illustrates the relationship among the signals involved with a DDR write operation.

Figure 8. DDR SDRAM Write Cycle Timing

PLB Clk

MemClkOut0

T

SA

Addr/Cmd

T

DS

T

HA

T

DS

DQS

T

SD

T

SD

MemData

T

HD

T

HD

T

= Setup time for address and command signals to MemClkOut0

= Hold time for address and command signals from MemClkOut0

SA

T

HA

SD

HD

T

= Setup time for data signals (minimum time data is valid before rising/falling edge of DSQ)

= Hold time for data signals (minimum time data is valid after rising/falling edge of DSQ)

= Delay from rising/falling edge of clock to the rising/falling edge of DQS

T

DS

Note: The timing data in the following tables is based on simulation runs using Einstimer.

Table 24. I/O Timing—DDR SDRAM T

DS

Notes:

1. All of the DQS signals are referenced to MemClkOut0 with the DQS delay line programmed to 1 cycle.

2. Clock speed is 200MHz.

T_DS(ns)

Signal Name

Minimum

Maximum

DQS0

DQS1

DQS2

DQS3

DQS4

4

6

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Data Sheet

Table 25. I/O Timing—DDR SDRAM T and T

SA

HA

T_SA(ns) Minimum

T_HA(ns) Minimum

Signal Name

MemAddr00:14

BA0:2

1.08

1.12

1.09

1.10

1.09

1.08

1.12

1.15

1.13

1.16

1.13

1.12

1.16

BankSel0:1

MemClkEn

CAS

RAS

WE

Table 26. I/O Timing—DDR SDRAM Write Timing T and T

SD

HD

Notes:

1. T_SDand T_HDare measured under worst case conditions.

2. Clock speed for the values in the table is 200MHz.

3. The time values in the table include 1/4 of a cycle at 200MHz (5ns x 0.25 = 1.25 ns).

4. To obtain adjusted T_SDand T_HDvalues for lower clock frequencies, subtract 1.25 ns from the values in the table and add 1/4

of the cycle time for the lower clock frequency (for example, T_SD− 1.25 + 0.25T_CYC).

T_SD(ns)

T_HD(ns)

Signal Names

MemData00:07, DM0

MemData08:15, DM1

MemData16:23, DM2

MemData24:31, DM3

ECC0:7, DM4

Reference Signal

DQS0

1.067

1.074

1.082

1.088

1.012

0.973

DQS1

DQS2

DQS3

DQS4

DDR SDRAM Read Operation

Data on a read is edge aligned with DQS. To capture the incoming data on the rising and falling edges, DQS is

delayed by the DDR controller in order to center a DQS edge on valid data. Programmable registers control the

delay.

DDR SDRAM MemClkOut0 and Read Clock Delay

In order to accommodate timing variations introduced by memory layout and process, a three-stage data path is

used to eliminate metastability and allow data sampling to be adjusted for minimum latency.

Figure 9 shows the data read path of a single data bit. Data entering on the left is captured in the Stage 1 Flip

Flops. Four Flip Flops are needed to capture an entire four beat burst on the DDR interface. The DDR controller

only supports burst of four. Data captured on the rising edge of DQS is stored in the even numbered Flip Flops.

Like wise, data captured on the falling edge of DQS is stored in the odd numbered Flips Flops.

To latch the data in Stage 1, a delayed version of DQS is used. Initialization software is responsible for tuning the

DQS delay timing so that DQS is centered on valid data. Since there is process variation between parts and

possible voltage variations on boards, read tuning is required. Fixed DQS delay values should not be used on

production systems.

The Feedback Data Capture Window selects which Flip Flop is used to store the data sampled by DQS. Each

output of this block generates a pulse to an input multiplexer. The series of four pulses selecting the input

multiplexer is initiated by a feedback signal pulse on the input of the Feedback Data Capture Window. The DDR

controller calculates when to assert the feedback signal based on when the data should be present after a read

command.

The width of the feedback pulse is the same as DDR 1X clock. The internal DDR 1X clock is the same frequency

as MemClkOut0. MemClkOut0 is slightly delayed relative to DDR 1X clock due to the insertion delay of the drivers.

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Data Sheet

The feedback signal to the Feedback Data Capture Window is adjusted for propagation delay by the fine/coarse

delays and is automatically adjusted for variations in the DDR I/O due to supply voltage and temperature.

Compensation for driver/receiver variations is accomplished by driving and receiving the feedback signal on the

external MemFBD and MemFBR pins. Tuning the fine/coarse delays adjust for propagation delay. When properly

tuned, the feedback pulse is aligned to the first DQS in a four-beat burst such that the rising edge of DQS is

nominally centered on the feedback pulse. Software must adjust the pulse using the fine/coarse delays when

tuning read DQS delay.

Note: Using minimum trace length, connect MemFBD directly to MemFBR.

The data captured in Stage 1 is relative to the DQS timing domain and is held for four DDR 1X cycles. Stage 2

samples the data in Stage 1 attempting to capture the data in the DDR 1X domain. The on-time-sample clock from

the Stage 2 Store block samples the Stage 1 data at sample cycle T1, T2, T3, or T4. The sample cycle is either

selected by initialization software or can be automatically selected and adjusted by the DDR controller. The Stage

1 data is sampled a second time by the over sample clock at a delayed sample point. The delay between the on-

time-sample and over sample clocks is the Over-Sampling-Guard-Band.

The feedback pulse is sampled with the data captured by the first DQS in the four beat burst. A match of one or

both of the sample clocks with the feedback pulse is a hit. The DDR controller based on hits or misses by the on-

time sample and over sample clocks adjust the sample cycle in order to track variations in DQS. Burst data from a

sample hit is passed to Stage 3.

In Stage 3 the data is synchronized to the PLB clock domain and eventually driven onto the PLB bus. The data

captured on the rising and falling DQS edges is unpacked into the correct bit locations on the upper (0:63) and

lower (64:127) PLB bus. When ECC is enable, ECC checking and corrections is done after Stage 3.

Figure 11 illustrates how the three-stage read logic captures the data in the DQS timing domain and synchronizes

it to the PLB clock domain. The first DQS of four beat burst is roughly centered on feedback signal pulse.

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Data Sheet

Figure 9. DDR SDRAM Read Data Path for a Single Data Bit

FF: Flip-Flop

DDR 1X Clock

Ext FeedBack

Signals

Driver

MemFBD

FeedBack

Signal Gen

Coarse Delay

Read Start

CAS Lat Delay

DDR 1X Clock

Read Latency adjust circuit

Rec

Stage 2 Store

Oversampling

Fine Delay

MemFBR

Fine Delay

(Guard Band)

DQS aligned

feedback signal

Cycles

Delay

+1

Feedback

T1 T2 T3 T4

On-time sample clock

Data Capture

Window

Adjust

Oversampling

Clock

0

1

2

Q2_Ovs

3

Package

pins

0

2

FF

Q3

Compare

FF

Q2

PLB bus

FF

(x64+ECC)

D

Read FIFO

[0:63]

Mux

C

Mux

Upper

DQS Rising

Edge Sync

MemData

Stage 2

Stage 3

Stage 1

Lower

(x32 bits +

x8 bits ECC)

FF

Q3

1

3

(x64+ECC)

Q2

PLB bus

FF

D

[64:127]

Mux

C

Mux

Programmed

Read DQS

Delay

DQS Falling

Edge Sync

DQS

(x4 + x1

ECC bits)

DDR 1X Clock

PLB 1X Clock

ECC detection and correction if enabled occurs after Stage 3 before completing the read on the PLB.

DDR SDRAM Read Cycle Timing

The following diagram illustrates the relationship of the signals involved with a DDR read operation.

Figure 10. DDR SDRAM Memory Data and DQS

DQS

T

SD

MemData

T

HD

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Data Sheet

Table 27. I/O Timing—DDR SDRAM Read Timing T and T

SD

HD

1. T_SDand T_HDare measured under worst case conditions.

2. Clock speed for the values in the table is 200MHz.

3. The time values in the table include 1/4 of a cycle at 200MHz (5ns x 0.25 = 1.25 ns).

4. To obtain adjusted T and T values for lower clock frequencies, subtract 0.75 ns from the values in the table and add 1/4

SD

HD

of the cycle time for the lower clock frequency (e.g., T

- 1.25 + 0.25T

).

SD

CYC

Read Data vs DQS Set up

T_SD(ns)

Read Data vs DQS Hold

T_HD(ns)

Signal Names

MemData00:07

Reference Signal

DQS0

DQS1

DQS2

DQS3

DQS4

0.27

0.45

MemData08:15

MemData16:23

MemData24:31

ECC0:7

In the following example, the data strobes (DQS) and the data are shown to be coincident. There is actually a slight

skew as specified by the SDRAM specifications, and there can be additional skew due to loading and signal

routing. It is recommended that the signal length for all of the DQS signals be matched.

The following example shows the timing relationship between SDRAM DDR Data at the input pin and storing the

data in Stage 1.

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Data Sheet

Figure 11. DDR SDRAM Read Cycle Timing—Example

Oversampling Guard Band

DDR 1X Clock

DDR 2X Clock

MemClkOut0 (Diff.)

DQS at Pin

MemData at Pin

MemFBR at Pin

D0

D2

D3

D4

D5

D6

D7

D8

D9

D1

Store 1st Data

in Stage 2

T1

T2

T3

T4

DDR 1X Clock cycle

Delayed DQS

Data Out Stage 1 (0)

Data Out Stage 1 (1)

Data out Stage 1 (2)

Valid

High

Low

D0

D1

D2

D3

Data Out Stage 2

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PCI Express (PCI-E) I/O Specifications

Data Sheet

The following tables provide the required I/O timing information regarding the use of the PCI Express interface on

this chip.

Table 28. PCI-E Receiver I/O Specifications

Parameter

Minimum

Maximum

Units

ps

Notes

Unit Interval (UI)

399.88

175

0.4

-

400.12

Differential Rx peak-peak voltage

Receiver eye time opening

1200

-

mV

UI

Maximum time delta between median and deviation from median

Rx differential return loss

0.3

-

UI

10

dB

Ω

Common mode Rx return loss

6

-

Receiver DC common mode impedance

DC differential impedance

40

60

120

150

-

80

Ω

Rx AC common mode voltage

-

mV

kΩ

ns

DC Input CM input impedance during reset or power down

Electrical idle detect threshold

200

65

125

Table 29. PCI-E Reference Clock I/O Specifications

Parameter

Minimum

100

Maximum

100

Units

MHz

ppm

%

Notes

PCI_E reference clock frequency (PCIEnClkC and PCIEnClkT )

1

Accuracy

-300

+300

55

Duty cycle

45

-6

-

86

ps

3

2

Peak-to-peak jitter for 1E-6 BER (1 x 10 bit error rate)

Spread Spectrum Clock (SSC) frequency

Common mode voltage

Differential signal amplitude

Notes:

30

0

33

kHz

mV

1600

200

1. The PCI-E reference clock frequency specification does not include +/- 300ppm accuracy specification.

2. The data rate can be modulated from +0.5% to −0.5% of the nominal data rate frequency, at a modulation rate in the range not

exceeding 30kHz–33kHz. The +/- 600ppm requirement remains which requires the two communicating ports to be modulated so that

they never exceed a total of 600ppm difference. For most implementations, this requires that both ports have the same bit rate clock

source when the data is modulated with an SSC.

3. 1E-6 is the probability that the jitter is greater than 86ps peak-to-peak.

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Data Sheet

Table 30. PCI-E Transmitter I/O Specifications

Parameter

Minimum

399.88

800

Maximum

Units

ps

Notes

Unit Interval (UI)

400.12

Differential p-p Tx voltage swing

Low power differential p-p Tx voltage swing

Tx de-emphasis level ratio

-

mV ppd

dB

400

-

-4.0

-

-3.0

Minimum Tx eye width

0.75

UI

Maximum time between the jitter median and maximum

deviation from the median

-

0.125

UI

Transmitter rise and fall time

Maximum Tx PLL bandwidth

Minimum Tx PLL BW for 3dB peaking

Tx AC common mode voltage

0.125

-

UI

-

1.5

-

22

-

MHz

mV

20

Absolute Delta of DC Common Mode Voltage during L0 and

Electrical Idle.

0

100

mV

Absolute Delta of DC Common Mode Voltage between PCIEnTx

and PCIEnTx

0

-

25

20

mV

Electrical Idle Differential Peak Output Voltage

The amount of voltage change allowed during Receiver

Detection

600

Transmitter DC common-mode voltage

Transmitter short-circuit current limit

Minimum time spent in Electrical Idle

0

-

3.6

90

-

V

mA

ns

20

Maximum time to transition to a valid Electrical Idle after sending

an EIOS

-

8

ns

Maximum transition time to valid differential signaling after

leaving Electrical Idle

Differential return loss

10

6

-

dB

Ω

Common mode return loss

DC differential Tx impedance

80

120

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Initialization

Data Sheet

The following describes the method by which initial chip settings are established when a system reset occurs.

Strapping

When the SysReset input is driven low (system reset), the state of certain I/O pins is read in order to enable default

initial conditions before PPC405EX start-up. The actual instant of capture is the nearest system clock edge before

the deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-down (logical 0)

resistors to select the desired default conditions. The recommended pull-up is 3kΩ to +3.3V, or 10kΩ to +5V. The

recommended pull-down is 1kΩ to GND. These pins are only used for strap functions during reset. They are used

for other signals during normal operation. The following table lists the strapping pins along with their functions and

strapping options. The signal names assigned to the pins for normal operation appear below the pin number.

Table 31. Strapping Pin Assignments

Pin Strapping

F04

(UART0DCD)

F02

(UART0DSR)

G02

(UART0CTS)

Initialization Source

EBC 8-bit wide ROM

Option

A

B

C

D

E

G

F

0

1

0

1

0

1

0

1

0

1

0

1

0

1

EBC 16-bit wide ROM

EBC 8-bit wide NAND Flash

IIC ROM at address 0xA8

EBC 8-bit wide ROM

IIC ROM at address 0xA4

H

Note: See the PPC405EX Embedded Processor User’s Manual for option descriptions and other details regarding the boot process.

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Revision Log

Data Sheet

Date

Version

1.00

Contents of Modification

02/27/2007

03/01/2007

Initial creation of document.

1.01

Updates following review of initial document.

Change package drawing to eliminate confusion.

Expand system memory map.

Define FSource0 signal as Reserved.

Add Recommended Operating Conditions data.

Add thermal data.

03/22/2007

04/24/2007

1.02

1.03

Misc. updates and additions.

Misc. updates and additions including some limited timing data.

Correct one of three ball numbers assigned to PerData28.

Swap four balls between V_DDand GND.

Swap one ball between OV_DDand SV_DD

Correct typographical errors in Table 3.

.

05/24/2007

1.04

Add missing alphabetical entries for PerAddr05, NAND Flash, and IIC1.

Add output current values to Tables 15 and 16.

Input various review comments.

Update Table 6 Notes column.

Update Block Diagram.

Swap SAV_DDan EAV_DDsignal name assignments on package balls.

06/04/2007

1.05

Add two UART configurations.

Add DDR SDRAM section extracted from 460EX with changes appropriate for 405EX.

Update timing information for all interfaces.

Add power values.

Update I/O capacitance values.

Remove Confidential status.

06/07/2007

06/28/2007

1.06

1.07

Input various review comments.

Input review comments and corrections.

Change default signals for GPIO balls to GPIO00–GPIO27 signals.

Eliminate confusing terminology in initialization section.

Change voltage names so that SDRAM voltage is always SV_DDfor both DDR1 and DDR2 types.

07/12/2007

08/21/2007

1.08

1.09

Six voltage pins originally labeled SV_DDchanged to EOV_DD

.

Update GMCRefClk specifications (rise time, jitter, etc.)

Add I/O timing figures for RGMII signals.

Correct AMCC telephone numbers.

Change PerErr to always pull down.

Implement Doc Issue 374.

Change chip revision level from A to B (Doc issue 380).

Implement Doc Issue 381.

10/25/2007

11/20/2007

1.11

1.12

Revise I/O timing figures for RGMII signals.

Major updates to DDR SDRAM section (and other parts of the DS) (Doc Issue 392).

Add PCI-E I/O specifications.

I/O timing values updates.

Change boot-from-EBC support (Doc Issue 383).

Misc. updates.

Change all 667 MHz specs to 600 MHz.

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Data Sheet

Date

Version

Contents of Modification

Misc. updates.

Change all 667 MHz specs to 600 MHz.

12/06/2007

1.13

Document Issues 412 and 435 implemented (includes removal of 333MHz parts and tape-and-

reel packaging).

Misc. updates from Doc Issue 440.

01/04/2008

01/15/2008

1.14

1.15

Note: Automatic change bars are now included on all changes.

Package tolerance update.

Implemented Doc Issue 447:

Supply voltage changes (wider voltage range with increased power consumption).

Remove common mode voltage specs.

Change DDR SDRAM and PCI-E specs.

01/16/2008

02/11/2008

02/15/2008

03/19/2008

1.16

1.17

1.18

1.19

Correct voltage changes.

Update SDRAM write timing.

Update PCIEnClk signal description.

Increase PCI-E differential signal amplitude to 1600mV (Doc Issue 468).

Change power consumption numbers from estimated to measured.

Misc. updates in Doc Issue 482.

Remove GMCMDIO timing numbers (Doc Issue 495).

Correct bracket placement on signal name (Doc Issue 500).

Add power sequence information (Doc Issue 509).

Misc. updates.

05/02/2008

07/09/2008

1.20

1.21

Updated part numbers, revision level, and PVR.

Added extended temperature operation of 533MHz part at 400MHz or less.

Added maximum power for each speed.

Added some functional unit power consumption figures.

Change part number nomenclature.

Doc Issue 548.

Bugzilla Issue 5097. Change RGMII I/O timing.

Remove Preliminary designation.

Update GMII and RGMII timing.

11/11/2008

01/28/2009

1.22

1.23

Bugzilla Issue 5170. Update GMII and RGMII timing.

Bugzilla Issue 5389. Added new row and footnote at the bottom of Table 18.

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Data Sheet

Applied Micro Circuits Corporation

215 Moffett Park Drive, Sunnyvale, CA 94089

Phone: (408) 542-8600 — (800) 840-6055 — Fax: (408) 542-8601

http://www.amcc.com

AMCC reserves the right to make changes to its products, its datasheets, or related documentation, without notice and war-

rants its products solely pursuant to its terms and conditions of sale, only to substantially comply with the latest available

datasheet. Please consult AMCC’s Term and Conditions of Sale for its warranties and other terms, conditions and limitations.

AMCC may discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest

version of relevant information to verify, before placing orders, that the information is current. AMCC does not assume any lia-

bility arising out of the application or use of any product or circuit described herein, neither does it convey any license under

its patent rights nor the rights of others. AMCC reserves the right to ship devices of higher grade in place of those of lower

grade.

AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE

SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL

APPLICATIONS.

AMCC is a registered Trademark of Applied Micro Circuits Corporation.

74

AMCC Proprietary

Product Change Notification: 110209-02

Update 11/19/09: Implementation and First Shipment date changed from February 13, 2009 to

February 13, 2010.

Product Change Notification Date

Product Change Title

November 13, 2009

PPC405EX and PPC405EXr Transition from revision C to revision D

All 405EX and 405EXr revision C part numbers.

See ‘From’ part numbers in the next section.

Affected Part Number List

From:

To:

PPC405EX-SSD400T

PPC405EX-SSD533T

PPC405EX-SSD600T

PPC405EX-NSD400T

PPC405EX-NSD533T

PPC405EX-NSD600T

PPC405EX-SPD400T

PPC405EX-SPD533T

PPC405EX-SPD600T

PPC405EX-NPD400T

PPC405EX-NPD533T

PPC405EX-NPD600T

PPC405EXr-SSD333T

PPC405EXr-SSD400T

PPC405EXr-SSD533T

PPC405EXr-NSD333T

PPC405EXr-NSD400T

PPC405EXr-NSD533T

PPC405EXr-SPD333T

PPC405EXr-SPD400T

PPC405EXr-SPD533T

PPC405EXr-NPD333T

PPC405EXr-NPD400T

PPC405EXr-NPD533T

PPC405EX-SSC400T

PPC405EX-SSC533T

PPC405EX-SSC600T

PPC405EX-NSC400T

PPC405EX-NSC533T

PPC405EX-NSC600T

PPC405EX-SPC400T

PPC405EX-SPC533T

PPC405EX-SPC600T

PPC405EX-NPC400T

PPC405EX-NPC533T

PPC405EX-NPC600T

PPC405EXr-SSC333T

PPC405EXr-SSC400T

PPC405EXr-SSC533T

PPC405EXr-NSC333T

PPC405EXr-NSC400T

PPC405EXr-NSC533T

PPC405EXr-SPC333T

PPC405EXr-SPC400T

PPC405EXr-SPC533T

PPC405EXr-NPC333T

PPC405EXr-NPC400T

PPC405EXr-NPC533T

Description of Change

(Part Number From/To)

Errata Fixes (Reference PPC405EX and PPC405EXr errata for

details.)

Description of Change

Die revision transition from Rev C (Rev1.2) to Rev D (Rev1.3)

6310 Sequence Drive, San Diego, CA 92121 (858) 450-9333 Fax (858) 450-9885 http://www.appliedmicro.com

Reason for Change

Errata Fixes.

Qualification/Test Data

Sample Availability Date

Available upon request

Available Now

February 13, 2010. After this date, orders of the older version

(Rev. C) will only be accepted based on available inventory.

Implementation Date

First Shipment Date

February 13, 2010

This form is the official notification of this change. Please review this

PCN carefully. If there are any concerns, please notify your AMCC

Sales Representative, Sales Manager or Field Applications Engineer

within 30 days. Automatic acceptance of this change shall be

assumed if no written objection is received.

Expected Customer Actions

Contact for Inquiries

Please direct sample requests to your Inside Sales Representative or

go to http://www.appliedmicro.com/Sales/SampleRequest.html

slsmith@amcc.com

6310 Sequence Drive, San Diego, CA 92121 (858) 450-9333 Fax (858) 450-9885 http://www.appliedmicro.com


型号：	PPC405EX-SSC400T
厂家：	APPLIED MICRO CIRCUITS CORPORATION
描述：	RISC Microprocessor, 32-Bit, 400MHz, CMOS, PBGA388, 27 X 27 MM, ROHS COMPLIANT, PLASTIC, MS-034C, EBGA-388
文件：	总76页 (文件大小：1242K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PPC405EX-SSC400T [AMCC]

相关型号：

PPC405EX-SSC533T

PPC405EX-SSC600T

PPC405EX-SSD400T

PPC405EX-SSD533T

PPC405EX-SSD600T

PPC405EXR-NPB400T

PPC405EXR-NPB533T

PPC405EXR-NPC400T

PPC405EXR-NPC533T

PPC405EXR-NPD400T

PPC405EXR-NPD533T

PPC405EXR-NSB533T