PPC405EXR-SSB533T [AMCC]
RISC Microprocessor, 32-Bit, 533MHz, CMOS, PBGA388, 27 X 27 MM, 1 MM PITCH, PLASTIC, ROHS COMPLIANT, MS-034C, BGA-388;型号: | PPC405EXR-SSB533T |
厂家: | APPLIED MICRO CIRCUITS CORPORATION |
描述: | RISC Microprocessor, 32-Bit, 533MHz, CMOS, PBGA388, 27 X 27 MM, 1 MM PITCH, PLASTIC, ROHS COMPLIANT, MS-034C, BGA-388 |
文件: | 总73页 (文件大小:1036K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Part Number 405EXr
Revision 1.09 - May 2, 2008
Preliminary Data Sheet
405EXr
PowerPC 405EXr Embedded Processor
Features
®
• One one-lane PCI Express interfaces operating up
to 2.5 Gbps
• AMCC PowerPC 405 32-bit RISC processor core
operating from 333MHz to 533MHz including
16KB I- and D-caches with parity checking
• One Gigabit Ethernet interfaces (half- and full-
duplex) to external PHY (GMII/MII/RGMII)
• On-chip 128-bit processor local bus (PLB)
operating up to 200MHz
• USB 2.0 OTG port configurable as either Host or
Device
• On-chip 32-bit peripheral bus (OPB) operating up
to 100 MHz
• Programmable universal interrupt controller (UIC)
• General Purpose Timer (GPT)
• External 8-,16-, or 32-bit peripheral bus (EBC)
operating up to 100MHz
• Up to two serial ports (16750 compatible UART)
• External bus master (EBM) operating up to
100MHz
• Two IIC interfaces operating up to 400kHz and
supporting all standard IIC EEPROMs
• On-chip Security feature with True Random
Number generation
• One SCP (SPI) synchronous full-duplex channel
operating up to 25MHz
• Eight- and 16-bit NAND Flash interface
• Inter-chip connectivity (SCP and IIC)
• General purpose I/Os (GPIOs), each with
programmable interrupts and outputs
• Boot from NOR Flash on the external peripheral
bus or NAND Flash on the NAND Flash interface
• Supports JTAG for board-level testing
• System power management, low power
dissipation and small form factor
• DMA (4-channel) support for all on-chip slaves
and external bus, UARTs, and devices on the EBC
• Available in a RoHS compliant (lead-free) package
• DDR1/2 SDRAM interface operating up to 400
Mbps
Description
With speeds up to 533MHz, a flexible off-chip memory
architecture, and a diverse communications package
that includes PCI Express, USB 2.0 OTG, and
10/100/1000 Ethernet, the PowerPC 405EXr
in need of performance and connectivity
improvements.
Technology: Cu-08 CMOS, 90nm
embedded processor provides a low power and small
footprint system-on-a-chip (SOC) solution for a wide
range of high performance, cost-constrained
Package: 388-ball, 27mm × 27mm, enhanced plastic
ball grid array (EPBGA), 1mm ball pitch
embedded applications. This includes wireless LAN
applications, security appliances, internet appliances,
line cards, and intelligent USB peripherals. It is an
easily programmable general purpose, 32-bit RISC
controller that offers an upgrade path for applications
Power consumption (est.): less than 1.5W, typical
Voltages required: 3.3V, 2.5V, 1.8V (DDR2 SDRAM
only), and 1.2V
AMCC Proprietary
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Revision 1.09 - May 2, 2008
PPC405EXr – PowerPC 405EXr Embedded Processor
Table of Contents
Preliminary Data Sheet
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Ordering, PVR, and JTAG Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Address Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
PowerPC 405 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Internal Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
External Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
NAND Flash Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
USB 2.0 OTG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
DDR1/2 SDRAM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Security Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
IIC Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Serial Communication Port Interface (SCP/SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
General Purpose I/O (GPIO) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Universal Interrupt Controller (UIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Ethernet Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Signal Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Signal Functional Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Ratings and Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Spread Spectrum Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
DDR 2/1 SDRAM I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
PCI Express (PCI-E) I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
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AMCC Proprietary
Revision 1.09 - May 2, 2008
PPC405EXr – PowerPC 405EXr Embedded Processor
List of Figures
Preliminary Data Sheet
Figure 1. PPC405EXr Embedded Controller Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Package 27mm, 388-Ball EPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 3. Clocking Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 4. Input Setup and Hold Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 5. Output Delay and Float Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 6. Input Setup and Hold Timing Waveform for RGMII Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 7. Output Delay and Hold Timing Waveform for RGMII Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 8. DDR SDRAM Simulation Signal Termination Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 9. DDR SDRAM Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 10. DDR SDRAM Read Data Path for a Single Data Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 11. DDR SDRAM Memory Data and DQS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 12. DDR SDRAM Read Cycle Timing—Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
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PPC405EXr – PowerPC 405EXr Embedded Processor
List of Tables
Preliminary Data Sheet
Table 1. System Memory Address Map (4GB System Memory) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. DCR Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. Signals Listed Alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 4. Signals Listed by Ball Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 5. Pin Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 6. Non-Functional Ball Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 7. Signal Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 8. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 9. Package Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 10. Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 11. I/O Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 12. Typical DC Power Supply Requirements with DDR1 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 13. Typical DC Power Supply Requirements with DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 14. DC Power Supply Loads with DDR1 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 15. DC Power Supply Loads with DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 16. System Clocking Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 17. Peripheral Interface I/O Clock Timings (not SDRAM or PCI-E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 18. I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 19. DDR SDRAM Output Driver Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 20. DDR SDRAM Write Operation Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 21. I/O Timing—DDR SDRAM T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
DS
Table 22. I/O Timing—DDR SDRAM T and T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
HA
SA
Table 23. I/O Timing—DDR SDRAM Write Timing T and T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
SD
HD
HD
Table 24. I/O Timing—DDR SDRAM Read Timing T and T
SD
Table 25. PCI-E Receiver I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 26. PCI-E Reference Clock I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 27. PCI-E Transmitter I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 28. Strapping Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
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PPC405EXr – PowerPC 405EXr Embedded Processor
Ordering, PVR, and JTAG Information
Preliminary Data Sheet
This section provides the part number nomenclature. For availability, contact your local AMCC sales office.
Order Part Number
Rev
Level
Product Name
Package
PVR Value
JTAG ID
(see Notes:)
PPC405EXr
PPC405EXr
PPC405EXr-SpBfffT
PPC405EXr-NpBfffT
27mm, 388-ball, EPBGA
27mm, 388-ball, EPBGA
A
A
0x12911473
0x12911471
0x1405B1E1
0x1405B1E1
Notes:
1. S = security feature present, N = security feature not present
2. p = Package: S = lead-free (RoHS compliant), P = leaded
3. B = Chip revision level A
4. fff = Processor frequency
333 = 333MHz
400 = 400MHz
533 = 533MHz
5. T = Case temperature range, -40°C to +85°C
The part number contains a part modifier. Included in the modifier is a revision code. This refers to the die mask
revision number and is specified in the part numbering scheme for identification purposes only.
The PVR (Processor Version Register) and the JTAG ID register are software accessible (read-only) and contain
information that uniquely identifies the part. See the PPC405EXr Embedded Processor User’s Manual for details
about accessing these registers.
Order Part Number Key
PPC405EXr-SSB533T
AMCC Part Number
Case Temperature Range
Processor Speed (MHz)
Security
Chip Package
Revision Level
Note: The example P/N above has the security feature, is lead-free, capable of running at 533MHz,
and is shipped in a tray (tape-and-reel packaging is not available).
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PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
Block Diagram
Figure 1. PPC405EXr Embedded Controller Functional Block Diagram
Universal
Interrupt
Controller
x3
Clock
Control
Reset
Power
Mgmt
Timers
MMU
NAND
Flash
Controller
DCRs
EBC
EBM
IICx2/ SCP
BSC
UART
x2
GPIO
Power PC
405 Processor
(SPI)
DCR
Bus
Arbiter
Trace
16KB D-Cache 16KB I-Cache
JTAG
On-chip Peripheral Bus (OPB)
OPB/PLB
Bridges
GPT
PKA
TRNG
Processor Local Bus (PLB4)—128 bits
Arbiter
PCI-E
DMA
DDR1/2
SDRAM
AHB-PLB
Bridge
EIP-94
Security
MAL/w
Interrupt Coalescing
1-lane
Controller
(4-Channel)
Controller
Feature
Ethernet
MAC
1Gbit
USB 2.0
OTG
Controller
HSS
ULPI
The PPC405EXr is designed using the IBM Microelectronics Blue LogicTM methodology in which major functional
blocks are integrated together to create an ASIC (application-specific integrated circuit) product. This approach
provides a consistent way to create complex ASICs using IBM CoreConnectTM Bus Architecture.
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PPC405EXr – PowerPC 405EXr Embedded Processor
Address Maps
Preliminary Data Sheet
The PPC405EXr incorporates two address maps. The first address map defines the possible use of addressable
memory regions that the processor can access. The second address map defines Device Configuration Register
(DCR) addresses (numbers). The DCRs are accessed by software running on the PPC405EXr processor through
the use of mtdcr and mfdcr instructions.
Table 1. System Memory Address Map (4GB System Memory)
Function
Local Memory
Subfunction
DDR 2/1 SDRAM
Start Address (Hex)
0 0000 0000
0 8000 0000
0 9000 0000
0 EF60 0000
0 EF60 0200
0 EF60 0208
0 EF60 0300
0 EF60 0308
0 EF60 0400
0 EF60 0420
0 EF60 0500
0 EF60 0520
0 EF60 0600
0 EF60 0606
0 EF60 0700
0 EF60 0740
0 EF60 0800
0 EF60 0880
0 EF60 0900
0 EF60 0A00
0 EF60 0B00
0 EF60 0C04
0 EF61 0000
0 EF62 0000
0 EF62 0100
0 EF6C 0000
0 EF70 0000
0 EF78 0000
0 F000 0000
0 FFE0 0000
End Address (Hex)
0 7FFF FFFF
0 8FFF FFFF
0 EF5F FFFF
0 EF60 01FF
0 EF60 0207
0 EF60 02FF
0 EF60 0307
0 EF60 03FF
0 EF60 041F
0 EF60 04FF
0 EF60 051F
0 EF60 05FF
0 EF60 0605
0 EF60 06FF
0 EF60 073F
0 EF60 07FF
0 EF60 087F
0 EF60 08FF
0 EF60 09FF
0 EF60 0AFF
0 EF60 0C03
0 EF60 FFFF
0 EF61 FFFF
0 EF62 00FF
0 EF6B FFFF
0 EF6F FFFF
0 EF77 FFFF
0 EFFF FFFF
0 FFDF FFFF
0 FFFF FFFF
Size
2GB
EBC
256MB
1.5GB
512B
8B
PCI Express
GPT
UART 0
Reserved
UART 1
248B
8B
Reserved
IIC 0
248B
32B
Reserved
IIC 1
224B
32B
Reserved
SCP
224B
6B
OPB Peripherals
Reserved
OPB Arbiter
Reserved
GPIO
250B
64B
192B
128B
128B
256B
256B
260B
62KB
64KB
256B
640KB
256KB
512KB
8.9MB
254MB
2MB
Reserved
Ethernet 0
Reserved
RGMII Bridge
Reserved
PKA +TRNG
PCI Express Interrupt Handler
Reserved
USB OTG
Security
PLB/AHB Peripherals
Reserved
EBC Memory
EBC Memory—Boot ROM
EBC
Notes:
1. If peripheral bus boot is selected, peripheral bank 0 is automatically configured at reset to the address range listed above.
2. After the boot process, software may reassign the boot memory regions for other uses.
3. PCI Express can use PLB address range 0x1 0000 0000 to 0xF FFFF FFFF even though the CPU can not access it.
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PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
Table 2. DCR Address Map
Function
1
Start Address (Hex)
0x000
End Address (Hex)
0x3FF
Size
1KW (4KB)1
Total DCR Address Space
Reserved
000
00C
00E
010
012
014
016
020
030
040
060
080
090
0A0
0A8
0B0
0B3
0C0
0D0
0E0
0F0
100
140
180
200
00B
00D
00F
011
013
015
01F
02F
03F
05F
07F
08F
09F
0A7
0AF
0B2
0BF
0CF
0DF
0EF
0FF
13F
17F
1FF
3FF
CPR (Clocking Power-on Reset)
System DCRs
DDR 2/1 SDRAM Controller
External Bus Controller (EBC)
External Bus Master (EBM)
Reserved
2W
2W
2W
2W
2W
PLB4XAHB Bridge
Reserved
16W
32W
PCI Express 0
Reserved
PLB4 Arbiter
16W
16W
8W
PLB-to-OPB Bridge
OPB-to-PLB Bridge
Reserved
Power Management
Reserved
3W
UIC 0
16W
16W
16W
UIC 1
UIC 2
Reserved
DMA
64W
Reserved
Ethernet MAL
Reserved
128W
Notes:
1. A DCR address is 10 bits (1024 or 1K unique addresses). Each unique address represents a single 32-bit (word) register, or one kiloword
(KW) (which equals 4KB).
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PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
PowerPC 405 Processor
The PPC405 processor is a fixed-point, 32-bit RISC unit.
Features include:
• Five-stage pipeline with single-cycle execution of most instructions, including loads and stores
• Separate, configurable 16 KB D- and I-caches, both two-way set associative
• Thirty-two 32-bit general purpose registers (GPRs)
• Unaligned load/store support
• Hardware multiply/divide
• Parity detection and reporting for the instruction cache, data cache, and translation look-aside buffer (TLB)
• Double word instruction fetch from cache
• Translation of the four GB logical address space into physical addresses
• Built-in timer and debug support
• Power management
• DCR interface is 32 bits wide
• Selectable processor vs. bus clock ratios (N:1 ratio only, where N =1, 2, 3,or 4 )
Internal Buses
The PPC405EXr contains four internal buses: the processor local bus (PLB), the Advanced High-Performance Bus
(AHB), the on-chip peripheral bus (OPB), and the device control register (DCR) bus. High performance devices
such as the processor, the DDR SDRAM memory controller, PCI Express, the Ethernet MAL, and DMA utilize the
PLB. Lower bandwidth I/O interfaces such as communications and timer interfaces utilize the OPB. The daisy-
chained DCR bus provides a lower bandwidth path for passing status and control information between the
processor and the other on-chip peripheral functions.
PLB
The Processor Local Bus (PLB) is a high-performance on-chip bus used to connect PLB-equipped master and
slave devices to the PPC405 CPU. It provides a 128-bit data path with 64-bit addressing and operates up to
200MHz. There are bridges between the PLB and the OPB.
Features include:
• Separate and simultaneous 6.4GB/s read and write data paths
• Decoupled address and data buses
• Address pipelining
• Late master request abort capability
• Hidden (overlapped) bus request/grant protocol
• Bus arbitration-locking mechanism
• Byte-enable capability allows for unaligned half word transfers and 3-B transfers
• Support for 32- and 64-B burst transfers
• Read word address capability
• Sequential burst protocol
• Guarded and unguarded memory transfers
• Simultaneous control, address, and data phases
• DMA buffered, flyby, peripheral-to-memory, memory-to-peripheral, and DMA memory-to-memory operations
AHB
The Advanced High-Performance Bus (AHB) is dedicated to the USB OTG 2.0.
Features include:
• 32-bit data path
• 32-bit address
• Synchronous to the PLB
• From 60MHz to 100MHz.
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PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
OPB
The OPB provides 32-bit address and data interfaces, and operates up to 100MHz. There are bridges between the
OPB and the PLB.
Features include:
• Pipelined read support
• Dynamic bus sizing
• Single-cycle data transfer between masters and slaves
DCR Bus
The daisy-chained DCR bus provides a path for passing status and control information between the processor core
and the other on-chip cores. All DCRs are 32 bits in width with 10-bit addressing.
External Bus Controller
The external bus controller (EBC and EBM) transfers data between the PLB and external memory or peripheral
devices attached to the external peripheral bus. The EBC provides direct attachment of memory devices such as
ROM and SRAM, DMA device paced memory devices, and DMA peripheral devices.
Features include:
• Up to 33MHz to 100 MHz speed
• Data bus is 8, 16, or 32 bits with a 27-bit address bus
• Up to four chip selects
• Arbitration and multi-master supported
• Flash ROM interface
• Boot from 8- or 16-bit NOR flash support
• Direct support for 8-,16-, or 32-bit SRAM and external peripherals
• External bus master support
NAND Flash Controller
The NAND Flash controller (NDFC) provides a simple interface between the External Bus Controller (EBC) and a
variety of NAND Flash-based storage devices.
Features include:
• Attachment as internal EBC slave device
• Eight- and 16-bit NAND Flash interface
• Up to four banks of NAND Flash supported
• Device sizes:
– 4MB and larger supported for read/write access
– 4MB to 256MB supported for boot-from-NAND flash (size supported depends on addressing mode)
• 512B + 16B or 2kB + 64B device page sizes supported
• ECC generation - hamming code, single-bit correction, double-bit detection (SEC/DED)
• Eight-bit command write, address write, and data read/write
• Interrupt on device ready (after long page write or block erase operations)
• Boot from NAND
– Executes up to 4KB of boot code out of first block
– Automatic page read accesses performed based on device configuration and read address
DMA Controller
The Direct Memory Access (DMA) controller is a Processor Local Bus (PLB) master that enables faster data
transfer between memory and peripherals than is possible under program control. The 4-channel DMA controller
handles data transfers between memory and peripherals and from memory-to-memory. Each channel has an
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PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
independent set of registers needed for data transfer: a control register, a source address register, a destination
address register, and a transfer count register.
Features include:
• Memory-to-memory transfers
• Buffered memory-to-peripheral transfers
• Buffered peripheral-to-memory transfers
• Four independent DMA channels
• Scatter/gather capability for dynamically programming multiple DMA transfers
• Programmable address increment or decrement
• Internal data buffering
• Can transfer data to/from any PLB slave, including the external bus
USB 2.0 OTG Interface
One USB 2.0 On-the-Go (OTG) controller that can be configured as either a Host or Device port.
Features include:
• Low- (Host only), Full- and High-Speed support
• Internal DMA to optimize performance and offload the CPU
• Up to two IN/OUT Endpoints in Device mode (one can be isochronous)
• Supports maximum packet size of 1024B (isochronous) and 512B (bulk)
• Support for isochronous traffic
• Three packets per microframe (24MB/s throughput)
• Eight KB buffer
• ULPI SDR interface
DDR1/2 SDRAM Controller
The Double Data Rate 1/2 (DDR1/2) SDRAM memory controller supports industry standard discrete devices that
are compatible with both the DDR1 or DDR2 specifications. The correct I/O supply voltage must be provided for the
two types of DDR devices: DDR1 devices require +2.5V and DDR2 devices require +1.8V.
Global memory timings, address and bank sizes, and memory addressing modes are programmable.
Features include:
• 16- or 32-bit memory interface
• Optional 8-bit error checking and correcting (ECC)
• 1.6-GB/s peak data rate
• Two memory banks of up to 1 GB each
• Maximum capacity of 2GB
• Support for one memory bank of 2GB with CAS latencies of 2, 2.5, or 3
• Clock frequencies from 133MHz (266Mbps) to 200MHz (400Mbps) supported
(Faster parts may be used, but must be clocked no faster than 200MHz)
• Page mode accesses (up to 16 open pages) with configurable paging policy
• Programmable address mapping and timing
• Software initiated self-refresh
• Power management (self-refresh, suspend)
• Two regions (two chip selects, one clock driver)
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Preliminary Data Sheet
PCI Express
The PCI Express single-lane interface include the following features:
Features include:
• Compliant with PCI Express base specification 1.1
• Port can be End Point or Root Complex. (Upstream & Downstream)
• PCI-Express to PCI-Express opaque (Non-Transparent) bridge
• Power Management
• Supports one virtual channel (VC0) with no Traffic Class (TC) filtering
• Maximum Payload block size 256B
• Supports up to 512B maximum Read request size
• Requests supported:
– Up to two posted outbound Write requests (memory and messages)
– Up to two posted inbound Write requests
– Up to two outbound Read requests outstanding on PCI Express
– Up to two inbound Read requests outstanding on PCI Express
– Outbound I/O request as a PCI Express Root Port
– Inbound I/O request as a PCI Express End Point
• Buffering in PCI Express Port for the following transaction types:
– 1KB Replay buffer: up to eight in flight transactions
– 512B for Outbound posted Writes
– 512B for Outbound Reads completion
– 512B for Inbound posted Writes
– 512B for Inbound Reads completion
• Parity checking on each buffer
• POM Programmable Outbound Memory Regions: 3 Memory, 1 I/O, 1 Message, 1 config, 1 Internal Regs
• PIM Programmable Inbound Memory Regions: 4 Memory, 1 I/O, 1 Expansion ROM
• INTx Interrupts support (PCI legacy):
– Up to four INTx Termination for Root Ports. A/B/C/D interrupts are wired to the UIC
– A/B/C/D INTx types Generation for Endpoints
• MSI - Message Signaled Interrupts
– MSI Generation for End Point
– MSI Termination for Root Ports
– MSI_X Termination for Root Ports
Security Function
The built-in security function is a cryptographic engine attached to the 128-bit PLB with built-in DMA and interrupt
controllers.
Features include:
• Federal Information Processing Standard (FIPS) 140-2 design
• Support for an unlimited number of Security Associations (SA)
• Different SA formats for each supported protocol (IPsec, SSL/TLS/DTLS, MACSec, SGT L2/L3 and sRTP)
• Internet Protocol Security (IPSec) features
– Full packet transforms (ESP & AH)
– Complete header and trailer processing (IPv4 and IPv6)
– Multi-mode automatic padding
– "Mutable bit" handler for AH, including IPv4 option and IPv6 extension headers
• Secure Socket Layer (SSL), Transport Layer Security (TLS), and Datagram Transport Layer Security (DTLS)
– Packet transforms
– One-pass hash-then-encrypt or decrypt-then-hash for SSL, TLS and DTLS packet transforms using ARC4
Stream Cipher
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PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
• Secure Real-Time Protocol (sRTP) features
– Packet transforms
– ROC removal and TAG insertion
– Variable bypass offset of header length per packet
• Media Access Control Security (MACSec) features
– Cipher suite GCM-AES-128
– Header insertion and removal
– Integrity and confidentiality with MSDU
• SGT L2 supported features:
– GCM-AES with 128-bit key.
– Integrity only and with confidentiality of MSDU
• ICV generation and validation SGT L3 supported features
– AES-GCM, AES-GMAC with 128, 192 and 256 bit key.
• IPsec/SSL security acceleration engine
• DES, 3DES, AES, ARC-4, AES-GCM, and GMAC-AES encryption/decryption
• MD-5, SHA-1, and SHA-256 hashing
• Public key acceleration for RSA, DSA and Diffie-Hellman
• Combined encryption-hash and hash-decryption with the AES-CCM algorithm.
• True or pseudo random number generators
– Non-deterministic true random numbers
– Pseudo random numbers with lengths of 8B or 16B
– ANSI X9.17 Annex C compliant using a DES algorithm
• Interrupt controller
– Fifteen programmable, maskable interrupts
– Initiate commands via an input interrupt
– Sixteen programmable interrupts indicating completion of certain operations
– All interrupts mapped to one level- or edge-sensitive programmable interrupt output
• DMA controller
– Autonomous, 4-channel
– 1024-words (32 bits/word) per DMA transfer
– Scatter/gather capability with byte aligned addressing
– Byte reverse capability on SA and descriptors
UART
The Universal Asynchronous Receiver/Transmitter (UART) interface provides four configurations:
• One 8-signal port
• Two 4-signal ports.
• Two 2-signal ports
• One 4-signal port and one 2-signal port
The UART performs serial-to-parallel conversion on data received from a peripheral device or a modem, and
parallel-to-serial conversion on data received from the processor.
Features include:
• Compatible with the16750
• All six software modem control functions (CTS, RTS, DSR, DTR, RI, DCD) on UART0
• Programmable auto flow (data flow controlled by RTS and CTS signals)
• Characters can be 5, 6, 7, or 8 bits
• Programmable start, stop, parity bit insertion
• Sixty-four byte FIFOs for buffering Tx and Rx data
• LIN sub-bus specification compliant - line break generation/detection and false start bit detection
• Programmable internal/external loopback capabilities
• Low Power and Sleep mode
• Register conformance (after reset) to configuration of the NS16450 register set
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Preliminary Data Sheet
• Hold and shift registers (eliminate need for precise synchronization between processor and serial data in
character mode)
• Complete status reporting
• Full prioritized interrupt system controls
• Independently controlled transmit, receive, line status, and data set interrupts
• Programmable baud generator (divides serial clock input and generates 16x clock)
• Ability to add/delete standard asynchronous communication bits such as start, stop, and parity to/from serial
data
• Even, odd, or no-parity bit generation and detection
• Stop bit generation of 1, 1.5, or 2 bits
• Variable baud rate
• Internal diagnostic capability
• Loopback controls for isolating communications link faults
• Break, parity, overrun, framing error simulation
• OPB interface with optional DMA support
IIC Bus Interface
®
The Inter-Integrated Circuit (IIC) interface provides a Philips I2C compatible interface operating up to 400kHz
either as a master, a slave, or both with a bootstrap controller (BSC) included. During chip reset, the bootstrap
controller can read configuration data from an IIC compatible memory device (e.g., EEPROM). This data can be
used to replace the default configuration settings provided by the chip.
Features include:
• Two IIC channels
• Compliant with Philips Semiconductors I2C Specification, dated 1995
• Operation at 100kHz or 400kHz
• Byte (8-bit) data
• Addresses are 10 or 7 bits
• Slave Transmit and Receive
• Master Transmit and Receive
• Multiple bus masters supported
• Programmable as master, slave, or master/slave
• Boot parameters read from IIC attached memory (Port 0) with IIC bootstrap controller
• OPB slave interface is 32 bits wide
Serial Communication Port Interface (SCP/SPI)
The Serial Communication Port (SCP) (also known as the Serial Peripheral Interface or SPI) is a full-duplex,
synchronous, character-oriented (byte) port that allows the exchange of data with other serial devices. The SCP is
a master on the serial port supporting a three-wire interface (receive, transmit, and clock), and is a slave on the
OPB.
Features include:
• One SCP channel, full duplex synchronous
• SCP master
• Up to 25MHz
• Programmable internal loopback capabilities
• Multi-master protocol supported
• Independent masking of all interrupts (master collision, transmit FIFO overflow, transmit FIFO empty, receive
FIFO full, receive FIFO underflow, receive FIFO overflow)
• Dynamic control of serial bit rate of data transfer (serial-master mode only)
• Data Item size for each data transfer under programmer control (4-to-16 bits)
• OPB slave interface is 32 bits wide
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General Purpose I/O (GPIO) Controller
Preliminary Data Sheet
The GPIO controller enables multiplexing of module I/O pins with multiple functions within the chip. That is, a single
package pin can be assigned to multiple I/O functions. Which function the pin is assigned to is determined by
register bit settings controlled by software. This significantly reduces the number of package pins needed to
support multiple I/O groups.
Features include:
• Up to 32 GPIOs available
– GPIOs are multiplexed with alternate functions
– If not in use for dedicated functions, I/Os are available as GPIOs
• Direct control of all functions from registers programmed by means of OPB bus master accesses
• Time multiplexing of controller outputs to module outputs
• Programmable conversion of module outputs to open-drain outputs (enables sharing of active low outputs
externally)
• Time multiplexing of module inputs to controller inputs
Universal Interrupt Controller (UIC)
The Universal Interrupt Controller (UIC) provides the control, status, and communications necessary between the
various sources of interrupts and the PPC405 processor.
Features include:
• Ten external interrupt sources supported
• Generate interrupt on level (high or low) or edge (rising or falling)
• Programmable as synchronous (edge-capture or level-sensitive) or asynchronous (edge- or level-sensitive
triggering)
• Each interrupt source/bit programmable as critical or non critical
• DCR bus interface is 32 bits wide
• Optional interrupt handler vector generation
– Programmable vector base address
– Programmable vector offset size
– Programmable interrupt priority ordering
• Programmable polarity for all interrupt types
• Interrupts of the same type do not need to be in contiguous bit positions
• Status registers provide: current state of all interrupts, current state of enabled interrupts
Ethernet Controller
The Ethernet support provides one 10/100/1000 Mbps interfaces (GMII/MII/RGMII ).
Features include:
• ANSI/IEEE Std. 802.3 and IEEE 802.3u supplement compliant
• Half-duplex and full-duplex support for the following:
– One Gigabit Media Independant Interface (GMII)
– One Media Independant Interface (MII)
– One Reduced GMII interfaces (RGMII)
• Receive and transmit FIFOs are 16K bytes with programmable thresholds
• FCS control for transmit/receive packets
• Multiple packet handling in transmit and receive FIFOs
• Unicast, multicast, broadcast, and promiscuous address filtering
• Two 256-bit hash filters for unicast and multicast frames
• Automatic retransmission of collided frames
• Runt frame rejection
• Programmable inter-frame gap
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PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
• IEEE 802.3x compliant for frame-based flow control mechanism, including self-assembled control frame
transmitting)
• Wake-on-LAN and Power-over-Internet supported
• Programmable internal/external loopback capabilities
• OPB slave (MAC) and PLB master (MAL) interfaces for control and configuration are 32 bits wide
• MAL has 128-bit PLB master interface for data path.
• Extensive error/status vector generation for each processed packet
• VLAN tag ID supported (according to IEEE Draft 802.3ac/D1.0 standard)
• Programmable automatic source address inclusion/replacement for transmit packets
• Programmable automatic Pad/FCS stripping for receive packets
• Programmable VLAN Tag inclusion/replacement for transmit packets
• Half- or full-duplex GMII/RGMII
• Jumbo frames support
• Memory Access Layer (MAL) provides DMA capability to Ethernet channel
• Interrupt coalescence support for two transmit and two receive channels
General Purpose Timer (GPT)
The GPT provides a time base counter and system timers in addition to those defined in the processor.
Features include:
• 32-bit time base counter driven by the OPB clock
• Seven 32-bit compare timers
JTAG
Features include:
• IEEE 1149.1 test access port
• JTAG Boundary Scan Description Language (BSDL)
Refer to http://www.amcc.com/Embedded/Partners for a list of AMCC partners supplying probes for use with the
JTAG interface.
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PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
Figure 2. Package 27mm, 388-Ball EPBGA
Gold Gate Release
Corresponds to
A01 Ball Location
Top View
Logo View
®
PPC405EXr
Part Number
Lot Number
1YWWBZZZZZ
Epoxy Mold
Compound
2.65 max
Side View
PCB
Substrate
0.3 min
27.0
25.0
Bottom View
AF
1.0 Basic
AE
AC
AD
AB
Y
AA
W
U
R
N
L
V
T
27.0
P
M
K
J
H
F
G
E
D
B
Notes: 1. All dimensions are in mm.
C
A
2. Package conforms to JEDEC MS-034C
3. Package available in leaded or lead-free versions
19 21 23 25
01 03 05 07 09 11 13 15 17
08 10
06
12 14
26
22 24
04
16 18
02
20
0.60 ± 0.1 SOLDERBALL x 388
AMCC Proprietary
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PPC405EXr – PowerPC 405EXr Embedded Processor
Signal Lists
Preliminary Data Sheet
The following table lists all the external signals in alphabetical order and shows the ball (pin) number on which the
signal appears. Shared signals are shown with the default signal (following reset) not in brackets and the alternate
signal in brackets. Signals that have different functions for different modes with the same function are separated by
commas.
Shared signals appear alphabetically multiple times in the list—once for each signal name on the ball. The Page
column indicates the page within the table “Signal Functional Description” on page 41 on which the signals in the
indicated interface group begin.
Table 3. Signals Listed Alphabetically (Sheet 1 of 14)
Signal Name
Ball
K01
Interface Group
Page
AGND
AGND
AGND
AGND
AHVDD
L04
P04
R01
M04
Power
Power
47
47
47
AHVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
R04
J03
K04
M01
N03
N04
P01
Power
T01
BA0
AD22
AF24
AE24
AF21
AE20
B03
BA1
DDR 2/1 SDRAM
DDR 2/1 SDRAM
45
45
BA2
BankSel0
BankSel1
BusReq[GPIO27][DMAEOT3][IRQ5]
CAS
External Bus Master
DDR 2/1 SDRAM
44
45
AF20
M25
T26
DM0
DM1
DM2
AD16
AD13
Y26
DDR 2/1 SDRAM
45
DM3
DM4
[DMAAck0]PerAddr07[TS1]
[DMAAck1]GPIO31[IRQ0]
[DMAAck2][HoldReq]GPIO22
[DMAAck3][ExtAck]GPIO25[IRQ3]
[DMAEOT0][PerAddr05]GPIO26[TS3]
[DMAEOT1]GPIO29[IRQ2]
[DMAEOT2][ExtReq]GPIO24[IRQ4]
[DMAEOT3][BusReq]GPIO27[IRQ5]
[DMAReq0]PerAddr06[TS2]
[DMAReq1]GPIO30[IRQ1]
[DMAReq2][HoldAck]GPIO23
[DMAReq3]PerAddr08[TS0]
J26
D01
B05
DMA
DMA
DMA
44
44
C04
K26
D03
A03
B03
K25
D02
C05
J25
44
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PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 2 of 14)
Signal Name
Ball
M26
Interface Group
Page
DQS0
DQS1
DQS2
DQS3
DQS4
EAGND
EAVDD
T25
AE16
AE12
Y25
DDR 2/1 SDRAM
45
AE07
AE08
V24
Power
47
45
ECC0
ECC1
ECC2
ECC3
ECC4
ECC5
ECC6
ECC7
EOVDD
W24
AB26
AB25
V25
DDR 2/1 SDRAM
W25
AA26
AA25
D12
EOVDD
EOVDD
EOVDD
EOVDD
EOVDD
T12
AC05
AB04
AC07
Power
47
44
AC08
C04
A03
[ExtAck]GPIO25[DMAAck3][IRQ3]
[ExtReq]GPIO24[DMAEOT2][IRQ4]
ExtReset
External Bus Master
B19
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PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 3 of 14)
Signal Name
Ball
AD04
AF04
AE04
AE03
AF02
AD07
AD09
AC11
AE10
AD10
AF09
AE09
AF07
AF06
AE06
AE05
AF05
AC06
AE01
AD02
AD01
AC03
AC02
AC01
AB03
AB02
AD05
AF03
Interface Group
Page
GMCCD
GMCCrS
GMCGTxClk, GMC0TxClk
GMCMDClk
GMCMDIO
GMCRefClk
GMCRxClk, GMC0RxClk
GMCRxD0, GMC0RxD0
GMCRxD1, GMC0RxD1
GMCRxD2, GMC0RxD2
GMCRxD3, GMC0RxD3
GMCRxD4
GMCRxD5
GMCRxD6
Ethernet
41
GMCRxD7
GMCRxDV, GMC0RxCtl
GMCRxEr
GMCTxClk
GMCTxD0, GMC0TxD0
GMCTxD1, GMC0TxD1
GMCTxD2, GMC0TxD2
GMCTxD3, GMC0TxD3
GMCTxD4
GMCTxD5
GMCTxD6
GMCTxD7
GMCTxEn, GMC0TxCtl
GMCTxEr
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Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 4 of 14)
Signal Name
Ball
A01
Interface Group
Page
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
A08
A13
A19
A26
B01
B02
B25
C01
C02
C03
C24
D04
D09
D14
D18
D23
E01
E03
H01
H26
J04
Power
47
J23
K24
L11
L13
L16
M12
M13
M14
M15
N12
N13
N14
N15
N16
N26
P11
P12
P13
P14
P15
P23
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Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 5 of 14)
Signal Name
Ball
R12
Interface Group
Page
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
R13
R14
R15
T11
T14
T16
U01
U02
V04
V23
W01
W26
AB01
AC04
AC09
AC13
AC18
AC23
AD03
AD24
AE02
AE25
AF01
AF08
AF14
AF19
AF26
Power
47
22
AMCC Proprietary
Revision 1.09 - May 2, 2008
PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 6 of 14)
Signal Name
Ball
A16
Interface Group
Page
GPIO00[PerDataPar0]
GPIO01[PerDataPar1]
GPIO02[PerDataPar2]
GPIO03[PerDataPar3]
B12
C09
B04
C13
B09
C12
D11
C20
A21
B20
H03
C11
B08
A10
B10
F04
F02
G02
G01
F03
F01
B05
C05
A03
C04
K26
B03
U03
D03
D02
D01
A02
C05
B05
AA01
Y03
AA04
AA02
GPIO04[PerData20][USB2Data4]
GPIO05[PerData21][USB2Data5]
GPIO06[PerData22][USB2Data6]
GPIO07[PerData23][USB2Data7]
GPIO08[PerCS1][NFCE1][IRQ7]
GPIO09[PerCS2][NFCE2][IRQ8]
GPIO10[PerCS3][NFCE3][IRQ9]
GPIO11[IRQ6]
GPIO12[PerData16][USB2Data0]
GPIO13[PerData17][USB2Data1]
GPIO14[PerData18][USB2Data2]
GPIO15[PerData19][USB2Data3]
GPIO16[UART0DCD][UART1CTS]
GPIO17[UART0DSR][UART1RTS]
GPIO18[UART0CTS]
System
43
GPIO19[UART0RTS]
GPIO20[UART0DTR][UART1Tx]
GPIO21[UART0RI][UART1Rx]
GPIO22[HoldReq][DMAAck2]
GPIO23[HoldAck][DMAReq2]
GPIO24[ExtReq][DMAEOT2][IRQ4]
GPIO25[ExtAck][DMAAck3][IRQ3]
GPIO26[PerAddr05][DMAEOT0][TS3]
GPIO27[BusReq][DMAEOT3][IRQ5]
GPIO28
GPIO29[IRQ2][DMAEOT1]
GPIO30[IRQ1][DMAReq1]
GPIO31[IRQ0][DMAAck1]
Halt
System
43
44
[HoldAck]GPIO23[DMAReq2]
[HoldReq]GPIO22[DMAAck2]
IIC0SData
External Bus Master
IIC0SClk
IIC
41
IIC1SData[SCPDO]
IIC1SClk[SCPClkOut]
AMCC Proprietary
23
Revision 1.09 - May 2, 2008
PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 7 of 14)
Signal Name
Ball
D01
Interface Group
Page
[IRQ0]GPIO31[DMAAck1]
[IRQ1]GPIO30[DMAReq1]
D02
[IRQ2]GPIO29[DMAEOT1]
[IRQ3][ExtAck]GPIO25[DMAAck3]
[IRQ4][ExtReq]GPIO24[DMAEOT2]
[IRQ5][BusReq]GPIO27[DMAEOT3]
[IRQ6]GPIO11
D03
C04
A03
Interrupts
42
B03
H03
[IRQ7][PerCS1][NFCE1]GPIO08
[IRQ8][PerCS2][NFCE2]GPIO09
[IRQ9][PerCS3][NFCE3]GPIO10
MemAddr00
C20
A21
B20
AE21
AD20
AF22
AE22
AF23
AD21
AC21
AE23
AE26
AD25
AD26
AC24
AB24
AC25
AC26
Y24
MemAddr01
MemAddr02
MemAddr03
MemAddr04
MemAddr05
MemAddr06
MemAddr07
DDR2/1 SDRAM
45
MemAddr08
MemAddr09
MemAddr10
MemAddr11
MemAddr12
MemAddr13
MemAddr14
MemClkEn
MemClkOut0
AA23
AA24
DDR2/1 SDRAM
45
MemClkOut0
24
AMCC Proprietary
Revision 1.09 - May 2, 2008
PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 8 of 14)
Signal Name
Ball
M24
Interface Group
Page
MemData00
MemData01
MemData02
MemData03
MemData04
MemData05
MemData06
MemData07
MemData08
MemData09
MemData10
MemData11
MemData12
MemData13
MemData14
MemData15
MemData16
MemData17
MemData18
MemData19
MemData20
MemData21
MemData22
MemData23
MemData24
MemData25
MemData26
MemData27
MemData28
MemData29
MemData30
MemData31
MemFBD
N24
P25
P24
L25
L26
N25
P26
R24
T24
V26
U24
R25
R26
U26
U25
DDR2/1 SDRAM
45
AE17
AF17
AE15
AF15
AF18
AD17
AF16
AD15
AE13
AF12
AF10
AD11
AE14
AF13
AF11
AE11
AD23
AF25
AD18
AE18
MemFBR
DDR2/1 SDRAM
45
MemODT0
MemODT1
AMCC Proprietary
25
Revision 1.09 - May 2, 2008
PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 9 of 14)
Signal Name
Ball
C06
Interface Group
Page
[NFALE]PerData30
[NFCE0]PerCS0
B21
C20
A21
B20
A06
C18
B18
C17
A18
D16
B17
C16
B16
A17
B15
C15
A15
B14
A14
C14
B13
A04
A05
C08
D05
[NFCE1][PerCS1]GPIO08[IRQ7]
[NFCE2][PerCS2]GPIO09[IRQ8]
[NFCE3][PerCS3]GPIO10[IRQ9]
[NFCLE]PerData29
[NFData00]PerData00
[NFData01]PerData01
[NFData02]PerData02
[NFData03]PerData03
[NFData04]PerData04
[NFData05]PerData05
[NFData06]PerData06
[NFData07]PerData07
[NFData08]PerData08
[NFData09]PerData09
[NFData10]PerData10
[NFData11]PerData11
[NFData12]PerData12
[NFData13]PerData13
[NFData14]PerData14
[NFData15]PerData15
[NFRdyBusy]PerData31
[NFREn]PerData27
NAND Flash
45
[NFWEn]PerData28
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
D07
D08
D13
D19
D20
D22
E04
E23
G04
G23
H23
L12
Power
47
L15
M11
M16
R11
V03
W04
Y04
26
AMCC Proprietary
Revision 1.09 - May 2, 2008
PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 10 of 14)
Signal Name
Ball
L03
Interface Group
Page
PCIE0ATB
PCIE0ClkC
PCIE0ClkT
PCIE0RExt
PCIE0RExtG
PCIE0Rx
L01
L02
M03
M02
J01
PCI Express
42
PCIE0Rx
J02
PCIE0Tx
K02
K03
K26
K25
J26
PCIE0Tx
[PerAddr05]GPIO26[TS3][DMAEOT0]
PerAddr06[TS2][DMAReq0]
PerAddr07[TS1][DMAAck0]
PerAddr08[TS0][DMAReq3]
PerAddr09[TS1E]
PerAddr10[TS0E]
PerAddr11[TS1O]
PerAddr12[TS0O]
PerAddr13
J25
H25
J24
G26
H24
G25
F26
E26
F25
G24
E25
D26
F24
C26
D25
F23
E24
C25
D24
B26
A25
B24
C23
C22
D21
A20
B21
C20
A21
B20
PerAddr14
PerAddr15
PerAddr16
PerAddr17
PerAddr18
External Peripheral
44
PerAddr19
PerAddr20
PerAddr21
PerAddr22
PerAddr23
PerAddr24
PerAddr25
PerAddr26
PerAddr27
PerAddr28
PerAddr29
PerAddr30
PerAddr31
PerBLast
External Peripheral
External Peripheral
44
44
PerClk
PerCS0[NFCE0]
[PerCS1][NFCE1]GPIO08[IRQ7]
[PerCS2][NFCE2]GPIO09[IRQ8]
[PerCS3][NFCE3]GPIO10[IRQ9]
AMCC Proprietary
27
Revision 1.09 - May 2, 2008
PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 11 of 14)
Signal Name
Ball
C18
Interface Group
Page
PerData00[NFData00]
PerData01[NFData01]
PerData02[NFData02]
PerData03[NFData03]
PerData04[NFData04]
PerData05[NFData05]
PerData06[NFData06]
PerData07[NFData07]
PerData08[NFData08]
PerData09[NFData09]
PerData10[NFData10]
PerData11[NFData11]
PerData12[NFData12]
PerData13[NFData13]
PerData14[NFData14]
PerData15[NFData15]
B18
C17
A18
D16
B17
C16
B16
A17
B15
C15
A15
B14
A14
C14
B13
C11
B08
A10
B10
C13
B09
C12
D11
A07
B07
B06
A05
C08
A06
C06
A04
A16
B12
C09
B04
C19
A24
B11
B23
A23
C21
B22
A22
A09
AD19
External Peripheral
44
[PerData16]GPIO12[USB2Data0]
[PerData17]GPIO13[USB2Data1]
[PerData18]GPIO14[USB2Data2]
[PerData19]GPIO15[USB2Data3]
[PerData20]GPIO04[USB2Data4]
[PerData21]GPIO05[USB2Data5]
[PerData22]GPIO06[USB2Data6]
[PerData23]GPIO07[USB2Data7]
PerData24[USB2Dir]
PerData25[USB2Stop]
PerData26[USB2Next]
PerData27[NFREn]
PerData28[NFWEn]
PerData29[NFCLE]
PerData30[NFALE]
PerData31[NFRdyBusy]
[PerDataPar0]GPIO00
[PerDataPar1]GPIO01
[PerDataPar2]GPIO02
[PerDataPar3]GPIO03
PerErr
External Peripheral
External Peripheral
External Peripheral
44
44
44
PerOE
PerReady
PerRW
PerWBE0
PerWBE1
PerWBE2
PerWBE3
PSROUser
System
43
45
RAS
DDR 2/1 SDRAM
28
AMCC Proprietary
Revision 1.09 - May 2, 2008
PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 12 of 14)
Signal Name
Ball
N01
Interface Group
Page
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SAGND
N02
P02
P03
R02
R03
T02
Other
47
T03
T04
AD12
A11
Power
47
46
SAVDD
A12
SCPClkOut[IIC1SClk]
SCPDI
AA02
AA03
AA04
N23
Serial Communication Port
SCPDO[IIC1SData]
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
R16
T15
W23
Y23
Power
47
AB23
AC19
AC20
AC22
AD14
AC14
T23
S
S
S
S
VREF1A
VREF1B
VREF2A
VREF2B
DDR2/1 SDRAM
System
45
43
AC16
L23
SysClk
SysErr
SysReset
TCK
C10
AD06
AD08
V02
W02
W03
Y02
D06
V01
L24
TDI
JTAG
42
43
TDO
TestEn
TmrClk
TMS
System
JTAG
Trace
JTAG
42
43
42
TrcClk
TRST
Y01
J25
[TS0]PerAddr08[DMAReq3]
[TS1]PerAddr07[DMAAck0]
J26
Trace
43
[TS2]PerAddr06[DMAReq0]
[TS3][PerAddr05]GPIO26[DMAEOT0]
K25
K26
AMCC Proprietary
29
Revision 1.09 - May 2, 2008
PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 13 of 14)
Signal Name
Ball
J24
Interface Group
Page
[TS0E]PerAddr10
[TS0O]PerAddr12
[TS1E]PerAddr09
[TS1O]PerAddr11
[UART0CTS]GPIO18
H24
H25
G26
G02
F04
F02
F03
F01
G01
G03
H02
F04
F02
F01
F03
E02
C07
C11
B08
A10
B10
C13
B09
C12
D11
A07
B06
B07
Trace
43
[UART0DCD][UART1CTS]GPIO16
[UART0DSR][UART1RTS]GPIO17
[UART0DTR][UART1Tx]GPIO20
[UART0RI][UART1Rx]GPIO21
[UART0RTS]GPIO19
UART Peripheral
46
46
UART0Rx
UART0Tx
[UART1CTS][UART0DCD]GPIO16
[UART1RTS][UART0DSR]GPIO17
[UART1Rx][UART0RI]GPIO21
[UART1Tx][UART0DTR]GPIO20
UARTSerClk
UART Peripheral
UART Peripheral
USB 2.0
46
46
USB2Clk
[USB2Data0][PerData16]GPIO12
[USB2Data1][PerData17]GPIO13
[USB2Data2][PerData18]GPIO14
[USB2Data3][PerData19]GPIO15
[USB2Data4][PerData20]GPIO04
[USB2Data5][PerData21]GPIO05
[USB2Data6][PerData22]GPIO06
[USB2Data7][PerData23]GPIO07
[USB2Dir]PerData24
USB 2.0
USB 2.0
46
46
[USB2Next]PerData26
[USB2Stop]PerData25
30
AMCC Proprietary
Revision 1.09 - May 2, 2008
PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 14 of 14)
Signal Name
Ball
D10
Interface Group
Page
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
WE
D15
D17
H04
K23
L14
M23
N11
P16
Power
47
R23
T13
U04
U23
AC10
AC12
AC15
AC17
AE19
DDR2/1 SDRAM
45
AMCC Proprietary
31
Revision 1.09 - May 2, 2008
PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
In the following table, only the default signal name is shown for each ball. Shared balls are marked with an asterisk
(*). To determine what signals or functions are shared on those balls, look up the default signal name in “Signals
Listed Alphabetically” on page 18. The following table lists the signals by ball assignment.
Table 4. Signals Listed by Ball Assignment (Sheet 1 of 7)
Ball
A01
Signal Name
Ball
B01
Signal Name
Ball
C01
Signal Name
Ball
D01
Signal Name
GPIO31 *
GND
Halt
GND
GND
GND
GND
GND
A02
A03
A04
A05
A06
A07
B02
B03
B04
B05
B06
B07
C02
C03
C04
C05
C06
C07
D02
D03
D04
D05
D06
D07
GPIO30 *
GPIO29 *
GND
GPIO24 *
GPIO27 *
PerData31 *
PerData27 *
PerData29 *
PerData24 *
GPIO03 *
GPIO25 *
GPIO23 *
PerData30 *
USB2Clk
OVDD
GPIO22 *
PerData26 *
PerData25 *
TmrClk
OVDD
OVDD
A08
A09
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
GND
B08
B09
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
GPIO13 *
C08
C09
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
PerData28 *
GPIO02 *
SysClk
D08
D09
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
PSROUser
GPIO14 *
SAGND
SAVDD
GPIO05 *
GND
VDD
GPIO15 *
PerReady
GPIO01 *
GPIO12 *
GPIO06 *
GPIO04 *
PerData14 *
PerData10 *
PerData06 *
PerData02 *
PerData00 *
PerErr
GPIO07 *
EOVDD
OVDD
GND
PerData15 *
PerData12 *
PerData09 *
PerData07 *
PerData05 *
PerData01 *
ExtReset
PerData13 *
PerData11 *
GPIO00 *
PerData08 *
PerData03 *
GND
GND
VDD
PerData04 *
VDD
GND
OVDD
OVDD
A20
A21
A22
A23
A24
A25
A26
PerClk
B20
B21
B22
B23
B24
B25
B26
GPIO10 *
PerCS0 *
PerWBE2
PerRW
C20
C21
C22
C23
C24
C25
C26
GPIO08 *
PerWBE1
PerAddr31
PerAddr30
GND
D20
D21
D22
D23
D24
D25
D26
PerCS2 *
PerWBE3
PerWBE0
PerOE
PerBLast
OVDD
GND
PerAddr29
GND
PerAddr26
PerAddr22
PerAddr19
PerAddr28
GND
PerAddr25
PerAddr21
PerAddr27
32
AMCC Proprietary
Revision 1.09 - May 2, 2008
PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
Table 4. Signals Listed by Ball Assignment (Sheet 2 of 7)
Ball
E01
Signal Name
Ball
F01
Signal Name
GPIO21 *
Ball
G01
Signal Name
GPIO19 *
Ball
H01
Signal Name
GND
GND
E02
E03
E04
E05
E06
E07
E08
E09
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
UARTSerClk
GND
F02
F03
F04
F05
F06
F07
F08
F09
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
GPIO17 *
GPIO20 *
GPIO16 *
No ball
G02
G03
G04
G05
G06
G07
G08
G09
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
G23
G24
G25
G26
GPIO18 *
UART0Rx *
OVDD
H02
H03
H04
H05
H06
H07
H08
H09
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
UART0Tx *
GPIO11 *
VDD
OVDD
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
OVDD
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
OVDD
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
OVDD
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
PerAddr23
PerAddr20
PerAddr16
PerAddr14
PerAddr24
PerAddr18
PerAddr15
PerAddr17
PerAddr13
PerAddr11 *
PerAddr12 *
PerAddr09 *
GND
AMCC Proprietary
33
Revision 1.09 - May 2, 2008
PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
Table 4. Signals Listed by Ball Assignment (Sheet 3 of 7)
Ball
J01
Signal Name
PCIE0Rx
Ball
K01
Signal Name
AGND
Ball
L01
Signal Name
PCIE0ClkC
Ball
M01
Signal Name
AVDD
J02
J03
PCIE0Rx
AVDD
K02
K03
PCIE0Tx
PCIE0Tx
AVDD
L02
L03
PCIE0ClkT
PCIE0ATB
M02
M03
PCIE0RExtG
PCIE0RExt
AHVDD
J04
J05
J06
J07
J08
J09
J10
J11
GND
K04
K05
K06
K07
K08
K09
K10
K11
L04
L05
L06
L07
L08
L09
L10
L11
AGND
No ball
No ball
No ball
No ball
No ball
No ball
GND
M04
M05
M06
M07
M08
M09
M10
M11
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
OVDD
OVDD
J12
J13
J14
J15
No ball
No ball
No ball
No ball
K12
K13
K14
K15
No ball
No ball
No ball
No ball
L12
L13
L14
L15
M12
M13
M14
M15
GND
GND
GND
GND
OVDD
GND
VDD
OVDD
J16
J17
J18
J19
J20
J21
J22
J23
J24
J25
J26
No ball
K16
K17
K18
K19
K20
K21
K22
K23
K24
K25
K26
No ball
No ball
No ball
No ball
No ball
No ball
No ball
VDD
L16
L17
L18
L19
L20
L21
L22
L23
L24
L25
L26
GND
M16
M17
M18
M19
M20
M21
M22
M23
M24
M25
M26
No ball
No ball
No ball
No ball
No ball
No ball
No ball
SVREF2B
No ball
No ball
No ball
No ball
No ball
No ball
VDD
No ball
No ball
No ball
No ball
No ball
GND
PerAddr10 *
PerAddr08 *
PerAddr07 *
GND
TrcClk
MemData00
DM0
PerAddr06 *
GPIO26 *
MemData04
MemData05
DQS0
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Revision 1.09 - May 2, 2008
PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
Table 4. Signals Listed by Ball Assignment (Sheet 4 of 7)
Ball
N01
Signal Name
Reserved
Ball
P01
Signal Name
AVDD
Ball
R01
Signal Name
AGND
Ball
T01
Signal Name
AVDD
N02
N03
Reserved
AVDD
P02
P03
Reserved
Reserved
R02
R03
Reserved
Reserved
AHVDD
T02
T03
Reserved
Reserved
AVDD
N04
N05
N06
N07
N08
N09
N10
N11
P04
P05
P06
P07
P08
P09
P10
P11
AGND
No ball
No ball
No ball
No ball
No ball
No ball
GND
R04
R05
R06
R07
R08
R09
R10
R11
T04
T05
T06
T07
T08
T09
T10
T11
Reserved
No ball
No ball
No ball
No ball
No ball
No ball
GND
No ball
No ball
No ball
No ball
No ball
No ball
VDD
No ball
No ball
No ball
No ball
No ball
No ball
OVDD
EOVDD
N12
N13
N14
N15
GND
GND
GND
GND
P12
P13
P14
P15
GND
R12
R13
R14
R15
GND
GND
GND
GND
SVDD
T12
T13
T14
T15
VDD
GND
GND
GND
GND
SVDD
VDD
N16
N17
N18
N19
N20
N21
N22
N23
N24
N25
N26
GND
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
T26
GND
No ball
No ball
No ball
No ball
No ball
No ball
SVDD
No ball
No ball
No ball
No ball
No ball
No ball
No ball
VDD
No ball
No ball
No ball
No ball
No ball
No ball
SVREF1B
No ball
No ball
No ball
No ball
No ball
GND
MemData01
MemData06
GND
MemData03
MemData02
MemData07
MemData08
MemData12
MemData13
MemData09
DQS1
DM1
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Revision 1.09 - May 2, 2008
PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
Table 4. Signals Listed by Ball Assignment (Sheet 5 of 7)
Ball
U01
Signal Name
Ball
V01
Signal Name
Ball
W01
W02
W03
Signal Name
Ball
Y01
Signal Name
TRST
GND
GND
TMS
TCK
GND
TDI
U02
U03
V02
V03
Y02
Y03
TestEn
IIC0SClk
OVDD
OVDD
GPIO28
VDD
TDO
OVDD
U04
U05
U06
U07
U08
U09
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
U23
U24
U25
U26
V04
V05
V06
V07
V08
V09
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
V21
V22
V23
V24
V25
V26
GND
W04
W05
W06
W07
W08
W09
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
W23
W24
W25
W26
Y04
Y05
Y06
Y07
Y08
Y09
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
Y24
Y25
Y26
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
VDD
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
GND
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
SVDD
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
SVDD
MemData11
MemData15
MemData14
ECC0
ECC1
ECC5
GND
MemClkEn
DQS4
ECC4
MemData10
DM4
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AMCC Proprietary
Revision 1.09 - May 2, 2008
PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
Table 4. Signals Listed by Ball Assignment (Sheet 6 of 7)
Ball
AA01
AA02
AA03
AA04
Signal Name
IIC0SData
Ball
AB01
AB02
AB03
AB04
Signal Name
Ball
AC01
AC02
AC03
AC04
Signal Name
GMCTxD5
Ball
AD01
AD02
AD03
AD04
Signal Name
GMCTxD2 *
GND
IIC1SClk *
SCPDI
GMCTxD7
GMCTxD6
EOVDD
GMCTxD4
GMCTxD3 *
GND
GMCTxD1 *
GND
IIC1SData *
GMCCD
EOVDD
AA05
AA06
AA07
AA08
AA09
AA10
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
AB05
AB06
AB07
AB08
AB09
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
No ball
SVDD
AC05
AC06
AC07
AC08
AC09
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AD05
AD06
AD07
AD08
AD09
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
GMCTxEn *
SysErr
GMCTxClk
EOVDD
GMCRefClk
EOVDD
SysReset
GMCRxClk *
GMCRxD2 *
MemData27
Reserved
DM3
GND
VDD
GMCRxD0 *
VDD
GND
S
VREF1A
SVDD
VDD
MemData23
DM2
SVREF2A
VDD
MemData21
MemODT0
RAS
GND
SVDD
SVDD
MemAddr01
MemAddr05
BA0
MemAddr06
SVDD
AA23
AA24
AA25
AA26
MemClkOut0
MemClkOut0
ECC7
AB23
AB24
AB25
AB26
AC23
AC24
AC25
AC26
GND
AD23
AD24
AD25
AD26
MemFBD
GND
MemAddr12
ECC3
MemAddr11
MemAddr13
MemAddr14
MemAddr09
MemAddr10
ECC6
ECC2
AMCC Proprietary
37
Revision 1.09 - May 2, 2008
PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
Table 4. Signals Listed by Ball Assignment (Sheet 7 of 7)
Ball
AE01
AE02
AE03
AE04
AE05
AE06
AE07
AE08
AE09
AE10
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AE26
Signal Name
GMCTxD0 *
Ball
AF01
AF02
AF03
AF04
AF05
AF06
AF07
AF08
AF09
AF10
AF11
AF12
AF13
AF14
AF15
AF16
AF17
AF18
AF19
AF20
AF21
AF22
AF23
AF24
AF25
AF26
Signal Name
Ball
Signal Name
Ball
Signal Name
GND
GND
GMCMDIO
GMCTxEr
GMCCrS
GMCRxEr
GMCRxD6
GMCRxD5
GND
GMCMDClk
GMCGTxClk *
GMCRxDV *
GMCRxD7
EAGND
EAVDD
GMCRxD4
GMCRxD1 *
MemData31
DQS3
GMCRxD3 *
MemData26
MemData30
MemData25
MemData29
GND
MemData24
MemData28
MemData18
DQS2
MemData19
MemData22
MemData17
MemData20
GND
MemData16
MemODT1
WE
BankSel1
MemAddr00
MemAddr03
MemAddr07
BA2
CAS
BankSel0
MemAddr02
MemAddr04
BA1
GND
MemFBR
GND
MemAddr08
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AMCC Proprietary
Revision 1.09 - May 2, 2008
PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
Pin Group List
The following table provides a summary of the number of package pins (balls) associated with each functional
interface group.
Table 5. Pin Groups
Group
Total Signal Pins
VDD
No. of Pins
237
17
20
6
OVDD
EOVDD
SVDD
10
71
7
GND
AVDD
AHVDD
SAVDD
2
1
1
SAGND
EAVDD
1
EAGND
AGND
1
4
Total Power Pins
Reserved
141
10
388
Total Pins
In the table “Signal Functional Description” on page 41, each external signal is listed along with a short description
of the signal function. Active-low signals (for example, Halt) are marked with an overline. See the preceding table,
“Signals Listed Alphabetically” on page 18, for the pin (ball) number to which each signal is assigned.
Shared Pins
Some signals are shared on the same package pin so that the pin can be used for different functions. In most
cases, the signal names shown in this table are not accompanied by signal names that might share the same pin.
If you need to know what, if any, signals are shared with a particular signal, look up the name in “Signals Listed
Alphabetically” on page 18. It is expected that in any single application a particular pin will always be programmed
to serve the same function. The flexibility of sharing allows a single chip to offer a richer pin selection than would
otherwise be possible.
Initialization Strapping
One group of pins is used as strapped inputs during system reset. These pins function as strapped inputs only
during reset and are used for other functions during normal operation (see “Initialization” on page 71). Note that the
use of these pins for strapping is not considered multiplexing since the strapping function is not programmable.
Pull-Up and Pull-Down Resistors
Pull-up and pull-down resistors are used for strapping during reset and to retain unused or undriven inputs in an
appropriate state. The recommended pull-up value of 3kΩ to +3.3V and pull-down value of 1kΩ to GND, applies
only to individually terminated signals. To prevent possible damage to the device, I/Os capable of becoming
outputs must never be tied together and terminated through a common resistor.
If your system-level test methodology permits, input-only signals can be connected together and terminated
through either a common resistor or directly to +3.3V or GND. When a resistor is used, its value must ensure that
the grouped I/Os reach a valid logical zero or logical one state when accounting for the total input current into the
PPC405EXr.
AMCC Proprietary
39
Revision 1.09 - May 2, 2008
PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
Reserved Balls
The balls marked Reserved on this chip are not functional. However, most of the reserved balls cannot be left
unconnected. Connect the balls shown in the following table as indicated:
Table 6. Non-Functional Ball Connections
Ball
N01
N02
P02
P03
R02
R03
T02
T03
T04
AD12
Connection
GND
GND
Open
Open
GND
GND
GND
GND
GND
Open
40
AMCC Proprietary
Revision 1.09 - May 2, 2008
PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
Signal Functional Descriptions
The following table provides a description of the I/O signals on the PPC405EXr.
Table 7. Signal Functional Description (Sheet 1 of 7)
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 39 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 39 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
Signal Name
Description
I/O
Type
Notes
Ethernet Interface
3.3V tolerant
2.5V CMOS
GMCCD
GMCCrS
GMII/MII: Collision detect.
GMII/MII: Carrier sense.
I
1, 5
1
3.3V tolerant
2.5V CMOS
I/O
O
GMCGTxClk,
GMC0TxClk
GMII/MII: Transmit clock for GMII 1000Mbps.
RGMII 0: Transmit clock.
3.3V tolerant
2.5V CMOS
3.3V tolerant
2.5V CMOS
GMCMDClk
GMCMDIO
Management data clock.
Management data I/O.
O
3.3V tolerant
2.5V CMOS
I/O
3.3V tolerant
2.5V CMOS
receiver
GMCRefClk
GMII/MII, RGMII: Required 125MHz reference clock.
I
1, 5
GMCRxClk,
GMC0RxClk
GMII/MII: Receive clock.
RGMII 0: Receive clock.
3.3V tolerant
2.5V CMOS
I
I
1, 5
1
GMCRxD0:3,
GMC0RxD0:3
GMII/MII: Receive data.
RGMII 0: Receive data.
3.3V tolerant
2.5V CMOS
3.3V tolerant
2.5V CMOS
GMCRxD4:7
GMII/MII: Receive data.
I
1
GMCRxDV,
GMC0RxCtl
GMII/MII: Receive data valid.
RGMII 0: Receive control.
3.3V tolerant
2.5V CMOS
I
1
3.3V tolerant
2.5V CMOS
GMCRxEr
GMCTxClk
GMII/MII: Receive error.
I
1
3.3V tolerant
2.5V CMOS
GMII/MII: Transmit clock for 10/100Mbps.
I
1, 5
GMCTxD0:3,
GMC0TxD0:3
GMII/MII: Transmit data.
RGMII 0: Transmit data.
3.3V tolerant
2.5V CMOS
O
O
O
O
3.3V tolerant
2.5V CMOS
GMCTxD4:7
GMII/MII: Transmit data.
GMCTxEn,
GMC0TxCtl
GMII/MII: Transmit enable.
RGMII 0: Transmit control.
3.3V tolerant
2.5V CMOS
3.3V tolerant
2.5V CMOS
GMCTxEr
GMII/MII: Transmit error.
IIC Interface
IIC0SClk
IIC Serial Clock.
IIC Serial Data.
IIC Serial Clock.
IIC Serial Data.
I/O
I/O
I/O
I/O
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
1, 2
2
IIC0SData
IIC1SClk
1
IIC1SData
1
AMCC Proprietary
41
Revision 1.09 - May 2, 2008
PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
Table 7. Signal Functional Description (Sheet 2 of 7)
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 39 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 39 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
Signal Name
PCI Express Interface
PCIE0ATB
Description
I/O
Type
Notes
Analog Test Bus for manufacturing test.
na
I
Analog
CML
PCIE0ClkC
PCIE0ClkT
Differential input for external reference clock.
5
External reference resistor. Attach a 1.37 kΩ, 1% resistor between
RExt and RExtG to provide the reference for both the bias currents
and the impedance calibration circuitry.
PCIE0RExt
PCIEnRExtG
na
Analog
Differential receiver for received serial data.
PCIE0Rx
PCIE0Rx
I
LVDS receiver
LVDS driver
Note: Input must be DC coupled and biased to 0V common mode.
Differential driver for transmitted serial data.
PCIE0Tx
PCIE0Tx
O
Note: Output must be AC coupled.
Interrupts Interface
IRQ0:2
External interrupt requests.
External interrupt requests.
External interrupt requests.
External interrupt requests.
I
I
I
I
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
IRQ3:5
1
1
IRQ6
IRQ7:9
JTAG Interface
TCK
Test clock.
I
I
3.3V LVTTL
1
3.3V LVTTL
w/pull-up
TDI
Test data in.
1, 4
TDO
TMS
Test data out.
Test mode select.
O
I
3.3V LVTTL
3.3V LVTTL
w/pull-up
1
Test reset. Must be low during power-on reset to initialize the JTAG
controller and for normal operation of the chip.
3.3V LVTTL
w/pull-up
TRST
I
1, 5
42
AMCC Proprietary
Revision 1.09 - May 2, 2008
PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
Table 7. Signal Functional Description (Sheet 3 of 7)
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 39 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 39 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
Signal Name
Description
I/O
Type
Notes
System Interface
3.3V tolerant
2.5V CMOS
receiver
SysClk
System input clock.
I
1
3.3V tolerant
2.5V CMOS
SysErr
Machine check exception has occurred.
O
Main system reset. This signal may be driven by the PPC405EXr to
cause a board level reset to occur.
3.3V tolerant
2.5V CMOS
SysReset
I/O
1, 2
3
3.3V LVTTL
receiver
w/pull-down
TestEn
Halt
Test enable. Reserved for manufacturing LSSD test.
External request to stop the processor.
Processor timer external input.
I
I
3.3V LVTTL
rcvr
w/pull-up
3.3V LVTTL
receiver
TmrClk
I
w/pull-up
General purpose I/O. Most of the GPIO signals are multiplexed with
other signals. Which signal is connected to the external pin depends
on the setting of bits in the GPIO registers.
GPIO00:27
GPIO29:31
I/O
3.3V LVTTL
General purpose I/O. Most of the GPIO signals are multiplexed with
other signals. Which signal is connected to the external pin depends
on the setting of bits in the GPIO registers.
3.3V tolerant
2.5V CMOS
GPIO28
I/O
O
Performance screen ring output. Use for module characterization and
screening only.
PSROUser
3
Trace Interface
TrcClk
Trace interface clock. Operates at half the CPU core frequency.
Even trace execution status.
O
3.3V LVTTL
3.3V LVTTL
TS0E
TS1E
I/O
TS0O
TS1O
Odd trace execution status.
Trace status.
I/O
I/O
3.3V LVTTL
3.3V LVTTL
TS0:3
AMCC Proprietary
43
Revision 1.09 - May 2, 2008
PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
Table 7. Signal Functional Description (Sheet 4 of 7)
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 39 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 39 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
Signal Name
Description
I/O
Type
Notes
External Peripheral Interface
PerAddr05:31
PerClk
Address bus 5:31.
I/O
O
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
Clock output.
PerCS0
Chip selects 0.
Chip selects 1:3.
Data bus 0:31.
Data bus parity 0:3.
Output enable.
O
2
PerCS1:3
PerData00:31
PerDataPar0:3
PerOE
I/O
I/O
I/O
O
1, 2
2
3.3V LVTTL
receiver
PerReady
Slave is ready to transfer data.
I
PerBLast
PerErr
Last transfer of burst access.
External bus error.
Read/Write.
I/O
I/O
I/O
I/O
O
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
1, 4
1, 3
1, 2
1, 2
PerRW
PerWBE0:3
ExtReset
Write Byte enable 0:3.
External reset.
External Bus Master Interface
BusReq
External bus request.
O
O
I
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
1
1
1
1
1
ExtAck
External data transfer complete.
External data transfer request.
External request for bus access.
External request acknowledge.
ExtReq
HoldReq
I
HoldAck
O
DMA Interface
DMAAck0:1
DMAAck2:3
DMAReq0:1
DMAReq2
DMAReq3
DMAEOT0:1
DMAEOT2:3
External peripheral DMA acknowledge.
External peripheral DMA acknowledge.
External peripheral DMA request.
O
O
I
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
1
1
External peripheral DMA request.
I
External peripheral DMA request.
I
External DMA peripheral end-of-transmission.
External DMA peripheral end-of-transmission.
I/O
I/O
1
44
AMCC Proprietary
Revision 1.09 - May 2, 2008
PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
Table 7. Signal Functional Description (Sheet 5 of 7)
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 39 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 39 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
Signal Name
NAND Flash Interface
NFALE
Description
I/O
Type
Notes
Address latch enable.
Chip select 0.
O
O
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
NFCE0
NFCE1:3
Chip selects 1:3.
Command latch enable.
Data Bus
O
1
NFCLE
O
NFData00:15
I/O
Read/Busy. If low, indicates that Read/Erase command is in process.
If high, indicates that the command is complete.
NFRdyBusy
I
3.3V LVTTL
NFRE
NFWE
Read enable.
Write enable.
O
O
3.3V LVTTL
3.3V LVTTL
DDR1/2 SDRAM Interface
2.5V (1.8V)
SSTL2 Dr/Rcv
MemData00:31
MemAddr00:14
RAS
Memory data.
I/O
O
2.5V (1.8V)
SSTL2 Dr/Rcv
Memory address.
2.5V (1.8V)
SSTL2 Dr/Rcv
Row address strobe.
O
2.5V (1.8V)
SSTL2 Dr/Rcv
CAS
Column address strobe.
Clock enable.
O
2.5V (1.8V)
SSTL2 Dr/Rcv
MemClkEn
O
MemClkOut0
MemClkOut0
2.5V (1.8V)
SSTL2 Dr/Rcv
Differential DDR SDRAM clock output.
O
Feedback driver. Connect directly to MemFBR with the minimum
trace length.
2.5V (1.8V)
SSTL2 Dr/Rcv
MemFBD
MemFBR
MemODT0:1
DM0:4
O
2.5V (1.8V)
SSTL2 Dr/Rcv
Feedback receiver. Connect externally to MemFBD.
On-die termination.
I
2.5V (1.8V)
SSTL2 Dr/Rcv
O
Write data byte lane mask. DM4 is the byte lane mask for the ECC
byte lane.
2.5V (1.8V)
SSTL2 Dr/Rcv
O
2.5V (1.8V)
SSTL2 Dr/Rcv
DQS0:4
BA0:2
Byte lane strobe. DQS4 is the strobe for the ECC lane.
Bank address for up to eight banks.
Bank select for up to two SDRAM memory banks.
ECC check bit byte.
I/O
O
2.5V (1.8V)
SSTL2 Dr/Rcv
2.5V (1.8V)
SSTL2 Dr/Rcv
BankSel0:1
ECC0:7
WE
O
2.5V (1.8V)
SSTL2 Dr/Rcv
I/O
O
2.5V (1.8V)
SSTL2 Dr/Rcv
Write enable.
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PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
Table 7. Signal Functional Description (Sheet 6 of 7)
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 39 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 39 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
Signal Name
Description
I/O
Type
Notes
DDR 1 (DDR2) Reference voltage 1 and 2 inputs:
SVREF1A:B
SVREF2A:B
1.25V (0.9V)
Volt ref receiver
Minimum +1.15 (+0.825)V
Nominal +1.25 (+0.9)V
Maximum +1.35 (0.975)V
I
Serial Communication Port (SCP) Interface
SCPClkOut
SCPDI
Output clock.
Data input.
I/O
I
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
SCPDO
Data output.
O
UART Peripheral Interface
The UART interface can be configured as follows:
1. One 8-pin
2. Two 4-pin
3. Two 2-pin (pull up DCD, DSR, CTS and RTS)
4. One 4-pin and one 2-pin
3.3V LVTTL
receiver
UARTSerClk
Serial clock input.
I
4
w/pull-up
UARTnCTS
UARTnDCD
UARTnDSR
UARTnDTR
UARTnRI
Clear to send.
I
I
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
1, 6
1, 6
1, 6
1, 4
1
Data carrier detect.
Data set ready.
Data terminal ready.
Ring indicator.
I
O
I
UARTnRTS
UARTnRx
Request to send.
Receive data.
O
I
1
UARTnTx
Transmit data.
O
USB 2.0 Interface
3.3V LVTTL
receiver
USB2Clk
USB clock.
I
5
USB2Data0:7
USB2Dir
Parallel data bus.
I/O
I
3.3V LVTTL
3.3V LVTTL
Data bus direction control.
Next data byte control. When data is being transferred to the PHY,
the next byte should be sent. When data is being received from the
PHY, the next byte is available.
USB2Next
USB2Stop
I
3.3V LVTTL
3.3V LVTTL
Stop output control.
O
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Revision 1.09 - May 2, 2008
PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
Table 7. Signal Functional Description (Sheet 7 of 7)
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 39 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 39 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
Signal Name
Description
I/O
Type
Notes
Power
VDD
Logic Supply (+1.2V).
I/O Supply (+3.3V).
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
OVDD
SVDD
EOVDD
DDR1/2 SDRAM Supply (+2.5V or +1.8V)
Ethernet I/O Supply (+2.5V)
GND
Ground.
SAVDD
System PLL Analog Supply (+2.5V).
System PLL Analog Ground.
SAGND
EAVDD
Ethernet PLL Analog Supply (+2.5V).
Ethernet PLL Analog Ground.
EAGND
AVDD
PCI-Express SerDes Analog Supply (+1.2V)
PCI-Express SerDes PLL Analog Supply (+2.5V).
PCI-Express Analog Ground (for AHVDD and AVDD)
AHVDD
AGND
Other
.
To avoid noise pickup problems, these balls must be connected in
any board design as shown Table 6 on page 40.
Reserved
na
na
na
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Revision 1.09 - May 2, 2008
PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
Ratings and Specifications
Table 8. Absolute Maximum Ratings
The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause
permanent damage to the device. None of the performance specification contained in this document are guaranteed when
operating at these maximum ratings.
Characteristic
Logic Supply Voltage (internal logic)
PCI-Express SerDes Analog Supply Voltage
PCI-Express SerDes PLL Analog Supply Voltage
I/O Supply Voltage
Symbol
Value
0 to +1.6
Unit
V
Notes
VDD
AVDD
AHVDD
OVDD
SVDD
EOVDD
SAVDD
EAVDD
VIN
0 to +1.6
V
1
1
0 to +2.6
V
0 to +3.6
V
SDRAM DDR1(2) Supply Voltage
Ethernet I/O Supply Voltage
0 to +2.6 (+1.9)
0 to +2.6
V
V
System PLL Analog Supply Voltage
Ethernet PLL Analog Supply Voltage
Input Voltage (3.3V LVTTL receivers)
Storage Temperature Range
0 to +2.6
V
1
1
0 to +2.6
V
0 to +3.6
V
TSTG
−55 to +150
−40 to +120
−40 to +125
°C
°C
°C
TC
Case Temperature Range under bias
Junction Temperature Range
TJMax
Notes:
1. The analog voltages can be derived from the +1.2V and +2.5V supplies, but must be filtered as shown below before entering the
PPC405EXr. Use a separate filter for each voltage. This circuit can be used for AVDD, AHVDD, SAVDD, and EAVDD
.
V
AV
DD
DD
L1 – Murata BLM18AG121SN1D
L1
C1
C1 – 0.1 μF ceramic
AGND
GND
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AMCC Proprietary
Revision 1.09 - May 2, 2008
PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
Table 9. Package Thermal Specifications
The PPC405EXr is designed to operate within a case temperature range TC defined in “Recommended DC Operating
Conditions” on page 50. Thermal resistance values for the EPBGA packages in a convection environment are as follows:
Airflow
ft/min (m/sec)
Parameter
Symbol
Unit
0 (0)
100 (0.51) 200 (1.02) 300 (1.52) 400 (2.02) 500 (2.53) 600 (3.03)
Junction-to-ambient
thermal resistance
without heat sink
θJA
θJA
18.9
16.6
12.5
15.8
11.4
15.4
10.9
15.0
10.7
14.7
10.5
14.4
10.3
°C/W
°C/W
Junction-to-ambient
thermal resistance
with heat sink
15.5
Resistance Value
Junction-to-case thermal
resistance
θJC
θJB
8.96
°C/W
°C/W
Junction-to-board thermal
resistance
13.74
Notes:
1. Values in the table are achieved with the following JEDEC standard board: 114.5mm x 101.6mm x 1.6mm, 4 layers.
2. For a chip mounted on a card with at least one signal and two power planes, the following relationships exist:
a. Case temperature, TC, is measured at top center of case surface with device soldered to circuit board.
b. TA = TC – PxθCA, where TA is ambient temperature and P is power consumption.
c. TCMax = TJMax – PxθJC, where TJMax is maximum junction temperature and P is power consumption.
Thermal Management
The following heat sink was used in the above thermal analysis:
26.92mm x 27mm x 11.43mm
The heat sink is manufactured by:
Aavid Thermalloy, P/N 62925
AMCC Proprietary
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Revision 1.09 - May 2, 2008
PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
Table 10. Recommended DC Operating Conditions (Sheet 1 of 2)
Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended
conditions can affect device reliability.
Parameter
Logic Supply Voltage—333MHz & 400MHz
Logic Supply Voltage—533MHz
I/O Supply Voltage
Symbol
Minimum
+1.1
Typical
+1.15
Maximum
+1.2
Unit
V
Notes
VDD
2
VDD
OVDD
SVDD
EOVDD
+1.2
+1.25
+1.3
V
+3.15
+3.3
+3.45
V
SDRAM DDR1(2) Supply Voltage
Ethernet I/O Supply Voltage
+2.4 (+1.7)
+2.4
+2.5 (+1.8)
+2.5
+2.6 (+1.9)
+2.6
V
V
AHVDD
SAVDD
EAVDD
PLL Analog Supply Voltage
+2.4
+2.5
+2.6
V
AVDD
AVDD
VIL
Analog Supply Voltage—333MHz & 400MHz
Analog Supply Voltage—533MHz
I/O Input Low (3.3V LVTTL)
+1.1
+1.2
0
+1.15
+1.25
+1.2
+1.3
+0.8
+3.6
+0.4
+3.6
+0.7
+3.6
+0.4
+2.7
V
V
V
V
V
V
V
V
V
V
2
VIH
I/O Input High (3.3V LVTTL)
+2.0
0
VOL
VOH
VIL
I/O Output Low (3.3V LVTTL)
I/O Output High (3.3V LVTTL)
+2.4
0
I/O Input Low (3.3V tol, 2.5V CMOS)
I/O Input High (3.3V tol, 2.5V CMOS)
I/O Output Low (3.3V tol, 2.5V CMOS)
I/O Output High (3.3V tol, 2.5V CMOS)
VIH
+1.7
0
VOL
VOH
+2.0
SVREF − 0.18
VIL
VIH
I/O Input Low DDR1 (DDR2) (SSTL2)
I/O Input High DDR1 (DDR2) (SSTL2)
− 0.3
V
V
(0.125)
SVREF + 0.18
(0.125)
SVDD + 0.3
VOL
VOH
I/O Output Low DDR1 (DDR2) (SSTL2)
I/O Output High DDR1 (DDR2) (SSTL2)
See JESD8-9 (JESD8-15A) standard.
See JESD8-9 (JESD8-15A) standard.
V
V
Input Leakage Current
(no pull-up or pull-down)
IIL1
IIL2
IIL3
0
1
μA
μA
μA
Input Leakage Current
(with internal pull-down)
0 (LPDL)
200 (MPUL)
0 (MPUL)
1
1
Input Leakage Current
(with internal pull-up)
−150 (LPDL)
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AMCC Proprietary
Revision 1.09 - May 2, 2008
PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
Table 10. Recommended DC Operating Conditions (Sheet 2 of 2)
Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended
conditions can affect device reliability.
Parameter
Symbol
Minimum
Typical
Maximum
Unit
Notes
I/O Maximum Allowable Overshoot
(3.3V LVTTL and 2.5V/3.3 tolerant CMOS)
VMAO
+3.9
V
3, 4
I/O Maximum Allowable Undershoot
(3.3V LVTTL and 2.5V/3.3 tolerant CMOS)
VMAU
TC
−0.6
−40
V
3,4
Case Temperature
+85
°C
Notes:
1. LPDL is least positive down level; MPUL is most positive up level.
2. Can be extended to 1.1V min., 1.2V typ., 1.3V max. with an estimated power increase of 130mW at 1.2V nom.
3. Maximum duration is 10% of the bus clock period. Bus clock is as follows:
EBC—PerClk
Ethernet—RxClk
USB—USB2Clk
4. Duration of the overshoot is time above VIH max. Duration of the undershoot is time below VIL min.
Power Supply Sequence
All the PPC405EXr I/O designs are power supply sequence independent. There is no requirement that the power
supplies power up in any particular order. The following items are power sequence considerations:
• If the logic power (VDD) is applied before the I/O supply voltages, the I/Os include internal supply sequencing
circuitry that ensures the output of the receiver connected to internal chip logic is 0 until the I/O power is
applied. When the logic power supply is on and the I/O power supplies are off, the I/O logic connected to the
associated ball neither sinks or sources significant current unless influenced by an internal pull-up or pull-down
resistor. While the I/O supply is ramping, the state of the I/O balls are not predictable. This power sequence is
not destructive to the I/Os or internal logic and does not cause any functional problems.
• If the I/O power is applied before the logic power is applied, the output driver output stage (connected to the
balls) will come up in an unknown state (driving 1, driving 0, or tri-state) until the internal logic voltage is stable
within normal operating range. This power sequence is not destructive to the I/Os or internal logic and does not
cause any functional problems.
• External voltage should not be applied to the chip I/O balls before the associated I/O power supply voltage is
applied to the chip.
• A chip power down cycle must complete (all I/O supply voltages and VDD are below +0.4V) before a new
power-up cycle is started.
• During a 405EX power-up cycle, the system reset and test reset inputs should be asserted low. System reset
and test reset should remain asserted until the system clock is stable and then at least 32 system clock times
after all power supplies are stable within normal operating range. Failure to follow this reset sequence during
the power-up cycle might result in unpredictable operation.
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PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
Table 11. I/O Input Capacitance
Parameter
Symbol
Maximum
2.3
Unit
pF
pF
pF
pF
pF
pF
Notes
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
3.3V LVTTL
2.5V CMOS
2.1
2.5/1.8V SSTL2
3.2
PCI Express differential data receiver
PCI Express differential data transmitter
PCI Express differential clock receiver
1.59
1.16
0.188
Table 12. Typical DC Power Supply Requirements with DDR1 SDRAM
+1.2V
+2.5V
+1.8V
(not used
with DDR1)
(VDD+AVDD
)
+3.3V
(SVDD+EOVDD
+
Frequency (MHz)
Total
Unit
Notes
(OVDD
)
AHVDD+SAVDD+EAVDD
)
+1.15V
0.97
1.09
na
+1.25V
na
333
400
na
na
na
0.49
0.55
0.55
0.11
0.11
0.11
1.57
1.75
2.12
W
W
W
1, 2
1, 3
1, 4
na
533
1.46
Notes:
1. Typical power is measured on a typical process part at a case temperature of +85°C with nominal voltages of VDD = +1.15V
for 333MHz and 400MHz and VDD= +1.25V for 533MHz, OVDD = +3.3V, SVDD = +2.5V, and EOVDD = +2.5V while running
Linux and test applications that exercise each function with representative traffic (1 PCI Express, 1 Gigabit Ethernet, USB,
and Security).
2. DDR1 running at 333MHz., PLB running at 166MHz.
3. DDR1 running at 400MHz., PLB running at 200MHz.
4. DDR1 running at 355MHz., PLB running at 177MHz.
Table 13. Typical DC Power Supply Requirements with DDR2 SDRAM
+1.2V
(VDD+AVDD
+2.5V
(EOVDD+AHVDD
)
+1.8V
+3.3V
+
Frequency (MHz)
Total
Unit
Notes
(SVDD
)
(OVDD)
SAVDD+EAVDD
)
+1.15V
0.97
1.09
na
+1.25V
na
333
400
0.21
0.26
0.21
0.18
0.18
0.19
0.11
0.11
0.11
1.47
1.64
1.97
W
W
W
1, 2
1, 3
1, 4
na
533
1.46
Notes:
1. Typical power is measured on a typical process part at a case temperature of +85°C with nominal voltages of VDD = +1.15V
for 333MHz and 400MHz and VDD= +1.25V for 533MHz, OVDD = +3.3V, SVDD = +1.8V, and EOVDD = +2.5V while running
Linux and test applications that exercise each function with representative traffic (1 PCI Express, 1 Gigabit Ethernet, USB,
and Security).
2. DDR2 running at 333MHz., PLB running at 166MHz.
3. DDR2 running at 400MHz., PLB running at 200MHz.
4. DDR2 running at 355MHz., PLB running at 177MHz.
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PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
Table 14. DC Power Supply Loads with DDR1 SDRAM
Parameter
Symbol
Typical
Maximum
Unit
mA
mA
mA
mA
mA
mA
mA
Notes
V
DD (+1.2V) active operating current
IDD
1192
4
2220
10
2
1
1
1
1
1
1
1
AVDD (+1.2V) active operating current
AHVDD (+2.5V) active operating current
OVDD (+3.3V) active operating current
SVDD + EOVDD (+2.5V) active operating current
SAVDD (+2.5V) active operating current
EAVDD (+2.5V) active operating current
Notes:
IADD
IAHDD
IODD
1
35
196
1
50
235
2
IEOSDD
ISADD
IEADD
1
2
1. The maximum current values listed above are not guaranteed to be the highest obtainable. These values are dependent on many
factors including the type of applications running, clock rates, use of internal functional capabilities, external interface usage, case
temperature, and the power supply voltages. Your specific application can produce significantly different results. VDD (logic) current and
power are primarily dependent on the applications running and the use of internal chip functions (DMA, PCI Express, Ethernet, and so
on). OVDD (I/O) current and power are primarily dependent on the capacitive loading, frequency, and utilization of the external buses.
The information in this table provides details about the conditions under which the listed values were obtained. Maximum power is
measured on a best-case process (worst-case power) part running at 600MHz with a case temperature of +85°C and with voltages of
V
DD = +1.30V, OVDD = +3.45V, SVDD = +2.6V, and EOVDD = +2.6V while running Linux and test applications that exercise each
function with representative traffic (2 PCI Express, 2 Gigabit Ethernet, USB, Security).
Table 15. DC Power Supply Loads with DDR2 SDRAM
Parameter
Symbol
Typical
Maximum
Unit
mA
mA
mA
mA
mA
mA
mA
mA
Notes
V
DD (+1.2V) active operating current
IDD
1165
4
2220
10
2
1
1
1
1
1
1
1
1
AVDD (+1.2V) active operating current
AHVDD (+2.5V) active operating current
OVDD (+3.3V) active operating current
SVDD (+1.8V) active operating current
EOVDD (+2.5V) active operating current
SAVDD (+2.5V) active operating current
EAVDD (+2.5V) active operating current
Notes:
IADD
IAHDD
IODD
1
25
145
76
1
50
155
80
2
ISDD
IEODD
ISADD
IEADD
1
2
1. The maximum current values listed above are not guaranteed to be the highest obtainable. These values are dependent on many
factors including the type of applications running, clock rates, use of internal functional capabilities, external interface usage, case
temperature, and the power supply voltages. Your specific application can produce significantly different results. VDD (logic) current and
power are primarily dependent on the applications running and the use of internal chip functions (DMA, PCI Express, Ethernet, and so
on). OVDD (I/O) current and power are primarily dependent on the capacitive loading, frequency, and utilization of the external buses.
The information in this table provides details about the conditions under which the listed values were obtained. Maximum power is
measured on a best-case process (worst-case power) part running at 600MHz with a case temperature of +85°C and with voltages of
V
DD = +1.30V, OVDD = +3.45V, SVDD = +2.6V, and EOVDD = +2.6V while running Linux and test applications that exercise each
function with representative traffic (2 PCI Express, 2 Gigabit Ethernet, USB, Security).
AMCC Proprietary
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Revision 1.09 - May 2, 2008
PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
Test Conditions
Clock timing and switching characteristics are specified in accordance with minimum
operating conditions shown in the table “Recommended DC Operating Conditions” on
page 50. For all signals, AC specifications are characterized at TC = 85°C with the test
load shown in the figure to the right.
Output
Pin
10pF
Table 16. System Clocking Specifications
Symbol
CPU
Parameter
Min
Max
Units
PFC
Processor clock frequency (must be ≥ SCFC)
333.33
533.33
MHz
SysClk Input
SCFC
Frequency
33.33
na
100
± 0.1
60
MHz
ns
SCTCS
SCTCH
SCTCL
SCRT
Edge stability (phase jitter, cycle-to-cycle)
High time (% of nominal period)
Low time (% of nominal period)
Rise time
40
%
40
60
%
na
1
ns
Note: Input slew rate = 1V/ns
Other Clocks
VCOFC
PLBFC
OPBFC
VCO frequency
PLB frequency
OPB frequency
600
133
66
1600
200
MHz
MHz
MHz
100
Figure 3. Clocking Waveform
2.0V
1.5V
0.8V
T
T
CL
CH
T
C
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Revision 1.09 - May 2, 2008
PPC405EXr – PowerPC 405EXr Embedded Processor
Spread Spectrum Clocking
Preliminary Data Sheet
Care must be taken if using a spread spectrum clock generator (SSCG) with the PPC405EXr. This controller uses
a PLL for clock generation inside the chip. The accuracy with which the PLL follows the SSCG is called tracking
skew. The PLL bandwidth and phase angle determine how much tracking skew exists between the SSCG and the
PLL for a given frequency deviation and modulation frequency. If using an SSCG with the PPC405EXr the
following conditions must be met:
• The frequency deviation must not violate the minimum clock cycle time. Therefore, when operating the
PPC405EXr with one or more internal clocks at their maximum supported frequency, the SSCG can only lower
the frequency.
• The maximum frequency deviation must not exceed −3%, and the modulation frequency must not exceed
40kHz. In some cases, on-board PPC405EXr peripherals impose more stringent requirements (see Note 1).
• Use the peripheral bus clock for logic that is synchronous to the peripheral bus because this clock tracks the
modulation.
Notes:
1. The serial port baud rates are synchronous to the modulated clock. The serial port has a tolerance of
approximately 1.5% on baud rate before framing errors begin to occur, assuming that the connected device is
running at precise baud rates. If an external serial clock is used, baud rate is unaffected by the modulation.
2. Ethernet operation is unaffected.
3. IIC operation is unaffected.
4. For PCI-E see the PCI Express I/O Specifications.
Caution: The system designer must ensure that any SSCG used with the PPC405EXr meets these requirements
and does not adversely affect other aspects of the system.
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Revision 1.09 - May 2, 2008
PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
Table 17. Peripheral Interface I/O Clock Timings (not SDRAM or PCI-E)
Clock
Min
Max
Units
MHz
ns
Notes
GMCTxClk frequency
GMCTxClk high time
GMCTxClk low time
GMCRxClk frequency
GMCRxClk high time
GMCRxClk low time
GMCGTxClk
125
125
45% of nominal
–
55% of nominal
–
ns
125
125
MHz
ns
45% of nominal
–
55% of nominal
–
ns
125
125
MHz
MHz
MHz
ns
GMCMDClk
2.5
25
GMCRefClk
125
125
GMCRefClk edge stability (phase jitter, cycle-to-cycle)
na
± 0.1
GMCRefClk rise time
GMCRefClk high time
GMCRefClk low time
GMC1RxClk
GMC1TxClk
UARTSerClk
TmrClk
na
40% of nominal
60% of nominal
125
1
ns
–
ns
–
ns
125
125
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
125
1000 / 2TOPB1 + 2ns
1
2
na
33
100
100
20
PerClk
TCK
na
USB2Clk (60MHz ± 0.05%)
TrcClk
57.97
66
60.03
300
Notes:
1. TOPB is the period in ns of the OPB clock. The internal OPB clock runs at an integral divisor ratio of the frequency of the PLB clock. The
maximum OPB clock frequency is 100MHz.
2. TrcClk is 1/2 CPU Clk. The maximum CPU Clk supported for instruction trace is 400 MHz.
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PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
Figure 4. Input Setup and Hold Timing Waveform
System Clock
1.5V
T
T
IS
IH
MIN
MIN
Inputs
1.5V
Valid
Figure 5. Output Delay and Float Timing Waveform
System Clock
1.5V
1.5V
T
T
OH
OV
MAX
MIN
Outputs
Valid
MAX
T
OF
MIN
1.5V
Outputs
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PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
Figure 6. Input Setup and Hold Timing Waveform for RGMII Signals
GMCnRxClk
1.25V
T
T
T
IS
T
IH
IH
IS
MIN
MIN
MIN
MIN
Inputs
1.25V
Valid
Valid
RGMII 1000Mb timing is with reference to the raising and falling edge of GMCnRxClk.
RGMII 10/100Mb timing is with reference only to the raising edge of GMCnRxClk.
Figure 7. Output Delay and Hold Timing Waveform for RGMII Signals
GMCnTxClk
1.25V
T
T
OH
OH
MIN
MIN
T
OV
T
OV
Outputs
MAX
MAX
High (Drive)
Float (High-Z)
Low (Drive)
Valid
Valid
Valid
Valid
RGMII 1000Mb timing is with reference to the raising and falling edge of GMCnTxClk.
RGMII 10/100Mb timing is with reference only to the raising edge of GMCnTxClk.
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PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
Table 18. I/O Specifications
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
Input (ns)
Output (ns)
Output Current (mA)
Signal
Clock
Notes
Setup Time Hold Time
Valid Delay
(TOV max)
Hold Time
(TOH min)
IOH
(min)
IOL
(min)
(TIS min)
(TIH min)
Ethernet GMII Interface
GMCMDIO
GMCCD
na
2
na
0
na
na
5.51
na
7.23
na
Async
1
1
1
1
1
1
1
1
1
Async
GMCCrS
2
0
na
na
Async
GMCRxD0:7
GMCRxDV
GMCRxEr
1.85
1.95
1.95
0
na
na
GMCRxClk
GMCRxClk
GMCRxClk
GMCGTxClk
GMCGTxClk
GMCGTxClk
0
na
na
0
na
na
GMCTxD0:7
GMCTxEr
2.3
2.4
2.4
2.0
2.0
2.0
5.51
5.51
5.51
7.23
7.23
7.23
GMCTxEn
Ethernet RGMII Interface (n = 0 or 1)
GMCnRxD0:3
GMCnRxCtl
GMCnTxD0:3
GMCnTxCtl
0.7
0.8
1
1
na
na
na
na
GMCnRxClk
GMCnRxClk
GMCnTxClk
GMCnTxClk
1
1
1
1
0.5
0.5
2.7
2.7
5.51
5.51
7.23
7.23
Internal Peripheral Interfaces (not SDRAM or PCI-E)
IICnSData
na
10.46
10.46
10.46
10.46
10.46
10.46
10.46
na
UARTnCTS
na
na
15.75
15.75
15.75
15.75
15.75
15.75
na
UARTnRTS
UARTnDSR
UARTnDCD
UARTnDTR
UARTnRI
UARTnRx
UARTnTx
SCPDI
na
na
na
na
na
na
na
na
na
na
na
na
na
na
15.75
na
10.46
na
SCPDO
na
10.46
10.46
na
USB2Data0:7
USB2Dir
3.9
3.7
3.5
0
0
0
6.3
6.4
2
2
15.75
na
USB2Clk
USB2Clk
USB2Clk
USB2Clk
USB2Next
USB2Stop
DMA Interface
DMAAck0:3
DMAReq0:3
DMAEOT0:3
Interrupts Interface
IRQ0:9
na
na
6.4
5.2
5.3
2
15.75
10.46
1.0
1.0
15.75
na
10.46
na
PerClk
PerClk
PerClk
2.4
2
1
1
15.75
10.46
15.75
10.46
JTAG Interface
TDI
na
15.75
na
na
10.46
na
TDO
TMS
TRST
na
na
AMCC Proprietary
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Revision 1.09 - May 2, 2008
PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
Table 18. I/O Specifications
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
Input (ns)
Output (ns)
Output Current (mA)
Signal
Clock
Notes
Setup Time Hold Time
Valid Delay
(TOV max)
Hold Time
(TOH min)
IOH
(min)
IOL
(min)
(TIS min)
(TIH min)
System Interface
GPIO00:10
GPIO11:15
GPIO16:27
GPIO28
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
11.08
5.51
11.08
15.75
11.08
na
7.37
7.23
7.37
10.46
7.37
na
GPIO29:31
Halt
SysErr
5.51
5.51
7.23
7.23
SysReset
External Peripheral Interface
PerAddr05:31
PerCS0:3
PerData00:31
PerDataPar0:3
PerOE
1.8
1
5.3
5.2
5.3
5.3
5.2
1
1
1
1
1
11.08
11.08
11.08
11.08
11.08
na
7.37
7.37
7.37
7.37
7.37
na
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
2.7
1.9
1
1
PerReady
PerRW
2
1
1
1
1
1
1.8
1.7
2
5.3
5.1
5
1
1
1
1
1
1
1
1
1
11.08
11.08
11.08
11.08
11.08
11.08
na
7.37
7.37
7.37
7.37
7.37
7.37
na
PerWBE0:3
PerBLast
PerErr
1.9
5.3
5.3
5.1
5.2
5.2
5
ExtReset
BusReq
2.3
2
1
1
HoldReq
HoldAck
11.08
11.08
na
7.37
7.37
na
ExtAck
2.3
2
1
1
ExtReq
5.3
5.3
5.3
5.3
5.3
NFALE
1
1
1
1
11.08
11.08
11.08
11.08
na
7.37
7.37
7.37
7.37
na
NFCE0:3
NFCLE
NFData0:15
NFRdyBusy
NFREn
2.3
1.7
1
1
5.3
5.3
1
1
11.08
11.08
7.37
7.37
NFWEn
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AMCC Proprietary
Revision 1.09 - May 2, 2008
PPC405EXr – PowerPC 405EXr Embedded Processor
DDR 2/1 SDRAM I/O Specifications
Preliminary Data Sheet
The DDR SDRAM controller times its operation using the internal PLB clock signal and generates MemClkOut from
the PLB clock. The PLB clock is an internal signal that cannot be directly observed. However MemClkOut is the
same frequency as the PLB clock signal and is in phase with the PLB clock signal.
Note: MemClkOut can be advanced with respect to the PLB clock by means of the SDRAM0_CLKTR
programming register. In a typical system, users advance MemClkOut by 90°. This depends on the specific
application and requires a thorough understanding of the memory system in general (refer to the DDR
SDRAM Controller chapter in the PPC405EXr Embedded Processor User’s Manual).
The signals are terminated as indicated in Figure 8 for the DDR timing data and output currents in the following
sections.
Figure 8. DDR SDRAM Simulation Signal Termination Model
MemClkOut0
10pF
120Ω
10pF
MemClkOut0
V
= SOV /2
DD
TT
PPC405EXr
50
Ω
Addr/Ctrl (DDR2)
Addr/Ctrl/Data/DQS/DM (DDR1)
30pF
Note: This diagram illustrates the model of the DDR SDRAM interface used when generating simulation timing data.
It is not a recommended physical circuit design for this interface. An actual interface design depends on many
factors, including the type of memory used and the board layout.
DDR2 SDRAM On-Die Termination Impedance Setting
For all DDR2 applications, the On-Die Termination (ODT) impedance value must be set to 75 ohms in the DIMM
Extended Mode Register (EMR) in order to optimize the data transmission during memory write operations.
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PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
Table 19. DDR SDRAM Output Driver Specifications
Output Current (mA)
Signal Path
I/O H (maximum)
I/O L (maximum)
Write Data
MemData00:31
ECC0:7
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
DM0:4
MemClkOut0
MemAddr00:14
BA0:2
RAS
CAS
WE
BankSel0:1
MemClkEn
DQS0:4
MemODT0:1
DDR SDRAM Write Operation
The rising edge of MemClkOut aligns with the first rising edge of the DQS signal on writes as indicated in Figure 9.
DQS rising and falling edges are centered on valid data for writes.
The data in Table 20 is generated by means of simulation and includes logic, driver, package RLC, and lengths.
Values are calculated over best case and worst case processes with speed, junction temperature, and voltage as
follows:
Table 20. DDR SDRAM Write Operation Conditions
Case
Best
Process Speed
Fast
Junction Temperature (°C)
Voltage (V)
+1.3
−40
Worst
Slow
+125
+1.1
Note: In the following tables and timing diagrams, minimum values are measured under best case conditions and
maximum values are measured under worst case conditions. The timing numbers in the following sections are
obtained using a simulation that assumes a model as shown in Figure 8.
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PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
The following diagram illustrates the relationship among the signals involved with a DDR write operation.
Figure 9. DDR SDRAM Write Cycle Timing
PLB Clk
MemClkOut0
T
SA
Addr/Cmd
T
DS
T
HA
T
DS
DQS
T
SD
T
SD
MemData
T
HD
T
HD
T
= Setup time for address and command signals to MemClkOut0
= Hold time for address and command signals from MemClkOut0
SA
T
HA
SD
HD
T
= Setup time for data signals (minimum time data is valid before rising/falling edge of DSQ)
= Hold time for data signals (minimum time data is valid after rising/falling edge of DSQ)
= Delay from rising/falling edge of clock to the rising/falling edge of DQS
T
T
DS
Note: The timing data in the following tables is based on simulation runs using Einstimer.
Table 21. I/O Timing—DDR SDRAM T
DS
Notes:
1. All of the DQS signals are referenced to MemClkOut0 with the DQS delay line programmed to 1 cycle.
2. Clock speed is 200MHz.
TDS (ns)
Signal Name
Minimum
Maximum
DQS0
DQS1
DQS2
DQS3
DQS4
4
4
4
4
4
6
6
6
6
6
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PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
Table 22. I/O Timing—DDR SDRAM T and T
SA
HA
TSA (ns) Minimum
THA (ns Minimum)
Signal Name
MemAddr00:14
BA0:2
1.08
1.12
1.09
1.10
1.10
1.09
1.08
1.12
1.15
1.13
1.16
1.13
1.12
1.16
BankSel0:1
MemClkEn
CAS
RAS
WE
Table 23. I/O Timing—DDR SDRAM Write Timing T and T
SD
HD
Notes:
1. TSD and THD are measured under worst case conditions.
2. Clock speed for the values in the table is 200MHz.
3. The time values in the table include 1/4 of a cycle at 200MHz (5ns x 0.25 = 1.25 ns).
4. To obtain adjusted TSD and THD values for lower clock frequencies, subtract 1.25 ns from the values in the table and add 1/4
of the cycle time for the lower clock frequency (for example, TSD − 1.25 + 0.25TCYC).
TSD (ns)
THD (ns)
Signal Names
MemData00:07, DM0
MemData08:15, DM1
MemData16:23, DM2
MemData24:31, DM3
ECC0:7, DM4
Reference Signal
DQS0
1.067
1.074
1.082
1.088
1.012
0.973
0.973
0.973
0.973
0.973
DQS1
DQS2
DQS3
DQS4
DDR SDRAM Read Operation
Data on a read is edge aligned with DQS. To capture the incoming data on the rising and falling edges, DQS is
delayed by the DDR controller in order to center a DQS edge on valid data. Programmable registers control the
delay.
DDR SDRAM MemClkOut0 and Read Clock Delay
In order to accommodate timing variations introduced by memory layout and process, a three-stage data path is
used to eliminate metastability and allow data sampling to be adjusted for minimum latency.
Figure 10 shows the data read path of a single data bit. Data entering on the left is captured in the Stage 1 Flip
Flops. Four Flip Flops are needed to capture an entire four beat burst on the DDR interface. The DDR controller
only supports burst of four. Data captured on the rising edge of DQS is stored in the even numbered Flip Flops.
Like wise, data captured on the falling edge of DQS is stored in the odd numbered Flips Flops.
To latch the data in Stage 1, a delayed version of DQS is used. Initialization software is responsible for tuning the
DQS delay timing so that DQS is centered on valid data. Since there is process variation between parts and
possible voltage variations on boards, read tuning is required. Fixed DQS delay values should not be used on
production systems.
The Feedback Data Capture Window selects which Flip Flop is used to store the data sampled by DQS. Each
output of this block generates a pulse to an input multiplexer. The series of four pulses selecting the input
multiplexer is initiated by a feedback signal pulse on the input of the Feedback Data Capture Window. The DDR
controller calculates when to assert the feedback signal based on when the data should be present after a read
command.
The width of the feedback pulse is the same as DDR 1X clock. The internal DDR 1X clock is the same frequency
as MemClkOut0. MemClkOut0 is slightly delayed relative to DDR 1X clock due to the insertion delay of the drivers.
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PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
The feedback signal to the Feedback Data Capture Window is adjusted for propagation delay by the fine/coarse
delays and is automatically adjusted for variations in the DDR I/O due to supply voltage and temperature.
Compensation for driver/receiver variations is accomplished by driving and receiving the feedback signal on the
external MemFBD and MemFBR pins. Tuning the fine/coarse delays adjust for propagation delay. When properly
tuned, the feedback pulse is aligned to the first DQS in a four beat burst such that the rising edge of DQS is
nominally centered on the feedback pulse. Software must adjust the pulse using the fine/coarse delays when
tuning read DQS delay.
Note: Using minimum trace length, connect MemFBD directly to MemFBR.
The data captured in Stage 1 is relative to the DQS timing domain and is held for four DDR 1X cycles. Stage 2
samples the data in Stage 1 attempting to capture the data in the DDR 1X domain. The on-time-sample clock from
the Stage 2 Store block samples the Stage 1 data at sample cycle T1, T2, T3 or T4. The sample cycle is either
selected by initialization software or can be automatically selected and adjusted by the DDR controller. The Stage
1 data is sampled a second time by the over sample clock at a delayed sample point. The delay between the on-
time-sample and over sample clocks is the Over-Sampling-Guard-Band.
The feedback pulse is sampled with the data captured by the first DQS in the four beat burst. A match of one or
both of the sample clocks with the feedback pulse is a hit. The DDR controller based on hits or misses by the on-
time sample and over sample clocks adjust the sample cycle in order to track variations in DQS. Burst data from a
sample hit is passed to Stage 3.
In Stage 3 the data is synchronized to the PLB clock domain and eventually driven onto the PLB bus. The data
captured on the rising and falling DQS edges is unpacked into the correct bit locations on the upper (0:63) and
lower (64:127) PLB bus. When ECC is enable, ECC checking and corrections is done after Stage 3.
Figure 12 illustrates how the three Stage read logic captures the data in the DQS timing domain and synchronizes
it to the PLB clock domain. The first DQS of four beat burst is roughly centered on feedback signal pulse.
AMCC Proprietary
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PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
Figure 10. DDR SDRAM Read Data Path for a Single Data Bit
FF: Flip-Flop
DDR 1X Clock
Ext FeedBack
Signals
Driver
MemFBD
FeedBack
Signal Gen
Coarse Delay
CAS Lat Delay
Read Start
DDR 1X Clock
Rec
Read Latency adjust circuit
Stage 2 Store
Oversampling
Fine Delay
MemFBR
Fine Delay
(Guard Band)
DQS aligned
feedback signal
Cycles
Delay
+1
Feedback
T1 T2 T3 T4
On-time sample clock
Data Capture
Window
Adjust
Oversampling
Clock
0
1
2
Q2_Ovs
3
Package
pins
0
2
FF
Q3
Compare
FF
Q2
PLB bus
FF
(x64+ECC)
D
Read FIFO
[0:63]
Mux
C
Mux
Upper
DQS Rising
Edge Sync
MemData
Stage 2
Stage 3
Stage 1
Lower
(x32 bits +
x8 bits ECC)
FF
FF
Q3
1
3
(x64+ECC)
Q2
PLB bus
FF
D
[64:127]
Mux
C
Mux
Programmed
Read DQS
Delay
DQS Falling
Edge Sync
DQS
(x4 + x1
ECC bits)
DDR 1X Clock
PLB 1X Clock
ECC detection and correction if enabled occurs after Stage 3 before completing the read on the PLB.
DDR SDRAM Read Cycle Timing
The following diagram illustrates the relationship of the signals involved with a DDR read operation.
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PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
Figure 11. DDR SDRAM Memory Data and DQS
DQS
T
SD
MemData
T
HD
Table 24. I/O Timing—DDR SDRAM Read Timing T and T
SD
HD
1. TSD and THD are measured under worst case conditions.
2. Clock speed for the values in the table is 200MHz.
3. The time values in the table include 1/4 of a cycle at 200MHz (5ns x 0.25 = 1.25 ns).
4. To obtain adjusted T and T values for lower clock frequencies, subtract 0.75 ns from the values in the table and add 1/4
SD
HD
of the cycle time for the lower clock frequency (e.g., T
- 1.25 + 0.25T
).
SD
CYC
Read Data vs DQS Set up
TSD (ns)
Read Data vs DQS Hold
THD (ns)
Signal Names
MemData00:07
Reference Signal
DQS0
DQS1
DQS2
DQS3
DQS4
0.27
0.27
0.27
0.27
0.27
0.45
0.45
0.45
0.45
0.45
MemData08:15
MemData16:23
MemData24:31
ECC0:7
In the following example, the data strobes (DQS) and the data are shown to be coincident. There is actually a slight
skew as specified by the SDRAM specifications, and there can be additional skew due to loading and signal
routing. It is recommended that the signal length for all of the DQS signals be matched.
The following example shows the timing relationship between SDRAM DDR Data at the input pin and storing the
data in Stage 1.
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PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
Figure 12. DDR SDRAM Read Cycle Timing—Example
Oversampling Guard Band
DDR 1X Clock
DDR 2X Clock
MemClkOut0 (Diff.)
DQS at Pin
Data at Pin
D0
D2
D3
D4
D5
D6
D7
D8
D9
D1
Store 1st Data
in Stage 2
MemFBR at Pin
T1
T2
T3
T4
DDR 1X Clock cycle
Delayed DQS
Data Out Stage 1 (0)
Data Out Stage 1 (1)
Data out Stage 1 (2)
Valid
High
Low
D0
D1
D2
D3
Data Out Stage 2
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PPC405EXr – PowerPC 405EXr Embedded Processor
PCI Express (PCI-E) I/O Specifications
Preliminary Data Sheet
The following tables provide the required I/O timing information regarding the use of the PCI Express interface on
this chip.
Table 25. PCI-E Receiver I/O Specifications
Parameter
Minimum
Maximum
Units
ps
Notes
Unit Interval (UI)
399.88
175
0.4
-
400.12
Differential Rx peak-peak voltage
Receiver eye time opening
1200
-
mV
UI
Maximum time delta between median and deviation from median
Rx differential return loss
0.3
-
UI
10
dB
dB
Ω
Common mode Rx return loss
6
-
Receiver DC common mode impedance
DC differential impedance
40
60
120
150
-
80
Ω
Rx AC common mode voltage
-
mV
kΩ
ns
DC Input CM input impedance during reset or power down
Electrical idle detect threshold
200
65
125
Table 26. PCI-E Reference Clock I/O Specifications
Parameter
Minimum
100
Maximum
100
Units
MHz
ppm
%
Notes
PCI_E reference clock frequency (PCIEnClkC and PCIEnClkT )
1
Accuracy
-300
+300
55
Duty cycle
45
-6
-
86
ps
3
2
Peak-to-peak jitter for 1E-6 BER (1 x 10 bit error rate)
Spread Spectrum Clock (SSC) frequency
Common mode voltage
Differential signal amplitude
Notes:
30
0
33
kHz
mV
mV
1600
1600
200
1. The PCI-E reference clock frequency specification does not include +/- 300ppm accuracy specification.
2. The data rate can be modulated from +0.5% to −0.5% of the nominal data rate frequency, at a modulation rate in the range not
exceeding 30kHz–33kHz. The +/- 600ppm requirement remains which requires the two communcicating ports to be modulated so that
they never exceed a total of 600ppm difference. For most implementations, this requires that both ports have the same bit rate clock
source when the data is modulated with an SSC.
3. 1E-6 is the probability that the jitter is greater than 86ps peak-to-peak.
AMCC Proprietary
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Revision 1.09 - May 2, 2008
PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
Table 27. PCI-E Transmitter I/O Specifications
Parameter
Minimum
399.88
800
Maximum
Units
ps
Notes
Unit Interval (UI)
400.12
Differential p-p Tx voltage swing
Low power differential p-p Tx voltage swing
Tx de-emphasis level ratio
-
mV ppd
mV ppd
dB
400
-
-4.0
-
-3.0
Minimum Tx eye width
0.75
UI
Maximum time between the jitter median and maximum
deviation from the median
-
0.125
UI
Transmitter rise and fall time
Maximum Tx PLL bandwidth
Minimum Tx PLL BW for 3dB peaking
Tx AC common mode voltage
0.125
-
UI
-
1.5
-
22
-
MHz
MHz
mV
20
Absolute Delta of DC Common Mode Voltage during L0 and
Electrical Idle.
0
100
mV
Absolute Delta of DC Common Mode Voltage between PCIEnTx
and PCIEnTx
0
0
-
25
20
mV
mV
mV
Electrical Idle Differential Peak Output Voltage
The amount of voltage change allowed during Receiver
Detection
600
Transmitter DC common-mode voltage
Transmitter short-circuit current limit
Minimum time spent in Electrical Idle
0
-
3.6
90
-
V
mA
ns
20
Maximum time to transition to a valid Electrical Idle after sending
an EIOS
-
-
8
8
ns
ns
Maximum transition time to valid differential signaling after
leaving Electrical Idle
Differential return loss
10
6
-
-
dB
dB
Ω
Common mode return loss
DC differential Tx impedance
80
120
70
AMCC Proprietary
Revision 1.09 - May 2, 2008
PPC405EXr – PowerPC 405EXr Embedded Processor
Initialization
Preliminary Data Sheet
The following describes the method by which initial chip settings are established when a system reset occurs.
Strapping
When the SysReset input is driven low (system reset), the state of certain I/O pins is read in order to enable default
initial conditions before PPC405EXr start-up. The actual instant of capture is the nearest system clock edge before
the deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-down (logical 0)
resistors to select the desired default conditions. The recommended pull-up is 3kΩ to +3.3V, or 10kΩ to +5V. The
recommended pull-down is 1kΩ to GND. These pins are only used for strap functions during reset. They are used
for other signals during normal operation. The following table lists the strapping pins along with their functions and
strapping options. The signal names assigned to the pins for normal operation appear below the pin number.
Table 28. Strapping Pin Assignments
Pin Strapping
F04
(UART0DCD)
F02
(UART0DSR)
G02
(UART0CTS)
Initialization Source
EBC 8-bit wide ROM
Option
A
B
C
D
E
G
F
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
EBC 16-bit wide ROM
EBC 16-bit wide ROM
EBC 8-bit wide NAND Flash
EBC 8-bit wide NAND Flash
IIC ROM at address 0xA8
EBC 8-bit wide ROM
IIC ROM at address 0xA4
H
Note: See the PPC405EXr Embedded Processor User’s Manual for option descriptions and other details regarding the boot process.
AMCC Proprietary
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Revision 1.09 - May 2, 2008
PPC405EXr – PowerPC 405EXr Embedded Processor
Revision Log
Preliminary Data Sheet
Date
Version
1.00
Contents of Modification
06/07/2007
06/28/2007
Initial creation of document.
Updates and corrections.
1.01
Correct AMCC phone numbers.
Change PerErr to always pull down.
Add revised I/O timing figures from 405EX DS.
Implement doc issues 374 and 382.
10/25/2007
1.02
Major updates to DDR SDRAM section (and other parts of the DS) (Doc issue 392).
Add PCI-E I/O specifications.
I/O timing values updates.
Change boot-from-EBC support (Doc Issue 383).
Six voltage pins originally labeled SVDD changed to EOVDD
.
11/21/2007
01/04/2008
1.03
1.04
S2VDD changed to SVDD.
Add TrcClk to Table 17.
Implemented document Issues 412, 436, and 440.
Note: Automatic change bars now appear on all updates.
Implemented doc issue 447:
Supply voltage changes (wider voltage range with increased power consumption).
Remove common mode voltage specs.
Change DDR SDRAM and PCI-E specs.
01/15/2008
01/16/2008
1.05
1.06
Correct voltage changes.
Change frequency spec on Analog supply voltage.
Update SDRAM write timing.
02/13/2008
02/15/2008
1.07
1.08
Update PCIEnClk signal description.
Increase PCI-E differential signal amplitude to 1600mV (doc issue 468).
Change power consumption numbers from estimated to measured..
Change number of RGMII interfaces from two to one (Doc Issue 476).
Misc updates (Doc Issue 482).
05/02/2008
1.09
Remove GMCMDIO timing numbers (Doc Issue 495).
Add power sequence information (Doc Issue 509)
Change GMCRefClk signal description (Doc Issue 523)
72
AMCC Proprietary
Revision 1.09 - May 2, 2008
PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
Applied Micro Circuits Corporation
215 Moffett Park Drive, Sunnyvale, CA 94089
Phone: (408) 542-8600 — (800) 840-6055 — Fax: (408) 542-8601
http://www.amcc.com
AMCC reserves the right to make changes to its products, its datasheets, or related documentation, without notice and war-
rants its products solely pursuant to its terms and conditions of sale, only to substantially comply with the latest available
datasheet. Please consult AMCC’s Term and Conditions of Sale for its warranties and other terms, conditions and limitations.
AMCC may discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest
version of relevant information to verify, before placing orders, that the information is current. AMCC does not assume any lia-
bility arising out of the application or use of any product or circuit described herein, neither does it convey any license under
its patent rights nor the rights of others. AMCC reserves the right to ship devices of higher grade in place of those of lower
grade.
AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE
SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL
APPLICATIONS.
AMCC is a registered Trademark of Applied Micro Circuits Corporation. Copyright © 2008 Applied Micro Circuits Corporation.
AMCC Proprietary
73
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