S19252 [AMCC]
STS-192 SONET/SDH/FEC/GbE/FC 16-bit EDC Transceiver with 10 G Clock; STS -192 SONET / SDH / FEC /千兆以太网/光纤通道的16位收发器EDC用10克钟
| 型号： | S19252 |
| 厂家： | 
APPLIED MICRO CIRCUITS CORPORATION |
| 描述： | STS-192 SONET/SDH/FEC/GbE/FC 16-bit EDC Transceiver with 10 G Clock |
| 文件： | 总2页 (文件大小：148K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
P R O D U C T B R I E F
S19252
STS-192 SONET/SDH/FEC/GbE/FC 16-bit EDC Transceiver with 10 G Clock
AMCC Suggested Interface Devices
Features
Description
•
•
•
Operational from 9.9 Gbps to 11.3 Gbps
Built-In Self Test (BIST) with Error Counter
On-chip High-Frequency PLLs for Clock Recov-
ery and Clock Gen.
The S19252 MUX/DeMux chip is a fully
integrated serialization/de-serialization SONET
STS-192/10 GB Ethernet/Fiber Channel
transceiver with Electronic Dispersion
Compensation (EDC). This device can be used
to compensate channel impairments caused by
Single Mode Fiber (SMF) and copper medium.
The chip performs all necessary parallel-to-serial
and serial-to-parallel functions in conformance
with SONET/SDH, 10 Gigabit Ethernet (10 GbE)
and 10 Gigabit Fibre Channel (10 G FC)
transmission standards. The figure below shows
a typical network application. The other
application block diagrams are shown on
page 2.
GANGES (S19202)
Rubicon/Niagara
HUDSON (S19203)
STS-192 POS/ATM SONET/SDH
Mapper
OC-192/48/12/3 DW/FEC/PM and
ASYNC Mapper Device
•
•
•
•
16-bit LVDS Parallel Data Path
TX and RX Lock Detect Indicators
Reference Loop Timing Modes
Line and Diagnostic Loopback Mode for Faulty
Node Identification
-40°C to 85°C Industrial Temperature Range
Supports MDIO, I2C and SPI serial interface
Complies with applicable OIF SFI-4 Phase 1,
Telcordia/ITU-T, 300-pin MSA, IEEE 802.3ae
and XFP MSA Standards
Variable Rate Digital Wrapper
Framer/Deframer, Performance
Monitor, and FEC Device
•
•
•
MEKONG (S19204)
STS-192 Pointer Processor
KHATANGA (S19205)
STS-192c SONET/SDH Framer/Map-
per with Integrated MAC
•
•
2000 V ESD rating on low speed pins, 1000 V
on high speed I/Os
2
15 mm x 15 mm , 0.8 mm pitch package with
Green / RoHS compliant lead free option.
1.2 W typical
S19233
Dual CDR imbedded in XFP module
•
•
JTAG support
The sequence of operations is as follows:
Transmitter Features
•
On-chip clock synthesis PLL components are
contained in the S19252 chip, allowing the use
of a slower external transmit clock reference.
The chip can be used with 155.52 MHz or 622.08
MHz (or equivalent FEC/10 GbE/10 G FC rates)
reference clocks, in support of existing system
clocking schemes. The low-jitter LVDS interface
guarantees compliance with the bit-error rate
requirements of the Telcordia and ITU-T
standards.
Ref. Freq. of 155.52 or 622.08 MHz (or eq. FEC
rate); Common 10 GbE/10 G FC Ref. of
156.25 MHz or 159.375 MHz for 10 G FC;
Divide by 16 or 64 of the TX rates
Internal, Self-Initializing FIFO to Decouple
Transmit Clocks
Programmable TSD Output Differential Swing
10 G Transmitter Serial Clock Output
Duo Binary Encoding
Transmitter Operations
•
•
•
•
16-bit parallel input
Parallel-to-serial conversion
Serial data output
•
Serial clock output
Receiver Operations
•
•
•
•
•
•
•
•
•
•
Serial input to post-Amplifier
ISI compensation
LOS and RSSI
Threshold and phase adjustment for improved BER
Clock and data recovery
Serial-to-parallel conversion
16-bit parallel data and clock output
Receiver Features
•
•
LOS/RSSI
ISI compensation. Tolerates additional 350 ps/
nm of chromatic dispersion with an OSNR
penalty of 1.0dB over a traditional demux
Tolerates up to 36” of Standard FR-4 Material
Adaptive Post-Amplifier Offset Adjust
Phase Adjust of -0.11 to +0.085 UI
Overview
•
•
•
•
Internal clocking and control functions are
transparent to the user.
The S19252 transceiver incorporates SONET/
SDH/10 GbE/10 G Fibre Channel serialization
and deserialization functions. This chip can be
used to implement the front end of SONET/10
GbE/10 G Fibre Channel equipment, which
consists primarily of the serial transmit interface
and the serial receive interface. The chip
includes parallel-to-serial, and serial-to-parallel
conversion and system timing.
Ref. Freq. of 155.52 MHz or 622.08 MHz (or eq.
FEC rate); Common ref. of 156.25 MHz for 10
GbE/10 GFC or 159.375 MHz for 10 GFC; Divide
by 16 or 64 of the RX rates
•
•
Capability to Interface with Single-Ended or
Differential TIAs (Center Tap Option)
Input Sensitivity of 10 mV p-p (one wire or
-12
two wire) at 10 BER
Applications
•
SONET/SDH and 10GbE-Based Transmission
Systems & Modules
•
•
•
•
Section Repeaters
Add Drop Multiplexers (ADM)
Broad-Band Cross-Connects
Fiber Optic Test Equipment
16
16
10G clk
data
OTX
ORX
ORX
OTX
LD
TIA
LD
AMCC
GANGES
HUDSON
MEKONG
KHATANGA
RUBICON
AMCC
GANGES
HUDSON
MEKONG
KHATANGA
RUBICON
AMCC
S19252
AMCC
S19252
16
16
10G Clk
data
TIA
System Block Diagram with the S19252
S P E C I F I C AT I O N S
S19252
Enable Adaptive Post-Amplifier Offset Control
Compensates up to 24" of FR-4
M
I
MDIO/I2C
/SPI
MDIO/I2C
/SPI
16
D
P
L
A
N
E
16
AMCC
S19252
AMCC
S19252
ASIC
ASIC
16
16
Enable Adaptive ISI Mitigation
Figure 1. Mid-Plane Application Block Diagram
Enable Adaptive Post-Amplifier Offset Control
Enable Adaptive ISI Mitigation
Disable EDC / 10G Clock
MDIO/I2C
/SPI
ASIC
OR
FRAMER
OR
16
AMCC
S19252
XFP MODULE
16
FEC
Compensates up to 24" of FR-4
(Improves BER Performance and extends the reach of the standard XFP Module)
Figure 2. XFP Application Block Diagram
16
C
O
N
N
E
C
T
300 MSA MODULE
Laser
Laser
ASIC
OR
FRAMER
OR
Driver
16
AMCC
S19252
FEC
TIA
O
R
FEC Control
PD
No Post Amplifier Required
Figure 3. 300 MSA Application Block Diagram
For technical support, please call 1-800-840-6055 or 858-535-6517, or email support@amcc.com.
AMCC reserves the right to make changes to its products, its datasheets, or related documentation, without notice and warrants its products solely pursuant to its terms and
conditions of sale, only to substantially comply with the latest available datasheet. Please consult AMCC’s Term and Conditions of Sale for its warranties and other terms, conditions
and limitations. AMCC may discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify,
before placing orders, that the information is current. AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does
it convey any license under its patent rights nor the rights of others. AMCC reserves the right to ship devices of higher grade in place of those of lower grade.
AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR
OTHER CRITICAL APPLICATIONS.
AMCC is a registered trademark of Applied Micro Circuits Corporation. PowerPC and the PowerPC logo are registered trademarks of IBM Corporation. All other trademarks are the
property of their respective holders. Copyright © 2006 Applied Micro Circuits Corporation. All Rights Reserved.
S19252_PB2028_v1.01_20061031
6290 Sequence Dr.
San Diego, CA 92121
P 858 450 9333
F 858 450 9885
www.amcc.com
相关型号：
©2020 ICPDF网 联系我们和版权申明