S2024B-8 [AMCC]
Crossbar Switch, 32-Bit, ECL, PQFP196, HEAT SINK, NON CONDUCTIVE TIE-BAR, LDCC-196;
| 型号： | S2024B-8 |
| 厂家： | 
APPLIED MICRO CIRCUITS CORPORATION |
| 描述： | Crossbar Switch, 32-Bit, ECL, PQFP196, HEAT SINK, NON CONDUCTIVE TIE-BAR, LDCC-196 外围集成电路 |
| 文件： | 总15页 (文件大小：114K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
DEVICE SPECIFICATION
“CROSSBOW” 32 X 32 800 MBIT/S CROSSPOINT SWITCH
S2024
FEATURES
GENERAL DESCRIPTION
• Full broadcast switching capability
• 32 x 32 crosspoint structure, expandable to 64 x
64 with no external components
• ECL 10K data path and TTL I/O for configuration
controlprovidehighspeedwitheasyinterfacingto
slower-speed circuitry
• Up to 800 Mbit/s NRZ data rate in transparent
mode,400-Mbit/soperationinsynchronousmode
• 196-pin LDCC package
The S2024 “Crossbow” is a high-speed 32 x 32
crosspoint switch with full broadcast capability—any of
its 32 inputs can be connected independently to any or
all of its 32 outputs. In addition, the S2024 can be
expanded, through use of its expansion data inputs
(XDIN0–XDIN31), to a 64 x 64 crosspoint switch with
noexternalcomponents. Furtherexpansionispossible
with external addressing logic.
Two operating modes—synchronous (400 Mbit/s) and
transparent (800 Mbit/s)—provide maximum flexibility
across a range of applications. The 10K ECL logic data
path makes the part ideal for high-speed applications,
while the S2024’s TTL addressing and control simplify
interfacingtoslower-speedcircuitry. Theswitchcanbe
completely reconfigured in only 4 ns without disturbing
switch operations.
• Reconfigurable without disturbing operation
• Differential or single-ended clocking
APPLICATIONS
• Internet switches
• Digital video
• Digital demultiplexing
• Microwave or fiber-optic data distribution
• High-speed automatic test equipment
• Datacom or telecom switching
Figure 1. Functional Block Diagram
32
XDINØ–31
32
32
32
32 x 32
CROSSPOINT
32
DINØ–31
DOUTØ–31
MDCLK
MDCLKN
VBB1
SDCLK
SDCLKN
VBB2
192
CONFIGURATION
LATCH
CNFGSTB
192
5
32
5:32
DECODE
OUTADDØ–4
OAEN
32 X 6
REGISTER
FILE
EN
CLK
RST
CNFGCLK
INADDØ–5
RESET
DATA
6
1
June 15, 1999 / Revision B
“CROSSBOW” 32 X 32 800 MBIT/S CROSSPOINT SWITCH
S2024
Figure 2. Synchronous Mode
OPERATING MODES
t SUDI
tHDI
SYNCHRONOUS MODE
A
C
B
DINØ–31
In synchronous mode, two clock signals, MDCLK for
data input and SDCLK for data output, provide the latch
enable strobes to allow the input data and output data
to be stored in 32-bit latches. The S2024 is capable of
400-Mbit/s operation in this mode. The data is latched
on the falling edge of SDCLK and MDCLK.
MCMPWL
MCMPWH
MDCLK/N
SDCLK/N
t OVRL
Inputs MDCLK/MDCLKN and SDCLK/SDCLKN can be
used as true differentials or as single-ended clocking
signals. Onboard voltage reference outputs VBB1 and
VBB2 allow single-ended clocking capability when con-
figured as shown in Figure 8.
t SUXDI
t HXDI
A
B
XDINØ–31
DOUTØ–31
t SCKDO
A
B
TRANSPARENT MODE
In transparent, or asynchronous, mode, any data ap-
pearing at the input will be passed immediately through
to its designated output. Transparent transfer of data
through the latches takes place when both MDCLK and
SDCLK clock inputs are held high. In this mode the
S2024 is capable of up to a 800 Mbit/s NRZ data rate.
Figure 3. Transparent Mode
DIMPW
E
D
A
C
B
DINØ–31
tDIDO
B
tCFDO
RECONFIGURATION MODE
A
C
D
E
DOUTØ–31
CNFGSTB
XINØ–31
The S2024 can be selectively reconfigured one output
at a time, or any number of outputs can be reconfigured
simultaneously.Configurationdataisstoredin32registers,
one register for each output data pin. The 6-bit content
of each register selects the input data pin which is to be
connected to that output data pin. To connect an output
to a given input, the output to reconfigure is selected
usingOUTADD0–4andOAENtoenabletheappropriate
outputconfigurationregister. Withtheoutputconfigura-
tion register selected, the desired input pin connection
is provided on INADD0–5. The input pin selection on
INADD0–5 will be stored into the selected output con-
figuration register on the rising edge of CNFGCLK.
tXIDO
XIMPW
B
E
D
A
C
Figure 4. Reconfiguration Mode
t HOA
tSUOA
OUTADDØ–4
ADDRESS VALID
tSUOAE
When the switch is to be reconfigured, the S2024 mini-
mizes the time required through the use of an additional
configuration latch. While the switch is operational (and
prior to the time at which it must be reconfigured) a new
set of input addresses can be loaded into the register
file. Whenallregistershavebeenupdated, thecontents
oftheregistersareparallel-transferredtotheconfigura-
tion latch, when CNFGSTB goes high. This process
allows a switch reconfiguration in just 4 ns.
t HOAE
OAEN
INADDØ–5
CNFGCLK
tSUIA
t HIA
VALID
CCMPWH
CCMPWL
CSMPWH
t SUCFC
CNFGSTB
2
June 15, 1999 / Revision B
“CROSSBOW” 32 X 32 800 MBIT/S CROSSPOINT SWITCH
S2024
Table 1. Synchronous Mode Timing
Symbol
Description
S2024B-8
Min Max
Setup time of DIN0–31 before falling edge of MDCLK/N 1160
S2024B-6
Min
980
770
Max Units
tSUDI
ps
ps
tHDI
Hold time of DIN0–31 after falling edge of MDCLK/N
Overlap when MDCLK/N and SDCLK/N are high
1220
tOVRL
1860
1760
2770
ps
ps
ps
ps
Setup time of XDIN0–31 before falling edge of
SDCLK/N
tSUXDI
tHXDI
1160
1400
1040
680
Hold time of DIN0–31 after falling edge of SDCLK/N
Propagation delay from rising edge of SDCLK/N to
DOUT0–31
tSCKDO
3400
400
MCMPWH
MCMPWL
FMAX
Pulse width high of MDCLK/N or SDCLK/N
Pulse width low of MDCLK/N or SDCLK/N
Data Rate
630
500
790
660
ps
ps
300 Mbit/s
Table 2. Transparent Mode Timing
Symbol
Description
S2024B-8
S2024B-6
Min
Max
4180
3040
Min
Max Units
tDIDO
tXIDO
Propagation delay from DIN0–31 to DOUT0–31
Propagation delay from XIN0–31 to DOUT0–31
5125
3400
ps
ps
Propagation delay from rising edge of CNFGSTB to
DOUT0–31 valid
tCFDO
3760
4150
ps
DIMPW
XIMPW
FMAX
Pulse width high of DIN0–31
Pulse width high of XDIN0–31
Data Rate
860
910
1030
1090
ps
ps
800
600 Mbit/s
3
June 15, 1999 / Revision B
“CROSSBOW” 32 X 32 800 MBIT/S CROSSPOINT SWITCH
S2024
Table 3. Reconfiguration Timing (S2024B-8, S2024B-6)
Symbol
tSUOA
Description
Min
4360
560
Max Units
Setup time of OUTADD0–4 before rising edge of CNFGCLK
Hold time of OUTADD0–4 after rising edge of CNFGCLK
Setup time of OAEN before rising edge of CNFGCLK
Hold time of OAEN before rising edge of CNFGCLK
Setup time of INADD0–5 before rising edge of CNFGCLK
Hold time of INADD0–5 before rising edge of CNFGCLK
ps
ps
ps
ps
ps
ps
tHOA
tSUOAE
tHOAE
tSUIA
tHIA
3860
–140
2660
980
Setup time of CNFGCLK to CNFGSTB so that the rising edge of
CNFGSTB will start reconfiguration
tSUCFC
760
ps
Setup time of CNFGSTB falling edge before the rising edge of
CNFGCLK
tSUCFG
1960
CCMPWL
CCMPWH
CSMPWH
Pulse width low of CNFGCLK
Pulse width high of CNFGCLK
Pulse width low of CNFGSTB
4200
4200
4200
ps
ps
ps
4
June 15, 1999 / Revision B
“CROSSBOW” 32 X 32 800 MBIT/S CROSSPOINT SWITCH
S2024
Table 4. Pin Assignment and Descriptions
Pin Name
Level I/O
Pin # Description
DIN31
DIN30
DIN29
DIN28
DIN27
DIN26
DIN25
DIN24
DIN23
DIN22
DIN21
DIN20
DIN19
DIN18
DIN17
DIN16
DIN15
DIN14
DIN13
DIN12
DIN11
DIN10
DIN9
ECL
I
181
180
179
177
176
175
174
169
167
166
164
161
160
159
157
156
155
154
153
152
150
145
143
142
141
140
139
137
136
134
135
131
Intput data. Active High.
DIN8
DIN7
DIN6
DIN5
DIN4
DIN3
DIN2
DIN1
DIN0
OUTADD4
OUTADD3
OUTADD2
OUTADD1
OUTADD0
TTL
TTL
I
I
13
5
Output configuration register address. Used to select the output
configuration registers in the register file.
3
2
1
INADD5
INADD4
INADD3
INADD2
INADD1
INADD0
21
20
19
18
15
14
Input data addresses. Used to select the input data pin
connected to each output data pin. Stored into register file by
CNFGCLK. INADD5=1 is used to select the expansion data
inputs.
OAEN
TTL
ECL
I
I
190
Output address enable. When high, enables the selection of
appropriate output configuration register.
MDCLK
MDCLKN
66
65
Master latch clock inputs (input data). True differential inputs.
Can be used single-ended with VBB1 and VBB2.
5
June 15, 1999 / Revision B
“CROSSBOW” 32 X 32 800 MBIT/S CROSSPOINT SWITCH
S2024
Table 4. Pin Assignment and Descriptions (Continued)
Pin Name
Level I/O
Pin # Description
XDIN31
XDIN30
XDIN29
XDIN28
XDIN27
XDIN26
XDIN25
XDIN24
XDIN23
XDIN22
XDIN21
XDIN20
XDIN19
XDIN18
XDIN17
XDIN16
XDIN15
XDIN14
XDIN13
XDIN12
XDIN11
XDIN10
XDIN9
ECL
I
183
184
185
192
194
8
Expansion input data. Active High. These inputs are selected
by the most significant bit of the output configuration registers.
11
12
27
29
33
36
37
38
39
41
42
43
44
45
47
48
49
52
54
55
56
57
58
59
62
61
XDIN8
XDIN7
XDIN6
XDIN5
XDIN4
XDIN3
XDIN2
XDIN1
XDIN0
SDCLK
SDCLKN
ECL
I
70
69
Slave latch clock inputs (output data). True differential inputs.
Can be used single-ended with VBB1 and VBB2.
CNFGCLK
RESET
TTL
TTL
TTL
I
I
I
188
191
189
Address configuration clock. On rising edge, stores data into
output configuration register.
Chip reset. Active High. Asynchronously resets the register file.
CNFGSTB
Reconfiguration enable input. The contents of the register file
are parallel-loaded into the configuration latch when
CNFGSTB goes high, causing switch reconfiguration.
VBB1
VBB2
–
O
64
72
Reference threshold voltage outputs to allow provision for
single-ended capability for clock inputs.
6
June 15, 1999 / Revision B
“CROSSBOW” 32 X 32 800 MBIT/S CROSSPOINT SWITCH
S2024
Table 4. Pin Assignment and Descriptions (Continued)
Pin Name
Level I/O
Pin # Description
DOUT31
DOUT30
DOUT29
DOUT28
DOUT27
DOUT26
DOUT25
DOUT24
DOUT23
DOUT22
DOUT21
DOUT20
DOUT19
DOUT18
DOUT17
DOUT16
DOUT15
DOUT14
DOUT13
DOUT12
DOUT11
DOUT10
DOUT9
ECL
O
130
129
127
125
121
119
117
116
115
111
110
107
106
105
104
103
100
99
Output data. Active High.
96
94
93
92
91
DOUT8
90
DOUT7
89
DOUT6
87
DOUT5
86
DOUT4
85
DOUT3
83
DOUT2
80
DOUT1
79
DOUT0
78
ACTEST
–
O
6, 31
Used during device testing to determine AC performance of
chip. Signal is the output of a 9-stage ring oscillator followed by
two divide-by-2 circuits. Minimum acceptable output frequency is
32.6 MHz.
THDIODE
EGND
–
–
–
146, 147 Thermal diode connections
GND
7, 30, 32, ECL I/O Power Supply
68, 77,
101, 109,
112, 187
+5V
+5V
–
50, 98, TTL I/O Power supply
148, 196
7
June 15, 1999 / Revision B
“CROSSBOW” 32 X 32 800 MBIT/S CROSSPOINT SWITCH
S2024
Table 4. Pin Assignment and Descriptions (Continued)
Pin Name
Level I/O
Pin # Description
Core Power Supply
17, 24,
– 5.2V
– 5.2V
–
25, 26,
35, 63,
73, 75,
76, 84,
113, 122,
123, 124,
133, 162,
170, 171,
173, 182
GND
GND
–
4, 10, 16, Ground
22, 28,
34, 40,
46, 51,
53, 60,
67, 71,
74, 81,
88, 95,
97, 102,
108, 114,
120, 126,
132, 138,
144, 149,
151, 158,
165, 168,
172, 178,
186, 193,
195
NC
–
–
9, 23, 82, No Connection
118, 128,
163
8
June 15, 1999 / Revision B
“CROSSBOW” 32 X 32 800 MBIT/S CROSSPOINT SWITCH
S2024
Figure 5. S2024 Pinout
1
2
OUTADD0
THDIODE
THDIODE
DIN10
GND
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
OUTADD1
OUTADD2
GND
3
4
5
OUTADD3
ACTEST
EGND
XDIN26
NC
GND
DIN9
6
DIN8
7
DIN7
8
DIN6
9
DIN5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
GND
XDIN25
XDIN24
OUTADD4
INADD0
INADD1
GND
DIN4
DIN3
DIN1
DIN2
-5.2V
GND
DIN0
-5.2V
INADD2
INADD3
INADD4
INADD5
GND
DOUT31
DOUT30
NC
DOUT29
GND
S2024 Pinout
Top View
196-pin LDCC
NC
DOUT28
-5.2V
-5.2V
-5.2V
-5.2V
-5.2V
-5.2V
XDIN23
DOUT27
GND
GND
XDIN22
EGND
DOUT26
NC
ACTEST
EGND
DOUT25
DOUT24
DOUT23
XDIN21
GND
GND
-5.2V
-5.2V
XDIN20
XDIN19
XDIN18
XDIN17
GND
EGND
DOUT22
DOUT21
EGND
GND
XDIN16
XDIN15
XDIN14
XDIN13
XDIN12
GND
XDIN11
XDIN10
XDIN9
DOUT20
DOUT19
DOUT18
DOUT17
DOUT16
GND
EGND
DOUT15
DOUT14
9
June 15, 1999 / Revision B
“CROSSBOW” 32 X 32 800 MBIT/S CROSSPOINT SWITCH
S2024
Figure 6. 196 LDCC Package
1.250 ±.015.
.420 ± .010
148
147
196
1
.105 ±.010
1.350 ±.010
99
98
49
50
.290 min
.055 ± .010
COPLANAR TO .004
.045 ± .005
.008 ± .002
.025 ± .002
1.550
± .015
Non-conductive Tie-bar*
TOP VIEW
All dimensions nominal in inches.
*Trim non-conductive tie-bar prior to board attachment.
Table 5. Thermal Management
Symbol
Θjc
Description
Airflow
Value
2.3
Units
oC/W
oC/W
Thermal resistance from junction to case
Thermal resistance from junction to ambient
Θjc
Θjc
Still air
25.6
Thermal resistance from junction to ambient
with heatsink
400
LFPM
4.8
oC/W
Note: S2024 requires an AMCC heatsink 45-10 with an airflow of 400 LFPM for operation over commercial temperatures.
10
June 15, 1999 / Revision B
“CROSSBOW” 32 X 32 800 MBIT/S CROSSPOINT SWITCH
S2024
Figure 7. AMCC Heatsink 45-10
Figure 8. Differential to Single-Ended Conversion
CLOCK
INPUT
RT
VT
MDCLKN
VBB1
VBB
GEN.
RT = Termination Resistor
VT = Termination Voltage
11
June 15, 1999 / Revision B
“CROSSBOW” 32 X 32 800 MBIT/S CROSSPOINT SWITCH
S2024
Table 6. Absolute Maximum Ratings
Parameter
Min
Typ
Max Units
ECL Supply Voltage VEE (VCC = 0)
ECL Input Voltage (VCC = 0)
–8.0 V/DC
GND
–3.0
V
ECL Output Source Current (continuous)
TTL Supply Voltage VCC (VEE = 0)
TTL Input Voltage (VEE = 0)
–50 mA/DC
7.0
5.5
V
V
–55
(ambient)
+125
(case)
Operating Temperature
oC
Operating Junction Temperature
Storage Temperature
+150
+150
oC
oC
–65
Table 7. Recommended Operating Conditions
Parameter
Min
Typ
Max Units
ECL (10K) Supply Voltage (VEE) VCC = 0
ECL Input Signal Rise/Fall Time
TTL Supply Voltage VCC
–4.94 –5.2 –5.46
V
ns
V
1.0
5.0
3.0
4.75
5.25
oC
0
70
Operating Temperature
(ambient)
(ambient)
Junction Temperature
130
194
oC
mA
mA
W
ICC
IEE
1589
0.58
POEF
12
June 15, 1999 / Revision B
“CROSSBOW” 32 X 32 800 MBIT/S CROSSPOINT SWITCH
S2024
Table 8. ECL 10K Input/Output DC Characteristics VEE = –5.2 V1
Tambient
25 oC
–730
–680
–980
–1105
–1475
–1620
–1980
–2000
30
0 oC
–770
–720
–1000
–1145
–1490
–1625
–1980
–2000
30
70 oC
–650
–600
–920
–1045
–1450
–1585
–1980
–2000
30
Units
mV
mV
mV
mV
mV
mV
mV
mV
µA
VOHmax
3
VIHmax
VOHmin
3
VIHmin
3
VILmax
VOLmax
VOLmin
3
VILmin
IIH2MAX
IIH2MAX
µA
–.5
–.5
–.5
Table 9. TTL Input/Output DC Characteristics
C
Symbol
Parameter
Test DC Conditions
COMM 0° /+70°
Units
Min
2.0
Typ 2 Max
Guaranteed input HIGH voltage for all
inputs
3
VIH
Input HIGH voltage
Input LOW voltage
V
V
Guaranteed input LOW voltage for all
inputs
3
VIL
0.8
VIK
IIH
Input clamp diode voltage VCC = Min, IIN = –18mA
Input HIGH current VCC = Max, VIN = 2.7V
Input HIGH current at MAX VCC = Max, VIN = 5.5V
Input LOW current VCC = Max, vIN = 0.5V
–0.8
–1.2
50
V
µA
mA
mA
II
1.0
IIL
–0.4
Notes
1. Data measured with VEE = –5.2 ± .1V assuming a +50°C rise between ambient (Ta) and junction temperature (Tj) for 0°C,
+25°C, and +70°C. These conditions will be met with an airflow of 400 for commercial environment.
2. Typical limits are at 25°C, VCC = 5.0V.
3a.These input levels provide zero noise immunity and should only be tested in a static, noise-free environment.
3b.Use extreme care in defining input levels for dynamic testing. Many ouputs may be charged at once, so there will be significant noise at the
device pins and they may not actually reach VIL or VIH until the noise has settled. AMCC recommends using VIL ≤ 0.4V and VIH ≥ 2.4V for
dynamic TTL testing and VILMIN and VIHMAX for ECL testing.
13
June 15, 1999 / Revision B
“CROSSBOW” 32 X 32 800 MBIT/S CROSSPOINT SWITCH
S2024
Figure 9. S2024 Expansion Diagram
EXPANDING THE S2024 TO A 64 X 64
CROSSPOINT SWITCH
Four S2024s can be easily connected to form a 64 x 64
crosspoint switch. In order to accomplish this, the
switches must be configured so that any input can be
multiplexed to any output. The accompanying figure
provides an example of a 64 x 64 switch, making use of
the S2024’s expansion data inputs.
Primary 1
DIN
Primary 2
DIN
DIN32–63
DOUT
DOUT
This arrangement allows all outputs to select input data
from any bit of the 64-bit data bus. The two secondary
S2024s receive data from the two primaries by means
of the expansion data inputs. The expansion inputs are
used when the switching operation has been realized
by the previous switches and only a flow through is
needed.
XDIN
Secondary 3
XDIN
Secondary 4
DINØ–31
DIN
DIN
DOUT
DOUT
DOUTØ–31
DOUT32–63
Crosspoint 1 switches D32–D63 to Crosspoint 3.
Crosspoint 2 switches D32–D63 to Crosspoint 4.
Crosspoint 3 switches D0–D31 to O0–O31 and/or re-
produces the outputs of Crosspoint 1 through the
expansion inputs.
Crosspoint 4 switches D0–D31 to O32–O63 and/or
reproduces the outputs of Crosspoint 2 through the
expansion inputs.
14
June 15, 1999 / Revision B
“CROSSBOW” 32 X 32 800 MBIT/S CROSSPOINT SWITCH
S2024
Ordering Information
PREFIX
DEVICE
PACKAGE
SPEED GRADE
6 – 600 Mbit/s
8 – 800 Mbit/s
S – Integrated Circuit
2024
B – 196 LDCC
with straight leads
C – 196 LDCC
leadformed
with heatsink
unattached
X
XXXX
X
-
XX
Prefix
Device
Package Speed grade
Applied Micro Circuits Corporation • 6290 Sequence Dr., San Diego, CA 92121
Phone: (619) 450-9333 • (800)755-2622 • Fax: (619) 450-9885
http://www.amcc.com
AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and
advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied
on is current.
AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it
convey any license under its patent rights nor the rights of others.
AMCC reserves the right to ship devices of higher grade in place of those of lower grade.
AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR
USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
AMCC is a registered trademark of Applied Micro Circuits Corporation.
Copyright ® 1999 Applied Micro Circuits Corporation
15
June 15, 1999 / Revision B
相关型号：
S2025L51
Silicon Controlled Rectifier, 25A I(T)RMS, 200V V(DRM), 200V V(RRM), 1 Element, TO-220AB, TO-220, 3 PIN
TECCOR
S2025L52
Silicon Controlled Rectifier, 25A I(T)RMS, 200V V(DRM), 200V V(RRM), 1 Element, TO-220AB, TO-220, 3 PIN
TECCOR
S2025L53
Silicon Controlled Rectifier, 25A I(T)RMS, 200V V(DRM), 200V V(RRM), 1 Element, TO-220AB, TO-220, 3 PIN
TECCOR
©2020 ICPDF网 联系我们和版权申明