S3016AH0 [AMCC]
ATM Network Interface, 1-Func, PDSO52, PQFP, TEP, 52 PIN;
| 型号： | S3016AH0 |
| 厂家： | 
APPLIED MICRO CIRCUITS CORPORATION |
| 描述： | ATM Network Interface, 1-Func, PDSO52, PQFP, TEP, 52 PIN ATM 异步传输模式 电信 光电二极管 电信集成电路 |
| 文件： | 总23页 (文件大小：148K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
DEVICE SPECIFICATION
S3015/S3016
E4/STM-1/OC-3 ATM INTERFACE CIRCUITS
FEATURES
GENERAL DESCRIPTION
• Complies with ANSI, Bellcore, and ITU-T
specifications
• On-chip high-frequency PLL for clock
generation and clock recovery
• On-chip analog circuitry for transformer driver
and equalization
The S3015 transmitter and S3016 receiver derive high
speed timing signals for SONET/SDH or PDH–based
equipment. These circuits are implemented using
AMCC’s proven Phase Locked Loop (PLL) technology.
Figures 1a and 1b show typical network applications.
The S3015 and S3016 each have an on-chip VCO
whichcanbesynchronizeddirectlytotheincomingdata
stream. The chipset can be used with a 19.44 MHz
referenceclockwhenoperatedintheSONET/SDHOC-
3 mode. In E4 mode the chipset can be operated with a
17.408 MHz reference clock in support of existing
system clocking schemes. On-chip coded-mark-inver-
sion (CMI) encoding and decoding is provided for
139.264 Mbit/s and 155.52 Mbit/s interfaces.
• Supports 139.264 Mbit/s (E4) and 155.52 Mbit/s
(OC-3) transmission rates
• Supports 139.264 Mbit/s and 155.52 Mbit/s
Coded Mark Inversion (CMI) interfaces
• Reference frequencies of 19.44 (OC-3) or
17.408 MHz (E4)
• Interface to both PECL and TTL logic
• Lock detect on clock recovery device
• Low jitter PECL interface
• 1.6W total typ power
• +5V only power supply
• Small 52 PQFP TEP package
• Supports both electrical and optical interfaces
The low jitter PECL interface guarantees compliance
with the bit-error rate requirements of the Bellcore,
ANSI, and ITU-T standards. The S3015/S3016 chipset
is packaged in a .65mm pitch, compact 52-pin PQFP,
offering designers a small package outline.
APPLICATIONS
The S3015 and S3016 provide the major components
on-chip for a coaxial cable interface, including analog
transformer driver circuitry and equalization interface
circuitry.
•
•
•
•
•
•
•
ATM over SONET
OC-3/STM-1 or E4-based transmission systems
OC-3/STM-1 or E4 modules
OC-3/STM-1 or E4 test equipment
Section repeaters
Add drop multiplexors
Broadband cross-connects
• Fiber optic terminators
• Fiber optic test equipment
Figure 1a. Electrical Interface
COAX
139/155 Mb/s NRZ
139/155 Mb/s CMI
139/155 Mb/s CMI
S3015
S3016
E4/STM-1/OC-3
OVERHEAD
PROCESSOR
XFMR
XFMR
139/155 Mb/s NRZ
17.408/19.44 Mhz
COAX
OSC
Figure 1b. Optical Interface
155 Mb/s NRZ
E4/STM-1/OC-3
OTX
OVERHEAD
PROCESSOR
155 Mb/s NRZ
155 MHz
155 Mb/s NRZ
ORX
S3015
S3016
OSC
1
S3015/S3016
E4/STM-1/OC-3 ATM INTERFACE CIRCUITS
handles the conversion from electrical to optical and
back with no overhead. It is responsible for transmitting
the electrical signals in optical form over the physical
media. The section layer handles the transport of the
framed electrical signals across the optical cable from
one end to the next. Key functions of this layer are
framing, scrambling, and error monitoring. The line
layer is responsible for the reliable transmission of the
path layer information stream carrying voice, data, and
video signals. Its main functions are synchronization,
multiplexing, and reliable transport. The path layer is
responsible for the actual transport of services at the
appropriate signaling rates.
SONET/SDH OVERVIEW
Synchronous Optical Network (SONET) is a standard
for connecting one fiber system to another at the optical
level. SONET, together with the Synchronous Digital
Hierarchy (SDH) administered by the ITU-T, form a
single international standard for fiber interconnect be-
tweentelephonenetworksofdifferentcountries.SONET
is capable of accommodating a variety of transmission
rates and applications.
The SONET standard is a layered protocol with four
separate layers defined. These are:
• Photonic
• Section
• Line
Data Rates and Signal Hierarchy
• Path
Table 1 contains the data rates and signal designations
of the SONET hierarchy. The lowest level is the basic
SONET signal referred to as the synchronous transport
signal level-1 (STS-1). An STS-N signal is made up of
N byte-interleaved STS-1 signals. The optical counter-
part of each STS-N signal is an optical carrier level-N
signal(OC-N). TheS3015/S3016chipsetsupportsOC-
3 rates (155.52 Mbit/s).
Figure 2 shows the layers and their functions. Each of
thelayershasoverheadbandwidthdedicatedtoadmin-
istration and maintenance. The photonic layer simply
Table 1. SONET Signal Hierarchy
Elec.
STS-1
ITU-T Optical Data Rate (Mbit/s)
Frame and Byte Boundary Detection
OC-1
51.84
The SONET/SDH fundamental frame format for STS-3
consists of nine transport overhead bytes followed by
Synchronous Payload Envelope (SPE) bytes. This pat-
tern of 9 overhead and 261 SPE bytes is repeated
nine times in each frame. Frame and byte boundaries
are detected using the A1 and A2 bytes found in the
transport overhead. (See Figure 3.)
STS-3
STM-1
STM-4
OC-3
155.52
STS-12
STS-24
STS-48
OC-12
OC-24
OC-48
622.08
1244.16
2488.32
STM-16
For more details on SONET operations, refer to the
ANSI SONET standard document.
Figure 3. SONET Structure
Functions
Figure 3. STS-3 Frame Format
Payload to
SPE mapping
Path layer
Path layer
9 x 261 =
2349 bytes
9
Rows
Maintenance,
protection,
switching
Line layer
Line layer
Scrambling,
framing
Section layer
Section layer
Transport Overhead
9 Columns
Synchronous
Optical
transmission
Photonic layer
Photonic layer
Payload
Envelope
Fiber Cable
End Equipment
End Equipment
125µsec
2
E4/STM-1/OC-3 ATM INTERFACE CIRCUITS
S3015/S3016 OVERVIEW
S3015/S3016
S3015 TRANSMITTER
FUNCTIONAL DESCRIPTION
The S3015 transmitter and the S3016 receiver can be
used to implement the front end of STS-3, OC-3 or E4
equipment. The block diagrams in Figures 4 and 10
show the basic operation of both chips.
The S3015 transmitter chip performs the last stage of
digital processing of a transmit SONET STS-3 or ITU-
T E4 bit serial data stream. A Coded Mark Inversion
(CMI) encoder can be enabled for encoding STS-3
electrical and E4 signals.
Whenserialdataispresentattheinputofthetransmitter,
theS3015VCOsynchronizesdirectlytotheincomingdata,
which is retimed for the purpose of optional CMI encod-
ing. In the absence of incoming serial data, the S3015
operates as a clock synthesizer. In this mode, a crystal
oscillator is connected to the TTL reference input and
synthesized up to the 155 MHz output frequency. The
S3016 receiver performs clock recovery by synchroniz-
ingitson-chipVCOdirectlytotheincomingdatastream.
Clock Recovery
If serial data is present on the SERDATIP/N inputs, the
clock is recovered from the serial data stream at 139.264
MHz or 155.52 MHz and synthesized to 278.528 MHz
or 311.04 MHz to CMI encode the incoming data.
Optical and Electrical Interfaces
The S3015 provides a PECL output for an optical
interface and two transformer driver outputs for an
electrical interface. One of these drivers is a monitor
output. The S3016 provides a PECL input for an optical
interface and an analog input for an electrical interface.
The digital data outputs (SERDATOP/N) are the PECL
outputs for an optical interface and are to be connected
to an electrical to optical converter, as shown in Figure
18. This data is also routed to two on-chip transformer
drivers and sent out on XFRMDRVA and XFRMDRVB
to drive the transformers of the electrical interface, as
showninFigure20.Theseoutputsareshutoffwhenthe
reset is active, XFRMEN is active, or when the chip is
in NRZ mode and the data inputs are in the logic zero
state. The electrical characteristics for the transformer
drivers are shown in Table 5.
When the chipset is used in an electrical interface, the
PECL output of the transmitter can be connected to the
PECL input of the receiver to implement a diagnostic
loopback mode for test. When the chipset is used in an
optical interface, a transformer driver output of the
transmitter can be connected to the analog input of the
receiver to implement the loopback mode.
Figure 4. S3015 OC3/STM-1/E4 Transmitter Functional Block Diagram
CAP1
LOOP
VCO
FILTER
CAP2
REFCKIN
REFCKOUT
2
TSTCLKEN
SERCLKOP/N
CLOCK
C
M
I
DIVIDER
CMISEL
DLCV
TRANSFORMER
DRIVERS
XFRMDRVA
RSTB
XFRMDRVB
PHASE DETECTOR
SERDATOP/N
2
SERDATIP/N
XFRMEN
SERDATEN
3
S3015/S3016
E4/STM-1/OC-3 ATM INTERFACE CIRCUITS
CMI Encoding
Figure 5. CMI Encoded Data
Coded Mark Inversion format (CMI) ensures at least
one data transition per 1.5 bit periods, thus aiding
the clock recovery process. Zeros are represented
by a Low state for one half a bit period, followed by
a High state for the rest of that bit period. Ones are
represented by a steady Low or High state for a full
bit period. The state of the ones bit period alternates
at each occurrence of a one. Figure 5 shows an
example of CMI-encoded data. The STS-3 electrical
interface and the E4 interface are specified to have
CMI-encoded data.
Figure 6. Jitter Generation Specifications
Compliant to G.823 and G.825
The CMI encoder on the S3015 accepts serial data
from SERDATIP/N at 139.264 or 155.52 Mb/s. The
data is then encoded into CMI format, and the result
is shifted out with transitions at twice the basic data
rate. The CMISEL input controls whether the CMI en-
coder is in the data path. A CMI code violation can be
inserted for diagnostic purposes by activating the
DLCV input. The DLCV input is sampled on every
cycle of the serial clock to allow a single or multiple
line code violations to be inserted. This violation is
either an inverted zero code or an inversion of the
alternating ones logic level, depending on the state of
the data. Subsequent one codes take into account
the induced violation to avoid error multiplication.
A1
A2
f1
f2
f3
f1(Hz)
—
A2
f2(KHz) f3(MHz) A1
.01(1)
.15(2)
.075(2)
—
65
10
—
.01(1)
1.5(2)
1.5(2)
OC-3
STM-1 500
1.3
3.5
E4
200
1. UI rms
2. UI p–p
Jitter Generation
Jitter Generation is defined as the amount of jitter at the
OC-3 or E-4 output of equipment. Jitter generation for
OC-3 shall not exceed 0.01 UI rms when measured
using a highpass filter with a 12 kHz cutoff frequency.
Figure 7. S3015 Maximum Allowable Input Jitter
A1
ForSTM-1andE4, thejittergeneratedshallnotexceed
the specifications shown in Figure 6.
Slope = +20 dB/decade
In order to meet the SONET, STM-1 E4 jitter specifica-
tionsasshowninFigure6,theSERDATIP/Nserialdata
input must meet the jitter characteristics as shown in
Figure 7.
A2
500Hz
OC-3
f2
225 KHz 1.3 MHz
f2(KHz)
—
A1
A2
.005(1) .005(1)
1.45(2) .10(2)
1.45(2) .025(2)
STM-1 65
E4
10
1. UI rms
2. UI p–p
4
E4/STM-1/OC-3 ATM INTERFACE CIRCUITS
S3015/S3016
Figure 8. Mask of a pulse corresponding to a binary 0 Compliant to G.703
T= 7.18 ns for E4
6.43 ns for 155 CMI
Figure 9. Mask of a pulse corresponding to a binary 1 Compliant to G.703
t= 1.35 ns for E4
1.20 ns for 155 CMI
T= 7.18 ns for E4
6.43 ns for 155 CMI
Notes:
1. The maximum “steady state” amplitude should not exceed the 0.55 V limit. Overshoots and other transients are
permitted to fall into the dotted area, bounded by the amplitude levels 0.55 V and 0.6 V, provided that they do not
exceed the steady state level by more than 0.05 V. The possibility of relaxing the amount by which the overshoot may
exceed the steady state level is under study.
2. For the purpose of these masks, the rise time and decay time should be measured between -0.4 V and 0.4 V, and
should not exceed 2 ns.
3. The inverse pulse in Figure 9 will have the same characteristics, noting that the timing tolerances at the zero level of the
negative and positive transitions are ±0.1 ns and ±0.5 ns respectively.
5
S3015/S3016
E4/STM-1/OC-3 ATM INTERFACE CIRCUITS
trolled Oscillator (VCO), which generates the recov-
ered clock. Frequency stability without incoming data
is guaranteed by an alternate reference input
(REFCKIN) to which the PLL locks when data is lost.
S3016 RECEIVER FUNCTIONAL
DESCRIPTION
The S3016 receiver provides the first stage of digital
processing of a receive SONET STS-3 or ITU-T E4 serial
bit stream. A Coded Mark Inversion (CMI) decoder can
be enabled for decoding STS-3 electrical and E4 signals.
When the test clock enable (TSTCLKEN) input is set
high, the clock recovery block is disabled. The refer-
ence clock (REFCKIN) is used as the bit rate clock
input in place of the recovered clock. This feature is
used for functional testing of the device.
Clock recovery is performed on the incoming
scrambled NRZ or CMI–coded data stream. A reference
clock is required for phase locked loop start-up and
proper operation under loss of signal conditions. An
integral prescaler and phase locked loop circuit is used
to multiply this reference frequency to the nominal bit rate.
The loop filter transfer function is optimized to enable
the PLL to track the jitter, yet tolerate the minimum
transition density expected in a received SONET or
E4 data signal. This transfer function yields a typical
capture time of 16 µs for random incoming NRZ data.
Clock Recovery
The total loop dynamics of the clock recovery PLL yield
a jitter tolerance which exceeds the minimum tolerance
proposed for OC-3/STM-1/E4 equipment by the Bellcore
and ITU-T documents, shown in Figure 13.
The Clock Recovery function, as shown in the block
diagram in Figure 10, generates a clock that is fre-
quency matched to the incoming data baud rate at
the SERDATIP/N differential inputs. The clock is
phase aligned by a PLL so that it samples the data
in the center of the data eye pattern.
Optical and Electrical Interfaces
The digital data inputs (SERDATIP/N) are the PECL
inputs from an optical to electrical converter, as shown
in Figure 16. The data input for the coaxial interface is
ANDATIN, which is the serial data input from the equal-
izer circuit and should be connected as shown in Figure
17. The EQUALSEL input is used to select either
SERDATIP/N or ANDATIN.
The phase relationship between the edge transitions
of the data and those of the generated clock are
compared by a phase/frequency discriminator. Output
pulses from the discriminator indicate the required
direction of phase corrections. These pulses are
smoothed by an integral loop filter. The output of the
loop filter controls the frequency of the Voltage Con-
Figure 10. S3016 OC-3/STM-1/E4 Receiver Functional Block Diagram
CAP1
LOOP
VCO
FILTER
CAP2
REFCKIN
TSTCLKEN
CMISEL
REFCKOUT
2
SERCLKOP/N
LCV
CLOCK
DIVIDER
C
M
I
LOCK
LOSOUT
DETECTOR
RSTB
2
BUFINA, BUFINB
BUFOUT
PHASE DETECTOR
2
SERDATOP/N
LOSOPT
2:1
MUX
LOSIN
LOSREF
2
SERDATIP/N
2:1
MUX
ANDATIN
EQUALSEL
6
E4/STM-1/OC-3 ATM INTERFACE CIRCUITS
S3015/S3016
CMI Decoding
Serial Clock Output to Data Output Timing
The CMI decoder block on the S3016 accepts serial
data from the SERDATIP/N input at the rate of 139.264
or 155.52 Mb/s. The incoming CMI data, which has
transitions that represent this data rate (the clock asso-
ciated with this data would be running at twice this rate),
is then decoded from CMI to NRZ format.
The serial data is clocked out on the falling edge of
SERCLKOP. (See Figure 12.) This timing is valid in
both NRZ and CMI modes.
Input Jitter Tolerance
Input jitter tolerance is defined as the peak to peak
amplitude of sinusoidal jitter applied on the input signal
that causes an equivalent 1 dB optical/electrical power
penalty. OC-3 and E-4 input jitter tolerance require-
ments are shown in Figure 13.
Loss of Signal
The clock recovery circuit monitors the incoming data
stream for loss of signal. If the incoming encoded data
streamhashadnotransitionscontinuouslyfor96to224
recovered clock cycles, loss of signal is declared and
the PLL will switch from locking onto the incoming data
tolockingontothereferenceclockpertherequirements
of G.775. Alternatively, the loss-of signal (LOSIN) input
can force a loss-of-signal condition. This signal is com-
pared internally against the LOSREF input reference
voltage. This input can be set to meet the conditions
showninFigure11. Ifthezerotopeaksignalleveldrops
below the LOSREF/20 voltage level for more than 96 to
224 bit intervals, a loss of signal condition will be
indicated on the LOSOUT pin and the PLL will change
itsreferencefromtheserialdatastreamtothereference
clock. When the peak input voltage is greater than
LOSREF/10, the loss of signal condition will be
deasserted and the PLL will recover the clock from the
serial data inputs.
The S3016 PLL complies with the minimum jitter toler-
ance for clock recovery proposed for SONET/SDH
equipment defined by the Bellcore TA-NWT-000253
standard when used as shown in Figure 13. The S3016
PLL also complies with the minimum jitter tolerance for
clock recovery as defined in the ITU-T E4 specification
when used as shown in Figure 17.
Figure 12. S3016 Clock to Data Timing
SERCLKOP
SERDATOP/N
tP
SER
InNRZmode, alogiclowlevelontheLOSOPTinputwill
cause the PLL to change its reference to the reference
clock. This pin should be driven by a PECL compatible
level signal detect signal from the fiber optic receiver.
Figure 13. Clock Recovery Jitter Tolerance
Compliant to G.823 and G.825
Figure 11. Criteria for determination of transition
conditions. Compliant to G.775.
nominal value
maximum
Sinusoidal
Input Jitter
Amplitude
(UI p-p)
A2
A3
A4
cable loss
3 dB
“transition condition”
must be declared
17
35
Tolerance range
f9
f0 f1
f2 f3
f4
f4
“no transition condition” or “transition
condition” may be declared
f9
(Hz)
f2
A3 A4
f0
f1
f3
A2
“no transition condition”
must be declared
(KHz)
(Hz) (Hz)
(KHz) (MHz)
Level below Nominal
OC-3
10
6.5
6.5
1.5 .15
1.5 0.15
1.5 0.075
30 300
65
65
65
—
15
391
391
The signal level 17 is (maximum cable loss +3)
dB below nominal.
STM-1 (Optical) 0.125
STM-1 (Electrical) 0.125
19.3 500
19.3 500
1.3
1.3
3.25
The signal level 35 is greater than the maximum
expected cross-talk level.
E4
TBD
0.5
1.5 0.075
TBD 200
65
1.3
15
Note:
1. Only tested to 20 due to test equipment limitation.
7
S3015/S3016
E4/STM-1/OC-3 ATM INTERFACE CIRCUITS
Test Mode
Reference Clock Input
The Test Clock Enable (TSTCLKEN) inputs on both
chips provide access to the PLL.
The reference clock input seen in Figure 10 provides
backup reference clock signals to the clock recovery
block when the clock recovery block detects a loss of
signal condition. It contains a counter that divides the
clock output from the clock recovery block down to the
same frequency as the reference clock REFCKIN.
The PLL-generated clock source on both the S3015
and S3016 can be bypassed by setting TSTCLKEN
high.Inthismode,anexternallygeneratedclocksource
must be applied at the REFCLKIN input.
OTHER OPERATING MODES
Clock Synthesis
Diagnostic Loopback
In the Clock Synthesis mode, the S3015 synthesizes
the E4 (139.264 MHz) clock from a 17.408 MHz crystal
oscillator or the STS-3/STM-1 (155.52 MHz) clock from
a 19.44 MHz crystal oscillator. In this mode, a crystal
oscillator is connected to the TTL reference input and
synthesized up to the output frequency.
When the chipset is used in an electrical interface, the
serial data output (SERDATOP/N) of the transmitter
can be connected the serial data input (SERDATIP/N)
ofthereceivertoimplementaloopbacktestfordiagnos-
tic purposes, as shown in Figure 14. In this mode,
SERDATEN on the transmitter and EQUALSEL on the
receiver are both held low. LOSOPT on the receiver is
held high or not connected.
The S3015 PLL complies with jitter generation for clock
synthesis proposed for SONET/SDH equipment de-
fined by the Bellcore TA-NWT-000253 standard, when
usedwithacrystalreferencesourceasdefinedinTable4.
Figure 14. Loopback Diagram
S3015
S3016
Control
CLK
S3016
S3015
CLK
Control
8
E4/STM-1/OC-3 ATM INTERFACE CIRCUITS
S3015/S3016
S3015 Pin Assignment and Descriptions
Pin Name
Level I/O
Pin # Description
REFCKIN
TTL
I
10
Reference clock. Input used as the reference for the internal bit
clock frequency synthesizer.
TSTCLKEN
TTL
I
35
Test clock enable signal, active high, that enables the reference
clock to be used in place of the VCO for testing. Allows a means
of testing the functions of the chip without the use of the PLL.
Set low for normal operation.
DLCV
Single--
ended
PECL
I
I
I
I
34
33
24
Diagnostic line code violation, set high to force a CMI line code
violation. DLCV is only active in CMI mode. DLCV is sampled on
the falling edge of SERCLKOP.
CMISEL
RSTB
TTL
TTL
–
CMI select, used to select CMI or NRZ. A logic high selects CMI
mode. A logic low selects NRZ mode. Both the SERDATOP/N
and the XFRMDRV outputs are controlled by CMISEL.
Reset input for the device, active low. Initializes the device to a
known state. When active, all data outputs are held low. Clock
outputs are still active during reset.
CAP1
CAP2
1
52
The loop filter capacitor is connected to these pins. The
capacitor value should be 0.1µf ±10% tolerance, X7R dielectric.
50 V is recommended (16 V is acceptable).
SERDATIP
SERDATIN
Diff.
I
I
45
46
Serial data in. The clock is recovered from transitions on these
inputs. No phase relationship to REFCKIN is required.
PECL
XFRMEN
TTL
TTL
23
Transformer driver enable used to enable the transformer driver
outputs. A logic low enables XFRMDRVA and XFRMDRVB. A
logic high turns off the transformer driver outputs.
SERDATEN
I
5
Serial data enable, used to enable the serial data outputs. A
logic low enables SERDATOP/N. A logic high turns off the serial
data outputs.
SERDATOP
SERDATON
Diff.
PECL
O
7
6
Serial data out signal. In NRZ mode, this signal is the delayed
version of the incoming data stream (SERDATIP/N) updated on
the falling edge of Serial Clock Out (SERCLKOP). In CMI mode,
this signal is the CMI-encoded version of SERDATIP/N.
SERCLKOP
SERCLKON
Diff.
O
O
29
30
Serial clock out signal that is a 155 MHz clock that is phase-
aligned with Serial Data Out (SERDATO) in NRZ mode. In CMI
mode, SERCLKOP/N cannot be used.
PECL
REFCKOUT
TTL
11
Single-ended TTL reference clock output.
9
S3015/S3016
E4/STM-1/OC-3 ATM INTERFACE CIRCUITS
S3015 Pin Assignment and Descriptions (Continued)
Pin Name
Level I/O
Pin # Description
XFRMDRVA
Analog
Analog
O
O
20
21
Transformer driver A, used to drive the transformer of the
electrical interface. For E4 operation, this output should be
connected per Figure 19 to provide the correct G.703 compatible
output levels from the transformer when connected to the
specified 75Ω cable.
XFRMDRVB
Transformer driver B, used to drive the monitor transformer of
the electrical interface. This output should be connected per
Figure 20 to provide the correct output levels from the
transformer when connected to the specified 75Ω cable.
AVEE
0V
–
–
–
2, 22, 39, Analog 0V
42, 43
AVCC
+5V
3, 19, 38, Analog +5V
40, 48
ECLVCC
4, 9, 12,
15, 25,
28, 31,37
ECLVEE
TTLGND
TTLVCC
NC
0V
GND
+5V
–
–
–
–
–
8, 32, 36 Digital 0V
13, 27
14, 26
TTL Power Supply (+5V if TTL)
No Connection
16, 17,
18, 41,
44, 47,
49, 50,
51
10
E4/STM-1/OC-3 ATM INTERFACE CIRCUITS
S3015/S3016
S3016 Pin Assignment and Descriptions
Pin Name
Level I/O
Pin # Description
BUFINA
BUFINB
Analog
Analog
TTL
I
I
22
23
Buffer inputs to the equalizer network buffer circuit. This circuit
provides a high impedance load to the transformer termination
network in order to comply with the required return loss
specifications. These pins should be connected as shown in
Figure 17. These pins are electrically equivalent.
ANDATIN
16
Analog serial data input from the equalizer circuit. It must be
connected to the output of the equalizer circuit as shown in
Figure 17. When the S3016 is used with a fiber optic receiver,
this input should be left open and the SERDATIP/N inputs
should be used.
EQUALSEL
REFCKIN
I
I
I
I
I
I
33
10
Equalization select used to select SERDATIP/N or ANDATIN. A
logic high selects ANDATIN.
Single-
ended
TTL
Input used as the reference for the VCO when the input data
signal is lost.
SERDATIP
SERDATIN
Diff.
PECL
45
46
Serial data in. Clock is recovered from transitions on these
inputs when selected by EQUALSEL.
TSTCLKEN
CMISEL
RSTB
TTL
TTL
TTL
35
32
34
Test clock enable signal, active high, that enables the reference
clock to be used in place of the VCO for testing. Allows a means
of testing the functions of the chip without the use of the PLL.
CMI Select used to select CMI or NRZ. A logic high selects CMI
mode. Either ANDATIN or SERDATIN may be used as inputs to
the CMI decoder.
Reset input for the device, active low. Initializes the device to a
known state, shuts off SERCLKOP/N, and forces the PLL to
acquire to the reference clock. A reset of at least 16 ms should
be applied at power-up and whenever it is necessary to
reacquire to the reference clock. The S3016 will also reacquire
to the reference clock if the serial data is held quiescent
(constant ones or constant zeros) or LOSIN or LOSOPT are
activated for at least 224 bit intervals.
11
S3015/S3016
E4/STM-1/OC-3 ATM INTERFACE CIRCUITS
S3016 Pin Assignment and Descriptions (Continued)
Pin Name
Level I/O
Pin # Description
LOSIN
Analog
I
18
Loss of signal in. A single-ended input that indicates a loss of
received signal. When the signal level at LOSIN drops below the
voltage level set by LOSREF for greater than 96 to 224 bit
intervals, the data on Serial Data Out (SERDATOP/N) will be
forced to a constant low, and the PLL will change its reference
from the serial data stream to the reference clock. This input is
to be driven by the external bandpass filter and peak detect
circuit as shown in Figure 17. This signal must be used to
assure correct automatic reacquisition to serial data following an
interruption and subsequent reconnection of the data path. This
will assure that the PLL does not "wander" out of reacquisition
range when no signal is applied. When LOSIN is inactive, data
on the SERDATIP/N pins will be processed normally.
LOSOPT
LOSREF
PECL
I
I
4
Loss of optical signal input, active low. It has the same
functionality as LOSIN, except that it is used in optical mode
instead of electrical. It should be driven by the external optical
receiver module to indicate a loss of received optical power.
Analog
19
Loss of signal reference that sets the comparator levels for
LOSIN. (See Table 6.)
CAP1
CAP2
–
I
1
52
The loop filter capacitor is connected to these pins. The
capacitor value should be 0.1µf ±10% tolerance, X7R dielectric.
50 V is recommended.
LOSOUT
TTL
O
5
Loss of signal out, active low. Clock recovery indicator. Set high
when the internal clock recovery has locked onto the incoming
datastream. LOSOUT is an asynchronous output. This output is
deasserted when there is no incoming serial data input or when
the received signal has dropped below the reference voltage set
by LOSREF for more than 96 to 224 bit intervals. In this case,
the PLL locks to the reference clock.
SERDATOP
SERDATON
Diff.
PECL
O
6
7
Serial NRZ data out signal. It can be either a delayed version of
the NRZ data input (NRZ mode) or the decoded CMI data (CMI
mode). SERDATOP/N is updated on the falling edge of
SERCLKOP/N per Figure 12.
SERCLKOP
SERCLKON
Diff.
O
O
28
29
Serial clock out signal that is phase-aligned with Serial Data Out
(SERDATOP). (See Figure 12 and Table 3 for timing.)
PECL
LCV
Single-
ended
PECL
31
Line code violation that is set high to indicate that the current bit
contains a CMI line code violation in CMI mode. LCV is updated
on the falling edge of SERCLKOP/N per Figure 12. In NRZ
mode, this is a test output.
12
E4/STM-1/OC-3 ATM INTERFACE CIRCUITS
S3015/S3016
S3016 Pin Assignment and Descriptions (Continued)
Pin Name
Level I/O
Pin # Description
BUFOUT
Analog
O
20
Buffer output of the equalizer network buffer circuit. This circuit
provides a low impedance driver to the equalizer circuit. This pin
should be connected as shown in Figure 17 to drive the
equalizer network.
REFCKOUT
AVEE
TTL
0V
O
11
Single-ended TTL reference clock output (19.44 MHz).
–
2, 17, 21, Analog 0V
39, 42,
43
AVCC
+5V
–
3, 15, 24, Analog +5V
38, 40,
48
ECLVEE
ECLVCC
0V
–
–
8, 36
Digital 0V
+5V
9, 12, 25, Digital +5V
30, 37
TTLGND
TTLVCC
NC
GND
+5V
–
–
–
–
13, 27
14, 26
TTL Ground
TTL Power Supply (+5V if TTL)
41, 44, No Connection
47, 49,
50, 51
13
S3015/S3016
E4/STM-1/OC-3 ATM INTERFACE CIRCUITS
Figure 15. 52-Pin PQFP Package and Heatsink
51
49
47
45
43
41 40
DW0045-29
1
2
39
38
4
6
36
34
32
30
28
Embedded
Heatsink
8
10
12
TOP VIEW
10.0
12.0
10˚
.64
1.40
.64
0.65
All dimensions nominal in mm.
14
E4/STM-1/OC-3 ATM INTERFACE CIRCUITS
S3015/S3016
Absolute Maximum Ratings
PARAMETER
MIN TYP MAX UNIT
Case Temperature under Bias
Junction Temperature under Bias
Storage Temperature
–55
–55
125 °C
150 °C
150 °C
–65
Voltage on VCC with Respect to GND
Voltage on Any TTL Input Pin
Voltage on Any PECL Input Pin
TTL Output Sink Current
–0.5
–0.5
VCC-3
+7.0
+5.5
VCC
V
V
V
20 mA
10 mA
TTL Output Source Current
High Speed PECL Output Source
Current
50 mA
V
Static Discharge Voltage
500
Recommended Operating Conditions
PARAMETER
MIN TYP MAX UNIT
Ambient Temperature under Bias
Junction Temperature under Bias
Voltage on VCC with Respect to GND
Voltage on Any TTL Input Pin
Voltage on Any PECL Input Pin
S3015 ICC
-40
-10
85
°C
+125 °C
4.75 5.0 5.25
V
V
V
0
VCC
VCC
VCC-2
141 240 mA
180 240 mA
S3016 ICC
15
S3015/S3016
E4/STM-1/OC-3 ATM INTERFACE CIRCUITS
Table 2. S3015/S3016 Clock Recovery Mode Performance Specifications
Parameter
Min
Typ
Max
Units
Condition
Nominal VCO
Center Frequency
622.08
MHz
Given REFCKIN = VCO ÷ 32
OC–3/STS–3
Lock Range
+8, -12
%
With respect to fixed reference
frequency
With device already powered up
and valid REFCLK
1
Acquisition Lock Time
64
70
µsec
Reference Clock
Input Duty Cycle
30
% of UI
Reference Clock Rise &
Fall Times
5.0
ns
10% to 90% of amplitude
PECL Output Rise & Fall
Times
10% to 90%, 50Ω load,
5 pf cap
850
100
ps
Reference Clock
Frequency Tolerance
-100
100
ppm
tP
SER
SERCLKOP Falling to
SERDATO Valid Prop
Delay
500
ps
See Figure 13
1. Specification based on design values. Not tested.
Table 3. S3015 Clock Synthesis Mode Performance Specifications
Parameter
Min
Typ
Max
Units
Condition
PECL Data Output Jitter
(S3015 SERDATOP/N)
OC–3/STS–3
In CSU mode, given
64
32
ps (rms)
• 56 ps rms jitter on
REFCKIN in 12KHz to
1 MHz band
• 28 ps rms jitter on
REFCKIN in 12KHz to
1 MHz band
E4–STS–3 CMI
Reference Clock
Frequency Tolerance
Clock Synthesis
Required to meet SONET output
jitter generation specification
-20
+20
ppm
(1)
Table 4. Electrical Characteristics for Transformer Driver
(VCC = +5V, TA = +25°C, input AC coupled unless otherwise noted.)
Parameter
Min
Typ
155
Max
Units
Condition
270 Ω || 3pF load
Operating Frequency
MHz
(2)
VSWR
1.3:1
1.5:1
75 Ω A.C. Coupled Termination
1. For output waveform characteristics, see Figures 8 and 9.
2. Up to 250 MHz.
16
E4/STM-1/OC-3 ATM INTERFACE CIRCUITS
S3015/S3016
Table 5. Electrical Characteristics for ANDATIN Input
(VCC = +5V, TA = +25°C, input AC coupled unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
V
Peak to Peak Input Voltage Range
Common-Mode Rejection Ratio
Power-Supply Rejection Ratio
Input Sensitivity
1.3
V
dB
dB
mV
V
iptp
CMRR(1)
PSRR(1)
40
40
S
110
T
= MIN to MAX
IN
A
DC offset at input (2)
V
- 1V
CC
1. Up to 300 KHz
2. Signal is undefined if left floating
Table 6. Electrical Characteristics for LOSIN Input
(VCC = +5V, TA = +25°C, input AC coupled unless otherwise noted.)
PARAMETER
SYMBOL CONDITIONS
MIN
TYP
MAX
UNITS
V
Peak to Peak Input Voltage Range
Common-Mode Rejection Ratio
Power-Supply Rejection Ratio
1.1
V
iptp
(1)
CMRR
40
dB
dB
(1)
35
PSRR
LOS-
LOS-
LOS-
Signal Level for LOS detected (3)
V/V
V/V
dB
T
T
= MIN to MAX
= MIN to MAX
A
A
REF/30 REF/20 REF/10
LOS-
REF/15 REF/10
LOS-
LOS-
REF/5
Signal Level for LOS cleared (3)
Hysterisis between "trans. cond."
4
6
(2)
and "no trans. cond."
1. Up to 300 KHz
2. LOSREF >0.5 volts
3. LOS detected and LOS cleared will maintain 2:1 ratio ±5%.
Below are typical operating conditions:
Voltage Applied at
Compare Voltage #1
Compare Voltage #2
Hysterisis
LOSREF
1.4 Volts
0.7 Volts
0.3 Volts
140 mV ± 0.6dB
70 mV ± 1dB
30 mV ± 1.6dB
70 mV ± 1dB
35 mV ± 1.6dB
15 mV ± 3.5dB
6dB +1.6 -1.4dB
6dB +2.7 -2.0dB
6dB +6.0 -3.7dB
17
S3015/S3016
E4/STM-1/OC-3 ATM INTERFACE CIRCUITS
Table 7. Electrical Characteristics for BUFIN, BUFOUT
At VCC = +5VDC, RLOAD = 75Ω a.c. coupled and TA = 25˚C unless otherwise noted.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
OUTPUT CHARACTERISTICS (BUFOUT)
Voltage Output
± 0.6
1
± 0.8
3
V
Output Resistance
8
Ω
TRANSFER CHARACTERISTICS
Gain (BUFIN to BUFOUT)(1)
.85
.93
1.1
V/V
With 75 ohm AC coupled
termination
VSWR(2)
VSWR
HD
1.3:1
1.5:1
Input = 0.3V p-p
Input = 0.6V p-p
Input = 1.2V p-p
35
30
25
40
35
30
Harmonic Distortion(2)
dBc
DC Input Bias
Input externally AC coupled
Output externally AC coupled
Vcc - 0.85
Vcc - 2.5
V
V
DC Output Bias
1. Up to 300 MHz
2. Up to 250 MHz
Thermal Management
Θja Still Air
w/DW0045-29
Max Still Air1
w/DW0045-29
Device
Power
S3015/S3016
1.25W
37.5˚C/W
85˚C
1. Max ambient temperature permitted in still air to maintain T <130˚C.
j
18
E4/STM-1/OC-3 ATM INTERFACE CIRCUITS
S3015/S3016
TTL Input/Output DC Characteristics
(TA = -40°C to +85°C, VCC = 5 V ±5%)
Symbol
Parameter
Input LOW Voltage
Input HIGH Voltage
Input LOW Current
Input HIGH Current
Min
Typ
Max
0.8
Unit
Volts
Volts
µA
Conditions
Guaranteed Input LOW Voltage
1
V
V
I
IL
1
2.0
Guaranteed Input HIGH Voltage
IH
-400.0
V
V
V
= MAX, V = 0.5V
IN
CC
CC
CC
IL
50.0
1.0
µA
= MAX, V = 2.7V
IN
I
I
IH
mA
= MAX, V = 5.5V
IN
Input HIGH current at
Max. VCC
I
-100.0
-1.2
-25.0
0.5
mA
V
CC
V
CC
V
CC
V
CC
= MAX, V
= 0.5V
I
Output Short Circuit Current
Input Clamp Diode Voltage
Output LOW Voltage
OUT
= MIN, I = -18 ma
OS
V
V
Volts
Volts
IK
IN
= MIN, I
= MIN, I
= 8 ma
OL
OL
= -1 ma
Output HIGH Voltage
Volts
V
2.7
OH
OH
1. These input levels provide zero noise immunity and should only be tested in a static, noise-free environment.
PECL Input/Output DC Characteristics
(TA = -40°C to +85°C, VCC = 5 V ±5%)
Symbol
Parameter
Min
Typ
Max
Unit
Conditions
Guaranteed Input LOW Voltage
for single-ended inputs
Input LOW Voltage
V
V
V
V
V
V
-2.000
V
V
-1.441
Volts
IL
CC
CC
Guaranteed Input HIGH Voltage
for single-ended inputs
Volts
Input HIGH Voltage
-1.225
-0.570
IH
IL
CC
CC
Guaranteed Input LOW Voltage
for differential inputs
Input LOW Voltage
Input HIGH Voltage
V
V
-2.000
-1.750
V
V
-0.700
-0.450
Volts
Volts
CC
CC
CC
CC
Guaranteed Input HIGH Voltage
for differential inputs
IH
ID
0.250
0.500
1.400
Volts
µA
V
I
Input Diff. Voltage
Input High Current
Input Low Current
Differential Input Voltage
20.000
20.000
-0.500
-0.500
V
V
= 500mV
= 500mV
IH
ID
ID
µA
I
IL
V
50 ohm termination to V
-2V
-2V
V
V
-2.000
V
V
-1.500
Volts
Output LOW Voltage
OL
CC
CC
CC
CC
V
V
Output HIGH Voltage
Output Diff. Voltage
50 ohm termination to V
-1.110
-0.670
Volts
Volts
OH
OD
CC
CC
0.390
1.330
Differential Output Voltage
1. These conditions will be met with no airflow.
2. When not used, tie the positive differential PECL pin to VCC and the negative
differential ECL pin to ground via a 3.9K resistor.
19
S3015/S3016
E4/STM-1/OC-3 ATM INTERFACE CIRCUITS
Figure 16. Differential ECL Input and Output Applications
SERDATIP
SERDATIN
Fiber Optic
Receiver
100 Ω
330 Ω
GND
330 Ω
ECL driver to
SERDATIP/N input
Figure 17. S3016 Transformer Input Application
S3016
27pF 470Ω
TRANSFORMER
BUFINA
BUFINB
75Ω
GND
GND
Cable Input
BUFOUT
ANDATIN
EQUALIZER
LOSIN
LOSIN
COMPENSATOR
+5V
LOSREF
.01µF
GND
GND
Figure 18. S3015 Differential ECL Output Application
SERDATOP/N
Electrical
to
100 Ω
Optical
330 Ω
330 Ω
GND
Figure 19. S3015 Transformer Output Application
XFRMDRVA
24Ω
30Ω
.01uf
Cable Output
XFRMDRVB GND
24Ω
30Ω
.01uf
Monitor Output
220Ω
220Ω
GND
GND
20
E4/STM-1/OC-3 ATM INTERFACE CIRCUITS
S3015/S3016
Figure 20. OC3 Application
19.44 MHz
S3026
REFCKIN
2
2
155 MHZ
TX_CLK_+/–
SERCLKOP/N
2
SUNI
IGT
TX_DATA_+/–
E/O
SYN155
S3016
REFCKIN
2
2
155 MHZ
SERCLKOP/N
RX_CLK_+/–
SERDATOP/N
LOS
RX_DATA_+/–
2
O/E
SERDATIP/N
Figure 21. STM-1 CMI, E4 Application
19.44 MHz
S3015
REFCKIN
SERDATIP/N
REFCKIN
2
TX_DATA_+/–
XFRMDRVA
Cable
Output
GND
GND
XFRMDRVB
Monitor
Output
SUNI-LITE
SUNI-PLUS
SABRE
SERDAT0P/N
2
S3016
SERDATIP/N
BUFIN
S3011/12
REFCKIN
Cable
Input
2
RX_CLK_+/–
SERCLKOP/N
SERDATOP/N
2
RX_DATA_+/–
GND
BUFOUT
Equalizer
ANDATIN
LOSIN
+5V
EQUALSEL
LOSREF
LOSIN
Compensator
.01µF
GND
21
S3015/S3016
E4/STM-1/OC-3 ATM INTERFACE CIRCUITS
Table 8. Suggested Interface Devices
Processor Interface
PMC PM5345
SUNI
Saturn User Network Interface
Saturn User Network Interface
Saturn User Network Interface
SONET LAN ATM Processor
155 Mbit/s Synchronizer
PMC PM5346
SUNI-Lite
SUNI-Plus
PMC PM5347
IGT WAC-013-A
TRANSWITCH SYN155
TI SABRE TDC 1500
AMCC S3011/12
Electrical Interface
Mini-Circuits
155 Mbit/s Processor
SONET/SDH/ATM 0C3 Transmitter & Receiver
MCL TXI-R5
MCL TO-75
Wideband RF Transformer (Surface Mount)
Wideband RF Transformer (Through-Hole)
Mini-Circuits
Optical Interface
HP HFBR-520x
CTS ODL-1408X
155 Mbit/s
155 Mbit/s
Fiber Optic Transceiver
Fiber Optic Transceiver
Fiber Optic Transceiver
Fiber Optic Transceiver
Sumitomo SDM4123-XC 155 Mbit/s
AMP 269039-1 155 Mbit/s
Ordering Information
GRADE
TRANSMITTER
S – Industrial/
commercial
A – 52 TQFP TEP
w/DW0045-29 heatsink unattached
H0 – No Heatsink
H0 – No Heatsink
3015
GRADE
RECEIVER
A – 52 TQFP TEP
S – Industrial/
commercial
3016
w/DW0045-29 heatsink unattached
X XXXX
X / XX
Grade Part number
Package H0 for no heatsink (identifier not marked on part)
22
E4/STM-1/OC-3 ATM INTERFACE CIRCUITS
S3015/S3016
Applied Micro Circuits Corporation • 6290 Sequence Dr., San Diego, CA 92121
Phone: (619) 450-9333 • (800)755-2622 • Fax: (619) 450-9885
http://www.amcc.com
AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and
advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied
on is current.
AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it
convey any license under its patent rights nor the rights of others.
AMCC reserves the right to ship devices of higher grade in place of those of lower grade.
AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR
USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
AMCC is a registered trademark of Applied Micro Circuits Corporation.
Copyright ® 1997 Applied Micro Circuits Corporation
June 2, 1997
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