S3050TT [AMCC]
Clock Recovery Circuit, 1-Func, Bipolar, PQFP32, HEAT SINK, TQFP-32;
| 型号： | S3050TT |
| 厂家： | 
APPLIED MICRO CIRCUITS CORPORATION |
| 描述： | Clock Recovery Circuit, 1-Func, Bipolar, PQFP32, HEAT SINK, TQFP-32 ATM 异步传输模式 电信 电信集成电路 |
| 文件： | 总17页 (文件大小：132K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
This product is not released
and the specifications herein
are subject to change.
DEVICE
SPECIFICATION
S3050
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
FEATURES
GENERAL DESCRIPTION
The function of the S3050 clock recovery unit is to
derive high speed timing signals for SONET/SDH-
based equipment. The S3050 is implemented using
AMCC’s proven Phase Locked Loop (PLL) technology.
•
•
Micro-power Bipolar technology
Complies with Bellcore and ITU-T specifica-
tions for jitter tolerance, jitter transfer and
jitter generation
The S3050 receives an OC-48, OC-24, GBE, OC-
12, or OC-3 scrambled NRZ signal and recovers
the clock from the data. The chip outputs a differ-
ential bit clock and retimed data. Figure 1 shows a
typical network application.
•
•
On-chip high frequency PLL with internal
loop filter for clock recovery
Supports clock recovery for:
OC-48 (2488.32 Mbps),
OC-24 (1244.16 Mbps),
Gigabit Ethernet (1250 Mbps),
OC-12 (622.08 Mbps),
OC-3 (155.52 Mbps) NRZ data
The S3050 utilizes an on-chip PLL which consists
of a phase detector, a loop filter, and a voltage
controlled oscillator (VCO). The phase detector
compares the phase relationship between the VCO
output and the serial data input. A loop filter con-
verts the phase detector output into a smooth DC
voltage, and the DC voltage is input to the VCO
whose frequency is varied by this voltage. A func-
tional block diagram is shown in Figure 2.
•
•
•
•
•
155.52 MHz reference frequency
Lock detect—monitors frequency
Low-jitter serial interface
+5V supply
32 TQFP/TEP package
Figure 1. System Block Diagram
8
8
8
8
8
8
S3041
Tx
S3042
8
8
OTX
8
8
ORX
S3050
OTX
Rx
8
8
8
8
8
8
8
8
8
8
S3042
Rx
S3041
Tx
S3050
ORX
July 9, 1999 / Revision D
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S3050
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
Suggested Interface Devices
S3050 OVERVIEW
Sumitomo
OC-48 Optical Receiver
OC-48 Receiver
The S3050 supports clock recovery for the OC-48,
OC-24, Gigabit Ethernet, OC-12, or OC-3 data rate.
Differential serial data is input to the chip at the speci-
fied rate, and clock recovery is performed on the in-
coming data stream. An external oscillator is required
to minimize the PLL lock time, and to provide a stable
output clock source in the absence of the serial input
data. The retimed data and clock are output from the
S3050.
AMCC S3044
AMCC S3042
OC-48 Receiver
Figure 2. S3050 Functional Block Diagram
LOOP
FILTER
VCO
CAP 1,2
2
REFCLKP/N
2
TESTEN
SERCLKOP/N
CLOCK
DIVIDER
2
RATESEL[1:0]
BYPASS
RESET
LOCK
DETECTOR
LOCKDET
LCKREFN
PHASE DETECTOR
2
SERDATOP/N
SDN
2
SERDATIP/N
July 9, 1999 / Revision D
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S3050
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
The loop filter transfer function is optimized to enable
the PLL to track the jitter, yet tolerate the minimum
transition density expected in a received SONET
data signal. This transfer function yields a typical
capture time as stated in Table 4 for random incom-
ing NRZ data.
S3050 FUNCTIONAL DESCRIPTION
The S3050 clock recovery device performs the clock
recovery function for SONET OC-48, OC-24, Gigabit
Ethernet, OC-12, or OC-3 serial data links. The chip
extracts the clock from the serial data inputs and
provides retimed clock and data outputs. A 155.52
MHz (156.25 for Gigabit Ethernet) reference clock is
required for phase locked loop start up and proper
operation under loss of signal conditions. An integral
prescaler and phase locked loop circuit is used to
multiply this reference to the nominal bit rate. The
input data rate is selected by the RATESEL[1:0]
inputs. (See Table 1.)
The total loop dynamics of the clock recovery PLL
yield a jitter tolerance which exceeds the minimum
tolerance proposed for SONET equipment by the
Bellcore TA-NWT-000253 standard, shown in Figure 3.
Lock Detect
The S3050 contains a lock detect circuit which monitors
the integrity of the serial data inputs. If the received
serial data fails the frequency test, the PLL will be
forced to lock to the local reference clock. This will
maintain the correct frequency of the recovered clock
output under loss of signal or loss of lock conditions. If
the recovered clock frequency deviates from the local
reference clock frequency by more than the value
stated in Table 4, the PLL will be declared out of lock.
The lock detect circuit will poll the input data stream in
an attempt to reacquire lock to data. If the recovered
clock frequency is determined to be within the specifi-
cation as in Table 4, the PLL will be declared in lock
and the lock detect output will go active.
Clock Recovery
Clock Recovery, as shown in the block diagram in
Figure 2, generates a clock that is at the same fre-
quency as the incoming data bit rate at the serial
data input. The clock is phase aligned by a PLL so
that it samples the data in the center of the data eye
pattern.
The phase relationship between the edge transi-
tions of the data and those of the generated clock
are compared by a phase/frequency discriminator.
Output pulses from the discriminator indicate the
required direction of phase corrections. These
pulses are smoothed by an integral loop filter. The
output of the loop filter controls the frequency of
the Voltage Controlled Oscillator (VCO), which
generates the recovered clock.
Table 1. Data Rate Select
Operating
Mode
REFCLK
Frequency
RATESEL0 RATESEL1
0
0
1
1
0
1
0
1
OC-48
OC-24
OC-12
OC-3
155.52 MHz
Frequency stability without incoming data is guaran-
teed by an alternate reference input (REFCLKP/N)
that the PLL locks onto when data is lost. If the Fre-
quency of the incoming signal is not within the range
stated in Table 4 with respect to REFCLKP/N, the PLL
will be declared out of lock, and the PLL will lock to the
reference clock. The assertion of Signal Detect (SDN)
will also cause an out of lock condition.
Gigabit
Ethernet
0
1
156.25 MHz
July 9, 1999 / Revision D
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S3050
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
Jitter Transfer
CHARACTERISTICS
Jitter transfer function is defined as the ratio of jitter
on the output OC-N/STS-N signal to the jitter applied
on the input OC-N/STS-N signal versus frequency.
Jitter transfer requirements are shown in Figure 4.
The measurement condition is that input sinusoidal
jitter up to the mask level in Figure 3 be applied.
Performance
The S3050 PLL complies with the jitter specifications
proposed for SONET/SDH equipment defined by the
Bellcore Specifications: GR-253-CORE, Issue 2, De-
cember 1995 and ITU-T Recommendations: G.958
document, when used with differential inputs and out-
puts.
Jitter Generation
The jitter of the serial clock and serial data outputs
shall not exceed 0.01 UI rms when a serial data input
with no jitter is presented to the serial data inputs.
(See Table 4).
Input Jitter Tolerance
Input jitter tolerance is defined as the peak to
peak amplitude of sinusoidal jitter applied on the
input signal that causes an equivalent 1 dB opti-
cal/electrical power penalty. SONET input jitter
tolerance requirements are shown in Figure 3.
The measurement condition is the input jitter am-
plitude which causes an equivalent of 1 dB power
penalty.
Figure 4. Jitter Transfer Specification
Figure 3. Input Jitter Tolerance Specification
P
Sinusodal
slope = -20 dB/decade
Input Jitter
Amplitude
15
1.5
Jitter
Transfer
Acceptable
(UI p-p)
Range
0.15
fc
Frequency
f0
f2
f3
ft
f1
OC/STS
fc
(kHz)
P
(dB)
Level1,2
Frequency
48
2000
0.1
OC/STS
f0
f1
f2
f3
ft
Level
(Hz)
(Hz)
(Hz) (kHz) (kHz)
243
12
48
10
600
6000
100
1000
500
225
0.1
0.1
241
12
3
10
10
30
30
300
300
25
250
65
1. Bellcore Specifications: GR-253- CORE, Issue 2,
December 1995.
2. ITU-T Recommendations: G.958.
3. Not specified in GR-253 or G.958.
3
6.5
1. Not specified in GR-253 and G.958.
July 9, 1999 / Revision D
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S3050
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
Table 2. Pin Assignment and Descriptions
Pin Name
Level
I/O
Pin#
Description
SERDATIP
SERDATIN
Diff.
PECL
5
6
Serial Data In. Clock is recovered from the transitions on these
inputs. Internally biased and terminated.
I
I
Test Input Signal used for production test. Active High. Leave
open for normal operation.
TESTEN
PECL
1
Signal Detect. Active Low. A single-ended 10K PECL input to be
driven by the external optical receiver module to indicate a loss of
received optical power. When SDN is inactive, the data on the
Serial Data In (SERDATIP/N) pins will be internally forced to a
constant zero, and the PLL will be forced to lock to the REFCLK
inputs. When SDN is active, data on the SERDATIP/N pins will be
processed normally. If not used, leave open.
SDN
PECL
I
I
11
Reference Clock. 155.52 MHz input used to establish the initial
operating frequency of the clock recovery PLL, and also used as
a standby clock in the absence of data, during reset or when SDN
is inactive. Internally biased.
REFCLKP
REFCLKN
Diff.
PECL
8
9
CAP1
CAP2
28
27
Loop Filter Capacitor. The loop filter capacitor and resistors are
connected to these pins. See Figure 14.
I
I
Lock to Reference. Active Low. When active, the serial clock
output will be forced to lock to the local reference clock input
[REFCLKP/N].
LCKREFN
TTL
10
RATESEL0
RATESEL1
31
24
TTL
I
I
Selects the operating mode (See Table 1).
Resets digital circuitry. Active High. Used for testing. To be open
during normal operation.
RESET
PECL
32
Serial Data Out. This signal is the delayed version of the incoming
data stream (SERDATI). Updated on the falling edge of Serial
Clock Out (SERCLKOP).
SERDATOP
SERDATON
19
18
CML
CML
TTL
TTL
O
O
O
I
SERCLKOP
SERCLKON
23
22
Serial Clock Out. This signal is phase aligned with Serial Data Out
(SERDATOP/N). (See Figure 7.)
Lock Detect. Clock recovery indicator. Set High when the internal
clock recovery has locked onto the incoming data stream.
LOCKDET is an asynchronous output.
LOCKDET
BYPASS
16
20
Bypass Enable. Active High. Used during production test to
bypass the VCO in the PLL. Tie to ground for normal operation.
July 9, 1999 / Revision D
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S3050
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
Table 2. Pin Assignment and Descriptions (Continued)
Pin Name
Level
I/O
Pin#
Description
2
29
AVCC
+5V
Analog power supply.
3
4
21
30
AVEE
GND
Analog GND connection.
12
14
25
VCC
VEE
+5V
Power Supply.
13
15
26
GND
Ground connection.
NC
7
No connection.
DNC
17
Do not connect. (Must be left floating.)
July 9, 1999 / Revision D
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S3050
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
Figure 5. S3050 Pinout—32 TQFP/TEP
RATESEL1
SERCLKOP
SERCLKON
AVEE
TESTEN
AVCC
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
S3050
32 TQFP/TEP
AVEE
AVEE
SERDATIP
SERDATIN
NC
BYPASS
SERDATOP
SERDATON
DNC
Top View
REFCLKP
Table 3. Thermal Management (32 TQFP/TEP Package)
Symbol
Θja
Description
Air Flow
Value
36
Units
Thermal resistance from junction to ambient in still air
Thermal resistance from junction to ambient
Thermal resistance from junction to ambient
Thermal resistance from junction to ambient
Thermal resistance from junction to ambient
Still Air
˚ C/W
˚ C/W
˚ C/W
˚ C/W
˚ C/W
Θja
100 LFPM
200 LFPM
300 LFPM
400 LFPM
34
Θja
32
Θja
31
Θja
30
July 9, 1999 / Revision D
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S3050
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
Figure 6. 32 TQFP/TEP Package
BOTTOM VIEW
TOP VIEW
Note: The S3050 package is equipped with an embedded conductive heatsink on the bottom (board side). Active circuitry and vias should not
appear in the area immediately under the package. This heatsink is electrically biased to the Vee potential of the S3050. For optimum thermal
management, a foil surface at ground (or Vee if other than ground) is recommended immediately under the package, and connected with
multiple vias to the internal plane(s) of similar potential. Thermally conductive epoxy or other conductive interposer can be used to establish a
good thermal dissipation path.
July 9, 1999 / Revision D
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S3050
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
Table 4. Performance Specifications
Parameter
Min
Typ
Max
Units
Condition
Nominal VCO
Center Frequency
2.5
GHz
CLK Output Jitter with VCO locked to
REFCLK
155 MHz Ref. Clk.
OC-48
OC-12
OC-3
0.01
0.007
0.004
UI (rms) rms jitter, SDN active.
CLK Output Jitter with VCO locked to
SERDATIP/N
0.01
UI (rms) With no jitter on serial data inputs.
ppm
Reference Clock Frequency Tolerance
Capture Range
-100
+100
ppm
With respect to fixed reference
frequency
±200
Capture Time
Lock Range
32
µs
%
±12
Minimum transition density of 20%
Guaranteed but not tested.
With device already powered up
and valid ref. clk.
Acquisition Lock Time
16
µsec
Reference Clock
Input Duty Cycle
40
60
1.0
150
% of UI
ns
Reference Clock Rise & Fall Times
CML Output Rise & Fall Times
20% to 80% of amplitude
20% to 80%, 50Ω load,
1 pF cap
100
600
ps
Frequency difference at which the PLL
goes out of lock (REFCLK compared
to the divided down VCO clock)
340
220
732
366
ppm
ppm
Frequency difference at which the
receive PLL goes into lock (REFCLK
compared to the divided down VCO
clock)
300
tSU
100
300
500
OC-48
OC-24/Gigabit Ethernet
OC-12
OC-3
ps
ps
See Figure 7.
See Figure 7.
2500
tH
100
300
500
OC-48
OC-24/Gigabit Ethernet
OC-12
OC-3
2500
July 9, 1999 / Revision D
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S3050
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
Figure 7. Receiver Output Timing Diagram
SERCLKOP
t
t
su
H
SERDATOP/N
Note: Output propagation delay time of high speed CML outputs is the time in pico seconds from the cross-over point of the reference signal
to the cross-over point of the output.
Table 5. Jitter Tolerance
Parameter
Min
Typ
Max
Units
Conditions
12kHz < F < 20MHz
Jitter Tolerance – STS-48
0.4
0.5
UI
Data Pattern = 27-1 PRBS
12kHz < F < 5MHz
Jitter Tolerance – STS-12
Jitter Tolerance – STS-3
0.4
0.4
0.6
0.8
UI
UI
ps
ps
Data Pattern = 27-1 PRBS
12kHz < F < 1MHz
Data Pattern = 27-1 PRBS
Gigabit Ethernet
Total Input Jitter Tolerance
599
370
As specified in IEEE 802.3z
As specified in IEEE 802.3z
Gigabit Ethernet
Deterministic Input Jitter Tolerance
Table 6. Recommended Operating Conditions
Parameter
Min
Typ
5.0
Max
+851
+70
5.25
VCC
Unit
˚ C
˚ C
V
Case Temperature under Bias
Ambient Temperature under Bias (commercial)
Voltage on VCC with Respect to GND
Voltage on Any TTL Input Pin
-40
0
4.75
0.0
V
Voltage on Any PECL Input Pin
V
CC -2
VCC
V
ICC Supply Current
251
317
mA
1. Maximum specification for case temperature at 85˚C.
July 9, 1999 / Revision D
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S3050
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
Table 7. Absolute Maximum Ratings
Parameter
Min
Typ
Max
+150
+7.0
+5.5
VCC
Unit
˚ C
V
Storage Temperature
-65
-0.5
Voltage on VCC with Respect to GND
Voltage on any TTL Input Pin
Voltage on any PECL Input Pin
TTL Output Sink Current
-0.5
V
VCC -2.0
V
20
mA
mA
V
TTL Output Source Current
ESD Sensitivity Rating 1
10
Under 500
1. Human body model.
Table 8. SERDATIP/N Differential PECL Input Characteristics
Symbol
Parameter
Min
Max Units
Conditions
VCC
–2.0
VCC
+0.5
VI1
Common Mode Input Voltage range
V
Note: VID = 2 VIS
See Figure 8.
1
1
VID
Differential Input Voltage Swing
Single-Ended Input Voltage Swing
0.5V
0.25
1.3
V
V
VIS
0.65
VIS = VSERDATP - VSERDATN
V
CC = MAX, VIH = VCC-0.8V,
VD = 0.5V (due principally to
current through internal
100 Ω Diff. termination)
IIL
Input LOW Current
–5.4
–3.0
mA
V
CC = MAX, VIH = VCC-2V,
VD = 0.5V (due principally to
current through internal
100 Ω Diff. termination)
IIH
Input HIGH Current
Internal Bias Voltage
4.0
VCC
6.4
VCC
mA
V
VIBIAS
Input Open
–0.6 –0.31
1. These input levels provide a zero-noise immunity and are valid for a static, noise free environment.
July 9, 1999 / Revision D
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S3050
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
Table 9. SERDATOP/N, SERCLKOP/N, CML Output Characteristics
Symbol
Parameter
Min
Max Units
Conditions
VCC
–1.2
VCC
–0.5
VOL
Output LOW Voltage
V
100Ω line-to-line termination
VCC
–0.4
VCC
–0.1
VOH
Output HIGH Voltage
V
100Ω line-to-line termination
OC-48
400
300
800
600
800
800
mV
mV
mV
mV
Single-Ended Output Voltage Swing
VOS
100Ω line-to-line termination
(VOD = 2 x VOS)
OC-3, OC-12, OC-24, GE
Single-Ended Output Voltage Swing
OC-48
1600
1600
Differential Ouput Voltage Swing
100Ω line-to-line termination
(VOD = 2 x VOS). See Figure 8.
VOD
OC-3, OC-12, OC-24, GE
Differential Ouput Voltage Swing
1. These input levels provide a zero-noise immunity and are valid for a static, noise free environment.
Figure 8. Differential Voltage Measurement
V(+)
V
SWING
V(–)
V(+) – V(-)
V
= 2 X V
D
SWING
0.0V
Note: V(+) – V(-) is the algebraic difference of the input signals.
July 9, 1999 / Revision D
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S3050
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
Table 10. REFCLKP/N, Differential PECL Input Characteristics
Symbol
Parameter
Min
Max Units
Conditions
VCC
–2.0
VCC
–0.5
VI1
VID
Maximum Input Voltage
V
Note: VID = 2 VIS
See Figure 8.
1
Differential Input Voltage Swing
0.500
0.250
2.0
1.0
V
VIS
IIL
Single-Ended Input Voltage Swing
Input LOW Current
V
Note: VIS = 1/2 VID
–300 –100
µA
µA
VCC = MAX, VIL = VCC–2.0V
VCC = MAX, VIH = VCC–0.8V
IIH
Input HIGH Current
100
380
VCC
–1.4
VCC
–1.2
VIBIAS
Internal Bias Voltage
V
Inputs Open
1. These input levels provide a zero-noise immunity and are valid for a static, noise free environment.
Table 11. SDN, RESET, TESTEN, Single-Ended PECL Input Characteristics
Symbol
Parameters
Min
Max Units
Conditions
Single-ended PECL LOW
voltage range.
Guaranteed at 85˚ C.
VCC
–2.0 –1.47
VCC
1, 2
VIL
VIH
Input LOW Voltage
V
Single-ended PECL HIGH
voltage range.
Guaranteed at -40˚ C.
VCC
–1.18 –0.4
VCC
1, 2
Input HIGH Voltage
V
IIL
Input LOW Current
Input HIGH Current
–600
100
0
µA
µA
VCC = MAX, VIL = VCC–2.0V
VCC = MAX, VIH = VCC–0.8V
IIH
500
1. These input levels provide a zero-noise immunity and are valid for a static, noise free environment.
2. The AMCC LVPECL inputs (VIL and VIH) are non-temperature compensated I/O which vary at 1.3mV/˚C.
July 9, 1999 / Revision D
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S3050
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
Table 12. TTL Input/Output DC Characteristics
Symbol Parameter
Min
Max Units
Test Conditions
Guaranteed Input Low
Voltage for all inputs.
1
VIL
Input Low Voltage
0.8
V
V
Guaranteed Input High
Voltage for all inputs.
1
VIH
Input High Voltage
2.0
-1
IIL
Input Low Current
mA
µA
mA
mA
V
VCC = MAX, VIN = 0.5V
VCC = MAX, VIN = 2.7V
VCC = MAX, VIN = 5.25V
VCC = MAX, VOUT= 0.5V
VCC = MIN, IIN= -18.0mA
VCC = MIN, IOL= 4mA
IIH
II
Input High Current
50.0
1.0
Input High Current at Max VCC
Output Short Circuit Current
Input Clamp Diode Voltage
TTL Output Low Voitage
TTL Output High VOltage
IOS
VIK
-40
-5.0
-1.2
VOL
VOH
0.5
V
2.4
V
VCC = MIN, IOH= -1.0mA
1. These input levels provide a zero-noise immunity and should only be tested in a static, noise-free environment.
July 9, 1999 / Revision D
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S3050
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
Figure 9. +5V Differential PECL Driver to S3050 Input Direct Coupled Termination
+5V
+5V
Vcc -0.4V
Zo=50Ω
Zo=50Ω
330Ω
330Ω
100Ω
Vcc -0.4V
S3050
SERDATIP/N
Figure 10. +5V Differential PECL Driver to S3050 Input AC Coupled Termination
+5V
+5V
Vcc -0.4V
0.01µF
330Ω
Zo=50Ω
Zo=50Ω
100Ω
330Ω
0.01µF
Vcc -0.4V
S3050
SERDATIP/N
Figure 11. S3050 to S3042/S3044 Terminations
+5V
+3.3V
Vcc -0.65V
0.01µF
0.01µF
Zo=50Ω
Zo=50Ω
100Ω
Vcc -0.65V
S3050
SERDATOP/N
SERCLKOP/N
S3042/44
SERDATIP/N
SERCLKIP/N
July 9, 1999 / Revision D
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S3050
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
Figure 12. +3.3V Single Ended LVPECL Driver to S3050 Reference Clock
Input AC Coupled Termination
+3.3V
+5V
Vcc -1.3V
0.01µF
Zo=50Ω
150Ω
51Ω
0.01µF
Vcc -1.3V
S3041/43
155MCK
S3050
REFCLKP/N
Figure 13. +5V Differential PECL Driver to S3050 Reference Clock
Input AC Coupled Termination
+5V
+5V
Vcc -1.3V
0.01µF
Zo=50Ω
330Ω
330Ω
100Ω
0.01µF Zo=50Ω
Vcc -1.3V
155 MHZ
S3050
OSCILLATOR
REFCLKP/N
Figure 14. Loop Filter Capacitor Connections
V
CC
150kΩ
24Ω
CAP1
CAP2
2.2 µF
20 µF
24Ω
150kΩ
V
S3050
CC
July 9, 1999 / Revision D
16
S3050
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
Ordering Information
PREFIX
DEVICE
PACKAGE
S- Integrated Circuit
3050
TT – 32 TQFP/TEP
XXXX
Device
XX
Package
X
Prefix
Applied Micro Circuits Corporation • 6290 Sequence Dr., San Diego, CA 92121
Phone: (858) 450-9333 • (800)755-2622 • Fax: (858) 450-9885
http://www.amcc.com
AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and
advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied
on is current.
AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it
convey any license under its patent rights nor the rights of others.
AMCC reserves the right to ship devices of higher grade in place of those of lower grade.
AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR
USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
AMCC is a registered trademark of Applied Micro Circuits Corporation.
Copyright ® 1999 Applied Micro Circuits Corporation
July 9, 1999 / Revision D
17
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