S4402A-66/D [AMCC]
Clock Generator, 66MHz, BICMOS, PQCC28, PLASTIC, LCC-28;
| 型号： | S4402A-66/D |
| 厂家： | 
APPLIED MICRO CIRCUITS CORPORATION |
| 描述： | Clock Generator, 66MHz, BICMOS, PQCC28, PLASTIC, LCC-28 时钟 信息通信管理 外围集成电路 晶体 |
| 文件： | 总13页 (文件大小：151K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
DEVICE SPECIFICATION
BiCMOS PLL CLOCK GENERATORS
S4402/S4403
FEATURES
APPLICATIONS
• Generates six clock outputs from 20 MHz to
80 MHz (the S4403 generates ten outputs and
HFOUT generates 10MHz to 40MHz)
• CMOS ASIC Systems
• High-speed Microprocessor Systems
• Backplane Clock Deskew and Distribution
• 21 selectable phase/frequency relationships for
the clock outputs
GENERAL DESCRIPTION
• Compensates for clock skew by allowing output
delay adjustment down to 3.125 ns increments
The S4402/S4403 BiCMOS clock generators allow
the user to generate multiphase TTL clocks in the
10–80 MHz range with less than 400 ps of skew. Use
of a single off-chip filter allows an entire 160–320
MHz phase-locked loop (PLL) to be implemented on-
chip. Divide-by-two and times-two outputs allow the
ability to generate output clocks at half, equal to, or
twice the reference clock input frequency. By using
the programmable divider and phase selector, the
user can select from up to 21 different output rela-
tionships. The outputs can be phase-adjusted in in-
crements as small as 3.125 ns to tailor the clocks to
exact system requirements.
• TTL outputs have less than 400 ps maximum
skew
• Lock Detect output indicates loop status
• Internal PLL with VCO operating at 160 to
320 MHz
• Test Enable input allows VCO bypass for open-
loop operation in board test
• Maximum 1.0 ns of phase error (750 ps from
part to part)
• Proven 1.0 micron BiCMOS technology
• Single +5V power supply operation
• 28/44 PLCC packages
Implemented in AMCC’s proven 1.0 micron BiCMOS
technology, the S4402 generates six TTL outputs,
while the S4403 provides those six plus four dupli-
cates (FOUT0A–FOUT3A) for a total of ten. Output
enables are provided for the various banks, allowing
clock control for board and system tests.
Figure 1. Clock Generator Block Diagram
REFCLK
PHASE
DETECTOR
LOCK
CHARGE
PUMP
FBCLK
FILTER
NOTE: FOUT0A, FOUT1A,
FOUT2A, FOUT3A, and
OUTEN2 apply only to the
S4403.
X2FOUT
VCO
÷ 2
HFOUT
I
FOUT0A
0
DIVIDER
FOUT0
I
1
AND
MUX
PHASE
CONTROL
LOGIC
FOUT1A
FOUT2A
FOUT3A
TSTEN
SELECT
FOUT1
FOUT2
FOUT3
Digital
+5V
DIVSEL
PHSEL0
PHSEL1
RESET
0V
OUTEN0
OUTEN1
Analog
+5V
0V
OUTEN2
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
Page 1
S4402/S4403
BiCMOS PLL CLOCK GENERATOR
HFOUT, or X2FOUT) is externally connected to
the feedback input (FBCLK) to produce the result-
ing waveforms shown in the appropriate row in the
table. The last seven columns specify the resulting
phase and frequency relationships of each output
to the user clock input (REFCLK). A negative value
indicates the time by which the output rising edge
precedes the input (REFCLK) rising edge. A posi-
tive value is the time by which the rising edge of
the output follows the rising edge of the input
clock.
FUNCTIONAL DESCRIPTION
Frequency and Phase Controls
The S4402/S4403 clock generators provide multiple
outputs that are synchronized in both frequency and
phase to a periodic clock input. Two select pins and
an external feedback path allow the user to phase-
adjust the six outputs (FOUT0–FOUT3, HFOUT, and
X2FOUT) relative to the input clock REFCLK, as well
as control their frequency.
Table 1. Example Phase Resolution
The DIVSEL input controls the programmable divider
that follows the voltage controlled oscillator (VCO).
This doubles the lock range of the PLL by allowing
the user to select a VCO frequency divided by four
(DIVSEL Low) or by eight (DIVSEL High).
FOUT0–3
Freq
Divider
Select
VCO
Freq
Min Phase
Resolution
80 MHz
66 MHz
50 MHz
40 MHz
40 MHz
33 MHz
25 MHz
20 MHz
4
4
4
4
8
8
8
8
320 MHz
266 MHz
200 MHz
160 MHz
320 MHz
266 MHz
200 MHz
160 MHz
3.125 ns
3.75 ns
5.0 ns
The frequency of the four FOUT0–FOUT3 outputs
(and the duplicate set of the four FOUT0A–
FOUT3A outputs on the S4403) is determined by
the REFCLK clock frequency and the output that is
tied back to the FBCLK input. In addition, the
X2FOUT TTL output provides a clock signal identi-
cal to the FOUT0 output in the divide-by-four
mode, and twice the FOUT0 frequency (maximum
frequency of 80 MHz) in the divide-by-eight mode.
The HFOUT TTL output provides a clock signal
that is in phase with the FOUT0 output, but at half
the FOUT0 frequency in both the divide-by-four
and divide-by-eight modes. Refer to the Output
Select Matrix in Table 3 for the specific relation-
ships.
6.25 ns
3.125 ns
3.75 ns
5.0 ns
6.25 ns
Table 2. Phase Selections
PHSEL1 PHSEL0
Phase Relationship
0
0
All at same phase
0
1
FOUT0–FOUT3 outputs skewed by
90 degrees from each other
1
1
0
1
FOUT1 leads FOUT0 by minimum
phase, FOUT2 lags FOUT0 by
minimum phase, and FOUT3 lags
FOUT0 by 90 degrees
Phase adjustments can be made in increments as
small as 3.125 ns. The minimum phase delay be-
tween FOUT0–FOUT3 signals is a function of the
VCO frequency. The VCO frequency can be deter-
mined by multiplying the output frequency by the di-
vide-by ratio of four or eight, controlled by DIVSEL.
The minimum phase delay t is equal to the period of
the VCO frequency:
FOUT1 lags FOUT0 by minimum
phase, FOUT2 lags FOUT1 by
minimum phase, and FOUT3 lags
FOUT2 by minimum phase
Example:
In a typical system, designers may need several
low-skew outputs, one early clock, one late clock,
a clock at half the input clock frequency, and one
at twice the input clock frequency. This system re-
quirement can be met by setting PHSEL1 to 1,
PHSEL0 to 0, and feeding back FOUT0 to the
FBCLK input (Row 10 of Table 3). The result is
that FOUT0 will be phase-aligned to REFCLK,
FOUT1 will lead REFCLK by a minimum phase
delay, FOUT2 will lag REFCLK by a minimum
phase delay, FOUT3 will phase-lag REFCLK by
90°, HFOUT will be phase-aligned with REFCLK
but at half the frequency, and X2FOUT will be ei-
ther phase-aligned at the same frequency as the
reference clock if DIVSEL = 0, or at twice the fre-
quency if DIVSEL = 1.
t = 1 / VCO freq
Since the VCO can operate in the 160 MHz to
320 MHz range, minimum phase delay values can
range from 6.25 ns to 3.125 ns. Table 1 shows vari-
ous FOUT/VCO frequencies and the associated
phase resolution.
The PHSEL1 and PHSEL0 inputs allow the user to
select several phase relationships among the four
FOUT0–FOUT3 TTL clock outputs. These choices
can be seen in Table 2, and the Output Select
Matrix provided in Table 3 describes the 21 output
configurations available to the user. The two “Se-
lect Pins” columns specify the signal levels on the
pins PHSEL0 and PHSEL1. These are active High
signals. The column entitled “Output Fed to
FBCLK” indicates which output (FOUT0–FOUT3,
Several other waveform examples and typical appli-
cations are provided on pages 7-8 and 7-9.
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
Page 2
BiCMOS PLL CLOCK GENERATOR
S4402/S4403
Enabling Outputs
Power Supply Considerations
The S4402 has two output-enable inputs that con-
trol which outputs toggle. (The S4403 has three
output-enable inputs.) When held LOW, OUTEN0
controls the frequency doubler output X2FOUT
and the half-frequency output HFOUT. OUTEN1
controls the FOUT0–FOUT3 outputs. The third in-
put on the S4403, OUTEN2, controls the duplicate
set of four outputs FOUT0A–FOUT3A. When an
output enable pin is held High, its associated out-
puts are disabled and held in a High state.
Power for the analog portion of the S4402/S4403
chips must be isolated from the digital power supplies
to minimize noise on the analog power supply pins.
This isolation between the analog and digital power
supplies can be accomplished with a simple external
power supply filter (Figure 3). The analog power
planes are connected to the digital power planes
through single ferrite beads (FB1 and FB2) or induc-
tors capable of handling 25 mA. The recommended
value for the inductors is in the range from 5 to
100µH, and depends upon the frequency spectrum of
the digital power supply noise. The ferrite beads
should exhibit 75Ω impedance at 10 MHz.
Filter
The FILTER output is a tap between the analog out-
put of the phase detector and the VCO input. This pin
allows a simple external filter (Figure 2) to be in-
cluded in the PLL. AMCC recommends the use of the
filter component values shown. This filter was chosen
for its ability to reduce the output jitter and filter out
noise on the REFCLK input. The filter components
should be in surface mounted packages with mini-
mum lead inductance.
Decoupling capacitors are also very important to mini-
mize noise. The decoupling capacitors must have low
lead inductance to be effective, so ceramic chip ca-
pacitors are recommended. Decoupling capacitors
should be located as close to the power pins as physi-
cally possible. And the decoupling should be placed
on the top surface of the board between the part and
its connections to the power and ground planes.
Figure 3. External Power Supply Filter
Figure 2. External PLL Filter
20
FB1
A +5V
A VCC
DIGITAL +5V
ANALOG +5V
0.1µF
10 µF
Tantalum
(optional)
0.1 µF
S4402
1.5k Ω
19
FB2
FILTER
DIGITAL GND
ANALOG GND
Test Capabilities
Reset
When the RESET pin is pulled low, all the internal
states go to zero one clock cycle (from the VCO or
REFCLK in the test mode) before the outputs go low.
After the chip is reset, the PLL requires a
resynchronization time of ≤5ms before lock is again
achieved.
The TSTEN input puts the S4402/S4403 into a test
mode and allows users to bypass the VCO and pro-
vide their own clock through the REFCLK input.
When TSTEN is High, the VCO is turned off and the
REFCLK signal drives the divider/phase adjust cir-
cuitry, directly sequencing the outputs. The TSTEN
and REFCLK inputs join the divider circuitry after the
initial divide-by-two stage. Therefore, REFCLK is di-
vided by two in the divide-by-four mode and divided
by four in the divide-by-eight mode.
Lock Detect
A lock detect function is provided by the LOCK out-
put. When REFCLK and FBCLK are within 2–4 ns of
each other, the PLL is in lock, and the LOCK output
goes High.
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
Page 3
BiCMOS PLL CLOCK GENERATOR
S4402/S4403
PIN DESCRIPTIONS
Input Signals
Output Signals
REFCLK. Frequency reference supplied by the user
that, along with the output tied to the FBCLK input,
determines the frequency of the FOUT0–FOUT3 out-
puts. Also replaces the VCO output when TSTEN is
high (after first divide-by-two stage in divider phase
control logic). See TSTEN.
FILTER. A tap between the analog output of the
phase detector and the VCO input. Allows a simple
external filter (a single resistor and one capacitor) to
be included in the PLL.
X2FOUT. Provides a clock signal identical to the
FOUT0 output in the divide-by-four mode and twice
the FOUT0 frequency (maximum of 80 MHz) in the
divide-by-eight mode.
FBCLK. Feedback clock that, along with the
REFCLK input, determines the frequency of the
FOUT0–FOUT3 outputs. One output is selected to
feed back to this input. (See Table 3.)
FOUT0. Clock output.
FOUT1. Clock output.
FOUT2. Clock output.
FOUT3. Clock output.
DIVSEL. Controls the divider circuit that follows the
VCO. When DIVSEL is low, the VCO frequency is
divided by four. When DIVSEL is high, the VCO fre-
quency is divided by eight. (See Tables 1 and 3.)
HFOUT. Provides a clock signal in phase with the
FOUT0 output, but at half the FOUT0 frequency in
both the divide-by-four and divide-by-eight modes.
PHSEL0. This input, along with PHSEL1, allows se-
lection of the phase relationship among the four
FOUT0–FOUT3 outputs. See Tables 2 and 3 for the
selection choices.
LOCK. Goes high when REFCLK and FBCLK are
within 2–4 ns of each other, demonstrating that the
PLL is in lock.
PHSEL1. Along with PHSEL0, allows selection of the
phase relationship among the four FOUT0–FOUT3
outputs. See Tables 2 and 3 for the selection
choices.
FOUT0A. (S4403 only.) Clock output—duplicates
FOUT0.
OUTEN0. Active Low. Output enable signal that con-
trols which outputs toggle. Controls the frequency
doubler output (X2FOUT) and the half-frequency out-
put (HFOUT).
FOUT1A. (S4403 only.) Clock output—duplicates
FOUT1.
FOUT2A. (S4403 only.) Clock output—duplicates
FOUT2.
OUTEN1. Active Low. Output enable signal that con-
trols which outputs toggle. Controls the FOUT0–
FOUT3 outputs.
FOUT3A. (S4403 only.) Clock output—duplicates
FOUT3.
OUTEN2. (S4403 only.) Active Low. Controls the
duplicate set of outputs to FOUT0–FOUT3
(FOUT0A, FOUT1A, FOUT2A, AND FOUT3A).
RESET. Active Low. Initializes internal states for test
purposes.
TSTEN. Active High. Allows REFCLK to drive the
divider phase adjust circuitry, after the first divide-by-
two stage. Therefore, REFCLK is divided by two in
the divide-by-four mode, and divided by four in the
divide-by-eight mode, and used to directly sequence
the outputs.
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
Page 4
S4402/S4403
BiCMOS PLL CLOCK GENERATOR
Table 3. Output Select Matrix
Configuration
Number
Select Pins
Output Fed
to FBCLK
Output Phase Relationships
FOUT0 FOUT1 FOUT2 FOUT3 HFOUT
÷4
÷8
PHSEL1 PHSEL0
X2FOUT
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
FOUT0–FOUT3
HFOUT
0
2(0)
0/2
0
0
2(0)
0/2
Q
0
2(0)
0/2
2Q
Q
0
2(0)
0/2
3Q
2Q
Q
0/2
0
0
2(0)
4(0)
0
2
2(0)
3
X2FOUT (÷8)
FOUT0
0/4
4
0/2
0
2(0)
2(–Q)
5
FOUT1
–Q
–2Q
–3Q
2(0)
0/2
0
0
–Q/2
–2Q/2
–3Q/2
0
–Q
6
FOUT2
–Q
–2Q
2(Q)
Q/2
–t
0
–2Q 2(–2Q)
–3Q 2(–3Q)
7
FOUT3
–Q
2(2Q)
2Q/2
t
0
8
HFOUT
2(3Q)
3Q/2
Q
2(0)
4(0)
0
9
X2FOUT (÷8)
FOUT0
0/4
10
11
12
13
14
15
16
17
18
19
20
21
0/2
0
t
2(0)
2(t)
FOUT1
t
0
2t
Q+t
Q–t
0
t/2
FOUT2
–t
–2t
–Q–t
2(–t)
–t/2
t
0
–t/2
–Q/2
0
–t
2(–t)
2(–Q)
4(0)
0
FOUT3
–Q
2(0)
0/2
0
–Q+t
2(t)
t/2
–Q
2(0)
HFOUT
2(Q)
Q/2
3t
X2FOUT (÷8)
FOUT0
0/4
2t
0/2
0
2(0)
2(–t)
2(–2t)
2(–3t)
4(0)
0
FOUT1
–t
0
t
2t
–t/2
–2t/2
–3t/2
0
–t
FOUT2
–2t
–3t
2(0)
0/2
–t
0
t
–2t
–3t
2(0)
FOUT3
–2t
2(t)
t/2
–t
0
HFOUT
2(2t)
2t/2
2(3t)
3t/2
X2FOUT (÷8)
0/4
Notes: 1. “0” implies the output is aligned with REFCLK.
2. “t” implies the output lags REFCLK by a minimum phase delay.
3. “Q” implies the output lags REFCLK by 90° of phase
4. “–t” implies the output leads REFCLK by a minimum phase delay.
5. “–Q” implies the output leads REFCLK by 90° of phase.
6. “2( )” implies the output is at twice the frequency of REFCLK.
Legend
Table
entry
Table
entry
Table
entry
Waveform
Waveform
Waveform
REFCLK
2(0)
REFCLK
REFCLK
Q
2Q
–Q
0
t
0/2
4(0)
0/4
2t
–t
–t 0 t 2t
–90° 0° 90° 180°
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
Page 5
S4402/S4403
EXAMPLES
Figure 4. Configuration Examples
REFCLK
FOUT0
FBCLK = FOUT0
PHSEL1 = 0
PHSEL0 = 0
FOUT1
FOUT2
(a)
S4402
Input
REFCLK
PHSEL0
FOUT3
X2FOUT
HFOUT
FOUT0
Low
Low
PHSEL1 FOUT1
HFOUT
FOUT2
FOUT3
(DIVSEL = 0) X2FOUT
(DIVSEL = 1) X2FOUT
FBCLK
REFCLK
FOUT0
FBCLK = HFOUT
PHSEL1 = 0
PHSEL0 = 0
FOUT1
FOUT2
(b)
S4402
Input
FOUT3
X2FOUT
HFOUT
FOUT0
FOUT1
FOUT2
REFCLK
PHSEL0
PHSEL1
Low
Low
HFOUT
FOUT3
(DIVSEL = 0) X2FOUT
(DIVSEL = 1) X2FOUT
FBCLK
FBCLK = HFOUT
PHSEL1 = 1
REFCLK
FOUT0
PHSEL0 = 1
FOUT1
FOUT2
(c)
S4402
FOUT3
Input
REFCLK
X2FOUT
HFOUT
FOUT0
FOUT1
FOUT2
FOUT3
High
High
PHSEL0
PHSEL1
HFOUT
(DIVSEL = 0) X2FOUT
(DIVSEL = 1) X2FOUT
FBCLK
0 t 2t 3t
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
Page 6
BiCMOS PLL CLOCK GENERATOR
TYPICAL APPLICATIONS
S4402/S4403
The S4402/S4403 chips are designed to meet a
large variety of system clocking requirements. Sev-
eral typical applications are provided below.
Clock Outputs
at twice, equal to,
or half the
XTAL
REFCLK
S4402
Application 1. High-Frequency, Low-Skew Clock
Generation
input frequency
One of the most basic capabilities of the S4402/
S4403 devices is generating multiple phase-
aligned low-skew clocks at various multiples of the
input clock frequency. For example, in a multiple-
board system a half-frequency clock can be gener-
ated for use across the backplane, where it is
simpler to route a low-speed signal. This signal
can then be doubled on the boards, and synchro-
nization will be maintained.
Application 2. Low-Skew Clock Distribution
XTAL
REFCLK
S4402
REFCLK
One common problem in clocking high-speed sys-
tems is that of distributing several copies of a sys-
tem clock while maintaining low skew throughout
the system. The S4402/S4403 devices guarantee
low skew among all the clocks in the system, as
they have effectively zero delay between their in-
put and output signals, with an output skew of less
than 400 ps. The user can also adjust the phases
of the outputs in increments as small as 3.125 ns,
for load and trace length matching.
S4402
REFCLK
S4402
REFCLK
S4402
Application 3. Delay Compensation
REFCLK
S4402
Since the relative edges of the S4402/S4403 out-
puts can be precisely controlled, these chips can
be used to compensate for different delays due to
trace lengths or to internal chip delays, simplifying
board layout and bus timing. In the example
shown, the two ASICs have a difference of several
nanoseconds in their propagation delays. The
S4402s ensure that the output signals are aligned,
so that the data valid uncertainty on the com-
mon bus is minimized.
ASIC
Input
Clock
REFCLK
S4402
ASIC
Clock tree output
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
Page 7
BiCMOS PLL CLOCK GENERATOR
S4402/S4403
ABSOLUTE MAXIMUM RATINGS
Commercial
TTL Supply Voltage VCC (VEE = 0)
7.0 V
TTL Input Voltage (VEE = 0)
Operating Temperature
5.5 V
0°C to 70°C ambient
+ 130°C
Operating Junction Temperature TJ
Storage Temperature
–65°C to +150°C
RECOMMENDED OPERATING CONDITIONS
Commercial
Parameter
Min
Nom
Max
Units
TTL Supply Voltage (VCC)
Operating Temperature
4.75
5.0
—
5.25
V
0
70
°C
(ambient)
(ambient)
Junction Temperature
—
—
130
°C
DC CHARACTERISTICS
1
Symbol
Parameter
DC Test Conditions
Min
Typ
Max Units
Guaranteed input HIGH voltage for
all inputs
2
V
Input HIGH voltage
2.0
V
IH
Guaranteed input LOW voltage for
all inputs
2
V
Input LOW voltage
0.8
V
IL
V
V
Input clamp diode voltage
Output HIGH voltage
V
= Min, I = -18mA
IN
-0.8
-1.2
V
V
IK
CC
CC
3
I
I
I
= -12mA (COM)
2.4
2.0
OH
OH
OL
V
= Min
= Min
OH
OL
3
= -24mA (COM)
V
V
3
V
Output LOW voltage
Input HIGH current
V
CC
V
CC
V
CC
V
CC
= 24mA (COM)
0.5
-200
50
µA
µA
mA
OUTEN2
I
I
I
I
= Min, V = 2.4V
IN
IH
Other
Input HIGH current at max
Input LOW current
= Max, V = V
IN
1.0
I
CC
OUTEN2
Other
-500
-50
µA
µA
= Min, V = 0.5V
IN
IL
4
Output short circuit current
Static
V
V
V
= Max, V
= Max
= 0V
OUT
-100
70
mA
mA
mA
-25
OS
CC
I
I
COM
COM
CC
CC
CC
Total I
(Dynamic and Static)
= 25pF at 50 MHz
190
CC
LOAD
1. Typical limits are at 25°C, VCC = 5.0V.
2. These input levels should only be tested in a static, noise-free environment.
3. IOH/IOL values indicated are for DC test correlation. Actual dynamic currents are
significantly higher and are optimized to balance rise and fall times.
4. Maximum test duration is one second.
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
Page 8
S4402/S4403
BiCMOS PLL CLOCK GENERATOR
Table 4. AC Specifications
S4402/3-66
S4402/3-80
Symbol
Description
Min
Max
Min
Max
Units
fVCO
fREF
VCO Frequency
REFCLK Frequency
160
10
7.0
-1.0
0
266
66
160
10
6.0
-1.0
0
320
80
MHz
MHz
ns
MPWREF
tPE
REFCLK Minimum Pulse Width
Phase Error between REFCLK and FBCLK
Phase Error Difference from Part to Part1
Output Skew2
0
750
400
55
0
750
400
55
ns
tPED
tSKEW
tDC
ps
0
0
ps
Output Duty Cycle3
45
20
10
40
3.75
-250
2
45
20
10
40
3.125
-250
2
%
fFOUT
fHFOUT
f2XFOUT
tPS
FOUT Frequency4
66
80
MHz
MHz
MHz
ns
HFOUT Frequency4
33
40
2XFOUT Frequency4
66
80
Nominal Phase Shift Increment
Phase Shift Variation5
6.25
+250
7
6.25
+250
7
tPSJ
ps
tOFD
tOFE
tIRF
Tpd OUTEN0–2 to FOUTs, Disable
Tpd OUTEN0–2 to FOUTs, Enable
Input Rise/Fall Time
ns
2
7
2
7
ns
1
3
1
3
ns
tORF
tLOCK
tj
FOUT Rise/Fall Time6
0.5
1.5
5
0.5
1.5
5
ns
Loop Acquisition Time7
ms
ps
Clock Stability8
500
500
1. Difference in phase error between two parts at the same voltage, temperature and frequency.
2. Output skew guaranteed for equal loading at each output.
3. Outputs loaded with 35pF, measured at 1.5V.
4. CLOAD = 35 pF.
5. All phase shift increments and variation are measured relative to FOUT0 at 1.5V.
6. With 35 pF output loading (0.8 V to 2.0 V transition).
7. Depends on loop filter chosen. (Number given is for example filter.)
8. Clock period jitter with all FOUT outputs operating at 66 MHz and loaded with 25pF using loop filter
shown. Parameter guaranteed, but not tested.
Figure 5. Timing Waveforms
MPW
PE
MPW
REF
REF
REFCLK
FBCLK
t
t
PE
t
t
SKEW
SKEW
FOUT0–3
HFOUT, X2FOUT
FOUT0–3
Output
Valid
Disabled
HFOUT, X2FOUT
t
t
OFD
OFE
OUTEN0–2
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
Page 9
BiCMOS PLL CLOCK GENERATOR
S4402/S4403
• No dynamic signal lines should pass through or
beneath the filter circuitry area (enclosed by dashed
lines in Figure 6) to avoid the possibility of noise due
to crosstalk.
BOARD LAYOUT CONSIDERATIONS
• The S4402/S4403 chips are sensitive to noise on
the Analog +5 V and Filter pins. Care should be
taken during board layout for optimum results.
• The analog VCC supply can be a filtered digital
VCC supply as shown below. The ferrite beads or
inductors, FB1 and FB2, should be placed within
three inches of the chip.
• All decoupling capacitors (C1–C4 = 0.1 µF) should
be bypassed between VCC and GND, and placed as
close to the chip as possible (preferably using ce-
ramic chip caps) and placed on top of board between
S4402/S4403 and the power and ground plane con-
nections.
• The analog VCC plane should be separated from
the digital VCC and ground planes by at least 1/8
inch.
Figure 6. Board Layout (S4402 shown)
+5
D
C2
3
2
1
28 27 26
25
4
5
6
A GND
24
FB2
7
8
9
23
22
21
C3
C1
C6
GND
D
10
11
20
19
16
17 18
FB1
R1
12
14 15
13
+5
+5
A
+5
D
D
C4
No signals should pass through
the area enclosed by dashed lines
Component
C1–C4
C6
Description
0.1 µF ceramic capacitor
0.1 µF ceramic capacitor
1.5 K 10% resistor
R1
FB1,FB2
Ferrite bead or inductor
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
Page 10
S4402/S4403
BiCMOS PLL CLOCK GENERATOR
Figure 7. S4402 28 PLCC Package and Pinout
2
1
28
26
3
27
4
5
6
7
25
24
23
D +5V
DIVSEL
PHSEL0
FOUT2
D +5V
DGND
FOUT1
PHSEL1
S4402A
GND-ANALOG
+5V ANALOG
8
22
21
20
19
9
FOUT0
D +5V
10
11
+5V ANALOG
FILTER
12
16 17 18
14 15
13
All dimensions nominal in inches.
28 PLCC Thermal Resistance
Still Air
100 Linear Ft./Min
50˚C/Watt
200 Linear Ft./Min
60˚C/Watt
45˚C/Watt
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
Page 11
S4402/S4403
BiCMOS PLL CLOCK GENERATOR
Figure 8. S4403 44 PLCC Package and Pinout
6
5
4
3
44 43
41 40
42
2
1
D +5V
39
7
8
D +5V
FOUT2A
FOUT2
NC
38
DIVSEL
PHSEL0
PHSEL1
NC
37
36
35
9
10
11
D +5V
S4403B
34
33
GND-ANALOG
+5V ANALOG
+5V ANALOG
FILTER
DGND
12
13
FOUT1A
FOUT1
FOUT0A
32
31
30
29
14
15
16
17
NC
FOUT0
D +5V
D +5V
24
23
22
25 26 27 28
21
18 19 20
All dimensions nominal in inches.
Ordering Information
AMCC clock driver products are available in several output skew and shipping configurations.
The order number is formed by a combination of:
• Device Number
• Package Type
• Speed Option
• Optional Shipping Configuration
S4402/03
A
– 66
/TD
Optional Shipping Configuration
Blank = tube
/D = dry pack
/TD = tape, reel and dry pack
Speed Option
– 66 = 66 MHz
– 80 = 80 MHz
Package Option
A = 28-pin PLCC (S4402)
B = 44-pin PLCC (S4403)
Device Number
S4402
S4403
Example:
S4402A-66/D
28-pin PLCC package, shipped dry packed in the standard tube.
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
Page 12
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121
•
(619) 450-9333
AMCC reserves the right to change specifications for this product in any manner without notice,
and substitute devices manufactured to higher grade levels than ordered.
AMCC is a registered trademark of Applied Micro Circuits Corporation.
Copyright ® 1996 Applied Micro Circuits Corporation
Printed in U.S.A./01-03-96
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