SC3318S-1/D [AMCC]
Low Skew Clock Driver, SC33 Series, 10 True Output(s), 0 Inverted Output(s), BICMOS, PDSO28, SOIC-28;
| 型号： | SC3318S-1/D |
| 厂家： | 
APPLIED MICRO CIRCUITS CORPORATION |
| 描述： | Low Skew Clock Driver, SC33 Series, 10 True Output(s), 0 Inverted Output(s), BICMOS, PDSO28, SOIC-28 驱动 信息通信管理 光电二极管 逻辑集成电路 |
| 文件： | 总8页 (文件大小：114K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
DEVICE SPECIFICATION
SC3318/68
10 AND 14-OUTPUT LVTTL CLOCK DRIVERS
FEATURES
APPLICATIONS
• Ten or fourteen clock outputs
• Datacom and Telecom networks
– Outputs operate at frequencies up to 80 MHz
– Outputs grouped in two banks of five outputs
on SC3318
• Compatible with PowerPC™ processors
• PCI Bus clock distribution
• Workstation and server systems with
high clock fanout
– Outputs grouped in a bank of six and a bank of
eight outputs on the SC3368
• Compatible with Intel’s Pentium™ and
Pentium Pro™ processors
• All outputs are leading-edge synchronized
to within ≤0.5 ns
• Proprietary output drivers with:
– Complementary 24 mA peak outputs,
source and sink
– 65–75Ω source series termination
– Dynamic drive adjustment to match load
conditions
– Edge rates less than 1.5 ns
• Output levels comply with JEDEC LVTTL
standard
GENERAL DESCRIPTION
The SC3318 and SC3368 are minimum skew clock
drivers with ten or fourteen outputs. They employ a
clock input from a single-ended TTL or an ECL differ-
ential source operating between +5V and ground.
This reference frequency input is received and distrib-
uted to the clock output drivers. All outputs are
“clamped” to conform with JEDEC LVTTL levels.
Applied Micro Circuits Corporation (AMCC) uses
proprietary complementary (source and sink) 24 mA
peak output drivers. In addition to their drive capability,
these circuits provide “source (series) termination” at
the TTL outputs that minimize over/undershoot without
requiring on-board termination networks. They are
designed for a maximum output slew rate of ≈1.5V/ns
to minimize simultaneous output-switching noise and
distortion.
• +5V VCC Supply
• 28 SOIC package
• Minimizes the ground-bounce, overshoot,
and ringing problems often encountered
when using CMOS and Bipolar drivers
SC3318 Logic Diagram
There are no Fa outputs on the SC3318
5
LVTTL
+Vcc
Fb
Fc
TA
DRIVER
20K
RESET
R
S - R
R
R
R
PECL
TTL
M
U
X
5
LVTTL
TA
DRIVER
CLOCK SEL
+5V
GND
Applied Micro Circuits Corporation
6290 Sequence Dr., San Diego, CA 92121-4358
1
SC3318/68
10 AND 14-OUTPUT LVTTL CLOCK DRIVERS
SC3368 Logic Diagram
There are no Fa outputs on the SC3368
6
LVTTL
TA
Fc
DRIVER
F
F
S
TTLOSC1
R
LC
F/2
+VCC
TFF
M
RESET
R
S - R
M
U
X
8
LVTTL
TA
Fb
DRIVER
F
F
TTLOSC0
LC
R
R
CLOCK SEL
SC3318/68 Product Selection Guide
Output Frequency
with Respect to Input Frequency
Total
Number of
Number of
P/N
Outputs
Outputs ÷ 1
Outputs ÷ 2
Special Features
Package
SC3318
10
14
10
6
N/A
8
28 SOIC
28 SOIC
Selectable single or
dual clock input.
SC3368
AC Test/Evaluation Circuit
Vcc = +5.0V
10
10
10
10
10
10
SC33XX
C
load
5
2.0
2.0
2.0
2.0
2.0
2.0
10
~6 INCHES of 70 OHM P.C.B.
NOTES: All inductance is in nH. Capacitance is in pF.
At frequencies above 50 MHz, a single point load destination is recommended.
Applied Micro Circuits Corporation
2
6290 Sequence Dr., San Diego, CA 92121-4358
10 AND 14-OUTPUT LVTTL CLOCK DRIVERS
SC3318/68
Absolute Maximum Ratings
Capacitance (package and die total)
Storage Temperature......................... -55° to +150°C
VCC Potential to Ground ..................... -0.5V to +7.0V
Input Voltage........................................ -0.5V to +VCC
Static Discharge Voltage ...............................>1750V
Maximum Junction Temperature ................... +140°C
Latch-up Current ..........................................>200 mA
Operating Ambient Temperature ............ 0° to +70°C
Input Pins ......................................................... 5.0 pF
TTL Output Pins............................................... 5.0 pF
Electrical Characteristics
VCC = +5.0V ± 5%, Ta = 0°C to + 70°C (reference “AC Test/Evaluation Circuit”)
Symbol
Parameter
Conditions
Min
Max
Unit
VIH
Input HIGH Voltage (PECL)
Input HIGH Voltage (TTL)
Input LOW Voltage (PECL)
Input LOW Voltage (TTL)
Input HIGH Current (PECL)
CLKSEL
RESET
TTL
Input LOW Current (PECL)
CLKSEL
RESET
Differential Source–PECL
All TTL Inputs
Differential Source–PECL
All TTL Inputs
VIN = VCC (max)
VIN = VCC (max)
VIN = 2.4V
VIN = 2.4V
VIN = VCC -2.0V
VIL +0.4
2.0
VCC -2.0 VIH -0.4
+VCC
VCC + 0.3
V
V
V
VIL
IIH
-0.5
0.8
200
350
-200
15
15
25
-325
15
3.65
0.4V
V
uA
uA
uA
uA
uA
uA
uA
uA
V
IIL
V
IN = 0.4V
VIN = 0.5V
VIN = 0.4V
TTL
VOH
VOL
Output HIGH Voltage
Output LOW Voltage
Output HIGH Short Ckt Current
Output LOW Short Ckt Current
Static Core Power Dissipation
FOUT = 80MHz, CL = 10pF
FOUT = 80MHz, CL = 10pF
Output High, VOUT = 0V Typ
Output Low, VOUT = VCC Typ
SC3318, 70°, Typ Pwr=340mW
SC3327, 70˚, Typ Pwr=290mW
SC3367, 70˚, Typ Pwr=250mW
SC3368, 70˚, Typ Pwr=250mW
2.3
V
1
IOHS
-45
55
mA
mA
mW
mW
mW
mW
1
IOLS
PWR
550
475
400
400
1. Maximum test duration, one second.
2. The SC3318/68 features source series termination of approximately
40 Ohms to assist in matching 65–75 Ohm P.C. board environments.
3. Maximum VOH level is specified at 60˚C and must be derated by 10mV/˚C for T > 60˚C.
a
PECL Differential Input Voltage Range
DC Characteristics
The outputs have been designed specifically for
clock distribution. In the development of this product,
AMCC has made several trade-offs between the his-
toric “high-drive, totem-pole outputs” and AMCC’s
dynamically adjusting source series terminated out-
puts. As a result of this, the output will dynamically
source and sink a symmetrical 24 mA of current. In a
DC state, it exhibits the following specifications:
+V
CC
V
V
IH
IH
INPUT DIFFERENTIA
V
L
V
≥ 400mV
ID
V
IL
IL
V
-2.0V
CC
Conditions
Min
Max
VOH
VOL
IOH = -2mA
IOL = 2mA
2.1V
0.6V
Applied Micro Circuits Corporation
3
6290 Sequence Dr., San Diego, CA 92121-4358
SC3318/68
10 AND 14-OUTPUT LVTTL CLOCK DRIVERS
AC Specifications—Using “AC Test/Evaluation Circuit”
VCC = +5.0V ± 5%, Ta = 0°C to 70°C, CLOAD = 10pF
Parameter
SC3318
SC3368
Units
Maximum Skew Across Fb Outputs
250
500
ps
Maximum Skew Across Fc Outputs
250
250
500
ps
ps
Maximum Skew Across Fb and Fc Outputs,
CLKSEL=0
Maximum Skew Across All Outputs
Options:
Standard
–1
—
0.5
ns
Delay of Fb from Fc outputs (CLKSEL = 1)
[Tdly or Tcb]
Typ. 0.5
Max. 1.0
ns
ns
ns
ns
ns
—
Delay of Fc from Fd outputs
[Tdc]
—
Min. 45%
Max. 55%
80
Maximum Output Duty Cycle Asymmetry
%
Maximum TTL Input Frequency
Maximum TTL Output Frequency
80
80
80
1.5
MHz
MHz
MHz
ns
80
Maximum PECL Differential Input Frequency
Maximum Rising/Falling Edge Rate
Notes:
1.5
1. Skew is referenced to the rising and falling edges of all outputs.
2. Output Duty Cycle Asymmetry is defined as the duty cycle deviation from 50%, measured at
1.5V. Output Duty Cycle will also be affected by voltage and load (including the length of the PC
trace).
3. Typical skew derating factor for different loads is 50ps/pF at 1.5V threshold. For example, a 5pF
load difference equals a 250 ps skew difference.
4. Edge rates are measured from 0.8V to 2.0V. Load consists of a 6" board trace (70 Ohm) with a
10 pF capacitive load. See “AC Test/Evaluation Circuit.” Synchronous outputs may be paralleled
for high loads.
5. Parameters guaranteed by design and characterization or tested.
Threshold Crossing Characteristics
50% ± 10%
0.5ns
MINIMUM
Vih-0.3V
ECL
DIFFERENTIAL
INPUTS
Vil+0.3V
MINIMUM
0.5ns
50% ± 5%
CLOCK
OUTPUT
+2.0V
+1.5V
+2.0V
+1.5V
+0.8V
+0.8V
T rise
1.5ns
1.5ns
T fall
NOTE: Trise and Tfall are “real load” dependent. The values indicated are for 6" of
board trace (70 Ohm) with a 10 pF capacitive load. See the Clock Driver Application Note.
Applied Micro Circuits Corporation
6290 Sequence Dr., San Diego, CA 92121-4358
4
10 AND 14-OUTPUT LVTTL CLOCK DRIVERS
SC3318/68
DESCRIPTION OF OPERATION
(Refer to Logic Diagram)
AMCC has developed ten and fourteen-output clock
buffer drivers using AMCC’s advanced BiCMOS pro-
cess. These designs have been optimized for mini-
mum skew across all outputs.
The output drivers are rise and fall slew rate con-
trolled to ~1.5V/ns to minimize noise and distortion
resulting from simultaneous switching of the outputs.
These outputs also feature series termination (~40
Ohms) to significantly reduce the overshoot and un-
dershoot of non-terminated transmission lines. This
will satisfy printed circuit line impedances of 65 to 75
Ohms terminated into 15 pF (two IC input package
receiver pins). When applications require large load
capacitance (>25pF with 50 Ohm P.C. board imped-
ance at higher frequencies) and/or large peak volt-
age amplitudes, two adjacent drivers may be
paralleled, thereby halving the series resistance
and doubling the peak current (see the Clock
Driver Application Note for spice models).
The clock source input for these devices may oper-
ate between +5V and ground and can provide ei-
ther differential ECL inputs (referenced to +5V,
PECL) or single-ended TTL (CMOS) input levels to
AMCC’s Clock Drivers. This selection is accom-
plished by use of the CLKSEL pin (on the SC3318),
where logic LOW (or “float”) selects TTL and logic
HIGH selects PECL. On the SC3368, CLKSEL
chooses the source of the clock for the Fb outputs.
When CLKSEL is low the TTLOSC0 input drives the
Fb outputs and when CLKSEL is high a divide-by-
two version of the TTLOSC1 input drives the Fb out-
puts. This input clock will be fanned out to translation
amplifiers and output drivers, refer to the Logic Dia-
grams. The output duty factor asymmetry becomes
largely a function of the input clock waveshape and
the output driver slew rate into the AC load.
Power and ground are interdigitated with the outputs.
Of the 28 package pins, 10 are used for low impedance
on-chip power distribution. Due to the simultaneous
switching of outputs, low impedance +VCC and ground
planes within the P.C. board are recommended, as well
as substantial decoupling capacitance (see the Clock
Driver Application Note for recommendations).
The RESET input is provided to hold off or clear the
outputs, as may be required by the user’s system.
This pin may be logically driven from a TTL output.
Optionally, if a capacitor (4.7uF = ~100ms) is con-
nected between this pin and ground, the device will
respond with a “power up reset”—a delay in the
clock outputs becoming active. At the onset of RE-
SET (low) the outputs will go low following four fall-
ing edge clock inputs (three falling edge clock inputs
for the SC3368). At the expiration of RESET (high)
the outputs will resume after four falling edge clock
inputs (three falling edge clock inputs for the
SC3368), from a high (leading edge) count origin.
The reset function is only operational when
CLKSEL=1.
The IC package and die layouts are tightly coupled
to assure precise matching of all of the outputs.
Collectively, the resistance, inductance, and capacitance
of the package and wire bonding is managed to
insure that the clock drivers will exhibit skews less
than the specified maximum. A plastic 28-lead
small outline package with .050" lead pitch is em-
ployed with an outer lead rectangular footprint of
approximately 0.7" by 0.4".
Applied Micro Circuits Corporation
5
6290 Sequence Dr., San Diego, CA 92121-4358
SC3318/68
10 AND 14-OUTPUT LVTTL CLOCK DRIVERS
SC3368 Application Examples
Example 1.
Example 2.
Low Skew, Single Reference Frequency Mode
Dual Reference Frequency Mode, Asynchronous
Six outputs at the primary frequency and eight
outputs at half the primary frequency; each group
internally synchronized. The 33 MHz outputs are
delayed from the 66 MHz outputs by ≈500 ps.
Six outputs at the primary frequency and eight
outputs at the secondary frequency.
66 MHz
50 MHz
F
66 MHz
F
50 MHz
33 MHz
TTLOSC1
TTLOSC1
c
c
SC3368
SC3368
33 MHz
TTLOSC0
33 MHz with
≈500ps delay
from 66 MHz
F
F
b
b
CLKSEL = 1
CLKSEL = 0
Example 3.
Single Reference Frequency Mode, Synchronous
All fourteen outputs will follow the input reference
with a maximum skew of 500 ps across all outputs.
TTLOSC1
F
c
66 MHz
SC3368
66 MHz
TTLOSC2
F
b
CLKSEL = 0
Applied Micro Circuits Corporation
6290 Sequence Dr., San Diego, CA 92121-4358
6
10 AND 14-OUTPUT LVTTL CLOCK DRIVERS
SC3318/68
Power Management
The overall goal of managing the power dissipated by
the clock driver is to limit its junction (die) temperature
to 140°C. A major component of the power dissipated
internally by the clock driver is determined by the load
that each output drives and the frequency that each
output is running. The “Output Power Dissipation”
table summarizes these dependencies (see “AC Test/
Evaluation Circuit”, for complete load definition).
For example: An application utilizes an clock driver
with 8 outputs driving 10 pF loads at 66 MHz. Total
chip power is calculated as follows:
Core Power (SC3318)
= 550 mW
8 outputs, 10 pF, 66 MHz = (8 x 33 mW) = 264 mW
2 outputs, no load, 66 MHz = (2 x 11 mW) = 22 mW
Total Power = 836 mW
The output power must be added to the core power
(550 mW) of the clock driver to determine the total
power being dissipated by the clock driver. This total
power is then multiplied by the clock driver’s thermal
resistance, with the result being added to the ambient
temperature to determine the junction temperature of
the clock driver. For greatest reliability, this junction
temperature should not exceed 140°C. The thermal
resistance for the clock driver is detailed in the 28-pin
SOIC Thermal Dissipation vs. Airflow graph in the
Package appendix at the end of this section.
The design specifies a 70˚C still air ambient. Refer-
ring to the 28-pin SOIC Thermal Dissipation vs.
Airflow graph in the Package appendix, the Θ for
ja
still air is 57.7˚C/watt. The clock driver’s junction
temperature would then be:
70˚C + (0.836 watts x 57.7˚C/watt) = 118˚C
Note this is below the 140˚C maximum junction
temperature.
Output Power Dissipation
FREQUENCY CLOAD=5pF CLOAD=10pF CLOAD=15pF CLOAD=25pF NO LOAD
80 MHz
66 MHz
50 MHz
40 MHz
33 MHz
25 MHz
20 MHz
29 mW
27 mW
20 mW
18 mW
13 mW
11 mW
10 mW
36 mW
33 mW
23 mW
21 mW
15 mW
13 mW
11 mW
43 mW
39 mW
27 mW
25 mW
17 mW
14 mW
13 mW
62 mW
53 mW
42 mW
36 mW
32 mW
22 mW
17 mW
13 mW
11 mW
10 mW
9 mW
8 mW
8 mW
7 mW
SC3318 Pinout
SC3368 Pinout
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
FB4
FB5
FB3
1
28
GND
FC3
FC2
VCC
FC1
GND
FC0
N/C
2
FB2
VCC
FB1
GND
FB0
TTLOSC0
GND
VCC
FC5
VCC
FC4
2
3
27
26
3
VCC
4
VCC
TTLOSC1
FB6
4
5
25
24
FC4
5
PECLOSCN
6
23
22
PECLOSCP
TTLOSC
6
7
7
N/C
FB7
N/C
8
CLKSEL
RESET
GND
21
20
CLKSEL
RESET
GND
8
9
VCC
FB0
VCC
9
19
18
10
11
12
13
14
10
11
FB4
FC0
VCC
FC1
FC2
17
16
15
FB1
GND
FB2
GND
FB3
12
13
FC3
GND
VCC
14
Applied Micro Circuits Corporation
6290 Sequence Dr., San Diego, CA 92121-4358
7
SC3318/68
10 AND 14-OUTPUT LVTTL CLOCK DRIVERS
Ordering Information
AMCC clock driver products are available in several output skew and shipping configurations.
The order number is formed by a combination of:
• Device Number
• Package Type
• Skew Option (if applicable)
• Optional Shipping Configuration
SC33XX
S
– 1
/TD
Optional Shipping Configuration
Blank = 25-unit tube
/D = dry pack
/T = tape, reel and dry pack
Skew Option
Blank = standard output-output skew
– 1 = 500 ps output-output skew
Package Option
S = 28-pin Small Outline Integrated Circuit (SOIC)
Device Number
Example: SC33XXS–1/D
28-pin SOIC package, 500 ps output-output skew,
shipped dry packed in the standard tube.
Part Number
SC3318
Standard
–1
✔
N/A
SC3368
✔
N/A
Applied Micro Circuits Corporation • 6290 Sequence Dr., San Diego, CA 92121
Phone: (619) 450-9333 • (800) 755-2622 • Fax: (619) 450-9885
http://www.amcc.com
AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and
advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied
on is current.
AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it
convey any license under its patent rights nor the rights of others.
AMCC reserves the right to ship devices of higher grade in place of those of lower grade.
AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR
USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
AMCC is a registered trademark of Applied Micro Circuits Corporation.
Copyright ® 1997 Applied Micro Circuits Corporation
June 25, 1997
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