AM27C020-90DC5 [AMD]
2 Megabit (256 K x 8-Bit) CMOS EPROM; 2兆位（ 256千×8位） CMOS EPROM
| 型号： | AM27C020-90DC5 |
| 厂家： | 
AMD |
| 描述： | 2 Megabit (256 K x 8-Bit) CMOS EPROM |
| 文件： | 总12页 (文件大小：165K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FINAL
Am27C020
2 Megabit (256 K x 8-Bit) CMOS EPROM
DISTINCTIVE CHARACTERISTICS
■ Fast access time
■ Single +5 V power supply
— Speed options as fast as 55 ns
■ Low power consumption
■ ±10% power supply tolerance standard
■ 100% Flashrite™ programming
— Typical programming time of 32 seconds
— 100 µA maximum CMOS standby current
■ JEDEC-approved pinout
■ Latch-up protected to 100 mA from –1 V to
VCC + 1 V
— Plug in upgrade of 1 Mbit EPROM
— Easy upgrade from 28-pin JEDEC EPROMs
■ High noise immunity
■ Compact 32-pin DIP, PDIP, and PLCC packages
GENERAL DESCRIPTION
The Am27C020 is a 2 Megabit, ultraviolet erasable pro-
grammable read-only memory. It is organized as 256
Kwords by 8 bits per word, operates from a single +5 V
supply, has a static standby mode, and features fast
single address location programming. Products are
available in windowed ceramic DIP packages, as well
as plastic one time programmable (OTP) PDIP and
PLCC packages.
thus eliminating bus contention in a multiple bus micro-
processor system.
AMD’s CMOS process technology provides high
speed, low power, and high noise immunity. Typical
power consumption is only 100 mW in active mode,
and 100 µW in standby mode.
All signals are TTL levels, including programming sig-
nals. Bit locations may be programmed singly, in
blocks, or at random. The device supports AMD’s
Flashrite programming algorithm (100 µs pulses), re-
sulting in a typical programming time of 32 seconds.
Data can be typically accessed in less than 55 ns, al-
lowing high-performance microprocessors to operate
without any WAIT states. The device offers separate
Output Enable (OE#) and Chip Enable (CE#) controls,
BLOCK DIAGRAM
V
Data Outputs
DQ0–DQ7
CC
V
V
SS
PP
Output Enable
Chip Enable
and
OE#
CE#
Output
Buffers
Prog Logic
PGM#
Y
Y
Gating
Decoder
A0–A17
Address
Inputs
2,097,152
Bit Cell
Matrix
X
Decoder
11507H-1
Publication# 11507 Rev: H Amendment/0
Issue Date: May 1998
PRODUCT SELECTOR GUIDE
Family Part Number
Am27C020
V
V
= 5.0 V ± 5%
= 5.0 V ± 10%
-55
55
55
55
35
-75
-70
70
-255
CC
Speed Options
-90
90
90
40
-120
120
120
50
-150
150
150
65
-200
200
200
75
CC
Max Access Time (ns)
CE# (E#) Access (ns)
OE# (G#) Access (ns)
250
250
100
70
40
CONNECTION DIAGRAMS
Top View
DIP
PLCC
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
VPP
A16
A15
A12
A7
2
PGM# (P#)
A17
3
4
3
2
1 32 31 30
4
A14
A7
A6
5
6
A14
29
5
A13
A13
28
A6
6
A8
A5
A4
A3
A2
A1
A0
7
A8
27
26
25
24
23
22
21
A5
7
A9
8
A9
A4
8
A11
9
A11
A3
9
OE# (G#)
A10
10
11
12
13
OE# (G#)
A10
A2
10
11
12
13
14
15
16
A1
CE# (E#)
DQ7
CE# (E#)
DQ7
A0
DQ0
DQ0
DQ6
16 17
19 20
18
15
14
DQ1
DQ2
VSS
DQ5
DQ4
DQ3
11507H-3
11507H-2
Notes:
1. JEDEC nomenclature is in parenthesis.
2. The 32-pin DIP to 32-pin PLCC configuration varies from the JEDEC 28-pin DIP to 32-pin PLCC configuration.
PIN DESIGNATIONS
LOGIC SYMBOL
A0–A17
= Address Inputs
CE# (E#)
= Chip Enable Input
18
DQ0–DQ7 = Data Input/Outputs
OE# (G#) = Output Enable Input
PGM# (P#) = Program Enable Input
8
A0–A17
DQ0–DQ7
CE# (E#)
PGM# (P#)
OE# (G#)
VCC
VPP
VSS
= VCC Supply Voltage
= Program Voltage Input
= Ground
11507H-4
2
Am27C020
ORDERING INFORMATION
UV EPROM Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of the following:
5
AM27C020
-55
D
C
B
OPTIONAL PROCESSING
Blank = Standard Processing
B
= Burn-In
VOLTAGE TOLERANCE
= V ± 5%, 55 ns only
5
CC
See Product Selector Guide and Valid Combinations
TEMPERATURE RANGE
C
I
E
= Commercial (0°C to +70°C)
= Industrial (–40°C to +85°C)
= Extended (–55°C to +125°C)
PACKAGE TYPE
= 32-Pin Ceramic DIP (CDV032)
D
SPEED OPTION
See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION
Am27C020
2 Megabit (256 K x 8-Bit) CMOS UV EPROM
Valid Combinations
Valid Combinations list configurations planned to be sup-
ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
Valid Combinations
AM27C020-55
= 5.0 V ± 5%
DC5, DC5B, DI5, DI5B
V
CC
AM27C020-55
= 5.0 V ± 10%
V
CC
DC, DCB, DI, DIB
AM27C020-70
AM27C020-90
AM27C020-120
AM27C020-150
AM27C020-200
AM27C020-255
DC, DCB, DI, DIB, DE, DEB
DC, DCB, DI, DIB
V
= 5.0 V ± 5%
CC
Am27C020
3
ORDERING INFORMATION
OTP EPROM Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of the following:
5
AM27C020
-55
J
C
OPTIONAL PROCESSING
Blank = Standard Processing
VOLTAGE TOLERANCE
5
= V ± 5%, 55 ns only
CC
See Product Selector Guide and Valid Combinations
TEMPERATURE RANGE
C
I
= Commercial (0°C to +70°C)
= Industrial (–40°C to +85°C)
PACKAGE TYPE
P
J
= 32-Pin Plastic DIP (PD 032)
= 32-Pin Plastic Leaded Chip Carrier (PL 032)
SPEED OPTION
See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION
Am27C020
2 Megabit (256 K x 8-Bit) CMOS OTP EPROM
Valid Combinations
Valid Combinations list configurations planned to be sup-
ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
Valid Combinations
AM27C020-55
PC5, PI5, JC5, JI5
V
= 5.0 V ± 5%
CC
AM27C020-55
= 5.0 V ± 10%
V
CC
AM27C020-75
AM27C020-90
AM27C020-120
AM27C020-150
AM27C020-200
AM27C020-255
JC, PC, JI, PI
V
= 5.0 V ± 5%
CC
4
Am27C020
FUNCTIONAL DESCRIPTION
Device Erasure
VPP = 12.75 V ± 0.25 V and PGM# LOW, and OE#
HIGH will program that particular device. A high-level
CE# input inhibits the other devices from being pro-
grammed.
In order to clear all locations of their programmed con-
tents, the device must be exposed to an ultraviolet light
source. A dosage of 15 W seconds/cm2 is required to
completely erase the device. This dosage can be ob-
tained by exposure to an ultraviolet lamp—wavelength
of 2537 Å—with intensity of 12,000 µW/cm2 for 15 to 20
minutes. The device should be directly under and about
one inch from the source, and all filters should be re-
moved from the UV light source prior to erasure.
Program Verify
A verification should be performed on the programmed
bits to determine that they were correctly programmed.
The verify should be performed with OE# and CE#, at
VIL, PGM# at VIH, and VPP between 12.5 V and 13.0 V.
Autoselect Mode
Note that all UV erasable devices will erase with light
sources having wavelengths shorter than 4000 Å, such
as fluorescent light and sunlight. Although the erasure
process happens over a much longer time period, ex-
posure to any light source should be prevented for
maximum system reliability. Simply cover the package
window with an opaque label or substance.
The autoselect mode provides manufacturer and de-
vice identification through identifier codes on DQ0–
DQ7. This mode is primarily intended for programming
equipment to automatically match a device to be pro-
grammed with its corresponding programming algo-
rithm. This mode is functional in the 25°C ± 5°C
ambient temperature range that is required when pro-
gramming the device.
Device Programming
Upon delivery, or after each erasure, the device has
all of its bits in the “ONE”, or HIGH state. “ZEROs” are
loaded into the device through the programming pro-
cedure.
To activate this mode, the programming equipment
must force VH on address line A9. Two identifier bytes
may then be sequenced from the device outputs by tog-
gling address line A0 from VIL to VIH (that is, changing
the address from 00h to 01h). All other address lines
must be held at VIL during the autoselect mode.
The device enters the programming mode when 12.75
V ± 0.25 V is applied to the VPP pin, and CE# and
PGM# are at VIL and OE# is at VIH.
Byte 0 (A0 = VIL) represents the manufacturer code,
and Byte 1 (A0 = VIH), the device identifier code. Both
codes have odd parity, with DQ7 as the parity bit.
For programming, the data to be programmed is ap-
plied 8 bits in parallel to the data pins.
The flowchart in the Programming section of the
EPROM Products Data Book (Section 5, Figure 5-1)
shows AMD’s Flashrite algorithm. The Flashrite algo-
rithm reduces programming time by using a 100 µs pro-
gramming pulse and by giving each address only as
many pulses to reliably program the data. After each
pulse is applied to a given address, the data in that ad-
dress is verified. If the data does not verify, additional
pulses are given until it verifies or the maximum pulses
allowed is reached. This process is repeated while se-
quencing through each address of the device. This part
of the algorithm is done at VCC = 6.25 V to assure that
each EPROM bit is programmed to a sufficiently high
threshold voltage. After the final address is completed,
Read Mode
To obtain data at the device outputs, Chip Enable (CE#)
and Output Enable (OE#) must be driven low. CE# con-
trols the power to the device and is typically used to se-
lect the device. OE# enables the device to output data,
independent of device selection. Addresses must be
stable for at least tACC–tOE. Refer to the Switching
Waveforms section for the timing diagram.
Standby Mode
The device enters the CMOS standby mode when CE#
is at VCC ± 0.3 V. Maximum VCC current is reduced to
100 µA. The device enters the TTL-standby mode
when CE# is at VIH. Maximum VCC current is reduced
to 1.0 mA. When in either standby mode, the device
places its outputs in a high-impedance state, indepen-
dent of the OE# input.
the entire EPROM memory is verified at VCC = VPP
5.25 V.
=
Please refer to Section 5 of the EPROM Products Data
Book for additional programming information and spec-
ifications.
Output OR-Tieing
To accommodate multiple memory connections, a
two-line control function provides:
Program Inhibit
Programming different data to multiple devices in par-
allel is easily accomplished. Except for CE#, all like in-
puts of the devices may be common. A TTL low-level
program pulse applied to one device’s CE# input with
■ Low memory power dissipation, and
■ Assurance that output bus contention will not occur.
Am27C020
5
CE# should be decoded and used as the primary de-
vice-selecting function, while OE# be made a common
connection to all devices in the array and connected to
the READ line from the system control bus. This as-
sures that all deselected memory devices are in their
low-power standby mode and that the output pins are
only active when data is desired from a particular mem-
ory device.
ing and falling edges of Chip Enable. The magnitude of
these transient current peaks is dependent on the out-
put capacitance loading of the device. At a minimum, a
0.1 µF ceramic capacitor (high frequency, low inherent
inductance) should be used on each device between
VCC and VSS to minimize transient effects. In addition,
to overcome the voltage drop caused by the inductive
effects of the printed circuit board traces on EPROM ar-
rays, a 4.7 µF bulk electrolytic capacitor should be used
between VCC and VSS for each eight devices. The loca-
tion of the capacitor should be close to where the
power supply is connected to the array.
System Applications
During the switch between active and standby condi-
tions, transient current peaks are produced on the ris-
MODE SELECT TABLE
Mode
CE#
OE#
PGM#
A0
X
A9
X
V
Outputs
PP
Read
V
V
X
X
X
X
X
X
X
X
D
OUT
IL
IL
Output Disable
Standby (TTL)
Standby (CMOS)
Program
X
V
X
X
High Z
High Z
High Z
IH
V
X
X
X
IH
V
± 0.3 V
X
X
X
CC
V
V
V
V
X
X
V
D
IN
IL
IL
IH
IH
IL
PP
PP
PP
Program Verify
Program Inhibit
V
V
X
X
V
V
D
OUT
IL
IH
V
X
X
X
X
High Z
01h
Manufacturer Code
Device Code
V
V
V
V
X
X
V
V
V
X
X
IL
IL
IL
IL
IL
H
H
Autoselect
(Note 3)
V
97h
IH
Notes:
1. V = 12.0 V ± 0.5 V.
H
2. X = Either V or V .
IH
IL
3. A1–A8 and A10–17 = V
IL
4. See DC Programming Characteristics for V voltage during programming.
PP
6
Am27C020
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature
Commercial (C) Devices
OTP Products. . . . . . . . . . . . . . . . . . –65°C to +125°C
All Other Products . . . . . . . . . . . . . . –65°C to +150°C
Ambient Temperature (TA) . . . . . . . . . . .0°C to +70°C
Industrial (I) Devices
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . –55°C to +125°C
Ambient Temperature (TA) . . . . . . . . .–40°C to +85°C
Extended (E) Devices
Voltage with Respect to VSS
All pins except A9, VPP, VCC . . –0.6 V to VCC + 0.6 V
Ambient Temperature (TA) . . . . . . . .–55°C to +125°C
Supply Read Voltages
A9 and VPP (Note 2) . . . . . . . . . . . . .–0.6 V to 13.5 V
VCC (Note 1). . . . . . . . . . . . . . . . . . . . .–0.6 V to 7.0 V
Notes:
VCC for ± 5% devices . . . . . . . . . . +4.75 V to +5.25 V
VCC for ± 10% devices . . . . . . . . . +4.50 V to +5.50 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
1. Minimum DC voltage on input or I/O pins –0.5 V. During
voltage transitions, the input may overshoot V to –2.0 V
SS
for periods of up to 20 ns. Maximum DC voltage on input
and I/O pins is V + 5 V. During voltage transitions, input
CC
and I/O pins may overshoot to V + 2.0 V for periods up
CC
to 20 ns.
2. Minimum DC input voltage on A9 is –0.5 V. During voltage
transitions, A9 and V may overshoot V to –2.0 V for
PP
SS
periods of up to 20 ns. A9 and V must not exceed +13.5
PP
V at any time.
Stresses above those listed under “Absolute Maximum Rat-
ings” may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these
or any other conditions above those indicated in the opera-
tional sections of this specification is not implied. Exposure of
the device to absolute maximum ratings for extended periods
may affect device reliability.
Am27C020
7
DC CHARACTERISTICS over operating range (unless otherwise specified)
Parameter
Symbol
Parameter Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Test Conditions
Min
Max
Unit
V
V
I
= –400 µA
= 2.1 mA
2.4
OH
OH
OL
V
I
0.45
V
OL
V
2.0
V
+ 0.5
V
IH
CC
V
Input LOW Voltage
–0.5
+0.8
1.0
5.0
30
V
IL
I
Input Load Current
V
V
= 0 V to V
CC
LI
IN
I
Output Leakage Current
= 0 V to V
CC
µA
LO
OUT
I
V
Active Current (Note 2)
C/I Devices
E Devices
CC1
CC
CE# = V , f = 10 MHz,
IL
mA
I
= 0 mA
OUT
60
I
I
V
V
V
TTL Standby Current
CMOS Standby Current
Supply Current (Read)
CE# = V
IH
1.0
100
100
mA
µA
µA
CC2
CC3
CC
CC
PP
CE# = V ± 0.3 V
CC
I
CE# = OE# = V , V = V
IL PP CC
PP1
Caution: The device must not be removed from (or inserted into) a socket when V or V is applied.
CC
PP
Notes:
1. V must be applied simultaneously or before V , and removed simultaneously or after V ..
CC
PP
PP
2. I
is tested with OE# = V to simulate open outputs.
IH
CC1
3. Minimum DC Input Voltage is –0.5 V. During transitions, the inputs may overshoot to –2.0 V for periods less than 20 ns.
Maximum DC Voltage on output pins is V + 0.5 V, which may overshoot to V + 2.0 V for periods less than 20 ns.
CC
CC
30
25
20
15
10
30
25
20
15
10
–75 –50 –55
0
25 50 75 100 125 150
1
2
3
4
5
6
7
8
9
10
Temperature in °C
Frequency in MHz
11507H-5
11507H-6
Figure 1. Typical Supply Current vs. Frequency
Figure 2. Typical Supply Current vs. Temperature
VCC = 5.5 V, f = 10 MHz
VCC = 5.5 V, T = 25°C
8
Am27C020
TEST CONDITIONS
5.0 V
Table 1. Test Specifications
Test Condition -55 All
1 TTL gate
Unit
2.7 kΩ
Output Load
Device
Under
Test
Output Load Capacitance, C
(including jig capacitance)
L
30
100
pF
C
L
6.2 kΩ
Input Rise and Fall Times
Input Pulse Levels
≤ 20
0.0–3.0 0.45–2.4
ns
V
Input timing measurement
reference levels
1.5
1.5
0.8, 2.0
0.8, 2.0
V
V
Note:
Output timing measurement
reference levels
Diodes are IN3064 or equivalents.
11507H-7
Figure 3. Test Setup
SWITCHING TEST WAVEFORM
3 V
2.4 V
2.0 V
2.0 V
Test Points
1.5 V
Test Points
1.5 V
0.8 V
0.8 V
0 V
0.45 V
Input
Output
Input
Output
Note: For C = 30 pF.
Note: For C = 100 pF.
L
L
11507H-8
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
KS000010-PAL
Am27C020
9
AC CHARACTERISTICS
Parameter Symbols
Am27C020
-75
-55 -70 -90 -120 -150 -200 -255 Unit
JEDEC Standard
Description
Test Setup
CE#,
OE# = V
t
t
t
Address to Output Delay
Max
55
70
90 120 150 200 250
90 120 150 200 250
ns
AVQV
ACC
IL
IL
IL
t
Chip Enable to Output Delay
OE# = V
Max
Max
55
40
70
40
ns
ns
ELQV
GLQV
CE
t
t
Output Enable to Output Delay CE# = V
40
50
65
75
100
OE
Chip Enable High or Output
Enable High to Output High Z,
Whichever Occurs First
t
t
t
EHQZ
GHQZ
DF
Max
Min
25
0
25
0
25
30
30
40
60
ns
ns
(Note 2)
Output Hold Time from
Addresses, CE# or OE#,
Whichever Occurs First
t
t
0
0
0
0
0
AXQX
OH
Caution: Do not remove the device from (or insert it into) a socket or board that has V or V applied.
PP
CC
Notes:
1. V must be applied simultaneously or before V , and removed simultaneously or after V .
PP
CC
PP
2. This parameter is sampled and not 100% tested.
3. Switching characteristics are over operating range, unless otherwise specified.
4. See Figure 3 and Table 1 for test specifications.
SWITCHING WAVEFORMS
2.4
2.0
0.8
2.0
0.8
Addresses
0.45
Addresses Valid
CE#
OE#
t
CE
t
(Note 2)
DF
t
OE
t
ACC
t
OH
(Note 1)
High Z
High Z
Output
Valid Output
11507H-9
Notes:
1. OE# may be delayed up to t
– t after the falling edge of the addresses without impact on t .
ACC
ACC
OE
2. t is specified from OE# or CE#, whichever occurs first.
DF
PACKAGE CAPACITANCE
CDV032
PD 032
Typ Max
PL 032
Parameter
Description
Parameter Symbol
Test Conditions
Typ
Max
12
Typ
Max
10
Unit
pF
C
Input Capacitance
Output Capacitance
V
V
= 0
10
12
10
12
12
15
8
9
IN
IN
C
= 0
15
12
pF
OUT
OUT
Notes:
1. This parameter is only sampled and not 100% tested.
2. T = +25°C, f = 1 MHz.
A
10
Am27C020
PHYSICAL DIMENSIONS*
CDV032—32-Pin Ceramic Dual In-Line Package, UV Lens (measured in inches)
DATUM D
CENTER PLANE
UV Lens
.565
.605
1
INDEX AND
TERMINAL NO. 1
I.D. AREA
TOP VIEW
DATUM D
CENTER PLANE
.700
MAX
1.635
1.680
.160
.220
BASE PLANE
SEATING PLANE
94°
105°
.125
.200
.015
.060
.300 BSC
.005 MIN
.600
BSC
.045
.065
.008
.018
.100 BSC
.014
.026
END VIEW
SIDE VIEW
16-000038H-3
CDV032
DF11
3-30-95 ae
* For reference only. BSC is an ANSI standard for Basic Space Centering.
PD 032—32-Pin Plastic Dual In-Line Package (measured in inches)
1.640
1.680
.600
.625
17
16
32
.008
.015
.530
.580
Pin 1 I.D.
.630
.700
.045
.065
0˚
10˚
.005 MIN
.140
.225
16-038-SB_AG
PD 032
DG75
SEATING PLANE
.090
.110
.015
.060
.014
.022
2-28-95 ae
.120
.160
Am27C020
11
PHYSICAL DIMENSIONS
PL 032—32-Pin Plastic Leaded Chip Carrier (measured in inches)
.485
.495
.447
.453
.009
.015
.042
.056
.125
.140
.585
.595
Pin 1 I.D.
.080
.095
.547
.553
SEATING
PLANE
.400
REF.
.490
.530
.013
.021
.050 REF.
16-038FPO-5
PL 032
DA79
.026
.032
TOP VIEW
SIDE VIEW
6-28-94 ae
l
REVISION SUMMARY FOR AM27C010
Revision H
Global
Changed formatting to match current data sheets.
Trademarks
Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.
Flashrite is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
12
Am27C020
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