AM27C040-150DCB [AMD]
4 Megabit (512 K x 8-Bit) CMOS EPROM; 4兆位（ 512K的×8位） CMOS EPROM
| 型号： | AM27C040-150DCB |
| 厂家： | 
AMD |
| 描述： | 4 Megabit (512 K x 8-Bit) CMOS EPROM |
| 文件： | 总13页 (文件大小：168K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FINAL
Am27C040
4 Megabit (512 K x 8-Bit) CMOS EPROM
DISTINCTIVE CHARACTERISTICS
■ Fast access time
■ Single +5 V power supply
— Available in speed options as fast as 90 ns
■ Low power consumption
■ ±10% power supply tolerance standard
■ 100% Flashrite™ programming
— Typical programming time of 1 minute
— <10 µA typical CMOS standby current
■ Latch-up protected to 100 mA from –1 V to
■ JEDEC-approved pinout
VCC + 1 V
— Plug-in upgrade for 1 Mbit and 2 Mbit EPROMs
— Easy upgrade from 28-pin JEDEC EPROMs
■ High noise immunity
■ Compact 32-pin DIP, PDIP, PLCC packages
GENERAL DESCRIPTION
The Am27C040 is a 4 Mbit ultraviolet erasable pro-
grammable read-only memory. It is organized as 512K
bytes, operates from a single +5 V supply, has a static
standby mode, and features fast single address loca-
tion programming. The device is available in windowed
ceramic DIP packages and plastic one-time program-
mable (OTP) packages.
thus eliminating bus contention in a multiple bus micro-
processor system.
AMD’s CMOS process technology provides high
speed, low power, and high noise immunity. Typical
power consumption is only 100 mW in active mode,
and 50 µW in standby mode.
All signals are TTL levels, including programming sig-
nals. Bit locations may be programmed singly, in
blocks, or at random. The device supports AMD’s
Flashrite programming algorithm (100 µs pulses) re-
sulting in typical programming time of 1 minute.
Data can be typically accessed in less than 90 ns, al-
lowing high-performance microprocessors to operate
without any WAIT states. The device offers separate
Output Enable (OE#) and Chip Enable (CE#) controls,
BLOCK DIAGRAM
V
Data Outputs
DQ0–DQ7
CC
V
V
SS
PP
Output Enable
Chip Enable
and
OE#
Output
Buffers
Prog Logic
CE#/PGM#
Y
Y
Gating
Decoder
A0–A18
Address
Inputs
X
4,194,304-Bit
Cell Matrix
Decoder
14971G-1
Publication# 14971 Rev: G Amendment/0
Issue Date: May 1998
F I N A L
PRODUCT SELECTOR GUIDE
Family Part Number
Am27C040
Speed Options (V = 5.0 V ± 10%)
-90
90
90
40
-120
-150
150
150
65
-200
200
200
75
CC
Max Access Time (ns)
CE# (E#) Access (ns)
OE# (G#) Access (ns)
120
120
50
CONNECTION DIAGRAMS
Top View
DIP
PLCC
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
VPP
A16
A15
A12
A7
2
A18
4
3
2
32 31 30
1
3
A17
5
A7
A6
A5
A4
A3
A2
A1
A0
29 A14
6
4
28
27
26
25
24
23
22
21
A13
A14
7
A8
5
A13
8
A9
A6
6
A8
9
A11
A5
7
A9
10
11
12
13
OE# (G#)
A10
A4
8
A11
A3
9
OE# (G#)
CE# (E#)/PGM# (P#)
DQ7
A2
10
11
12
13
14
15
16
A10
DQ0
A1
CE# (E#)/PGM# (P#)
14 15 16 17 18 19 20
A0
DQ7
DQ6
DQ0
DQ1
DQ2
VSS
DQ5
DQ4
DQ3
14971G-3
14971G-2
Notes:
1. JEDEC nomenclature is in parenthesis.
2. The 32-pin DIP to 32-pin PLCC configuration varies from the JEDEC 28-pin DIP to 32-pin PLCC configuration.
PIN DESIGNATIONS
LOGIC SYMBOL
A0–A18
=
Address Inputs
CE# (E#)/PGM# (P#)= Chip Enable/Program Enable Input
19
DQ0–DQ7
OE# (G#)
=
=
=
=
=
Data Inputs/Outputs
Output Enable Input
A0–A18
8
DQ0–DQ7
CE# (E#)/PGM#(P#)
OE# (G#)
V
V
V
V
Supply Voltage
CC
CC
PP
SS
Program Voltage Input
GroundLogic Symbol
14971E-4
2
Am27C040
F I N A L
ORDERING INFORMATION
UV EPROM Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of:
AM27C040
-90
D
C
OPTIONAL PROCESSING
Blank = Standard Processing
B
= Burn-In
TEMPERATURE RANGE
C
I
E
= Commercial (0°C to +70°C)
= Industrial (–40°C to +85°C)
= Extended (–55°C to +125°C)
PACKAGE TYPE
= 32-Pin Ceramic DIP (CDV032)
D
SPEED OPTION
See Product Selector Guide and
Valid Combinations
DEVICE NUMBER/DESCRIPTION
Am27C040
4 Megabit (512K x 8-Bit) CMOS UV EPROM
Valid Combinations
Valid Combinations list configurations planned to be sup-
ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
Valid Combinations
AM27C040-90
AM27C040-120
AM27C040-150
AM27C040-200
DC, DCB, DI, DIB, DE, DEB
Am27C040
3
F I N A L
ORDERING INFORMATION
OTP EPROM Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of:
AM27C040
-90
J
C
OPTIONAL PROCESSING
Blank = Standard Processing
TEMPERATURE RANGE
C
I
E
= Commercial (0°C to +70°C)
= Industrial (–40°C to +85°C)
= Extended (–55°C to 125°C)
PACKAGE TYPE
P
J
= 32-Pin Plastic DIP (PD 032)
= 32-Pin Rectangular Plastic Leaded Chip
Carrier (PL 032)
SPEED OPTION
See Product Selector Guide and
Valid Combinations
DEVICE NUMBER/DESCRIPTION
Am27C040
4 Megabit (512K x 8-Bit) CMOS OTP EPROM
Valid Combinations
Valid Combinations
AM27C040-90
Valid Combinations list configurations planned to be sup-
ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
AM27C040-120
AM27C040-150
AM27C040-200
PC, PI, JC, JI
4
Am27C040
F I N A L
FUNCTIONAL DESCRIPTION
Device Erasure
that particular device. A high-level CE#/PGM# input in-
hibits the other devices from being programmed.
In order to clear all locations of their programmed
contents, the device must be exposed to an ultraviolet
light source. A dosage of 15 W seconds/cm2 is required
to completely erase the device. This dosage can be ob-
tained by exposure to an ultraviolet lamp — wavelength
of 2537 Å — with intensity of 12,000 µW/cm2 for 15 to 20
minutes. The device should be directly under and about
one inch from the source and all filters should be re-
moved from the UV light source prior to erasure.
Program Verify
A verification should be performed on the programmed
bits to determine that they were correctly programmed.
The verify should be performed with OE# at VIL, CE#/
PGM# at VIH, and VPP between 12.5 V and 13.0 V.
Auto Select Mode
The autoselect mode provides manufacturer and de-
vice identification through identifier codes on DQ0–
DQ7. This mode is primarily intended for programming
equipment to automatically match a device to be pro-
grammed with its corresponding programming algo-
rithm. This mode is functional in the 25°C ± 5°C
ambient temperature range that is required when pro-
gramming the device.
Note that all UV erasable devices will erase with light
sources having wavelengths shorter than 4000 Å, such
as fluorescent light and sunlight. Although the erasure
process happens over a much longer time period, ex-
posure to any light source should be prevented for
maximum system reliability. Simply cover the package
window with an opaque label or substance.
To activate this mode, the programming equipment
must force VH on address line A9. Two identifier bytes
may then be sequenced from the device outputs by tog-
gling address line A0 from VIL to VIH (that is, changing
the address from 00h to 01h). All other address lines
must be held at VIL during the autoselect mode.
Device Programming
Upon delivery, or after each erasure, the device has
all of its bits in the “ONE”, or HIGH state. “ZEROs” are
loaded into the device through the programming pro-
cedure.
The programming mode is entered when 12.75 V ±
0.25 V is applied to the VPP pin, CE#/PGM# is at VIL
Byte 0 (A0 = VIL) represents the manufacturer code,
and Byte 1 (A0 = VIH), the device identifier code. Both
codes have odd parity, with DQ7 as the parity bit.
and OE# is at VIH
.
For programming, the data to be programmed is ap-
plied 8 bits in parallel to the data output pins.
Read Mode
To obtain data at the device outputs, Chip Enable (CE#/
PGM#) and Output Enable (OE#) must be driven low.
CE#/PGM# controls the power to the device and is typ-
ically used to select the device. OE# enables the device
to output data, independent of device selection. Ad-
dresses must be stable for at least tACC–tOE. Refer to
the Switching Waveforms section for the timing dia-
gram.
The flowchart in the EPROM Products Data Book, Pro-
gramming section (Section 5, Figure 5-1) shows AMD’s
Flashrite algorithm. The Flashrite algorithm reduces pro-
gramming time by using a 100 µs programming pulse
and by giving each address only as many pulses to reli-
ably program the data. After each pulse is applied to a
given address, the data in that address is verified. If the
data does not verify, additional pulses are given until it
verifies or the maximum pulses allowed is reached. This
process is repeated while sequencing through each ad-
dress of the device. This part of the algorithm is done at
VCC = 6.25 V to assure that each EPROM bit is pro-
grammed to a sufficiently high threshold voltage. After
the final address is completed, the entire EPROM mem-
ory is verified at VCC = VPP = 5.25 V.
Standby Mode
The device enters the CMOS standby mode when
CE#/PGM# is at VCC ± 0.3 V. Maximum VCC current is
reduced to 100 µA. The device enters the TTL-standby
mode when CE#/PGM# is at VIH. Maximum VCC cur-
rent is reduced to 1.0 mA. When in either standby
mode, the device places its outputs in a high-imped-
ance state, independent of the OE# input.
Please refer to the EPROM Products Data Book, Sec-
tion 5 for the programming flow chart and characteris-
tics.
Output OR-Tieing
To accommodate multiple memory connections, a
two-line control function is provided to allow for:
Program Inhibit
Programming different data to multiple devices in par-
allel is easily accomplished. Except for CE#/PGM#, all
like inputs of the devices may be common. A TTL
low-level program pulse applied to one device’s CE#/
PGM# input with VPP = 12.75 V ± 0.25 V will program
■ Low memory power dissipation, and
■ Assurance that output bus contention will not occur
CE#/PGM# should be decoded and used as the pri-
mary device-selecting function, while OE# be made a
Am27C040
5
F I N A L
common connection to all devices in the array and con-
nected to the READ line from the system control bus.
This assures that all deselected memory devices are in
their low-power standby mode and that the output pins
are only active when data is desired from a particular
memory device.
these transient current peaks is dependent on the out-
put capacitance loading of the device. At a minimum, a
0.1 µF ceramic capacitor (high frequency, low inherent
inductance) should be used on each device between
VCC and VSS to minimize transient effects. In addition,
to overcome the voltage drop caused by the inductive
effects of the printed circuit board traces on EPROM ar-
rays, a 4.7 µF bulk electrolytic capacitor should be used
between VCC and VSS for each eight devices. The loca-
tion of the capacitor should be close to where the
power supply is connected to the array.
System Applications
During the switch between active and standby condi-
tions, transient current peaks are produced on the ris-
ing and falling edges of Chip Enable. The magnitude of
MODE SELECT TABLE
Mode
CE#/PGM#
OE#
A0
X
A9
X
V
Outputs
PP
Read
V
V
V
X
X
X
X
D
OUT
IL
IL
IL
Output Disable
Standby (TTL)
Standby (CMOS)
Program
V
X
X
HIGH Z
HIGH Z
HIGH Z
IH
V
X
X
X
IH
V
+ 0.3 V
X
X
X
CC
V
V
V
X
X
V
D
IN
IL
IL
IH
PP
PP
PP
Program Verify
Program Inhibit
V
X
X
V
V
D
OUT
IL
V
X
X
X
HIGH Z
01h
IH
Manufacturer Code
Device Code
V
V
V
V
V
V
X
X
Auto Select
(Note 3)
IL
IL
IL
IL
IL
H
V
V
9Bh
IH
H
Note:
1. V = 12.0 V ± 0.5 V.
H
2. X = Either V or V
IH
IL
3. A1 – A8 = A10 – A18 = V
IL
4. See DC Programming Characteristics in the EPROM Products Data Book for V voltage during programming
PP
6
Am27C040
F I N A L
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
OPERATING RANGES
Commercial (C) Devices
OTP Products . . . . . . . . . . . . . . . . –65°C to +125°C
All Other Products. . . . . . . . . . . . . –65°C to +150°C
Ambient Temperature (TA) . . . . . . . . . . .0°C to +70°C
Industrial (I) Devices
Ambient Temperature
with Power Applied. . . . . . . . . . . . . .–55°C to + 125°C
Ambient Temperature (TA) . . . . . . . . .–40°C to +85°C
Extended (E) Devices
Voltage with Respect to VSS
Ambient Temperature (TA) . . . . . . . .–55°C to +125°C
Supply Read Voltages
All pins except A9, VPP,
VCC (Note 1) . . . . . . . . . . . . . . –0.6 V to VCC +0.5 V
VCC for ± 5% devices . . . . . . . . . . +4.75 V to +5.25 V
VCC for ± 10% devices . . . . . . . . . +4.50 V to +5.50 V
A9 and VPP (Note 2) . . . . . . . . . . . .–0.6 V to +13.5 V
VCC . . . . . . . . . . . . . . . . . . . . . . . . . .–0.6 V to +7.0 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
1. During voltage transitions, inputs may overshoot V to –
SS
2.0 V for periods of up to 20 ns. Maximum DC voltage on
input and I/O pins may overshoot to V
periods up to 20ns.
+ 2.0 V for
CC
2. During voltage transitions, A9 and V may overshoot
PP
V
to –2.0 V for periods of up to 20 ns. A9 and V must
SS
PP
not exceed +13.5 V at any time.
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is
a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the op-
erational sections of this specification is not implied. Expo-
sure of the device to absolute maximum rating conditions for
extended periods may affect device reliability.
Am27C040
7
F I N A L
DC CHARACTERISTICS over operating ranges unless otherwise specified
Parameter
Symbol
Parameter Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Test Conditions
= –400 µA
Min
Max
Unit
V
V
I
2.4
OH
OH
V
I
= 2.1 mA
= 0 V to V
0.45
V
OL
OL
V
2.0
V
+ 0.5
V
IH
CC
V
–0.5
+0.8
1.0
5.0
5.0
40
V
IL
C/I Devices
E Devices
Input Load Current
V
V
IN
CC
I
µA
µA
LI
I
Output Leakage Current
= 0 V to V
OUT CC
LO
C/I Devices
E Devices
CE# = V , f = 10 MHz,
IL
I
V
Active Current (Note 3)
mA
CC1
CC
I
= 0 MA
60
OUT
I
I
V
V
TTL Standby Current
CMOS Standby
CE# = V
IH
1.0
mA
µA
CC2
CC3
CC
CC
CE# = V ± 0.3 V
100
100
CC
Current
CE# = OE# = V , V
IL PP
I
V
Current During Read
µA
PP1
PP
= V
CC
Caution: The device must not be removed from (or inserted into) a socket when V or V is applied.
CC
PP
Notes:
1. V must be applied simultaneously or before V and removed simultaneously or after V
CC
PP
PP
2. I
is tested with OE# = V to simulate open outputs.
IH
CC1
3. Minimum DC Input Voltage is –0.5. During transitions, the inputs may overshoot to –2.0 V for periods less than 20 ns. Maxi-
mum DC Voltage on output pins is Vcc +0.5 V, which may overshoot to V +2.0 V for periods less than 20 ns.
CC
25
25
20
20
15
15
10
10
5
–75 –50 –25
5
0
25 50 75 100 125 150
1
2
3
4
5
6
7
8
9
10
Temperature in °C
Frequency in MHz
Figure 1. Typical Supply Current vs. Frequency
Figure 2. Typical Supply Current vs. Temperature
VCC = 5.5 V, f = 10 MHz
VCC = 5.5 V, T = 25°C
14971E-1
14971E-1
8
Am27C040
F I N A L
TEST CONDITIONS
5.0 V
Table 1. Test Specifications
Test Condition
Output Load
All
Unit
2.7 kΩ
1 TTL gate
Device
Under
Test
Output Load Capacitance, C
(including jig capacitance)
L
100
pF
C
L
6.2 kΩ
Input Rise and Fall Times
Input Pulse Levels
≤ 20
ns
0.45–2.4
V
Input timing measurement reference
levels
0.8, 2.0
0.8, 2.0
V
V
Note:
Output timing measurement
reference levels
Diodes are IN3064 or equivalents.
14971G-5
Figure 1. Test Setup
SWITCHING TEST WAVEFORM
3 V
2.4 V
2.0 V
0.8 V
2.0 V
Test Points
1.5 V
Test Points
1.5 V
0.8 V
0 V
0.45 V
Input
Output
Input
Output
Note: For C = 30 pF.
Note: For C = 100 pF.
L
L
14971G-6
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
KS000010-PAL
Am27C040
9
F I N A L
AC CHARACTERISTICS
Parameter Symbols
Am27C040
JEDEC
Std.
Description
Test Setup
-90
-120 -150 -200
Unit
CE# = OE#
t
t
t
Address to Output Delay
Max
90
120
150
200
ns
AVQV
ACC
= V
IL
t
Chip Enable to Output Delay
OE# = V
Max
Max
90
40
120
50
150
65
200
75
ns
ns
ELQV
GLQV
CE
IL
t
t
t
Output Enable to Output Delay
Chip Enable High or Output Enable High,
CE# = V
OE
IL
t
EHQZ
GHQZ
DF
Max
Min
30
0
30
0
30
0
40
0
ns
ns
t
(Note 2) Whichever Occurs First, to Output High Z
Output Hold Time from Addresses, CE# or
OE#, Whichever Occurs First
t
t
OH
AXQX
Caution: Do not remove the device from (or inserted into) a socket when V or V is applied.
CC
PP
Notes:
1. V must be applied simultaneously or before V , and removed simultaneously or after V .
CC
PP
PP
2. This parameter is sampled and not 100% tested.
3. Switching characteristics are over operating range, unless otherwise specified.
4. See Figure 1 and Table 1 for test specifications.
SWITCHING WAVEFORMS
2.4
2.0
0.8
2.0
0.8
Addresses Valid
Addresses
0.45
CE#/PGM#
OE#
t
CE
t
DF
t
OE
(Note 2)
t
ACC
t
OH
(Note 1)
High Z
High Z
Output
Valid Output
14971E-1
Note:
1. OE# may be delayed up to tACC - tOE after the falling edge of the addresses without impact on tACC.
2. tDF is specified from OE# or CE#, whichever occurs first.
PACKAGE CAPACITANCE
CDV032
PD 032
PL 032
Typ
Parameter
Symbol
Parameter
Description
Test
Conditions
Typ
Max
12
Typ
Max
12
Max
10
Unit
pF
C
Input Capacitance
V
= 0 V
IN
10
12
10
12
8
9
IN
C
Output Capacitance V
= 0 V
15
15
12
pF
OUT
OUT
Notes:
1. This parameter is only sampled and not 100% tested.
2. T = +25°C, f = 1 MHz.
A
10
Am27C040
F I N A L
PHYSICAL DIMENSIONS
PD 032—32-Pin Plastic Dual In-Line Package (measured in inches)
1.640
1.670
.600
.625
17
16
32
.009
.015
.530
.580
Pin 1 I.D.
.630
.700
.045
.065
0°
10°
.005 MIN
.140
.225
16-038-S_AG
PD 032
EC75
SEATING PLANE
.090
.110
.015
.060
.016
.022
5-28-97 lv
.120
.160
PL 032—32-Pin Plastic Leaded Chip Carrier (measured in inches)
.485
.495
.447
.453
.009
.015
.042
.056
.125
.140
.585
.595
Pin 1 I.D.
.080
.095
.547
.553
SEATING
PLANE
.400
REF.
.490
.530
.013
.021
.050 REF.
16-038FPO-5
PL 032
DA79
.026
.032
TOP VIEW
SIDE VIEW
6-28-94 ae
Am27C040
11
F I N A L
PHYSICAL DIMENSIONS*
CDV032—32-Pin Ceramic DIP, UV Lens (measured in inches)
DATUM D
CENTER PLANE
UV Lens
.565
.605
1
INDEX AND
TERMINAL NO. 1
I.D. AREA
TOP VIEW
DATUM D
CENTER PLANE
.700
MAX
1.635
1.680
.160
.220
BASE PLANE
SEATING PLANE
94°
105°
.125
.200
.015
.060
.300 BSC
.005 MIN
.600
BSC
.045
.065
.008
.018
.100 BSC
.014
.026
END VIEW
SIDE VIEW
16-000038H-3
CDV032
DF11
3-30-95 ae
* For reference only. BSC is an ANSI standard for Basic Space Centering.
REVISION SUMMARY FOR AM27C040
Revision E/1
Product Selector Guide:
Added -90 (90 ns, ±10% VCC) and deleted -100 speed options.
Ordering Information, UV EPROM Products:
The -90 part number is now listed in the example.
Valid Combinations: Added -90 and deleted -100 speed options in valid combinations.
Ordering Information, OTP EPROM Products:
The -90 part number is now listed in the example.
Valid Combinations: Added -90 and deleted -100 speed options in valid combinations.
Programming the Am27C040:
The fourth paragraph should read, “Please refer to Section 5 for programming…”.
12
Am27C040
F I N A L
OTP EPROM Products: Changed -75 speed option to
Operating Ranges:
-90.
Changed Supply Read Voltages listings to match those
in the Product Selector Guide.
Temperature Range: Added “E = Extended (–55°C to
125°C)”.
AC Characteristics:
Package Type: Deleted “E = 32-pin Thin Small Outline
Package (TSOP) Standard Pinout (TS 032)”.
Added -90 and deleted -100 speed options in table, re-
arranged notes, moved text from table title to Note 4,
renamed table.
Valid Combinations: Deleted EC and EI options.
Revision F
Functional Description:
Deleted -255 speed option.
Replaced device specific text with generic text.
Changed all active low signal designations from over-
bars or trailing “#”s.
Test Conditions:
New section with Test Setup Figure and Test Specifica-
tions Table.
Revision G
Global
Switching Test Waveform:
Made formatting and layout consistent with other data
sheets. Used updated common tables and diagrams.
Modified figure.
Operating Ranges:
Distinctive Characteristics:
Supply Read Voltages: Replaced with generic data.
Low Power Consumption: Changed “100 µA maximum”
to “<10 µA typical”.
DC Characteristics:
Modified Figures 1 and 2.
TSOP package deleted.
Switching Waveform:
General Description:
Corrected “DF” to “tDF” in Note 2.
In the third paragraph, changed “100 µW in standby
mode” to 50 µW in standby mode”.
Package Capacitance:
Deleted TSOP data.
Connection Diagrams:
Physical Dimensions:
Deleted TSOP Pinout figure.
New section, added figures for the 32-Pin Ceramic DIP,
32-Pin Plastic DIP, and 32-Pin Plastic Leaded Chip
Carrier.
Pin Designations:
Changed “Chip Enable Input” to “Chip Enable/Program
Enable Input”.
Ordering Information:
UV EPROM Products: Changed -75 speed option to
-90.
Trademarks
Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.
Flashrite is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
Am27C040
13
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