AM27C256-200 [AMD]
256 Kilobit (32,768 x 8-Bit) CMOS EPROM; 256千位（ 32,768 ×8位） CMOS EPROM
| 型号： | AM27C256-200 |
| 厂家： | 
AMD |
| 描述： | 256 Kilobit (32,768 x 8-Bit) CMOS EPROM |
| 文件： | 总12页 (文件大小：94K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FINAL
Advanced
Micro
Am27C256
256 Kilobit (32,768 x 8-Bit) CMOS EPROM
Devices
DISTINCTIVE CHARACTERISTICS
■ Fast access time
■ Latch-up protected to 100 mA from –1 V to
VCC + 1 V
— 55 ns
■ High noise immunity
■ Low power consumption
■ Versatile features for simple interfacing
— 20 µA typical CMOS standby current
■ JEDEC-approved pinout
— Both CMOS and TTL input/output
compatibility
■ Single +5 V power supply
— Two line control functions
■ ±10% power supply tolerance available
■ 100% Flashrite programming
— Typical programming time of 4 seconds
■ Standard 28-pin DIP, PDIP, 32-pin TSOP and
PLCC packages
GENERAL DESCRIPTION
The Am27C256 is a 256K-bit ultraviolet erasable pro-
grammable read-only memory. It is organized as 32K
words by 8 bits per word, operates from a single +5 V
supply, has a static standby mode, and features fast sin-
gle address location programming. Products are avail-
ableinwindowedceramicDIPpackagesaswellasplas-
tic one time programmable (OTP) PDIP, TSOP, and
PLCC packages.
controls, thus eliminating bus contention in a multiple
bus microprocessor system.
AMD’s CMOS process technology provides high speed,
low power, and high noise immunity. Typical power con-
sumption is only 80 mW in active mode, and 100 µW in
standby mode.
All signals are TTL levels, including programming sig-
nals. Bit locations may be programmed singly, in blocks,
or at random. The Am27C256 supports AMD’s Flashrite
programming algorithm (100 µs pulses) resulting in typi-
cal programming time of 4 seconds.
Typically, any byte can be accessed in less than 55 ns,
allowing operation with high-performance microproces-
sors without any WAIT states. The Am27C256 offers
separate Output Enable (OE) and Chip Enable (CE)
BLOCK DIAGRAM
Data Outputs
DQ0–DQ7
V
V
V
CC
SS
PP
Output Enable
Chip Enable
and
OE
CE
Output
Buffers
Prog Logic
Y
Y
Decoder
Gating
A0–A14
Address
Inputs
262,144
Bit Cell
Matrix
X
Decoder
08007H-1
Publication# 08007 Rev. H Amendment/0
Issue Date: May 1995
2-32
AMD
-255
PRODUCT SELECTOR GUIDE
Family Part No.
Am27C256
Ordering Part No:
VCC ± 5%
V
CC ± 10%
-55
55
55
35
-70
70
70
40
-90
90
90
40
-120
120
120
50
-150
150
150
50
-200
200
200
50
Max Access Time (ns)
CE (E) Access Time (ns)
OE (G) Access Time (ns)
250
250
50
CONNECTION DIAGRAMS
Top View
DIP
PLCC
1
2
3
4
5
6
28
27
26
25
24
23
VPP
A12
A7
VCC
A14
A13
4
3 2 1 32 31 30
A6
A8
A9
5
29
28
A6
A5
A4
A3
A8
A5
A4
6
A9
7
27 A11
A11
A3
8
NC
26
25
7
8
22
21
A2
9
OE (G)
OE (G)
A10
24 A10
A1
10
11
12
13
A2
A1
A0
CE (E)
9
20
19
18
17
16
15
23
22
21
CE (E)
DQ7
NC
DQ0
DQ7
DQ6
10
11
12
13
14
A0
DQ0
DQ1
DQ2
DQ6
DQ5
DQ4
DQ3
14 15 16 17 18 19 20
VSS
08007H-3
08007H-2
Notes:
1. JEDEC nomenclature is in parentheses.
2-33
Am27C256
AMD
CONNECTION DIAGRAM
TSOP*
OE (G)
1
2
3
4
5
6
7
NC
A10
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
CE (E)
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
NC
A13
NC
A14
VCC
VPP
NC
A12
A7
A6
A5
A4
A3
8
9
10
11
12
13
14
15
16
A0
A1
A2
08007H-4
*Contact local AMD sales office for package availability
Standard Pinout
PIN DESIGNATIONS
LOGIC SYMBOL
A0–A14
CE (E)
DQ0–DQ7
OE (G)
VCC
=
=
=
=
=
=
=
=
Address Inputs
Chip Enable
15
Data Inputs/Outputs
Output Enable Input
VCC Supply Voltage
Program Voltage Input
Ground
A0–A14
8
VPP
DQ0–DQ7
VSS
DU
Don’t Use
CE (E)
OE (G)
08007H-5
2-34
Am27C256
AMD
ORDERING INFORMATION
UV EPROM Products
AMD Standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of:
AM27C256
-55
D
C
B
OPTIONAL PROCESSING
Blank = Standard Processing
B = Burn-in
TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I
= Industrial (–40°C to +85°C)
E = Extended Commercial (–55°C to +125°C)
PACKAGE TYPE
D = 28-Pin Ceramic DIP (CDV028)
SPEED OPTION
See Product Selector Guide and Valid Combinations
DEVICE NUMBER
Am27C256
256 Kilobit (32,768 x 8-Bit) CMOS UV EPROM
Valid Combinations
Valid Combinations
Valid Combinations list configurations planned to be
supported in volume for this device. Consult the lo-
cal AMD sales office to confirm availability of specific
valid combinations and to check on newly released
combinations.
AM27C256-55
DC, DCB, DI, DIB
AM27C256-70
AM27C256-90
AM27C256-120
AM27C256-150
AM27C256-200
AM27C256-255
DC, DCB, DI,
DIB, DE, DEB
DC, DCB, DI, DIB
2-35
Am27C256
AMD
ORDERING INFORMATION
OTP Products
AMD Standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of:
AM27C256
-55
P
C
OPTIONAL PROCESSING
Blank = Standard Processing
TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I
= Industrial (–40°C to + 85°C)
PACKAGE TYPE
P = 28-Pin Plastic DIP (PD 028)
J = 32-Pin Rectangular Plastic Leaded Chip
Carrier (PL 032)
E = 32-Pin TSOP (TS 032)
SPEED OPTION
See Product Selector Guide and Valid Combinations
DEVICE NUMBER
Am27C256
256 Kilobit (32,768 x 8-Bit) CMOS OTP EPROM
Valid Combinations
Valid Combinations
Valid Combinations list configurations planned to be
supported in volume for this device. Consult the lo-
cal AMD sales office to confirm availability of specific
valid combinations and to check on newly released
combinations.
AM27C256-55
JC, PC, EC
AM27C256-70
AM27C256-90
AM27C256-120
AM27C256-150
AM27C256-200
AM27C256-255
JC, PC, EC,
JI, PI, EI
2-36
Am27C256
AMD
FUNCTIONAL DESCRIPTION
Erasing the Am27C256
OE High will program that Am27C256. A high-level CE
input inhibits the other Am27C256 devices from
being programmed.
In order to clear all locations of their programmed con-
tents, it is necessary to expose the Am27C256 to an
ultraviolet light source. A dosage of 15 W sec/cm2 is
required to completely erase an Am27C256. This dos-
agecanbeobtainedbyexposuretoanultravioletamp—
Program Verify
A verify should be performed on the programmed bits to
determine that they were correctly programmed. The
verify should be performed with OE at VIL, CE at VIH, and
VPP between 12.5 V to 13.0 V.
2
°
A
wavelength of 2537 —with intensity of 12,000 µW/cm
for 15 to 20 minutes. The Am27C256 should be directly
under and about one inch from the source and all filters
should be removed from the UV light source prior
to erasure.
Auto Select Mode
The auto select mode allows the reading out of a binary
code from an EPROM that will identify its manufacturer
andtype. Thismodeisintendedforusebyprogramming
equipment for the purpose of automatically matching
the device to be programmed with its corresponding
programming algorithm. This mode is functional in the
25°C ± 5°C ambient temperature range that is required
when programming the Am27C256.
It is important to note that the Am27C256 and similar
deviceswillerasewithlightsourceshavingwavelengths
°
A
shorter than 4000 . Although erasure times will be
°
A
much longer than with UV sources at 2537 , exposure
to fluorescent light and sunlight will eventually erase the
Am27C256 and exposure to them should be prevented
to realize maximum system reliability. If used in such an
environment, the package window should be covered
by an opaque label or substance.
To activate this mode, the programming equipment
must force 12.0 V ± 0.5 V on address like A9 of the
Am27C256. Two identifier bytes may then be se-
quenced from the device outputs by toggling address
line A0 from VIL to VIH. All other address lines must be
held at VIL during auto select mode.
Programming the Am27C256
Upon delivery or after each erasure the Am27C256 has
all 262,144 bits in the “ONE” or HIGH state. “ZEROs”
are loaded into the Am27C256 through the procedure
of programming.
Byte 0 (A0 = VIL) represents the manufacturer code, and
byte 1 (A0 = VIH), the device code. For the Am27C256,
these two identifier bytes are given in the Mode Select
Table. All identifiers for manufacturer and device codes
will possess odd parity, with the MSB (DQ7) defined as
the parity bit.
The programming mode is entered when 12.75 V
± 0.25 V is applied to the VPP pin, OE is at VIH, and CE is
at VIL.
For programming, the data to be programmed is applied
8 bits in parallel to the data output pins.
Read Mode
The Flashrite algorithm reduces programming time by
using 100 µs programming pulses and by giving each
address only as many pulses as is necessary in order to
reliably program the data. After each pulse is applied to
a given address, the data in that address is verified. If
the data does not verify, additional pulses are given until
it verifies or the maximum is reached. This process is re-
peated while sequencing through each address of the
Am27C256. This part of the algorithm is done at
VCC = 6.25 V to assure that each EPROM bit is pro-
grammed to a sufficiently high threshold voltage. After
the final address is completed, the entire EPROM mem-
ory is verified at VCC = VPP = 5.25 V.
The Am27C256 has two control functions, both of which
must be logically satisfied in order to obtain data at the
outputs. Chip Enable (CE) is the power control and
shouldbeusedfordeviceselection. OutputEnable(OE)
is the output control and should be used to gate data to
the output pins, independent of device selection. As-
suming that addresses are stable, address access time
(tACC) is equal to the delay from CE to output (tCE). Data
is available at the outputs tOE after the falling edge of
OE, assuming that CE has been LOW and addresses
have been stable for at least tACC–tOE.
Standby Mode
Please refer to Section 6 for programming flow chart
and characteristics.
The Am27C256 has a CMOS standby mode which re-
duces the maximum VCC current to 100µA. It is placed in
CMOS-standby when CE is at VCC ± 0.3 V. The
Am27C256 also has a TTL-standby mode which re-
ducesthemaximumVCC currentto1.0mA. Itisplacedin
TTL-standby when CE is at VIH. When in standby mode,
the outputs are in a high-impedance state, independent
of the OE input.
Program Inhibit
Programming of multiple Am27C256 in parallel with dif-
ferent data is also easily accomplished. Except for CE,
all like inputs of the parallel Am27C256 may be com-
mon. A TTL low-level program pulse applied to an
Am27C256 CE input with VPP = 12.75 V ± 0.25 V, and
2-37
Am27C256
AMD
Output OR-Tieing
System Applications
To accommodate multiple memory connections, a two-
line control function is provided to allow for:
During the switch between active and standby condi-
tions, transient current peaks are produced on the rising
and falling edges of Chip Enable. The magnitude of
these transient current peaks is dependent on the out-
put capacitance loading of the device. At a minimum, a
0.1-µF ceramic capacitor (high frequency, low inherent
inductance) should be used on each device between
VCC and VSS to minimize transient effects. In addition, to
overcome the voltage drop caused by the inductive ef-
fects of the printed circuit board traces on EPROM ar-
rays, a 4.7-µF bulk electrolytic capacitor should be used
between VCC and VSS for each eight devices. The loca-
tion of the capacitor should be close to where the power
supply is connected to the array.
■ Low memory power dissipation
■ Assurance that output bus contention will not occur
It is recommended that CE be decoded and used as the
primary device-selecting function, while OE be made a
common connection to all devices in the array and con-
nected to the READ line from the system control bus.
This assures that all deselected memory devices are in
low-power standby mode and that the output pins are
only active when data is desired from a particular
memory device.
MODE SELECT TABLE
Pins
CE
OE
VIL
VIH
X
A0
X
A9
X
VPP
X
Outputs
DOUT
Mode
Read
VIL
Output Disable
Standby (TTL)
Standby (CMOS)
Program
X
VIH
X
X
X
High-Z
High-Z
High-Z
DIN
X
X
X
VCC + 0.3 V
VIL
X
X
X
X
VIH
VIL
VIH
X
X
VPP
VPP
VPP
Program Verify
Program Inhibit
VIH
X
X
DOUT
VIH
X
X
High-Z
Manufacturer
Code
Auto Select
(Note 3)
VIL
VIL
VIL
VIL
VIL
VIH
VH
VH
X
X
01H
10H
Device Code
Notes:
1. VH = 12.0 V + 0.5 V
2. X = Either VIH or VIL
3. A1–A8 = A10–A14 = VIL
4. See DC Programming Characteristics for VPP voltage during programming.
2-38
Am27C256
AMD
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature
Commercial (C) Devices
OTP Products . . . . . . . . . . . . . . . –65°C to +125°C
All Other Products . . . . . . . . . . . . –65°C to +150°C
Ambient Temperature (TA) . . . . . . . 0°C to +70°C
Industrial (I) Devices
Ambient Temperature
with Power Applied . . . . . . . . . . . . . –55°C to +125°C
Ambient Temperature (TA) . . . . . –40°C to +85°C
Extended Commercial (E) Devices
Voltage with Respect To VSS
Ambient Temperature (TA) . . . . –55°C to +125°C
All pins except A9,VPP,VCC
(Note 1) . . . . . . . . . . . . . . . –0.6 V to VCC + 0.5 V
Supply Read Voltages
VCC for Am27C256-XX5 . . . . . +4.75 V to +5.25 V
A9 and VPP (Note 2) . . . . . . . . . . –0.6 V to +13.5 V
VCC . . . . . . . . . . . . . . . . . . . . . . . –0.6 V to +7.0 V
VCC for Am27C256-XX0 . . . . . +4.50 V to +5.50 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V. During
transitions, the inputs may overshoot VSS to –2.0 V for peri-
ods of up to 20 ns. Maximum DC voltage on input andI/O
pins is VCC + 0.5 V which may overshoot to VCC + 2.0 V for
periods up to 20 ns.
2. For A9 and VPP the minimum DC input is –0.5 V. During
transitions, A9 and VPP may overshoot VSS to –2.0 V for
periods of up to 20 ns. A9 and VPPmust not exceed 13.5 V
for any period of time.
Stresses above those listed under “Absolute Maximum Rat-
ings” may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these
or any other conditions above those indicated in the opera-
tional sections of this specification is not implied. Exposure of
the device to absolute maximum rating conditions for ex-
tended periods may affect device reliability.
2-39
Am27C256
AMD
DC CHARACTERISTICS over operating range unless otherwise specified.
(Notes 1, 2 and 4)
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
VOH
Output HIGH Voltage
IOH = –400 µA
2.4
V
VOL
VIH
VIL
ILI
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Leakage Current
IOL = 2.1 mA
0.45
VCC + 0.5
+0.8
1.0
V
V
2.0
–0.5
V
µA
VIN = 0 V to +VCC
C/I Devices
E Devices
1.0
ILO
VOUT = 0 V to +VCC
µA
5.0
25
mA
ICC1
VCC Active Current
(Note 3)
CE = VIL, f = 10 MHz,
IOUT = 0 mA
ICC2
ICC3
IPP1
VCC TTL Standby Current
CE = VIH
1.0
100
100
mA
µA
µA
VCC CMOS Standby Current CE = VCC ± 0.3 V
VPP Current During Read CE = OE = VIL, VPP = VCC
Notes:
1. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP.
2. Caution: The Am27C256 must not be removed from (or inserted into) a socket when VCC or VPP is applied.
3. ICC1 is tested with OE = VIH to simulate open outputs.
4. Minimum DC Input Voltage is –0.5 V. During transitions, the inputs may overshoot to –2.0 V for periods less than 20 ns.
Maximum DC Voltage on output pins is VCC + 0.5 V, which may overshoot to VCC + 2.0 V for periods less than 20 ns.
30
25
20
15
10
30
25
20
15
10
1
2
3
4
5
6
7
8
9
10
–75 –50 –25
0
25 50 75 100 125 150
Frequency in MHz
Temperature in °C
Figure 1. Typical Supply Current
vs. Frequency
Figure 2. Typical Supply Current
vs. Temperature
VCC = 5.5 V, T = 25°C
VCC = 5.5 V, f = 10 MHz
08007H-6
08007H-7
2-40
Am27C256
AMD
CAPACITANCE
CDV028
PL 032
PD 028
TS 032
Parameter
Symbol
Parameter
Description
Test
Conditions
Typ Max Typ Max Typ Max Typ Max Unit
CIN
Input Capacitance
Output Capacitance
VIN = 0
8
8
12
12
8
8
12
12
6
8
10
10
10
12
12
14
pF
pF
COUT
VOUT = 0
Notes:
1. This parameter is only sampled and not 100% tested.
2. TA = +25°C, f = 1 MHz.
SWITCHING CHARACTERISTICS over operating range unless otherwise specified
(Notes 1, 3 and 4)
Parameter
Symbols
Am27C256
Parameter
Test
JEDEC Standard Description
Conditions
-55
-70
-90
-120 -150
-200 -255 Unit
tAVQV
tACC
Address to
CE = OE = Min
–
–
–
–
–
–
–
Output Delay
VIL
Max 55
Min
Max 55
Min
Max 35
Min
Max 25
70
90
120
150
200
250
ns
ns
ns
tELQV
tGLQV
tCE
tOE
Chip Enable to
Output Delay
OE = VIL
–
–
70
–
90
–
120
–
150
–
200
–
250
Output Enable to
Output Delay
CE = VIL
–
–
40
–
40
–
50
–
50
–
50
–
50
tEHQZ,
tGHQZ
tDF
–
–
–
–
–
–
–
Chip Enable HIGH or
Output Enable HIGH,
whichever comes
(Note 2)
25
25
30
30
30
30
ns
first, to Output Float
tAXQX
tOH
Min
0
–
0
–
0
–
0
–
0
–
0
–
0
–
Output Hold from
Addresses, CE,
or OE, whichever
occurred first
Max
ns
Notes:
1. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP.
2. This parameter is only sampled and not 100% tested.
3. Caution: The Am27C256 must not be removed from (or inserted into) a socket or board when VPP or VCC is applied.
4. For the -55 and -70:
Output Load: 1 TTL gate and CL = 30 pF
Input Rise and Fall Times: 20 ns
Input Pulse Levels: 0 V to 3 V
Timing Measurement Reference Level: 1.5 V for inputs and outputs
For all other versions:
Output Load: 1 TTL gate and CL = 100 pF
Input Rise and Fall Times: 20 ns
Input Pulse Levels: 0.45 V to 2.4 V
Timing Measurement Reference Level: 0.8 V and 2 V inputs and outputs
2-41
Am27C256
AMD
SWITCHING TEST CIRCUIT
2.7 kΩ
Device
Under
Test
+5.0 V
Diodes = IN3064
or Equivalent
CL
6.2 kΩ
CL = 100 pF including jig capacitance (30 pF for -55, -70)
08007H-8
SWITCHING TEST WAVEFORM
2.4 V
3 V
0 V
2.0 V
0.8 V
2.0 V
0.8 V
Test Points
Test Points
1.5 V
Input
1.5 V
Output
0.45 V
Input
Output
08007H-9
AC Testing: Inputs are driven at 2.4 V for a logic “1”
and 0.45 V for a logic “0”. Input pulse
rise and fall times are ≤ 20 ns.
AC Testing: Inputs are driven at 3.0 V for a logic “1”
and 0 V for a logic “0”. Input pulse rise and
fall times are ≤ 20 ns for -55 and -70.
2-42
Am27C256
AMD
KEY TO SWITCHING TEST WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Must Be
Steady
Will Be
Steady
May
Change
from H to L
Will Be
Changing
from H to L
May
Change
from L to H
Will Be
Changing
from L to H
Don’t Care,
Any Change
Permitted
Changing
State
Unknown
Does Not
Apply
Center
Line is High
Impedence
“Off” State
KS000010
SWITCHING WAVEFORMS
2.4
2.0
0.8
2.0
0.8
Addresses Valid
Addresses
0.45
CE
OE
tCE
tDF
(Note 2)
tOE
tACC
(Note 1)
tOH
High Z
High Z
Output
Valid Output
Notes:
08007H-10
1. OE may be delayed up to tACC–tOE after the falling edge of the addresses without impact on tACC.
2. tDF is specified from OE or CE, whichever occurs first.
2-43
Am27C256
相关型号：
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