AM28F512A-90JIB [AMD]
512 Kilobit (64 K x 8-Bit) CMOS 12.0 Volt, Bulk Erase Flash Memory with Embedded Algorithms; 512千比特（一个64 K ×8位）的CMOS 12.0伏，整体擦除闪存与嵌入式算法
| 型号： | AM28F512A-90JIB |
| 厂家： | 
AMD |
| 描述： | 512 Kilobit (64 K x 8-Bit) CMOS 12.0 Volt, Bulk Erase Flash Memory with Embedded Algorithms |
| 文件： | 总34页 (文件大小：438K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FINAL
Am28F512A
512 Kilobit (64 K x 8-Bit)
CMOS 12.0 Volt, Bulk Erase Flash Memory with Embedded Algorithms
DISTINCTIVE CHARACTERISTICS
■ High performance
■ Embedded Erase Electrical Bulk Chip-Erase
— 70 ns maximum access time
— Two seconds typical chip-erase including
pre-programming
■ CMOS low power consumption
— 30 mA maximum active current
— 100 µA maximum standby current
— No data retention power consumption
■ Embedded Program
— 4 µs typical byte-program including time-out
— One second typical chip program
■ Command register architecture for
microprocessor/microcontroller compatible
write interface
■ Compatible with JEDEC-standard byte-wide
32-Pin EPROM pinouts
— 32-pin PDIP
■ On-chip address and data latches
— 32-pin PLCC
■ Advanced CMOS flash memory technology
— Low cost single transistor memory cell
— 32-pin TSOP
■ 100,000 write/erase cycles minimum
■ Write and erase voltage 12.0 V −5%
■ Embedded algorithms for completely
self-timed write/erase operations
■ Latch-up protected to 100 mA from -1 V
to VCC +1 V
GENERAL DESCRIPTION
The Am28F512A is a 512 Kbit Flash memory orga-
nized as 64 Kbytes of 8 bits each. AMD’s Flash memo-
ries offer the most cost-effective and reliable read/write
non- volatile random access memory. The Am28F512A
is packaged in 32-pin PDIP, PLCC, and TSOP versions.
It is designed to be reprogrammed and erased in-sys-
tem or in standard EPROM programmers. The
Am28F512A is erased when shipped from the factory.
programming mechanisms. In addition, the combina-
tion of advanced tunnel oxide processing and low inter-
nal electric fields for erase and programming
operations produces reliable cycling. The Am28F512A
uses a 12.0V±5% VPP high voltage input to perform
the erase and programming functions.
The highest degree of latch-up protection is achieved
with AMD’s proprietary non-epi process. Latch-up pro-
tection is provided for stresses up to 100 milliamps on
address and data pins from –1 V to VCC +1 V.
The standard Am28F512A offers access times as fast
as 70 ns, allowing operation of high-speed micropro-
cessors without wait states. To eliminate bus conten-
tion, the Am28F512A has separate chip enable (CE#)
and output enable (OE#) controls.
Embedded Program
The Am28F512A is byte programmable using the Em-
bedded Programming algorithm. The Embedded Pro-
gramming algorithm does not require the system to
time-out or verify the data programmed. The typical
room temperature programming time of the
Am28F512A is one second.
AMD’s Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
Am28F512A uses a command register to manage this
functionality, while maintaining a JEDEC Flash stan-
dard 32-pin pinout. The command register allows for
100% TTL level control inputs and fixed power supply
levels during erase and programming.
Embedded Erase
The entire chip is bulk erased using the Embedded
Erase algorithm. The Embedded Erase algorithm auto-
matically programs the entire array prior to electrical
erase. The timing and verification of electrical erase are
AMD’s Flash technology reliably stores memory con-
tents even after 100,000 erase and program cycles.
The AMD cell is designed to optimize the erase and
Publication# 18880 Rev: C Amendment/+2
Issue Date: April 1998
controlled internal to the device. Typical erasure at room
temperature is accomplished in two seconds, including
programming.
AMD’s Am28F512A is entirely pin and software com-
patible with AMD Am28F020A, Am28F010A, and
Am28F256A Flash memories.
Comparing Embedded Algorithms with Flasherase and Flashrite Algorithms
Am28F512A with
Embedded Algorithms
Am28F512 using AMD Flashrite
and Flasherase Algorithms
Embedded
Programming
Algorithm vs.
Flashrite
Programming
Algorithm
AMD’s Embedded Programming algorithm
requires the user to only write a program
set-up command and a program command
(program data and address). The device
automatically times the programming
pulse width, verifies the programming, and
counts the number of sequences. A status
bit, Data# Polling, provides the user with
the programming operation status.
The Flashrite Programming algorithm requires the
user to write a program set-up command, a program
command, (program data and address), and a
program verify command, followed by a read and
compare operation. The user is required to time the
programming pulse width in order to issue the
program verify command. An integrated stop timer
prevents any possibility of overprogramming.
Upon completion of this sequence, the data is read
back from the device and compared by the user with
the data intended to be written; if there is not a
match, the sequence is repeated until there is a
match or the sequence has been repeated 25 times.
Embedded Erase
Algorithm vs.
Flasherase Erase
Algorithm
AMD’s Embedded Erase algorithm
requires the user to only write an erase set- to be completely programmed prior to executing an
The Flasherase Erase algorithm requires the device
up command and erase command. The
device automatically pre-programs and
verifies the entire array. The device then
automatically times the erase pulse width,
verifies the erase operation, and counts
the number of sequences. A status bit,
Data# Polling, provides the user with the
erase operation status.
erase command.
To invoke the erase operation, the user writes an
erase set-up command, an erase command, and an
erase verify command. The user is required to time
the erase pulse width in order to issue the erase
verify command. An integrated stop timer prevents
any possibility of overerasure.
Upon completion of this sequence, the data is read
back from the device and compared by the user with
erased data. If there is not a match, the sequence is
repeated until there is a match or the sequence has
been repeated 1,000 times.
Commands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as inputs to an internal state-machine
which controls the erase and programming circuitry.
During write cycles, the command register internally
latches address and data needed for the program-
ming and erase operations. For system design simpli-
fication, the Am28F512A is designed to support either
WE# or CE controlled writes. During a system write
cycle, addresses are latched on the falling edge of
WE# or CE# whichever occurs last. Data is latched on
the rising edge of WE# or CE# whichever occurs first.
To simplify the following discussion, the WE# pin is
used as the write cycle control pin throughout the rest
of this text. All setup and hold times are with respect
to the WE# signal.
AMD’s Flash technology combines years of EPROM
and EEPROM experience to produce the highest lev-
els of quality, reliability, and cost effectiveness. The
Am28F512A electrically erases all bits simulta-
neously using Fowler-Nordheim tunneling. The bytes
are programmed one byte at a time using the EPROM
programming mechanism of hot electron injection.
2
Am28F512A
BLOCK DIAGRAM
DQ0–DQ7
V
V
CC
SS
Input/Output
Buffers
Erase Voltage
Switch
V
PP
To Array
State
WE#
Control
Command
Register
Program
Voltage Switch
Data
Latch
Chip Enable
Output Enable
Logic
CE#
OE#
Embedded
Algorithms
Y-Decoder
X-Decoder
Y-Gating
Program/Erase
Pulse Timer
Low V
Detector
CC
524,288
Bit Cell Matrix
A0–A15
18880C-1
PRODUCT SELECTOR GUIDE
Family Part Number
Am28F512A
Speed Options (V = 5.0 V ±10%)
-70
70
70
35
-90
90
90
35
-120
120
120
50
-150
150
150
55
-200
200
200
55
CC
Max Access Time (ns)
CE# (E#) Access (ns)
OE# (G#) Access (ns)
Am28F512A
3
CONNECTION DIAGRAMS
PDIP
PLCC
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
V
PP
NC
A15
A12
A7
2
WE# (W#)
NC
3
4
31 30
1 32
2
3
A7
A6
5
6
A14
A13
29
28
4
A14
5
A13
A5
A4
7
A8
27
26
25
24
23
22
21
A6
6
A8
8
A9
A5
7
A9
A3
9
A11
A4
8
A11
A2
10
11
12
13
OE# (G#)
A10
A3
9
OE# (G#)
A10
A1
A2
10
11
12
13
14
15
16
A0
CE (E#)
DQ7
DQ0
A1
CE# (E#)
DQ7
16 17
19 20
18
15
14
A0
DQ0
DQ6
DQ1
DQ2
DQ5
DQ4
DQ3
18880C-3
V
SS
18880C-2
Note: Pin 1 is marked for orientation.
4
Am28F512A
CONNECTION DIAGRAMS (Continued)
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
A13
A14
NC
OE#
A10
CE#
D7
D6
D5
WE#
D4
D3
V
CC
9
V
V
PP
SS
10
11
12
13
14
15
16
NC
A15
A12
A7
A6
A5
D2
D1
D0
A0
A1
A2
A3
A4
32-Pin TSOP—Standard Pinout
OE#
A10
CE#
D7
D6
D5
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
A13
A14
NC
D4
D3
WE#
V
V
CC
V
9
SS
PP
D2
D1
D0
A0
A1
A2
A3
10
11
12
13
14
15
16
NC
A15
A12
A7
A6
A5
A4
32-Pin TSOP—Reverse Pinout
18880C-4
LOGIC SYMBOL
16
8
A0–A15
DQ0–DQ7
CE# (E#)
OE# (G#)
WE# (W#)
18880C-5
Am28F512A
5
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of:
AM28F512A
-70
J
C
B
OPTIONAL PROCESSING
Blank = Standard Processing
B
= Burn-In
Contact an AMD representative for more information.
TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
E = Extended (–55°C to +125°C)
PACKAGE TYPE
P = 32-Pin Plastic DIP (PD 032)
J = 32-Pin Rectangular Plastic Leaded Chip
Carrier (PL 032)
E = 32-Pin Thin Small Outline Package (TSOP)
Standard Pinout (TS 032)
F = 32-Pin Thin Small Outline Package (TSOP)
Reverse Pinout (TSR032)
SPEED OPTION
See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION
Am28F512A
512 Kilobit (64 K x 8-Bit) 12.0 Volt CMOS Flash Memory with Embedded Algorithms
Valid Combinations
Valid Combinations
Valid Combinations list configurations planned to be sup-
ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
AM28F512A-70
AM28F512A-90
AM28F512A-120
AM28F512A-150
AM28F512A-200
PC, PI, PE,
JC, JI, JE,
EC, EI, EE,
FC, FI, FE
6
Am28F512A
PIN DESCRIPTION
VCC
Power supply for device operation. (5.0 V ± 5% or 10%)
A0–A15
Address Inputs for memory locations. Internal latches
hold addresses during write cycles.
VPP
Program voltage input. VPP must be at high voltage in
order to write to the command register. The command
register controls all functions required to alter the mem-
ory array contents. Memory contents cannot be altered
when VPP ≤ VCC +2 V.
CE# (E#)
Chip Enable active low input activates the chip’s con-
trol logic and input buffers. Chip Enable high will dese-
lect the device and operates the chip in stand-by mode.
VSS
DQ0–DQ7
Ground.
Data Inputs during memory write cycles. Internal
latches hold data during write cycles. Data Outputs
during memory read cycles.
WE# (W#)
Write Enable active low input controls the write function
of the command register to the memory array. The tar-
get address is latched on the falling edge of the Write
Enable pulse and the appropriate data is latched on the
rising edge of the pulse. Write Enable high inhibits
writing to the device.
NC
No Connect-corresponding pin is not connected
internally to the die.
OE# (G#)
Output Enable active low input gates the outputs of the
device through the data buffers during memory read
cycles. Output Enable is high during command
sequencing and program/erase operations.
Am28F512A
7
BASIC PRINCIPLES
This section contains descriptions about the device
read, erase, and program operations, and write opera-
tion status of the Am29FxxxA, 12.0 volt family of Flash
devices. References to some tables or figures may be
given in generic form, such as “Command Definitions
table”, rather than “Table 1”. Refer to the corresponding
data sheet for the actual table or figure.
Embedded Programming Algorithm
AMD now makes programming extremely simple and
reliable. The Embedded Programming algorithm re-
quires the user to only write a program setup command
and a program command. The device automatically
times the programming pulse width, provides the pro-
gram verify and counts the number of sequences. A
status bit, Data# Polling, provides feedback to the user
as to the status of the programming operation.
The Am28FxxxA family uses 100% TTL-level control
inputs to manage the command register. Erase and
reprogramming operations use a fixed 12.0 V ± 5%
high voltage input.
DATA PROTECTION
The device is designed to offer protection against acci-
dental erasure or programming caused by spurious
system level signals that may exist during power transi-
tions. The device powers up in its read only state. Also,
with its control register architecture, alteration of the
memory contents only occurs after successful comple-
tion of specific command sequences.
Read Only Memory
Without high VPP voltage, the device functions as a
read only memory and operates like a standard
EPROM. The control inputs still manage traditional
read, standby, output disable, and Auto select modes.
Command Register
The device also incorporates several features to pre-
vent inadvertent write cycles resulting from VCC
power-up and power-down transitions or system noise.
The command register is enabled only when high volt-
age is applied to the V
pin. The erase and repro-
PP
gramming operations are only accessed via the
register. In addition, two-cycle commands are required
for erase and reprogramming operations. The tradi-
tional read, standby, output disable, and Auto select
modes are available via the register.
Low VCC Write Inhibit
To avoid initiation of a write cycle during VCC power-up
and power-down, the device locks out write cycles for
VCC < VLKO (see DC characteristics section for volt-
ages). When VCC < VLKO, the command register is dis-
abled, all internal program/erase circuits are disabled,
and the device resets to the read mode. The device ig-
nores all writes until VCC > VLKO. The user must ensure
that the control pins are in the correct logic state when
VCC > VLKO to prevent unintentional writes.
The device’s command register is written using standard
microprocessor write timings. The register controls an
internal state machine that manages all device opera-
tions. For system design simplification, the device is de-
signed to support either WE# or CE# controlled writes.
During a system write cycle, addresses are latched on
the falling edge of WE# or CE# whichever occurs last.
Data is latched on the rising edge of WE# or CE# which-
ever occur first. To simplify the following discussion, the
WE# pin is used as the write cycle control pin throughout
the rest of this text. All setup and hold times are with re-
spect to the WE# signal.
Write Pulse “Glitch” Protection
Noise pulses of less than 10 ns (typical) on OE#, CE#
or WE# will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of OE# = VIL,
CE#=VIH or WE# = VIH. To initiate a write cycle CE#
and WE# must be a logical zero while OE# is a logical
one.
OVERVIEW OF ERASE/PROGRAM
OPERATIONS
Embedded Erase Algorithm
Power-Up Write Inhibit
AMD now makes erasure extremely simple and reli-
able. The Embedded Erase algorithm requires the user
to only write an erase setup command and erase com-
mand. The device will automatically pre-program and
verify the entire array. The device automatically times
the erase pulse width, provides the erase verify and
counts the number of sequences. A status bit, Data#
Polling, provides feedback to the user as to the status
of the erase operation.
Power-up of the device with WE# = CE# = VIL and
OE# = V will not accept commands on the rising
IH
edge of WE#. The internal state machine is automati-
cally reset to the read mode on power-up.
8
Am28F512A
FUNCTIONAL DESCRIPTION
Description Of User Modes
Table 1. Am28F512A Device Bus Operations (Notes 7 and 8)
CE#
(E#)
OE#
(G#)
WE#
(W#) (Note 1)
V
PP
Operation
Read
A0
A0
X
A9
A9
X
I/O
V
V
X
X
V
V
V
D
OUT
IL
IL
PPL
PPL
PPL
Standby
V
X
HIGH Z
IH
Output Disable
V
V
V
V
X
X
HIGH Z
IL
IL
IH
IH
Read-Only
Auto-select Manufacturer
Code (Note 2)
V
CODE
(01h)
ID
V
V
V
V
IL
IH
PPL
PPL
IL
(Note 3)
Auto-select Device
Code (Note 2)
V
CODE
(AEh)
ID
V
V
V
V
V
V
V
V
V
IL
IL
IL
IL
IH
IH
(Note 3)
Read
A0
A9
D
IH
PPH
OUT
(Note 4)
Standby (Note 5)
Read/Write
V
X
X
V
V
V
X
X
X
X
HIGH Z
HIGH Z
IH
PPH
PPH
PPH
Output Disable
V
V
V
V
IL
IL
IH
IH
IH
Write
V
V
A0
A9
D
IL
IN
(Note 6)
Legend:
X = Don’t care, where Don’t Care is either V or V levels. V
= V < V + 2 V. See DC Characteristics for voltage levels
PP CC
IL
IH
PPL
of V
. 0 V < An < V + 2 V, (normal TTL or CMOS input levels, where n = 0 or 9).
PPH
CC
Notes:
1. V
may be grounded, connected with a resistor to ground, or < V + 2.0 V. V
is the programming voltage specified for
PPL
CC
PPH
the device. Refer to the DC characteristics. When V = V
, memory contents can be read but not written or erased.
PP
PPL
2. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 2.
3. 11.5 < V < 13.0 V. Minimum V rise time and fall time (between 0 and V voltages) is 500 ns.
ID
ID
ID
4. Read operation with V = V
may access array data or the Auto select codes.
PP
PPH
5. With V at high voltage, the standby current is I + I (standby).
PP
CC
PP
6. Refer to Table 3 for valid D during a write operation.
IN
7. All inputs are Don’t Care unless otherwise stated, where Don’t Care is either V or V levels. In the Auto select mode all
IL
IH
addresses except A and A must be held at V .
9
0
IL
8. If V ≤ 1.0 Volt, the voltage difference between V and V should not exceed 10.0 volts. Also, the Am28F256 has a V
CC
PP
CC
PP
rise time and fall time specification of 500 ns minimum.
Am28F512A
9
READ-ONLY MODE
When VPP is less than VCC + 2 V, the command register
is inactive. The device can either read array or autose-
lect data, or be standby mode.
Output Disable
Output from the device is disabled when OE# is at a
logic high level. When disabled, output pins are in a
high impedance state.
Read
The device functions as a read only memory when VPP
< VCC + 2 V. The device has two control functions. Both
must be satisfied in order to output data. CE# controls
power to the device. This pin should be used for spe-
cific device selection. OE# controls the device outputs
and should be used to gate data to the output pins if a
device is selected.
Auto Select
Flash memories can be programmed in-system or in a
standard PROM programmer. The device may be sol-
dered to the circuit board upon receipt of shipment and
programmed in-system. Alternatively, the device may
initially be programmed in a PROM programmer prior
to soldering the device to the board.
Address access time tACC is equal to the delay from
stable addresses to valid output data. The chip enable
access time tCE is the delay from stable addresses and
stable CE# to valid data at the output pins. The output
enable access time is the delay from the falling edge of
OE# to valid data at the output pins (assuming the ad-
dresses have been stable at least tACC - tOE).
The Auto select mode allows the reading out of a binary
code from the device that will identify its manufacturer and
type. This mode is intended for the purpose of automati-
cally matching the device to be programmed with its cor-
responding programming algorithm. This mode is
functional over the entire temperature range of the device.
Programming In A PROM Programmer
Standby Mode
To activate this mode, the programming equipment
must force VID (11.5 V to 13.0 V) on address A9. Two
identifier bytes may then be sequenced from the device
outputs by toggling address A0 from VIL to VIH. All other
address lines must be held at VIL, and VPP must be
less than or equal to VCC + 2.0 V while using this Auto
select mode. Byte 0 (A0 = VIL) represents the manufac-
turer code and byte 1 (A0 = VIH) the device identifier
code. For the device the two bytes are given in the table
2 of the device data sheet. All identifiers for manufac-
turer and device codes will exhibit odd parity with the
MSB (DQ7) defined as the parity bit.
The device has two standby modes. The CMOS
standby mode (CE# input held at VCC ± 0.5 V), con-
sumes less than 100 µA of current. TTL standby mode
(CE# is held at VIH) reduces the current requirements
to less than 1 mA. When in the standby mode the out-
puts are in a high impedance state, independent of the
OE# input.
If the device is deselected during erasure, program-
ming, or program/erase verification, the device will
draw active current until the operation is terminated.
Table 2. Am28F512A Auto Select Code
Code
(HEX)
Type
A0
Manufacturer Code
Device Code
V
01
IL
V
AE
IH
10
Am28F512A
ERASE, PROGRAM, AND READ MODE
When VPP is equal to 12.0 V ± 5%, the command reg-
ister is active. All functions are available. That is, the
device can program, erase, read array or autoselect
data, or be standby mode.
Refer to AC Write Characteristics and the Erase/Pro-
gramming Waveforms for specific timing parameters.
Command Definitions
The contents of the command register default to 00h
(Read Mode) in the absence of high voltage applied to
the VPP pin. The device operates as a read only
memory. High voltage on the VPP pin enables the
command register. Device operations are selected by
writing specific data codes into the command register.
Table 3 in the device data sheet defines these register
commands.
Write Operations
High voltage must be applied to the V pin in order to
PP
activate the command register. Data written to the reg-
ister serves as input to the internal state machine. The
output of the state machine determines the operational
function of the device.
The command register does not occupy an address-
able memory location. The register is a latch that stores
the command, along with the address and data infor-
mation needed to execute the command. The register
is written by bringing WE# and CE# to VIL, while OE#
is at VIH. Addresses are latched on the falling edge of
WE#, while data is latched on the rising edge of the
WE# pulse. Standard microprocessor write timings are
used.
Read Command
Memory contents can be accessed via the read com-
mand when VPP is high. To read from the device, write
00h into the command register. Standard microproces-
sor read cycles access data from the memory. The de-
vice will remain in the read mode until the command
register contents are altered.
The command register defaults to 00h (read mode)
upon VPP power-up. The 00h (Read Mode) register de-
fault helps ensure that inadvertent alteration of the
memory contents does not occur during the VPP power
transition. Refer to the AC Read Characteristics and
Waveforms for the specific timing parameters.
The device requires the OE# pin to be VIH for write op-
erations. This condition eliminates the possibility for
bus contention during programming operations. In
order to write, OE# must be VIH, and CE# and WE#
must be VIL. If any pin is not in the correct state a write
command will not be executed.
Table 3. Am28F512A Command Definitions
First Bus Cycle
Second Bus Cycle
Operation
(Note 1)
Address
(Note 2)
Data
(Note 3)
Operation
(Note 1)
Address
(Note 2)
Data
(Note 3)
Command
Read Memory (Note 4)
Read Auto select
Write
Write
X
X
00h/FFh
Read
Read
RA
RD
80h or 90h
00h/01h
01h/AEh
Embedded Erase Set-up/
Embedded Erase
Write
X
30h
Write
X
30h
Embedded Program Set-up/
Embedded Program
Write
Write
X
X
10h or 50h
00h/FFh
Write
Write
PA
X
PD
Reset (Note 4)
00h/FFh
Notes:
1. Bus operations are defined in Table 1.
2. RA = Address of the memory location to be read.
PA = Address of the memory location to be programmed.
Addresses are latched on the falling edge of the WE# pulse.
X = Don’t care.
3. RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data latched on the rising edge of WE#.
4. Please reference Reset Command section.
Am28F512A
11
FLASH MEMORY PROGRAM/ERASE
OPERATIONS
has been achieved for the memory array (no erase ver-
ify command is required). The margin voltages are in-
ternally generated in the same manner as when the
standard erase verify command is used.
Embedded Erase Algorithm
The automatic chip erase does not require the device
to be entirely pre-programmed prior to executing the
Embedded set-up erase command and Embedded
erase command. Upon executing the Embedded erase
command the device automatically will program and
verify the entire memory for an all zero data pattern.
The system is not required to provide any controls or
timing during these operations.
The Embedded Erase Set-Up command is a command
only operation that stages the device for automatic
electrical erasure of all bytes in the array. Embedded
Erase Setup is performed by writing 30h to the com-
mand register.
When the device is automatically verified to contain an
all zero pattern, a self-timed chip erase and verify be-
gin. The erase and verify operation are complete when
the data on DQ7 is “1" (see Write Operation Status sec-
tion) atwhich time the device returns to Read mode.
The system is not required to provide any control or
timing during these operations.
To commence automatic chip erase, the command 30h
must be written again to the command register. The au-
tomatic erase begins on the rising edge of the WE and
terminates when the data on DQ7 is “1" (see Write Op-
eration Status section) at which time the device returns
to Read mode.
Figure 1 and Table 4 illustrate the Embedded Erase al-
gorithm, a typical command string and bus operation.
When using the Embedded Erase algorithm, the erase
automatically terminates when adequate erase margin
START
Apply V
PPH
Write Embedded Erase Setup Command
Write Embedded Erase Command
Data# Poll from Device
Erasure Completed
18880C-6
Figure 1. Embedded Erase Algorithm
Table 4. Embedded Erase Algorithm
Command
Bus Operations
Standby
Comments
(see Note)
PPH
Wait for V Ramp to V
PP
Embedded Erase Setup Command Data = 30h
Embedded Erase Command Data = 30h
Write
Read
Data# Polling to Verify Erasure
Compare Output to FFh
Standby
Read
Available for Read Operations
Note: See AC and DC Characteristics for values of V parameters. The V power supply can be hard-wired to the device or
PP
PP
switchable. When V is switched, V
may be ground, no connect with a resistor tied to ground, or less than V + 2.0 V. Refer
PP
PPL
CC
to Functional Description.
12
Am28F512A
of WE# also begins the programming operation. The
system is not required to provide further controls or
timings. The device will automatically provide an ade-
quate internally generated program pulse and verify
margin. The automatic programming operation is
completed when the data on DQ7 is equivalent to data
written to this bit (see Write Operation Status section)
at which time the device returns to Read mode.
Embedded Programming Algorithm
The Embedded Program Setup is a command only op-
eration that stages the device for automatic program-
ming. Embedded Program Setup is performed by
writing 10h or 50h to the command register.
Once the Embedded Setup Program operation is per-
formed, the next WE# pulse causes a transition to an
active programming operation. Addresses are latched
on the falling edge of CE# or WE# pulse, whichever
happens later. Data is latched on the rising edge of
WE# or CE#, whichever happens first. The rising edge
Figure 2 and Table 5 illustrate the Embedded Program
algorithm, a typical command string, and bus operation.
START
Apply V
PPH
Write Embedded Setup Program Command
Write Embedded Program Command (A/D)
Data# Poll Device
No
Increment Address
Last Address
Yes
Programming Completed
18880C-7
Figure 2. Embedded Programming Algorithm
Table 5. Embedded Programming Algorithm
Bus Operations
Standby
Command
Comments
(see Note)
PPH
Wait for V Ramp to V
PP
Write
Write
Read
Read
Embedded Program Setup Command Data = 10h or 50h
Embedded Program Command Valid Address/Data
Data# Polling to Verify Completion
Available for Read Operations
Note: See AC and DC Characteristics for values of V parameters. The V power supply can be hard-wired to the device or
PP
PP
switchable. When V is switched, V
may be ground, no connect with a resistor tied to ground, or less than V + 2.0 V. Refer
PP
PPL
CC
to Functional Description. Device is either powered-down, erase inhibit or program inhibit.
Am28F512A
13
While the Embedded Erase algorithm is in operation,
DQ7 will read “0" until the erase operation is com-
pleted. Upon completion of the erase operation, the
data on DQ7 will read “1.” The Data# Polling feature is
valid after the rising edge of the second WE# pulse of
the two Write pulse sequence.
Write Operation Status
Data Polling—DQ7
The device features Data# Polling as a method to indi-
cate to the host system that the Embedded algorithms
are either in progress or completed.
While the Embedded Programming algorithm is in oper-
ation, an attempt to read the device at a valid address
will produce the complement of expected Valid data on
DQ7. Upon completion of the Embedded Program algo-
rithm an attempt to read the device at a valid address will
produce Valid data on DQ7. The Data# Polling feature is
valid after the rising edge of the second WE# pulse of
the two write pulse sequence.
The Data# Polling feature is only active during Embed-
ded Programming or erase algorithms.
See Figures 3 and 4 for the Data# Polling timing spec-
ifications and diagrams. Data# Polling is the standard
method to check the write operation status, however,
an alternative method is available using Toggle Bit.
START
Read Byte
(DQ0–DQ7)
Addr = VA
VA = Byte address for programming
= XXXXh during chip erase
Yes
DQ7 = Data
?
No
No
DQ5 = 1
?
Yes
Read Byte
(DQ0–DQ7)
Addr = VA
Yes
DQ7 = Data
?
No
Fail
Pass
18880C-8
Note:
DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5 or after DQ5.
Figure 3. Data# Polling Algorithm
14
Am28F512A
t
CH
CE#
t
DF
t
OE
OE#
WE#
t
OEH
t
CE
t
OH
*
High Z
DQ7 =
Valid Data
DQ7
DQ7#
t
WHWH 3 or 4
DQ0–DQ7
Valid Data
DQ0–DQ6
DQ0–DQ6 = Invalid
18880C-9
*DQ7 = Valid Data (The device has completed the Embedded operation.)
Figure 4. AC Waveforms for Data# Polling during Embedded Algorithm Operations
Am28F512A
15
Toggle Bit—DQ6
toggling to indicate the completion of either Embedded
operation. Only on the next read cycle will valid data be
obtained. The toggle bit is valid after the rising edge of
the first WE# pulse of the two write pulse sequence, un-
like Data# Polling which is valid after the rising edge of
the second WE# pulse. This feature allows the user to
determine if the device is partially through the two write
pulse sequence.
The device also features a “Toggle Bit” as a method to
indicate to the host system that the Embedded algo-
rithms are either in progress or completed.
Successive attempts to read data from the device at a
valid address, while the Embedded Program algorithm
is in progress, or at any address while the Embedded
Erase algorithm is in progress, will result in DQ6 tog-
gling between one and zero. Once the Embedded Pro-
gram or Erase algorithm is completed, DQ6 will stop
See Figures 5 and 6 for the Toggle Bit timing specifica-
tions and diagrams.
START
VA = Byte address for programming
= XXXXh during chip erase
Read Byte
(DQ0–DQ7)
Addr = VA
No
DQ6 = Toggle
?
Yes
No
DQ5 = 1
?
Yes
Read Byte
(DQ0–DQ7)
Addr = VA
No
DQ6 = Toggle
?
Yes
Fail
Pass
18880C-10
Note:
DQ6 is rechecked even if DQ5 = “1” because DQ6 may stop toggling at the same time as DQ5 changing to “1”.
Figure 5. Toggle Bit Algorithm
16
Am28F512A
CE#
t
OEH
WE#
OE#
*
DQ6
Stop Toggling
Data
DQ0–DQ7
DQ0–DQ7
Valid
DQ6 =
DQ6 =
t
OE
18880C-11
Note:
*DQ6 stops toggling (The device has completed the Embedded operation.)
Figure 6. AC Waveforms for Toggle Bit during Embedded Algorithm Operations
Power-Up/Power-Down Sequence
DQ5
The device powers-up in the Read only mode. Power
supply sequencing is not required. Note that if VCC
1.0 Volt, the voltage difference between VPP and VCC
should not exceed 10.0 Volts. Also, the device has a
Exceeded Timing Limits
≤
DQ5 will indicate if the program or erase time has
exceeded the specified limits. This is a failure condi-
tion and the device may not be used again (internal
pulse count exceeded). Under these conditions DQ5
will produce a “1.” The program or erase cycle was not
successfully completed. Data# Polling is the only op-
erating function of the device under this condition. The
CE# circuit will partially power down the device under
these conditions (to approximately 2 mA). The OE#
and WE# pins will control the output disable functions
as described in the Command Definitions table in the
corresponding device data sheet.
rise V rise time and fall time specification of 500 ns
PP
minimum.
Reset Command
The Reset command initializes the Flash memory de-
vice to the Read mode. In addition, it also provides the
user with a safe method to abort any device operation
(including program or erase).
The Reset must be written two consecutive times after
the Setup Program command (10h or 50h). This will
reset the device to the Read mode.
Parallel Device Erasure
The Embedded Erase algorithm greatly simplifies par-
allel device erasure. Since the erase process is internal
to the device, a single erase command can be given to
multiple devices concurrently. By implementing a paral-
lel erase algorithm, total erase time may be minimized.
Following any other Flash command, write the Reset
command once to the device. This will safely abort any
previous operation and initialize the device to the Read
mode.
The Setup Program command (10h or 50h) is the only
command that requires a two-sequence reset cycle. The
first Reset command is interpreted as program data.
However, FFh data is considered as null data during pro-
gramming operations (memory cells are only pro-
grammed from a logical “1" to “0"). The second Reset
command safely aborts the programming operation and
resets the device to the Read mode.
Note that the Flash memories may erase at different
rates. If this is the case, when a device is completely
erased, use a masking code to prevent further erasure
(over-erasure). The other devices will continue to erase
until verified. The masking code applied could be the
read command (00h).
Memory contents are not altered in any case.
Am28F512A
17
This detailed information is for your reference. It may
prove easier to always issue the Reset command two
consecutive times. This eliminates the need to deter-
mine if you are in the Setup Program state or not.
in-system, manufacturer and device codes must be
accessible while the device resides in the target
system. PROM programmers typically access the sig-
nature codes by raising A9 to a high voltage. However,
multiplexing high voltage onto address lines is not a
generally desired system design practice.
In-System Programming Considerations
Flash memories can be programmed in-system or in a
standard PROM programmer. The device may be sol-
dered to the circuit board upon receipt of shipment and
programmed in-system. Alternatively, the device may
initially be programmed in a PROM programmer prior
to soldering the device to the circuit board.
The device contains an Auto Select operation to supple-
ment traditional PROM programming methodologies.
The operation is initiated by writing 80h or 90h into the
command register. Following this command, a read
cycle address 0000h retrieves the manufacturer code of
01h (AMD). A read cycle from address 0001h returns
the device code (see the Auto Select Code table of the
corresponding device data sheet). To terminate the op-
eration, it is necessary to write another valid command,
such as Reset (00h or FFh), into the register.
Auto Select Command
AMD’s Flash memories are designed for use in appli-
cations where the local CPU alters memory contents.
In order to correctly program any Flash memories
18
Am28F512A
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . . –65°C to +150°C
Plastic Packages . . . . . . . . . . . . . . . –65°C to +125°C
Commercial (C) Devices
Ambient Temperature (TA) . . . . . . . . . . .0°C to +70°C
Industrial (I) Devices
Ambient Temperature
with Power Applied. . . . . . . . . . . . . .–55°C to + 125°C
Ambient Temperature (TA) . . . . . . . . .–40°C to +85°C
Extended (E) Devices
Voltage with Respect To Ground
All pins except A9 and VPP
Ambient Temperature (TA) . . . . . . . .–55°C to +125°C
VCC Supply Voltages
(Note 1) . . . . . . . . . . . . . . . . . . . . . . .–2.0 V to +7.0 V
V
CC (Note 1). . . . . . . . . . . . . . . . . . . .–2.0 V to +7.0 V
VCC . . . . . . . . . . . . . . . . . . . . . . . +4.50 V to +5.50 V
VPP Voltages
A9 (Note 2). . . . . . . . . . . . . . . . . . . .–2.0 V to +14.0 V
VPP (Note 2). . . . . . . . . . . . . . . . . . .–2.0 V to +14.0 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Read . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +12.6 V
Program, Erase, and Verify. . . . . . +11.4 V to +12.6 V
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V. During
Operating ranges define those limits between which the
functionality of the device is guaranteed.
voltage transitions, inputs may overshoot V to –2.0 V
SS
for periods of up to 20 ns. Maximum DC voltage on input
and I/O pins is V
+ 0.5 V. During voltage transitions,
CC
input and I/O pins may overshoot to V
periods up to 20ns.
+ 2.0 V for
CC
2. Minimum DC input voltage on A9 and V pins is –0.5 V.
PP
During voltage transitions, A9 and V
may overshoot
PP
V
to –2.0 V for periods of up to 20 ns. Maximum DC
SS
input voltage on A9 and V
is +13.0 V which may
PP
overshoot to 14.0 V for periods up to 20 ns.
3. No more than one output shorted to ground at a time.
Duration of the short circuit should not be greater than
one second.
Stresses above those listed under “Absolute Maximum Rat-
ings” may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these
or any other conditions above those indicated in the opera-
tional sections of this specification is not implied. Exposure of
the device to absolute maximum rating conditions for
extended periods may affect device reliability.
Am28F512A
19
MAXIMUM OVERSHOOT
20 ns
20 ns
+0.8 V
–0.5 V
–2.0 V
20 ns
18880C-12
18880C-13
18880C-14
Maximum Negative Input Overshoot
20 ns
V
+ 2.0 V
CC
V
+ 0.5 V
2.0 V
CC
20 ns
20 ns
Maximum Positive Input Overshoot
20 ns
14.0 V
13.5 V
V
+ 0.5 V
CC
20 ns
20 ns
Maximum VPP Overshoot
20
Am28F512A
DC CHARACTERISTICS over operating range unless otherwise specified
TTL/NMOS Compatible
Parameter
Symbol
Parameter Description
Input Leakage Current
Test Conditions
= V Max, V = V or V
SS
Min
Typ
Max
±1.0
±1.0
1.0
Unit
µA
I
V
V
V
V
LI
CC
CC
CC
CC
IN
CC
I
Output Leakage Current
= V Max, V
= V or V
SS
µA
LO
CC
OUT
CC
I
V
Standby Current
= V Max, CE# = V
IH
0.2
20
mA
CCS
CC
CC
CC
V
Max, CE# = V OE# = V
IL, IH
CC = CC
I
I
V
Active Read Current
30
30
30
mA
mA
CC1
CC2
I
= 0 mA, at 6 MHz
OUT
CE# = V
IL
V
Programming Current
20
20
CC
Programming in Progress (Note 4)
CE# = V
IL
I
I
V
V
Erase Current
mA
µA
CC3
PPS
CC
Erasure in Progress (Note 4)
Standby Current
V
V
V
V
= V
= V
= V
= V
±1.0
200
PP
PP
PP
PP
PP
PPL
PPH
PPL
PPH
70
I
V
Read Current
µA
PP1
PP
±1.0
I
I
V
V
Programming Current
Erase Current
10
10
30
mA
mA
PP2
PP3
PP
Programming in Progress (Note 4)
V
= V
PP
PPH
30
PP
Erasure in Progress (Note 4)
V
Input Low Voltage
–0.5
2.0
0.8
V
V
IL
V
Input High Voltage
V
+ 0.5
IH
CC
V
Output Low Voltage
Output High Voltage
A9 Auto Select Voltage
A9 Auto Select Current
I
I
= 5.8 mA, V = V Min
0.45
V
OL
OL
CC
CC
V
= –2.5 mA, V = V Min
2.4
V
OH1
OH
CC
CC
V
A9 = V
11.5
13.0
50
V
ID
ID
I
A9 = V Max, V = V Max
5
µA
ID
ID
CC
CC
V
during Read-Only
Note: Erase/Program are inhibited
when V = V
PP
V
0.0
V
+2.0
CC
V
PPL
Operations
PP
PPL
V
during Read/Write
PP
V
V
11.4
3.2
12.6
V
V
PPH
Operations
Low V Lock-out Voltage
3.7
LKO
CC
Notes:
1. Caution: The Am28F512A must not be removed from (or inserted into) a socket when V or V is applied. If V ≤ 1.0
CC
PP
CC
volt, the voltage difference between V and V should not exceed 10.0 volts. Also, the Am28F512A has a V rise time
PP
CC
PP
and fall time specification of 500 ns minimum.
2. I
is tested with OE# = V to simulate open outputs.
IH
CC1
3. Maximum active power usage is the sum of I and I
.
PP
CC
4. Not 100% tested.
Am28F512A
21
DC CHARACTERISTICS
CMOS Compatible
Parameter
Symbol
Parameter Description
Test Conditions
= V Max, V = V or V
SS
Min
Typ
Max
±1.0
±1.0
100
Unit
µA
I
Input Leakage Current
V
V
V
V
LI
CC
CC
CC
CC
IN
CC
I
Output Leakage Current
= V Max, V
= V or V
SS
µA
LO
CC
OUT
CC
I
V
Standby Current
= V Max, CE# = V + 0.5 V
15
20
µA
CCS
CC
CC
CC
CC
= V Max, CE# = V OE# = V
IH
CC
CC
IL,
I
I
V
Active Read Current
30
30
30
mA
mA
mA
CC1
CC2
I
= 0 mA, at 6 MHz
OUT
CE# = V
IL
V
V
Programming Current
Erase Current
20
20
CC
CC
Programming in Progress (Note 4)
CE# = V
IL
I
I
CC3
PPS
Erasure in Progress (Note 4)
V
V
Standby Current
Read Current
V
V
V
= V
= V
= V
±1.0
µA
µA
PP
PP
PP
PP
PPL
PPH
PPH
I
I
70
10
200
PP1
PP2
PP
V
Programming Current
Erase Current
30
mA
mA
PP
PP
Programming in Progress (Note 4)
V
= V
PP
PPH
I
V
10
30
PP3
Erasure in Progress (Note 4)
V
Input Low Voltage
Input High Voltage
Output Low Voltage
–0.5
0.8
V
V
V
IL
V
0.7 V
V
+ 0.5
CC
IH
CC
V
I
I
I
= 5.8 mA, V = V Min
0.45
OL
OL
OH
OH
CC
CC
V
V
= –2.5 mA, V = V Min
0.85 V
CC
OH1
OH2
CC
CC
Output High Voltage
V
= –100 µA, V = V Min
V
–0.4
CC
CC
CC
V
A9 Auto Select Voltage
A9 Auto Select Current
A9 = V
11.5
0.0
13.0
50
V
ID
ID
I
A9 = V Max, V = V Max
5
µA
ID
ID
CC
CC
V
during Read-Only
Note: Erase/Program are inhibited
when V = V
PPL
V
V
+ 2.0
V
PPL
CC
Operations
PP
PPL
V
during Read/Write
PP
V
V
11.4
3.2
12.6
V
V
PPH
Operations
Low V Lock-out Voltage
3.7
LKO
CC
Notes:
1. Caution: The Am28F512A must not be removed from (or inserted into) a socket when V or V is applied. If V ≤ 1.0 volt,
CC
PP
CC
the voltage difference between V and V should not exceed 10.0 volts. Also, the Am28F512A has a V rise time and fall
PP
CC
PP
time specification of 500 ns minimum.
2. I
is tested with OE# = V to simulate open outputs.
IH
CC1
3. Maximum active power usage is the sum of I and I
.
PP
CC
4. Not 100% tested.
22
Am28F512A
25
20
15
10
5
55°C
0°C
25°C
70°C
125°C
0
0
1
2
3
4
5
6
7
8
9
10
11
12
Frequency in MHz
18880B-15
Figure 7. Am28F512A—Average ICC Active vs. Frequency
VCC = 5.5 V, Addressing Pattern = Minmax
Data Pattern = Checkerboard
TEST CONDITIONS
Table 6. Test Specifications
5.0 V
Test Condition
Output Load
-70
All others Unit
2.7 kΩ
1 TTL gate
Device
Under
Test
Output Load Capacitance, C
(including jig capacitance)
L
30
100
pF
C
L
6.2 kΩ
Input Rise and Fall Times
Input Pulse Levels
≤10
0.0–3.0 0.45–2.4
ns
V
Input timing measurement
reference levels
1.5
1.5
0.8, 2.0
0.8, 2.0
V
V
Note: Diodes are IN3064 or equivalent
Output timing measurement
reference levels
18880C-16
Figure 8. Test Setup
23
Am28F512A
SWITCHING TEST WAVEFORMS
3 V
0 V
2.4 V
2.0 V
0.8 V
2.0 V
0.8 V
Test Points
1.5 V
Test Points
1.5 V
0.45 V
Input
Output
Input
Output
AC Testing (all speed options except -70): Inputs are driven
at 2.4 V for a logic “1” and 0.45 V for a logic “0”. Input pulse
rise and fall times are ≤10 ns.
AC Testing for -70 devices: Inputs are driven at 3.0 V for a
logic “1” and 0 V for a logic “0”. Input pulse rise and fall times
are ≤10 ns.
18880C-17
SWITCHING CHARACTERISTICS over operating range unless otherwise specified
AC Characteristics—Read Only Operation
Parameter Symbols
JEDEC Standard
Am28F512A Speed Options
Parameter Description
Read Cycle Time (Note 2)
-70
70
70
70
35
-90
90
90
90
35
-120
120
120
120
50
-150
150
150
150
55
-200
200
200
200
55
Unit
ns
t
t
Min
Max
Max
Max
AVAV
RC
t
t
t
Chip Enable Access Time
Address Access Time
ns
ELQV
AVQV
GLQV
CE
t
ns
ACC
t
t
Output Enable Access Time
ns
OE
Chip Enable to Output in Low Z
(Note 2)
t
t
Min
Max
Min
Max
Min
Min
0
20
0
0
20
0
0
30
0
0
35
0
0
35
0
ns
ns
ns
ns
ns
µs
ELQX
EHQZ
GLQX
GHQZ
LZ
Chip Disable to Output in High Z
(Note 1)
t
t
t
DF
Output Enable to Output in Low Z
(Note 2)
t
OLZ
Output Disable to Output in
High Z (Note 2)
t
t
20
0
20
0
30
0
35
0
35
0
DF
Output Hold from first of Address,
CE#, or OE# Change (Note 2)
t
t
OH
AXQX
V
Setup Time to Valid Read
CC
t
50
50
50
50
50
VCS
(Note 2)
Notes:
1. Guaranteed by design not tested.
2. Not 100% tested.
Am28F512A
24
AC Characteristics—Write/Erase/Program Operations
Parameter Symbols
Am28F512A Speed Options
JEDEC Standard
Parameter Description
Write Cycle Time (Note 4)
-70
70
0
-90
90
0
-120
120
0
-150
150
0
-200
200
0
Unit
ns
t
t
Min
Min
Min
Min
Min
AVAV
WC
t
t
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
ns
AVWL
WLAX
DVWH
WHDX
AS
AH
DS
DH
t
t
45
45
10
45
45
10
50
60
75
ns
t
t
t
50
50
50
ns
t
10
10
10
ns
Output Enable Hold Time
for Embedded Algorithm only
t
Min
Min
Min
10
0
10
0
10
0
10
0
10
0
µs
µs
ns
OEH
t
Read Recovery Time before Write
GHWL
Chip Enable Embedded Algorithm
Setup Time
t
t
20
20
20
20
20
ELWLE
CSE
t
t
Chip Enable Hold Time
Write Pulse Width
Min
Min
Min
0
0
0
0
0
ns
ns
ns
WHEH
WLWH
WHWL
CH
t
t
45
20
45
20
50
20
60
20
60
20
WP
t
t
Write Pulse Width HIGH
WPH
Embedded Programming Operation
(Note 2)
t
t
Min
Typ
Min
14
5
14
5
14
5
14
5
14
5
µs
ms
ns
WHWH3
WHWH4
Embedded Erase Operation (Note 2)
V
Setup Time to Chip Enable LOW
PP
t
100
100
100
100
100
VPEL
(Note 4)
V
Setup Time to Chip Enable LOW
CC
t
Min
50
50
50
50
50
µs
VCS
(Note 4)
t
V
V
V
Rise Time 90% V (Note 4)
PPH
Min
Min
Min
500
500
100
500
500
100
500
500
100
500
500
100
500
500
100
ns
ns
ns
VPPR
PP
PP
CC
t
Fall Time 10% V
(Note 4)
PPL
VPPF
t
< V
to Reset (Note 4)
LKO
LKO
Notes:
1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC
Characteristics for Read Only operations.
2. Embedded Program Operation of 14 µs consists of 10 µs program pulse and 4 ms write recovery before read. This is the
minimum time for one pass through the programming algorithm.
3. Embedded Erase Operation of 5 sec consists of 4 sec array pre-programming time and one sec array erase time. This is a
typical time for one embedded erase operation.
4. Not 100% tested.
25
Am28F512A
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
SWITCHING WAVEFORMS
Device and
Address Selection
Data
Valid
Outputs
Enabled
Power-up, Standby
Standby, Power-down
Addresses Stable
Addresses
t
(t
)
AVAV RC
CE# (E#)
OE# (G#)
t
(t
EHQZ
)
DF
t
t
WHGL
GHQZ
(t
)
DF
WE# (W#)
t
(t
)
GLQV OE
t
(t
)
ELQV CE
t
(t
)
AXQX OH
t
(t
)
GLQX OLZ
t
VCS
t
(t )
ELQX LZ
High Z
High Z
Output Valid
Data (DQ)
t
(t
)
AVQV ACC
5.0 V
V
CC
0 V
18880C-18
Figure 9. AC Waveforms for Read Operations
Am28F512A
26
SWITCHING WAVEFORMS
Embedded
Erase Setup
Embedded
Erase
Data# Polling
Read
Erase
Standby
Addresses
t
RC
t
t
WC
AS
CE#
t
AH
t
GHWL
OE#
WE#
Data
t
t
WHWH3 OR 4
WP
t
WPH
t
DF
t
CSE
t
DH
t
OE
30h
30h
DQ7#
DQ7#
t
VCS
t
DS
t
OH
V
CC
t
CE
V
PP
t
VPEL
18880C-19
Note:
DQ7# is the complement of the data written to the device.
Figure 10. AC Waveforms for Embedded Erase Operation
27
Am28F512A
SWITCHING WAVEFORMS
Embedded
Program
Embedded
Program Setup
Data# Polling
PA
Read
Addresses
PA
t
t
WC
RC
t
AS
CE#
t
AH
t
GHWL
OE#
WE#
Data
t
WHWH3 OR 4
t
WP
t
t
CSE
WPH
t
DF
t
t
DH
OE
D
DQ7# DQ7# DOUT
50h
IN
t
VCS
t
t
OH
DS
V
CC
t
CE
V
PP
t
VPEL
18880C-20
Notes:
1. D is data input to the device.
IN
2. DQ7# is the complement of the data written to the device.
3. D is the data written to the device.
OUT
Figure 11. AC Waveforms for Embedded Programming Operation
Am28F512A
28
AC CHARACTERISTICS—WRITE/ERASE/PROGRAM OPERATIONS
Alternate CE# Controlled Writes
Parameter Symbols
JEDEC Standard
Am28F512A Speed Options
Parameter Description
Write Cycle Time (Note 4)
-70
70
0
-90
90
0
-120
120
0
-150
150
0
-200
200
0
Unit
ns
t
t
Min
Min
Min
Min
Min
AVAV
AVEL
ELAX
DVEH
EHDX
WC
t
t
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
ns
AS
AH
DS
DH
t
t
45
45
10
45
45
10
50
60
75
ns
t
t
50
50
50
ns
t
t
10
10
10
ns
Output Enable Hold Time
for Embedded Algorithm only
t
Min
10
10
10
10
10
µs
OEH
t
Read Recovery Time before Write
WE# Setup Time by CE#
WE# Hold Time
Min
Min
Min
Min
Min
0
0
0
0
0
0
0
0
0
0
ns
ns
ns
ns
ns
GHEL
t
t
WLEL
WS
t
t
0
0
0
0
0
EHWK
WH
t
t
Write Pulse Width
65
20
65
20
70
20
80
20
80
20
ELEH
EHEL
CP
t
t
Write Pulse Width HIGH
CPH
Embedded Programming Operation
(Note 2)
t
t
Min
Typ
Min
14
5
14
5
14
5
14
5
14
5
µs
sec
ns
EHEH3
EHEH4
Embedded Erase Operation (Note 3)
V
Setup Time to Chip Enable LOW
PP
t
100
100
100
100
100
VPEL
(Note 4)
V
Setup Time to Chip Enable LOW
CC
t
Min
50
50
50
50
50
µs
VCS
(Note 4)
t
V
V
V
Rise Time 90% V (Note 4)
PPH
Min
Min
Min
500
500
100
500
500
100
500
500
100
500
500
100
500
500
100
ns
ns
ns
VPPR
PP
PP
CC
t
Fall Time 10% V
(Note 4)
VPPF
PPL
t
< V
to Reset (Note 4)
LKO
LKO
Notes:
1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC
Characteristics for Read Only operations.
2. Embedded Program Operation of 14 µs consists of 10 µs program pulse and 4 ms write recovery before read. This is the
minimum time for one pass through the programming algorithm.
3. Embedded Erase Operation of 5 sec consists of 4 sec array pre-programming time and one sec array erase time. This is a
typical time for one embedded erase operation.
4. Not 100% tested.
29
Am28F512A
SWITCHING WAVEFORMS
Embedded
Program
Embedded
Program Setup
Data# Polling
PA
Addresses
PA
t
WC
t
t
AS
CE#
OE#
AH
t
GHEL
t
CPH
t
EHEH3 OR 4
t
CP
WE#
Data
t
DH
t
WS
D
D
OUT
50h
DQ7# DQ7#
IN
t
DS
V
CC
V
PP
t
VPEL
18880C-21
Notes:
1. D is data input to the device.
IN
2. DQ7# is the complement of the data written to the device.
3. D is the data written to the device.
OUT
Figure 12. AC Waveforms for Embedded Programming Operation Using CE# Controlled Writes
Am28F512A
30
ERASE AND PROGRAMMING PERFORMANCE
Limits
Typ
Max
Parameter
Chip Erase Time
Min
(Note 1) (Note 2)
Unit
sec
Comments
1
1
10
7
Excludes 00h programming prior to erasure
Excludes system-level overhead
Chip Programming Time
Write/Erase Cycles
sec
100,000
Cycles
µs
14
Byte Programming Time
96
(Note 3)
ms
Notes:
1. 25°C, 12 V V
.
PP
2. Maximum time specified is lower than worst case. Worst case is derived from the Embedded Algorithm internal counter which
allows for a maximum 6000 pulses for both program and erase operations. Typical worst case for program and erase is
significantly less than the actual device limit.
3. Typical worst case = 84 µs. DQ5 = “1” only after a byte takes longer than 96 ms to program.
LATCHUP CHARACTERISTICS
Parameter
Input Voltage with respect to V on all pins except I/O pins (Including A9 and V
Min
Max
)
PP
–1.0 V
–1.0 V
–100 mA
13.5 V
SS
Input Voltage with respect to V on all pins I/O pins
V
+ 1.0 V
SS
CC
Current
+100 mA
Includes all pins except V . Test conditions: V = 5.0 V, one pin at a time.
CC
CC
PIN CAPACITANCE
Parameter
Symbol
Parameter Description
Input Capacitance
Output Capacitance
Input Capacitance
Test Conditions
Typ
8
Max
Unit
pF
C
V
V
V
= 0
10
12
12
IN
IN
C
= 0
= 0
8
pF
OUT
OUT
C
V
8
pF
IN2
PP
PP
Note: Sampled, not 100% tested. Test conditions T = 25°C, f = 1.0 MHz.
A
DATA RETENTION
Parameter
Test Conditions
Min
10
Unit
Years
Years
150°C
125°C
Minimum Pattern Data Retention Time
20
31
Am28F512A
PHYSICAL DIMENSIONS
PD032—32-Pin Plastic DIP (measured in inches)
1.640
1.670
.600
.625
17
16
32
.009
.015
.530
.580
Pin 1 I.D.
.630
.700
.045
.065
0°
10°
.005 MIN
.140
.225
16-038-S_AG
PD 032
EC75
SEATING PLANE
.090
.110
.015
.060
.016
.022
5-28-97 lv
.120
.160
PL032—32-Pin Plastic Leaded Chip Carrier (measured in inches)
.485
.495
.447
.453
.009
.015
.042
.056
.125
.140
.585
.595
Pin 1 I.D.
.080
.095
.547
.553
SEATING
PLANE
.400
REF.
.490
.530
.013
.021
.050 REF.
16-038FPO-5
PL 032
DA79
.026
.032
TOP VIEW
SIDE VIEW
6-28-94 ae
Am28F512A
32
PHYSICAL DIMENSIONS
TS032—32-Pin Standard Thin Small Outline Package (measured in millimeters)
0.95
1.05
Pin 1 I.D.
1
7.90
8.10
0.50 BSC
0.05
0.15
18.30
18.50
19.80
20.20
0.08
16-038-TSOP-2
TS 032
DA95
1.20
MAX
0.20
0.10
0.21
3-25-97 lv
0°
5°
0.50
0.70
33
Am28F512A
PHYSICAL DIMENSIONS
TSR032—32-Pin Reversed Thin Small Outline Package (measured in millimeters)
0.95
1.05
Pin 1 I.D.
1
7.90
8.10
0.50 BSC
0.05
0.15
18.30
18.50
19.80
20.20
16-038-TSOP-2
TSR032
DA95
0.08
0.20
1.20
MAX
0.10
0.21
3-25-97 lv
0°
5°
0.50
0.70
DATA SHEET REVISION SUMMARY FOR AM28F512A
Revision C
Revision C+2
Deleted -75, -95, and -250 speed options. Matched for-
matting to other current data sheets.
Product Selector Guide
Corrected maximum access time for -200 to 200 ns.
Revision C+1
Connection Diagrams
Programming In A PROM Programmer
On standard TSOP, corrected pin 9 to VPP and pin 10
to NC. On reverse TSOP, corrected pin 23 to NC and
pin 24 to VPP.
Deleted the paragraph “(Refer to the AUTO SELECT
paragraph in the ERASE, PROGRAM, and READ
MODE section for programming the Flash memory de-
vice in-system).”
Trademarks
Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
Am28F512A
34
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