AM29DL400BB-120ED_技术文档

Am29DL400B

Data Sheet

RETIRED

PRODUCT

This product has been retired and is not recommended for designs. For new and current designs,

S29AL004D supersedes Am29DL400B and is the factory-recommended migration path. Please refer

to the S29AL004D datasheet for specifications and ordering information. Availability of this docu-

ment is retained for reference and historical purposes only.

April 2005

The following document specifies Spansion memory products that are now offered by both Advanced

Micro Devices and Fujitsu. Although the document is marked with the name of the company that

originally developed the specification, these products will be offered to customers of both AMD and

Fujitsu.

Continuity of Specifications

There is no change to this datasheet as a result of offering the device as a Spansion product. Any

changes that have been made are the result of normal datasheet improvement and are noted in the

document revision summary, where supported. Future routine revisions will occur when appro-

priate, and changes will be noted in a revision summary.

For More Information

Please contact your local AMD or Fujitsu sales office for additional information about Spansion

memory solutions.

Publication Number 21606 Revision E Amendment +4 Issue Date June 7, 2005

THIS PAGE LEFT INTENTIONALLY BLANK.

Am29DL400B

4 Megabit (512 K x 8-Bit/256 K x 16-Bit)

CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory

This product has been retired and is not recommended for designs. For new and current designs, S29AL004D supersedes Am29DL400B and is the factory-recommended migration path.

Please refer to the S29AL004D datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only.

DISTINCTIVE CHARACTERISTICS

— Sectors can be locked in-system or via

programming equipment

— Temporary Sector Unprotect feature allows

code changes in previously locked sectors

■ Simultaneous Read/Write operations

— Host system can program or erase in one bank,

then immediately and simultaneously read

from the other bank

— Zero latency between read and write

operations

— Read-while-erase

■ Top or bottom boot block configurations

available

■ Embedded Algorithms

— Read-while-program

— Embedded Erase algorithm automatically

pre-programs and erases sectors or entire chip

■ Single power supply operation

— 2.7 to 3.6 volt read and write operations for

battery-powered applications

— Embedded Program algorithm automatically

programs and verifies data at specified address

■ Manufactured on 0.32 µm process

■ Minimum 1 million program/erase cycles

technology

guaranteed per sector

■ High performance

■ 20-year data retention at 125° C

— Access times as fast as 70 ns

— Reliable operation for the life of the system

■ Low current consumption (typical

■ Package options

values at 5 MHz)

— 7 mA active read current

— 21 mA active read-while-program or read-

while-erase current

— 17 mA active program-while-erase-suspended

current

— 44-pin SO

— 48-pin TSOP

■ Compatible with JEDEC standards

— Pinout and software compatible with

single-power-supply flash standard

— Superior inadvertent write protection

— 200 nA in standby mode

— 200 nA in automatic sleep mode

■ Data# Polling and Toggle Bits

— Standard t chip enable access time applies to

CE

transition from automatic sleep mode to active

mode

— Provides a software method of detecting

program or erase cycle completion

■ Flexible sector architecture

■ Ready/Busy# output (RY/BY#)

— Two 16 Kword, two 8 Kword, four 4 Kword, and

six 32 Kword sectors in word mode

— Two 32 Kbyte, two 16 Kbyte, four 8 Kbyte, and

six 64 Kbyte sectors in byte mode

— Hardware method for detecting program or

erase cycle completion

■ Erase Suspend/Erase Resume

— Any combination of sectors can be erased

— Supports full chip erase

— Suspends or resumes erasing sectors to allow

reading and programming in other sectors

— No need to suspend if sector is in the other

bank

■ Unlock Bypass Program Command

— Reduces overall programming time when

issuing multiple program command sequences

■ Hardware reset pin (RESET#)

— Hardware method of resetting the device to

reading array data

■ Sector protection

— Hardware method of locking a sector to

prevent any program or erase operation within

that sector

This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data Sheet may

be revised by subsequent versions or modifications due to changes in technical specifications.

Publication# 21606

Issue Date: June 7, 2005

Rev: E Amendment/+4

GENERAL DESCRIPTION

The Am29DL400B is an 4 Mbit, 3.0 volt-only flash

memory device, organized as 262,144 words or

524,288 bytes. The device is offered in 44-pin SO

and 48-pin TSOP packages. The word-wide (x16)

data appears on DQ0–DQ15; the byte-wide (x8)

data appears on DQ0–DQ7. This device requires only

by requiring only two write cycles to program data

instead of four.

Device erasure occurs by executing the erase com-

mand sequence. This initiates the Embedded Erase

algorithm—an internal algorithm that automatically

preprograms the array (if it is not already pro-

grammed) before executing the erase operation.

During erase, the device automatically times the

erase pulse widths and verifies proper cell margin.

a single 3.0 volt V

supply to perform read, pro-

CC

gram, and erase operations. A standard EPROM

programmer can also be used to program and erase

the device.

The host system can detect whether a program or

erase operation is complete by observing the RY/BY#

pin, or by reading the DQ7 (Data# Polling) and DQ6

(toggle) status bits. After a program or erase cycle

has been completed, the device automatically re-

turns to reading array data.

The standard device offers access times of 70, 80,

90, and 120 ns, allowing high-speed microprocessors

to operate without wait states. Standard control

pins—chip enable (CE#), write enable (WE#), and

output enable (OE#)—control read and write opera-

tions, and avoid bus contention issues.

The sector erase architecture allows memory sec-

tors to be erased and reprogrammed without

affecting the data contents of other sectors. The de-

vice is fully erased when shipped from the factory.

The device requires only a single 3.0 volt power

supply for both read and write functions. Internally

generated and regulated voltages are provided for

the program and erase operations.

Hardware data protection measures include a low

Simultaneous Read/Write Operations with

Zero Latency

V

detector that automatically inhibits write opera-

CC

tions during power transitions. The hardware

sector protection feature disables both program

and erase operations in any combination of the sec-

tors of memory. This can be achieved in-system or

via programming equipment.

The Simultaneous Read/Write architecture provides

simultaneous operation by dividing the memory

space into two banks. Bank 1 contains boot/parame-

ter sectors, and Bank 2 consists of larger, code

sectors of uniform size. The device can improve

overall system performance by allowing a host sys-

tem to program or erase in one bank, then

immediately and simultaneously read from the other

bank, with zero latency. This releases the system

from waiting for the completion of program or erase

operations.

The Erase Suspend feature enables the user to put

erase on hold for any period of time to read data

from, or program data to, any sector within that

bank that is not selected for erasure. True back-

ground erase can thus be achieved. There is no need

to suspend the erase operation if the read data is in

the other bank.

The hardware RESET# pin terminates any opera-

tion in progress and resets the internal state

machine to reading array data. The RESET# pin may

be tied to the system reset circuitry. A system reset

would thus also reset the device to reading array

data, enabling the system microprocessor to read

the boot-up firmware from the Flash memory.

Am29DL400B Features

The device offers complete compatibility with the

JEDEC single-power-supply Flash command set

standard. Commands are written to the command

register using standard microprocessor write tim-

ings. Register contents serve as input to an internal

state machine that controls the erase and program-

ming circuitry. Write cycles also internally latch

addresses and data needed for the programming and

erase operations. Reading data out of the device is

similar to reading from other Flash or EPROM

devices.

The device offers two power-saving features. When

addresses have been stable for a specified amount of

time, the device enters the automatic sleep mode.

The system can also place the device into the

standby mode. Power consumption is greatly re-

duced in both these modes.

Device programming occurs by executing the pro-

gram command sequence. This initiates the

Embedded Program algorithm—an internal algo-

rithm that automatically times the program pulse

widths and verifies proper cell margin. The Unlock

Bypass mode facilitates faster programming times

AMD’s Flash technology combines years of Flash

memory manufacturing experience to produce the

highest levels of quality, reliability, and cost

effectiveness. The device electrically erases all bits

within a sector simultaneously via Fowler-Nordheim

tunneling. The bytes are programmed one byte or

word at a time using hot electron injection.

2

Am29DL400B

TABLE OF CONTENTS

Product Selector Guide.......................................... 4

Block Diagram......................................................... 4

Connection Diagrams............................................. 5

Connection diagramS............................................. 6

Pin Description........................................................ 7

Logic Symbol .......................................................... 7

Ordering Information.............................................. 8

Device Bus Operations........................................... 9

Table 1. Am29DL400B Device Bus Operations ................................9

Word/Byte Configuration .......................................................... 9

Requirements for Reading Array Data ..................................... 9

Writing Commands/Command Sequences .............................. 9

Simultaneous Read/Write Operations with Zero

Latency ................................................................................... 10

Standby Mode ........................................................................10

Automatic Sleep Mode ........................................................... 10

RESET#: Hardware Reset Pin ...............................................10

Output Disable Mode ..............................................................11

Table 2. Am29DL400BT Top Boot Sector

RY/BY#: Ready/Busy# ............................................................21

DQ6: Toggle Bit I ....................................................................22

DQ2: Toggle Bit II ...................................................................22

Reading Toggle Bits DQ6/DQ2 ...............................................22

Figure 6. Toggle Bit Algorithm........................................................ 23

DQ5: Exceeded Timing Limits ................................................23

DQ3: Sector Erase Timer .......................................................23

Table 6. Write Operation Status ..................................................... 24

Absolute Maximum Ratings................................. 25

Figure 7. Maximum Negative Overshoot Waveform ..................... 25

Figure 8. Maximum Positive Overshoot Waveform....................... 25

Operating Ranges................................................. 26

DC Characteristics................................................ 27

CMOS Compatible ..................................................................27

Figure 9. I Current vs. Time (Showing Active

CC1

and Automatic Sleep Currents)...................................................... 28

Figure 10. Typical I vs. Frequency ........................................... 28

CC1

Test Conditions..................................................... 29

Figure 11. Test Setup.................................................................... 29

Table 7. Test Specifications ........................................................... 29

Key to Switching Waveforms ..................................................29

Figure 12. Input Waveforms and Measurement

Architecture .....................................................................................11

Table 3. Am29DL400BB Bottom Boot Sector

Architecture .....................................................................................12

Autoselect Mode .....................................................................12

Table 4. Am29DL400B Autoselect Codes (High Voltage Method) ..13

Sector Protection/Unprotection ...............................................13

Temporary Sector Unprotect .................................................. 13

Figure 1. Temporary Sector Unprotect Operation........................... 13

Figure 2. In-System Sector Protect/Unprotect

Levels............................................................................................. 29

AC Characteristics................................................ 30

Read-Only Operations ...........................................................30

Figure 13. Read Operation Timings............................................... 30

Figure 14. Reset Timings............................................................... 31

Figure 15. BYTE# Timings for Read Operations............................ 32

Figure 16. BYTE# Timings for Write Operations............................ 32

Figure 17. Program Operation Timings.......................................... 34

Figure 18. Chip/Sector Erase Operation Timings .......................... 34

Figure 19. Back-to-Back Read/Write Cycle Timings...................... 35

Figure 20. Data# Polling Timings (During Embedded Algorithms). 35

Figure 21. Toggle Bit Timings (During Embedded Algorithms)...... 36

Figure 22. DQ2 vs. DQ6................................................................. 36

Figure 23. Temporary Sector Unprotect Timing

Diagram.......................................................................................... 37

Figure 24. Sector Protect/Unprotect Timing

Diagram.......................................................................................... 38

Alternate CE# Controlled Erase/Program

Operations ..............................................................................39

Figure 25. Alternate CE# Controlled Erase/Program

Operation Timings.......................................................................... 40

Erase and Programming Performance ............... 41

Latchup Characteristics....................................... 42

TSOP and SO Pin Capacitance............................ 42

Data Retention....................................................... 42

Physical Dimensions*........................................... 43

TS 048—48-Pin Standard TSOP ............................................43

TSR048—48-Pin Reverse TSOP ...........................................44

SO 044—44-Pin Small Outline ...............................................45

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 46

Algorithms ....................................................................................... 14

Hardware Data Protection ...................................................... 15

Low VCC Write Inhibit ............................................................15

Write Pulse “Glitch” Protection ...............................................15

Logical Inhibit .......................................................................... 15

Power-Up Write Inhibit ............................................................15

Command Definitions ........................................... 15

Reading Array Data ................................................................15

Reset Command .....................................................................15

Autoselect Command Sequence ............................................15

Byte/Word Program Command Sequence ............................. 16

Unlock Bypass Command Sequence .....................................16

Figure 3. Program Operation .......................................................... 17

Chip Erase Command Sequence ...........................................17

Sector Erase Command Sequence ........................................17

Erase Suspend/Erase Resume Commands ........................... 18

Figure 4. Erase Operation............................................................... 19

Command Definitions........................................... 20

Table 5. Am29DL400B Command Definitions ................................20

Write Operation Status......................................... 21

DQ7: Data# Polling .................................................................21

Figure 5. Data# Polling Algorithm ................................................... 21

Am29DL400B

3

PRODUCT SELECTOR GUIDE

Family Part Number

Am29DL400B

-80 -90

80 90

Speed Options (Full Voltage Range: V

Max Access Time (ns)

CE# Access (ns)

= 2.7 – 3.6 V)

-70

70

-120

120

50

CC

70

80

30

90

35

OE# Access (ns)

30

Note: See “AC Characteristics” for full specifications.

BLOCK DIAGRAM

OE# BYTE#

V

CC

SS

Upper Bank Address

A0–A17

Upper Bank

X-Decoder

RY/BY#

A0–A17

RESET#

STATE

CONTROL

&

COMMAND

REGISTER

Status

WE#

CE#

DQ0–DQ15

Control

BYTE#

DQ0–DQ15

X-Decoder

Lower Bank

A0–A17

Lower Bank Address

OE# BYTE#

4

Am29DL400B

CONNECTION DIAGRAMS

A15

A14

A13

A12

A11

A10

A9

A8

NC

1

2

3

4

5

6

7

8

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A16

BYTE#

V_SS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

DQ12

DQ4

V_CC

WE#

RESET#

NC

RY/BY#

NC

Standard TSOP

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

V_SS

CE#

A0

A17

A7

A6

A5

A4

A3

A2

A1

A16

BYTE#

V_SS

1

2

3

4

5

6

7

8

9

48

A15

A14

A13

A12

A11

A10

A9

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

V_CC

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

V_SS

A8

NC

WE#

RESET#

NC

RY/BY#

NC

A17

A7

A6

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

Reverse TSOP

A5

A4

A3

A2

CE#

A0

A1

Am29DL400B

5

CONNECTION DIAGRAMSPIN DESCRIPTION

RY/BY#

NC

A17

A7

1

2

3

4

5

6

7

8

9

44 RESET#

43 WE#

42 A8

41 A9

A6

40 A10

A5

39 A11

A4

38 A12

A3

37 A13

A2

36 A14

A1 10

A0 11

35 A15

34 A16

SO

CE# 12

V_SS13

33 BYTE#

32 V_SS

OE# 14

DQ0 15

DQ8 16

DQ1 17

DQ9 18

DQ2 19

DQ10 20

DQ3 21

DQ11 22

31 DQ15/A-1

30 DQ7

29 DQ14

28 DQ6

27 DQ13

26 DQ5

25 DQ12

24 DQ4

23 V_CC

PIN DESCRIPTION

A0-A17

= 18 Addresses

LOGIC SYMBOL

DQ0-DQ14= 15 Data Inputs/Outputs

18

DQ15/A-1 = DQ15 (Data Input/Output, word mode),

A-1 (LSB Address Input, byte mode)

A0–A17

16 or 8

CE#

OE#

= Chip Enable

= Output Enable

DQ0–DQ15

(A-1)

WE#

= Write Enable

BYTE#

RESET#

RY/BY#

= Selects 8-bit or 16-bit mode

= Hardware Reset Pin, Active Low

= Ready/Busy Output

= 3.0 volt-only single power supply

(see Product Selector Guide for speed

options and voltage supply tolerances)

CE#

OE#

WE#

V

CC

RESET#

BYTE#

RY/BY#

V

= Device Ground

SS

NC

= Pin Not Connected Internally

6

Am29DL400B

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Com-

bination) is formed by a combination of the following:

Am29DL400B

T

70

E

I

TEMPERATURE RANGE

C

I

E

D

F

K

=

Commercial (0°C to +70°C)

^{Industrial (–40}°C to +85°C)

Extended (–55°C to +125°C)

Commercial (0°C to +70°C) for Pb-free Package

Industrial (-40°C to +85°C) for Pb-free Package

Extended (-55°C to +125°C) for Pb-free Package

PACKAGE TYPE

E

F

S

=

48-Pin Thin Small Outline Package

(TSOP) Standard Pinout (TS 048)

48-Pin Thin Small Outline Package (TSOP)

Reverse Pinout (TSR048)

44-Pin Small Outline Package (SO 044)

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T

B

=

Top sector

Bottom sector

DEVICE NUMBER/DESCRIPTION

Am29DL400B

4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS Flash Memory

3.0 Volt-only Read, Program, and Erase

Valid Combinations

Valid Combinations list configurations planned to be

supported in volume for this device. Consult the local

AMD sales office to confirm availability of specific

valid combinations to check on newly released com-

binations.

Valid Combinations

AM29DL400BT-70

AM29DL400BB-70

EC, EI, FC, FI, ED, EF

SC, SI, SD, SF

AM29DL400BT-80

AM29DL400BB-80

EC, EI, EE, ED, EF, EK

FC, FI, FE,

SC, SI, SE, SD, SF, SK

AM29DL400BT-90

AM29DL400BB-90

AM29DL400BT-120

AM29DL400BB-120

Am29DL400B

7

DEVICE BUS OPERATIONS

This section describes the requirements and use of

the device bus operations, which are initiated

through the internal command register. The com-

mand register itself does not occupy any addressable

memory location. The register is a latch used to

store the commands, along with the address and

data information needed to execute the command.

The contents of the register serve as inputs to the in-

ternal state machine. The state machine outputs

dictate the function of the device. Table 1 lists the

device bus operations, the inputs and control levels

they require, and the resulting output. The following

subsections describe each of these operations in fur-

ther detail.

Table 1. Am29DL400B Device Bus Operations

DQ8–DQ15

DQ0– BYTE# BYTE#

WE

Addresses

(Note 1)

Operation

CE# OE#

#

H

L

RESET#

DQ7

D_OUT

D_IN

= V_IH

D_OUT

D_IN

= V_IL

Read

Write

L

H

A_IN

DQ8–DQ14 = High-Z,

DQ15 = A-1

H

V_CC

0.3 V

±

V_CC±

0.3 V

Standby

X

High-Z High-Z

High-Z

Output Disable

Reset

L

H

X

H

X

H

L

X

High-Z High-Z

High-Z

X

Sector Address,

A6 = L, A1 = H,

A0 = L

Sector Protect (Note 2)

L

H

L

V_ID

D_IN

X

Sector Address,

A6 = H, A1 = H,

A0 = L

Sector Unprotect (Note 2)

L

H

X

L

V_ID

D_IN

X

Temporary Sector Unprotect

X

A_IN

D_IN

High-Z

Legend:

L = Logic Low = V_IL, H = Logic High = V_IH, V_ID= 12.0 ± ±0.5 V, X = Don’t Care, A_IN= Address In, D_IN= Data In, D_OUT= Data Out

Notes:

1. Addresses are A17:A0 in word mode (BYTE# = V_IH), A17:A-1 in byte mode (BYTE# = V_IL).

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Pro-

tection/Unprotection” section.

memory content occurs during the power transition.

Word/Byte Configuration

No command is necessary in this mode to obtain

The BYTE# pin controls whether the device data I/O

array data. Standard microprocessor read cycles that

pins operate in the byte or word configuration. If the

assert valid addresses on the device address inputs

BYTE# pin is set at logic ‘1’, the device is in word

produce valid data on the device data outputs. Each

configuration, DQ0-15 are active and controlled by

bank remains enabled for read access until the com-

CE# and OE# .

mand register contents are altered.

If the BYTE# pin is set at logic ‘0’, the device is in

See “Reading Array Data” for more information.

byte configuration, and only data I/O pins DQ0–DQ7

Refer to the AC Read-Only Operations table for tim-

are active and controlled by CE# and OE#. The data

ing specifications and to Figure 13 for the timing

I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin

diagram. I

in the DC Characteristics table repre-

CC1

is used as an input for the LSB (A-1) address

function.

sents the active current specification for reading

array data.

Requirements for Reading Array Data

To read array data from the outputs, the system

Writing Commands/Command Sequences

To write a command or command sequence (which

includes programming data to the device and erasing

sectors of memory), the system must drive WE# and

must drive the CE# and OE# pins to V . CE# is the

IL

power control and selects the device. OE# is the out-

put control and gates array data to the output pins.

CE# to V , and OE# to V .

IL

IH

WE# should remain at V . The BYTE# pin deter-

IH

mines whether the device outputs array data in

words or bytes.

For program operations, the BYTE# pin determines

whether the device accepts program data in bytes or

words. Refer to “Word/Byte Configuration” for more

information.

The internal state machine is set for reading array

data upon device power-up, or after a hardware re-

set. This ensures that no spurious alteration of the

8

Am29DL400B

The device features an Unlock Bypass mode to fa-

cilitate faster programming. Once a bank enters the

Unlock Bypass mode, only two write cycles are re-

quired to program a word or byte, instead of four.

The “Byte/Word Program Command Sequence” sec-

tion has details on programming data to the device

using both standard and Unlock Bypass command

sequences.

The device also enters the standby mode when the

RESET# pin is driven low. Refer to the next section,

“RESET#: Hardware Reset Pin”.

If the device is deselected during erasure or pro-

gramming, the device draws active current until the

operation is completed.

I

in the DC Characteristics table represents the

CC3

standby current specification.

An erase operation can erase one sector, multiple

sectors, or the entire device. Tables 2 and 3 indicate

the address space that each sector occupies. The de-

vice address space is divided into two banks: Bank 1

contains the boot/parameter sectors, and Bank 2

contains the larger, code sectors of uniform size. A

“bank address” is the address bits required to

uniquely select a bank. Similarly, a “sector address”

is the address bits required to uniquely select a

sector.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device

energy consumption. The device automatically en-

ables this mode when addresses remain stable for

t

+ 30 ns. The automatic sleep mode is indepen-

ACC

dent of the CE#, WE#, and OE# control signals.

Standard address access timings provide new data

when addresses are changed. While in sleep mode,

output data is latched and always available to the

If the system writes the autoselect command se-

quence, the device enters the autoselect mode. The

system can then read autoselect codes from the in-

ternal register (which is separate from the memory

array) on DQ7–DQ0. Standard read cycle timings

apply in this mode. Refer to the Autoselect Mode and

Autoselect Command Sequence sections for more

information.

system. I

in the DC Characteristics table repre-

CC4

sents the automatic sleep mode current

specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of re-

setting the device to reading array data. When the

RESET# pin is driven low for at least a period of t ,

RP

the device immediately terminates any operation

in progress, tristates all output pins, and ignores all

read/write commands for the duration of the RE-

SET# pulse. The device also resets the internal state

machine to reading array data. The operation that

was interrupted should be reinitiated once the device

is ready to accept another command sequence, to

ensure data integrity.

I

in the DC Characteristics table represents the

CC2

active current specification for the write mode. The

AC Characteristics section contains timing specifica-

tion tables and timing diagrams for write operations.

Simultaneous Read/Write Operations with

Zero Latency

This device is capable of reading data from one bank

of memory while programming or erasing in the

other bank of memory. An erase operation may also

be suspended to read from or program to another lo-

cation within the same bank (except the sector being

erased). Figure 19 shows how read and write cycles

may be initiated for simultaneous operation with

zero latency. I

table represent the current specifications for read-

while-program and read-while-erase, respectively.

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at V ±0.3 V, the device

SS

draws CMOS standby current (I

). If RESET# is

CC4

held at V but not within V ±0.3 V, the standby

IL

SS

current will be greater.

The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the

Flash memory, enabling the system to read the

boot-up firmware from the Flash memory.

and I

in the DC Characteristics

CC6

CC7

If RESET# is asserted during a program or erase op-

eration, the RY/BY# pin remains a “0” (busy) until

the internal reset operation is complete, which re-

Standby Mode

When the system is not reading or writing to the de-

vice, it can place the device in the standby mode. In

this mode, current consumption is greatly reduced,

and the outputs are placed in the high impedance

state, independent of the OE# input.

quires a time of t

(during Embedded

READY

Algorithms). The system can thus monitor RY/BY# to

determine whether the reset operation is complete.

If RESET# is asserted when a program or erase op-

eration is not executing (RY/BY# pin is “1”), the

The device enters the CMOS standby mode when the

CE# and RESET# pins are both held at V ± 0.3 V.

(Note that this is a more restricted voltage range

reset operation is completed within a time of t

CC

READY

(not during Embedded Algorithms). The system can

than V .) If CE# and RESET# are held at V , but

read data t

after the RESET# pin returns to V .

IH

RH

IH

not within V

standby mode, but the standby current will be

± 0.3 V, the device will be in the

CC

Refer to the AC Characteristics tables for RESET#

parameters and to Figure 14 for the timing diagram.

greater. The device requires standard access time

(t ) for read access when the device is in either of

CE

these standby modes, before it is ready to read data.

Am29DL400B

9

Output Disable Mode

When the OE# input is at V , output from the de-

IH

vice is disabled. The output pins are placed in the

high impedance state.

Table 2. Am29DL400BT Top Boot Sector Architecture

Sector Address

Bank

Address

Sector Size

(Kbytes/

Kwords)

(x8)

(x16)

Bank

Sector A17 A16 A15 A14 A13 A12

Address Range

SA0

SA1

SA2

SA3

SA4

SA5

SA6

0

1

0

1

0

1

0

1

0

1

0

1

0

X

0

1

0

1

X

0

1

0

1

0

1

0

1

X

0

1

0

1

X

64/32

16/8

00000h–0FFFFh

10000h–1FFFFh

20000h–2FFFFh

30000h–3FFFFh

40000h–4FFFFh

50000h–5FFFFh

60000h–63FFFh

00000h–07FFFh

08000h–0FFFFh

10000h–17FFFh

18000h–1FFFFh

20000h–27FFFh

28000h–2FFFFh

30000h–31FFFh

Bank 2

SA7

1

0

32/16

64000h–6BFFFh

32000h–35FFFh

SA8

SA9

1

0

1

8/4

6C000h–6DFFFh

6E000h–6FFFFh

70000h–71FFFh

72000h–73FFFh

36000h–36FFFh

37000h–37FFFh

38000h–38FFFh

39000h–39FFFh

Bank 1

SA10

SA11

SA12

SA13

1

32/16

16/8

74000h–7BFFFh

7C000h–7FFFFh

3A000h–3DFFFh

3E000h–3FFFFh

Note: The address range is A17:A-1 if in byte mode (BYTE# = V_IL). The address range is A17:A0 if in word mode (BYTE# =

V_IH).

10

Am29DL400B

Table 3. Am29DL400BB Bottom Boot Sector Architecture

Sector Address

Bank

Address

Sector Size

Sector A17 A16 A15 A14 A13 A12 (Kbytes/Kwords)

(x8)

Address Range

(x16)

Address Range

Bank

SA13

SA12

SA11

SA10

SA9

1

0

1

0

1

0

1

0

1

0

1

0

1

X

1

0

1

0

X

1

0

1

0

1

0

1

0

X

1

0

1

0

X

64/32

16/8

70000h–7FFFFh

60000h–6FFFFh

50000h–5FFFFh

40000h–4FFFFh

30000h–3FFFFh

20000h–2FFFFh

1C000h–1FFFFh

38000h–3FFFFh

30000h–37FFFh

28000h–2FFFFh

20000h–27FFFh

18000h–1FFFFh

10000h–17FFFh

0E000h–0FFFFh

Bank 2

SA8

SA7

SA6

0

1

32/16

14000h–1BFFFh

0A000h–0DFFFh

SA5

SA4

SA3

SA2

0

1

0

8/4

12000h–13FFFh

10000h–11FFFh

0E000h–0FFFFh

0C000h–0DFFFh

09000h–09FFFh

08000h–08FFFh

07000h–07FFFh

06000h–06FFFh

Bank 1

SA1

SA0

0

32/16

16/8

04000h–0BFFFh

00000h–03FFFh

02000h–05FFFh

00000h–01FFFh

Note: The address range is A17:A-1 if in byte mode (BYTE# = V_IL). The address range is A17:A0 if in word mode (BYTE# =

V_IH).

tion, the sector address must appear on the

Autoselect Mode

appropriate highest order address bits (see Tables 2

The autoselect mode provides manufacturer and de-

and 3). Table 4 shows the remaining address bits

vice identification, and sector protection verification,

that are don’t care. When all necessary bits have

through identifier codes output on DQ7–DQ0. This

been set as required, the programming equipment

mode is primarily intended for programming equip-

may then read the corresponding identifier code on

ment to automatically match a device to be

DQ7-DQ0.

programmed with its corresponding programming al-

gorithm. However, the autoselect codes can also be

accessed in-system through the command register.

To access the autoselect codes in-system, the host

system can issue the autoselect command via the

command register, as shown in Table 5. This method

When using programming equipment, the autoselect

does not require V . Refer to the Autoselect Com-

ID

mode requires V (11.5 V to 12.5 V) on address pin

ID

mand Sequence section for more information.

A9. Address pins A6, A1, and A0 must be as shown

in Table 4. In addition, when verifying sector protec-

Am29DL400B

11

Table 4. Am29DL400B Autoselect Codes (High Voltage Method)

A17 A11

to to

Mode CE# OE# WE# A12 A10 A9

A8

to

A7

A5

to

A2

DQ8

to

DQ15

DQ7

to

DQ0

Description

A6

A1

A0

Manufacturer ID: AMD

L

H

BA

X

V_ID

X

L

X

L

X

01h

0C

Device ID:

Am29DL400B

(Top Boot Block)

Word

Byte

Word

Byte

22h

BA

X

V_ID

L

H

L

H

X

22h

X

0C

0F

Device ID:

Am29DL400B

(Bottom Boot Block)

BA

SA

X

V_ID

X

01h

(protected)

X

Sector Protection Verification

L

H

V_ID

L

H

L

00h

(unprotected

)

Note: L = Logic Low = V_IL, H = Logic High = V_IH, BA = Bank

Address, SA = Sector Address, X = Don’t care.

mode, formerly protected sectors can be pro-

grammed or erased by selecting the sector

Sector Protection/Unprotection

The hardware sector protection feature disables both

program and erase operations in any sector. The

hardware sector unprotection feature re-enables

both program and erase operations in previously

protected sectors. Sector protection/unprotection

can be implemented via two methods.

addresses. Once V is removed from the RESET#

ID

pin, all the previously protected sectors are

protected again. Figure 1 shows the algorithm, and

Figure 23 shows the timing diagrams, for this

feature.

The primary method requires V on the RESET# pin

ID

only, and can be implemented either in-system or via

programming equipment. Figure 2 shows the algo-

rithms and Figure 24 shows the timing diagram. This

method uses standard microprocessor bus cycle tim-

ing. For sector unprotect, all unprotected sectors

must first be protected prior to the first sector un-

protect write cycle.

START

RESET# = V_ID

(Note 1)

The alternate method intended only for program-

Perform Erase or

Program Operations

ming equipment requires V on address pin A9 and

ID

OE#. This method is compatible with programmer

routines written for earlier 3.0 volt-only AMD flash

devices. Publication number 22145 contains further

details; contact an AMD representative to request a

copy.

RESET# = V_IH

The device is shipped with all sectors unprotected.

AMD offers the option of programming and protect-

ing sectors at its factory prior to shipping the device

through AMD’s ExpressFlash™ Service. Contact an

AMD representative for details.

Temporary Sector

Unprotect Completed

(Note 2)

It is possible to determine whether a sector is pro-

tected or unprotected. See the Autoselect Mode

section for details.

Notes:

1. All protected sectors unprotected.

2. All previously protected sectors are protected once again.

Temporary Sector Unprotect

This feature allows temporary unprotection of previ-

ously protected sectors to change data in-system.

The Sector Unprotect mode is activated by setting

Figure 1. Temporary Sector Unprotect

Operation

the RESET# pin to V (11.5 V – 12.5 V). During this

ID

12

Am29DL400B

START

Protect all sectors:

The indicated portion

of the sector protect

algorithm must be

performed for all

PLSCNT = 1

RESET# = V_ID

unprotected sectors

prior to issuing the

first sector

Wait 1 μs

unprotect address

No

First Write

Cycle = 60h?

Temporary Sector

Unprotect Mode

Temporary Sector

Unprotect Mode

Cycle = 60h?

Yes

Set up sector

address

No

All sectors

protected?

Sector Protect:

Write 60h to sector

address with

A6 = 0, A1 = 1,

A0 = 0

Yes

Set up first sector

address

Sector Unprotect:

Wait 150 µs

Write 60h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Verify Sector

Protect: Write 40h

to sector address

with A6 = 0,

Reset

PLSCNT = 1

Increment

PLSCNT

Wait 15 ms

A1 = 1, A0 = 0

Verify Sector

Unprotect: Write

40h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector address

with A6 = 0,

A1 = 1, A0 = 0

Increment

PLSCNT

No

PLSCNT

= 25?

Read from

sector address

with A6 = 1,

Data = 01h?

Yes

A1 = 1, A0 = 0

No

Yes

Set up

next sector

address

Yes

No

PLSCNT

= 1000?

Protect another

sector?

Data = 00h?

Yes

Device failed

No

Yes

Remove V_ID

from RESET#

No

Last sector

verified?

Device failed

Write reset

command

Yes

Remove V_ID

Sector Unprotect

Algorithm

from RESET#

Sector Protect

Algorithm

Sector Protect

complete

Write reset

command

Sector Unprotect

complete

Figure 2. In-System Sector Protect/Unprotect Algorithms

Am29DL400B

13

the control pins to prevent unintentional writes when

is greater than V

Hardware Data Protection

V

.

LKO

CC

The command sequence requirement of unlock cy-

cles for programming or erasing provides data

protection against inadvertent writes (refer to Table

5 for command definitions). In addition, the follow-

ing hardware data protection measures prevent

accidental erasure or programming, which might

otherwise be caused by spurious system level signals

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE#

or WE# do not initiate a write cycle.

Logical Inhibit

during V power-up and power-down transitions, or

from system noise.

CC

Write cycles are inhibited by holding any one of OE#

= V , CE# = V or WE# = V . To initiate a write

IL

IH

cycle, CE# and WE# must be a logical zero while

OE# is a logical one.

Low V

Write Inhibit

CC

When V is less than V

, the device does not ac-

LKO

CC

Power-Up Write Inhibit

cept any write cycles. This protects data during V

CC

power-up and power-down. The command register

and all internal program/erase circuits are disabled,

and the device resets to reading array data. Subse-

If WE# = CE# = V and OE# = V during power

IL

IH

up, the device does not accept commands on the ris-

ing edge of WE#. The internal state machine is

automatically reset to reading array data on

power-up.

quent writes are ignored until V

is greater than

CC

V

. The system must provide the proper signals to

LKO

COMMAND DEFINITIONS

Writing specific address and data commands or se-

quences into the command register initiates device

operations. Table 5 defines the valid register com-

mand sequences. Writing incorrect address and

data values or writing them in the improper se-

quence resets the device to reading array data.

Reset Command

Writing the reset command resets the banks to the

read or erase-suspend-read mode. Address bits are

don’t cares for this command.

The reset command may be written between the se-

quence cycles in an erase command sequence before

erasing begins. This resets the bank to which the

system was writing to reading array data. Once era-

sure begins, however, the device ignores reset

commands until the operation is complete.

All addresses are latched on the falling edge of WE#

or CE#, whichever happens later. All data is latched

on the rising edge of WE# or CE#, whichever hap-

pens first. Refer to the appropriate timing diagrams

in the AC Characteristics section.

The reset command may be written between the se-

quence cycles in a program command sequence

before programming begins. This resets the bank to

which the system was writing to the reading array

data. If the program command sequence is written

to a bank that is in the Erase Suspend mode, writing

the reset command returns that bank to the erase-

suspend-read mode. Once programming begins,

however, the device ignores reset commands until

the operation is complete.

Reading Array Data

The device is automatically set to reading array data

after device power-up. No commands are required to

retrieve data. Each bank is ready to read array data

after completing an Embedded Program or Embed-

ded Erase algorithm.

After the device accepts an Erase Suspend com-

mand, the corresponding bank enters the erase-

suspend-read mode, after which the system can

read data from any non-erase-suspended sector

within the same bank. After completing a program-

ming operation in the Erase Suspend mode, the

system may once again read array data with the

same exception. See the Erase Suspend/Erase Re-

sume Commands section for more information.

The reset command may be written between the se-

quence cycles in an autoselect command sequence.

Once in the autoselect mode, the reset command

must be written to return to reading array data. If a

bank entered the autoselect mode while in the Erase

Suspend mode, writing the reset command returns

that bank to the erase-suspend-read mode.

The system must issue the reset command to return

a bank to the read (or erase-suspend-read) mode if

DQ5 goes high during an active program or erase op-

eration, or if the bank is in the autoselect mode. See

the next section, Reset Command, for more

information.

If DQ5 goes high during a program or erase opera-

tion, writing the reset command returns the banks to

reading array data (or erase-suspend-read mode if

that bank was in Erase Suspend).

Autoselect Command Sequence

See also Requirements for Reading Array Data in the

Device Bus Operations section for more information.

The “Read-Only Operations” table provides the read

parameters, and Figure 13 shows the timing

diagram.

The autoselect command sequence allows the host

system to access the manufacturer and devices

codes, and determine whether or not a sector is pro-

tected. Table 5 shows the address and data

14

Am29DL400B

requirements. This method is an alternative to that

shown in Table 4, which is intended for PROM pro-

dresses are no longer latched. The system can

determine the status of the program operation by

using DQ7, DQ6, or RY/BY#. Note that while the Em-

bedded Program operation is in progress, the system

can read data from the non-programming bank.

Refer to the Write Operation Status section for infor-

mation on these status bits.

grammers and requires V on address pin A9. The

ID

autoselect command sequence may be written to an

address within a bank that is either in the read or

erase-suspend-read mode. The autoselect com-

mand may not be written while the device is actively

programming or erasing in the other bank.

Any commands written to the device during the Em-

bedded Program Algorithm are ignored. Note that a

hardware reset immediately terminates the pro-

gram operation. The program command sequence

should be reinitiated once that bank has returned to

reading array data, to ensure data integrity.

The autoselect command sequence is initiated by

first writing two unlock cycles. This is followed by a

third write cycle that contains the bank address and

the autoselect command. The addressed bank then

enters the autoselect mode. The system may read at

any address within the same bank any number of

times without initiating another autoselect command

sequence:

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed

from “0” back to a “1.” Attempting to do so may

cause that bank to set DQ5 = 1, or cause the DQ7

and DQ6 status bits to indicate the operation was

successful. However, a succeeding read will show

that the data is still “0.” Only erase operations can

convert a “0” to a “1.”

■ A read cycle at address (BA)XX00h (where BA is

the bank address) returns the manufacturer code.

■ A read cycle at address (BA)XX01h in word mode

(or (BA)XX02h in byte mode) returns the device

code.

■ A read cycle to an address containing a sector ad-

dress (SA) within the same bank, and the address

02h on A7–A0 in word mode (or the address 04h

on A6–A-1 in byte mode) returns 01h if the sector

is protected, or 00h if it is unprotected. Refer to

Tables 2 and 3 for valid sector addresses.

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to pro-

gram bytes or words to a bank faster than using the

standard program command sequence. The unlock

bypass command sequence is initiated by first writ-

ing two unlock cycles. This is followed by a third

write cycle containing the unlock bypass command,

20h. That bank then enters the unlock bypass mode.

A two-cycle unlock bypass program command se-

quence is all that is required to program in this

mode. The first cycle in this sequence contains the

unlock bypass program command, A0h; the second

cycle contains the program address and data. Addi-

tional data is programmed in the same manner. This

mode dispenses with the initial two unlock cycles re-

quired in the standard program command sequence,

resulting in faster total programming time. Table 5

shows the requirements for the command sequence.

The system may continue to read array data from

the other bank while a bank is in the autoselect

mode. To exit the autoselect mode, the system must

write the reset command to return both banks to

reading array data. If a bank enters the autoselect

mode while erase suspended, a reset command re-

turns that bank to the erase-suspend-read mode. A

subsequent Erase Resume command returns the

bank to the erase operation.

Byte/Word Program Command Sequence

The system may program the device by word or

byte, depending on the state of the BYTE# pin. Pro-

gramming is a four-bus-cycle operation. The

program command sequence is initiated by writing

two unlock write cycles, followed by the program

set-up command. The program address and data are

written next, which in turn initiate the Embedded

Program algorithm. The system is not required to

provide further controls or timings. The device auto-

matically generates the program pulses and verifies

the programmed cell margin. Table 5 shows the ad-

dress and data requirements for the byte program

command sequence.

During the unlock bypass mode, only the Unlock By-

pass Program and Unlock Bypass Reset commands

are valid. To exit the unlock bypass mode, the sys-

tem must issue the two-cycle unlock bypass reset

command sequence. The first cycle must contain the

bank address and the data 90h. The second cycle

need only contain the data 00h. The bank then re-

turns to reading array data.

Figure 3 illustrates the algorithm for the program op-

eration. Refer to the Erase and Program Operations

table in the AC Characteristics section for parame-

ters, and Figure 17 for timing diagrams.

When the Embedded Program algorithm is complete,

that bank then returns to reading array data and ad-

Am29DL400B

15

should be reinitiated once that bank has returned to

reading array data, to ensure data integrity.

Figure 4 illustrates the algorithm for the erase opera-

tion. Refer to the Erase and Program Operations

tables in the AC Characteristics section for parame-

ters, and Figure 18 section for timing diagrams.

START

Write Program

Command Sequence

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector

erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two

additional unlock cycles are written, and are then fol-

lowed by the address of the sector to be erased, and

the sector erase command. Table 5 shows the ad-

dress and data requirements for the sector erase

command sequence.

Data Poll

from System

Embedded

Program

algorithm

in progress

Verify Data?

Yes

The device does not require the system to prepro-

gram prior to erase. The Embedded Erase algorithm

automatically programs and verifies the entire mem-

ory for an all zero data pattern prior to electrical

erase. The system is not required to provide any

controls or timings during these operations.

No

Increment Address

Last Address?

Yes

After the command sequence is written, a sector

erase time-out of 50 µs occurs. During the time-out

period, additional sector addresses and sector erase

commands may be written. Loading the sector erase

buffer may be done in any sequence, and the num-

ber of sectors may be from one sector to all sectors.

The time between these additional cycles must be

less than 50 µs, otherwise the last address and com-

mand may not be accepted, and erasure may begin.

It is recommended that processor interrupts be dis-

abled during this time to ensure all commands are

accepted. The interrupts can be re-enabled after the

last Sector Erase command is written. Any com-

mand other than Sector Erase or Erase Suspend

during the time-out period resets that bank to

reading array data. The system must rewrite the

command sequence and any additional addresses

and commands.

Programming

Completed

3. Note: See Table 5 for program command sequence.

Figure 3. Program Operation

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip

erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two

additional unlock write cycles are then followed by

the chip erase command, which in turn invokes the

Embedded Erase algorithm. The device does not re-

quire the system to preprogram prior to erase. The

Embedded Erase algorithm automatically prepro-

grams and verifies the entire memory for an all zero

data pattern prior to electrical erase. The system is

not required to provide any controls or timings dur-

ing these operations. Table 5 shows the address and

data requirements for the chip erase command

sequence.

The system can monitor DQ3 (in the erasing bank)

to determine if the sector erase timer has timed out

(See the section on DQ3: Sector Erase Timer.). The

time-out begins from the rising edge of the final

WE# pulse in the command sequence.

When the Embedded Erase algorithm is complete,

the bank returns to reading array data and ad-

dresses are no longer latched. Note that while the

Embedded Erase operation is in progress, the system

can read data from the non-erasing bank. The sys-

tem can determine the status of the erase operation

by reading DQ7, DQ6, DQ2, or RY/BY# in the erasing

bank. Refer to the Write Operation Status section for

information on these status bits.

When the Embedded Erase algorithm is complete,

that bank returns to reading array data and ad-

dresses are no longer latched. The system can

determine the status of the erase operation by using

DQ7, DQ6, DQ2, or RY/BY#. Refer to the Write Oper-

ation Status section for information on these status

bits.

Once the sector erase operation has begun, only the

Erase Suspend command is valid. All other com-

mands are ignored. However, note that a hardware

reset immediately terminates the erase operation. If

that occurs, the sector erase command sequence

Any commands written during the chip erase opera-

tion are ignored. However, note that a hardware

reset immediately terminates the erase operation. If

that occurs, the chip erase command sequence

should be reinitiated once that bank has returned to

reading array data, to ensure data integrity.

16

Am29DL400B

Figure 4 illustrates the algorithm for the erase opera-

tion. Refer to the Erase and Program Operations

tables in the AC Characteristics section for parame-

ters, and Figure 18 section for timing diagrams.

In the erase-suspend-read mode, the system can

also issue the autoselect command sequence. Refer

to the Autoselect Mode and Autoselect Command Se-

quence sections for details.

To resume the sector erase operation, the system

must write the Erase Resume command. The bank

address of the erase-suspended bank is required

when writing this command. Further writes of the

Resume command are ignored. Another Erase Sus-

pend command can be written after the chip has

resumed erasing.

Erase Suspend/Erase Resume Commands

The Erase Suspend command, B0h, allows the sys-

tem to interrupt a sector erase operation and then

read data from, or program data to, any sector not

selected for erasure. The bank address is required

when writing this command. This command is valid

only during the sector erase operation, including the

50 µs time-out period during the sector erase com-

mand sequence. The Erase Suspend command is

ignored if written during the chip erase operation or

Embedded Program algorithm.

START

When the Erase Suspend command is written during

the sector erase operation, the device requires a

maximum of 20 µs to suspend the erase operation.

However, when the Erase Suspend command is writ-

ten during the sector erase time-out, the device

immediately terminates the time-out period and sus-

pends the erase operation.

Write Erase

Command Sequence

(Notes 1, 2)

After the erase operation has been suspended, the

bank enters the erase-suspend-read mode. The sys-

tem can read data from or program data to any

sector not selected for erasure. (The device “erase

suspends” all sectors selected for erasure.) Reading

at any address within erase-suspended sectors pro-

duces status information on DQ7–DQ0. The system

can use DQ7, or DQ6 and DQ2 together, to deter-

mine if a sector is actively erasing or is erase-

suspended. Refer to the Write Operation Status sec-

tion for information on these status bits.

Data Poll to Erasing

Bank from System

Embedded

Erase

algorithm

in progress

No

Data = FFh?

Yes

After an erase-suspended program operation is com-

plete, the bank returns to the erase-suspend-read

mode. The system can determine the status of the

program operation using the DQ7 or DQ6 status bits,

just as in the standard Byte Program operation.

Refer to the Write Operation Status section for more

information.

Erasure Completed

Notes:

1. See Table 5 for erase command sequence.

2. See the section on DQ3 for information on the sector erase timer.

Figure 4. Erase Operation

Am29DL400B

17

COMMAND DEFINITIONS

Table 5. Am29DL400B Command Definitions

Bus Cycles (Notes 2–5)

Third Fourth

Addr

Command

Sequence

(Note 1)

First

Second

Fifth

Sixth

Addr Data Addr Data

Data

Addr

Data Addr Data Addr Data

Read (Note 6)

Reset (Note 7)

1

RA

RD

F0

XXX

555

AAA

555

AAA

555

AAA

Word

Byte

Word

Byte

Word

Byte

2AA

555

2AA

555

2AA

555

(BA)555

(BA)AAA

(BA)555

(BA)AAA

(BA)555

(BA)AAA

Manufacturer ID

4

AA

55

90

(BA)X00

01

(BA)X01

(BA)X02

(BA)X01

(BA)X02

220C

0C

Device ID,

Top Boot Block

220F

0F

Device ID,

Bottom Boot Block

XX00

XX01

00

(SA)

X02

Word

Byte

555

AAA

2AA

555

(BA)555

(BA)AAA

Sector Protect Verify

(Note 9)

4

AA

55

90

(SA)

X04

01

Word

Byte

Word

Byte

555

AAA

555

AAA

XXX

BA

2AA

555

2AA

555

PA

555

AAA

555

AAA

Program

4

3

AA

55

A0

20

PA

PD

Unlock Bypass

Unlock Bypass Program (Note 10)

Unlock Bypass Reset (Note 11)

2

A0

90

PD

00

XXX

2AA

555

2AA

555

Word

555

AAA

555

AAA

BA

555

AAA

555

AAA

555

AAA

555

AAA

2AA

555

2AA

555

AAA

Chip Erase

Byte

6

AA

55

80

AA

55

10

30

Word

Sector Erase

Byte

SA

Erase Suspend (Note 12)

Erase Resume (Note 13)

1

B0

30

BA

Legend:

X = Don’t care

RA = Address of the memory location to be read.

RD = Data read from location RA during read operation.

PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse,

whichever happens later.

PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first.

SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A17–A12 uniquely select any sector.

BA = Address of the bank that is being switched to autoselect mode, is in bypass mode, or is being erased. Address bits A17–

A16 select a bank.

Notes:

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

8. The fourth cycle of the autoselect command sequence is

a read cycle. The system must provide the bank address

to obtain the manufacturer or device ID information.

3. Except when reading array or autoselect data, all bus

cycles are write operations.

9. The data is 00h for an unprotected sector and 01h for a

protected sector. See the Autoselect Command

Sequence section for more information.

10.The Unlock Bypass command is required prior to the

Unlock Bypass Program command.

4. Data bits DQ15–DQ8 are don’t cares for unlock and

command cycles in word mode.

5. Address bits A17–A11 are don’t cares for unlock and

command cycles, unless bank address (BA) is required.

6. No unlock or command cycles required when bank is in

read mode.

11.The Unlock Bypass Reset command is required to return

to reading array data when the bank is in the unlock

bypass mode.

7. The Reset command is required to return to reading

array data (or to the erase-suspend-read mode if

previously in Erase Suspend) when a bank is in the

autoselect mode, or if DQ5 is goes high (while the bank

is providing status information).

12.The system may read and program in non-erasing

sectors, or enter the autoselect mode, when in the Erase

Suspend mode. The Erase Suspend command is valid

only during a sector erase operation, and requires the

bank address.

13. The Erase Resume command is valid only during the Erase

Suspend mode, and requires the bank address.

18

Am29DL400B

WRITE OPERATION STATUS

The device provides several bits to determine the

status of a write operation in the bank where a pro-

gram or erase operation is in progress: DQ2, DQ3,

DQ5, DQ6, DQ7, and RY/BY#. Table 6 and the fol-

lowing subsections describe the function of these

bits. DQ7, RY/BY#, and DQ6 each offer a method for

determining whether a program or erase operation is

complete or in progress. These three bits are dis-

cussed first.

20 in the AC Characteristics section shows the Data#

Polling timing diagram.

START

Read DQ7–DQ0

Addr = VA

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host sys-

tem whether an Embedded Program or Erase

algorithm is in progress or completed, or whether a

bank is in Erase Suspend. Data# Polling is valid after

the rising edge of the final WE# pulse in the com-

mand sequence.

Yes

DQ7 = Data?

During the Embedded Program algorithm, the device

outputs on DQ7 the complement of the datum pro-

grammed to DQ7. This DQ7 status also applies to

programming during Erase Suspend. When the Em-

bedded Program algorithm is complete, the device

outputs the datum programmed to DQ7. The system

must provide the program address to read valid sta-

tus information on DQ7. If a program address falls

within a protected sector, Data# Polling on DQ7 is

active for approximately 1 µs, then that bank returns

to reading array data.

No

DQ5 = 1?

Yes

Read DQ7–DQ0

Addr = VA

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase

algorithm is complete, or if the bank enters the

Erase Suspend mode, Data# Polling produces a “1”

on DQ7. The system must provide an address within

any of the sectors selected for erasure to read valid

status information on DQ7.

Yes

DQ7 = Data?

No

After an erase command sequence is written, if all

sectors selected for erasing are protected, Data#

Polling on DQ7 is active for approximately 100 µs,

then the bank returns to reading array data. If not all

selected sectors are protected, the Embedded Erase

algorithm erases the unprotected sectors, and ig-

nores the selected sectors that are protected.

However, if the system reads DQ7 at an address

within a protected sector, the status may not be

valid.

PASS

FAIL

Notes:

1. VA = Valid address for programming. During a sector

erase operation, a valid address is any sector address

within the sector being erased. During chip erase, a valid

address is any non-protected sector address.

Just prior to the completion of an Embedded Pro-

gram or Erase operation, DQ7 may change

asynchronously with DQ0–DQ6 while Output Enable

(OE#) is asserted low. That is, the device may

change from providing status information to valid

data on DQ7. Depending on when the system sam-

ples the DQ7 output, it may read the status or valid

data. Even if the device has completed the program

or erase operation and DQ7 has valid data, the data

outputs on DQ0–DQ6 may be still invalid. Valid data

on DQ0–DQ7 will appear on successive read cycles.

2. DQ7 should be rechecked even if DQ5 = “1” because DQ7

may change simultaneously with DQ5.

Figure 5. Data# Polling Algorithm

RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output pin

that indicates whether an Embedded Algorithm is in

progress or complete. The RY/BY# status is valid

after the rising edge of the final WE# pulse in the

command sequence. Since RY/BY# is an open-drain

output, several RY/BY# pins can be tied together in

Table 6 shows the outputs for Data# Polling on DQ7.

Figure 5 shows the Data# Polling algorithm. Figure

parallel with a pull-up resistor to V

.

CC

Am29DL400B

19

If the output is low (Busy), the device is actively

erasing or programming. (This includes program-

ming in the Erase Suspend mode.) If the output is

high (Ready), the device is ready to read array data,

is in the standby mode, or one of the banks is in the

erase-suspend-read mode.

DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, when used with DQ6, in-

dicates whether a particular sector is actively erasing

(that is, the Embedded Erase algorithm is in

progress), or whether that sector is erase-sus-

pended. Toggle Bit II is valid after the rising edge of

the final WE# pulse in the command sequence.

Table 6 shows the outputs for RY/BY#.

DQ2 toggles when the system reads at addresses

within those sectors that have been selected for era-

sure. (The system may use either OE# or CE# to

control the read cycles.) But DQ2 cannot distinguish

whether the sector is actively erasing or is erase-

suspended. DQ6, by comparison, indicates whether

the device is actively erasing, or is in Erase Suspend,

but cannot distinguish which sectors are selected for

erasure. Thus, both status bits are required for sec-

tor and mode information. Refer to Table 6 to

compare outputs for DQ2 and DQ6.

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded

Program or Erase algorithm is in progress or com-

plete, or whether the device has entered the Erase

Suspend mode. Toggle Bit I may be read at any ad-

dress within the programming or erasing bank, and

is valid after the rising edge of the final WE# pulse in

the command sequence (prior to the program or

erase operation), and during the sector erase time-

out.

During an Embedded Program or Erase algorithm op-

eration, successive read cycles to any address within

the programming or erasing bank cause DQ6 to tog-

gle. The system may use either OE# or CE# to

control the read cycles. When the operation is com-

plete, DQ6 stops toggling.

Figure 6 shows the toggle bit algorithm in flowchart

form, and the section “DQ2: Toggle Bit II” explains

the algorithm. See also the DQ6: Toggle Bit I subsec-

tion. Figure 21 shows the toggle bit timing diagram.

Figure 22 shows the differences between DQ2 and

DQ6 in graphical form.

After an erase command sequence is written, if all

sectors selected for erasing are protected, DQ6 tog-

gles for approximately 100 µs, then returns to

reading array data. If not all selected sectors are

protected, the Embedded Erase algorithm erases the

unprotected sectors, and ignores the selected sec-

tors that are protected.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 6 for the following discussion. When-

ever the system initially begins reading toggle bit

status, it must read DQ7–DQ0 at least twice in a row

to determine whether a toggle bit is toggling. Typi-

cally, the system would note and store the value of

the toggle bit after the first read. After the second

read, the system would compare the new value of

the toggle bit with the first. If the toggle bit is not

toggling, the device has completed the program or

erase operation. The system can read array data on

DQ7–DQ0 on the following read cycle.

The system can use DQ6 and DQ2 together to deter-

mine whether a sector is actively erasing or is erase-

suspended. When a bank is actively erasing (that is,

the Embedded Erase algorithm is in progress), DQ6

toggles. When that bank enters the Erase Suspend

mode, DQ6 stops toggling. However, the system

must also use DQ2 to determine which sectors are

erasing or erase-suspended. Alternatively, the sys-

tem can use DQ7 (see the subsection on DQ7:

Data# Polling).

However, if after the initial two read cycles, the sys-

tem determines that the toggle bit is still toggling,

the system also should note whether the value of

DQ5 is high (see the section on DQ5). If it is, the

system should then determine again whether the

toggle bit is toggling, since the toggle bit may have

stopped toggling just as DQ5 went high. If the toggle

bit is no longer toggling, the device has successfully

completed the program or erase operation. If it is

still toggling, the device did not completed the oper-

ation successfully, and the system must write the

reset command to return to reading array data.

If a program address falls within a protected sector,

DQ6 toggles for approximately 1 µs after the pro-

gram command sequence is written, then returns to

reading array data.

DQ6 also toggles during the erase-suspend-program

mode, and stops toggling once the Embedded Pro-

gram algorithm is complete.

Table 6 shows the outputs for Toggle Bit I on DQ6.

Figure 6 shows the toggle bit algorithm. Figure 21 in

the “AC Characteristics” section shows the toggle bit

timing diagrams. Figure 22 shows the differences be-

tween DQ2 and DQ6 in graphical form. See also the

subsection on DQ2: Toggle Bit II.

The remaining scenario is that the system initially

determines that the toggle bit is toggling and DQ5

has not gone high. The system may continue to

monitor the toggle bit and DQ5 through successive

read cycles, determining the status as described in

the previous paragraph. Alternatively, it may choose

to perform other system tasks. In this case, the sys-

tem must start at the beginning of the algorithm

when it returns to determine the status of the opera-

tion (top of Figure 6).

20

Am29DL400B

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time

has exceeded a specified internal pulse count limit.

Under these conditions DQ5 produces a “1,” indicat-

ing that the program or erase cycle was not

successfully completed.

START

Read DQ7–DQ0

The device may output a “1” on DQ5 if the system

tries to program a “1” to a location that was previ-

ously programmed to “0.” Only an erase operation

can change a “0” back to a “1.” Under this condi-

tion, the device halts the operation, and when the

timing limit has been exceeded, DQ5 produces a “1”.

Read DQ7–DQ0

Under both these conditions, the system must write

the reset command to return to reading array data

(or to the erase-suspend-read mode if a bank was

previously in the erase-suspend-program mode).

No

Toggle Bit

= Toggle?

DQ3: Sector Erase Timer

Yes

After writing a sector erase command sequence, the

system may read DQ3 to determine whether or not

erasure has begun. (The sector erase timer does not

apply to the chip erase command.) If additional sec-

tors are selected for erasure, the entire time-out also

applies after each additional sector erase command.

When the time-out period is complete, DQ3 switches

from a “0” to a “1”. If the system can guarantee the

time between additional sector erase commands to

be less than 50 µs, it need not monitor DQ3. See

also the Sector Erase Command Sequence section.

No

DQ5 = 1?

Yes

Read DQ7–DQ0

Twice

After the sector erase command is written, the sys-

tem should read the status of DQ7 (Data# Polling) or

DQ6 (Toggle Bit I) to ensure that the device has ac-

cepted the command sequence, and then read DQ3.

If DQ3 is “1”, the Embedded Erase algorithm has be-

gun; all further commands (except Erase Suspend)

are ignored until the erase operation is complete. If

DQ3 is “0”, the device will accept additional sector

erase commands. To ensure the command has been

accepted, the system software should check the sta-

tus of DQ3 prior to and following each subsequent

sector erase command. If DQ3 is high on the second

status check, the last command might not have been

accepted.

Toggle Bit

= Toggle?

No

Yes

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Note: The system should recheck the toggle bit even if DQ5

= “1” because the toggle bit may stop toggling as DQ5

changes to “1.” See the subsections on DQ6 and DQ2 for

more information.

Table 6 shows the status of DQ3 relative to the other

status bits.

Figure 6. Toggle Bit Algorithm

Am29DL400B

21

Table 6. Write Operation Status

DQ7

DQ5

DQ2

Status

(Note 2)

DQ6

Toggle

(Note 1)

DQ3

N/A

1

(Note 2)

RY/BY#

Embedded Program Algorithm

Embedded Erase Algorithm

Erase

Erase-Suspend-

Read

DQ7#

0

No toggle

Toggle

0

Standard

Mode

1

No toggle

0

N/A

Toggle

1

Suspended Sector

Erase

Suspend

Mode

Non-Erase

Suspended Sector

Data

0

Data

N/A

Data

N/A

1

0

Erase-Suspend-Program

DQ7#

Toggle

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

Refer to the section on DQ5 for more information.

2. DQ7 and DQ2 require a valid address when reading

status information. Refer to the appropriate subsection

for further details.

3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm is in

progress. The device outputs array data if the system addresses a non-busy bank.

22

Am29DL400B

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

A9, OE#,

Plastic Packages. . . . . . . . . . . . . .–65°C to +150°C

and RESET# (Note 2). . . . . . .–0.5 V to +12.5 V

Ambient Temperature

All other pins

with Power Applied. . . . . . . . . . . .–65°C to +125°C

(Note 1) . . . . . . . . . . . . . . –0.5 V to V +0.5 V

CC

Voltage with Respect to Ground

Output Short Circuit Current (Note 3). . . . . 200 mA

V

(Note 1) . . . . . . . . . . . . . .–0.5 V to +4.0 V

CC

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V.

During voltage transitions, input or I/O pins may

undershoot V_SSto –2.0 V for periods of up to 20 ns.

Maximum DC voltage on input or I/O pins is V_CC+0.5 V.

See Figure 7. During voltage transitions, input or I/O

pins may overshoot to V_CC+2.0 V for periods up to 20

ns. See Figure 8.

A9 is +12.5 V which may overshoot to 14.0 V for periods

up to 20 ns.

3. No more than one output may be shorted to ground at a

time. Duration of the short circuit should not be greater

than one second.

Stresses above those listed under “Absolute Maximum Rat-

ings” may cause permanent damage to the device. This is a

stress rating only; functional operation of the device at

these or any other conditions above those indicated in the

operational sections of this data sheet is not implied. Expo-

sure of the device to absolute maximum rating conditions

for extended periods may affect device reliability.

2. Minimum DC input voltage on pins A9, OE#, and

RESET# is –0.5 V. During voltage transitions, A9, OE#,

and RESET# may undershoot V_SSto –2.0 V for periods

of up to 20 ns. See . Maximum DC input voltage on pin

20 ns

+0.8 V

–0.5 V

–2.0 V

20 ns

Figure 7. Maximum Negative

Overshoot Waveform

20 ns

V_CC

+2.0 V

V_CC

+0.5 V

2.0 V

20 ns

Figure 8. Maximum Positive

Overshoot Waveform

Am29DL400B

23

OPERATING RANGES

Commercial (C) Devices

Extended (E) Devices

Ambient Temperature (T ). . . . . . –55°C to +125°C

Ambient Temperature (T ). . . . . . . . . 0°C to +70°C

A

Industrial (I) Devices

V

Supply Voltages

CC

Ambient Temperature (T ). . . . . . . –40°C to +85°C

V

for all devices . . . . . . . . . . . . . .2.7 V to 3.6 V

A

CC

Operating ranges define those limits between which the functionality of the device is guaranteed.

24

Am29DL400B

DC CHARACTERISTICS

CMOS Compatible

Parameter

Symbol

I_LI

Parameter Description

Test Conditions

V_IN= V_SSto V_CC

Min

Typ

Max

± 1.0

35

Unit

µA

,

Input Load Current

V_CC= V_{CC max}

I_LIT

A9 Input Load Current

Output Leakage Current

V_CC= V_{CC max}; A9 = 12.5 V

µA

V_OUT= V_SSto V_CC

V_CC= V_{CC max}

,

I_LO

± 1.0

µA

5 MHz

1 MHz

5 MHz

1 MHz

7

2

7

2

12

4

CE# = V_IL,OE# = V_IH

Byte Mode

,

V_CCActive Read Current

(Notes 1, 2)

I_CC1

mA

12

4

CE# = V_IL,OE# = V_IH

Word Mode

V_CCActive Write Current

(Notes 2, 3)

I_CC2

CE# = V_IL,OE# = V_IH, WE# = V_IL

OE# = V_IL

15

30

V_CCStandby Current

(Note 2)

;

I_CC3

I_CC4

I_CC5

0.2

5

µA

CE#, RESET# = V_CC± ±0.3 V

V_CCReset Current (Note 2)

RESET# = V_SS± ±0.3 V

Automatic Sleep Mode

(Notes 2, 4)

V_IH= V_CC± 0.3 V;

V_IL= V_SS± ±0.3 V

V_CCActive Read-While-

Program Current (Notes 1, 2,

5)

Byte

21

45

CE# = V_IL,

OE# ₌V_IH

I_CC6

I_CC7

I_CC8

mA

Word

Byte

21

45

V_CCActive Read-While-Erase

Current (Notes 1, 2, 5)

CE# = V_IL,

OE# ₌V_IH

Word

V_CCActive Program-While-

Erase-Suspended Current

(Notes 2, 5)

CE# = V_IL,

OE# ₌V_IH

17

35

V_IL

Input Low Voltage

Input High Voltage

–0.5

0.8

V

V_IH

0.7 x V_CC

V_CC+ 0.3

Voltage for Autoselect and

Temporary Sector Unprotect

V_ID

V_CC= 3.0 V ± 10%

11.5

12.5

0.45

V

V_OL

Output Low Voltage

I_OL= 4.0 mA, V_CC= V_{CC min}

_OH= –2.0 mA, V_CC= V_{CC min}

I_OH= –100 µA, V_CC= V_{CC min}

V

V_OH1

V_OH2

I

0.85 V_CC

V_CC–0.4

Output High Voltage

Low V_CCLock-Out Voltage

(Note 5)

V_LKO

2.3

2.5

V

Notes:

1. The I_CCcurrent listed is typically less than 2 mA/MHz, with OE# at V_IH

.

2. Maximum I_CCspecifications are tested with V_CC

V_CCmax.

=

3.

I

_CCactive while Embedded Erase or Embedded Program

is in progress.

4. Automatic sleep mode enables the low power mode

when addresses remain stable for t_ACC+ 30 ns. Typical

sleep mode current is 200 nA.

5. Not 100% tested.

Am29DL400B

25

DC CHARACTERISTICS

Zero-Power Flash

20

15

10

5

0

500

1000

1500

2000

2500

3000

3500

4000

Time in ns

Note: Addresses are switching at 1 MHz

Figure 9.

I

Current vs. Time (Showing Active and Automatic Sleep Currents)

CC1

10

8

3.6 V

2.7 V

6

4

2

0

1

2

3

4

5

Frequency in MHz

Note: T = 25 °C

Figure 10. Typical I

vs. Frequency

CC1

26

Am29DL400B

TEST CONDITIONS

3.3 V

2.7 kΩ

Device

Under

Test

C

L

6.2 kΩ

Note: Diodes are IN3064 or equivalent

Figure 11. Test Setup

Table 7. Test Specifications

Test Condition

-70, -80

All others

1 TTL gate

Unit

Output Load

Output Load Capacitance, C_L

(including jig capacitance)

30

100

pF

Input Rise and Fall Times

5

0.0–3.0

1.5

ns

V

Input Pulse Levels

Input timing measurement reference levels

V

Output timing measurement reference levels

1.5

V

Key to Switching Waveforms

WAVEFORM

INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Center Line is High Impedance State (High Z)

3.0 V

0.0 V

1.5 V

Input

Measurement Level

Output

Figure 12. Input Waveforms and Measurement Levels

Am29DL400B

27

AC CHARACTERISTICS

Read-Only Operations

Parameter

Speed Options

Description

JEDEC

Std

Test Setup

-70

-80

-90

-120 Unit

t_AVAV

t_RC

Read Cycle Time (Note 1)

Min

70

80

90

120

ns

CE#, OE# =

V_IL

t_AVQV

t_ACC

Address to Output Delay

Max

70

80

90

t_ELQV

t_GLQV

t_EHQZ

t_GHQZ

t_CE

t_OE

t_DF

Chip Enable to Output Delay

OE# = V_IL

Max

70

30

80

30

90

35

120

50

ns

Output Enable to Output Delay

Chip Enable to Output High Z (Note 1)

Output Enable to Output High Z (Note 1)

16

Output Hold Time From Addresses, CE# or

OE#, Whichever Occurs First

t_AXQX

t_OH

Min

0

ns

Read

Output Enable Hold

Time (Note 1)

t_OEH

Toggle and

10

Data# Polling

Notes:

1. Not 100% tested.

2. See Figure 11 and Table 7 for test specifications.

t_RC

Addresses Stable

t_ACC

Addresses

CE#

t_RH

t_DF

t_OE

OE#

t_OEH

WE#

t_CE

t_OH

HIGH Z

Output Valid

Outputs

RESET#

RY/BY#

0 V

Figure 13. Read Operation Timings

28

Am29DL400B

AC CHARACTERISTICS

Hardware Reset (RESET#)

Parameter

Description

JEDEC

Std

All Speed Options

Unit

RESET# Pin Low (During Embedded Algorithms)

to Read Mode (See Note)

t_Ready

Max

20

µs

RESET# Pin Low (NOT During Embedded

Algorithms) to Read Mode (See Note)

t_Ready

500

ns

t_RP

t_RH

t_RPD

t_RB

RESET# Pulse Width

Min

500

50

20

0

ns

µs

ns

Reset High Time Before Read (See Note)

RESET# Low to Standby Mode

RY/BY# Recovery Time

Note: Not 100% tested.

RY/BY#

CE#, OE#

RESET#

t_RH

t_RP

t_Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

t_Ready

RY/BY#

t_RB

CE#, OE#

RESET#

t_RP

Figure 14. Reset Timings

Am29DL400B

29

AC CHARACTERISTICS

Word/Byte Configuration (BYTE#)

Parameter

Speed Options

Description

JEDEC

Std

t_{ELFL/ ELFH}

t_FLQZ

t_FHQV

-70

-80

-90

-120

Unit

ns

t

CE# to BYTE# Switching Low or High

BYTE# Switching Low to Output HIGH Z

BYTE# Switching High to Output Active

Max

Min

5

25

70

25

80

30

90

30

ns

120

ns

CE#

OE#

BYTE#

t_ELFL

Data Output

(DQ0–DQ14)

Data Output

(DQ0–DQ7)

BYTE#

DQ0–DQ14

Switching

from word

to byte

mode

Address

Input

DQ15

Output

DQ15/A-1

t_FLQZ

t_ELFH

BYTE#

Switching

from byte

to word

Data Output

(DQ0–DQ7)

Data Output

DQ0–DQ14

DQ15/A-1

(DQ0–DQ14)

mode

Address

Input

DQ15

Output

t_FHQV

Figure 15. BYTE# Timings for Read Operations

CE#

The falling edge of the last WE# signal

WE#

BYTE#

t_SET

(t_AS

)

t_HOLD(t_AH

)

Note: Refer to the Erase/Program Operations table for t_ASand t_AHspecifications.

Figure 16. BYTE# Timings for Write Operations

30

Am29DL400B

AC CHARACTERISTICS

Erase and Program Operations

Parameter

Speed Options

Description

JEDEC

t_AVAV

Std

t_WC

t_AS

-70

-80

-90 -120 Unit

Write Cycle Time (Note 1)

Address Setup Time

Min

70

80

90

120

ns

t_AVWL

0

Address Setup Time to OE# low during toggle bit

polling

t_ASO

t_AH

Min

45

50

ns

t_WLAX

Address Hold Time

Address Hold Time From CE# or OE# high

during toggle bit polling

t_AHT

0

t_DVWH

t_WHDX

t_DS

t_DH

Data Setup Time

Min

35

20

35

20

45

20

50

25

ns

Data Hold Time

t_OEPH

Output Enable High during toggle bit polling

Read Recovery Time Before Write

(OE# High to WE# Low)

t_GHWL

Min

ns

t_ELWL

t_WHEH

t_WLWH

t_WHDL

t_CS

t_CH

CE# Setup Time

Min

Typ

Min

0

ns

CE# Hold Time

t_WP

Write Pulse Width

35

50

t_WPH

t_SR/W

Write Pulse Width High

30

0

Zero Latency Between Read and Write Operations

Byte

9

t_WHWH1

t_WHWH2

t_WHWH1Programming Operation (Note 2)

t_WHWH2Sector Erase Operation (Note 2)

µs

Word

11

0.7

50

0

sec

µs

t_VCS

t_RB

V_CCSetup Time (Note 1)

Write Recovery Time from RY/BY#

Program/Erase Valid to RY/BY# Delay

ns

t_BUSY

90

ns

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

Am29DL400B

31

AC CHARACTERISTICS

Program Command Sequence (last two cycles)

Read Status Data (last two cycles)

t_AS

PA

t_WC

Addresses

555h

PA

t_AH

CE#

OE#

t_CH

t_WHWH1

t_WP

WE#

Data

t_WPH

t_CS

t_DS

t_DH

PD

D_OUT

A0h

Status

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. PA = program address, PD = program data, D_OUTis the true data at the program address.

2. Illustration shows device in word mode.

Figure 17. Program Operation Timings

t_AS

SA

t_WC

VA

Addresses

CE#

2AAh

VA

555h for chip erase

t_AH

t_CH

OE#

t_WP

WE#

t_WPH

t_WHWH2

t_CS

t_DS

t_DH

In

Progress

Data

Complete

55h

30h

10 for Chip Erase

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status” ).

2. Illustration shows device in word mode.

Figure 18. Chip/Sector Erase Operation Timings

32

Am29DL400B

AC CHARACTERISTICS

t_WC

Valid PA

t_WC

t_RC

t_WC

Valid PA

Valid RA

Valid PA

Addresses

t_AH

t_CPH

t_ACC

t_CE

CE#

t_CP

t_OE

OE#

t_OEH

t_GHWL

t_WP

WE#

t_DF

t_WPH

t_DS

t_OH

t_DH

Valid

Out

Valid

In

Valid

In

Valid

In

Data

t_SR/W

WE# Controlled Write Cycle

Read Cycle

CE# Controlled Write Cycles

Figure 19. Back-to-Back Read/Write Cycle Timings

t_RC

Addresses

CE#

VA

t_ACC

t_CE

VA

t_CH

t_OE

OE#

WE#

t_OEH

t_DF

t_OH

High Z

DQ7

Valid Data

Complement

True

DQ0–DQ6

Status Data

True

Valid Data

Status Data

t_BUSY

RY/BY#

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data

read cycle.

Figure 20. Data# Polling Timings (During Embedded Algorithms)

Am29DL400B

33

AC CHARACTERISTICS

t_AHT

t_AS

Addresses

t_AHT

t_ASO

CE#

t_OEH

WE#

t_CEPH

t_OEPH

OE#

t_DH

Valid Data

t_OE

Valid

Status

Valid

Status

Valid

Status

DQ6/DQ2

Valid Data

(first read)

(second read)

(stops toggling)

RY/BY#

Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status

read cycle, and array data read cycle

Figure 21. Toggle Bit Timings (During Embedded Algorithms)

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

Erase

Erase Suspend

Read

Erase

Suspend

Program

Erase

Complete

WE#

Erase

Erase Suspend

Read

DQ6

DQ2

Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle

DQ2 and DQ6.

Figure 22. DQ2 vs. DQ6

34

Am29DL400B

AC CHARACTERISTICS

Temporary Sector Unprotect

Parameter

Description

JEDEC

Std

All Speed Options

Unit

t_VIDR

V_IDRise and Fall Time (See Note)

Min

500

ns

RESET# Setup Time for Temporary Sector

Unprotect

t_RSP

4

µs

RESET# Hold Time from RY/BY# High for

Temporary Sector Unprotect

t_RRB

Min

Note: Not 100% tested.

12 V

RESET#

0 V or 3 V

t_VIDR

Program or Erase Command Sequence

CE#

WE#

t_RRB

t_RSP

RY/BY#

Figure 23. Temporary Sector Unprotect Timing Diagram

Am29DL400B

35

AC CHARACTERISTICS

V

ID

IH

V

RESET#

SA, A6,

A1, A0

Valid*

Status

Sector Protect/Unprotect

Verify

40h

Data

60h

Sector Protect: 100 µs

Sector Unprotect: 10 ms

1 µs

CE#

WE#

OE#

*

For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.

Figure 24. Sector Protect/Unprotect Timing Diagram

36

Am29DL400B

AC CHARACTERISTICS

Alternate CE# Controlled Erase/Program

Operations

Parameter

Speed Options

Description

JEDEC

t_AVAV

t_AVWL

t_ELAX

Std

t_WC

t_AS

t_AH

t_DS

t_DH

-70

-80

-90

-120

Unit

ns

Write Cycle Time (Note 1)

Address Setup Time

Address Hold Time

Data Setup Time

Min

70

80

90

120

0

ns

45

35

45

35

45

50

ns

t_DVEH

t_EHDX

ns

Data Hold Time

0

ns

Read Recovery Time Before Write

(OE# High to WE# Low)

t_GHEL

Min

ns

t_WLEL

t_EHWH

t_ELEH

t_EHEL

t_WS

t_WH

t_CP

WE# Setup Time

WE# Hold Time

Min

Typ

0

ns

CE# Pulse Width

CE# Pulse Width High

35

50

t_CPH

30

9

Byte

Programming Operation (Note

2)

t_WHWH1

µs

Word

11

0.7

t_WHWH2

Notes:

t_WHWH2Sector Erase Operation (Note 2)

sec

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

Am29DL400B

37

AC CHARACTERISTICS

555 for program

PA for program

2AA for erase

SA for sector erase

555 for chip erase

Data# Polling

Addresses

PA

t_WC

t_WH

t_AS

t_AH

WE#

OE#

t_GHEL

t_{WHWH1 or 2}

t_CP

CE#

Data

t_WS

t_CPH

t_DS

t_BUSY

t_DH

DQ7#

D_OUT

t_RH

A0 for program

55 for erase

PD for program

30 for sector erase

10 for chip erase

RESET#

RY/BY#

Notes:

1. Figure indicates last two bus cycles of a program or erase operation.

2. PA = program address, SA = sector address, PD = program data, DQ7# = complement of the data written to the device,

D_OUT= data written to the device.

3. Waveforms are for the word mode.

Figure 25. Alternate CE# Controlled Erase/Program Operation Timings

38

Am29DL400B

ERASE AND PROGRAMMING PERFORMANCE

Max (Note

Parameter

Typ (Note 1)

2)

Unit

sec

µs

Comments

Sector Erase Time

Chip Erase Time

Byte Program Time

Word Program Time

0.7

10

9

15

Excludes 00h programming

prior to erasure (Note 4)

300

360

13.5

8.7

11

4.5

2.9

µs

Excludes system level

overhead (Note 5)

Byte Mode

Word Mode

Chip Program Time

(Note 3)

sec

Notes:

1. Typical program and erase times assume the following

^{conditions: 25}°C, 3.0 V V_CC, 1,000,000 cycles.

Additionally, programming typicals assume

checkerboard pattern.

4. In the pre-programming step of the Embedded Erase

algorithm, all bytes are programmed to 00h before

erasure.

5. System-level overhead is the time required to execute

the two- or four-bus-cycle sequence for the program

command. See Table 5 for further information on

command definitions.

2. Under worst case conditions of 90°C, V_CC= 2.7 V,

1,000,000 cycles.

3. The typical chip programming time is considerably less

than the maximum chip programming time listed, since

most bytes program faster than the maximum program

times listed.

6. The device has a guaranteed minimum erase and program

cycle endurance of 1,000,000 cycles.

Am29DL400B

39

LATCHUP CHARACTERISTICS

Min

Max

Input voltage with respect to V_SSon all pins except I/O pins

(including A9, OE#, and RESET#)

–1.0 V

12.5 V

Input voltage with respect to V_SSon all I/O pins

V_CCCurrent

–1.0 V

V_CC+ 1.0 V

+100 mA

–100 mA

Includes all pins except V_CC. Test conditions: V_CC= 3.0 V, one pin at a time.

TSOP AND SO PIN CAPACITANCE

Parameter

Symbol

Parameter Description

Input Capacitance

Test Setup

V_IN= 0

Typ

6

Max

7.5

12

Unit

pF

C_IN

C_OUT

C_IN2

Output Capacitance

V_OUT= 0

V_IN= 0

8.5

7.5

pF

Control Pin Capacitance

9

pF

Notes:

1. Sampled, not 100% tested.

2. Test conditions T_A= 25°C, f = 1.0 MHz.

DATA RETENTION

Parameter Description

Test Conditions

150°C

Min

10

Unit

Years

Minimum Pattern Data Retention Time

125°C

20

40

Am29DL400B

PHYSICAL DIMENSIONS*

TS 048—48-Pin Standard TSOP

Dwg rev AA; 10/99

* For reference only. BSC is an ANSI standard for Basic Space Centering

Am29DL400B

41

PHYSICAL DIMENSIONS (continued)

TSR048—48-Pin Reverse TSOP

Dwg rev AA; 10/99

* For reference only. BSC is an ANSI standard for Basic Space Centering.

42

Am29DL400B

PHYSICAL DIMENSIONS (continued)

SO 044—44-Pin Small Outline

Dwg rev AC; 10/99

Am29DL400B

43

REVISION SUMMARY

Revision A (January 1998)

Initial release.

Distinctive Characterisitics

Added 20 Year data retention at 125° C bullet.

Ordering Information

Revision B (March 1998)

Corrected TSOP description to 48-pin.

Expanded data sheet from Advance Information to

Preliminary version.

Revision D+1 (March 23, 1999)

AC Characteristics, Read-only Operations table

Revision C (April 1998)

Corrected t , t

90 ns.

, and t for 90 ns speed option to

CE

RC ACC

Global

Changed -70R speed option to -70.

Revision E (December 7, 1999)

Figure 1, In-system Sector Protect/Unprotect

Algorithm

AC Characteristics—Figure 17. Program

Operations Timing and Figure 18. Chip/Sector

Erase Operations

Added “PSLSCNT=1” to sector protect algorithm.

Reset Command

Deleted t

at high.

and changed OE# waveform to start

GHWL

Deleted last paragraph; applies only to hardware

reset.

Physical Dimensions

DQ6: Toggle Bit I

Replaced figures with more detailed illustrations.

First and second para., clarified that the toggle bit

may be read “at any address within the program-

ming or erasing bank,” not at “any address.” Fourth

para., clarified “device” to “bank”

Revision E+1 (May 12, 2000)

Ordering Information

Optional processing: Deleted the burn-in option

Operating Ranges

AC Characteristics—Read-Only Operations

Deleted reference to regulated voltage range

Changed t to 16 ns for all speeds.

DF

DC Characteristics

Revision E+2 (November 21, 2000)

Added table of contents.

Added Note 4 reference to I

and I

.

CC7

CC6

Erase and Program Operations

Revision E+3 (January 7, 2005)

Corrected note references for t

, t

,

WHWH1 WHWH2

and t

Global

VCS

Added Colophon

Temporary Sector Unprotect

Added note reference to t

.

Updated Trademark

Updated fonts

VIDR

Figure 24, Sector Protect/Unprotect Timing

Diagram

Ordering Information

Updated figure to correct address waveform—valid ad-

dress not required in first cycle.

Added temperature ranges for Pb-free (Lead-free)

Packages

Alternate CE# Controlled Erase/Program

Operations

Added new valid combinations.

Revision E+4 (June 7, 2005)

Cover page and Title page

Corrected note references for t

, t

WHWH1 WHWH2

Erase and Programming Performance

In Note 2, changed worst case endurance to 1 million

cycles.

Updated EOL disclaimers. Added notation to

superseding documents.

Revision D (June 1999)

44

Am29DL400B

Colophon

The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary

industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that

includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal

injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control,

medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and

artificial satellite). Please note that Spansion LLC will not be liable to you and/or any third party for any claims or damages arising in connection with above-

mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such

failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels

and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on ex-

port under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the

prior authorization by the respective government entity will be required for export of those products.

Trademarks

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

ExpressFlash is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies

Am29DL400B

45


型号：	AM29DL400BB-120ED
厂家：	AMD
描述：	4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory 4兆位（ 512K的×8位/ 256千×16位） CMOS 3.0伏只，同时操作闪存闪存内存集成电路光电二极管
文件：	总47页 (文件大小：1121K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AM29DL400BB-120ED [AMD]

相关型号：

AM29DL400BB-120EDB

AM29DL400BB-120EE

AM29DL400BB-120EEB

AM29DL400BB-120EEB

AM29DL400BB-120EF

AM29DL400BB-120EFB

AM29DL400BB-120EI

AM29DL400BB-120EIB

AM29DL400BB-120EK

AM29DL400BB-120EKB

AM29DL400BB-120FC

AM29DL400BB-120FCB