AM29DL640D35WHE_技术文档

Am29DL640D

Data Sheet

This product has been retired and is not available for designs.

For new and current designs involving TSOP packages, S29JL064H supersedes Am29DL640D and is the factory-

recommended migration path. Please refer to the S29JL064H datasheet for specifications and ordering informa-

tion.

For new and current designs involving Fine-pitch BGA (FBGA) packages, S29PL064J supersedes Am29DL640D

and is the factory-recommended migration path. Please refer to the S29PL064J Datasheet for specifications and

ordering information.

Availability of this document is retained for reference and historical purposes only.

July 2003

The following document specifies Spansion memory products that are now offered by both Advanced

Micro Devices and Fujitsu. Although the document is marked with the name of the company that

originally developed the specification, these products will be offered to customers of both AMD and

Fujitsu.

Continuity of Specifications

There is no change to this datasheet as a result of offering the device as a Spansion product. Any

changes that have been made are the result of normal datasheet improvement and are noted in the

document revision summary, where supported. Future routine revisions will occur when appropri-

ate, and changes will be noted in a revision summary.

Continuity of Ordering Part Numbers

AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To

order these products, please use only the Ordering Part Numbers listed in this document.

For More Information

Please contact your local AMD or Fujitsu sales office for additional information about Spansion mem-

ory solutions.

Publication Number 23695 Revision C Amendment 3 Issue Date December 13, 2005

A D V A N C E I N F O R M A T I O N

THIS PAGE LEFT INTENTIONALLY BLANK

2

December 13, 2005

Am29DL640D

64 Megabit (8 M x 8-Bit/4 M x 16-Bit)

CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory

This product has been retired and is not available for designs.

For new and current designs involving TSOP packages, S29JL064H supersedes Am29DL640D and is the factory-recommended migration path. Please refer to the S29JL064H datasheet

for specifications and ordering information.

For new and current designs involving Fine-pitch BGA (FBGA) packages, S29PL064J supersedes Am29DL640D and is the factory-recommended migration path. Please refer to the

S29PL064J Datasheet for specifications and ordering information.

Availability of this document is retained for reference and historical purposes only.

DISTINCTIVE CHARACTERISTICS

ARCHITECTURAL ADVANTAGES

— 10 mA active read current at 5 MHz

— 200 nA in standby or automatic sleep mode

Simultaneous Read/Write operations

— Data can be continuously read from one bank while

executing erase/program functions in another bank.

Minimum 1 million erase cycles guaranteed per

sector

20 year data retention at 125°C

— Reliable operation for the life of the system

— Zero latency between read and write operations

Flexible Bank^TMarchitecture

— Read may occur in any of the three banks not being

written or erased.

SOFTWARE FEATURES

Data Management Software (DMS)

— Four banks may be grouped by customer to achieve

desired bank divisions.

— AMD-supplied software manages data programming,

enabling EEPROM emulation

Boot Sectors

— Eases historical sector erase flash limitations

— Top and bottom boot sectors in the same device

— Any combination of sectors can be erased

Supports Common Flash Memory Interface (CFI)

Program/Erase Suspend/Erase Resume

— Suspends program/erase operations to allow

programming/erasing in same bank

Manufactured on 0.23 µm process technology

Secured Silicon Sector: Extra 256 Byte sector

— Factory locked and identifiable: 16 bytes available for

secure, random factory Electronic Serial Number;

verifiable as factory locked through autoselect

function. ExpressFlash option allows entire sector to

be available for factory-secured data

Data# Polling and Toggle Bits

— Provides a software method of detecting the status of

program or erase cycles

Unlock Bypass Program command

— Reduces overall programming time when issuing

multiple program command sequences

— Customer lockable: Can be read or programmed just

like other sectors. Once locked, data cannot be

changed

HARDWARE FEATURES

Ready/Busy# output (RY/BY#)

— Hardware method for detecting program or erase

cycle completion

Zero Power Operation

— Sophisticated power management circuits reduce

power consumed during inactive periods to nearly

zero.

Hardware reset pin (RESET#)

— Hardware method of resetting the internal state

machine to the read mode

Compatible with JEDEC standards

— Pinout and software compatible with

single-power-supply flash standard

WP#/ACC input pin

— Write protect (WP#) function protects sectors 0, 1,

140, and 141, regardless of sector protect status

PACKAGE OPTIONS

■

63-ball Fine Pitch BGA

48-pin TSOP

— Acceleration (ACC) function accelerates program

timing

Sector protection

PERFORMANCE CHARACTERISTICS

— Hardware method of locking a sector, either

in-system or using programming equipment, to

prevent any program or erase operation within that

sector

High performance

— Access time as fast as 90 ns

— Program time: 4 µs/word typical utilizing Accelerate

function

— Temporary Sector Unprotect allows changing data in

protected sectors in-system

Ultra low power consumption (typical values)

— 2 mA active read current at 1 MHz

Publication# 23695 Rev: C Amendment/3

Issue Date: December 13, 2005

Refer to AMD’s Website (www.amd.com) for the latest information.

GENERAL DESCRIPTION

The Am29DL640D is a 64 megabit, 3.0 volt-only flash

memory device, organized as 4,194,304 words of 16

bits each or 8,388,608 bytes of 8 bits each. Word

mode data appears on DQ0–DQ15; byte mode data

appears on DQ0–DQ7. The device is designed to be

programmed in-system with the standard 3.0 volt V_CC

supply, and can also be programmed in standard

EPROM programmers.

byte ESN (Electronic Serial Number), customer code

(programmed through AMD’s ExpressFlash service),

or both. Customer Lockable parts may utilize the Se-

cured Silicon Sector as bonus space, reading and

writing like any other flash sector, or may permanently

lock their own code there.

DMS (Data Management Software) allows systems

to easily take advantage of the advanced architecture

of the simultaneous read/write product line by allowing

removal of EEPROM devices. DMS also allows the

system software to be simplified, as it performs all

functions necessary to modify data in file structures,

as opposed to single-byte modifications. To write or

update a particular piece of data (a phone number or

configuration data, for example), the user only needs

to state which piece of data is to be updated, and

where the updated data is located in the system. This

is an advantage compared to systems where

user-written software must keep track of the old data

location, status, logical to physical translation of the

data onto the Flash memory device (or memory de-

vices), and more. Using DMS, user-written software

does not need to interface with the Flash memory di-

rectly. Instead, the user's software accesses the Flash

memory by calling one of only six functions. AMD pro-

vides this software to simplify system design and

software integration efforts.

The device is available with an access time of 90 or

120 ns and is offered in 48-pin TSOP and 63-ball

Fine-Pitch BGA. Standard control pins—chip enable

(CE#), write enable (WE#), and output enable

(OE#)—control normal read and write operations, and

avoid bus contention issues.

The device requires only a single 3.0 volt power sup-

ply for both read and write functions. Internally

generated and regulated voltages are provided for the

program and erase operations.

Simultaneous Read/Write Operations with

Zero Latency

The Simultaneous Read/Write architecture provides

simultaneous operation by dividing the memory

space into four banks, two 8 Mb banks with small and

large sectors, and two 24 Mb banks of large sectors.

Sector addresses are fixed, system software can be

used to form user-defined bank groups.

The device offers complete compatibility with the

JEDEC single-power-supply Flash command set

standard. Commands are written to the command

register using standard microprocessor write timings.

Reading data out of the device is similar to reading

from other Flash or EPROM devices.

During an Erase/Program operation, any of the three

non-busy banks may be read from. Note that only two

banks can operate simultaneously. The device can im-

prove overall system performance by allowing a host

system to program or erase in one bank, then

immediately and simultaneously read from the other

bank, with zero latency. This releases the system from

waiting for the completion of program or erase

operations.

The host system can detect whether a program or

erase operation is complete by using the device sta-

tus bits: RY/BY# pin, DQ7 (Data# Polling) and

DQ6/DQ2 (toggle bits). After a program or erase cycle

has been completed, the device automatically returns

to the read mode.

The Am29DL640D can be organized as both a top and

bottom boot sector configuration.

Bank

Megabits

Sector Sizes

The sector erase architecture allows memory sec-

tors to be erased and reprogrammed without affecting

the data contents of other sectors. The device is fully

erased when shipped from the factory.

Eight 8 Kbyte/4 Kword,

Fifteen 64 Kbyte/32 Kword

Bank 1

8 Mb

Bank 2

Bank 3

24 Mb

Forty-eight 64 Kbyte/32 Kword

Hardware data protection measures include a low

V_CCdetector that automatically inhibits write opera-

tions during power transitions. The hardware sector

protection feature disables both program and erase

operations in any combination of the sectors of mem-

ory. This can be achieved in-system or via

programming equipment.

Eight 8 Kbyte/4 Kword,

Fifteen 64 Kbyte/32 Kword

Bank 4

8 Mb

Am29DL640D Features

The Secured Silicon Sector is an extra 256 byte sec-

tor capable of being permanently locked by AMD or

customers. The Secured Silicon Indicator Bit (DQ7)

is permanently set to a 1 if the part is factory locked,

and set to a 0 if customer lockable. This way, cus-

tomer lockable parts can never be used to replace a

factory locked part.

The device offers two power-saving features. When

addresses have been stable for a specified amount of

time, the device enters the automatic sleep mode.

The system can also place the device into the

standby mode. Power consumption is greatly re-

duced in both modes.

Factory locked parts provide several options. The Se-

cured Silicon Sector may store a secure, random 16

2

Am29DL640D

December 13, 2005

TABLE OF CONTENTS

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 6

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9

Table 1. Am29DL640D Device Bus Operations ................................9

Word/Byte Configuration ........................................ 9

Requirements for Reading Array Data ..................................... 9

Writing Commands/Command Sequences ............................ 10

Accelerated Program Operation ............................................. 10

Autoselect Functions .............................................................. 10

Simultaneous Read/Write Operations with Zero Latency ....... 10

Standby Mode ...................................................... 10

Automatic Sleep Mode ........................................................... 11

RESET#: Hardware Reset Pin ............................................... 11

Output Disable Mode .............................................................. 11

Table 2. Am29DL640D Sector Architecture ....................................11

Table 3. Bank Address ....................................................................14

Secured Silicon Sector Addresses............................. 14

Autoselect Mode ................................................... 14

Table 5. Am29DL640D Autoselect Codes, (High Voltage Method) 15

Sector/Sector Block Protection and Unprotection 16

Table 6. Am29DL640D Boot Sector/Sector Block Addresses for Pro-

tection/Unprotection ........................................................................16

Write Protect (WP#) ................................................................ 17

Table 7. WP#/ACC Modes ..............................................................17

Temporary Sector Unprotect .................................................. 17

Figure 1. Temporary Sector Unprotect Operation........................... 17

Figure 2. In-System Sector Protect/Unprotect Algorithms .............. 18

Secured Silicon Sector

Write Operation Status . . . . . . . . . . . . . . . . . . . . 29

DQ7: Data# Polling ................................................................. 29

Figure 6. Data# Polling Algorithm .................................................. 29

RY/BY#: Ready/Busy# ......................................... 30

DQ6: Toggle Bit I .................................................................... 30

Figure 7. Toggle Bit Algorithm........................................................ 30

DQ2: Toggle Bit II ................................................................... 31

Reading Toggle Bits DQ6/DQ2 ............................................... 31

DQ5: Exceeded Timing Limits ................................................ 31

DQ3: Sector Erase Timer ....................................................... 31

Table 13. Write Operation Status ................................................... 32

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 33

Figure 8. Maximum Negative Overshoot Waveform ...................... 33

Figure 9. Maximum Positive Overshoot Waveform........................ 33

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 33

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 10. I_CC1Current vs. Time (Showing Active and

Automatic Sleep Currents)............................................................. 35

Figure 11. Typical I_CC1vs. Frequency............................................ 35

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 12. Test Setup.................................................................... 36

KEY TO SWITCHING WAVEFORMS . . . . . . . . . . 36

Figure 13. Input Waveforms and Measurement Levels ................. 36

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 37

Read-Only Operations ........................................................... 37

Figure 14. Read Operation Timings............................................... 37

Hardware Reset (RESET#) .................................................... 38

Figure 15. Reset Timings............................................................... 38

Word/Byte Configuration (BYTE#) .......................................... 39

Figure 16. BYTE# Timings for Read Operations............................ 39

Figure 17. BYTE# Timings for Write Operations............................ 39

Erase and Program Operations .............................................. 40

Figure 18. Program Operation Timings.......................................... 41

Figure 19. Accelerated Program Timing Diagram.......................... 41

Figure 20. Chip/Sector Erase Operation Timings .......................... 42

Figure 21. Back-to-back Read/Write Cycle Timings ...................... 43

Figure 22. Data# Polling Timings (During Embedded Algorithms). 43

Figure 23. Toggle Bit Timings (During Embedded Algorithms)...... 44

Figure 24. DQ2 vs. DQ6................................................................. 44

Temporary Sector Unprotect .................................................. 45

Figure 25. Temporary Sector Unprotect Timing Diagram .............. 45

Figure 26. Sector/Sector Block Protect and

Flash Memory Region ............................................................ 19

Figure 3. Secured Silicon Sector Protect Verify.............................. 20

Hardware Data Protection ...................................................... 20

Low VCC Write Inhibit ............................................................ 20

Write Pulse “Glitch” Protection ............................................... 20

Logical Inhibit .......................................................................... 20

Power-Up Write Inhibit ............................................................ 20

Common Flash Memory Interface (CFI) . . . . . . .20

Table 8. CFI Query Identification String...................... 21

System Interface String............................................... 21

Table 10. Device Geometry Definition ........................ 22

Table 11. Primary Vendor-Specific Extended Query .. 23

Command Definitions . . . . . . . . . . . . . . . . . . . . . . 24

Reading Array Data ................................................................ 24

Reset Command ..................................................................... 24

Autoselect Command Sequence ............................................ 24

Enter/Exit Secured Silicon Sector

Unprotect Timing Diagram ............................................................. 46

Alternate CE# Controlled Erase and Program Operations ..... 47

Figure 27. Alternate CE# Controlled Write (Erase/Program)

Operation Timings.......................................................................... 48

Erase And Programming Performance . . . . . . . 49

Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 49

TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . . 49

Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 50

FBE063—63-Ball Fine-Pitch Ball Grid Array (FBGA)

Command Sequence .............................................................. 24

Byte/Word Program Command Sequence ............................. 25

Unlock Bypass Command Sequence ..................................... 25

Figure 4. Program Operation .......................................................... 26

Chip Erase Command Sequence ........................................... 26

Sector Erase Command Sequence ........................................ 26

Erase Suspend/Erase Resume Commands ........................... 27

Figure 5. Erase Operation............................................................... 27

Table 12. Am29DL640D Command Definitions .......... 28

12 x 11 mm package ..............................................................50

TS 048—48-Pin Standard TSOP ............................................ 51

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 52

December 13, 2005

Am29DL640D

3

PRODUCT SELECTOR GUIDE

Part Number

Am29DL640D

Speed Option

Standard Voltage Range: V_CC= 2.7–3.6 V

90

35

120

50

Max Access Time (ns), t_ACC

CE# Access (ns), t_CE

OE# Access (ns), t_OE

BLOCK DIAGRAM

V

CC

OE# BYTE#

SS

Mux

Bank 1

Bank 1 Address

A20–A0

X-Decoder

Bank 2 Address

RY/BY#

Bank 2

X-Decoder

A20–A0

RESET#

STATE

CONTROL

&

Status

WE#

CE#

DQ15–DQ0

COMMAND

REGISTER

BYTE#

Control

Mux

WP#/ACC

DQ0–DQ15

X-Decoder

Bank 3

Bank 3 Address

X-Decoder

Bank 4

A20–A0

Bank 4 Address

Mux

4

Am29DL640D

December 13, 2005

CONNECTION DIAGRAMS

A15

A14

A13

A12

A11

A10

A9

A8

1

2

3

4

5

6

7

8

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A16

BYTE#

V_SS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

V_CC

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

V_SS

CE#

A0

48-Pin Standard TSOP

A19

A20

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

WE#

RESET#

NC

WP#/ACC

RY/BY#

A18

A17

A7

A6

A5

A4

A3

A2

A1

63-Ball Fine-Pitch BGA (FBGA)

Top View, Balls Facing Down

L8

M8

A8

B8

NC

NC*

A7

B7

C7

D7

E7

F7

G7

H7

J7

K7

L7

M7

V_SS

NC

NC*

A13

A12

A14

A15

A16

BYTE# DQ15/A-1

C6

A9

D6

A8

E6

F6

G6

H6

J6

K6

A10

A11

DQ7

DQ14

DQ13

DQ6

C5

D5

E5

F5

G5

H5

J5

K5

V_CC

WE# RESET#

A21

A19

DQ5

DQ12

DQ4

C4 D4

E4

F4

G4

H4

J4

K4

RY/BY# WP#/ACC A18

A20

DQ2

DQ10

DQ11

DQ3

C3

A7

D3

E3

A6

F3

A5

G3

H3

J3

K3

A17

DQ0

DQ8

DQ9

DQ1

C2

A3

D2

A4

E2

A2

F2

A1

G2

A0

H2

J2

K2

L2

M2

A2

V_SS

CE#

OE#

NC*

A1

B1

L1

M1

* Balls are shorted together via the substrate but not connected to the die.

NC*

December 13, 2005

Am29DL640D

5

PIN DESCRIPTION

LOGIC SYMBOL

A0–A21

= 22 Addresses

22

DQ0–DQ14 = 15 Data Inputs/Outputs

(x16-only devices)

A0–A21

16 or 8

DQ0–DQ15

(A-1)

DQ15/A-1

= DQ15 (Data Input/Output, word

mode), A-1 (LSB Address Input, byte

mode)

CE#

OE#

CE#

OE#

WE#

= Chip Enable

= Output Enable

= Write Enable

WE#

WP#/ACC

RESET#

BYTE#

RY/BY#

WP#/ACC = Hardware Write Protect/

Acceleration Pin

RESET#

BYTE#

RY/BY#

V_CC

= Hardware Reset Pin, Active Low

= Selects 8-bit or 16-bit mode

= Ready/Busy Output

= 3.0 volt-only single power supply

(see Product Selector Guide for speed

options and voltage supply tolerances)

V_SS

NC

= Device Ground

= Pin Not Connected Internally

6

Am29DL640D

December 13, 2005

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is

formed by a combination of the following:

Am29DL640D

90

E

I

OPTIONAL PROCESSING

Blank

N

=

Standard Processing

16-byte ESN devices

(Contact an AMD representative for more information)

TEMPERATURE RANGE

I

=

Industrial (–40°C to +85°C)

E

F

K

Extended (–55°C to +125°C)

Industrial for Pb-free Package (–40°C to +85°C)

Extended for Pb-free Package (–55°C to +125°C)

PACKAGE TYPE

E

=

48-Pin Thin Small Outline Package

(TSOP) Standard Pinout (TS 048)

WH

=

63-Ball Fine-Pitch Ball Grid Array,

0.80 mm pitch, 12 x 11 mm package (FBE063)

SPEED OPTION

See Product Selector Guide and Valid Combinations

DEVICE NUMBER/DESCRIPTION

Am29DL640D

64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS Flash Memory

3.0 Volt-only Read, Program, and Erase

firm availability of specific valid combinations and to check on

newly released combinations.

Valid Combinations for TSOP Packages

Am29DL640D90

Am29DL640D120

EI, EF

Valid Combinations for BGA Packages

EI, EE, EF, EK

Order Number

Package Marking

Valid Combinations

WHF,

WHI

Am29DL640D90

D640D90V

D640D12V

I, F

Valid Combinations list configurations planned to be supported in

volume for this device. Consult the local AMD sales office to con-

WHI,

WHE,

WHF,

WHK

I, E,

F, K

Am29DL640D120

December 13, 2005

Am29DL640D

7

DEVICE BUS OPERATIONS

This section describes the requirements and use of

the device bus operations, which are initiated through

the internal command register. The command register

itself does not occupy any addressable memory loca-

tion. The register is a latch used to store the

commands, along with the address and data informa-

tion needed to execute the command. The contents of

the register serve as inputs to the internal state ma-

chine. The state machine outputs dictate the function

of the device. Table 1 lists the device bus operations,

the inputs and control levels they require, and the re-

sulting output. The following subsections describe

each of these operations in further detail.

Table 1. Am29DL640D Device Bus Operations

DQ8–DQ15

Addresses

(Note 2)

DQ0– BYTE# BYTE#

Operation

CE# OE# WE# RESET# WP#/ACC

DQ7

D_OUT

D_IN

= V_IH

D_OUT

D_IN

= V_IL

Read

Write

L

H

L

H

L/H

A_IN

DQ8–DQ14 =

High-Z, DQ15 = A-1

H

(Note 3)

V_CC

0.3 V

±

V_CC±

0.3 V

Standby

X

H

X

High-Z High-Z

High-Z

Output Disable

Reset

L

H

X

H

X

H

L

L/H

X

High-Z High-Z

High-Z

X

SA, A6 = L,

A1 = H, A0 = L

Sector Protect (Note 2)

L

X

H

X

L

X

V_ID

L/H

D_IN

X

SA, A6 = H,

A1 = H, A0 = L

Sector Unprotect (Note 2)

(Note 3)

Temporary Sector

Unprotect

A_IN

D_IN

High-Z

Legend: L = Logic Low = V_IL, H = Logic High = V_IH, V_ID= 8.5–12.5 V, V_HH= 9.0 0.5 V, X = Don’t Care, SA = Sector Address,

A_IN= Address In, D_IN= Data In, D_OUT= Data Out

Notes:

1. Addresses are A21:A0 in word mode (BYTE# = V_IH), A21:A-1 in byte mode (BYTE# = V_IL).

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the Sector/Sector

Block Protection and Unprotection section.

3. If WP#/ACC = V_IL, sectors 0, 1, 140, and 141 remain protected. If WP#/ACC = V_IH, protection on sectors 0, 1, 140, and 141

depends on whether they were last protected or unprotected using the method described in Sector/Sector Block Protection

and Unprotection. If WP#/ACC = V_HH, all sectors are unprotected.

Word/Byte Configuration

Requirements for Reading Array Data

The BYTE# pin controls whether the device data I/O

pins operate in the byte or word configuration. If the

BYTE# pin is set at logic “1,” the device is in word con-

figuration, DQ0–DQ15 are active and controlled by

CE# and OE#.

To read array data from the outputs, the system must

drive the CE# and OE# pins to V_IL. CE# is the power

control and selects the device. OE# is the output con-

trol and gates array data to the output pins. WE#

should remain at V_IH. The BYTE# pin determines

whether the device outputs array data in words or

bytes.

If the BYTE# pin is set at logic “0,” the device is in byte

configuration, and only data I/O pins DQ0–DQ7 are

active and controlled by CE# and OE#. The data I/O

pins DQ8–DQ14 are tri-stated, and the DQ15 pin is

used as an input for the LSB (A-1) address function.

The internal state machine is set for reading array data

upon device power-up, or after a hardware reset. This

ensures that no spurious alteration of the memory

content occurs during the power transition. No com-

mand is necessary in this mode to obtain array data.

Standard microprocessor read cycles that assert valid

8

Am29DL640D

December 13, 2005

addresses on the device address inputs produce valid

data on the device data outputs. Each bank remains

enabled for read access until the command register

contents are altered.

would use a two-cycle program command sequence

as required by the Unlock Bypass mode. Removing

V_HHfrom the WP#/ACC pin returns the device to nor-

mal operation. Note that V_HHmust not be asserted on

WP#/ACC for operations other than accelerated pro-

gramming, or device damage may result. In addition,

the WP#/ACC pin must not be left floating or uncon-

nected; inconsistent behavior of the device may result.

See “Write Protect (WP#)” on page 16 for related

information.

Refer to the AC Read-Only Operations table for timing

specifications and to Figure 14 for the timing diagram.

I_CC1in the DC Characteristics table represents the ac-

tive current specification for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which in-

cludes programming data to the device and erasing

sectors of memory), the system must drive WE# and

CE# to V_IL, and OE# to V_IH.

Autoselect Functions

If the system writes the autoselect command se-

quence, the device enters the autoselect mode. The

system can then read autoselect codes from the inter-

nal register (which is separate from the memory array)

on DQ15–DQ0. Standard read cycle timings apply in

this mode. Refer to the Autoselect Mode and Autose-

lect Command Sequence sections for more

information.

For program operations, the BYTE# pin determines

whether the device accepts program data in bytes or

words. Refer to Word/Byte Configuration for more

information.

The device features an Unlock Bypass mode to facili-

tate faster programming. Once a bank enters the

Unlock Bypass mode, only two write cycles are re-

quired to program a word or byte, instead of four. The

Byte/Word Program Command Sequence section has

details on programming data to the device using both

standard and Unlock Bypass command sequences.

Simultaneous Read/Write Operations with

Zero Latency

This device is capable of reading data from one bank

of memory while programming or erasing in the other

bank of memory. An erase operation may also be sus-

pended to read from or program to another location

within the same bank (except the sector being

erased). Figure 21 shows how read and write cycles

may be initiated for simultaneous operation with zero

latency. ICC6 and ICC7 in the DC Characteristics table

represent the current specifications for read-while-pro-

gram and read-while-erase, respectively.

An erase operation can erase one sector, multiple sec-

tors, or the entire device. Table 2 indicates the address

space that each sector occupies. The device address

space is divided into four banks: Banks 1 and 4 con-

tains the boot/parameter sectors, and Banks 2 and 3

contains the larger, code sectors of uniform size. A

“bank address” is the address bits required to uniquely

select a bank. Similarly, a “sector address” is the ad-

dress bits required to uniquely select a sector. The

Command Definitions section has details on erasing a

sector or the entire chip, or suspending/resuming the

erase operation.

Standby Mode

When the system is not reading or writing to the de-

vice, it can place the device in the standby mode. In

this mode, current consumption is greatly reduced,

and the outputs are placed in the high impedance

state, independent of the OE# input.

I_CC2in the DC Characteristics table represents the ac-

tive current specification for the write mode. The AC

Characteristics section contains timing specification

tables and timing diagrams for write operations.

The device enters the CMOS standby mode when the

CE# and RESET# pins are both held at V_CC0.3 V.

(Note that this is a more restricted voltage range than

V_IH.) If CE# and RESET# are held at V_IH, but not within

V_CC0.3 V, the device is in the standby mode, but the

standby current is greater. The device requires stan-

dard access time (t_CE) for read access when the

device is in either of these standby modes, before it is

ready to read data.

Accelerated Program Operation

The device offers accelerated program operations

through the ACC function. This is one of two functions

provided by the WP#/ACC pin. This function is prima-

rily intended to allow faster manufacturing throughput

at the factory.

If the device is deselected during erasure or program-

ming, the device draws active current until the

operation is completed.

If the system asserts V_HHon this pin, the device auto-

matically enters the aforementioned Unlock Bypass

mode, temporarily unprotects any protected sectors,

and uses the higher voltage on the pin to reduce the

time required for program operations. The system

ICC3 in the DC Characteristics table represents the

standby current specification.

December 13, 2005

Am29DL640D

9

draws CMOS standby current (ICC4). If RESET# is

held at V_ILbut not within V_SS0.3 V, the standby cur-

rent is greater.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device en-

ergy consumption. The device automatically enables

this mode when addresses remain stable for t_ACC

+

The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash

memory, enabling the system to read the boot-up firm-

ware from the Flash memory.

30 ns. The automatic sleep mode is independent of

the CE#, WE#, and OE# control signals. Standard ad-

dress access timings provide new data when

addresses are changed. While in sleep mode, output

data is latched and always available to the system.

ICC5 in the DC Characteristics table represents the

automatic sleep mode current specification.

If RESET# is asserted during a program or erase op-

eration, the RY/BY# pin remains a “0” (busy) until the

internal reset operation is complete, which requires a

time of t_READY(during Embedded Algorithms). The sys-

tem can thus monitor RY/BY# to determine whether

the reset operation is complete. If RESET# is asserted

when a program or erase operation is not executing

(RY/BY# pin is “1”), the reset operation is completed

within a time of t_READY(not during Embedded Algo-

rithms). The system can read data t_RHafter the

RESET# pin returns to V_IH.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of re-

setting the device to reading array data. When the

RESET# pin is driven low for at least a period of t_RP,

the device immediately terminates any operation in

progress, tristates all output pins, and ignores all

read/write commands for the duration of the RESET#

pulse. The device also resets the internal state ma-

chine to reading array data. The operation that was

interrupted should be reinitiated once the device is

ready to accept another command sequence, to en-

sure data integrity.

Refer to the AC Characteristics tables for RESET# pa-

rameters and to Figure 15 for the timing diagram.

Output Disable Mode

When the OE# input is at V_IH, output from the device is

disabled. The output pins are placed in the high

impedance state.

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at V_SS0.3 V, the device

Table 2. Am29DL640D Sector Architecture

Sector Address

Sector Size

(Kbytes/Kwords)

(x8)

Address Range

(x16)

Address Range

Bank

Sector

A21–A12

SA0

SA1

0000000000

0000000001

0000000010

0000000011

0000000100

0000000101

0000000110

0000000111

0000001xxx

0000010xxx

0000011xxx

0000100xxx

0000101xxx

0000110xxx

0000111xxx

0001000xxx

0001001xxx

0001010xxx

0001011xxx

0001100xxx

0001101xxx

0001110xxx

0001111xxx

8/4

000000h–001FFFh

002000h–003FFFh

004000h–005FFFh

006000h–007FFFh

008000h–009FFFh

00A000h–00BFFFh

00C000h–00DFFFh

00E000h–00FFFFFh

010000h–01FFFFh

020000h–02FFFFh

030000h–03FFFFh

040000h–04FFFFh

050000h–05FFFFh

060000h–06FFFFh

070000h–07FFFFh

080000h–08FFFFh

090000h–09FFFFh

0A0000h–0AFFFFh

0B0000h–0BFFFFh

0C0000h–0CFFFFh

0D0000h–0DFFFFh

0E0000h–0EFFFFh

0F0000h–0FFFFFh

00000h–00FFFh

01000h–01FFFh

02000h–02FFFh

03000h–03FFFh

04000h–04FFFh

05000h–05FFFh

06000h–06FFFh

07000h–07FFFh

08000h–0FFFFh

10000h–17FFFh

18000h–1FFFFh

20000h–27FFFh

28000h–2FFFFh

30000h–37FFFh

38000h–3FFFFh

40000h–47FFFh

48000h–4FFFFh

50000h–57FFFh

58000h–5FFFFh

60000h–67FFFh

68000h–6FFFFh

70000h–77FFFh

78000h–7FFFFh

SA2

8/4

SA3

8/4

SA4

8/4

SA5

8/4

SA6

8/4

SA7

8/4

SA8

64/32

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

Bank 1

10

Am29DL640D

December 13, 2005

Table 2. Am29DL640D Sector Architecture (Continued)

Sector Address

A21–A12

Sector Size

(Kbytes/Kwords)

(x8)

(x16)

Address Range

Bank

Sector

Address Range

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

0010000xxx

0010001xxx

0010010xxx

0010011xxx

0010100xxx

0010101xxx

0010110xxx

0010111xxx

0011000xxx

0011001xxx

0011010xxx

0011011xxx

0011100xxx

0011101xxx

0011110xxx

0011111xxx

0100000xxx

0100001xxx

0100010xxx

0101011xxx

0100100xxx

0100101xxx

0100110xxx

0100111xxx

0101000xxx

0101001xxx

0101010xxx

0101011xxx

0101100xxx

0101101xxx

0101110xxx

0101111xxx

0110000xxx

0110001xxx

0110010xxx

0110011xxx

0100100xxx

0110101xxx

0110110xxx

0110111xxx

0111000xxx

0111001xxx

0111010xxx

0111011xxx

0111100xxx

0111101xxx

0111110xxx

0111111xxx

64/32

100000h–00FFFFh

110000h–11FFFFh

120000h–12FFFFh

130000h–13FFFFh

140000h–14FFFFh

150000h–15FFFFh

160000h–16FFFFh

170000h–17FFFFh

180000h–18FFFFh

190000h–19FFFFh

1A0000h–1AFFFFh

1B0000h–1BFFFFh

1C0000h–1CFFFFh

1D0000h–1DFFFFh

1E0000h–1EFFFFh

1F0000h–1FFFFFh

200000h–20FFFFh

210000h–21FFFFh

220000h–22FFFFh

230000h–23FFFFh

240000h–24FFFFh

250000h–25FFFFh

260000h–26FFFFh

270000h–27FFFFh

280000h–28FFFFh

290000h–29FFFFh

2A0000h–2AFFFFh

2B0000h–2BFFFFh

2C0000h–2CFFFFh

2D0000h–2DFFFFh

2E0000h–2EFFFFh

2F0000h–2FFFFFh

300000h–30FFFFh

310000h–31FFFFh

320000h–32FFFFh

330000h–33FFFFh

340000h–34FFFFh

350000h–35FFFFh

360000h–36FFFFh

370000h–37FFFFh

380000h–38FFFFh

390000h–39FFFFh

3A0000h–3AFFFFh

3B0000h–3BFFFFh

3C0000h–3CFFFFh

3D0000h–3DFFFFh

3E0000h–3EFFFFh

3F0000h–3FFFFFh

80000h–87FFFh

88000h–8FFFFh

90000h–97FFFh

98000h–9FFFFh

A0000h–A7FFFh

A8000h–AFFFFh

B0000h–B7FFFh

B8000h–BFFFFh

C0000h–C7FFFh

C8000h–CFFFFh

D0000h–D7FFFh

D8000h–DFFFFh

E0000h–E7FFFh

E8000h–EFFFFh

F0000h–F7FFFh

F8000h–FFFFFh

F9000h–107FFFh

108000h–10FFFFh

110000h–117FFFh

118000h–11FFFFh

120000h–127FFFh

128000h–12FFFFh

130000h–137FFFh

138000h–13FFFFh

140000h–147FFFh

148000h–14FFFFh

150000h–157FFFh

158000h–15FFFFh

160000h–167FFFh

168000h–16FFFFh

170000h–177FFFh

178000h–17FFFFh

180000h–187FFFh

188000h–18FFFFh

190000h–197FFFh

198000h–19FFFFh

1A0000h–1A7FFFh

1A8000h–1AFFFFh

1B0000h–1B7FFFh

1B8000h–1BFFFFh

1C0000h–1C7FFFh

1C8000h–1CFFFFh

1D0000h–1D7FFFh

1D8000h–1DFFFFh

1E0000h–1E7FFFh

1E8000h–1EFFFFh

1F0000h–1F7FFFh

1F8000h–1FFFFFh

Bank 2

December 13, 2005

Am29DL640D

11

Table 2. Am29DL640D Sector Architecture (Continued)

Sector Address

A21–A12

Sector Size

(Kbytes/Kwords)

(x8)

(x16)

Address Range

Bank

Sector

Address Range

SA71

SA72

SA73

SA74

SA75

SA76

SA77

SA78

SA79

SA80

SA81

SA82

SA83

SA84

SA85

SA86

SA87

SA88

SA89

SA90

SA91

SA92

SA93

SA94

SA95

SA96

SA97

SA98

SA99

SA100

SA101

SA102

SA103

SA104

SA105

SA106

SA107

SA108

SA109

SA110

SA111

SA112

SA113

SA114

SA115

SA116

SA117

SA118

1000000xxx

1000001xxx

1000010xxx

1000011xxx

1000100xxx

1000101xxx

1000110xxx

1000111xxx

1001000xxx

1001001xxx

1001010xxx

1001011xxx

1001100xxx

1001101xxx

1001110xxx

1001111xxx

1010000xxx

1010001xxx

1010010xxx

1010011xxx

1010100xxx

1010101xxx

1010110xxx

1010111xxx

1011000xxx

1011001xxx

1011010xxx

1011011xxx

1011100xxx

1011101xxx

1011110xxx

1011111xxx

1100000xxx

1100001xxx

1100010xxx

1100011xxx

1100100xxx

1100101xxx

1100110xxx

1100111xxx

1101000xxx

1101001xxx

1101010xxx

1101011xxx

1101100xxx

1101101xxx

1101110xxx

1101111xxx

64/32

400000h–40FFFFh

410000h–41FFFFh

420000h–42FFFFh

430000h–43FFFFh

440000h–44FFFFh

450000h–45FFFFh

460000h–46FFFFh

470000h–47FFFFh

480000h–48FFFFh

490000h–49FFFFh

4A0000h–4AFFFFh

4B0000h–4BFFFFh

4C0000h–4CFFFFh

4D0000h–4DFFFFh

4E0000h–4EFFFFh

4F0000h–4FFFFFh

500000h–50FFFFh

510000h–51FFFFh

520000h–52FFFFh

530000h–53FFFFh

540000h–54FFFFh

550000h–55FFFFh

560000h–56FFFFh

570000h–57FFFFh

580000h–58FFFFh

590000h–59FFFFh

5A0000h–5AFFFFh

5B0000h–5BFFFFh

5C0000h–5CFFFFh

5D0000h–5DFFFFh

5E0000h–5EFFFFh

5F0000h–5FFFFFh

600000h–60FFFFh

610000h–61FFFFh

620000h–62FFFFh

630000h–63FFFFh

640000h–64FFFFh

650000h–65FFFFh

660000h–66FFFFh

670000h–67FFFFh

680000h–68FFFFh

690000h–69FFFFh

6A0000h–6AFFFFh

6B0000h–6BFFFFh

6C0000h–6CFFFFh

6D0000h–6DFFFFh

6E0000h–6EFFFFh

6F0000h–6FFFFFh

200000h–207FFFh

208000h–20FFFFh

210000h–217FFFh

218000h–21FFFFh

220000h–227FFFh

228000h–22FFFFh

230000h–237FFFh

238000h–23FFFFh

240000h–247FFFh

248000h–24FFFFh

250000h–257FFFh

258000h–25FFFFh

260000h–267FFFh

268000h–26FFFFh

270000h–277FFFh

278000h–27FFFFh

280000h–28FFFFh

288000h–28FFFFh

290000h–297FFFh

298000h–29FFFFh

2A0000h–2A7FFFh

2A8000h–2AFFFFh

2B0000h–2B7FFFh

2B8000h–2BFFFFh

2C0000h–2C7FFFh

2C8000h–2CFFFFh

2D0000h–2D7FFFh

2D8000h–2DFFFFh

2E0000h–2E7FFFh

2E8000h–2EFFFFh

2F0000h–2FFFFFh

2F8000h–2FFFFFh

300000h–307FFFh

308000h–30FFFFh

310000h–317FFFh

318000h–31FFFFh

320000h–327FFFh

328000h–32FFFFh

330000h–337FFFh

338000h–33FFFFh

340000h–347FFFh

348000h–34FFFFh

350000h–357FFFh

358000h–35FFFFh

360000h–367FFFh

368000h–36FFFFh

370000h–377FFFh

378000h–37FFFFh

Bank 3

12

Am29DL640D

December 13, 2005

Table 2. Am29DL640D Sector Architecture (Continued)

Sector Address

A21–A12

Sector Size

(Kbytes/Kwords)

(x8)

(x16)

Address Range

Bank

Sector

Address Range

SA119

SA120

SA121

SA122

SA123

SA124

SA125

SA126

SA127

SA128

SA129

SA130

SA131

SA132

SA133

SA134

SA135

SA136

SA137

SA138

SA139

SA140

SA141

1110000xxx

1110001xxx

1110010xxx

1110011xxx

1110100xxx

1110101xxx

1110110xxx

1110111xxx

1111000xxx

1111001xxx

1111010xxx

1111011xxx

1111100xxx

1111101xxx

1111110xxx

1111111000

1111111001

1111111010

1111111011

1111111100

1111111101

1111111110

1111111111

64/32

8/4

700000h–70FFFFh

710000h–71FFFFh

720000h–72FFFFh

730000h–73FFFFh

740000h–74FFFFh

750000h–75FFFFh

760000h–76FFFFh

770000h–77FFFFh

780000h–78FFFFh

790000h–79FFFFh

7A0000h–7AFFFFh

7B0000h–7BFFFFh

7C0000h–7CFFFFh

7D0000h–7DFFFFh

7E0000h–7EFFFFh

7F0000h–7F1FFFh

7F2000h–7F3FFFh

7F4000h–7F5FFFh

7F6000h–7F7FFFh

7F8000h–7F9FFFh

7FA000h–7FBFFFh

7FC000h–7FDFFFh

7FE000h–7FFFFFh

380000h–387FFFh

388000h–38FFFFh

390000h–397FFFh

398000h–39FFFFh

3A0000h–3A7FFFh

3A8000h–3AFFFFh

3B0000h–3B7FFFh

3B8000h–3BFFFFh

3C0000h–3C7FFFh

3C8000h–3CFFFFh

3D0000h–3D7FFFh

3D8000h–3DFFFFh

3E0000h–3E7FFFh

3E8000h–3EFFFFh

3F0000h–3F7FFFh

3F8000h–3F8FFFh

3F9000h–3F9FFFh

3FA000h–3FAFFFh

3FB000h–3FBFFFh

3FC000h–3FCFFFh

3FD000h–3FDFFFh

3FE000h–3FEFFFh

3FF000h–3FFFFFh

Bank 4

8/4

Note: The address range is A21:A-1 in byte mode (BYTE#=V_IL) or A21:A0 in word mode (BYTE#=V_IH).

Table 3. Bank Address

Bank

A21–A19

000

1

2

3

4

001, 010, 011

100, 101, 110

111

Table 4. Secured Silicon Sector Addresses

(x8)

(x16)

Device

Am29DL640D

Sector Size

Address Range

256 bytes

000000h–0000FFh

00000h–0007Fh

shows the remaining address bits that are don’t care.

When all necessary bits have been set as required,

the programming equipment may then read the corre-

sponding identifier code on DQ7–DQ0. However, the

autoselect codes can also be accessed in-system

through the command register, for instances when the

Am29DL640 is erased or programmed in a system

without access to high voltage on the A9 pin. The com-

mand sequence is illustrated in Table 12. Note that if a

Bank Address (BA) on address bits A21, A20, and A19

is asserted during the third write cycle of the autose-

lect command, the host system can read autoselect

data that bank and then immediately read array data

from the other bank, without exiting the autoselect

mode.

Autoselect Mode

The autoselect mode provides manufacturer and de-

vice identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This

mode is primarily intended for programming equip-

ment to automatically match a device to be

programmed with its corresponding programming al-

gorithm. However, the autoselect codes can also be

accessed in-system through the command register.

When using programming equipment, the autoselect

mode requires V_ID(8.5 V to 12.5 V) on address pin A9.

Address pins A6, A1, and A0 must be as shown in

Table 5. In addition, when verifying sector protection,

the sector address must appear on the appropriate

highest order address bits (see Table 2). Table 5

December 13, 2005

Am29DL640D

13

To access the autoselect codes in-system, the host

system can issue the autoselect command via the

command register, as shown in Table 12. This method

does not require V_ID. Refer to the Autoselect Com-

mand Sequence section for more information.

Table 5. Am29DL640D Autoselect Codes, (High Voltage Method)

DQ8 to DQ15

A21 A11

to to

A8

to

A5

to

DQ7

to

BYTE# BYTE#

Description

CE# OE# WE# A12 A10 A9 A7 A6 A4 A3 A2 A1 A0

= V_IH

= V_IL

DQ0

Manufacturer ID:

AMD

V_ID

L

H

BA

X

L

X

L

X

01h

Read Cycle 1

Read Cycle 2

Read Cycle 3

L

H

L

H

L

H

L

22h

7Eh

02h

01h

V_ID

L

H

X

H

Sector Protection

Verification

01h (protected),

00h (unprotected)

V_ID

L

H

SA

BA

X

L

X

H

L

X

80h (factory locked),

00h (not factory

locked)

Secured Silicon

Indicator Bit (DQ7)

L

H

Legend: L = Logic Low = V_IL, H = Logic High = V_IH, BA = Bank Address, SA = Sector Address, X = Don’t care

.

14

Am29DL640D

December 13, 2005

Sector/Sector Block Protection and

Unprotection

(Note: For the following discussion, the term “sector”

applies to both sectors and sector blocks. A sector

block consists of two or more adjacent sectors that are

protected or unprotected at the same time (see

Table 6).

Sector/

Sector Block Size

Sector

A21–A12

SA63–SA66

SA67–SA70

SA71–SA74

SA75–SA78

SA79–SA82

SA83–SA86

SA87–SA90

SA91–SA94

SA95–SA98

SA99–SA102

SA103–SA106

SA107–SA110

SA111–SA114

SA115–SA118

SA119–SA122

SA123–SA126

SA127–SA130

01110XXXXX

01111XXXXX

10000XXXXX

10001XXXXX

10010XXXXX

10011XXXXX

10100XXXXX

10101XXXXX

10110XXXXX

10111XXXXX

11000XXXXX

11001XXXXX

11010XXXXX

11011XXXXX

11100XXXXX

11101XXXXX

11110XXXXX

256 (4x64) Kbytes

The hardware sector protection feature disables both

program and erase operations in any sector. The hard-

ware sector unprotection feature re-enables both

program and erase operations in previously protected

sectors. Sector protection/unprotection can be imple-

mented via two methods.

Table 6. Am29DL640D Boot Sector/Sector Block

Addresses for Protection/Unprotection

Sector/

Sector

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

A21–A12

Sector Block Size

0000000000

0000000001

0000000010

0000000011

0000000100

0000000101

0000000110

0000000111

8 Kbytes

1111100XXX,

1111101XXX,

1111110XXX

8 Kbytes

SA131–SA133

192 (3x64) Kbytes

8 Kbytes

SA134

SA135

SA136

SA137

SA138

SA139

SA140

SA141

1111111000

1111111001

1111111010

1111111011

1111111100

1111111101

1111111111

8 Kbytes

0000001XXX,

0000010XXX,

0000011XXX,

SA8–SA10

192 (3x64) Kbytes

SA11–SA14

SA15–SA18

SA19–SA22

SA23–SA26

SA27-SA30

SA31-SA34

SA35-SA38

SA39-SA42

SA43-SA46

SA47-SA50

SA51-SA54

SA55–SA58

SA59–SA62

00001XXXXX

00010XXXXX

00011XXXXX

00100XXXXX

00101XXXXX

00110XXXXX

00111XXXXX

01000XXXXX

01001XXXXX

01010XXXXX

01011XXXXX

01100XXXXX

01101XXXXX

256 (4x64) Kbytes

Sector Protection/Unprotection requires V_IDon the

RESET# pin only, and can be implemented either

in-system or via programming equipment. Figure 2

shows the algorithms and Figure 26 shows the timing

diagram. For sector unprotect, all unprotected sectors

must first be protected prior to the first sector unpro-

tect write cycle. Note that the sector unprotect

algorithm unprotects all sectors in parallel. All previ-

ously protected sectors must be individually

re-protected. To change data in protected sectors effi-

ciently, the temporary sector unprotect function is

available. See “Temporary Sector Unprotect”.

December 13, 2005

Am29DL640D

15

The alternate method intended only for programming

equipment requires V_IDon address pin A9 and OE#.

This method is compatible with programmer routines

written for earlier 3.0 volt-only AMD flash devices.

Temporary Sector Unprotect

(Note: For the following discussion, the term “sector”

applies to both sectors and sector blocks. A sector

block consists of two or more adjacent sectors that are

protected or unprotected at the same time (see

Table 6).

The device is shipped with all sectors unprotected.

AMD offers the option of programming and protecting

sectors at its factory prior to shipping the device

through AMD’s ExpressFlash™ Service. Contact an

AMD representative for details.

This feature allows temporary unprotection of previ-

ously protected sectors to change data in-system. The

Sector Unprotect mode is activated by setting the RE-

SET# pin to V_ID(8.5 V – 12.5 V). During this mode,

formerly protected sectors can be programmed or

erased by selecting the sector addresses. Once V_IDis

removed from the RESET# pin, all the previously pro-

tected sectors are protected again. Figure 1 shows the

algorithm, and Figure 25 shows the timing diagrams,

for this feature. If the WP#/ACC pin is at V_IL, sectors 0,

1, 140, and 141 remains protected during the Tempo-

rary sector Unprotect mode.

It is possible to determine whether a sector is pro-

tected or unprotected. See the Autoselect Mode

section for details.

Write Protect (WP#)

The Write Protect function provides a hardware

method of protecting without using V_ID. This function is

one of two provided by the WP#/ACC pin.

If the system asserts V_ILon the WP#/ACC pin, the de-

vice disables program and erase functions in sectors

0, 1, 140, and 141, independently of whether those

sectors were protected or unprotected using the

method described in Sector/Sector Block Protection

and Unprotection.

START

If the system asserts V_IHon the WP#/ACC pin, the de-

vice reverts to whether sectors 0, 1, 140, and 141

were last set to be protected or unprotected. That is,

sector protection or unprotection for these sectors de-

pends on whether they were last protected or

unprotected using the method described in Sec-

tor/Sector Block Protection and Unprotection.

RESET# = V_ID

(Note 1)

Perform Erase or

Program Operations

Note that the WP#/ACC pin must not be left floating or

unconnected; inconsistent behavior of the device may

result.

RESET# = V_IH

Table 7. WP#/ACC Modes

Temporary Sector

Unprotect Completed

(Note 2)

Device

Mode

WP# Input

Voltage

Disables programming and erasing in

SA0, SA1, SA140, and SA141

V_IL

V_IH

Enables programming and erasing in

SA0, SA1, SA140, and SA141

Notes:

1. All protected sectors unprotected (If WP#/ACC = V_IL,

sectors 0, 1, 140, and 141 remain protected).

Enables accelerated programming

(ACC). See “Accelerated Program

Operation” on page 9.

V_HH

2. All previously protected sectors are protected once

again.

Figure 1. Temporary Sector Unprotect Operation

16

Am29DL640D

December 13, 2005

START

Protect all sectors:

The indicated portion

of the sector protect

algorithm must be

performed for all

PLSCNT = 1

RESET# = V_ID

unprotected sectors

prior to issuing the

first sector

Wait 1 μs

unprotect address

No

First Write

Cycle = 60h?

No

First Write

Cycle = 60h?

Temporary Sector

Unprotect Mode

Temporary Sector

Unprotect Mode

Yes

Set up sector

address

No

All sectors

protected?

Sector Protect:

Write 60h to sector

address with

A6 = 0, A1 = 1,

A0 = 0

Yes

Set up first sector

address

Sector Unprotect:

Write 60h to any

address with

A6 = 1, A1 = 1,

A0 = 0

Wait 150 µs

Verify Sector

Protect: Write 40h

to sector address

with A6 = 0,

Reset

PLSCNT = 1

Increment

PLSCNT

Wait 15 ms

A1 = 1, A0 = 0

Verify Sector

Unprotect: Write

40h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector address

with A6 = 0,

A1 = 1, A0 = 0

Increment

PLSCNT

No

PLSCNT

= 25?

Read from

sector address

with A6 = 1,

Data = 01h?

Yes

A1 = 1, A0 = 0

No

Yes

Set up

next sector

address

Yes

No

PLSCNT

= 1000?

Protect another

sector?

Data = 00h?

Yes

Device failed

No

Yes

Remove V_ID

from RESET#

No

Last sector

verified?

Device failed

Write reset

command

Yes

Remove V_ID

Sector Unprotect

Algorithm

from RESET#

Sector Protect

Algorithm

Sector Protect

complete

Write reset

command

Sector Unprotect

complete

Figure 2. In-System Sector Protect/Unprotect Algorithms

Am29DL640D

December 13, 2005

17

mode (or 000000h–00000Fh in byte mode). The se-

cure ESN is programmed in the next 8 words at

addresses 000008h–00000Fh (or 000010h–000020h

in byte mode). The device is available preprogrammed

with one of the following:

Secured Silicon Sector

Flash Memory Region

The Secured Silicon Sector feature provides a Flash

memory region that enables permanent part identifica-

tion through an Electronic Serial Number (ESN). The

Secured Silicon Sector is 256 bytes in length, and

uses a Secured Silicon Sector Indicator Bit (DQ7) to

indicate whether or not the Secured Silicon Sector is

locked when shipped from the factory. This bit is per-

manently set at the factory and cannot be changed,

which prevents cloning of a factory locked part. This

ensures the security of the ESN once the product is

shipped to the field.

A random, secure ESN only

Customer code through the ExpressFlash service

Both a random, secure ESN and customer code

through the ExpressFlash service.

Customers may opt to have their code programmed by

AMD through the AMD ExpressFlash service. AMD

programs the customer’s code, with or without the ran-

dom ESN. The devices are then shipped from AMD’s

factory with the Secured Silicon Sector permanently

locked. Contact an AMD representative for details on

using AMD’s ExpressFlash service.

AMD offers the device with the Secured Silicon Sector

either factory locked or customer lockable. The fac-

tory-locked version is always protected when shipped

from the factory, and has the Secured Silicon Sector

Indicator Bit permanently set to a “1.” The cus-

tomer-lockable version is shipped with the Secured

Silicon Sector unprotected, allowing customers to uti-

lize the that sector in any manner they choose. The

customer-lockable version has the Secured Silicon

Sector Indicator Bit permanently set to a “0.” Thus, the

Secured Silicon Sector Indicator Bit prevents cus-

tomer-lockable devices from being used to replace

devices that are factory locked. Note that the ACC

function and unlock bypass modes are not available

when the Secured Silicon Sector is enabled.

Customer Lockable: Secured Silicon Sector NOT

Programmed or Protected At the Factory

If the security feature is not required, the Secured Sili-

con Sector can be treated as an additional Flash

memory space. The Secured Silicon Sector can be

read any number of times, but can be programmed

and locked only once. Note that the accelerated pro-

gramming (ACC) and unlock bypass functions are not

available when programming the Secured Silicon

Sector.

The Secured Silicon Sector area can be protected

using one of the following procedures:

The system accesses the Secured Silicon Sector Se-

cure through a command sequence (see Enter/Exit

Secured Silicon Sector Command Sequence). After

the system has written the Enter Secured Silicon Sec-

tor command sequence, it may read the Secured

Silicon Sector by using the addresses normally occu-

pied by the boot sectors. This mode of operation

continues until the system issues the Exit Secured Sil-

icon Sector command sequence, or until power is

removed from the device. On power-up, or following a

hardware reset, the device reverts to sending com-

mands to the first 256 bytes of Sector 0. Note that the

ACC function and unlock bypass modes are not avail-

able when the Secured Silicon Sector is enabled.

Write the three-cycle Enter Secured Silicon Sector

Region command sequence, and then follow the

in-system sector protect algorithm as shown in

Figure 2, except that RESET# may be at either V_IH

or V_ID. This allows in-system protection of the Se-

cured Silicon Sector Region without raising any de-

vice pin to a high voltage. Note that this method is

only applicable to the Secured Silicon Sector.

To verify the protect/unprotect status of the Secured

Silicon Sector, follow the algorithm shown in

Figure 3.

Once the Secured Silicon Sector is locked and veri-

fied, the system must write the Exit Secured Silicon

Sector Region command sequence to return to read-

ing and writing the remainder of the array.

Factory Locked: Secured Silicon Sector

Programmed and Protected At the Factory

In a factory locked device, the Secured Silicon Sector

is protected when the device is shipped from the fac-

tory. The Secured Silicon Sector cannot be modified in

any way. The device is preprogrammed with both a ran-

dom number and a secure ESN. The 8-word random

number will at addresses 000000h–000007h in word

The Secured Silicon Sector lock must be used with

caution since, once locked, there is no procedure

available for unlocking the Secured Silicon Sector area

and none of the bits in the Secured Silicon Sector

memory space can be modified in any way.

18

Am29DL640D

December 13, 2005

Logical Inhibit

Write cycles are inhibited by holding any one of OE# =

V_IL, CE# = V_IHor WE# = V_IH. To initiate a write cycle,

CE# and WE# must be a logical zero while OE# is a

logical one.

START

If data = 00h,

SecSi Sector is

unprotected.

If data = 01h,

SecSi Sector is

protected.

RESET# =

V_IHor V_ID

Power-Up Write Inhibit

If WE# = CE# = V_ILand OE# = V_IHduring power up,

the device does not accept commands on the rising

edge of WE#. The internal state machine is automati-

cally reset to the read mode on power-up.

Wait 1 ms

Write 60h to

any address

Remove V_IHor V_ID

from RESET#

COMMON FLASH MEMORY INTERFACE

(CFI)

Write 40h to SecSi

Sector address

with A6 = 0,

Write reset

command

The Common Flash Interface (CFI) specification out-

lines device and host system software interrogation

handshake, which allows specific vendor-specified

software algorithms to be used for entire families of

devices. Software support can then be device-inde-

pendent, JEDEC ID-independent, and forward- and

backward-compatible for the specified flash device

families. Flash vendors can standardize their existing

interfaces for long-term compatibility.

A1 = 1, A0 = 0

SecSi Sector

Protect Verify

complete

Read from SecSi

Sector address

with A6 = 0,

A1 = 1, A0 = 0

This device enters the CFI Query mode when the sys-

tem writes the CFI Query command, 98h, to address

55h in word mode (or address AAh in byte mode), any

time the device is ready to read array data. The

system can read CFI information at the addresses

given in Tables 8–11. To terminate reading CFI data,

the system must write the reset command. The CFI

Query mode is not accessible when the device is exe-

cuting an Embedded Program or embedded Erase

algorithm.

Figure 3. Secured Silicon Sector Protect Verify

Hardware Data Protection

The command sequence requirement of unlock cycles

for programming or erasing provides data protection

against inadvertent writes (refer to Table 12 for com-

mand definitions). In addition, the following hardware

data protection measures prevent accidental erasure

or programming, which might otherwise be caused by

spurious system level signals during V_CCpower-up

and power-down transitions, or from system noise.

The system can also write the CFI query command

when the device is in the autoselect mode. The device

enters the CFI query mode, and the system can read

CFI data at the addresses given in Tables 8–11. The

system must write the reset command to return the

device to reading array data.

Low V_CCWrite Inhibit

When V_CCis less than V_LKO, the device does not ac-

cept any write cycles. This protects data during V_CC

power-up and power-down. The command register

and all internal program/erase circuits are disabled,

and the device resets to the read mode. Subsequent

writes are ignored until V_CCis greater than V_LKO. The

system must provide the proper signals to the control

pins to prevent unintentional writes when V_CCis

For further information, please refer to the CFI Specifi-

cation and CFI Publication 100, available via the World

Wide Web at http://www.amd.com/flash/cfi. Alterna-

tively, contact an AMD representative for copies of

these documents.

greater than V_LKO

.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE#

or WE# do not initiate a write cycle.

December 13, 2005

Am29DL640D

19

Table 8. CFI Query Identification String

Addresses

(Word Mode)

(Byte Mode)

Data

Description

10h

11h

12h

20h

22h

24h

0051h

0052h

0059h

Query Unique ASCII string “QRY”

13h

14h

26h

28h

0002h

0000h

Primary OEM Command Set

15h

16h

2Ah

2Ch

0040h

0000h

Address for Primary Extended Table

17h

18h

2Eh

30h

0000h

Alternate OEM Command Set (00h = none exists)

Address for Alternate OEM Extended Table (00h = none exists)

19h

1Ah

32h

34h

0000h

Table 9. System Interface String

Addresses

(Word Mode)

(Byte Mode)

Data Description

V_CCMin. (write/erase)

0027h

1Bh

1Ch

36h

38h

D7–D4: volt, D3–D0: 100 millivolt

V_CCMax. (write/erase)

0036h

D7–D4: volt, D3–D0: 100 millivolt

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

3Ah

3Ch

3Eh

40h

42h

44h

46h

48h

4Ah

4Ch

0000h

0004h

0000h

000Ah

0000h

0005h

0000h

0004h

0000h

V_PPMin. voltage (00h = no V_PPpin present)

V_PPMax. voltage (00h = no V_PPpin present)

Typical timeout per single byte/word write 2^Nµs

Typical timeout for Min. size buffer write 2^Nµs (00h = not supported)

Typical timeout per individual block erase 2^Nms

Typical timeout for full chip erase 2^Nms (00h = not supported)

Max. timeout for byte/word write 2^Ntimes typical

Max. timeout for buffer write 2^Ntimes typical

Max. timeout per individual block erase 2^Ntimes typical

Max. timeout for full chip erase 2^Ntimes typical (00h = not supported)

20

Am29DL640D

December 13, 2005

Table 10. Device Geometry Definition

Addresses

(Word Mode)

(Byte Mode)

Data

Description

27h

4Eh

0017h

Device Size = 2^Nbyte

28h

29h

50h

52h

0002h

0000h

Flash Device Interface description (refer to CFI publication 100)

2Ah

2Bh

54h

56h

0000h

Max. number of byte in multi-byte write = 2^N

(00h = not supported)

2Ch

58h

0003h

Number of Erase Block Regions within device

2Dh

2Eh

2Fh

30h

5Ah

5Ch

5Eh

60h

0007h

0000h

0020h

0000h

Erase Block Region 1 Information

(refer to the CFI specification or CFI publication 100)

31h

32h

33h

34h

62h

64h

66h

68h

007Dh

0000h

0001h

Erase Block Region 2 Information

(refer to the CFI specification or CFI publication 100)

35h

36h

37h

38h

6Ah

6Ch

6Eh

70h

0007h

0000h

0020h

0000h

Erase Block Region 3 Information

(refer to the CFI specification or CFI publication 100)

39h

3Ah

3Bh

3Ch

72h

74h

76h

78h

0000h

Erase Block Region 4 Information

(refer to the CFI specification or CFI publication 100)

December 13, 2005

Am29DL640D

21

Table 11. Primary Vendor-Specific Extended Query

Addresses

(Word Mode)

(Byte Mode)

Data

Description

40h

41h

42h

80h

82h

84h

0050h

0052h

0049h

Query-unique ASCII string “PRI”

43h

44h

86h

88h

0031h

0033h

Major version number, ASCII (reflects modifications to the silicon)

Minor version number, ASCII (reflects modifications to the CFI table)

Address Sensitive Unlock (Bits 1-0)

0 = Required, 1 = Not Required

45h

8Ah

0000h

Silicon Revision Number (Bits 7-2)

Erase Suspend

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

46h

47h

48h

8Ch

8Eh

90h

0002h

0001h

Sector Protect

0 = Not Supported, X = Number of sectors in per group

Sector Temporary Unprotect

00 = Not Supported, 01 = Supported

Sector Protect/Unprotect scheme

49h

92h

0004h

01 =29F040 mode, 02 = 29F016 mode, 03 = 29F400, 04 = 29LV800

mode

0077h

(See Note)

Simultaneous Operation

00 = Not Supported, X = Number of Sectors in Bank 2 (Uniform Bank)

4Ah

4Bh

4Ch

94h

96h

98h

Burst Mode Type

00 = Not Supported, 01 = Supported

0000h

Page Mode Type

00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

ACC (Acceleration) Supply Minimum

4Dh

4Eh

9Ah

9Ch

0085h

0095h

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

ACC (Acceleration) Supply Maximum

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

Top/Bottom Boot Sector Flag

00h = Uniform device, 01h = 8 x 8 Kbyte Sectors, Both Top and Bottom

Boot with Write Protect, 02h = Bottom Boot Device, 03h = Top Boot

Device, 04h = Both Top and Bottom

4Fh

9Eh

0001h

Program Suspend

50h

57h

58h

59h

5Ah

5Bh

A0h

AEh

B0h

B2h

B4h

B6h

0001h

0004h

*0017h

*0030h

0017h

0 = Not supported, 1 = Supported

Bank Organization

00 = Data at 4Ah is zero, X = Number of Banks

Bank 1 Region Information

X = Number of Sectors in Bank 1

Bank 2 Region Information

X = Number of Sectors in Bank 2

Bank 3 Region Information

X = Number of Sectors in Bank 3

Bank 4 Region Information

X = Number of Sectors in Bank 4

Note: The number of sectors in Bank 2 is device dependent.

22

Am29DL640D

December 13, 2005

COMMAND DEFINITIONS

Writing specific address and data commands or se-

quences into the command register initiates device

operations. Table 12 defines the valid register com-

mand sequences. Writing incorrect address and

data values or writing them in the improper se-

quence may place the device in an unknown state. A

reset command is then required to return the device to

reading array data.

The reset command may be written between the

sequence cycles in a program command sequence

before programming begins. This resets the bank to

which the system was writing to the read mode. If the

program command sequence is written to a bank that

is in the Erase Suspend mode, writing the reset

command returns that bank to the erase-sus-

pend-read mode. Once programming begins, however,

the device ignores reset commands until the operation

is complete.

All addresses are latched on the falling edge of WE#

or CE#, whichever happens later. All data is latched on

the rising edge of WE# or CE#, whichever happens

first. Refer to the AC Characteristics section for timing

diagrams.

The reset command may be written between the se-

quence cycles in an autoselect command sequence.

Once in the autoselect mode, the reset command

must be written to return to the read mode. If a bank

entered the autoselect mode while in the Erase Sus-

pend mode, writing the reset command returns that

bank to the erase-suspend-read mode.

Reading Array Data

The device is automatically set to reading array data

after device power-up. No commands are required to

retrieve data. Each bank is ready to read array data

after completing an Embedded Program or Embedded

Erase algorithm.

If DQ5 goes high during a program or erase operation,

writing the reset command returns the banks to the

read mode (or erase-suspend-read mode if that bank

was in Erase Suspend).

After the device accepts an Erase Suspend command,

the corresponding bank enters the erase-sus-

pend-read mode, after which the system can read

data from any non-erase-suspended sector within the

same bank. The system can read array data using the

standard read timing, except that if it reads at an ad-

dress within erase-suspended sectors, the device

outputs status data. After completing a programming

operation in the Erase Suspend mode, the system

may once again read array data with the same excep-

tion. See the Erase Suspend/Erase Resume

Commands section for more information.

Autoselect Command Sequence

The autoselect command sequence allows the host

system to access the manufacturer and device codes,

and determine whether or not a sector is protected.

The autoselect command sequence may be written to

an address within a bank that is either in the read or

erase-suspend-read mode. The autoselect command

may not be written while the device is actively pro-

gramming or erasing in the other bank.

The autoselect command sequence is initiated by first

writing two unlock cycles. This is followed by a third

write cycle that contains the bank address and the au-

toselect command. The bank then enters the

autoselect mode. The system may read any number of

autoselect codes without reinitiating the command

sequence.

The system must issue the reset command to return a

bank to the read (or erase-suspend-read) mode if DQ5

goes high during an active program or erase opera-

tion, or if the bank is in the autoselect mode. See the

next section, Reset Command, for more information.

See also Requirements for Reading Array Data in the

Device Bus Operations section for more information.

The Read-Only Operations table provides the read pa-

rameters, and Figure 14 shows the timing diagram.

Table 12 shows the address and data requirements.

To determine sector protection information, the system

must write to the appropriate bank address (BA) and

sector address (SA). Table 2 shows the address range

and bank number associated with each sector.

Reset Command

Writing the reset command resets the banks to the

read or erase-suspend-read mode. Address bits are

don’t cares for this command.

The system must write the reset command to return to

the read mode (or erase-suspend-read mode if the

bank was previously in Erase Suspend).

The reset command may be written between the se-

quence cycles in an erase command sequence before

erasing begins. This resets the bank to which the sys-

tem was writing to the read mode. Once erasure

begins, however, the device ignores reset commands

until the operation is complete.

Enter/Exit Secured Silicon Sector

Command Sequence

The Secured Silicon Sector region provides a secured

data area containing a random, sixteen-byte electronic

serial number (ESN). The system can access the Se-

cured Silicon Sector region by issuing the three-cycle

December 13, 2005

Am29DL640D

23

Enter Secured Silicon Sector command sequence.

The device continues to access the Secured Silicon

Sector region until the system issues the four-cycle

Exit Secured Silicon Sector command sequence. The

Exit Secured Silicon Sector command sequence re-

turns the device to normal operation. The Secured

Silicon Sector is not accessible when the device is ex-

ecuting an Embedded Program or embedded Erase

algorithm. Table 12 shows the address and data re-

quirements for both command sequences. See also

Secured Silicon Sector Flash Memory Region for fur-

ther information. Note that the ACC function and

unlock bypass modes are not available when the Se-

cured Silicon Sector is enabled.

from “0” back to a “1.” Attempting to do so may

cause that bank to set DQ5 = 1, or cause the DQ7 and

DQ6 status bits to indicate the operation was success-

ful. However, a succeeding read shows that the data is

still “0.” Only erase operations can convert a “0” to a

“1.”

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to pro-

gram bytes or words to a bank faster than using the

standard program command sequence. The unlock

bypass command sequence is initiated by first writing

two unlock cycles. This is followed by a third write

cycle containing the unlock bypass command, 20h.

That bank then enters the unlock bypass mode. A

two-cycle unlock bypass program command sequence

is all that is required to program in this mode. The first

cycle in this sequence contains the unlock bypass pro-

gram command, A0h; the second cycle contains the

program address and data. Additional data is pro-

grammed in the same manner. This mode dispenses

with the initial two unlock cycles required in the stan-

dard program command sequence, resulting in faster

total programming time. Table 12 shows the require-

ments for the command sequence.

Byte/Word Program Command Sequence

The system may program the device by word or byte,

depending on the state of the BYTE# pin. Program-

ming is a four-bus-cycle operation. The program

command sequence is initiated by writing two unlock

write cycles, followed by the program set-up com-

mand. The program address and data are written next,

which in turn initiate the Embedded Program algo-

rithm. The system is not required to provide further

controls or timings. The device automatically provides

internally generated program pulses and verifies the

programmed cell margin. Table 12 shows the address

and data requirements for the byte program command

sequence. Note that the Secured Silicon Sector, au-

toselect, and CFI functions are unavailable when a

program operation in is progress.

During the unlock bypass mode, only the Unlock By-

pass Program and Unlock Bypass Reset commands

are valid. To exit the unlock bypass mode, the system

must issue the two-cycle unlock bypass reset com-

mand sequence. (See Table 12).

The device offers accelerated program operations

through the WP#/ACC pin. When the system asserts

V_HHon the WP#/ACC pin, the device automatically en-

ters the Unlock Bypass mode. The system may then

write the two-cycle Unlock Bypass program command

sequence. The device uses the higher voltage on the

WP#/ACC pin to accelerate the operation. Note that

the WP#/ACC pin must not be at V_HHany operation

other than accelerated programming, or device dam-

age may result. In addition, the WP#/ACC pin must not

be left floating or unconnected; inconsistent behavior

of the device may result.

When the Embedded Program algorithm is complete,

that bank then returns to the read mode and ad-

dresses are no longer latched. The system can

determine the status of the program operation by

using DQ7, DQ6, or RY/BY#. Refer to the Write Oper-

ation Status section for information on these status

bits.

Any commands written to the device during the Em-

bedded Program Algorithm are ignored. Note that a

hardware reset immediately terminates the program

operation. The program command sequence should

be reinitiated once that bank has returned to the read

mode, to ensure data integrity.

Figure 4 illustrates the algorithm for the program oper-

ation. Refer to the Erase and Program Operations

table in the AC Characteristics section for parameters,

and Figure 18 for timing diagrams.

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed

24

Am29DL640D

December 13, 2005

Any commands written during the chip erase operation

are ignored. However, note that a hardware reset im-

mediately terminates the erase operation. If that

occurs, the chip erase command sequence should be

reinitiated once that bank has returned to reading

array data, to ensure data integrity.

START

Figure 5 illustrates the algorithm for the erase opera-

tion. Refer to the Erase and Program Operations

tables in the AC Characteristics section for parame-

ters, and Figure 20 section for timing diagrams.

Write Program

Command Sequence

Data Poll

from System

Sector Erase Command Sequence

Embedded

Program

algorithm

in progress

Sector erase is a six bus cycle operation. The sector

erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two ad-

ditional unlock cycles are written, and are then

followed by the address of the sector to be erased, and

the sector erase command. Table 12 shows the ad-

dress and data requirements for the sector erase

command sequence. Note that the Secured Silicon

Sector, autoselect, and CFI functions are unavailable

when an erase operation in is progress.

Verify Data?

Yes

No

Increment Address

Last Address?

Yes

The device does not require the system to preprogram

prior to erase. The Embedded Erase algorithm auto-

matically programs and verifies the entire memory for

an all zero data pattern prior to electrical erase. The

system is not required to provide any controls or tim-

ings during these operations.

Programming

Completed

Note: See Table 12 for program command sequence.

After the command sequence is written, a sector erase

time-out of 80 µs occurs. During the time-out period,

additional sector addresses and sector erase com-

mands may be written. Loading the sector erase buffer

may be done in any sequence, and the number of sec-

tors may be from one sector to all sectors. The time

between these additional cycles must be less than 80

µs, otherwise erasure may begin. Any sector erase ad-

dress and command following the exceeded time-out

may or may not be accepted. It is recommended that

processor interrupts be disabled during this time to en-

sure all commands are accepted. The interrupts can

be re-enabled after the last Sector Erase command is

written. Any command other than Sector Erase or

Erase Suspend during the time-out period resets

that bank to the read mode. The system must rewrite

the command sequence and any additional addresses

and commands. Note that the Secured Silicon Sector,

autoselect, and CFI functions are unavailable when an

erase operation in is progress.

Figure 4. Program Operation

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase

command sequence is initiated by writing two unlock

cycles, followed by a set-up command. Two additional

unlock write cycles are then followed by the chip erase

command, which in turn invokes the Embedded Erase

algorithm. The device does not require the system to

preprogram prior to erase. The Embedded Erase algo-

rithm automatically preprograms and verifies the entire

memory for an all zero data pattern prior to electrical

erase. The system is not required to provide any con-

trols or timings during these operations. Table 12

shows the address and data requirements for the chip

erase command sequence. Note that the Secured Sili-

con Sector, autoselect, and CFI functions are

unavailable when an erase operation in is progress.

The system can monitor DQ3 to determine if the sec-

tor erase timer has timed out (See the section on DQ3:

Sector Erase Timer.). The time-out begins from the ris-

ing edge of the final WE# pulse in the command

sequence.

When the Embedded Erase algorithm is complete,

that bank returns to the read mode and addresses are

no longer latched. The system can determine the sta-

tus of the erase operation by using DQ7, DQ6, DQ2,

or RY/BY#. Refer to the Write Operation Status sec-

tion for information on these status bits.

When the Embedded Erase algorithm is complete, the

bank returns to reading array data and addresses are

December 13, 2005

Am29DL640D

25

no longer latched. Note that while the Embedded

Erase operation is in progress, the system can read

data from the non-erasing bank. The system can de-

termine the status of the erase operation by reading

DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. Refer

to the Write Operation Status section for information

on these status bits.

mode. The system can determine the status of the

program operation using the DQ7 or DQ6 status bits,

just as in the standard Byte Program operation.

Refer to the Write Operation Status section for more

information.

In the erase-suspend-read mode, the system can also

issue the autoselect command sequence. The device

allows reading autoselect codes even at addresses

within erasing sectors, since the codes are not stored

in the memory array. When the device exits the au-

toselect mode, the device reverts to the Erase

Suspend mode, and is ready for another valid opera-

tion. Refer to the Autoselect Mode and Autoselect

Command Sequence sections for details.

Once the sector erase operation has begun, only the

Erase Suspend command is valid. All other com-

mands are ignored. However, note that a hardware

reset immediately terminates the erase operation. If

that occurs, the sector erase command sequence

should be reinitiated once that bank has returned to

reading array data, to ensure data integrity.

Figure 5 illustrates the algorithm for the erase opera-

tion. Refer to the Erase and Program Operations

tables in the AC Characteristics section for parame-

ters, and Figure 20 section for timing diagrams.

To resume the sector erase operation, the system

must write the Erase Resume command (address bits

are don’t care). The bank address of the erase-sus-

pended bank is required when writing this command.

Further writes of the Resume command are ignored.

Another Erase Suspend command can be written after

the chip has resumed erasing.

Erase Suspend/Erase Resume

Commands

The Erase Suspend command, B0h, allows the sys-

tem to interrupt a sector erase operation and then read

data from, or program data to, any sector not selected

for erasure. The bank address is required when writing

this command. This command is valid only during the

sector erase operation, including the 80 µs time-out

period during the sector erase command sequence.

The Erase Suspend command is ignored if written dur-

ing the chip erase operation or Embedded Program

algorithm.

START

Write Erase

Command Sequence

(Notes 1, 2)

When the Erase Suspend command is written during

the sector erase operation, the device requires a max-

imum of 20 µs to suspend the erase operation.

However, when the Erase Suspend command is writ-

ten during the sector erase time-out, the device

immediately terminates the time-out period and sus-

pends the erase operation. Addresses are

“don’t-cares” when writing the Erase suspend

command.

Data Poll to Erasing

Bank from System

Embedded

Erase

algorithm

in progress

No

Data = FFh?

After the erase operation has been suspended, the

bank enters the erase-suspend-read mode. The sys-

tem can read data from or program data to any sector

not selected for erasure. (The device “erase sus-

pends” all sectors selected for erasure.) Reading at

any address within erase-suspended sectors pro-

duces status information on DQ7–DQ0. The system

can use DQ7, or DQ6 and DQ2 together, to determine

if a sector is actively erasing or is erase-suspended.

Refer to the Write Operation Status section for infor-

mation on these status bits.

Yes

Erasure Completed

Notes:

1. See Table 12 for erase command sequence.

2. See the section on DQ3 for information on the sector

erase timer.

Figure 5. Erase Operation

After an erase-suspended program operation is com-

plete, the bank returns to the erase-suspend-read

26

Am29DL640D

December 13, 2005

Table 12. Am29DL640D Command Definitions

Bus Cycles (Notes 2–5)

Command

Sequence (Note 1)

(Notes)

First

Second

Third

Addr

Fourth

Addr Data

Fifth

Addr

Sixth

Addr

Addr Data Addr Data

Data

Read (6)

Reset (7)

1

RA

XXX

555

AAA

555

AAA

555

AAA

555

AAA

555

AAA

555

AAA

555

AAA

555

AAA

XXX

BA

RD

F0

Word

Byte

Word

Byte

Word

Byte

Word

Byte

Word

Byte

Word

Byte

Word

Byte

Word

Byte

2AA

555

2AA

555

2AA

555

2AA

555

2AA

555

2AA

555

2AA

555

2AA

555

PA

(BA)555

(BA)AAA

(BA)555

(BA)AAA

(BA)555

(BA)AAA

(BA)555

(BA)AAA

555

AAA

555

AAA

555

Manufacturer ID

4

6

4

3

4

3

AA

55

90 (BA)X00 01

(BA)X01

(BA)X0E

(BA)X1C

(BA)X0F

(BA)X1E

Device ID (9)

90

88

90

A0

20

7E

02

01

(BA)X02

(BA)X03

(BA)X06

(SA)X02

(SA)X04

Secured Silicon Sector

Factory Protect (10)

80/00

00/01

Sector/Sector Block

Protect Verify (11)

Enter Secured Silicon

Sector Region

Exit Secured Silicon Sector

Region

XXX

PA

00

Program

PD

AAA

555

AAA

Unlock Bypass

Unlock Bypass Program (12)

Unlock Bypass Reset (13)

2

A0

90

PD

00

XXX

2AA

555

2AA

555

Word

Byte

Word

Byte

555

AAA

555

AAA

BA

555

AAA

555

AAA

555

2AA

555

2AA

555

AAA

Chip Erase

6

AA

55

80

AA

55

10

30

Sector Erase

SA

AAA

Erase Suspend (14)

Erase Resume (15)

1

B0

30

BA

Word

Byte

55

AA

CFI Query (16)

1

98

Legend:

X = Don’t care

PD = Data to be programmed at location PA. Data latches on the rising

edge of WE# or CE# pulse, whichever happens first.

RA = Address of the memory location to be read.

RD = Data read from location RA during read operation.

PA = Address of the memory location to be programmed. Addresses

latch on the falling edge of the WE# or CE# pulse, whichever happens

later.

SA = Address of the sector to be verified (in autoselect mode) or

erased. Address bits A21–A15 uniquely select any sector in a x16-only

device. Address bits A22–A16 uniquely select any sector in a x8-only

device. Refer to Table 2 for information on sector addresses.

BA = Address of the bank that is being switched to autoselect mode, is

in bypass mode, or is being erased.

Notes:

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

9. The device ID must be read across the fourth, fifth, and sixth

cycles.

10. The data is 80h for factory locked and 00h for not factory locked.

11. The data is 00h for an unprotected sector/sector block and 01h for

a protected sector/sector block.

12. The Unlock Bypass command is required prior to the Unlock

Bypass Program command.

13. The Unlock Bypass Reset command is required to return to the

read mode when the bank is in the unlock bypass mode.

14. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode.

The Erase Suspend command is valid only during a sector erase

operation, and requires the bank address.

15. The Erase Resume command is valid only during the Erase

Suspend mode, and requires the bank address.

16. Command is valid when device is ready to read array data or when

device is in autoselect mode.

3. Except for the read cycle and the fourth cycle of the autoselect

command sequence, all bus cycles are write cycles.

4. Data bits DQ15–DQ8 are don’t care in command sequences,

except for RD and PD.

5. Unless otherwise noted, address bits A21–A11 (x16-only devices)

or address bits A22–A11 (x8-only devices) are don’t cares for

unlock and command cycles, unless SA or PA is required.

6. No unlock or command cycles required when bank is reading

array data.

7. The Reset command is required to return to the read mode (or to

the erase-suspend-read mode if previously in Erase Suspend)

when a bank is in the autoselect mode, or if DQ5 goes high (while

the bank is providing status information).

8. The fourth cycle of the autoselect command sequence is a read

cycle. The system must provide the bank address to obtain the

manufacturer ID, device ID, or Secured Silicon Sector factory

protect information. Data bits DQ15–DQ8 are don’t care. See the

Autoselect Command Sequence section for more information.

December 13, 2005

Am29DL640D

27

WRITE OPERATION STATUS

The device provides several bits to determine the status of a

program or erase operation: DQ2, DQ3, DQ5, DQ6, and

DQ7. Table 13 and the following subsections describe the

function of these bits. DQ7 and DQ6 each offer a method for

determining whether a program or erase operation is com-

plete or in progress. The device also provides a

hardware-based output signal, RY/BY#, to determine

whether an Embedded Program or Erase operation is in

progress or has been completed.

has completed the program or erase operation and

DQ7 has valid data, the data outputs on DQ0–DQ15

may be still invalid. Valid data on DQ0–DQ15 (or

DQ0–DQ7 for x8-only device) appears on successive

read cycles.

Table 13 shows the outputs for Data# Polling on DQ7.

Figure 6 shows the Data# Polling algorithm. Figure 22

in the AC Characteristics section shows the Data#

Polling timing diagram.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host system

whether an Embedded Program or Erase algorithm is in

progress or completed, or whether a bank is in Erase Sus-

pend. Data# Polling is valid after the rising edge of the final

WE# pulse in the command sequence.

START

Read DQ7–DQ0

Addr = VA

During the Embedded Program algorithm, the device out-

puts on DQ7 the complement of the datum programmed to

DQ7. This DQ7 status also applies to programming during

Erase Suspend. When the Embedded Program algorithm is

complete, the device outputs the datum programmed to

DQ7. The system must provide the program address to

read valid status information on DQ7. If a program address

falls within a protected sector, Data# Polling on DQ7 is ac-

tive for approximately 1 µs, then that bank returns to the

read mode.

Yes

DQ7 = Data?

No

DQ5 = 1?

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase

algorithm is complete, or if the bank enters the Erase

Suspend mode, Data# Polling produces a “1” on DQ7.

The system must provide an address within any of the

sectors selected for erasure to read valid status infor-

mation on DQ7.

Yes

Read DQ7–DQ0

Addr = VA

After an erase command sequence is written, if all

sectors selected for erasing are protected, Data# Poll-

ing on DQ7 is active for approximately 100 µs, then the

bank returns to the read mode. If not all selected sec-

tors are protected, the Embedded Erase algorithm

erases the unprotected sectors, and ignores the se-

lected sectors that are protected. However, if the

system reads DQ7 at an address within a protected

sector, the status may not be valid.

Yes

DQ7 = Data?

No

PASS

FAIL

When the system detects DQ7 has changed from the

complement to true data, it can read valid data at

DQ15–DQ0 (or DQ7–DQ0 for x8-only device) on the

following read cycles. Just prior to the completion of an

Embedded Program or Erase operation, DQ7 may

change asynchronously with DQ8–DQ15 (DQ0–-DQ7

for x8-only device) while Output Enable (OE#) is as-

serted low. That is, the device may change from

providing status information to valid data on DQ7. De-

pending on when the system samples the DQ7 output,

it may read the status or valid data. Even if the device

Notes:

1. VA = Valid address for programming. During a sector

erase operation, a valid address is any sector address

within the sector being erased. During chip erase, a

valid address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

Figure 6. Data# Polling Algorithm

28

Am29DL640D

December 13, 2005

DQ6 also toggles during the erase-suspend-program

mode, and stops toggling once the Embedded Pro-

gram algorithm is complete.

RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output pin

which indicates whether an Embedded Algorithm is in

progress or complete. The RY/BY# status is valid after

the rising edge of the final WE# pulse in the command

sequence. Since RY/BY# is an open-drain output, sev-

eral RY/BY# pins can be tied together in parallel with a

Table 13 shows the outputs for Toggle Bit I on DQ6.

Figure 7 shows the toggle bit algorithm. Figure 23 in

the AC Characteristics section shows the toggle bit

timing diagrams. Figure 24 shows the differences be-

tween DQ2 and DQ6 in graphical form. See also the

subsection on DQ2: Toggle Bit II.

pull-up resistor to V_CC

.

If the output is low (Busy), the device is actively eras-

ing or programming. (This includes programming in

the Erase Suspend mode.) If the output is high

(Ready), the device is in the read mode, the standby

mode, or one of the banks is in the erase-sus-

pend-read mode.

START

Table 13 shows the outputs for RY/BY#.

Read DQ7–DQ0

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded

Program or Erase algorithm is in progress or com-

plete, or whether the device has entered the Erase

Suspend mode. Toggle Bit I may be read at any ad-

dress, and is valid after the rising edge of the final

WE# pulse in the command sequence (prior to the

program or erase operation), and during the sector

erase time-out.

Read DQ7–DQ0

No

Toggle Bit

= Toggle?

During an Embedded Program or Erase algorithm op-

eration, successive read cycles to any address cause

DQ6 to toggle. The system may use either OE# or

CE# to control the read cycles. When the operation is

complete, DQ6 stops toggling.

Yes

No

DQ5 = 1?

Yes

After an erase command sequence is written, if all

sectors selected for erasing are protected, DQ6 tog-

gles for approximately 100 µs, then returns to reading

array data. If not all selected sectors are protected, the

Embedded Erase algorithm erases the unprotected

sectors, and ignores the selected sectors that are

protected.

Read DQ7–DQ0

Twice

The system can use DQ6 and DQ2 together to deter-

mine whether a sector is actively erasing or is

erase-suspended. When the device is actively erasing

(that is, the Embedded Erase algorithm is in progress),

DQ6 toggles. When the device enters the Erase Sus-

pend mode, DQ6 stops toggling. However, the system

must also use DQ2 to determine which sectors are

erasing or erase-suspended. Alternatively, the system

can use DQ7 (see the subsection on DQ7: Data#

Polling).

Toggle Bit

= Toggle?

No

Yes

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Note: The system should recheck the toggle bit even if DQ5

= “1” because the toggle bit may stop toggling as DQ5

changes to “1.” See the subsections on DQ6 and DQ2 for

more information.

If a program address falls within a protected sector,

DQ6 toggles for approximately 1 µs after the program

command sequence is written, then returns to reading

array data.

Figure 7. Toggle Bit Algorithm

December 13, 2005

Am29DL640D

29

the toggle bit and DQ5 through successive read cy-

cles, determining the status as described in the

previous paragraph. Alternatively, it may choose to

perform other system tasks. In this case, the system

must start at the beginning of the algorithm when it re-

turns to determine the status of the operation (top of

Figure 7).

DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, when used with DQ6, indi-

cates whether a particular sector is actively erasing

(that is, the Embedded Erase algorithm is in progress),

or whether that sector is erase-suspended. Toggle Bit

II is valid after the rising edge of the final WE# pulse in

the command sequence.

DQ5: Exceeded Timing Limits

DQ2 toggles when the system reads at addresses

within those sectors that have been selected for era-

sure. (The system may use either OE# or CE# to

control the read cycles.) But DQ2 cannot distinguish

whether the sector is actively erasing or is erase-sus-

pended. DQ6, by comparison, indicates whether the

device is actively erasing, or is in Erase Suspend, but

cannot distinguish which sectors are selected for era-

sure. Thus, both status bits are required for sector and

mode information. Refer to Table 13 to compare out-

puts for DQ2 and DQ6.

DQ5 indicates whether the program or erase time has

exceeded a specified internal pulse count limit. Under these

conditions DQ5 produces a “1,” indicating that the program

or erase cycle was not successfully completed.

The device may output a “1” on DQ5 if the system tries

to program a “1” to a location that was previously pro-

grammed to “0.” Only an erase operation can

change a “0” back to a “1.” Under this condition, the

device halts the operation, and when the timing limit

has been exceeded, DQ5 produces a “1.”

Figure 7 shows the toggle bit algorithm in flowchart

form, and the section DQ2: Toggle Bit II explains the

algorithm. See also the DQ6: Toggle Bit I subsection.

Figure 23 shows the toggle bit timing diagram.

Figure 24 shows the differences between DQ2 and

DQ6 in graphical form.

Under both these conditions, the system must write

the reset command to return to the read mode (or to

the erase-suspend-read mode if a bank was previ-

ously in the erase-suspend-program mode).

DQ3: Sector Erase Timer

Reading Toggle Bits DQ6/DQ2

After writing a sector erase command sequence, the

system may read DQ3 to determine whether or not

erasure has begun. (The sector erase timer does not

apply to the chip erase command.) If additional

sectors are selected for erasure, the entire time-out

also applies after each additional sector erase com-

mand. When the time-out period is complete, DQ3

switches from a “0” to a “1.” If the time between addi-

tional sector erase commands from the system can be

assumed to be less than 50 µs, the system need not

monitor DQ3. See also the Sector Erase Command

Sequence section.

Refer to Figure 7 for the following discussion. When-

ever the system initially begins reading toggle bit

status, it must read DQ15–DQ0 (or DQ7–DQ0 for

x8-only device) at least twice in a row to determine

whether a toggle bit is toggling. Typically, the system

would note and store the value of the toggle bit after

the first read. After the second read, the system would

compare the new value of the toggle bit with the first. If

the toggle bit is not toggling, the device has completed

the program or erase operation. The system can read

array data on DQ15–DQ0 (or DQ7–DQ0 for x8-only

device) on the following read cycle.

After the sector erase command is written, the system

should read the status of DQ7 (Data# Polling) or DQ6

(Toggle Bit I) to ensure that the device has accepted

the command sequence, and then read DQ3. If DQ3 is

“1,” the Embedded Erase algorithm has begun; all fur-

ther commands (except Erase Suspend) are ignored

until the erase operation is complete. If DQ3 is “0,” the

device accepts additional sector erase commands. To

ensure the command has been accepted, the system

software should check the status of DQ3 prior to and

following each subsequent sector erase command. If

DQ3 is high on the second status check, the last com-

mand might not have been accepted.

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the sys-

tem also should note whether the value of DQ5 is high

(see the section on DQ5). If it is, the system should

then determine again whether the toggle bit is tog-

gling, since the toggle bit may have stopped toggling

just as DQ5 went high. If the toggle bit is no longer

toggling, the device has successfully completed the

program or erase operation. If it is still toggling, the de-

vice did not completed the operation successfully, and

the system must write the reset command to return to

reading array data.

Table 13 shows the status of DQ3 relative to the other

status bits.

The remaining scenario is that the system initially de-

termines that the toggle bit is toggling and DQ5 has

not gone high. The system may continue to monitor

30

Am29DL640D

December 13, 2005

Table 13. Write Operation Status

DQ7

DQ5

DQ2

Status

(Note 2)

DQ6

(Note 1)

DQ3

N/A

1

(Note 2)

RY/BY#

Embedded Program Algorithm

Embedded Erase Algorithm

Erase

Erase-Suspend-

Read

DQ7#

0

Toggle

0

No toggle

Toggle

0

Standard

Mode

1

No toggle

0

N/A

Toggle

1

Suspended Sector

Erase

Suspend

Mode

Non-Erase

Suspended Sector

Data

0

Data

N/A

Data

N/A

1

0

Erase-Suspend-Program

DQ7#

Toggle

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

Refer to the section on DQ5 for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further

details.

3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm

is in progress. The device outputs array data if the system addresses a non-busy bank.

December 13, 2005

Am29DL640D

31

ABSOLUTE MAXIMUM RATINGS

Exposure of the device to absolute maximum rating

conditions for extended periods may affect device reliability.

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . –65°C to +125°C

20 ns

Voltage with Respect to Ground

+0.8 V

V_CC(Note 1) . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V

–0.5 V

–2.0 V

A9, OE#, and RESET#

(Note 2). . . . . . . . . . . . . . . . . . . .–0.5 V to +12.5 V

WP#/ACC . . . . . . . . . . . . . . . . . .–0.5 V to +10.5 V

All other pins (Note 1). . . . . . –0.5 V to V_CC+0.5 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

20 ns

Notes:

Figure 8. Maximum Negative

Overshoot Waveform

1. Minimum DC voltage on input or I/O pins is –0.5 V.

During voltage transitions, input or I/O pins may

overshoot V_SSto –2.0 V for periods of up to 20 ns.

Maximum DC voltage on input or I/O pins is V_CC+0.5 V.

See Figure 8. During voltage transitions, input or I/O pins

may overshoot to V_CC+2.0 V for periods up to 20 ns. See

Figure 9.

20 ns

V_CC

+2.0 V

V_CC

+0.5 V

2. Minimum DC input voltage on pins A9, OE#, RESET#,

and WP#/ACC is –0.5 V. During voltage transitions, A9,

OE#, WP#/ACC, and RESET# may overshoot V_SSto

–2.0 V for periods of up to 20 ns. See Figure 8. Maximum

DC input voltage on pin A9 is +12.5 V which may

overshoot to +14.0 V for periods up to 20 ns. Maximum

DC input voltage on WP#/ACC is +9.5 V which may

overshoot to +12.0 V for periods up to 20 ns.

2.0 V

20 ns

3. No more than one output may be shorted to ground at a

time. Duration of the short circuit should not be greater

than one second.

Figure 9. Maximum Positive Overshoot Waveform

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This

is a stress rating only; functional operation of the device at

these or any other conditions above those indicated in the

operational sections of this data sheet is not implied.

OPERATING RANGES

Industrial (I) Devices

Ambient Temperature (T_A) . . . . . . . . . –40°C to +85°C

Extended (E) Devices

Ambient Temperature (T_A) . . . . . . . . –55°C to +125°C

V_CCSupply Voltages

V

_CCfor standard voltage range . . . . . . .2.7 V to 3.6 V

Operating ranges define those limits between which the

functionality of the device is guaranteed.

32

Am29DL640D

December 13, 2005

DC CHARACTERISTICS

CMOS Compatible

Parameter

Symbol

Parameter Description

(Notes)

Test Conditions

V_IN= V_SSto V_CC

V_CC= V_{CC max}

V_CC= V_{CC max}; A9 = 12.5 V

_OUT= V_SSto V_CC

V_CC= V_{CC max}

Min

Typ

Max

±1.0

35

Unit

µA

,

I_LI

Input Load Current

I_LIT

I_LO

A9 Input Load Current

Output Leakage Current

µA

V

,

±1.0

µA

5 MHz

1 MHz

5 MHz

1 MHz

10

2

16

4

CE# = V_IL, OE# ₌V_IH,

Byte Mode

V_CCActive Read Current

(1, 2)

I_CC1

mA

10

2

16

4

CE# = V_IL, OE# = V_IH,

Word Mode

I_CC2

I_CC3

I_CC4

V_CCActive Write Current (2, 3)

V_CCStandby Current (2)

V_CCReset Current (2)

CE# = V_IL, OE# = V_IH, WE# = V_IL

CE#, RESET# = V_CC± 0.3 V

RESET# = V_SS± 0.3 V

15

0.2

30

5

mA

µA

5

V

_IH= V_CC± 0.3 V;

I_CC5

Automatic Sleep Mode (2, 4)

0.2

5

µA

V_IL= V_SS± 0.3 V

Byte

Word

Byte

21

45

V_CCActive Read-While-Program

Current (1, 2)

I_CC6

CE# = V_IL, OE# = V_IH

mA

V_CCActive Read-While-Erase

Current (1, 2)

I_CC7

CE# = V_IL, OE# = V_IH

mA

Word

V_CCActive

Program-While-Erase-Suspended

Current (2, 5)

I_CC8

17

35

V_IL

V_IH

Input Low Voltage

Input High Voltage

–0.5

0.8

V

0.7 x V_CC

V_CC+ 0.3

Voltage for WP#/ACC Sector

Protect/Unprotect and Program

Acceleration

V_HH

V_CC= 3.0 V 10%

8.5

9.5

V

Voltage for Autoselect and Temporary

Sector Unprotect

V_ID

V_CC= 3.0 V ± 10%

11.5

12.5

0.45

V_OL

V_OH1

Output Low Voltage

I_OL= 4.0 mA, V_CC= V_{CC min}

I_OH= –2.0 mA, V_CC= V_{CC min}

I_OH= –100 µA, V_CC= V_{CC min}

V

0.85 V_CC

V_CC– 0.4

2.3

Output High Voltage

V_OH2

V_LKO

Low V_CCLock-Out Voltage (5)

2.5

V

Notes:

1. The I_CCcurrent listed is typically less than 2 mA/MHz, with OE# at V_IH.

2. Maximum I_CCspecifications are tested with V_CC= V_CCmax.

3. I_CCactive while Embedded Erase or Embedded Program is in progress.

4. Automatic sleep mode enables the low power mode when addresses remain stable for t_ACC+ 30 ns. Typical sleep mode current is

200 nA.

5. Not 100% tested.

December 13, 2005

Am29DL640D

33

DC CHARACTERISTICS

Zero-Power Flash

25

20

15

10

5

0

500

1000

1500

2000

2500

3000

3500

4000

Time in ns

Note: Addresses are switching at 1 MHz

Figure 10. I_CC1Current vs. Time (Showing Active and Automatic Sleep Currents)

12

10

8

3.6 V

2.7 V

6

4

2

0

1

2

3

4

5

Frequency in MHz

Note: T = 25 °C

Figure 11. Typical I_CC1vs. Frequency

34

Am29DL640D

December 13, 2005

TEST CONDITIONS

Table 14. Test Specifications

Test Condition 90, 120

1 TTL gate

3.3 V

Unit

Output Load

2.7 kΩ

Device

Under

Test

Output Load Capacitance, C_L

(including jig capacitance)

30

pF

Input Rise and Fall Times

Input Pulse Levels

5

ns

V

C

L

6.2 kΩ

0.0–3.0

Input timing measurement

reference levels

1.5

V

Output timing measurement

reference levels

Note: Diodes are IN3064 or equivalent

Figure 12. Test Setup

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Center Line is High Impedance State (High Z)

KS000010-PAL

3.0 V

0.0 V

1.5 V

Input

Measurement Level

Output

Figure 13. Input Waveforms and Measurement Levels

December 13, 2005

Am29DL640D

35

AC CHARACTERISTICS

Read-Only Operations

Parameter

Speed Options

Description

(Notes)

JEDEC

t_AVAV

Std.

Test Setup

90

35

120

50

Unit

ns

t_RC

Read Cycle Time (1)

Min

Max

t_AVQV

t_ELQV

t_GLQV

t_EHQZ

t_GHQZ

t_ACCAddress to Output Delay

CE#, OE# = V_IL

OE# = V_IL

ns

t_CE

t_OE

t_DF

Chip Enable to Output Delay

ns

Output Enable to Output Delay

Chip Enable to Output High Z (1, 3)

Output Enable to Output High Z ( 1, 3)

ns

30

ns

Output Hold Time From Addresses, CE# or

OE#, Whichever Occurs First

t_AXQX

t_OH

Min

0

ns

Read

Min

0

ns

Output Enable

Hold Time (1)

t_OEH

Toggle and Data# Polling

10

Notes:

1. Not 100% tested.

2. See Figure 12 and Table 14 for test specifications

3. Measurements performed by placing a 50Ω termination on the data pin with a bias of V_CC/2. The time from OE# high to the

data bus driven to V_CC/2 is taken as t_DF

.

t_RC

Addresses Stable

t_ACC

Addresses

CE#

t_RH

t_DF

t_OE

OE#

t_OEH

WE#

t_CE

t_OH

HIGH Z

Output Valid

Outputs

RESET#

RY/BY#

0 V

Figure 14. Read Operation Timings

36

Am29DL640D

December 13, 2005

AC CHARACTERISTICS

Hardware Reset (RESET#)

Parameter

JEDEC

Std

Description

All Speed Options

Unit

RESET# Pin Low (During Embedded Algorithms)

to Read Mode (See Note)

t_Ready

Max

20

µs

RESET# Pin Low (NOT During Embedded

Algorithms) to Read Mode (See Note)

t_Ready

500

ns

t_RP

t_RH

t_RPD

t_RB

RESET# Pulse Width

Min

500

50

20

0

ns

µs

ns

Reset High Time Before Read (See Note)

RESET# Low to Standby Mode

RY/BY# Recovery Time

Note: Not 100% tested.

RY/BY#

CE#, OE#

RESET#

t_RH

t_RP

t_Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

t_Ready

RY/BY#

t_RB

CE#, OE#

RESET#

t_RP

Figure 15. Reset Timings

December 13, 2005

Am29DL640D

37

AC CHARACTERISTICS

Word/Byte Configuration (BYTE#)

Parameter

Speed Options

JEDEC

Std

t_{ELFL/ ELFH}

t_FLQZ

t_FHQV

Description

90

120

Unit

ns

t

CE# to BYTE# Switching Low or High

BYTE# Switching Low to Output HIGH Z

BYTE# Switching High to Output Active

Max

Min

5

30

90

30

ns

120

ns

CE#

OE#

BYTE#

t_ELFL

Data Output

(DQ0–DQ14)

Data Output

(DQ0–DQ7)

BYTE#

DQ0–DQ14

Switching

from word

to byte

Address

Input

DQ15

Output

mode

DQ15/A-1

t_FLQZ

t_ELFH

BYTE#

Switching

from byte

to word

Data Output

(DQ0–DQ7)

Data Output

(DQ0–DQ14)

DQ0–DQ14

DQ15/A-1

mode

Address

Input

DQ15

Output

t_FHQV

Figure 16. BYTE# Timings for Read Operations

CE#

The falling edge of the last WE# signal

WE#

BYTE#

t_SET

(t_AS

)

t_HOLD(t_AH

)

Note: Refer to the Erase/Program Operations table for t_ASand t_AHspecifications.

Figure 17. BYTE# Timings for Write Operations

38

Am29DL640D

December 13, 2005

AC CHARACTERISTICS

Erase and Program Operations

Parameter

Speed Options

Description

(Notes)

JEDEC

t_AVAV

Std

t_WC

t_AS

90

0

120

Unit

ns

Write Cycle Time (1)

Address Setup Time

Min

120

t_AVWL

t_ASO

t_AH

t_AHT

t_DS

Address Setup Time to OE# low during toggle bit polling

Address Hold Time

15

0

t_WLAX

45

50

Address Hold Time From CE# or OE# high during toggle bit polling Min

t_DVWH

t_WHDX

Data Setup Time

Data Hold Time

Min

t_DH

0

t_OEPHOutput Enable High during toggle bit polling

20

Read Recovery Time Before Write

t_GHWL

Min

0

ns

(OE# High to WE# Low)

t_ELWL

t_WHEH

t_WLWH

t_WHDL

t_CS

t_CH

CE# Setup Time

Min

Typ

Min

Max

0

ns

CE# Hold Time

t_WP

Write Pulse Width

35

30

50

30

t_WPH

t_SR/W

Write Pulse Width High

Latency Between Read and Write Operations

0

8.6

12.6

4

Byte

t_WHWH1

t_WHWH1Programming Operation (2)

µs

Word

t_WHWH1

t_WHWH2

t_WHWH1Accelerated Programming Operation, Word or Byte (2)

t_WHWH2Sector Erase Operation (2)

µs

sec

µs

0.7

50

0

t_VCS

t_RB

V_CCSetup Time (1)

Write Recovery Time from RY/BY#

ns

t_BUSYProgram/Erase Valid to RY/BY# Delay

90

ns

Notes:

1. Not 100% tested.

2. See the Erase And Programming Performance section for more information.

December 13, 2005

Am29DL640D

39

AC CHARACTERISTICS

Program Command Sequence (last two cycles)

Read Status Data (last two cycles)

t_AS

PA

t_WC

Addresses

555h

PA

t_AH

CE#

OE#

t_CH

t_WHWH1

t_WP

WE#

Data

t_WPH

t_CS

t_DS

t_DH

PD

D_OUT

A0h

Status

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. PA = program address, PD = program data, D_OUTis the true data at the program address.

2. Illustration shows device in word mode.

Figure 18. Program Operation Timings

V_HH

V_ILor V_IH

WP#/ACC

V_ILor V_IH

t_VHH

Figure 19. Accelerated Program Timing Diagram

40

Am29DL640D

December 13, 2005

AC CHARACTERISTICS

Erase Command Sequence (last two cycles)

Read Status Data

VA

t_AS

SA

t_WC

VA

Addresses

CE#

2AAh

555h for chip erase

t_AH

t_CH

OE#

t_WP

WE#

t_WPH

t_WHWH2

t_CS

t_DS

t_DH

In

Data

Complete

55h

30h

Progress

10 for Chip Erase

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation Status.)

2. These waveforms are for the word mode.

Figure 20. Chip/Sector Erase Operation Timings

December 13, 2005

Am29DL640D

41

AC CHARACTERISTICS

t_WC

Valid PA

t_WC

t_RC

t_WC

Valid PA

Valid RA

Valid PA

Addresses

t_AH

t_CPH

t_ACC

t_CE

CE#

t_CP

t_OE

OE#

t_OEH

t_GHWL

t_WP

WE#

t_DF

t_WPH

t_DS

t_OH

t_DH

Valid

Out

Valid

In

Valid

In

Valid

In

Data

t_SR/W

WE# Controlled Write Cycle

Read Cycle

CE# Controlled Write Cycles

Figure 21. Back-to-back Read/Write Cycle Timings

t_RC

Addresses

CE#

VA

t_ACC

t_CE

VA

t_CH

t_OE

OE#

WE#

t_OEH

t_DF

t_OH

High Z

DQ7

Valid Data

Complement

True

DQ0–DQ6

Valid Data

Status Data

True

Status Data

t_BUSY

RY/BY#

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data

read cycle.

Figure 22. Data# Polling Timings (During Embedded Algorithms)

42

Am29DL640D

December 13, 2005

AC CHARACTERISTICS

t_AHT

t_AS

Addresses

t_AHT

t_ASO

CE#

t_OEH

WE#

t_CEPH

t_OEPH

OE#

t_DH

Valid Data

t_OE

Valid

Status

Valid

Status

Valid

Status

DQ6/DQ2

Valid Data

(first read)

(second read)

(stops toggling)

RY/BY#

Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read

cycle, and array data read cycle.

Figure 23. Toggle Bit Timings (During Embedded Algorithms)

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

Erase

Erase Suspend

Read

Erase

Suspend

Program

Erase

Complete

WE#

Erase

Erase Suspend

Read

DQ6

DQ2

Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle

DQ2 and DQ6.

Figure 24. DQ2 vs. DQ6

December 13, 2005

Am29DL640D

43

AC CHARACTERISTICS

Temporary Sector Unprotect

Parameter

JEDEC

Std

t_VIDR

t_VHH

Description

All Speed Options

Unit

ns

V_IDRise and Fall Time (See Note)

V_HHRise and Fall Time (See Note)

Min

500

250

ns

RESET# Setup Time for Temporary Sector

Unprotect

t_RSP

Min

4

µs

RESET# Hold Time from RY/BY# High for

Temporary Sector Unprotect

t_RRB

Note: Not 100% tested.

V_ID

RESET#

V_SS, V_IL,

or V_IH

V_SS, V_IL,

or V_IH

t_VIDR

Program or Erase Command Sequence

CE#

WE#

t_RRB

t_RSP

RY/BY#

Figure 25. Temporary Sector Unprotect Timing Diagram

44

Am29DL640D

December 13, 2005

AC CHARACTERISTICS

V_ID

V_IH

RESET#

SA, A6,

A1, A0

Valid*

Status

Sector/Sector Block Protect or Unprotect

60h 60h

Verify

40h

Data

Sector/Sector Block Protect: 150 µs,

Sector/Sector Block Unprotect: 15 ms

1 µs

CE#

WE#

OE#

* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.

Figure 26. Sector/Sector Block Protect and

Unprotect Timing Diagram

December 13, 2005

Am29DL640D

45

AC CHARACTERISTICS

Alternate CE# Controlled Erase and Program Operations

Parameter

Speed Options

Description

JEDEC

t_AVAV

Std

t_WC

t_AS

(Notes)

90

120

Unit

ns

Write Cycle Time (1)

Address Setup Time

Address Hold Time

Data Setup Time

Data Hold Time

Min

90

120

t_AVWL

t_ELAX

t_DVEH

t_EHDX

0

ns

t_AH

t_DS

t_DH

45

50

ns

0

ns

Read Recovery Time Before Write

(OE# High to WE# Low)

t_GHEL

Min

ns

t_WLEL

t_EHWH

t_ELEH

t_EHEL

t_WS

t_WH

t_CP

WE# Setup Time

WE# Hold Time

Min

Typ

0

ns

CE# Pulse Width

CE# Pulse Width High

45

50

t_CPH

30

8.6

12.6

4

Byte

t_WHWH1

Programming Operation (2)

µs

Word

t_WHWH1

t_WHWH2

Notes:

t_WHWH1

t_WHWH2

Accelerated Programming Operation, Word or Byte (2)

Sector Erase Operation (2)

µs

0.7

sec

1. Not 100% tested.

2. See the Erase And Programming Performance section for more information.

46

Am29DL640D

December 13, 2005

AC CHARACTERISTICS

555 for program

PA for program

2AA for erase

SA for sector erase

555 for chip erase

Data# Polling

Addresses

PA

t_WC

t_WH

t_AS

t_AH

WE#

OE#

t_GHEL

t_{WHWH1 or 2}

t_CP

CE#

Data

t_WS

t_CPH

t_DS

t_BUSY

t_DH

DQ7#

D_OUT

t_RH

A0 for program

55 for erase

PD for program

30 for sector erase

10 for chip erase

RESET#

RY/BY#

Notes:

1. Figure indicates last two bus cycles of a program or erase operation.

2. PA = program address, SA = sector address, PD = program data.

3. DQ7# is the complement of the data written to the device. D_OUTis the data written to the device.

4. Waveforms are for the word mode.

Figure 27. Alternate CE# Controlled Write (Erase/Program) Operation Timings

December 13, 2005

Am29DL640D

47

ERASE AND PROGRAMMING PERFORMANCE

Typ

Max

Parameter

Sector Erase Time

(Note 1)

(Note 2)

Unit

sec

µs

Comments

0.7

100

5

15

Excludes 00h programming

prior to erasure (Note 4)

Chip Erase Time

Byte Program Time

150

120

210

126

84

Accelerated Byte/Word Program Time

Word Program Time

4

µs

Excludes system level

overhead (Note 5)

7

µs

Byte Mode

Word Mode

42

28

Chip Program Time (Note 3)

sec

Notes:

1. Typical program and erase times assume the following conditions: 25°C, 3.0 V V_CC, 1,000,000 cycles. Additionally,

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, V_CC= 2.7 V, 1,000,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See

Table 12 for further information on command definitions.

6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTICS

Description

Min

Max

Input voltage with respect to V_SSon all pins except I/O pins

(including A9, OE#, and RESET#)

–1.0 V

12.5 V

Input voltage with respect to V_SSon all I/O pins

V_CCCurrent

–1.0 V

V_CC+ 1.0 V

+100 mA

–100 mA

Note: Includes all pins except V_CC. Test conditions: V_CC= 3.0 V, one pin at a time.

TSOP PIN CAPACITANCE

Parameter

Symbol

Parameter Description

Input Capacitance

Test Setup

V_IN= 0

Typ

6

Max

7.5

12

Unit

pF

C_IN

C_OUT

C_IN2

Output Capacitance

Control Pin Capacitance

V_OUT= 0

V_IN= 0

8.5

7.5

pF

9

pF

Notes:

1. Sampled, not 100% tested.

2. Test conditions T_A= 25°C, f = 1.0 MHz.

DATA RETENTION

Parameter Description

Test Conditions

150°C

Min

10

Unit

Years

Minimum Pattern Data Retention Time

125°C

20

48

Am29DL640D

December 13, 2005

PHYSICAL DIMENSIONS

FBE063—63-Ball Fine-Pitch Ball Grid Array (FBGA) 12 x 11 mm package

xFBE 063

Dwg rev AF; 10/99

December 13, 2005

Am29DL640D

49

PHYSICAL DIMENSIONS

TS 048—48-Pin Standard TSOP

Dwg rev AA; 10/99

50

Am29DL640D

December 13, 2005

REVISION SUMMARY

Revision A (March 5, 2001)

Revision B+2 (October 11, 2001)

Initial release.

Connection Diagrams, Ordering Information,

Physical Dimensions

Revision A+1 (March 9, 2001)

Added 64-ball Fortified BGA package information.

Ordering Information

Revision B+3 (November 5, 2001)

Corrected FBGA package marking to include “V” des-

ignation. Deleted “0” from 120 ns package marking.

Global

Removed Preliminary designation from document.

Revision B (August 10, 2001)

Ordering Information

Global

Corrected BGA part numbers and markings.

Replaced the phrase “outermost 8 Kb sectors” with the

actual sector names (sectors 0, 1, 140, and 141) for

greater clarity. Changed data sheet status from “Ad-

vance Information” to “Preliminary”.

Distinctive Characteristics

Corrected accelerated programming specification.

Block Diagram

Device Bus Operations

Corrected address bus callout from A20 to A21.

Added Table 3, Bank Address.

Factory Locked: SecSi Sector Programmed and

Protected At the Factory

Table 10, Device Geometry Definition

Added definition for address 4Fh.

Deleted references to top and bottom boot devices.

Revision B+4 (April 15, 2002)

Customer Lockable: SecSi Sector NOT

Programmed or Protected At the Factory

Ordering Information

Deleted reference to 64 Kbyte SecSi Sector.

Added P designator to package marking for Fortified

BGA package.

Table 4, SecSi™ Sector Addresses

Revision B+5 (August 19, 2002)

Distinctive Characteristics

Added table.

Table 5, Am29DL640D Autoselect Codes, (High

Voltage Method)

Corrected erase cycles.b

Deleted rows for byte mode.

Connection Diagram

Table 7, WP#/ACC Modes

Changed all references to RFU to NC.

Added table for clarity.

Table 2. Am29DL640D Sector Architecture

Revision B+1 (August 30, 2001)

Corrected SA20 and SA21 sector’s, sector address to

0001101xxx and 0001110xxx.

Autoselect Command Sequence

Deleted explanatory bullets and included references to

the appropriate tables for autoselect functions.

Corrected SA35 sector’s, sector address to

0011100xxx.

Table 12, Am29DL640D Command Definitions

DC Characteristics Table

Added second and third read cycle information for the

autoselect device ID command sequence.

Deleted the I_ACCspecification row.

Command Definitions

AC Characteristics: Erase and Program Operations

Modified the last sentence in the first paragraph.

Changed t_BUSYspecification from minimum to

maximum.

CFI

Changed the text at the end of the last sentence in the

third paragraph to: “reading array data.”

December 13, 2005

Am29DL640D

51

Noted that the SecSi Sector, autoselect, and CFI

functions are unavailable when a program or erase

operation is in progress.

Revision C (January 10, 2003)

Package Options

Removed the 64-ball Fortified BGA package and

pinout.

Common Flash Memory Interface (CFI)

Changed CFI website address.

Sector/Sector Block Protection and Unprotection

Revision C+1 (October 7, 2004)

Change wording of first sentence of third paragraph.

Cover Sheet and Title Page

Customer Lockable: SecSi Sector NOT

Programmed or Protected at the factory.

Added notation to superseding documents.

Added second bullet, SecSi sector-protect verify text

and figure 3.

Revision C+2 (January 11, 2005)

Ordering Information and Valid Combinations

Added Pb-free package options.

SecSi Sector Flash Memory Region, and Enter

SecSi Sector/Exit SecSi Sector Command

Sequence

Updated cross-references.

Changed SecSi™ to Selected Silicon

Removed Sales Office Listing

Noted that the ACC function and unlock bypass modes

are not available when the SecSi sector is enabled.

Byte/Word Program Command Sequence, Sector

Erase Command Sequence, and Chip Erase Com-

mand Sequence

Revision C+3 (December 13, 2005)

This product has been retired and is not available for

designs. Availability of this document is retained for

reference and historical purposes only.

Colophon

The products described in this document are designed, developed and manufactured as contemplated for general use, including without limita-

tion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as con-

templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the

public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,

aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for

any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to

you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor de-

vices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design mea-

sures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating

conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign

Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au-

thorization by the respective government entity will be required for export of those products.

Trademarks

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

ExpressFlash is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

52

Am29DL640D

December 13, 2005


型号：	AM29DL640D35WHE
厂家：	AMD
描述：	64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory 64兆位（8M ×8位/ 4米x 16位） CMOS 3.0伏只，同步读/写闪存闪存
文件：	总54页 (文件大小：1063K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AM29DL640D35WHE [AMD]

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