AM29DL800BT70WBF [AMD]
8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory; 8兆位( 1一M× 8位/ 512的K× 16位) CMOS 3.0伏只,同时操作闪存型号: | AM29DL800BT70WBF |
厂家: | AMD |
描述: | 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory |
文件: | 总46页 (文件大小:1480K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Am29DL800B
Data Sheet
The following document contains information on Spansion memory products. Although the document
is marked with the name of the company that originally developed the specification, Spansion will
continue to offer these products to existing customers.
Continuity of Specifications
There is no change to this data sheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal data sheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
Spansion continues to support existing part numbers beginning with “Am” and “MBM”. To order these
products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local sales office for additional information about Spansion memory solutions.
Publication Number 21519 Revision C Amendment 4 Issue Date December 4, 2006
Publication Number 21519 Revision C Amendment 4 Issue Date December 4, 2006
THIS PAGE LEFT INTENTIONALLY BLANK.
DATA SHEET
Am29DL800B
8 Megabit (1 M x 8-Bit/512 K x 16-Bit)
CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory
DISTINCTIVE CHARACTERISTICS
■ Simultaneous Read/Write operations
■ Sector protection
— Host system can program or erase in one bank,
then immediately and simultaneously read from
the other bank
— Hardware method of locking a sector to prevent
any program or erase operation within that sector
— Sectors can be locked in-system or via
programming equipment
— Zero latency between read and write operations
— Read-while-erase
— Temporary Sector Unprotect feature allows code
changes in previously locked sectors
— Read-while-program
■ Top or bottom boot block configurations
■ Single power supply operation
available
— Full voltage range: 2.7 to 3.6 volt read and write
operations for battery-powered applications
■ Embedded Algorithms
— Embedded Erase algorithm automatically
pre-programs and erases sectors or entire chip
■ Manufactured on 0.35 µm process technology
— Compatible with 0.5 µm Am29DL800 device
— Embedded Program algorithm automatically
programs and verifies data at specified address
■ High performance
— Access times as fast as 70 ns
■ Minimum 1,000,000 program/erase cycles
■ Low current consumption (typical values
guaranteed per sector
at 5 MHz)
■ Package options
— 44-pin SO
— 7 mA active read current
— 21 mA active read-while-program or read-while-
erase current
— 48-pin TSOP
— 48-ball FBGA
— 17 mA active program-while-erase-suspended current
— 200 nA in standby mode
■ Compatible with JEDEC standards
— Pinout and software compatible with
single-power-supply flash standard
— 200 nA in automatic sleep mode
— Standard t chip enable access time applies to
CE
— Superior inadvertent write protection
transition from automatic sleep mode to active mode
■ Data# Polling and Toggle Bits
■ Flexible sector architecture
— Provides a software method of detecting
program or erase cycle completion
— Two 16 Kword, two 8 Kword, four 4 Kword, and
fourteen 32 Kword sectors in word mode
— Two 32 Kbyte, two 16 Kbyte, four 8 Kbyte, and
fourteen 64 Kbyte sectors in byte mode
■ Ready/Busy# output (RY/BY#)
— Hardware method for detecting program or
erase cycle completion
— Any combination of sectors can be erased
— Supports full chip erase
■ Erase Suspend/Erase Resume
■ Unlock Bypass Program Command
— Suspends or resumes erasing sectors to allow
reading and programming in other sectors
— Reduces overall programming time when
issuing multiple program command sequences
— No need to suspend if sector is in the other bank
■ Hardware reset pin (RESET#)
— Hardware method of resetting the device to
reading array data
Publication# 21519 Rev: C Amendment: 4
Issue Date: December 4, 2006
D A T A S H E E T
GENERAL DESCRIPTION
The Am29DL800B is an 8 Mbit, 3.0 volt-only flash
memory device, organized as 524,288 words or
1,048,576 bytes. The device is offered in 44-pin SO,
48-pin TSOP, and 48-ball FBGA packages. The word-
wide (x16) data appears on DQ0–DQ15; the byte-wide
(x8) data appears on DQ0–DQ7. This device requires
proper cell margin. The Unlock Bypass mode facili-
tates faster programming times by requiring only two
write cycles to program data instead of four.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the Embedded Erase
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
only a single 3.0 volt V supply to perform read, pro-
CC
gram, and erase operations. A standard EPROM
programmer can also be used to program and erase
the device.
This device is manufactured using AMD’s 0.35 µm pro-
cess technology, and offers all the features and
benefits of the Am29DL800, which was manufactured
using a 0.5 µm technology.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle has
been completed, the device automatically returns to
reading array data.
The standard device offers access times of 70, 90, and
120 ns, allowing high-speed microprocessors to oper-
ate without wait states. Standard control pins—chip
enable (CE#), write enable (WE#), and output enable
(OE#)—control read and write operations, and avoid
bus contention issues.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
The device requires only a single 3.0 volt power sup-
ply for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
Hardware data protection measures include a low
VCC detector that automatically inhibits write operations
during power transitions. The hardware sector protec-
tion feature disables both program and erase operations
in any combination of the sectors of memory. This can be
achieved in-system or via programming equipment.
Simultaneous Read/Write Operations with
Zero Latency
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector within that bank that is
not selected for erasure. True background erase can
thus be achieved. There is no need to suspend the
erase operation if the read data is in the other bank.
The Simultaneous Read/Write architecture provides si-
multaneous operation by dividing the memory space
into two banks. Bank 1 contains eight boot/parameter
sectors, and Bank 2 consists of fourteen larger, code
sectors of uniform size. The device can improve overall
system performance by allowing a host system to pro-
gram or erase in one bank, then immediately and
simultaneously read from the other bank, with zero la-
tency. This releases the system from waiting for the
completion of program or erase operations.
The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device to reading array data, enabling the sys-
tem microprocessor to read the boot-up firmware from
the Flash memory.
Am29DL800B Features
The device offers complete compatibility with the
JEDEC single-power-supply Flash command set
standard. Commands are written to the command reg-
ister using standard microprocessor write timings.
Register contents serve as input to an internal state
machine that controls the erase and programming cir-
cuitry. Write cycles also internally latch addresses and
data needed for the programming and erase opera-
tions. Reading data out of the device is similar to
reading from other Flash or EPROM devices.
The device offers two power-saving features. When ad-
dresses have been stable for a specified amount of
time, the device enters the automatic sleep mode.
The system can also place the device into the standby
mode. Power consumption is greatly reduced in both
these modes.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability, and cost
effectiveness. The device electrically erases all bits
within a sector simultaneously via Fowler-Nordheim
tunneling. The bytes are programmed one byte or word
at a time using hot electron injection.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
2
Am29DL800B
21519C4 December 4, 2006
D A T A S H E E T
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5
Special Handling Instructions for FBGA Package .................... 6
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .9
Table 1. Am29DL800B Device Bus Operations ................................9
Word/Byte Configuration .......................................................... 9
Requirements for Reading Array Data ..................................... 9
Writing Commands/Command Sequences .............................. 9
Simultaneous Read/Write Operations with Zero Latency ....... 10
Standby Mode ........................................................................ 10
Automatic Sleep Mode ........................................................... 10
RESET#: Hardware Reset Pin ............................................... 11
Output Disable Mode .............................................................. 11
Table 2. Am29DL800BT Top Boot Sector Architecture ..................12
Table 3. Am29DL800BB Bottom Boot Sector Architecture .............13
Autoselect Mode ..................................................................... 13
Table 4. Am29DL800B Autoselect Codes (High Voltage Method) ..14
Sector Protection/Unprotection ............................................... 14
Temporary Sector Unprotect .................................................. 14
Figure 1. Temporary Sector Unprotect Operation........................... 14
Figure 2. In-System Sector Protect/Unprotect Algorithms .............. 15
Hardware Data Protection ...................................................... 16
Command Definitions . . . . . . . . . . . . . . . . . . . . . 16
Reading Array Data ................................................................ 16
Reset Command ..................................................................... 16
Autoselect Command Sequence ............................................ 16
Byte/Word Program Command Sequence ............................. 17
Figure 3. Program Operation .......................................................... 18
Chip Erase Command Sequence ........................................... 18
Sector Erase Command Sequence ........................................ 18
Erase Suspend/Erase Resume Commands ........................... 19
Figure 4. Erase Operation............................................................... 19
Command Definitions ............................................................. 20
Table 5. Am29DL800B Command Definitions ................................20
Write Operation Status . . . . . . . . . . . . . . . . . . . . .21
DQ7: Data# Polling ................................................................. 21
Figure 5. Data# Polling Algorithm ................................................... 21
RY/BY#: Ready/Busy# ........................................................... 22
DQ6: Toggle Bit I .................................................................... 22
DQ2: Toggle Bit II ................................................................... 22
Reading Toggle Bits DQ6/DQ2 ............................................... 22
Figure 6. Toggle Bit Algorithm........................................................ 23
DQ5: Exceeded Timing Limits ................................................ 23
DQ3: Sector Erase Timer ....................................................... 23
Table 6. Write Operation Status ......................................................24
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 25
Figure 7. Maximum Negative Overshoot Waveform ..................... 25
Figure 8. Maximum Positive Overshoot Waveform....................... 25
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 25
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 9. ICC1 Current vs. Time (Showing Active and Automatic
Sleep Currents).............................................................................. 27
Figure 10. Typical ICC1 vs. Frequency ........................................... 27
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 11. Test Setup.................................................................... 28
Table 7. Test Specifications ........................................................... 28
Key to Switching Waveforms . . . . . . . . . . . . . . . 28
Figure 12. Input Waveforms and Measurement Levels ................. 28
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 13. Read Operation Timings............................................... 29
Figure 14. Reset Timings............................................................... 30
Figure 15. BYTE# Timings for Read Operations............................ 31
Figure 16. BYTE# Timings for Write Operations............................ 31
Erase and Program Operations .............................................. 32
Figure 17. Program Operation Timings.......................................... 33
Figure 18. Chip/Sector Erase Operation Timings .......................... 33
Figure 19. Back-to-Back Read/Write Cycle Timings...................... 34
Figure 20. Data# Polling Timings (During Embedded Algorithms). 34
Figure 21. Toggle Bit Timings (During Embedded Algorithms)...... 35
Figure 22. DQ2 vs. DQ6................................................................. 35
Figure 23. Temporary Sector Unprotect Timing Diagram .............. 36
Figure 24. Sector Protect/Unprotect Timing Diagram .................... 36
Alternate CE# Controlled Erase/Program Operations ............ 37
Figure 25. Alternate CE# Controlled Erase/Program
Operation Timings.......................................................................... 38
Erase and Programming Performance . . . . . . . 39
Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 39
TSOP and SO Pin Capacitance . . . . . . . . . . . . . . 39
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 40
TS 048—48-Pin Standard TSOP ............................................ 40
FBB048 —48-Ball Fine-Pitch Ball Grid Array (FBGA),
6 x 9 mm package .................................................................. 41
SO 044—44-Pin Small Outline .............................................. 42
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 43
December 4, 2006 21519C4
Am29DL800B
3
D A T A S H E E T
PRODUCT SELECTOR GUIDE
Family Part Number
Am29DL800B
Speed Option
Full Voltage Range: V
= 2.7 – 3.6 V
70
70
70
30
90
90
90
35
120
120
120
50
CC
Max Access Time (ns)
CE# Access (ns)
OE# Access (ns)
Note: See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
OE# BYTE#
V
V
CC
SS
Upper Bank Address
A0–A18
Upper Bank
RY/BY#
X-Decoder
A0–A18
RESET#
STATE
CONTROL
&
COMMAND
REGISTER
Status
WE#
CE#
DQ0–DQ15
Control
BYTE#
DQ0–DQ15
X-Decoder
Lower Bank
A0–A18
Lower Bank Address
OE# BYTE#
4
Am29DL800B
21519C4 December 4, 2006
D A T A S H E E T
CONNECTION DIAGRAMS
A15
A14
A13
A12
A11
A10
A9
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
A8
NC
NC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
WE#
RESET#
NC
Standard TSOP
NC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
December 4, 2006 21519C4
Am29DL800B
5
D A T A S H E E T
CONNECTION DIAGRAMS
RY/BY#
1
2
3
4
5
6
7
8
9
44 RESET#
43 WE#
42 A8
A18
A17
A7
41 A9
A6
40 A10
A5
39 A11
A4
38 A12
A3
37 A13
A2
36 A14
A1 10
A0 11
35 A15
34 A16
SO
CE# 12
VSS 13
33 BYTE#
32 VSS
OE# 14
DQ0 15
DQ8 16
DQ1 17
DQ9 18
DQ2 19
DQ10 20
DQ3 21
DQ11 22
31 DQ15/A-1
30 DQ7
29 DQ14
28 DQ6
27 DQ13
26 DQ5
25 DQ12
24 DQ4
23 VCC
48-Ball FBGA
Top View, Balls Facing Down
A6
B6
C6
D6
E6
F6
G6
H6
A13
A12
A14
A15
A16
BYTE# DQ15/A-1 VSS
A5
A9
B5
A8
C5
D5
E5
F5
G5
H5
A10
A11
DQ7
DQ14
DQ13
DQ6
A4
B4
C4
D4
E4
F4
G4
H4
WE# RESET#
NC
NC
DQ5
DQ12
VCC
DQ4
A3
B3
C3
D3
E3
F3
G3
H3
RY/BY#
NC
A18
NC
DQ2
DQ10
DQ11
DQ3
A2
A7
B2
C2
A6
D2
A5
E2
F2
G2
H2
A17
DQ0
DQ8
DQ9
DQ1
A1
A3
B1
A4
C1
A2
D1
A1
E1
A0
F1
G1
H1
CE#
OE#
VSS
Flash memory devices in FBGA packages may be
damaged if exposed to ultrasonic cleaning methods.
The package and/or data integrity may be compro-
mised if the package body is exposed to temperatures
above 150°C for prolonged periods of time.
Special Handling Instructions for FBGA
Package
Special handling is required for Flash Memory products
in FBGA packages.
6
Am29DL800B
21519C4 December 4, 2006
D A T A S H E E T
PIN DESCRIPTION
LOGIC SYMBOL
A0-A18
= 19 Addresses
19
DQ0-DQ14= 15 Data Inputs/Outputs
A0–A18
16 or 8
DQ15/A-1 = DQ15 (Data Input/Output, word mode),
A-1 (LSB Address Input, byte mode)
DQ0–DQ15
(A-1)
CE#
= Chip Enable
OE#
= Output Enable
CE#
OE#
WE#
BYTE#
= Write Enable
= Selects 8-bit or 16-bit mode
WE#
RESET# = Hardware Reset Pin, Active Low
RY/BY# = Ready/Busy Output
RESET#
BYTE#
RY/BY#
V
= 3.0 volt-only single power supply
(see Product Selector Guide for speed
options and voltage supply tolerances)
CC
V
= Device Ground
SS
NC
= Pin Not Connected Internally
December 4, 2006 21519C4
Am29DL800B
7
D A T A S H E E T
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combi-
nation) is formed by a combination of the following:
Am29DL800B
T
70
E
I
TEMPERATURE RANGE
C
D
I
=
=
=
=
=
=
Commercial (0°C to +70°C)
Commercial (0°C to +70°C) with Pb-Free package
Industrial (–40°C to +85°C)
Industrial (–40°C to +85°C) with Pb-Free package
Extended (–55°C to +125°C)
F
E
K
Extended (–55°C to +125°C) with Pb-Free package
PACKAGE TYPE
E
=
48-Pin Thin Small Outline Package
(TSOP) Standard Pinout (TS 048)
S
=
=
44-Pin Small Outline Package (SO 044)
WB
48-Ball Fine-Pitch Ball Grid Array (FBGA)
0.80 mm pitch, 6 x 9 mm package (FBB048)
SPEED OPTION
See Product Selector Guide and Valid Combinations
BOOT CODE SECTOR ARCHITECTURE
T
B
=
=
Top sector
Bottom sector
DEVICE NUMBER/DESCRIPTION
Am29DL800B
8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS Flash Memory
3.0 Volt-only Read, Program, and Erase
Valid Combinations for TSOP and SO Packages
Valid Combinations for FBGA Packages
Order Number Package Marking
AM29DL800BT70,
AM29DL800BB70
EC, EI, ED, EF
SC, SI, SD, SF
WBC,
AM29DL800BT90,
AM29DL800BB90
AM29DL800BT70,
AM29DL800BB70
WBI, D800BT70V,
WBD, D800BB70V
WBF
C, I,
D, F
EC, EI, EE, ED, EF, EK
SC, SI, SE, SD, SF, SK
AM29DL800BT120,
AM29DL800BB120
AM29DL800BT90,
AM29DL800BB90
WBC, D800BT90V,
WBI, D800BB90V
WBE,
Valid Combinations
C, I, E,
D, F, K
WBD,
WBF,
WBK
Valid Combinations list configurations planned to be sup-
ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
AM29DL800BT120,
AM29DL800BB120
D800BT12V,
D800BB12V
8
Am29DL800B
21519C4 December 4, 2006
D A T A S H E E T
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register it-
self does not occupy any addressable memory
location. The register is a latch used to store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the in-
puts and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Table 1. Am29DL800B Device Bus Operations
DQ8–DQ15
BYTE#
Addresses
(Note 1)
DQ0– BYTE#
Operation
CE# OE# WE# RESET#
DQ7
DOUT
DIN
= VIH
DOUT
DIN
= VIL
Read
Write
L
L
L
H
L
H
H
AIN
AIN
DQ8–DQ14 = High-Z,
DQ15 = A-1
H
VCC
0.3 V
±
VCC ±
0.3 V
Standby
X
X
X
High-Z High-Z
High-Z
Output Disable
Reset
L
H
X
H
X
H
L
X
X
High-Z High-Z
High-Z High-Z
High-Z
High-Z
X
Sector Address,
A6 = L, A1 = H,
A0 = L
Sector Protect (Note 2)
L
H
L
VID
DIN
X
X
Sector Address,
A6 = H, A1 = H,
A0 = L
Sector Unprotect (Note 2)
L
H
X
L
VID
VID
DIN
DIN
X
X
Temporary Sector Unprotect
X
X
AIN
DIN
High-Z
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Addresses are A18:A0 in word mode (BYTE# = VIH), A18:A-1 in byte mode (BYTE# = VIL).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector
Protection/Unprotection” section.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
ensures that no spurious alteration of the memory con-
pins operate in the byte or word configuration. If the
tent occurs during the power transition. No command is
BYTE# pin is set at logic ‘1’, the device is in word con-
necessary in this mode to obtain array data. Standard
figuration, DQ0-15 are active and controlled by CE#
microprocessor read cycles that assert valid addresses
and OE# .
on the device address inputs produce valid data on the
device data outputs. Each bank remains enabled for
read access until the command register contents are
altered.
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are ac-
tive and controlled by CE# and OE#. The data I/O pins
DQ8–DQ14 are tri-stated, and the DQ15 pin is used as
an input for the LSB (A-1) address function.
See “Reading Array Data” for more information. Refer
to the AC Read-Only Operations table for timing speci-
fications and to Figure 13 for the timing diagram. I
in the DC Characteristics table represents the active
current specification for reading array data.
CC1
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V . CE# is the power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE# should
IL
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
remain at V . The BYTE# pin determines whether the
IH
device outputs array data in words or bytes.
December 4, 2006 21519C4
Am29DL800B
9
D A T A S H E E T
sectors of memory), the system must drive WE# and
CE# to V , and OE# to V .
pended to read from or program to another location
within the same bank (except the sector being erased).
Figure 19 shows how read and write cycles may be ini-
tiated for simultaneous operation with zero latency.
IL
IH
For program operations, the BYTE# pin determines
whether the device accepts program data in bytes or
words. Refer to “Word/Byte Configuration” for more
information.
I
and I
in the DC Characteristics table represent
CC6
CC7
the current specifications for read-while-program and
read-while-erase, respectively.
The device features an Unlock Bypass mode to facili-
tate faster programming. Once a bank enters the
Unlock Bypass mode, only two write cycles are re-
quired to program a word or byte, instead of four. The
“Byte/Word Program Command Sequence” section
has details on programming data to the device using
both standard and Unlock Bypass command
sequences.
Standby Mode
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, inde-
pendent of the OE# input.
The device enters the CMOS standby mode when the
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Tables 2 and 3 indicate the
address space that each sector occupies. The device
address space is divided into two banks: Bank 1 con-
tains the boot/parameter sectors, and Bank 2 contains
the larger, code sectors of uniform size. A “bank ad-
dress” is the address bits required to uniquely select a
bank. Similarly, a “sector address” is the address bits
required to uniquely select a sector.
CE# and RESET# pins are both held at V ± 0.3 V.
CC
(Note that this is a more restricted voltage range than
V .) If CE# and RESET# are held at V , but not within
IH
IH
V
± 0.3 V, the device will be in the standby mode, but
CC
the standby current will be greater. The device requires
standard access time (t ) for read access when the
CE
device is in either of these standby modes, before it is
ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
If the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the Autoselect Mode and Autoselect
Command Sequence sections for more information.
I
in the DC Characteristics table represents the
CC3
standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device en-
ergy consumption. The device automatically enables
I
in the DC Characteristics table represents the ac-
CC2
tive current specification for the write mode. The AC
Characteristics section contains timing specification ta-
bles and timing diagrams for write operations.
this mode when addresses remain stable for t
+ 30
ACC
ns. The automatic sleep mode is independent of the
CE#, WE#, and OE# control signals. Standard address
access timings provide new data when addresses are
changed. While in sleep mode, output data is latched
Simultaneous Read/Write Operations with
Zero Latency
This device is capable of reading data from one bank of
memory while programming or erasing in the other
bank of memory. An erase operation may also be sus-
and always available to the system. I
in the DC
CC4
Characteristics table represents the automatic sleep
mode current specification.
10
Am29DL800B
21519C4 December 4, 2006
D A T A S H E E T
memory, enabling the system to read the boot-up firm-
RESET#: Hardware Reset Pin
ware from the Flash memory.
The RESET# pin provides a hardware method of reset-
ting the device to reading array data. When the
If RESET# is asserted during a program or erase oper-
ation, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
RESET# pin is driven low for at least a period of t , the
RP
device immediately terminates any operation in
progress, tristates all output pins, and ignores all read/
write commands for the duration of the RESET# pulse.
The device also resets the internal state machine to
reading array data. The operation that was interrupted
should be reinitiated once the device is ready to accept
another command sequence, to ensure data integrity.
time of t
(during Embedded Algorithms). The
READY
system can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of t
(not during Embedded Algo-
READY
rithms). The system can read data t
after the
RH
Current is reduced for the duration of the RESET#
RESET# pin returns to V .
IH
pulse. When RESET# is held at V
0.3 V, the device
SS
Refer to the AC Characteristics tables for RESET# pa-
rameters and to Figure 14 for the timing diagram.
draws CMOS standby current (I
). If RESET# is held
CC4
at V but not within V
0.3 V, the standby current will
IL
SS
be greater.
Output Disable Mode
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
When the OE# input is at V , output from the device is
IH
disabled. The output pins are placed in the high imped-
ance state.
December 4, 2006 21519C4
Am29DL800B
11
D A T A S H E E T
Table 2. Am29DL800BT Top Boot Sector Architecture
Sector Address
Sector Size
Bank Address
(Kbytes/
Kwords)
(x8)
(x16)
Address Range
Bank
Sector A18 A17 A16 A15 A14 A13 A12
Address Range
SA0
SA1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
16/8
00000h–0FFFFh
10000h–1FFFFh
20000h–2FFFFh
30000h–3FFFFh
40000h–4FFFFh
50000h–5FFFFh
60000h–6FFFFh
70000h–7FFFFh
80000h–8FFFFh
90000h–9FFFFh
A0000h–AFFFFh
B0000h–BFFFFh
C0000h–CFFFFh
D0000h–DFFFFh
E0000h–E3FFFh
00000h–07FFFh
08000h–0FFFFh
10000h–17FFFh
18000h–1FFFFh
20000h–27FFFh
28000h–2FFFFh
30000h–37FFFh
38000h–3FFFFh
40000h–47FFFh
48000h–4FFFFh
50000h–57FFFh
58000h–5FFFFh
60000h–67FFFh
68000h–6FFFFh
70000h–71FFFh
SA2
SA3
SA4
SA5
SA6
Bank 2
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
0
1
E4000h–E7FFFh,
E8000h–EBFFFh
72000h–73FFFh
74000h–75FFFh
SA15
1
1
1
0
32/16
1
0
SA16
SA17
SA18
SA19
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
8/4
8/4
8/4
8/4
EC000h–EDFFFh
EE000h–EFFFFh
F0000h–F1FFFh
F2000h–F3FFFh
76000h–76FFFh
77000h–77FFFh
78000h–78FFFh
79000h–79FFFh
1
1
1
Bank 1
0
0
0
0
0
1
0
1
X
X
X
F4000h–F7FFFh,
F8000h–FBFFFh
7A000h–7BFFFh
7C000h–7DFFFh
SA20
SA21
1
1
1
1
1
1
1
1
32/16
16/8
1
0
1
1
FC000h–FFFFFh
7E000h–7FFFFh
Note: The address range is A18:A-1 if in byte mode (BYTE# = VIL). The address range is A18:A0 if in word mode (BYTE# = VIH).
12
Am29DL800B
21519C4 December 4, 2006
D A T A S H E E T
Table 3. Am29DL800BB Bottom Boot Sector Architecture
Sector Address
Sector Size
Bank Address
(Kbytes/
Kwords)
(x8)
(x16)
Address Range
Bank
Sector A18 A17 A16 A15 A14 A13 A12
Address Range
SA21
SA20
SA19
SA18
SA17
SA16
SA15
SA14
SA13
SA12
SA11
SA10
SA9
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
16/8
F0000h–FFFFFh
E0000h–EFFFFh
D0000h–DFFFFh
C0000h–CFFFFh
B0000h–BFFFFh
A0000h–AFFFFh
90000h–9FFFFh
80000h–8FFFFh
70000h–7FFFFh
60000h–6FFFFh
50000h–5FFFFh
40000h–4FFFFh
30000h–3FFFFh
20000h–2FFFFh
1C000h–1FFFFh
78000h–7FFFFh
70000h–77FFFh
68000h–6FFFFh
60000h–67FFFh
58000h–5FFFFh
50000h–57FFFh
48000h–4FFFFh
40000h–47FFFh
38000h–3FFFFh
30000h–37FFFh
28000h–2FFFFh
20000h–27FFFh
18000h–1FFFFh
10000h–17FFFh
0E000h–0FFFFh
Bank 2
SA8
SA7
1
0
18000h–1BFFFh
14000h–17FFFh
0C000h–0DFFFh
0A000h–0BFFFh
SA6
0
0
0
1
32/16
0
1
SA5
SA4
SA3
SA2
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
8/4
8/4
8/4
8/4
12000h–13FFFh
10000h–11FFFh
0E000h–0FFFFh
0C000h–0DFFFh
09000h–09FFFh
08000h–08FFFh
07000h–07FFFh
06000h–06FFFh
0
0
0
Bank 1
1
1
1
1
1
0
1
0
X
X
X
08000h–0BFFFh,
04000h–07FFFh
04000h–05FFFh,
02000h–03FFFh,
SA1
SA0
0
0
0
0
0
0
0
0
32/16
16/8
0
1
0
0
00000h–03FFFh
00000h–01FFFh
Note: The address range is A18:A-1 if in byte mode (BYTE# = VIL). The address range is A18:A0 if in word mode (BYTE# = VIH).
Table 4. In addition, when verifying sector protection,
the sector address must appear on the appropriate
Autoselect Mode
The autoselect mode provides manufacturer and de-
highest order address bits (see Tables 2 and 3). Table
vice identification, and sector protection verification,
4 shows the remaining address bits that are don’t care.
through identifier codes output on DQ7–DQ0. This
When all necessary bits have been set as required, the
mode is primarily intended for programming equipment
programming equipment may then read the corre-
to automatically match a device to be programmed with
sponding identifier code on DQ7-DQ0.
its corresponding programming algorithm. However,
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 5. This method
the autoselect codes can also be accessed in-system
through the command register.
When using programming equipment, the autoselect
does not require V . Refer to the Autoselect Command
ID
mode requires V (11.5 V to 12.5 V) on address pin
ID
Sequence section for more information.
A9. Address pins A6, A1, and A0 must be as shown in
December 4, 2006 21519C4
Am29DL800B
13
D A T A S H E E T
Table 4. Am29DL800B Autoselect Codes (High Voltage Method)
A18 A11
to to
Mode CE# OE# WE# A12 A10 A9
A8
to
A7
A5
to
A2
DQ8
to
A0 DQ15
DQ7
to
DQ0
Description
A6
A1
Manufacturer ID: AMD
L
L
L
L
H
H
BA
X
VID
X
X
L
X
X
L
L
X
01h
4Ah
Device ID:
Am29DL800B
(Top Boot Block)
Word
Byte
Word
Byte
22h
BA
X
VID
L
L
L
L
H
L
L
L
L
L
L
H
H
H
X
22h
X
4Ah
CBh
CBh
Device ID:
Am29DL800B
(Bottom Boot Block)
BA
SA
X
X
VID
X
X
X
X
H
L
01h
(protected)
X
X
Sector Protection Verification
L
L
H
VID
L
H
00h
(unprotected)
Note: L = Logic Low = VIL, H = Logic High = VIH, BA = Bank Address, SA = Sector Address, X = Don’t care.
SET# pin to V (11.5 V – 12.5 V). During this mode,
formerly protected sectors can be programmed or
Sector Protection/Unprotection
ID
The hardware sector protection feature disables both
program and erase operations in any sector. The hard-
ware sector unprotection feature re-enables both
program and erase operations in previously protected
sectors. Sector protection/unprotection can be imple-
mented via two methods.
erased by selecting the sector addresses. Once V is
ID
removed from the RESET# pin, all the previously pro-
tected sectors are protected again. Figure 1 shows the
algorithm, and Figure 23 shows the timing diagrams,
for this feature.
The primary method requires V on the RESET# pin
ID
only, and can be implemented either in-system or via
programming equipment. Figure 2 shows the algo-
rithms and Figure 24 shows the timing diagram. This
method uses standard microprocessor bus cycle tim-
ing. For sector unprotect, all unprotected sectors must
first be protected prior to the first sector unprotect write
cycle.
START
RESET# = VID
(Note 1)
Perform Erase or
Program Operations
The alternate method intended only for programming
equipment requires V on address pin A9 and OE#.
ID
This method is compatible with programmer routines
written for earlier 3.0 volt-only AMD flash devices. Pub-
lication number 21467 contains further details; contact
an AMD representative to request a copy.
RESET# = VIH
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.
Temporary Sector
Unprotect Completed
(Note 2)
It is possible to determine whether a sector is protected
or unprotected. See the Autoselect Mode section for
details.
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once
again.
Temporary Sector Unprotect
This feature allows temporary unprotection of previ-
ously protected sectors to change data in-system. The
Sector Unprotect mode is activated by setting the RE-
Figure 1. Temporary Sector Unprotect Operation
14
Am29DL800B
21519C4 December 4, 2006
D A T A S H E E T
START
START
Protect all sectors:
The indicated portion
of the sector protect
algorithm must be
performed for all
PLSCNT = 1
PLSCNT = 1
RESET# = VID
RESET# = VID
unprotected sectors
prior to issuing the
first sector
Wait 1 μs
Wait 1 μs
unprotect address
No
First Write
Cycle = 60h?
No
First Write
Cycle = 60h?
Temporary Sector
Unprotect Mode
Temporary Sector
Unprotect Mode
Yes
Yes
Set up sector
address
No
All sectors
protected?
Sector Protect:
Write 60h to sector
address with
A6 = 0, A1 = 1,
A0 = 0
Yes
Set up first sector
address
Sector Unprotect:
Wait 150 µs
Write 60h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Verify Sector
Protect: Write 40h
to sector address
with A6 = 0,
Reset
PLSCNT = 1
Increment
PLSCNT
Wait 15 ms
A1 = 1, A0 = 0
Verify Sector
Unprotect: Write
40h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Read from
sector address
with A6 = 0,
A1 = 1, A0 = 0
Increment
PLSCNT
No
No
PLSCNT
= 25?
Read from
sector address
with A6 = 1,
Data = 01h?
Yes
A1 = 1, A0 = 0
No
Yes
Set up
next sector
address
Yes
No
PLSCNT
= 1000?
Protect another
sector?
Data = 00h?
Yes
Device failed
No
Yes
Remove VID
from RESET#
No
Last sector
verified?
Device failed
Write reset
command
Yes
Remove VID
Sector Unprotect
Algorithm
from RESET#
Sector Protect
Algorithm
Sector Protect
complete
Write reset
command
Sector Unprotect
complete
Figure 2. In-System Sector Protect/Unprotect Algorithms
Am29DL800B
December 4, 2006 21519C4
15
D A T A S H E E T
prevent unintentional writes when V
is greater than
Hardware Data Protection
CC
V
.
LKO
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 5 for com-
mand definitions). In addition, the following hardware
data protection measures prevent accidental erasure
or programming, which might otherwise be caused by
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
spurious system level signals during V power-up and
CC
Write cycles are inhibited by holding any one of OE# =
power-down transitions, or from system noise.
V , CE# = V or WE# = V . To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
IL
IH
IH
Low V
Write Inhibit
CC
When V
is less than V
, the device does not ac-
LKO
CC
cept any write cycles. This protects data during V
CC
Power-Up Write Inhibit
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets to reading array data. Subsequent writes
If WE# = CE# = V and OE# = V during power up, the
IL
IH
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
are ignored until V is greater than V
. The system
CC
LKO
must provide the proper signals to the control pins to
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates device
operations. Table 5 defines the valid register command
sequences. Writing incorrect address and data val-
ues or writing them in the improper sequence resets
the device to reading array data.
Reset Command
Writing the reset command resets the banks to the
read or erase-suspend-read mode. Address bits are
don’t cares for this command.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the bank to which the sys-
tem was writing to reading array data. Once erasure
begins, however, the device ignores reset commands
until the operation is complete.
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the AC
Characteristics section.
The reset command may be written between the se-
quence cycles in a program command sequence
before programming begins. This resets the bank to
which the system was writing to the reading array data.
If the program command sequence is written to a bank
that is in the Erase Suspend mode, writing the reset
command returns that bank to the erase-suspend-read
mode. Once programming begins, however, the device
ignores reset commands until the operation is
complete.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. Each bank is ready to read array data
after completing an Embedded Program or Embedded
Erase algorithm.
After the device accepts an Erase Suspend command,
the corresponding bank enters the erase-suspend-
read mode, after which the system can read data from
any non-erase-suspended sector within the same
bank. After completing a programming operation in the
Erase Suspend mode, the system may once again
read array data with the same exception. See the Erase
Suspend/Erase Resume Commands section for more
information.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must
be written to return to reading array data. If a bank en-
tered the autoselect mode while in the Erase Suspend
mode, writing the reset command returns that bank to
the erase-suspend-read mode.
The system must issue the reset command to return a
bank to the read (or erase-suspend-read) mode if DQ5
goes high during an active program or erase operation,
or if the bank is in the autoselect mode. See the next
section, Reset Command, for more information.
If DQ5 goes high during a program or erase operation,
writing the reset command returns the banks to reading
array data (or erase-suspend-read mode if that bank
was in Erase Suspend).
See also Requirements for Reading Array Data in the
Device Bus Operations section for more information.
The Read-Only Operations table provides the read pa-
rameters, and Figure 13 shows the timing diagram.
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and devices codes,
16
Am29DL800B
21519C4 December 4, 2006
D A T A S H E E T
and determine whether or not a sector is protected.
When the Embedded Program algorithm is complete,
that bank then returns to reading array data and ad-
dresses are no longer latched. The system can
determine the status of the program operation by using
DQ7, DQ6, or RY/BY#. Note that while the Embedded
Program operation is in progress, the system can read
data from the non-programming bank. Refer to the
Write Operation Status section for information on these
status bits.
Table 5 shows the address and data requirements. This
method is an alternative to that shown in Table 4, which
is intended for PROM programmers and requires V
ID
on address pin A9. The autoselect command sequence
may be written to an address within a bank that is either
in the read or erase-suspend-read mode. The autose-
lect command may not be written while the device is
actively programming or erasing in the other bank.
The autoselect command sequence is initiated by first
writing two unlock cycles. This is followed by a third
write cycle that contains the bank address and the au-
toselect command. The addressed bank then enters
the autoselect mode. The system may read at any ad-
dress within the same bank any number of times
without initiating another autoselect command
sequence:
Any commands written to the device during the Em-
bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program
operation. The program command sequence should be
reinitiated once that bank has returned to reading array
data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from “0” back to a “1.” Attempting to do so may cause
that bank to set DQ5 = 1, or cause the DQ7 and DQ6
status bits to indicate the operation was successful.
However, a succeeding read will show that the data is
still “0.” Only erase operations can convert a “0” to a “1.”
■ A read cycle at address (BA)XX00h (where BA is
the bank address) returns the manufacturer code.
■ A read cycle at address (BA)XX01h in word mode
(or (BA)XX02h in byte mode) returns the device
code.
Unlock Bypass Command Sequence
■ A read cycle to an address containing a sector ad-
dress (SA) within the same bank, and the address
02h on A7–A0 in word mode (or the address 04h on
A6–A-1 in byte mode) returns 01h if the sector is
protected, or 00h if it is unprotected. Refer to Tables
2 and 3 for valid sector addresses.
The unlock bypass feature allows the system to pro-
gram bytes or words to a bank faster than using the
standard program command sequence. The unlock by-
pass command sequence is initiated by first writing two
unlock cycles. This is followed by a third write cycle
containing the unlock bypass command, 20h. That
bank then enters the unlock bypass mode. A two-cycle
unlock bypass program command sequence is all that
is required to program in this mode. The first cycle in
this sequence contains the unlock bypass program
command, A0h; the second cycle contains the program
address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program
command sequence, resulting in faster total program-
ming time. Table 5 shows the requirements for the
command sequence.
The system may continue to read array data from the
other bank while a bank is in the autoselect mode. To
exit the autoselect mode, the system must write the
reset command to return both banks to reading array
data. If a bank enters the autoselect mode while erase
suspended, a reset command returns that bank to the
erase-suspend-read mode. A subsequent Erase Re-
sume command returns the bank to the erase
operation.
Byte/Word Program Command Sequence
The system may program the device by word or byte,
depending on the state of the BYTE# pin. Program-
ming is a four-bus-cycle operation. The program
command sequence is initiated by writing two unlock
write cycles, followed by the program set-up command.
The program address and data are written next, which
in turn initiate the Embedded Program algorithm. The
system is not required to provide further controls or tim-
ings. The device automatically generates the program
pulses and verifies the programmed cell margin. Table
5 shows the address and data requirements for the
byte program command sequence.
During the unlock bypass mode, only the Unlock By-
pass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com-
mand sequence. The first cycle must contain the bank
address and the data 90h. The second cycle need only
contain the data 00h. The bank then returns to reading
array data.
Figure 3 illustrates the algorithm for the program oper-
ation. Refer to the Erase and Program Operations table
in the AC Characteristics section for parameters, and
Figure 17 for timing diagrams.
December 4, 2006 21519C4
Am29DL800B
17
D A T A S H E E T
occurs, the chip erase command sequence should be
reinitiated once that bank has returned to reading array
data, to ensure data integrity.
START
Figure 4 illustrates the algorithm for the erase opera-
tion. Refer to the Erase and Program Operations tables
in the AC Characteristics section for parameters, and
Figure 18 section for timing diagrams.
Write Program
Command Sequence
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two un-
lock cycles, followed by a set-up command. Two
additional unlock cycles are written, and are then fol-
lowed by the address of the sector to be erased, and
the sector erase command. Table 5 shows the address
and data requirements for the sector erase command
sequence.
Data Poll
from System
Embedded
Program
algorithm
in progress
Verify Data?
Yes
No
The device does not require the system to preprogram
prior to erase. The Embedded Erase algorithm auto-
matically programs and verifies the entire memory for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
No
Increment Address
Last Address?
Yes
After the command sequence is written, a sector erase
time-out of 50 µs occurs. During the time-out period,
additional sector addresses and sector erase com-
mands within the bank may be written. Loading the
sector erase buffer may be done in any sequence, and
the number of sectors may be from one sector to all
sectors. The time between these additional cycles must
be less than 50 µs, otherwise the last address and
command may not be accepted, and erasure may be-
gin. It is recommended that processor interrupts be
disabled during this time to ensure all commands are
accepted. The interrupts can be re-enabled after the
last Sector Erase command is written. Any command
other than Sector Erase or Erase Suspend during
the time-out period resets that bank to reading
array data. The system must rewrite the command se-
quence and any additional addresses and commands.
Programming
Completed
Note: See Table 5 for program command sequence.
Figure 3. Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Table 5 shows
the address and data requirements for the chip erase
command sequence.
The system can monitor DQ3 (in the erasing bank) to
determine if the sector erase timer has timed out (See
the section on DQ3: Sector Erase Timer.). The time-out
begins from the rising edge of the final WE# pulse in
the command sequence.
When the Embedded Erase algorithm is complete, the
bank returns to reading array data and addresses are
no longer latched. Note that while the Embedded Erase
operation is in progress, the system can read data from
the non-erasing bank. The system can determine the
status of the erase operation by reading DQ7, DQ6,
DQ2, or RY/BY# in the erasing bank. Refer to the Write
Operation Status section for information on these sta-
tus bits.
When the Embedded Erase algorithm is complete, that
bank returns to reading array data and addresses are
no longer latched. The system can determine the sta-
tus of the erase operation by using DQ7, DQ6, DQ2, or
RY/BY#. Refer to the Write Operation Status section for
information on these status bits.
Any commands written during the chip erase operation
are ignored. However, note that a hardware reset im-
mediately terminates the erase operation. If that
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands
are ignored. However, note that a hardware reset im-
18
Am29DL800B
21519C4 December 4, 2006
D A T A S H E E T
mediately terminates the erase operation. If that
In the erase-suspend-read mode, the system can also
issue the autoselect command sequence. Refer to the
Autoselect Mode and Autoselect Command Sequence
sections for details.
occurs, the sector erase command sequence should
be reinitiated once that bank has returned to reading
array data, to ensure data integrity.
Figure 4 illustrates the algorithm for the erase opera-
tion. Refer to the Erase and Program Operations tables
in the AC Characteristics section for parameters, and
Figure 18 section for timing diagrams.
To resume the sector erase operation, the system must
write the Erase Resume command. The bank address
of the erase-suspended bank is required when writing
this command. Further writes of the Resume command
are ignored. Another Erase Suspend command can be
written after the chip has resumed erasing.
Erase Suspend/Erase Resume Commands
The Erase Suspend command, B0h, allows the system
to interrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. The bank address is required when writing
this command. This command is valid only during the
sector erase operation, including the 50 µs time-out pe-
riod during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program
algorithm.
START
Write Erase
Command Sequence
(Notes 1, 2)
When the Erase Suspend command is written during
the sector erase operation, the device requires a max-
imum of 20 µs to suspend the erase operation.
However, when the Erase Suspend command is written
during the sector erase time-out, the device immedi-
ately terminates the time-out period and suspends the
erase operation.
Data Poll to Erasing
Bank from System
Embedded
Erase
algorithm
in progress
No
After the erase operation has been suspended, the
bank enters the erase-suspend-read mode. The sys-
tem can read data from or program data to any sector
not selected for erasure. (The device “erase suspends”
all sectors selected for erasure.) Reading at any ad-
dress within erase-suspended sectors produces status
information on DQ7–DQ0. The system can use DQ7,
or DQ6 and DQ2 together, to determine if a sector is
actively erasing or is erase-suspended. Refer to the
Write Operation Status section for information on these
status bits.
Data = FFh?
Yes
Erasure Completed
After an erase-suspended program operation is com-
plete, the bank returns to the erase-suspend-read
mode. The system can determine the status of the pro-
gram operation using the DQ7 or DQ6 status bits, just
as in the standard Byte Program operation. Refer to the
Write Operation Status section for more information.
Notes:
1. See Table 5 for erase command sequence.
2. See the section on DQ3 for information on the sector
erase timer.
Figure 4. Erase Operation
December 4, 2006 21519C4
Am29DL800B
19
D A T A S H E E T
Command Definitions
Table 5. Am29DL800B Command Definitions
Bus Cycles (Notes 2–5)
Command
Sequence
(Note 1)
First
Second
Third
Addr
Fourth
Addr
Fifth
Sixth
Addr Data Addr Data
Data
Data Addr Data Addr Data
Read (Note 6)
Reset (Note 7)
1
1
RA
XXX
555
RD
F0
Word
Manufacturer ID
Byte
2AA
555
2AA
555
2AA
555
(BA)555
(BA)AAA
(BA)555
(BA)AAA
(BA)555
(BA)AAA
4
4
4
AA
AA
AA
55
55
55
90 (BA)X00
01
AAA
555
Word
Byte
Word
Byte
(BA)X01 224A
Device ID,
Top Boot Block
90
90
AAA
555
(BA)X02
4A
(BA)X01 22CB
Device ID,
Bottom Boot Block
AAA
(BA)X02
CB
XX00
XX01
00
(SA)
X02
Word
Byte
555
2AA
555
(BA)555
(BA)AAA
Sector Protect Verify
(Note 9)
4
AA
55
90
(SA)
X04
AAA
01
Word
Byte
Word
Byte
555
AAA
555
AAA
XXX
BA
2AA
555
2AA
555
PA
555
AAA
555
Program
Unlock Bypass
4
3
AA
AA
55
55
A0
20
PA
PD
AAA
Unlock Bypass Program (Note 10)
Unlock Bypass Reset (Note 11)
2
2
A0
90
PD
00
XXX
2AA
555
2AA
555
Word
555
AAA
555
AAA
BA
555
AAA
555
555
AAA
555
2AA
555
2AA
555
555
Chip Erase
Byte
6
6
AA
AA
55
55
80
80
AA
AA
55
55
10
30
AAA
Word
Sector Erase
Byte
SA
AAA
AAA
Erase Suspend (Note 12)
Erase Resume (Note 13)
1
1
B0
30
BA
Legend:
X = Don’t care
PD = Data to be programmed at location PA. Data latches on the
rising edge of WE# or CE# pulse, whichever happens first.
RA = Address of the memory location to be read.
SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A18–A12 uniquely select any sector.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed.
BA = Address of the bank that is being switched to autoselect
mode, is in bypass mode, or is being erased. Address bits A18–A16
select a bank.
Addresses latch on the falling edge of the WE# or CE# pulse,
whichever happens later.
Notes:
8. The fourth cycle of the autoselect command sequence is a read
cycle. The system must provide the bank address to obtain the
manufacturer or device ID information.
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
9. The data is 00h for an unprotected sector and 01h for a
protected sector. See the Autoselect Command Sequence
section for more information.
3. Except when reading array or autoselect data, all bus cycles
are write operations.
4. Data bits DQ15–DQ8 are don’t cares for unlock and command
cycles.
10. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
5. Address bits A18–A11 are don’t cares for unlock and command
cycles, unless bank address (BA) is required.
11. The Unlock Bypass Reset command is required to return to
reading array data when the bank is in the unlock bypass mode.
6. No unlock or command cycles required when bank is in read
mode.
12. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector
erase operation, and requires the bank address.
7. The Reset command is required to return to reading array data
(or to the erase-suspend-read mode if previously in Erase
Suspend) when a bank is in the autoselect mode, or if DQ5 is
goes high (while the bank is providing status information).
13. The Erase Resume command is valid only during the Erase
Suspend mode, and requires the bank address.
20
Am29DL800B
21519C4 December 4, 2006
D A T A S H E E T
WRITE OPERATION STATUS
The device provides several bits to determine the sta-
tus of a write operation in the bank where a program or
erase operation is in progress: DQ2, DQ3, DQ5, DQ6,
DQ7, and RY/BY#. Table 6 and the following subsec-
tions describe the function of these bits. DQ7, RY/BY#,
and DQ6 each offer a method for determining whether
a program or erase operation is complete or in
progress. These three bits are discussed first.
invalid. Valid data on DQ0–DQ7 will appear on succes-
sive read cycles.
Table 6 shows the outputs for Data# Polling on DQ7.
Figure 5 shows the Data# Polling algorithm. Figure 20
in the AC Characteristics section shows the Data# Poll-
ing timing diagram.
DQ7: Data# Polling
START
The Data# Polling bit, DQ7, indicates to the host sys-
tem whether an Embedded Program or Erase
algorithm is in progress or completed, or whether a
bank is in Erase Suspend. Data# Polling is valid after
the rising edge of the final WE# pulse in the command
sequence.
Read DQ7–DQ0
Addr = VA
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum pro-
grammed to DQ7. This DQ7 status also applies to
programming during Erase Suspend. When the Em-
bedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for ap-
proximately 1 µs, then that bank returns to reading
array data.
Yes
DQ7 = Data?
No
No
DQ5 = 1?
Yes
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase al-
gorithm is complete, or if the bank enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
The system must provide an address within any of the
sectors selected for erasure to read valid status infor-
mation on DQ7.
Read DQ7–DQ0
Addr = VA
Yes
DQ7 = Data?
After an erase command sequence is written, if all sec-
tors selected for erasing are protected, Data# Polling
on DQ7 is active for approximately 100 µs, then the
bank returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se-
lected sectors that are protected. However, if the
system reads DQ7 at an address within a protected
sector, the status may not be valid.
No
PASS
FAIL
Notes:
Just prior to the completion of an Embedded Program
or Erase operation, DQ7 may change asynchronously
with DQ0–DQ6 while Output Enable (OE#) is asserted
low. That is, the device may change from providing sta-
tus information to valid data on DQ7. Depending on
when the system samples the DQ7 output, it may read
the status or valid data. Even if the device has com-
pleted the program or erase operation and DQ7 has
valid data, the data outputs on DQ0–DQ6 may be still
1. VA = Valid address for programming. During a sector
erase operation, a valid address is any sector address
within the sector being erased. During chip erase, a valid
address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
Figure 5. Data# Polling Algorithm
December 4, 2006 21519C4
Am29DL800B
21
D A T A S H E E T
Table 6 shows the outputs for Toggle Bit I on DQ6. Fig-
RY/BY#: Ready/Busy#
ure 6 shows the toggle bit algorithm. Figure 21 in the
“AC Characteristics” section shows the toggle bit timing
diagrams. Figure 22 shows the differences between
DQ2 and DQ6 in graphical form. See also the subsec-
tion on DQ2: Toggle Bit II.
The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, sev-
eral RY/BY# pins can be tied together in parallel with a
DQ2: Toggle Bit II
pull-up resistor to V
.
CC
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
If the output is low (Busy), the device is actively erasing
or programming. (This includes programming in the
Erase Suspend mode.) If the output is high (Ready),
the device is ready to read array data, is in the standby
mode, or one of the banks is in the erase-suspend-read
mode.
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. (The system may use either OE# or CE# to
control the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus-
pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era-
sure. Thus, both status bits are required for sector and
mode information. Refer to Table 6 to compare outputs
for DQ2 and DQ6.
Table 6 shows the outputs for RY/BY#.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address within
the programming or erasing bank, and is valid after the
rising edge of the final WE# pulse in the command se-
quence (prior to the program or erase operation), and
during the sector erase time-out.
Figure 6 shows the toggle bit algorithm in flowchart
form, and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the DQ6: Toggle Bit I subsection.
Figure 21 shows the toggle bit timing diagram. Figure
22 shows the differences between DQ2 and DQ6 in
graphical form.
During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address within
the programming or erasing bank cause DQ6 to toggle.
The system may use either OE# or CE# to control the
read cycles. When the operation is complete, DQ6
stops toggling.
Reading Toggle Bits DQ6/DQ2
After an erase command sequence is written, if all sec-
tors selected for erasing are protected, DQ6 toggles for
approximately 100 µs, then returns to reading array
data. If not all selected sectors are protected, the Em-
bedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are
protected.
Refer to Figure 6 for the following discussion. When-
ever the system initially begins reading toggle bit
status, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, the
system would note and store the value of the toggle bit
after the first read. After the second read, the system
would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has com-
pleted the program or erase operation. The system can
read array data on DQ7–DQ0 on the following read
cycle.
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is erase-
suspended. When a bank is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6
toggles. When that bank enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on DQ7: Data# Polling).
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys-
tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is toggling,
since the toggle bit may have stopped toggling just as
DQ5 went high. If the toggle bit is no longer toggling,
the device has successfully completed the program or
erase operation. If it is still toggling, the device did not
completed the operation successfully, and the system
must write the reset command to return to reading
array data.
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 µs after the program
command sequence is written, then returns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
22
Am29DL800B
21519C4 December 4, 2006
D A T A S H E E T
The remaining scenario is that the system initially de-
DQ5: Exceeded Timing Limits
termines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles, de-
termining the status as described in the previous
paragraph. Alternatively, it may choose to perform
other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to de-
termine the status of the operation (top of Figure 6).
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a “1,” indicating that
the program or erase cycle was not successfully
completed.
The device may output a “1” on DQ5 if the system tries
to program a “1” to a location that was previously pro-
grammed to “0.” Only an erase operation can change
a “0” back to a “1.” Under this condition, the device
halts the operation, and when the timing limit has been
exceeded, DQ5 produces a “1”.
START
Under both these conditions, the system must write the
reset command to return to reading array data (or to the
erase-suspend-read mode if a bank was previously in
the erase-suspend-program mode).
Read DQ7–DQ0
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not era-
sure has begun. (The sector erase timer does not apply
to the chip erase command.) If additional sectors are
selected for erasure, the entire time-out also applies
after each additional sector erase command. When the
time-out period is complete, DQ3 switches from a “0” to
a “1”. If the system can guarantee the time between ad-
ditional sector erase commands to be less than 50 µs,
it need not monitor DQ3. See also the Sector Erase
Command Sequence section.
Read DQ7–DQ0
No
Toggle Bit
= Toggle?
Yes
No
DQ5 = 1?
Yes
After the sector erase command is written, the system
should read the status of DQ7 (Data# Polling) or DQ6
(Toggle Bit I) to ensure that the device has accepted
the command sequence, and then read DQ3. If DQ3 is
“1”, the Embedded Erase algorithm has begun; all fur-
ther commands (except Erase Suspend) are ignored
until the erase operation is complete. If DQ3 is “0”, the
device will accept additional sector erase commands.
To ensure the command has been accepted, the sys-
tem software should check the status of DQ3 prior to
and following each subsequent sector erase command.
If DQ3 is high on the second status check, the last com-
mand might not have been accepted.
Read DQ7–DQ0
Twice
Toggle Bit
= Toggle?
No
Table 6 shows the status of DQ3 relative to the other
status bits.
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Note: The system should recheck the toggle bit even if DQ5
= “1” because the toggle bit may stop toggling as DQ5
changes to “1.” See the subsections on DQ6 and DQ2 for
more information.
Figure 6. Toggle Bit Algorithm
December 4, 2006 21519C4
Am29DL800B
23
D A T A S H E E T
Table 6. Write Operation Status
DQ7
DQ5
DQ2
Status
(Note 2)
DQ6
(Note 1)
DQ3
N/A
1
(Note 2)
RY/BY#
Embedded Program Algorithm
Embedded Erase Algorithm
Erase
Erase-Suspend-
Read
DQ7#
0
Toggle
Toggle
0
0
No toggle
Toggle
0
0
Standard
Mode
1
No toggle
0
N/A
Toggle
1
Suspended Sector
Erase
Suspend
Mode
Non-Erase
Suspended Sector
Data
Data
Data
0
Data
N/A
Data
N/A
1
0
Erase-Suspend-Program
DQ7#
Toggle
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
Refer to the section on DQ5 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm
is in progress. The device outputs array data if the system addresses a non-busy bank.
24
Am29DL800B
21519C4 December 4, 2006
D A T A S H E E T
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C
20 ns
20 ns
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . –65°C to +125°C
+0.8 V
–0.5 V
–2.0 V
Voltage with Respect to Ground
V
(Note 1) . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V
CC
A9, OE#,
20 ns
and RESET# (Note 2). . . . . . . . .–0.5 V to +12.5 V
All other pins
(Note 1). . . . . . . . . . . . . . . . . –0.5 V to V +0.5 V
Figure 7. Maximum Negative
Overshoot Waveform
CC
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes:
20 ns
1. Minimum DC voltage on input or I/O pins is –0.5 V. During
voltage transitions, input or I/O pins may overshoot VSS to
–2.0 V for periods of up to 20 ns. Maximum DC voltage on
input or I/O pins is VCC +0.5 V. See Figure 7. During
voltage transitions, input or I/O pins may overshoot to VCC
+2.0 V for periods up to 20 ns. See Figure 8.
VCC
+2.0 V
VCC
+0.5 V
2.0 V
2. Minimum DC input voltage on pins A9, OE#, and RESET#
is –0.5 V. During voltage transitions, A9, OE#, and
RESET# may overshoot VSS to –2.0 V for periods of up to
20 ns. See Figure 7. Maximum DC input voltage on pin A9
is +12.5 V which may overshoot to 14.0 V for periods up
to 20 ns.
20 ns
20 ns
Figure 8. Maximum Positive
Overshoot Waveform
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.
Stresses above those listed under “Absolute Maximum Rat-
ings” may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these
or any other conditions above those indicated in the opera-
tional sections of this data sheet is not implied. Exposure of
the device to absolute maximum rating conditions for ex-
tended periods may affect device reliability.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (T ) . . . . . . . . . . . 0°C to +70°C
A
Industrial (I) Devices
Ambient Temperature (T ) . . . . . . . . . –40°C to +85°C
A
Extended (E) Devices
Ambient Temperature (T ) . . . . . . . . –55°C to +125°C
A
V
Supply Voltages
CC
V
for all devices . . . . . . . . . . . . . . . . .2.7 V to 3.6 V
CC
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
December 4, 2006 21519C4
Am29DL800B
25
D A T A S H E E T
DC CHARACTERISTICS
CMOS Compatible
Parameter
Symbol
Parameter Description
Test Conditions
VIN = VSS to VCC
Min
Typ
Max
±1.0
35
Unit
µA
,
ILI
Input Load Current
VCC = VCC max
ILIT
A9 Input Load Current
Output Leakage Current
VCC = VCC max; A9 = 12.5 V
µA
VOUT = VSS to VCC
,
ILO
±1.0
µA
VCC = VCC max
5 MHz
1 MHz
5 MHz
1 MHz
7
2
7
2
12
4
CE# = VIL, OE# = VIH,
Byte Mode
VCC Active Read Current
(Notes 1, 2)
ICC1
mA
mA
12
4
CE# = VIL, OE# = VIH,
Word Mode
VCC Active Write Current
(Notes 2, 3)
ICC2
CE# = VIL, OE# = VIH, WE# = VIL
15
30
OE# = VIL;
CE#, RESET# = VCC ± 0.3 V
ICC3
ICC4
ICC5
VCC Standby Current (Note 2)
VCC Reset Current (Note 2)
0.2
0.2
0.2
5
5
5
µA
µA
µA
RESET# = VSS ± 0.3 V
Automatic Sleep Mode
(Notes 2, 4)
VIH = VCC ± 0.3 V;
VIL = VSS ± 0.3 V
Byte
21
21
21
21
45
45
45
45
VCC Active Read-While-
Program Current (Notes 1, 2, 5) OE# = VIH
CE# = VIL,
ICC6
mA
mA
Word
Byte
VCC Active Read-While-Erase CE# = VIL,
Current (Notes 1, 2, 5)
ICC7
OE# = VIH
Word
VCC Active Program-While-
Erase-Suspended Current
(Notes 2, 5)
CE# = VIL,
OE# = VIH
ICC8
17
35
mA
VIL
VIH
Input Low Voltage
Input High Voltage
–0.5
0.8
V
V
0.7 x VCC
VCC + 0.3
Voltage for Autoselect and
Temporary Sector Unprotect
VID
VCC = 3.0 V ± 10%
11.5
12.5
0.45
V
VOL
VOH1
VOH2
Output Low Voltage
IOL = 4.0 mA, VCC = VCC min
IOH = –2.0 mA, VCC = VCC min
IOH = –100 µA, VCC = VCC min
V
V
V
0.85 VCC
VCC–0.4
Output High Voltage
Low VCC Lock-Out Voltage
(Note 5)
VLKO
2.3
2.5
V
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.
2. Maximum ICC specifications are tested with VCC = VCCmax.
3. ICC active while Embedded Erase or Embedded Program is in progress.
4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode
current is 200 nA.
5. Not 100% tested.
26
Am29DL800B
21519C4 December 4, 2006
D A T A S H E E T
DC CHARACTERISTICS
Zero-Power Flash
20
15
10
5
0
0
500
1000
1500
2000
2500
3000
3500
4000
Time in ns
Note: Addresses are switching at 1 MHz
Figure 9.
I
Current vs. Time (Showing Active and Automatic Sleep Currents)
CC1
10
8
3.6 V
2.7 V
6
4
2
0
1
2
3
4
5
Frequency in MHz
Note: T = 25 °C
Figure 10. Typical I
vs. Frequency
CC1
December 4, 2006 21519C4
Am29DL800B
27
D A T A S H E E T
TEST CONDITIONS
Table 7. Test Specifications
3.3 V
Test Condition
70
90, 120
Unit
Output Load
1 TTL gate
2.7 kΩ
Device
Under
Test
Output Load Capacitance, CL
30
100
5
pF
(including jig capacitance)
Input Rise and Fall Times
Input Pulse Levels
C
L
ns
V
6.2 kΩ
0.0–3.0
Input timing measurement
reference levels
1.5
1.5
V
V
Output timing measurement
reference levels
Note: Diodes are IN3064 or equivalent
Figure 11. Test Setup
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
3.0 V
0.0 V
1.5 V
1.5 V
Input
Measurement Level
Output
Figure 12. Input Waveforms and Measurement Levels
28
Am29DL800B
21519C4 December 4, 2006
D A T A S H E E T
AC CHARACTERISTICS
Read-Only Operations
Parameter
Speed Options
JEDEC
tAVAV
Std Description
Test Setup
70
70
70
70
30
25
25
90
90
90
90
35
30
30
120
120
120
120
50
Unit
ns
tRC
Read Cycle Time (Note 1)
Min
CE#, OE# = VIL Max
tAVQV
tELQV
tGLQV
tEHQZ
tGHQZ
tACC Address to Output Delay
ns
tCE
tOE
tDF
tDF
Chip Enable to Output Delay
OE# = VIL
Max
Max
Max
Max
ns
Output Enable to Output Delay
ns
Chip Enable to Output High Z (Note 1)
Output Enable to Output High Z (Note 1)
30
ns
30
ns
Output Hold Time From Addresses, CE# or
OE#, Whichever Occurs First
tAXQX
tOH
Min
Min
Min
0
0
ns
ns
ns
Read
Output Enable Hold
Time (Note 1)
tOEH
Toggle and
10
Data# Polling
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 7 for test specifications.
tRC
Addresses Stable
tACC
Addresses
CE#
tRH
tRH
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0 V
Figure 13. Read Operation Timings
December 4, 2006 21519C4
Am29DL800B
29
D A T A S H E E T
AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
JEDEC
Std
Description
All Speed Options
Unit
RESET# Pin Low (During Embedded Algorithms)
to Read Mode (See Note)
tReady
Max
Max
20
µs
RESET# Pin Low (NOT During Embedded
Algorithms) to Read Mode (See Note)
tReady
500
ns
tRP
tRH
tRPD
tRB
RESET# Pulse Width
Min
Min
Min
Min
500
50
20
0
ns
ns
µs
ns
Reset High Time Before Read (See Note)
RESET# Low to Standby Mode
RY/BY# Recovery Time
Note: Not 100% tested.
RY/BY#
CE#, OE#
RESET#
tRH
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRP
Figure 14. Reset Timings
30
Am29DL800B
21519C4 December 4, 2006
D A T A S H E E T
AC CHARACTERISTICS
Word/Byte Configuration (BYTE#)
Parameter
JEDEC
Std
tELFL/ ELFH
tFLQZ
tFHQV
Description
70
90
5
120
Unit
ns
t
CE# to BYTE# Switching Low or High
BYTE# Switching Low to Output HIGH Z
BYTE# Switching High to Output Active
Max
Max
Min
25
70
30
90
30
ns
120
ns
CE#
OE#
BYTE#
tELFL
Data Output
(DQ0–DQ14)
Data Output
(DQ0–DQ7)
BYTE#
DQ0–DQ14
Switching
from word
to byte
Address
Input
DQ15
Output
mode
DQ15/A-1
tFLQZ
tELFH
BYTE#
BYTE#
Switching
from byte
to word
Data Output
(DQ0–DQ7)
Data Output
(DQ0–DQ14)
DQ0–DQ14
DQ15/A-1
mode
Address
Input
DQ15
Output
tFHQV
Figure 15. BYTE# Timings for Read Operations
CE#
The falling edge of the last WE# signal
WE#
BYTE#
tSET
(tAS
)
tHOLD (tAH
)
Note: Refer to the Erase/Program Operations table for tAS and tAH specifications.
Figure 16. BYTE# Timings for Write Operations
Am29DL800B
December 4, 2006 21519C4
31
D A T A S H E E T
AC CHARACTERISTICS
Erase and Program Operations
Parameter
JEDEC
tAVAV
Std
tWC
tAS
Description
70
90
90
0
120
Unit
ns
Write Cycle Time (Note 1)
Address Setup Time
Min
Min
Min
Min
70
120
tAVWL
ns
tASO
tAH
Address Setup Time to OE# low during toggle bit polling
Address Hold Time
45
45
45
45
50
50
ns
tWLAX
ns
Address Hold Time From CE# or OE# high
during toggle bit polling
tAHT
Min
0
ns
tDVWH
tWHDX
tDS
tDH
Data Setup Time
Data Hold Time
Min
Min
Min
35
20
45
0
50
25
ns
ns
ns
tOEPH Output Enable High during toggle bit polling
20
Read Recovery Time Before Write
tGHWL
tGHWL
Min
0
ns
(OE# High to WE# Low)
tELWL
tWHEH
tWLWH
tWHDL
tCS
tCH
CE# Setup Time
Min
Min
Min
Min
Min
Typ
Typ
Typ
Min
Min
Max
0
0
ns
ns
ns
ns
ns
CE# Hold Time
tWP
Write Pulse Width
35
35
30
0
50
tWPH
tSR/W
Write Pulse Width High
Zero Latency Between Read and Write Operations
Byte
9
tWHWH1
tWHWH2
tWHWH1 Programming Operation (Note 2)
µs
Word
11
0.7
50
0
tWHWH2 Sector Erase Operation (Note 2)
sec
µs
tVCS
tRB
VCC Setup Time (Note 1)
Write Recovery Time from RY/BY#
Program/Erase Valid to RY/BY# Delay
ns
tBUSY
90
ns
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
32
Am29DL800B
21519C4 December 4, 2006
D A T A S H E E T
AC CHARACTERISTICS
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tAS
PA
tWC
Addresses
555h
PA
PA
tAH
CE#
OE#
tCH
tWHWH1
tWP
WE#
Data
tWPH
tCS
tDS
tDH
PD
DOUT
A0h
Status
tBUSY
tRB
RY/BY#
VCC
tVCS
Notes:
1. PA = program address, PD = program data, DOUT is the true data at the program address.
2. Illustration shows device in word mode
Figure 17. Program Operation Timings
tAS
SA
tWC
VA
VA
Addresses
CE#
2AAh
555h for chip erase
tAH
tCH
OE#
tWP
WE#
tWPH
tWHWH2
tCS
tDS
tDH
In
Progress
Data
Complete
55h
30h
10 for Chip Erase
tBUSY
tRB
RY/BY#
VCC
tVCS
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data(see “Write Operation Status”).
2. Illustration shows device in word mode.
Figure 18. Chip/Sector Erase Operation Timings
December 4, 2006 21519C4
Am29DL800B
33
D A T A S H E E T
AC CHARACTERISTICS
tWC
Valid PA
tWC
tRC
tWC
Valid PA
Valid RA
Valid PA
Addresses
tAH
tCPH
tACC
tCE
CE#
tCP
tOE
OE#
tOEH
tGHWL
tWP
WE#
tDF
tWPH
tDS
tOH
tDH
Valid
Out
Valid
In
Valid
In
Valid
In
Data
tSR/W
WE# Controlled Write Cycle
Read Cycle
CE# Controlled Write Cycles
Figure 19. Back-to-Back Read/Write Cycle Timings
tRC
Addresses
CE#
VA
tACC
tCE
VA
VA
tCH
tOE
OE#
WE#
tOEH
tDF
tOH
High Z
High Z
DQ7
Valid Data
Complement
Complement
True
DQ0–DQ6
Status Data
True
Valid Data
Status Data
tBUSY
RY/BY#
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
Figure 20. Data# Polling Timings (During Embedded Algorithms)
34
Am29DL800B
21519C4 December 4, 2006
D A T A S H E E T
AC CHARACTERISTICS
tAHT
tAS
Addresses
tAHT
tASO
CE#
tOEH
WE#
tCEPH
tOEPH
OE#
tDH
Valid Data
tOE
Valid
Status
Valid
Status
Valid
Status
DQ6/DQ2
Valid Data
(first read)
(second read)
(stops toggling)
RY/BY#
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read
cycle, and array data read cycle
Figure 21. Toggle Bit Timings (During Embedded Algorithms)
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase
Complete
WE#
Erase
Erase Suspend
Read
DQ6
DQ2
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle
DQ2 and DQ6.
Figure 22. DQ2 vs. DQ6
December 4, 2006 21519C4
Am29DL800B
35
D A T A S H E E T
AC CHARACTERISTICS
Temporary Sector Unprotect
Parameter
JEDEC
Std
Description
All Speed Options
Unit
tVIDR
VID Rise and Fall Time (See Note)
Min
Min
500
ns
RESET# Setup Time for Temporary Sector
Unprotect
tRSP
4
4
µs
µs
RESET# Hold Time from RY/BY# High for
Temporary Sector Unprotect
tRRB
Min
Note: Not 100% tested.
12 V
RESET#
0 V or 3 V
0 V or 3 V
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
tRRB
tRSP
RY/BY#
Figure 23. Temporary Sector Unprotect Timing Diagram
VID
VIH
RESET#
SA, A6,
A1, A0
Valid*
Valid*
Valid*
Status
Sector Protect/Unprotect
Verify
40h
Data
60h
60h
Sector Protect: 150 µs
Sector Unprotect: 15 ms
1 µs
CE#
WE#
OE#
* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
Figure 24. Sector Protect/Unprotect Timing Diagram
36
Am29DL800B
21519C4 December 4, 2006
D A T A S H E E T
AC CHARACTERISTICS
Alternate CE# Controlled Erase/Program Operations
Parameter
JEDEC
tAVAV
Std
tWC
tAS
tAH
tDS
tDH
Description
70
90
90
0
120
Unit
ns
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
Min
Min
Min
Min
Min
70
120
tAVWL
tELAX
tDVEH
tEHDX
ns
45
35
45
45
0
50
50
ns
ns
ns
Read Recovery Time Before Write
(OE# High to WE# Low)
tGHEL
tGHEL
Min
0
ns
tWLEL
tEHWH
tELEH
tEHEL
tWS
tWH
tCP
WE# Setup Time
WE# Hold Time
Min
Min
Min
Min
Typ
Typ
Typ
0
0
ns
ns
ns
ns
CE# Pulse Width
CE# Pulse Width High
35
35
30
9
50
tCPH
Byte
Programming Operation
(Note 2)
tWHWH1
tWHWH2
Notes:
tWHWH1
µs
Word
11
0.7
tWHWH2 Sector Erase Operation (Note 2)
sec
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
December 4, 2006 21519C4
Am29DL800B
37
D A T A S H E E T
AC CHARACTERISTICS
555 for program
PA for program
2AA for erase
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tWH
tAS
tAH
WE#
OE#
tGHEL
tWHWH1 or 2
tCP
CE#
Data
tWS
tCPH
tDS
tBUSY
tDH
DQ7#
DOUT
tRH
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data, DQ7# = complement of the data written to the device,
DOUT = data written to the device.
3. Waveforms are for the word mode.
Figure 25. Alternate CE# Controlled Erase/Program Operation Timings
38
Am29DL800B
21519C4 December 4, 2006
D A T A S H E E T
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ (Note 1) Max (Note 2)
Unit
sec
sec
µs
Comments
Sector Erase Time
Chip Erase Time
Byte Program Time
Word Program Time
0.7
14
9
15
Excludes 00h programming
prior to erasure (Note 4)
300
360
27
11
9
µs
Excludes system level
overhead (Note 5)
Byte Mode
Word Mode
Chip Program Time
(Note 3)
sec
5.8
17
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See
Table 5 for further information on command definitions.
6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Min
Max
Input voltage with respect to VSS on all pins except I/O pins
(including A9, OE#, and RESET#)
–1.0 V
12.5 V
Input voltage with respect to VSS on all I/O pins
VCC Current
–1.0 V
VCC + 1.0 V
+100 mA
–100 mA
Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.
TSOP AND SO PIN CAPACITANCE
Parameter
Symbol
Parameter Description
Input Capacitance
Test Setup
VIN = 0
Typ
6
Max
7.5
12
Unit
pF
CIN
COUT
CIN2
Output Capacitance
Control Pin Capacitance
VOUT = 0
VIN = 0
8.5
7.5
pF
9
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
DATA RETENTION
Parameter Description
Test Conditions
150°C
Min
10
Unit
Years
Years
Minimum Pattern Data Retention Time
125°C
20
December 4, 2006 21519C4
Am29DL800B
39
D A T A S H E E T
PHYSICAL DIMENSIONS
TS 048—48-Pin Standard TSOP
Dwg rev AA; 10/99
* For reference only. BSC is an ANSI standard for Basic Space Centering
40
Am29DL800B
21519C4 December 4, 2006
D A T A S H E E T
PHYSICAL DIMENSIONS (continued)
FBB048 —48-Ball Fine-Pitch Ball Grid Array (FBGA),
6 x 9 mm package
Dwg rev AF; 10/99
December 4, 2006 21519C4
Am29DL800B
41
D A T A S H E E T
PHYSICAL DIMENSIONS (continued)
SO 044—44-Pin Small Outline
Dwg rev AC; 10/99
42
Am29DL800B
21519C4 December 4, 2006
D A T A S H E E T
REVISION SUMMARY
Revision A (January 1998)
Revision A+4 (August 1998)
Initial release.
Ordering Information
Corrected description for E and F package type desig-
nators to 48-pin TSOP.
Revision A+1 (January 1998)
Reset Command
AC Characteristics
Deleted last paragraph in section, which applied to RESET#,
not the reset command.
Read Operations: Corrected t , t
speed option.
, t
for 90 ns
RC ACC CE
Revision A+2 (Febrauary 1998)
Figure 24, Sector Protection/Unprotection Timing
Diagram
Hardware Reset (RESET#)
Changed timing parameters to match those in Figure 2.
Added note to table, fixed references to note.
Revision B (January 1999)
Revision A+3 (April 1998)
Connection Diagrams
Global
Changed FBGA drawing to top view.
Removed references to the 80 ns speed option.
Ordering Information
Changed the 70R ns (V
5%) speed option to the
CC
70 ns (V
10%) speed option.
Changed FBGA package reference to FBB048. Added
FBGA package markings to valid combinations table.
CC
Figure 2, In-System Sector Protect/Unprotect
Algorithms
Revision B+1 (February 1999)
In the sector protect algorithm, added a “Reset
PLSCNT=1” box in the path from “Protect another sec-
tor?” back to setting up the next sector address.
Physical Dimensions
Corrected ball grid layout on FBB048.
DQ6: Toggle Bit I
Revision B+2 (July 2, 1999)
In the first and second paragraphs, clarified that the
toggle bit may be read “at any address within the pro-
gramming or erasing bank,” not “at any address.” In the
fourth paragraph, clarified “device” to “bank.”
Test Conditions
Test Specifications table: Corrected to indicate that the
70 ns speed is tested at 30 pF loading.
DC Characteristics
Revision C (December 7, 1999)
Added reference to Note 4 on I
and I
specifications.
CC6
CC7
AC Characteristics—Figure 17. Program
Operations Timing and Figure 18. Chip/Sector
Erase Operations
AC Characteristics
Erase/Program Operations; Alternate CE# Controlled
Erase/Program Operations: Corrected the
Deleted t
high.
and changed OE# waveform to start at
GHWL
notes reference for t
and t
. These param-
WHWH1
WHWH2
eters are 100% tested. Corrected the note reference for
. This parameter is not 100% tested.
t
Physical Dimensions
VCS
Replaced figures with more detailed illustrations.
Temporary Sector Unprotect Table
Added note reference for t
100% tested.
. This parameter is not
VIDR
Revision C+1 (November 21, 2000)
Global
Figure 24, Sector Protect/Unprotect Timing
Diagram
Added table of contents.
A valid address is not required for the first write cycle;
only the data 60h.
Ordering Information
Deleted burn-in option.
Erase and Programming Performance
In Note 2, the worst case endurance is now 1 million cycles.
December 4, 2006 21519C4
Am29DL800B
43
D A T A S H E E T
Revision C+2 (June 7, 2000)
Revision C4 (December 4, 2006)
Ordering Information
Erase and Program Operations table
Changed t to a maximum specification.
Added Pb-Free OPNs.
BUSY
Revision C+3 (January 5, 2006)
Global
Removed TSR048 48-pin Reverse TSOP option.
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limita-
tion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as con-
templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor de-
vices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design mea-
sures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating
conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign
Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au-
thorization by the respective government entity will be required for export of those products
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marks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are
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Copyright © 2006 Spansion Inc. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, HD-SIM, and combinations thereof are
trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners.
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Am29DL800B
21519C4 December 4, 2006
相关型号:
AM29DL800BT70WBI
8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory
AMD
AM29DL800BT70WBIB
8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory
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AM29DL800BT70WBK
8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory
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