AM29DS163DT120WAK_技术文档

Am29DS163D

Data Sheet

July 2003

The following document specifies Spansion memory products that are now offered by both Advanced

Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-

inally developed the specification, these products will be offered to customers of both AMD and

Fujitsu.

Continuity of Specifications

There is no change to this datasheet as a result of offering the device as a Spansion product. Any

changes that have been made are the result of normal datasheet improvement and are noted in the

document revision summary, where supported. Future routine revisions will occur when appropriate,

and changes will be noted in a revision summary.

Continuity of Ordering Part Numbers

AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order

these products, please use only the Ordering Part Numbers listed in this document.

For More Information

Please contact your local AMD or Fujitsu sales office for additional information about Spansion

memory solutions.

Publication Number 22326 Revision A Amendment +1 Issue Date November 8, 2004

THIS PAGE LEFT INTENTIONALLY BLANK.

ADVANCE INFORMATION

Am29DS163D

16 Megabit (2 M x 8-Bit/1 M x 16-Bit)

CMOS 1.8 Volt-only, Simultaneous Operation Flash Memory

DISTINCTIVE CHARACTERISTICS

ARCHITECTURAL ADVANTAGES

■ 20 Year data retention at 125°C

— Reliable operation for the life of the system

■ Simultaneous Read/Write operations

— Data can be continuously read from one bank while

executing erase/program functions in other bank

SOFTWARE FEATURES

■ Data Management Software (DMS)

— Zero latency between read and write operations

— AMD-supplied software manages data programming

and erasing, enabling EEPROM emulation

■ Multiple bank architectures

— Two devices available with different bank sizes (refer

to Table 3)

— Eases sector erase limitations

■ Supports Common Flash Memory Interface (CFI)

■ Secured Silicon (SecSi) Sector

■ Erase Suspend/Erase Resume

— Suspends erase operations to allow programming in

same bank

— Factory locked and identifiable: 16 bytes available for

secure, random factory Electronic Serial Number;

verifiable as factory locked through autoselect

function. ExpressFlash option allows entire sector to

be available for factory-secured data.

■ Data# Polling and Toggle Bits

— Provides a software method of detecting the status of

program or erase cycles

— Customer lockable: Can be read, programmed, or

erased just like other sectors. Once locked, data

cannot be changed.

■ Unlock Bypass Program command

— Reduces overall programming time when issuing

multiple program command sequences

— 64 Kbyte sector size

■ Zero Power Operation

HARDWARE FEATURES

— Sophisticated power management circuits reduce

power consumed during inactive periods to nearly

zero

■ Any combination of sectors can be erased

■ Ready/Busy# output (RY/BY#)

— Hardware method for detecting program or erase

cycle completion

■ Package options

— 48-ball FBGA

■ Hardware reset pin (RESET#)

■ Top or bottom boot block

— Hardware method of resetting the internal state

machine to reading array data

■ Manufactured on 0.23 µm process technology

■ Compatible with JEDEC standards

■ WP#/ACC input pin

— Pinout and software compatible with

single-power-supply flash standard

— Write protect (WP#) function allows protection of two

outermost boot sectors, regardless of sector protect status

— Acceleration (ACC) function provides accelerated

program times

PERFORMANCE CHARACTERISTICS

■ High performance

■ Sector protection

— Access time as fast 100 ns

— Hardware method of locking a sector, either

in-system or using programming equipment, to

prevent any program or erase operation within that

sector

— Program time: 13 µs/word typical utilizing Accelerate function

■ Ultra low power consumption (typical values)

— 1 mA active read current at 1 MHz

— 5 mA active read current at 5 MHz

— Temporary Sector Unprotect allows changing data in

protected sectors in-system

— 200 nA in standby or automatic sleep mode

■ Minimum 1 million write cycles guaranteed per sector

Publication# 22326 Rev: A Amendment/1

Issue Date: November 8, 2004

This document contains information on a product under development at Advanced Micro Devices. The information

is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed

product without notice.

Refer to AMD’s Website (www.amd.com) for the latest information.

A D V A N C E I N F O R M A T I O N

GENERAL DESCRIPTION

The Am29DS163D family consists of 16 megabit, 1.8

volt-only flash memory devices, organized as 1,048,576

words of 16 bits each or 2,097,152 bytes of 8 bits each.

Word mode data appears on DQ0–DQ15; byte mode

data appears on DQ0–DQ7. The device is designed to

be programmed in-system with the standard 1.8 volt

V_CCsupply, and can also be programmed in standard

EPROM programmers.

removal of EEPROM devices. DMS also allows the

system software to be simplified, as it performs all

functions necessary to modify data in file structures,

as opposed to single-byte modifications. To write or

update a particular piece of data (a phone number or

configuration data, for example), the user only needs

to state which piece of data is to be updated, and

where the updated data is located in the system. This

is an advantage compared to systems where

user-written software must keep track of the old data

location, status, logical to physical translation of the

data onto the Flash memory device (or memory de-

vices), and more. Using DMS, user-written software

does not need to interface with the Flash memory di-

rectly. Instead, the user's software accesses the Flash

memory by calling one of only six functions. AMD pro-

vides this software to simplify system design and

software integration efforts.

The device is available with an access time of 100 and

120 ns. The devices are offered in an 48-ball FBGA

package. Standard control pins—chip enable (CE#),

write enable (WE#), and output enable (OE#)—control

normal read and write operations, and avoid bus con-

tention issues.

The device requires only a single 1.8 volt power sup-

ply for both read and write functions. Internally

generated and regulated voltages are provided for the

program and erase operations.

The device offers complete compatibility with the

JEDEC single-power-supply Flash command set

standard. Commands are written to the command

register using standard microprocessor write timings.

Reading data out of the device is similar to reading

from other Flash or EPROM devices.

Simultaneous Read/Write Operations with

Zero Latency

The Simultaneous Read/Write architecture provides

simultaneous operation by dividing the memory

space into two banks. The device can improve overall

system performance by allowing a host system to pro-

gram or erase in one bank, then immediately and

simultaneously read from the other bank, with zero la-

tency. This releases the system from waiting for the

completion of program or erase operations.

The host system can detect whether a program or

erase operation is complete by using the device sta-

tus bits: RY/BY# pin, DQ7 (Data# Polling) and

DQ6/DQ2 (toggle bits). After a program or erase cycle

is completed, the device automatically returns to read-

ing array data.

Am29DS163D Features

The sector erase architecture allows memory sec-

tors to be erased and reprogrammed without affecting

the data contents of other sectors. The device is fully

erased when shipped from the factory.

The Secured Silicon (SecSi) Sector is an additional

64 Kbyte sector capable of being permanently locked

by AMD or customers. The SecSi Sector Indicator

Bit (DQ7) is permanently set to a 1 if the part is fac-

tory locked, and set to a 0 if customer lockable. This

way, customer lockable parts can never be used to re-

place a factory locked part.

Hardware data protection measures include a low

V_CCdetector that automatically inhibits write opera-

tions during power transitions. The hardware sector

protection feature disables both program and erase

operations in any combination of the sectors of mem-

ory. This is achieved in-system or via programming

equipment.

Factory locked parts provide several options. The

SecSi Sector may store a secure, random 16 byte

ESN (Electronic Serial Number), customer code (pro-

grammed through AMD’s ExpressFlash service), or

both. Customer Lockable parts may utilize the SecSi

Sector as bonus space, reading and writing like any

other flash sector, or may permanently lock their own

code there.

The device offers two power-saving features. When

addresses are stable for a specified amount of time,

the device enters the automatic sleep mode. The

system can also place the device into the standby

mode. Power consumption is greatly reduced in both

modes.

DMS (Data Management Software) allows systems

to easily take advantage of the advanced architecture

of the simultaneous read/write product line by allowing

4

Am29DS163D

A D V A N C E I N F O R M A T I O N

TABLE OF CONTENTS

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 6

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 7

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 10

Table 1. Am29DS163D Device Bus Operations .............................10

Word/Byte Configuration ........................................................ 10

Requirements for Reading Array Data ...................................10

Writing Commands/Command Sequences ............................11

Accelerated Program Operation ......................................................11

Autoselect Functions .......................................................................11

Simultaneous Read/Write Operations with Zero Latency .......11

Standby Mode ........................................................................ 11

Automatic Sleep Mode ...........................................................12

RESET#: Hardware Reset Pin ...............................................12

Output Disable Mode .............................................................. 12

Table 2. Am29DS163D Device Bank Divisions ...............................12

Table 3. Top Boot Sector Addresses (Am29DS16xDT) ..................13

SecSi Sector Addresses for Top Boot Devices.............................. 13

Table 5. Bottom Boot Sector Addresses (Am29DS16xDB) ............14

SecSi Sector Addresses for Bottom Boot Devices......................... 14

Autoselect Mode ..................................................................... 15

Table 7. Am29DS163D Autoselect Codes (High Voltage Method) 15

Sector/Sector Block Protection and Unprotection .................. 16

Table 8. Top Boot Sector/Sector Block Addresses

Sector Erase Command Sequence ........................................25

Erase Suspend/Erase Resume Commands ...........................26

Figure 4. Erase Operation.............................................................. 26

Table 14. Am29DS163D Command Definitions.............................. 27

Write Operation Status . . . . . . . . . . . . . . . . . . . . 28

DQ7: Data# Polling .................................................................28

Figure 5. Data# Polling Algorithm .................................................. 28

RY/BY#: Ready/Busy# ............................................................ 29

DQ6: Toggle Bit I ....................................................................29

Figure 6. Toggle Bit Algorithm........................................................ 29

DQ2: Toggle Bit II ................................................................... 30

Reading Toggle Bits DQ6/DQ2 ...............................................30

DQ5: Exceeded Timing Limits ................................................ 30

DQ3: Sector Erase Timer ....................................................... 30

Table 15. Write Operation Status ................................................... 31

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 32

Figure 7. Maximum Negative Overshoot Waveform ...................... 32

Figure 8. Maximum Positive Overshoot Waveform....................... 32

Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 32

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 9. I_CC1Current vs. Time (Showing Active

and Automatic Sleep Currents)...................................................... 34

Figure 10. Typical I_CC1vs. Frequency............................................ 34

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 11. Test Setup.................................................................... 35

Table 16. Test Specifications ......................................................... 35

Figure 12. Input Waveforms and Measurement Levels ................. 35

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 13. Read Operation Timings ............................................... 36

Figure 14. Reset Timings ............................................................... 37

Word/Byte Configuration (BYTE#) ..........................................38

Figure 15. BYTE# Timings for Read Operations............................ 38

Figure 16. BYTE# Timings for Write Operations............................ 38

Erase and Program Operations ..............................................39

Figure 17. Program Operation Timings.......................................... 40

Figure 18. Accelerated Program Timing Diagram.......................... 40

Figure 19. Chip/Sector Erase Operation Timings .......................... 41

Figure 20. Back-to-back Read/Write Cycle Timings ...................... 42

Figure 21. Data# Polling Timings (During Embedded Algorithms). 42

Figure 22. Toggle Bit Timings (During Embedded Algorithms)...... 43

Figure 23. DQ2 vs. DQ6................................................................. 43

Temporary Sector/Sector Block Unprotect ............................. 44

Figure 24. Temporary Sector/Sector Block

for Protection/Unprotection .............................................................16

Table 9. Bottom Boot Sector/Sector Block Addresses

for Protection/Unprotection .............................................................16

Write Protect (WP#) ................................................................17

Temporary Sector/Sector Block Unprotect ............................. 17

Figure 1. Temporary Sector Unprotect Operation........................... 17

Figure 2. In-System Sector/Sector Block Protect

and Unprotect Algorithms................................................................ 18

SecSi (Secured Silicon) Sector Flash Memory Region .......... 19

Hardware Data Protection ......................................................19

Low VCC Write Inhibit .....................................................................20

Write Pulse “Glitch” Protection ........................................................20

Logical Inhibit ..................................................................................20

Power-Up Write Inhibit ....................................................................20

Common Flash Memory Interface (CFI) . . . . . . . 20

Table 10. CFI Query Identification String........................................ 20

System Interface String................................................................... 21

Table 12. Device Geometry Definition ............................................ 21

Table 13. Primary Vendor-Specific Extended Query ...................... 22

Command Definitions . . . . . . . . . . . . . . . . . . . . . . 23

Reading Array Data ................................................................23

Reset Command .....................................................................23

Autoselect Command Sequence ............................................23

Enter SecSi Sector/Exit SecSi Sector Command Sequence ..24

Byte/Word Program Command Sequence ............................. 24

Unlock Bypass Command Sequence ..............................................24

Figure 3. Program Operation .......................................................... 25

Chip Erase Command Sequence ........................................... 25

Unprotect Timing Diagram ............................................................. 44

Figure 25. Sector/Sector Block Protect/Unprotect Timing Diagram 45

Alternate CE# Controlled Erase and Program Operations ..... 46

Figure 26. Alternate CE# Controlled Write

(Erase/Program) Operation Timings .............................................. 47

Erase And Programming Performance . . . . . . . 48

Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 48

Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 49

FBA048—48-Ball Fine-Pitch Ball Grid Array (FBGA)

6 x 8 mm package .................................................................49

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 50

Am29DS163D

5

A D V A N C E I N F O R M A T I O N

PRODUCT SELECTOR GUIDE

Part Number

Am29DS163D

Speed Option

Standard Voltage Range: V_CC= 1.8–2.2 V

100

35

120

50

Max Access Time (ns)

CE# Access (ns)

OE# Access (ns)

BLOCK DIAGRAM

OE# BYTE#

V

CC

SS

Upper Bank Address

A0–A19

Upper Bank

X-Decoder

RY/BY#

A0–A19

RESET#

STATE

CONTROL

&

COMMAND

REGISTER

WE#

CE#

Status

DQ0–DQ15

BYTE#

Control

WP#/ACC

DQ0–DQ15

X-Decoder

Lower Bank

A0–A19

Lower Bank Address

OE# BYTE#

6

Am29DS163D

A D V A N C E I N F O R M A T I O N

CONNECTION DIAGRAMS

48-Ball FBGA

Top View, Balls Facing Down

A6

B6

C6

D6

E6

F6

G6

H6

V_SS

A13

A12

A14

A15

A16

BYTE# DQ15/A-1

A5

A9

B5

A8

C5

D5

E5

F5

G5

H5

A10

A11

DQ7

DQ14

DQ13

DQ6

A4

B4

C4

D4

E4

F4

G4

H4

WE# RESET#

NC

A19

DQ5

DQ12

V_CC

DQ4

A3 B3

C3

D3

E3

F3

G3

H3

RY/BY# WP#/ACC A18

NC

DQ2

DQ10

DQ11

DQ3

A2

A7

B2

C2

A6

D2

A5

E2

F2

G2

H2

A17

DQ0

DQ8

DQ9

DQ1

A1

A3

B1

A4

C1

A2

D1

A1

E1

A0

F1

G1

H1

V_SS

CE#

OE#

Flash memory devices in FBGA packages may be

damaged if exposed to ultrasonic cleaning methods.

The package and/or data integrity may be compro-

mised if the package body is exposed to temperatures

above 150°C for prolonged periods of time.

Special Handling Instructions for FBGA

Package

Special handling is required for Flash Memory prod-

ucts in FBGA packages.

Am29DS163D

7

A D V A N C E I N F O R M A T I O N

PIN DESCRIPTION

LOGIC SYMBOL

A0–A19

= 20 Addresses

20

DQ0–DQ14 = 15 Data Inputs/Outputs

A0–A19

16 or 8

DQ15/A-1

= DQ15 (Data Input/Output, word

mode), A-1 (LSB Address Input, byte

mode)

DQ0–DQ15

(A-1)

CE#

OE#

CE#

OE#

WE#

= Chip Enable

= Output Enable

= Write Enable

WE#

WP#/ACC

RESET#

BYTE#

WP#/ACC = Hardware Write Protect/

Acceleration Pin

RY/BY#

RESET#

BYTE#

RY/BY#

V_CC

= Hardware Reset Pin, Active Low

= Selects 8-bit or 16-bit mode

= Ready/Busy Output

= 1.8 volt-only single power supply

(see Product Selector Guide for speed

options and voltage supply tolerances)

V_SS

NC

= Device Ground

= Pin Not Connected Internally

8

Am29DS163D

A D V A N C E I N F O R M A T I O N

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid

Combination) is formed by a combination of the following:

Am29DS163D

T

100

E

I

OPTIONAL PROCESSING

Blank = Standard Processing

N

=

16-byte ESN devices

(Contact an AMD representative for more information)

TEMPERATURE RANGE

I

=

Industrial (–40°C to +85°C)

E

F

K

Extended (–55°C to +125°C)

Industrial (-40^oC to +85^oC) with Pb-free Package

Extended (-55^oC to +125^oC) with Pb-free Package

PACKAGE TYPE

WA

=

48-Ball Fine-Pitch Ball Grid Array (FBGA)

0.80 mm pitch, 6 x 8 mm package (FBA048)

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T

B

=

Top sector

Bottom sector

DEVICE NUMBER/DESCRIPTION

Am29DS163D

16Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS Flash Memory

1.8 Volt-only Read, Program, and Erase

Valid Combinations

Valid Combinations for FBGA Packages

Order Number Package Marking

Am29DS163DT100,

Valid Combinations list configurations planned to be supported in

volume for this device. Consult the local AMD sales office to con-

firm availability of specific valid combinations and to check on

newly released combinations.

S163DT10V,

S163DB10V

WAI,

WAE,

WAF,

WAK

Am29DS163DB100

I, E,

F, K

Am29DS163DT120,

Am29DS163DB120

S163DT12V,

S163DB12V

Am29DS163D

9

A D V A N C E I N F O R M A T I O N

DEVICE BUS OPERATIONS

This section describes the requirements and use of

the device bus operations, which are initiated through

the internal command register. The command register

itself does not occupy any addressable memory loca-

tion. The register is a latch used to store the

commands, along with the address and data informa-

tion needed to execute the command. The contents of

the register serve as inputs to the internal state ma-

chine. The state machine outputs dictate the function

of the device. Table 1 lists the device bus operations,

the inputs and control levels they require, and the re-

sulting output. The following subsections describe

each of these operations in further detail.

Table 1. Am29DS163D Device Bus Operations

DQ8–DQ15

Addresses

(Note 2)

DQ0– BYTE# BYTE#

Operation

CE# OE# WE# RESET# WP#/ACC

DQ7

D_OUT

D_IN

= V_IH

D_OUT

D_IN

= V_IL

Read

Write

L

H

L

H

L/H

A_IN

DQ8–DQ14=High-Z,

DQ15 = A-1

H

(Note 3)

V_CC

0.3 V

V_CC

0.3 V

Standby

X

H

X

High-Z High-Z

High-Z

Output Disable

Reset

L

H

X

H

X

H

L

L/H

X

High-Z High-Z

High-Z

X

SA, A6 = L,

A1 = H, A0 = L

Sector Protect (Note 2)

L

H

L

V_ID

L/H

D_IN

X

SA, A6 = H,

A1 = H, A0 = L

Sector Unprotect (Note 2)

Temporary Sector Unprotect

L

H

X

L

V_ID

(Note 3)

D_IN

X

A_IN

D_IN

High-Z

Legend: L = Logic Low = V_IL, H = Logic High = V_IH, V_ID= 9.0–11.0 V, V_HH= 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address,

_IN= Address In, D_IN= Data In, D_OUT= Data Out

A

Notes:

1. Addresses are A19:A0 in word mode (BYTE# = V_IH), A19:A-1 in byte mode (BYTE# = V_IL).

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See “Sector/Sector

Block Protection and Unprotection” on page 16.

3. If WP#/ACC = V_IL, the two outermost boot sectors remain protected. If WP#/ACC = V_IH, the two outermost boot sector

protection depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block

Protection and Unprotection” on page 16. If WP#/ACC = V_HH,all sectors are unprotected.

Word/Byte Configuration

Requirements for Reading Array Data

The BYTE# pin controls whether the device data I/O

pins operate in the byte or word configuration. If the

BYTE# pin is set at logic ‘1’, the device is in word con-

figuration, DQ0–DQ15 are active and controlled by

CE# and OE#.

To read array data from the outputs, the system must

drive the CE# and OE# pins to V_IL. CE# is the power

control and selects the device. OE# is the output con-

trol and gates array data to the output pins. WE#

should remain at V_IH. The BYTE# pin determines

whether the device outputs array data in words or

bytes.

If the BYTE# pin is set at logic ‘0’, the device is in byte

configuration, and only data I/O pins DQ0–DQ7 are

active and controlled by CE# and OE#. The data I/O

pins DQ8–DQ14 are tri-stated, and the DQ15 pin is

used as an input for the LSB (A-1) address function.

The internal state machine is set for reading array data

upon device power-up, or after a hardware reset. This

ensures that no spurious alteration of the memory

content occurs during the power transition. No com-

mand is necessary in this mode to obtain array data.

Standard microprocessor read cycles that assert valid

10

Am29DS163D

A D V A N C E I N F O R M A T I O N

addresses on the device address inputs produce valid

would use a two-cycle program command sequence

as required by the Unlock Bypass mode. Removing

data on the device data outputs. Each bank remains

enabled for read access until the command register

contents are altered.

V

_HHfrom the WP#/ACC pin returns the device to nor-

mal operation. Note that the WP#/ACC pin must not be

at V_HHfor operations other than accelerated program-

ming, or device damage may result. In addition, the

WP#/ACC pin must not be left floating or unconnected;

inconsistent behavior of the device may result.

See “Requirements for Reading Array Data” on

page 10 for more information. Refer to the Table on

page 36 for timing specifications and to Figure 13, on

page 36 for the timing diagram. I_CC1in the DC Charac-

teristics table represents the active current

specification for reading array data.

Autoselect Functions

If the system writes the autoselect command se-

quence, the device enters the autoselect mode. The

system can then read autoselect codes from the inter-

nal register (which is separate from the memory array)

on DQ7–DQ0. Standard read cycle timings apply in

this mode. Refer to “Autoselect Mode” on page 15 and

“Autoselect Command Sequence” on page 23 for

more information.

Writing Commands/Command Sequences

To write a command or command sequence (which in-

cludes programming data to the device and erasing

sectors of memory), the system must drive WE# and

CE# to V_IL, and OE# to V_IH.

For program operations, the BYTE# pin determines

whether the device accepts program data in bytes or

words. Refer to “Word/Byte Configuration” on page 10

for more information.

Simultaneous Read/Write Operations with

Zero Latency

This device is capable of reading data from one bank

of memory while programming or erasing in the other

bank of memory. An erase operation may also be sus-

pended to read from or program to another location

within the same bank (except the sector being

erased). Figure 20, on page 42 shows how read and

write cycles may be initiated for simultaneous opera-

tion with zero latency. I_CC6and I_CC7in the DC

Characteristics table represent the current specifica-

tions for read-while-program and read-while-erase,

respectively.

The device features an Unlock Bypass mode to facili-

tate faster programming. Once a bank enters the

Unlock Bypass mode, only two write cycles are re-

quired to program a word or byte, instead of four. The

“Word/Byte Configuration” section contains details on

programming data to the device using both standard

and Unlock Bypass command sequences.

An erase operation can erase one sector, multiple sec-

tors, or the entire device. Table 3 on page 13 to

Table 6 on page 14 indicate the address space that

each sector occupies. The device address space is di-

vided into two banks: Bank 1 contains the

boot/parameter sectors, and Bank 2 contains the

larger, code sectors of uniform size. A “bank address”

is the address bits required to uniquely select a bank.

Similarly, a “sector address” is the address bits re-

quired to uniquely select a sector.

Standby Mode

When the system is not reading or writing to the de-

vice, it can place the device in the standby mode. In

this mode, current consumption is greatly reduced,

and the outputs are placed in the high impedance

state, independent of the OE# input.

I_CC2in the DC Characteristics table represents the ac-

tive current specification for the write mode. The “AC

Characteristics” on page 36 section contains timing

specification tables and timing diagrams for write

operations.

The device enters the CMOS standby mode when the

CE# and RESET# pins are both held at V_CC± 0.3 V.

(Note that this is a more restricted voltage range than

V_IH.) If CE# and RESET# are held at V_IH, but not within

V_CC± 0.3 V, the device is in the standby mode, but the

standby current is greater. The device requires stan-

dard access time (t_CE) for read access when the

device is in either of these standby modes, before it is

ready to read data.

Accelerated Program Operation

The device offers accelerated program operations

through the ACC function. This is one of two functions

provided by the WP#/ACC pin. This function is prima-

rily intended to allow faster manufacturing throughput

at the factory.

If the device is deselected during erasure or program-

ming, the device draws active current until the

operation is completed.

If the system asserts V_HHon this pin, the device auto-

matically enters the aforementioned Unlock Bypass

mode, temporarily unprotects any protected sectors,

and uses the higher voltage on the pin to reduce the

time required for program operations. The system

I_CC3in the DC Characteristics table represents the

standby current specification.

Am29DS163D

11

A D V A N C E I N F O R M A T I O N

at V_ILbut not within V_SS±0.3 V, the standby current is

Automatic Sleep Mode

greater.

The automatic sleep mode minimizes Flash device en-

ergy consumption. The device automatically enables

The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash

memory, enabling the system to read the boot-up firm-

ware from the Flash memory.

this mode when addresses remain stable for t_ACC

+

30 ns. The automatic sleep mode is independent of

the CE#, WE#, and OE# control signals. Standard ad-

dress access timings provide new data when

addresses are changed. While in sleep mode, output

data is latched and always available to the system.

I_CC4in the “DC Characteristics” on page 33 represents

the automatic sleep mode current specification.

If RESET# is asserted during a program or erase op-

eration, the RY/BY# pin remains a “0” (busy) until the

internal reset operation is complete, which requires a

time of t_READY(during Embedded Algorithms). The sys-

tem can thus monitor RY/BY# to determine whether

the reset operation is complete. If RESET# is asserted

when a program or erase operation is not executing

(RY/BY# pin is “1”), the reset operation is completed

within a time of t_READY(not during Embedded Algo-

rithms). The system can read data t_RHafter the

RESET# pin returns to V_IH.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of re-

setting the device to reading array data. When the

RESET# pin is driven low for at least a period of t_RP,

the device immediately terminates any operation in

progress, tristates all output pins, and ignores all

read/write commands for the duration of the RESET#

pulse. The device also resets the internal state ma-

chine to reading array data. The operation that was

interrupted should be reinitiated once the device is

ready to accept another command sequence, to en-

sure data integrity.

Refer to “AC Characteristics” on page 36 for RESET#

parameters and to Figure 14, on page 37 for the timing

diagram.

Output Disable Mode

When the OE# input is at V_IH, output from the device is

disabled. The output pins are placed in the high

impedance state.

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at V_SS±0.3 V, the device

draws CMOS standby current (I_CC4). If RESET# is held

Table 2. Am29DS163D Device Bank Divisions

Bank 1

Bank 2

Sector Sizes

Device

Part Number

Megabits

Sector Sizes

Megabits

Eight 8 Kbyte/4 Kword,

seven 64 Kbyte/32 Kword

Twenty-four

64 Kbyte/32 Kword

Am29DS163D

4 Mbit

12 Mbit

12

Am29DS163D

A D V A N C E I N F O R M A T I O N

Table 3. Top Boot Sector Addresses (Am29DS16xDT)

Sector Address

A19–A12

Sector Size

(Kbytes/Kwords)

(x8)

(x16)

Address Ranges

Sector

Address Range

SA0

SA1

00000xxx

00001xxx

00010xxx

00011xxx

00100xxx

00101xxx

00110xxx

00111xxx

01000xxx

01001xxx

01010xxx

01011xxx

01100xxx

01101xxx

01110xxx

01111xxx

10000xxx

10001xxx

10010xxx

10011xxx

10100xxx

10101xxx

10110xxx

10111xxx

11000xxx

11001xxx

11010xxx

11011xxx

11100xxx

11101xxx

11110xxx

11111000

11111001

11111010

11111011

11111100

11111101

11111110

11111111

64/32

8/4

000000h-00FFFFh

010000h-01FFFFh

020000h-02FFFFh

030000h-03FFFFh

040000h-04FFFFh

050000h-05FFFFh

060000h-06FFFFh

070000h-07FFFFh

080000h-08FFFFh

090000h-09FFFFh

0A0000h-0AFFFFh

0B0000h-0BFFFFh

0C0000h-0CFFFFh

0D0000h-0DFFFFh

0E0000h-0EFFFFh

0F0000h-0FFFFFh

100000h-10FFFFh

110000h-11FFFFh

120000h-12FFFFh

130000h-13FFFFh

140000h-14FFFFh

150000h-15FFFFh

160000h-16FFFFh

170000h-17FFFFh

180000h-18FFFFh

190000h-19FFFFh

1A0000h-1AFFFFh

1B0000h-1BFFFFh

1C0000h-1CFFFFh

1D0000h-1DFFFFh

1E0000h-1EFFFFh

1F0000h-1F1FFFh

1F2000h-1F3FFFh

1F4000h-1F5FFFh

1F6000h-1F7FFFh

1F8000h-1F9FFFh

1FA000h-1FBFFFh

1FC000h-1FDFFFh

1FE000h-1FFFFFh

00000h–07FFFh

08000h–0FFFFh

10000h–17FFFh

18000h–1FFFFh

20000h–27FFFh

28000h–2FFFFh

30000h–37FFFh

38000h–3FFFFh

40000h–47FFFh

48000h–4FFFFh

50000h–57FFFh

58000h–5FFFFh

60000h–67FFFh

68000h–6FFFFh

70000h–77FFFh

78000h–7FFFFh

80000h–87FFFh

88000h–8FFFFh

90000h–97FFFh

98000h–9FFFFh

A0000h–A7FFFh

A8000h–AFFFFh

B0000h–B7FFFh

B8000h–BFFFFh

C0000h–C7FFFh

C8000h–CFFFFh

D0000h–D7FFFh

D8000h–DFFFFh

E0000h–E7FFFh

E8000h–EFFFFh

F0000h–F7FFFh

F8000h–F8FFFh

F9000h–F9FFFh

FA000h–FAFFFh

FB000h–FBFFFh

FC000h–FCFFFh

FD000h–FDFFFh

FE000h–FEFFFh

FF000h–FFFFFh

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

8/4

Note: The address range is A19:A-1 in byte mode (BYTE#=V_IL) or A19:A0 in word mode (BYTE#=V_IH). The bank address bits are A19 and A18 for

Am29DS163DT.

Table 4. SecSi Sector Addresses for Top Boot Devices

Sector Address

A19–A12

(x8)

(x16)

Address Range

SecSi Sector

Entire Sector

Size

Address Range

11111xxx

64 Kbytes/32 Kwords

16 bytes/8 words

1F0000h-1FFFFFh F8000h–FFFFFh

1F0000h-1F000Fh F8000h–F8007h

Factory Programmed ESN

Am29DS163D

13

A D V A N C E I N F O R M A T I O N

Table 5. Bottom Boot Sector Addresses (Am29DS16xDB)

Sector Address

A19–A12

Sector Size

(Kbytes/Kwords)

(x8)

(x16)

Address Range

Sector

Address Range

SA0

SA1

00000000

00000001

00000010

00000011

00000100

00000101

00000110

00000111

00001XXX

00010XXX

00011XXX

00100XXX

00101XXX

00110XXX

00111XXX

01000XXX

01001XXX

01010XXX

01011XXX

01100XXX

01101XXX

01110XXX

01111XXX

10000XXX

10001XXX

10010XXX

10011XXX

10100XXX

10101XXX

10110XXX

10111XXX

11000XXX

11001XXX

11010XXX

11011XXX

11100XXX

11101XXX

11110XXX

11111XXX

8/4

000000h-001FFFh

002000h-003FFFh

004000h-005FFFh

006000h-007FFFh

008000h-009FFFh

00A000h-00BFFFh

00C000h-00DFFFh

00E000h-00FFFFh

010000h-01FFFFh

020000h-02FFFFh

030000h-03FFFFh

040000h-04FFFFh

050000h-05FFFFh

060000h-06FFFFh

070000h-07FFFFh

080000h-08FFFFh

090000h-09FFFFh

0A0000h-0AFFFFh

0B0000h-0BFFFFh

0C0000h-0CFFFFh

0D0000h-0DFFFFh

0E0000h-0EFFFFh

0F0000h-0FFFFFh

100000h-10FFFFh

110000h-11FFFFh

120000h-12FFFFh

130000h-13FFFFh

140000h-14FFFFh

150000h-15FFFFh

160000h-16FFFFh

170000h-17FFFFh

180000h-18FFFFh

190000h-19FFFFh

1A0000h-1AFFFFh

1B0000h-1BFFFFh

1C0000h-1CFFFFh

1D0000h-1DFFFFh

1E0000h-1EFFFFh

1F0000h-1FFFFFh

00000h-00FFFh

01000h-01FFFh

02000h-02FFFh

03000h-03FFFh

04000h-04FFFh

05000h-05FFFh

06000h-06FFFh

07000h-07FFFh

08000h-0FFFFh

10000h-17FFFh

18000h-1FFFFh

20000h-27FFFh

28000h-2FFFFh

30000h-37FFFh

38000h-3FFFFh

40000h-47FFFh

48000h-4FFFFh

50000h-57FFFh

58000h-5FFFFh

60000h-67FFFh

68000h-6FFFFh

70000h-77FFFh

78000h-7FFFFh

80000h-87FFFh

88000h-8FFFFh

90000h-97FFFh

98000h-9FFFFh

A0000h-A7FFFh

A8000h-AFFFFh

B0000h-B7FFFh

B8000h-BFFFFh

C0000h-C7FFFh

C8000h-CFFFFh

D0000h-D7FFFh

D8000h-DFFFFh

E0000h-E7FFFh

E8000h-EFFFFh

F0000h-F7FFFh

F8000h-FFFFFh

8/4

SA2

8/4

SA3

8/4

SA4

8/4

SA5

8/4

SA6

8/4

SA7

8/4

SA8

64/32

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

Note: The address range is A19:A-1 in byte mode (BYTE#=V_IL) or A19:A0 in word mode (BYTE#=V_IH). The bank address bits are A19 and A18 for

Am29DS163DB.

Table 6. SecSi Sector Addresses for Bottom Boot Devices

Sector Address

A19–A12

(x8)

(x16)

Address Range

SecSi Sector

Entire Sector

Size

Address Range

00000XXX

64 Kbytes/32 Kwords

16 bytes/8 words

000000h-00FFFFh 00000h-07FFFh

000000h-00000Fh 00000h–00007h

Factory Programmed ESN

14

Am29DS163D

A D V A N C E I N F O R M A T I O N

Table 7. In addition, when verifying sector protection,

Autoselect Mode

the sector address must appear on the appropriate

highest order address bits (see Tables 3–6). Table 7

shows the remaining address bits that are don’t care.

When all necessary bits are set as required, the pro-

gramming equipment may then read the

corresponding identifier code on DQ7–DQ0.

The autoselect mode provides manufacturer and de-

vice identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This

mode is primarily intended for programming equip-

ment to automatically match a device to be

programmed with its corresponding programming al-

gorithm. However, the autoselect codes can also be

accessed in-system through the command register.

To access the autoselect codes in-system, the host

system can issue the autoselect command via the

command register, as shown in Table 14. This method

does not require V_ID. Refer to the Autoselect Com-

mand Sequence section for more information.

When using programming equipment, the autoselect

mode requires V_ID(9.0 V to 11.0 V) on address pin A9.

Address pins A6, A1, and A0 must be as shown in

Table 7. Am29DS163D Autoselect Codes (High Voltage Method)

DQ8 to DQ15

A19

to

A11

to

A8

to

A5

to

DQ7

to

BYTE# BYTE#

Description

CE# OE# WE# A12

A10 A9 A7 A6 A2 A1 A0

= V_IH

= V_IL

DQ0

V_ID

Manufacturer ID: AMD

Device ID: Am29DS163D

L

H

BA

X

L

X

L

X

01h

H

22h

X

95h (T), 96h (B)

Sector Protection

Verification

01h (protected),

00h (unprotected)

V_ID

L

H

SA

BA

X

L

X

H

L

X

85h (factory locked),

05h (not factory

locked)

SecSi Sector Indicator Bit

(DQ7)

H

Legend: T = Top Boot Block, B = Bottom Boot Block, L = Logic Low = V_IL, H = Logic High = V_IH, BA = Bank Address, SA =

Sector Address, X = Don’t care.

Am29DS163D

15

A D V A N C E I N F O R M A T I O N

Table 9. Bottom Boot Sector/Sector Block

Addresses for Protection/Unprotection

Sector/Sector Block Protection and

Unprotection

Sector / Sector

Block

(Note: For the following discussion, the term “sector”

applies to both sectors and sector blocks. A sector

block consists of two or more adjacent sectors that are

protected or unprotected at the same time (see Tables

8 and 9).

A19–A12

Sector / Sector Block Size

SA38

11111XXX

64 Kbytes

11110XXX,

11101XXX,

11100XXX

SA37-SA35

192 (3x64) Kbytes

SA34-SA31

SA30-SA27

SA26-SA23

SA22-SA19

SA18-SA15

SA14-SA11

110XXXXX

101XXXXX

100XXXXX

011XXXXX

010XXXXX

001XXXXX

256 (4x64) Kbytes

Table 8. Top Boot Sector/Sector Block Addresses

for Protection/Unprotection

Sector / Sector

Block

A19–A12

Sector / Sector Block Size

SA0

00000XXX

64 Kbytes

00001XXX,

00010XXX,

00011XXX

SA1-SA3

192 (3x64) Kbytes

00001XXX,

00010XXX,

00011XXX

SA10-SA8

192 (3x64) Kbytes

SA4-SA7

SA8-SA11

SA12-SA15

SA16-SA19

SA20-SA23

SA24-SA27

001XXXXX

010XXXXX

011XXXXX

100XXXXX

101XXXXX

110XXXXX

256 (4x64) Kbytes

SA7

SA6

SA5

SA4

SA3

SA2

SA1

SA0

00000111

00000110

00000101

00000100

00000011

00000010

00000001

00000000

8 Kbytes

11100XXX,

11101XXX,

11110XXX

SA28-SA30

192 (3x64) Kbytes

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

11111000

11111001

11111010

11111011

11111100

11111101

11111110

11111111

8 Kbytes

The hardware sector protection feature disables both

program and erase operations in any sector. The hard-

ware sector unprotection feature re-enables both

program and erase operations in previously protected

sectors. Sector protection and unprotection can be im-

plemented via two methods.

The primary method requires V_IDon the RESET# pin

only, and can be implemented either in-system or via

programming equipment. Figure 2 shows the algo-

rithms and Figure 25 shows the timing diagram. This

method uses standard microprocessor bus cycle tim-

ing. For sector unprotect, all unprotected sectors must

first be protected prior to the first sector unprotect

write cycle.

16

Am29DS163D

A D V A N C E I N F O R M A T I O N

The alternate method intended only for programming

block consists of two or more adjacent sectors that are

protected or unprotected at the same time (see Tables

8 and 9).

equipment requires V_IDon address pin A9 and OE#.

This method is compatible with programmer routines

written for earlier 1.8 volt-only AMD flash devices.

Contact an AMD representative for further details.

This feature allows temporary unprotection of previ-

ously protected sectors to change data in-system. The

Sector Unprotect mode is activated by setting the RE-

SET# pin to V_ID(9.0 – 11.0 V). During this mode,

formerly protected sectors can be programmed or

erased by selecting the sector addresses. Once V_IDis

removed from the RESET# pin, all the previously pro-

tected sectors are protected again. Figure 1 shows the

algorithm, and Figure 24 shows the timing diagrams,

for this feature.

The device is shipped with all sectors unprotected.

AMD offers the option of programming and protecting

sectors at its factory prior to shipping the device

through AMD’s ExpressFlash™ Service. Contact an

AMD representative for details.

It is possible to determine whether a sector is pro-

tected or unprotected. See the Autoselect Mode

section for details.

Write Protect (WP#)

The Write Protect function provides a hardware

method of protecting certain boot sectors without

using V_ID. This function is one of two provided by the

WP#/ACC pin.

START

If the system asserts V_ILon the WP#/ACC pin, the de-

vice disables program and erase functions in the two

“outermost” 8 Kbyte boot sectors independently of

whether those sectors were protected or unprotected

using the method described in “Sector/Sector Block

Protection and Unprotection”. The two outermost 8

Kbyte boot sectors are the two sectors containing the

lowest addresses in a bottom-boot-configured device,

or the two sectors containing the highest addresses in

a top-boot-configured device.

RESET# = V_ID

(Note 1)

Perform Erase or

Program Operations

RESET# = V_IH

If the system asserts V_IHon the WP#/ACC pin, the de-

vice reverts to whether the two outermost 8 Kbyte boot

sectors were last set to be protected or unprotected.

That is, sector protection or unprotection for these two

sectors depends on whether they were last protected

or unprotected using the method described in “Sec-

tor/Sector Block Protection and Unprotection”.

Temporary Sector

Unprotect Completed

(Note 2)

Notes:

1. All protected sectors unprotected (If WP#/ACC = V_IL,

outermost boot sectors will remain protected).

Note that the WP#/ACC pin must not be left floating or

unconnected; inconsistent behavior of the device may

result.

2. All previously protected sectors are protected once

again.

Temporary Sector/Sector Block Unprotect

(Note: For the following discussion, the term “sector”

applies to both sectors and sector blocks. A sector

Figure 1. Temporary Sector Unprotect Operation

Am29DS163D

17

A D V A N C E I N F O R M A T I O N

START

Protect all sectors:

PLSCNT = 1

The indicated portion

of the sector protect

algorithm must be

performed for all

unprotected sectors

prior to issuing the

first sector

RESET# = V_ID

Wait 1 µs

unprotect address

No

First Write

No

First Write

Cycle = 60h?

Temporary Sector

Unprotect Mode

Temporary Sector

Unprotect Mode

Cycle = 60h?

Yes

Set up sector

address

No

All sectors

protected?

Sector Protect:

Write 60h to sector

address with

A6 = 0, A1 = 1,

A0 = 0

Yes

Set up first sector

address

Sector Unprotect:

Wait 150 µs

Write 60h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Verify Sector

Protect: Write 40h

to sector address

with A6 = 0,

Reset

PLSCNT = 1

Increment

PLSCNT

Wait 15 ms

A1 = 1, A0 = 0

Verify Sector

Unprotect: Write

40h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector address

with A6 = 0,

A1 = 1, A0 = 0

Increment

PLSCNT

No

PLSCNT

= 25?

Read from

sector address

with A6 = 1,

Data = 01h?

Yes

A1 = 1, A0 = 0

No

Yes

Set up

next sector

address

Yes

No

PLSCNT

= 1000?

Protect another

sector?

Data = 00h?

Yes

Device failed

No

Yes

Remove V_ID

from RESET#

No

Last sector

verified?

Device failed

Write reset

command

Yes

Remove V_ID

Sector Unprotect

Algorithm

from RESET#

Sector Protect

Algorithm

Sector Protect

complete

Write reset

command

Sector Unprotect

complete

Note: The term “sector” in the figure applies to both sectors and sector blocks.

Figure 2. In-System Sector/Sector Block Protect and Unprotect Algorithms

18

Am29DS163D

A D V A N C E I N F O R M A T I O N

In devices that have an ESN, a Bottom Boot device

SecSi (Secured Silicon) Sector Flash

Memory Region

has the 16-byte ESN at addresses 00000h–00007h in

word mode (or 000000h–00000Fh in byte mode). In

the Top Boot device the starting address of the ESN is

at addresses F8000h–F8007h in word mode (or

1F0000h–1F000Fh in byte mode).

The SecSi (Secured Silicon) Sector feature provides

an additional 64Kbyte Flash memory region that en-

ables permanent part identification through an

Electronic Serial Number (ESN). An SecSi Sector Indi-

cator Bit indicates whether or not the SecSi Sector is

locked when shipped from the factory. This bit is per-

manently set at the factory and cannot be changed,

which prevents cloning of a factory locked part. This

ensures the security of the ESN once the product is

shipped to the field.

Customers may opt to have their code programmed by

AMD through the AMD ExpressFlash service. AMD

programs the customer’s code, with or without the ran-

dom ESN. The devices are then shipped from AMD’s

factory with the permanently locked. Contact an AMD

representative for details on using AMD’s Express-

Flash service.

AMD offers the device with the SecSi Sector either

factory locked or customer lockable. The fac-

tory-locked version is always protected when shipped

from the factory, and the SecSi Sector Indicator Bit is

permanently set to a “1.” The customer-lockable ver-

sion is shipped with the unprotected, allowing

customers to utilize the that sector in any manner they

choose. In the customer-lockable version, the SecSi

Sector Indicator Bit is permanently set to a “0.” Thus,

the SecSi Sector Indicator Bit prevents customer-lock-

able devices from being used to replace devices that

are factory locked.

Customer Lockable: SecSi Sector NOT

Programmed or Protected at the Factory

If the security feature is not required, the SecSi Sector

can be treated as an additional Flash memory space,

expanding the size of the available Flash array by 64

Kbytes. The SecSi Sector can be read, programmed,

and erased as often as required. The SecSi Sector area

can be protected using one of the following procedures:

■ Write the three-cycle Enter SecSi Sector Region

command sequence, and then follow the in-system

sector protect algorithm as shown in Figure 2, ex-

cept that RESET# may be at either V_IHor V_ID. This

allows in-system protection of the without raising

any device pin to a high voltage. Note that this

method is only applicable to the SecSi Sector.

The system accesses the SecSi Sector through a

command sequence (see “Enter SecSi Sector/Exit

SecSi Sector Command Sequence” on page 24). After

the system writes the Enter SecSi Sector command

sequence, it may read the SecSi Sector by using the

addresses normally occupied by the boot sectors. This

mode of operation continues until the system issues

the Exit SecSi Sector command sequence, or until

power is removed from the device. On power-up, or

following a hardware reset, the device reverts to send-

ing commands to the boot sectors.

■ Write the three-cycle Enter SecSi Sector Region

command sequence, and then use the alternate

method of sector protection described in “Sec-

tor/Sector Block Protection and Unprotection” on

page 16.

Once the SecSi Sector is locked and verified, the sys-

tem must write the Exit SecSi Sector Region

command sequence to return to reading and writing

the remainder of the array.

The following restrictions apply to using the SecSi

Sector: Once the device enters the SecSi Sector, any

attempt to initiate program or erase operations in the

array is ignored until the device exits the SecSi Sector.

Conversely, when a program or erase operation in the

array is in progress, the device ignores any attempt to

enter the SecSi Sector until programming or erasing is

complete.

The SecSi Sector protection must be used with cau-

tion since, once protected, there is no procedure

available for unprotecting the SecSi Sector area and

none of the bits in the SecSi Sector memory space

can be modified in any way. Note also that the multiple

program and erase capability of the customer lockable

version of this device may be subject to change on fu-

ture device revisions.

Factory Locked: SecSi Sector Programmed

and Protected at the Factory

In a factory locked device, the SecSi Sector is pro-

tected when the device is shipped from the factory.

The SecSi Sector cannot be modified in any way. The

device is available preprogrammed with one of the

following:

Hardware Data Protection

The command sequence requirement of unlock cycles

for programming or erasing provides data protection

against inadvertent writes (refer to Table 14 on

page 27 for command definitions). In addition, the fol-

lowing hardware data protection measures prevent

accidental erasure or programming, which might oth-

erwise be caused by spurious system level signals

■ A random, secure ESN only

■ Customer code through the ExpressFlash service

■ Both a random, secure ESN and customer code

through the ExpressFlash service.

Am29DS163D

19

A D V A N C E I N F O R M A T I O N

during V_CCpower-up and power-down transitions, or

The Common Flash Interface (CFI) specification out-

lines device and host system software interrogation

handshake, which allows specific vendor-specified

software algorithms to be used for entire families of

devices. Software support can then be device-inde-

pendent, JEDEC ID-independent, and forward- and

backward-compatible for the specified flash device

families. Flash vendors can standardize their existing

interfaces for long-term compatibility.

from system noise.

Low V_CCWrite Inhibit

When V_CCis less than V_LKO, the device does not ac-

cept any write cycles. This protects data during V_CC

power-up and power-down. The command register

and all internal program/erase circuits are disabled,

and the device resets to reading array data. Subse-

quent writes are ignored until V_CCis greater than V_LKO

The system must provide the proper signals to the

control pins to prevent unintentional writes when V_CC

.

This device enters the CFI Query mode when the sys-

tem writes the CFI Query command, 98h, to address

55h in word mode (or address AAh in byte mode), any

time the device is ready to read array data. The sys-

tem can read CFI information at the addresses given

in Table 10 on page 20 to Table 13 on page 22. To ter-

minate reading CFI data, the system must write the

reset command.

is greater than V_LKO

.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE#

or WE# do not initiate a write cycle.

The system can also write the CFI query command

when the device is in the autoselect mode. The device

enters the CFI query mode, and the system can read

CFI data at the addresses given in Table 10 on

page 20 to Table 13 on page 22. The system must

write the reset command to return the device to the

autoselect mode.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# =

V_IL, CE# = V_IHor WE# = V_IH. To initiate a write cycle,

CE# and WE# must be a logical zero while OE# is a

logical one.

Power-Up Write Inhibit

For further information, please refer to the CFI Specifi-

cation and CFI Publication 100, available via the

World Wide Web at http://www.amd.com/prod-

ucts/nvd/overview/cfi.html. Alternatively, contact an

AMD representative for copies of these documents.

If WE# = CE# = V_ILand OE# = V_IHduring power up,

the device does not accept commands on the rising

edge of WE#. The internal state machine is automati-

cally reset to reading array data on power-up.

COMMON FLASH MEMORY INTERFACE

(CFI)

Table 10. CFI Query Identification String

Addresses

(Word Mode)

(Byte Mode)

Data

Description

10h

11h

12h

20h

22h

24h

0051h

0052h

0059h

Query Unique ASCII string “QRY”

13h

14h

26h

28h

0002h

0000h

Primary OEM Command Set

15h

16h

2Ah

2Ch

0040h

0000h

Address for Primary Extended Table

17h

18h

2Eh

30h

0000h

Alternate OEM Command Set (00h = none exists)

Address for Alternate OEM Extended Table (00h = none exists)

19h

1Ah

32h

34h

0000h

20

Am29DS163D

A D V A N C E I N F O R M A T I O N

Table 11. System Interface String

Addresses

(Word Mode)

(Byte Mode)

Data

Description

V_CCMin. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

1Bh

1Ch

36h

38h

0018h

V_CCMax. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

0022h

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

3Ah

3Ch

3Eh

40h

42h

44h

46h

48h

4Ah

4Ch

0000h

0004h

0000h

000Ah

0000h

0005h

0000h

0004h

0000h

V_PPMin. voltage (00h = no V_PPpin present)

V_PPMax. voltage (00h = no V_PPpin present)

Typical timeout per single byte/word write 2^Nµs

Typical timeout for Min. size buffer write 2^Nµs (00h = not supported)

Typical timeout per individual block erase 2^Nms

Typical timeout for full chip erase 2^Nms (00h = not supported)

Max. timeout for byte/word write 2^Ntimes typical

Max. timeout for buffer write 2^Ntimes typical

Max. timeout per individual block erase 2^Ntimes typical

Max. timeout for full chip erase 2^Ntimes typical (00h = not supported)

Table 12. Device Geometry Definition

Addresses

(Word Mode)

(Byte Mode)

Data

Description

27h

4Eh

0015h

Device Size = 2^Nbyte

28h

29h

50h

52h

0002h

0000h

Flash Device Interface description (refer to CFI publication 100)

2Ah

2Bh

54h

56h

0000h

Max. number of byte in multi-byte write = 2^N

(00h = not supported)

2Ch

58h

0002h

Number of Erase Block Regions within device

2Dh

2Eh

2Fh

30h

5Ah

5Ch

5Eh

60h

0007h

0000h

0020h

0000h

Erase Block Region 1 Information

(refer to the CFI specification or CFI publication 100)

31h

32h

33h

34h

62h

64h

66h

68h

001Eh

0000h

0001h

Erase Block Region 2 Information

Erase Block Region 3 Information

Erase Block Region 4 Information

35h

36h

37h

38h

6Ah

6Ch

6Eh

70h

0000h

39h

3Ah

3Bh

3Ch

72h

74h

76h

78h

0000h

Am29DS163D

21

A D V A N C E I N F O R M A T I O N

Table 13. Primary Vendor-Specific Extended Query

Addresses

(Word Mode)

(Byte Mode)

Data

Description

40h

41h

42h

80h

82h

84h

0050h

0052h

0049h

Query-unique ASCII string “PRI”

43h

44h

86h

88h

0031h

0032h

Major version number, ASCII

Minor version number, ASCII

Address Sensitive Unlock (Bits 1-0)

0 = Required, 1 = Not Required

45h

8Ah

0000h

Silicon Revision Number (Bits 7-2)

Erase Suspend

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

46h

47h

48h

49h

4Ah

4Bh

4Ch

8Ch

8Eh

90h

92h

94h

96h

98h

0002h

0001h

0004h

Sector Protect

0 = Not Supported, X = Number of sectors in per group

Sector Temporary Unprotect

00 = Not Supported, 01 = Supported

Sector Protect/Unprotect scheme

04 = 29LV800 mode

00XXh

(See Note)

Simultaneous Operation

00 = Not Supported, X= Number of Sectors in Bank 2 (Uniform Bank)

Burst Mode Type

00 = Not Supported, 01 = Supported

0000h

Page Mode Type

00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

ACC (Acceleration) Supply Minimum

4Dh

4Eh

4Fh

9Ah

9Ch

9Eh

0085h

0095h

000Xh

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

ACC (Acceleration) Supply Maximum

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

Top/Bottom Boot Sector Flag

02h = Bottom Boot Device, 03h = Top Boot Device

Note:

The number of sectors in Bank 2 is device dependent.

Am29DS163 = 18h

22

Am29DS163D

A D V A N C E I N F O R M A T I O N

COMMAND DEFINITIONS

Writing specific address and data commands or se-

quences into the command register initiates device

operations. Table 14 on page 27 defines the valid reg-

ister command sequences. Writing incorrect address

and data values or writing them in the improper se-

quence resets the device to reading array data.

command returns that bank to the erase-sus-

pend-read mode. Once programming begins, however,

the device ignores reset commands until the operation

is complete.

The reset command may be written between the se-

quence cycles in an autoselect command sequence.

Once in the autoselect mode, the reset command

must be written to return to reading array data. If a

bank entered the autoselect mode while in the Erase

Suspend mode, writing the reset command returns

that bank to the erase-suspend-read mode.

All addresses are latched on the falling edge of WE#

or CE#, whichever happens later. All data is latched on

the rising edge of WE# or CE#, whichever happens

first. Refer to the AC Characteristics section for timing

diagrams.

If DQ5 goes high during a program or erase operation,

writing the reset command returns the banks to read-

ing array data (or erase-suspend-read mode if that

bank was in Erase Suspend).

Reading Array Data

The device is automatically set to reading array data

after device power-up. No commands are required to

retrieve data. Each bank is ready to read array data

after completing an Embedded Program or Embedded

Erase algorithm.

Autoselect Command Sequence

The autoselect command sequence allows the host

system to access the manufacturer and device codes,

and determine whether or not a sector is protected.

Table 14 on page 27 shows the address and data re-

quirements. This method is an alternative to that

shown in Table 7 on page 15, which is intended for

PROM programmers and requires V_IDon address pin

A9. The autoselect command sequence may be writ-

ten to an address within a bank that is either in the

read or erase-suspend-read mode. The autoselect

command may not be written while the device is ac-

tively programming or erasing in the other bank.

After the device accepts an Erase Suspend command,

the corresponding bank enters the erase-sus-

pend-read mode, after which the system can read

data from any non-erase-suspended sector within the

same bank. After completing a programming operation

in the Erase Suspend mode, the system may once

again read array data with the same exception. See

the “Erase Suspend/Erase Resume Commands” on

page 26 section for more information.

The system must issue the reset command to return a

bank to the read (or erase-suspend-read) mode if DQ5

goes high during an active program or erase opera-

tion, or if the bank is in the autoselect mode. See the

next section, “Reset Command", for more information.

The autoselect command sequence is initiated by first

writing two unlock cycles. This is followed by a third

write cycle that contains the bank address and the

autoselect command. The bank then enters the

autoselect mode. The system may read at any address

within the same bank any number of times without ini-

tiating another autoselect command sequence. The fol-

lowing table describes the hex address requirements

for the various autoselect functions, and the resulting

data. BA represents the bank address, and SA repre-

sents the sector address.

See also “Requirements for Reading Array Data” on

page 10 for more information. Table on page 36 pro-

vides the read parameters, and Figure 13, on page 36

shows the timing diagram.

Reset Command

Writing the reset command resets the banks to the

read or erase-suspend-read mode. Address bits are

don’t cares for this command.

Word

Address

Byte

Address

Description

Read Data*

The reset command may be written between the se-

quence cycles in an erase command sequence before

erasing begins. This resets the bank to which the sys-

tem was writing to reading array data. Once erasure

begins, however, the device ignores reset commands

until the operation is complete.

Manufacturer

ID

(BA) + 00 (BA) + 00

(BA) + 01 (BA) + 02

(SA) + 02 (SA) + 04

01

2295 (top boot)

2296 (bottom boot)

Device ID

Sector Block

Protect Verify

00 (unlocked),

01 (locked)

The reset command may be written between the

sequence cycles in a program command sequence

before programming begins. This resets the bank to

which the system was writing to reading array data. If

the program command sequence is written to a bank

that is in the Erase Suspend mode, writing the reset

SecSi Sector

Factory

Protect

85 (factory locked)

05 (not factory locked)

(BA) + 03 (BA) + 06

* For byte mode, ignore data output bits D8–DQ15.

Am29DS163D

23

A D V A N C E I N F O R M A T I O N

The system must write the reset command to return to

reading array data (or erase-suspend-read mode if the

bank was previously in Erase Suspend).

cause that bank to set DQ5 = 1, or cause the DQ7 and

DQ6 status bits to indicate the operation was success-

ful. However, a succeeding read shows that the data is

still “0.” Only erase operations can convert a “0” to a

“1.”

Enter SecSi Sector/Exit SecSi Sector

Command Sequence

Unlock Bypass Command Sequence

The system can access the SecSi Sector region by is-

suing the three-cycle Enter SecSi Sector command

sequence. The device continues to access the SecSi

Sector region until the system issues the four-cycle

Exit SecSi Sector command sequence. The Exit SecSi

Sector command sequence returns the device to nor-

mal operation. Table 14 on page 27 shows the

address and data requirements for both command se-

quences. See also “SecSi (Secured Silicon) Sector

Flash Memory Region” on page 19 for further informa-

tion. Note that a hardware reset (RESET#=V_IL) resets

the device to reading array data.

The unlock bypass feature allows the system to pro-

gram bytes or words to a bank faster than using the

standard program command sequence. The unlock

bypass command sequence is initiated by first writing

two unlock cycles. This is followed by a third write

cycle containing the unlock bypass command, 20h.

That bank then enters the unlock bypass mode. A

two-cycle unlock bypass program command sequence

is all that is required to program in this mode. The first

cycle in this sequence contains the unlock bypass pro-

gram command, A0h; the second cycle contains the

program address and data. Additional data is pro-

grammed in the same manner. This mode dispenses

with the initial two unlock cycles required in the stan-

dard program command sequence, resulting in faster

total programming time. Table 14 on page 27 shows

the requirements for the command sequence.

Byte/Word Program Command Sequence

The system may program the device by word or byte,

depending on the state of the BYTE# pin. Program-

ming is a four-bus-cycle operation. The program

command sequence is initiated by writing two unlock

write cycles, followed by the program set-up com-

mand. The program address and data are written next,

which in turn initiate the Embedded Program algo-

rithm. The system is not required to provide further

controls or timings. The device automatically provides

internally generated program pulses and verifies the

programmed cell margin. Table 14 on page 27 shows

the address and data requirements for the byte pro-

gram command sequence.

During the unlock bypass mode, only the Unlock By-

pass Program and Unlock Bypass Reset commands

are valid. To exit the unlock bypass mode, the system

must issue the two-cycle unlock bypass reset com-

mand sequence. The first cycle must contain the bank

address and the data 90h. The second cycle need

only contain the data 00h. The bank then returns to the

reading array data.

The device offers accelerated program operations

through the WP#/ACC pin. When the system asserts

V_HHon the WP#/ACC pin, the device automatically en-

ters the Unlock Bypass mode. The system may then

write the two-cycle Unlock Bypass program command

sequence. The device uses the higher voltage on the

WP#/ACC pin to accelerate the operation. Note that

the WP#/ACC pin must not be at V_HHany operation

other than accelerated programming, or device dam-

age may result. In addition, the WP#/ACC pin must not

be left floating or unconnected; inconsistent behavior

of the device may result.

When the Embedded Program algorithm is complete,

that bank then returns to reading array data and ad-

dresses are no longer latched. The system can

determine the status of the program operation by

using DQ7, DQ6, or RY/BY#. Refer to “Write Opera-

tion Status” on page 28 for information on these status

bits.

Any commands written to the device during the Em-

bedded Program Algorithm are ignored. Note that a

hardware reset immediately terminates the program

operation. The program command sequence should

be reinitiated once that bank returns to reading array

data, to ensure data integrity.

Figure 3, on page 25 illustrates the algorithm for the

program operation. Refer to the “Erase and Program

Operations” on page 39 for parameters, and Figure

17, on page 40 for timing diagrams.

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed

from “0” back to a “1.” Attempting to do so may

24

Am29DS163D

A D V A N C E I N F O R M A T I O N

Any commands written during the chip erase operation

are ignored. However, note that a hardware reset im-

mediately terminates the erase operation. If that

occurs, the chip erase command sequence should be

reinitiated once that bank returns to reading array

data, to ensure data integrity.

START

Figure 4, on page 26 illustrates the algorithm for the

erase operation. Refer to the “Erase and Program Op-

erations” on page 39 tables in the AC Characteristics

section for parameters, and Figure 19, on page 41

section for timing diagrams.

Write Program

Command Sequence

Data Poll

from System

Embedded

Program

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector

erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two ad-

ditional unlock cycles are written, and are then

followed by the address of the sector to be erased,

and the sector erase command. Table 14 on page 27

shows the address and data requirements for the sec-

tor erase command sequence.

algorithm

in progress

Verify Data?

Yes

No

Increment Address

Last Address?

Yes

The device does not require the system to preprogram

prior to erase. The Embedded Erase algorithm auto-

matically programs and verifies the entire memory for

an all zero data pattern prior to electrical erase. The

system is not required to provide any controls or tim-

ings during these operations.

Programming

Completed

After the command sequence is written, a sector erase

time-out of 50 µs occurs. During the time-out period,

additional sector addresses and sector erase com-

mands may be written. Loading the sector erase buffer

may be done in any sequence, and the number of sec-

tors may be from one sector to all sectors. The time

between these additional cycles must be less than

50 µs, otherwise erasure may begin. Any sector erase

address and command following the exceeded

time-out may or may not be accepted. It is recom-

mended that processor interrupts be disabled during

this time to ensure all commands are accepted. The

interrupts can be re-enabled after the last Sector

Erase command is written. Any command other than

Sector Erase or Erase Suspend during the

time-out period resets that bank to reading array

data. The system must rewrite the command se-

quence and any additional addresses and commands.

Note: See Table 14 for program command sequence.

Figure 3. Program Operation

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase

command sequence is initiated by writing two unlock

cycles, followed by a set-up command. Two additional

unlock write cycles are then followed by the chip erase

command, which in turn invokes the Embedded Erase

algorithm. The device does not require the system to

preprogram prior to erase. The Embedded Erase algo-

rithm automatically preprograms and verifies the entire

memory for an all zero data pattern prior to electrical

erase. The system is not required to provide any con-

trols or timings during these operations. Table 14

shows the address and data requirements for the chip

erase command sequence.

The system can monitor DQ3 to determine if the sec-

tor erase timer timed out (See the section on “DQ3:

Sector Erase Timer” on page 30.). The time-out begins

from the rising edge of the final WE# pulse in the com-

mand sequence.

When the Embedded Erase algorithm is complete,

that bank returns to reading array data and addresses

are no longer latched. The system can determine the

status of the erase operation by using DQ7, DQ6,

DQ2, or RY/BY#. Refer to the Write Operation Status

section for information on these status bits.

When the Embedded Erase algorithm is complete, the

bank returns to reading array data and addresses are

no longer latched. Note that while the Embedded

Erase operation is in progress, the system can read

data from the non-erasing bank. The system can de-

Am29DS163D

25

A D V A N C E I N F O R M A T I O N

termine the status of the erase operation by reading

mode. The system can determine the status of the

program operation using the DQ7 or DQ6 status bits,

just as in the standard Byte Program operation.

Refer to the “Write Operation Status” on page 28 sec-

tion for more information.

DQ7, DQ6, DQ2, or RY/BY# in the erasing bank.

Refer to “Write Operation Status” on page 28 for infor-

mation on these status bits.

Once the sector erase operation starts, only the Erase

Suspend command is valid. All other commands are

ignored. However, note that a hardware reset imme-

diately terminates the erase operation. If that occurs,

the sector erase command sequence should be reiniti-

ated once that bank returns to reading array data, to

ensure data integrity.

In the erase-suspend-read mode, the system can also

issue the autoselect command sequence. Refer to the

“Autoselect Mode” on page 15 and “Autoselect Com-

mand Sequence” on page 23 sections for details.

To resume the sector erase operation, the system

must write the Erase Resume command. The bank

address of the erase-suspended bank is required

when writing this command. Further writes of the Re-

sume command are ignored. Another Erase Suspend

command can be written after the chip resumes

erasing.

Figure 4 illustrates the algorithm for the erase opera-

tion. Refer to the “Erase and Program Operations” on

page 39 for parameters, and Figure 19, on page 41

section for timing diagrams.

Erase Suspend/Erase Resume

Commands

The Erase Suspend command, B0h, allows the sys-

tem to interrupt a sector erase operation and then read

data from, or program data to, any sector not selected

for erasure. The bank address is required when writing

this command. This command is valid only during the

sector erase operation, including the 50 µs time-out

period during the sector erase command sequence.

The Erase Suspend command is ignored if written dur-

ing the chip erase operation or Embedded Program

algorithm.

START

Write Erase

Command Sequence

(Notes 1, 2)

When the Erase Suspend command is written during

the sector erase operation, the device requires a max-

imum of 20 µs to suspend the erase operation.

However, when the Erase Suspend command is writ-

ten during the sector erase time-out, the device

immediately terminates the time-out period and sus-

pends the erase operation.

Data Poll to Erasing

Bank from System

Embedded

Erase

algorithm

in progress

No

Data = FFh?

After the erase operation is suspended, the bank en-

ters the erase-suspend-read mode. The system can

read data from or program data to any sector not se-

lected for erasure. (The device “erase suspends” all

sectors selected for erasure.) Reading at any address

within erase-suspended sectors produces status infor-

mation on DQ7–DQ0. The system can use DQ7, or

DQ6 and DQ2 together, to determine if a sector is ac-

tively erasing or is erase-suspended. Refer to the

“Write Operation Status” on page 28 section for infor-

mation on these status bits.

Yes

Erasure Completed

Notes:

1. See Table 14 on page 27 for erase command

sequence.

2. See the section on DQ3 for information on the sector

erase timer.

After an erase-suspended program operation is com-

plete, the bank returns to the erase-suspend-read

Figure 4. Erase Operation

26

Am29DS163D

A D V A N C E I N F O R M A T I O N

Table 14. Am29DS163D Command Definitions

Bus Cycles (Notes 2–5)

Command

Sequence

(Note 1)

First

Second

Third

Addr

Fourth

Fifth

Sixth

Addr Data Addr Data

Data

Addr

Data

Addr Data Addr Data

Read (Note 6)

Reset (Note 7)

1

RA

XXX

555

AAA

555

AAA

555

AAA

555

AAA

555

AAA

555

AAA

555

AAA

555

AAA

XXX

BA

RD

F0

Word

Byte

Word

Byte

Word

Byte

Word

Byte

Word

Byte

Word

Byte

Word

Byte

Word

Byte

2AA

555

2AA

555

2AA

555

2AA

555

2AA

555

2AA

555

2AA

555

2AA

555

PA

(BA)555

(BA)AAA

(BA)555

(BA)AAA

(BA)555

(BA)AAA

(BA)555

(BA)AAA

555

Manufacturer ID

4

3

4

3

AA

55

90 (BA)X00

01

(BA)X01

90

(see

Table 7)

Device ID

(BA)X02

(BA)X03

90

SecSi Sector Factory

Protect (Note 9)

85/05

00/01

(BA)X06

(SA)X02

90

Sector Protect Verify

(Note 10)

(SA)X04

Enter SecSi Sector Region

Exit SecSi Sector Region

Program

88

AAA

555

90

A0

20

XXX

PA

00

AAA

555

PD

AAA

555

Unlock Bypass

AAA

Unlock Bypass Program (Note 11)

Unlock Bypass Reset (Note 12)

2

A0

90

PD

00

XXX

2AA

555

2AA

555

Word

555

AAA

555

AAA

BA

555

AAA

555

AAA

555

2AA

555

2AA

555

Chip Erase

6

AA

55

80

AA

55

10

30

Byte

Word

Byte

AAA

Sector Erase

SA

AAA

Erase Suspend (Note 13)

Erase Resume (Note 14)

1

B0

30

BA

Word

Byte

55

CFI Query (Note 15)

1

98

AA

Legend:

X = Don’t care

PD = Data to be programmed at location PA. Data latches on the rising

edge of WE# or CE# pulse, whichever happens first.

RA = Address of the memory location to be read.

RD = Data read from location RA during read operation.

SA = Address of the sector to be verified (in autoselect mode) or

erased. Address bits A19–A12 uniquely select any sector.

BA = Address of the bank that is being switched to autoselect mode, is

in bypass mode, or is being erased.

PA = Address of the memory location to be programmed. Addresses

latch on the falling edge of the WE# or CE# pulse, whichever happens

later.

Notes:

1. See Table 1 on page 10 for description of bus operations.

9. The data is 85h for factory locked and 05h for not factory locked.

2. All values are in hexadecimal.

10. The data is 00h for an unprotected sector/sector block and 01h for

a protected sector/sector block.

3. Except for the read cycle and the fourth cycle of the autoselect

command sequence, all bus cycles are write cycles.

11. The Unlock Bypass command is required prior to the Unlock

Bypass Program command.

4. Data bits DQ15–DQ8 are don’t care in command sequences,

except for RD and PD.

12. The Unlock Bypass Reset command is required to return to

reading array data when the bank is in the unlock bypass mode.

5. Unless otherwise noted, address bits A19–A11 are don’t cares.

13. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode.

The Erase Suspend command is valid only during a sector erase

operation, and requires the bank address.

6. No unlock or command cycles required when bank is in read

mode.

7. The Reset command is required to return to reading array data

(or to the erase-suspend-read mode if previously in Erase

Suspend) when a bank is in the autoselect mode, or if DQ5 goes

high (while the bank is providing status information).

14. The Erase Resume command is valid only during the Erase

Suspend mode, and requires the bank address.

15. Command is valid when device is ready to read array data or when

device is in autoselect mode.

8. The fourth cycle of the autoselect command sequence is a read

cycle. The system must provide the bank address to obtain the

manufacturer ID, device ID, or SecSi Sector factory protect

information. Data bits DQ15–DQ8 are don’t care. See the

“Autoselect Command Sequence” on page 23 section for

more information.

Am29DS163D

27

A D V A N C E I N F O R M A T I O N

WRITE OPERATION STATUS

The device provides several bits to determine the sta-

tus of a program or erase operation: DQ2, DQ3, DQ5,

DQ6, and DQ7. Table 15 on page 31 and the following

subsections describe the function of these bits. DQ7

and DQ6 each offer a method for determining whether

a program or erase operation is complete or in

progress. The device also provides a hardware-based

output signal, RY/BY#, to determine whether an Em-

bedded Program or Erase operation is in progress or

is completed.

invalid. Valid data on DQ0–DQ7 appears on succes-

sive read cycles.

Table 15 on page 31 shows the outputs for Data# Poll-

ing on DQ7. Figure 5 shows the Data# Polling

algorithm. Figure 21, on page 42 shows the Data#

Polling timing diagram.

START

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host sys-

tem whether an Embedded Program or Erase

algorithm is in progress or completed, or whether a

bank is in Erase Suspend. Data# Polling is valid after

the rising edge of the final WE# pulse in the command

sequence.

Read DQ7–DQ0

Addr = VA

Yes

DQ7 = Data?

During the Embedded Program algorithm, the device

outputs on DQ7 the complement of the datum pro-

grammed to DQ7. This DQ7 status also applies to

programming during Erase Suspend. When the Em-

bedded Program algorithm is complete, the device

outputs the datum programmed to DQ7. The system

must provide the program address to read valid status

information on DQ7. If a program address falls within a

protected sector, Data# Polling on DQ7 is active for

approximately 1 µs, then that bank returns to reading

array data.

No

DQ5 = 1?

Yes

Read DQ7–DQ0

Addr = VA

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase

algorithm is complete, or if the bank enters the Erase

Suspend mode, Data# Polling produces a “1” on DQ7.

The system must provide an address within any of the

sectors selected for erasure to read valid status infor-

mation on DQ7.

Yes

DQ7 = Data?

No

After an erase command sequence is written, if all

sectors selected for erasing are protected, Data# Poll-

ing on DQ7 is active for approximately 100 µs, then the

bank returns to reading array data. If not all selected

sectors are protected, the Embedded Erase algorithm

erases the unprotected sectors, and ignores the se-

lected sectors that are protected. However, if the

system reads DQ7 at an address within a protected

sector, the status may not be valid.

PASS

FAIL

Notes:

1. VA = Valid address for programming. During a sector

erase operation, a valid address is any sector address

within the sector being erased. During chip erase, a

valid address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

Just prior to the completion of an Embedded Program

or Erase operation, DQ7 may change asynchronously

with DQ0–DQ6 while Output Enable (OE#) is asserted

low. That is, the device may change from providing

status information to valid data on DQ7. Depending on

when the system samples the DQ7 output, it may read

the status or valid data. Even if the device completes

the program or erase operation and DQ7 contains

valid data, the data outputs on DQ0–DQ6 may be still

Figure 5. Data# Polling Algorithm

28

Am29DS163D

A D V A N C E I N F O R M A T I O N

Table 15 on page 31 shows the outputs for Toggle Bit I

RY/BY#: Ready/Busy#

on DQ6. Figure 6 shows the toggle bit algorithm. Fig-

ure 22, on page 43 shows the toggle bit timing

diagrams. Figure 23, on page 43 shows the differ-

ences between DQ2 and DQ6 in graphical form. See

also the subsection on “DQ2: Toggle Bit II” on

page 30.

The RY/BY# is a dedicated, open-drain output pin

which indicates whether an Embedded Algorithm is in

progress or complete. The RY/BY# status is valid after

the rising edge of the final WE# pulse in the command

sequence. Since RY/BY# is an open-drain output, sev-

eral RY/BY# pins can be tied together in parallel with a

pull-up resistor to V_CC

.

If the output is low (Busy), the device is actively eras-

ing or programming. (This includes programming in

the Erase Suspend mode.) If the output is high

(Ready), the device is reading array data, the standby

mode, or one of the banks is in the erase-sus-

pend-read mode.

START

Read DQ7–DQ0

Table 15 on page 31 shows the outputs for RY/BY#.

DQ6: Toggle Bit I

Read DQ7–DQ0

Toggle Bit I on DQ6 indicates whether an Embedded

Program or Erase algorithm is in progress or com-

plete, or whether the device enters the Erase Suspend

mode. Toggle Bit I may be read at any address, and is

valid after the rising edge of the final WE# pulse in the

command sequence (prior to the program or erase op-

eration), and during the sector erase time-out.

No

Toggle Bit

= Toggle?

Yes

During an Embedded Program or Erase algorithm op-

eration, successive read cycles to any address cause

DQ6 to toggle. The system may use either OE# or

CE# to control the read cycles. When the operation is

complete, DQ6 stops toggling.

No

DQ5 = 1?

Yes

After an erase command sequence is written, if all

sectors selected for erasing are protected, DQ6 tog-

gles for approximately 100 µs, then returns to reading

array data. If not all selected sectors are protected, the

Embedded Erase algorithm erases the unprotected

sectors, and ignores the selected sectors that are

protected.

Read DQ7–DQ0

Twice

Toggle Bit

= Toggle?

No

The system can use DQ6 and DQ2 together to deter-

mine whether a sector is actively erasing or is

erase-suspended. When the device is actively erasing

(that is, the Embedded Erase algorithm is in progress),

DQ6 toggles. When the device enters the Erase Sus-

pend mode, DQ6 stops toggling. However, the system

must also use DQ2 to determine which sectors are

erasing or erase-suspended. Alternatively, the system

can use DQ7 (see the subsection on DQ7: Data#

Polling).

Yes

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Note: The system should recheck the toggle bit even if DQ5

= “1” because the toggle bit may stop toggling as DQ5

changes to “1.” See the subsections on DQ6 and DQ2 for

more information.

If a program address falls within a protected sector,

DQ6 toggles for approximately 1 µs after the program

command sequence is written, then returns to reading

array data.

Figure 6. Toggle Bit Algorithm

DQ6 also toggles during the erase-suspend-program

mode, and stops toggling once the Embedded Pro-

gram algorithm is complete.

Am29DS163D

29

A D V A N C E I N F O R M A T I O N

gle bit and DQ5 through successive read cycles,

DQ2: Toggle Bit II

determining the status as described in the previous

paragraph. Alternatively, it may choose to perform

other system tasks. In this case, the system must start

at the beginning of the algorithm when it returns to de-

termine the status of the operation (top of Figure 6, on

page 29).

The “Toggle Bit II” on DQ2, when used with DQ6, indi-

cates whether a particular sector is actively erasing

(that is, the Embedded Erase algorithm is in progress),

or whether that sector is erase-suspended. Toggle Bit

II is valid after the rising edge of the final WE# pulse in

the command sequence.

DQ5: Exceeded Timing Limits

DQ2 toggles when the system reads at addresses

within those sectors that were selected for erasure.

(The system may use either OE# or CE# to control the

read cycles.) But DQ2 cannot distinguish whether the

sector is actively erasing or is erase-suspended. DQ6,

by comparison, indicates whether the device is ac-

tively erasing, or is in Erase Suspend, but cannot

distinguish which sectors are selected for erasure.

Thus, both status bits are required for sector and

mode information. Refer to Table 15 on page 31 to

compare outputs for DQ2 and DQ6.

DQ5 indicates whether the program or erase time ex-

ceeded a specified internal pulse count limit. Under

these conditions DQ5 produces a “1,” indicating that

the program or erase cycle was not successfully

completed.

The device may output a “1” on DQ5 if the system tries

to program a “1” to a location that was previously pro-

grammed to “0.” Only an erase operation can

change a “0” back to a “1.” Under this condition, the

device halts the operation, and when the timing limit is

exceeded, DQ5 produces a “1.”

Figure 6, on page 29 shows the toggle bit algorithm in

flowchart form, and the section “DQ2: Toggle Bit II” ex-

plains the algorithm. See also the “DQ6: Toggle Bit I”

on page 29 subsection. Figure 22, on page 43 shows

the toggle bit timing diagram. Figure 23, on page 43

shows the differences between DQ2 and DQ6 in

graphical form.

Under both these conditions, the system must write

the reset command to return to reading array data (or

to the erase-suspend-read mode if a bank was previ-

ously in the erase-suspend-program mode).

DQ3: Sector Erase Timer

Reading Toggle Bits DQ6/DQ2

After writing a sector erase command sequence, the

system may read DQ3 to determine whether or not

erasure started. (The sector erase timer does not

apply to the chip erase command.) If additional

sectors are selected for erasure, the entire time-out

also applies after each additional sector erase com-

mand. When the time-out period is complete, DQ3

switches from a “0” to a “1.” If the time between addi-

tional sector erase commands from the system can be

assumed to be less than 50 µs, the system need not

monitor DQ3. See also “Sector Erase Command Se-

quence” on page 25.

Refer to Figure 6, on page 29 for the following discus-

sion. Whenever the system initially begins reading

toggle bit status, it must read DQ7–DQ0 at least twice

in a row to determine whether a toggle bit is toggling.

Typically, the system would note and store the value of

the toggle bit after the first read. After the second read,

the system would compare the new value of the toggle

bit with the first. If the toggle bit is not toggling, the de-

vice completed the program or erase operation. The

system can read array data on DQ7–DQ0 on the fol-

lowing read cycle.

After the sector erase command is written, the system

should read the status of DQ7 (Data# Polling) or DQ6

(Toggle Bit I) to ensure that the device accepted the

command sequence, and then read DQ3. If DQ3 is

“1,” the Embedded Erase algorithm started; all further

commands (except Erase Suspend) are ignored until

the erase operation is complete. If DQ3 is “0,” the de-

vice accepts additional sector erase commands. To

ensure the command is accepted, the system software

should check the status of DQ3 prior to and following

each subsequent sector erase command. If DQ3 is

high on the second status check, the last command

might not have been accepted.

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the sys-

tem also should note whether the value of DQ5 is high

(see the section on DQ5). If it is, the system should

then determine again whether the toggle bit is tog-

gling, since the toggle bit may have stopped toggling

just as DQ5 went high. If the toggle bit is no longer

toggling, the device successfully completed the pro-

gram or erase operation. If it is still toggling, the device

did not completed the operation successfully, and the

system must write the reset command to return to

reading array data.

The remaining scenario is that the system initially de-

termines that the toggle bit is toggling and DQ5 did not

go high. The system may continue to monitor the tog-

Table 15 on page 31 shows the status of DQ3 relative

to the other status bits.

30

Am29DS163D

A D V A N C E I N F O R M A T I O N

Table 15. Write Operation Status

DQ7

DQ5

DQ2

Status

(Note 2)

DQ6

(Note 1)

DQ3

N/A

1

(Note 2)

RY/BY#

Embedded Program Algorithm

Embedded Erase Algorithm

Erase

Erase-Suspend-

Read

DQ7#

0

Toggle

0

No toggle

Toggle

0

Standard

Mode

1

No toggle

0

N/A

Toggle

1

Suspended Sector

Erase

Suspend

Mode

Non-Erase

Suspended Sector

Data

0

Data

N/A

Data

N/A

1

0

Erase-Suspend-Program

DQ7#

Toggle

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation exceeds the maximum timing limits. Refer

to the section on DQ5 for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further

details.

3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm

is in progress. The device outputs array data if the system addresses a non-busy bank.

Am29DS163D

31

A D V A N C E I N F O R M A T I O N

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

20 ns

Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C

+0.8 V

Ambient Temperature

with Power Applied . . . . . . . . . . . . . –65°C to +125°C

–0.5 V

–2.0 V

Voltage with Respect to Ground

V_CC(Note 1) . . . . . . . . . . . . . . . . .–0.5 V to +2.5 V

20 ns

A9, OE#, and RESET#

(Note 2). . . . . . . . . . . . . . . . . . . . . –0.5 V to +11 V

WP#/ACC . . . . . . . . . . . . . . . . . .–0.5 V to +10.5 V

All other pins (Note 1) . . . . . . –0.5 V to V_CC+0.5 V

Output Short Circuit Current (Note 3) . . . . . . 100 mA

Figure 7. Maximum Negative

Overshoot Waveform

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V.

During voltage transitions, input or I/O pins may

overshoot V_SSto –2.0 V for periods of up to 20 ns.

Maximum DC voltage on input or I/O pins is V_CC+0.5 V.

See Figure 7. During voltage transitions, input or I/O pins

may overshoot to V_CC+2.0 V for periods up to 20 ns. See

Figure 8.

20 ns

V_CC

+2.0 V

V_CC

+0.5 V

2.0 V

2. Minimum DC input voltage on pins A9, OE#, RESET#,

and WP#/ACC is –0.5 V. During voltage transitions, A9,

OE#, WP#/ACC, and RESET# may overshoot V_SSto

–2.0 V for periods of up to 20 ns. See Figure 7. Maximum

DC input voltage on pin A9 is +12.5 V which may

overshoot to +14.0 V for periods up to 20 ns. Maximum

DC input voltage on WP#/ACC is +9.5 V which may

overshoot to +12.0 V for periods up to 20 ns.

20 ns

Figure 8. Maximum Positive

Overshoot Waveform

3. No more than one output may be shorted to ground at a

time. Duration of the short circuit should not be greater

than one second.

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This

is a stress rating only; functional operation of the device at

these or any other conditions above those indicated in the

operational sections of this data sheet is not implied.

Exposure of the device to absolute maximum rating

conditions for extended periods may affect device reliability.

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (T_A) . . . . . . . . . . . 0°C to +70°C

Industrial (I) Devices

Ambient Temperature (T_A) . . . . . . . . . –40°C to +85°C

Extended (E) Devices

Ambient Temperature (T_A) . . . . . . . . –55°C to +125°C

V_CCSupply Voltages

V_CCfor standard voltage range . . . . . . .1.8 V to 2.2 V

Operating ranges define those limits between which the func-

tionality of the device is guaranteed.

32

Am29DS163D

A D V A N C E I N F O R M A T I O N

DC CHARACTERISTICS

CMOS Compatible

Parameter

Symbol

Parameter Description

Test Conditions

V_IN= V_SSto V_CC

V_CC= V_{CC max}

V_CC= V_{CC max}; A9 = 11 V

Min

Typ

Max

1.0

35

Unit

µA

,

I_LI

Input Load Current

I_LIT

I_LO

A9 Input Load Current

Output Leakage Current

µA

V_OUT= V_SSto V_CC

V_CC= V_{CC max}

,

1.0

µA

5 MHz

1 MHz

5 MHz

1 MHz

5

1

16

4

CE# = V_IL,OE# ₌V_IH,

Byte Mode

V_CCActive Read Current

(Notes 1, 2)

I_CC1

mA

5

16

4

CE# = V_IL,OE# ₌V_IH,

Word Mode

1

I_CC2

I_CC3

I_CC4

V_CCActive Write Current (Notes 2, 3) CE# = V_IL,OE# ₌V_IH, WE# = V_IL

10

0.2

15

5

mA

µA

V_CCStandby Current (Note 2)

V_CCReset Current (Note 2)

CE#, RESET# = V_CC0.3 V

RESET# = V_SS0.3 V

5

V_IH= V_CC0.3 V;

V_IL= V_SS0.3 V

I_CC5

Automatic Sleep Mode (Notes 2, 4)

0.2

5

µA

Byte

15

25

V_CCActive Read-While-Program

Current (Notes 1, 2)

I_CC6

CE# = V_IL, OE# = V_IH

mA

Word

Byte

V_CCActive Read-While-Erase

Current (Notes 1, 2)

I_CC7

I_CC8

I_ACC

mA

Word

V_CCActive

Program-While-Erase-Suspended

Current (Notes 2, 5)

CE# = V_IL, OE# = V_IH

10

15

ACC pin

V_CCpin

5

10

mA

V

ACC Accelerated Program Current,

Word or Byte

10

15

V_IL

V_IH

Input Low Voltage

Input High Voltage

–0.5

V_CCx 0.2

V_CC+ 0.3

0.8 x V_CC

V

Voltage for WP#/ACC Sector

Protect/Unprotect and Program

Acceleration

V_HH

V_CC= 1.8–2.2 V

8.5

9.0

9.5

V

Voltage for Autoselect and Temporary

Sector Unprotect

V_ID

11.0

0.25

V_OL

V_OH1

V_OH2

V_LKO

Output Low Voltage

I_OL= 2.0 mA, V_CC= V_{CC min}

I_OH= –2.0 mA, V_CC= V_{CC min}

I_OH= –100 µA, V_CC= V_{CC min}

V

0.7 V_CC

V_CC–0.1

1.2

Output High Voltage

Low V_CCLock-Out Voltage (Note 5)

1.6

V

Notes:

1. The I_CCcurrent listed is typically less than 1 mA/MHz, with OE# at V_IH.

2. Maximum I_CCspecifications are tested with V_CC= V_CCmax.

3. I_CCactive while Embedded Erase or Embedded Program is in progress.

4. Automatic sleep mode enables the low power mode when addresses remain stable for t_ACC+ 30 ns. Typical sleep mode current is

200 nA.

5. Not 100% tested.

Am29DS163D

33

A D V A N C E I N F O R M A T I O N

DC CHARACTERISTICS

Zero-Power Flash

25

20

15

10

5

0

500

1000

1500

2000

2500

3000

3500

4000

Time in ns

Note: Addresses are switching at 1 MHz

Figure 9. I_CC1Current vs. Time (Showing Active and Automatic Sleep Currents)

12

10

8

2.2 V

6

4

1.8 V

2

0

1

2

3

4

5

Frequency in MHz

Note: T = 25 °C

Figure 10. Typical I_CC1vs. Frequency

34

Am29DS163D

A D V A N C E I N F O R M A T I O N

TEST CONDITIONS

Table 16. Test Specifications

Test Condition

Output Load

100, 120

Unit

Device

Under

Test

1 TTL gate

Output Load Capacitance, C_L

(including jig capacitance)

30

pF

C

L

Input Rise and Fall Times

Input Pulse Levels

5

ns

V

0.0–2.0 V

Input timing measurement

reference levels

1.0

V

Note: Diodes are IN3064 or equivalent

Output timing measurement

reference levels

Figure 11. Test Setup

Key To Switching Waveforms

WAVEFORM

INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Center Line is High Impedance State (High Z)

2.0 V

0.0 V

1.0 V

Input

Measurement Level

Output

Figure 12. Input Waveforms and Measurement Levels

Am29DS163D

35

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Read-Only Operations

Parameter

JEDEC

t_AVAV

Std

t_RC

t_ACC

t_CE

t_OE

t_DF

Description

Test Setup

100

35

120

50

Unit

ns

Read Cycle Time (Note 1)

Min

Max

t_AVQV

t_ELQV

t_GLQV

t_EHQZ

t_GHQZ

Address to Output Delay

CE#, OE# = V_IL

OE# = V_IL

ns

Chip Enable to Output Delay

Output Enable to Output Delay

Chip Enable to Output High Z (Note 1)

Output Enable to Output High Z (Note 1)

ns

30

ns

t_DF

ns

Output Hold Time From Addresses, CE# or OE#,

Whichever Occurs First

t_AXQX

t_OH

Min

0

ns

Read

Output Enable Hold

t_OEH

Toggle and

Data# Polling

Time (Note 1)

10

Notes:

1. Not 100% tested.

2. See Figure 11 and Table 16 for test specifications.

t_RC

Addresses Stable

t_ACC

Addresses

CE#

t_RH

t_DF

t_OE

OE#

t_OEH

WE#

t_CE

t_OH

HIGH Z

Output Valid

Outputs

RESET#

RY/BY#

0 V

Figure 13. Read Operation Timings

36

Am29DS163D

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Hardware Reset (RESET#)

Parameter

JEDEC

Std

Description

RESET# Pin Low (During Embedded Algorithms)

All Speed Options

Unit

t_Ready

Max

20

µs

to Read Mode (See Note)

RESET# Pin Low (NOT During Embedded

Algorithms) to Read Mode (See Note)

t_Ready

500

ns

t_RP

t_RH

t_RPD

t_RB

RESET# Pulse Width

Min

500

200

20

ns

µs

ns

Reset High Time Before Read (See Note)

RESET# Low to Standby Mode

RY/BY# Recovery Time

0

Note: Not 100% tested.

RY/BY#

CE#, OE#

RESET#

t_RH

t_RP

t_Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

t_Ready

RY/BY#

t_RB

CE#, OE#

RESET#

t_RP

Figure 14. Reset Timings

Am29DS163D

37

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Word/Byte Configuration (BYTE#)

Parameter

JEDEC

Std

t_{ELFL/ ELFH}

t_FLQZ

t_FHQV

Description

100

120

Unit

ns

t

CE# to BYTE# Switching Low or High

BYTE# Switching Low to Output HIGH Z

BYTE# Switching High to Output Active

Max

Min

10

40

ns

100

120

ns

CE#

OE#

BYTE#

t_ELFL

Data Output

(DQ0–DQ14)

Data Output

(DQ0–DQ7)

BYTE#

DQ0–DQ14

Switching

from word

to byte

Address

Input

DQ15

Output

mode

DQ15/A-1

t_FLQZ

t_ELFH

BYTE#

Switching

from byte

to word

Data Output

(DQ0–DQ7)

Data Output

(DQ0–DQ14)

DQ0–DQ14

DQ15/A-1

mode

Address

Input

DQ15

Output

t_FHQV

Figure 15. BYTE# Timings for Read Operations

CE#

The falling edge of the last WE# signal

WE#

BYTE#

t_SET

(t_AS

)

t_HOLD(t_AH

)

Note: Refer to the Erase/Program Operations table for t_ASand t_AHspecifications.

Figure 16. BYTE# Timings for Write Operations

Am29DS163D

38

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Erase and Program Operations

Parameter

JEDEC

t_AVAV

Std

t_WC

t_AS

Description

100

0

120

0

Unit

ns

Write Cycle Time (Note 1)

Address Setup Time

Min

t_AVWL

ns

t_ASO

t_AH

Address Setup Time to OE# low during toggle bit polling

Address Hold Time

15

50

ns

t_WLAX

ns

Address Hold Time From CE# or OE# high

during toggle bit polling

t_AHT

Min

0

ns

t_DVWH

t_WHDX

t_DS

t_DH

Data Setup Time

Min

50

0

ns

Data Hold Time

t_OEPH

Output Enable High during toggle bit polling

20

Read Recovery Time Before Write

(OE# High to WE# Low)

t_GHWL

Min

0

ns

t_ELWL

t_WHEH

t_WLWH

t_WHDL

t_CS

t_CH

CE# Setup Time

Min

Typ

0

ns

CE# Hold Time

t_WP

Write Pulse Width

50

30

0

t_WPH

t_SR/W

Write Pulse Width High

Latency Between Read and Write Operations

Byte

Programming Operation (Note 2)

Word

9

t_WHWH1

µs

13

Accelerated Programming Operation,

Word or Byte (Note 2)

t_WHWH1

t_WHWH2

t_WHWH1

Typ

7

t_WHWH2

t_VCS

Sector Erase Operation (Note 2)

V_CCSetup Time (Note 1)

Typ

Min

2

50

0

sec

µs

t_RB

Write Recovery Time from RY/BY#

Program/Erase Valid to RY/BY# Delay

ns

t_BUSY

90

ns

Notes:

1. Not 100% tested.

2. See “Erase And Programming Performance” on page 48 for more information.

Am29DS163D

39

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Program Command Sequence (last two cycles)

Read Status Data (last two cycles)

t_AS

PA

t_WC

Addresses

555h

PA

t_AH

CE#

t_CH

t_GHWL

OE#

t_WHWH1

t_WP

WE#

t_WPH

t_CS

t_DS

t_DH

PD

D_OUT

A0h

Status

Data

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. PA = program address, PD = program data, D_OUTis the true data at the program address.

2. Illustration shows device in word mode.

Figure 17. Program Operation Timings

V_HH

V_ILor V_IH

WP#/ACC

V_ILor V_IH

t_VHH

Figure 18. Accelerated Program Timing Diagram

40

Am29DS163D

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Erase Command Sequence (last two cycles)

Read Status Data

VA

t_AS

SA

t_WC

VA

Addresses

2AAh

555h for chip erase

t_AH

CE#

t_GHWL

t_CH

OE#

t_WP

WE#

t_WPH

t_WHWH2

t_CS

t_DS

t_DH

In

Data

Complete

55h

30h

Progress

10 for Chip Erase

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status” on page 28).

2. These waveforms are for the word mode.

Figure 19. Chip/Sector Erase Operation Timings

Am29DS163D

41

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

t_WC

Valid PA

t_WC

t_RC

t_WC

Valid PA

Valid RA

Valid PA

Addresses

t_AH

t_CPH

t_ACC

t_CE

CE#

t_CP

t_OE

OE#

t_OEH

t_GHWL

t_WP

WE#

t_DF

t_WPH

t_DS

t_OH

t_DH

Valid

Out

Valid

In

Valid

In

Valid

In

Data

t_SR/W

WE# Controlled Write Cycle

Read Cycle

CE# Controlled Write Cycles

Figure 20. Back-to-back Read/Write Cycle Timings

t_RC

Addresses

VA

t_ACC

t_CE

VA

CE#

t_CH

t_OE

OE#

t_OEH

t_DF

t_OH

WE#

High Z

DQ7

Valid Data

Complement

True

DQ0–DQ6

Valid Data

Status Data

True

Status Data

t_BUSY

RY/BY#

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data

read cycle.

Figure 21. Data# Polling Timings (During Embedded Algorithms)

42

Am29DS163D

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

t_AHT

t_AS

Addresses

t_AHT

t_ASO

CE#

t_OEH

WE#

t_CEPH

t_OEPH

OE#

t_DH

Valid Data

t_OE

Valid

Status

Valid

Status

Valid

Status

DQ6/DQ2

Valid Data

(first read)

(second read)

(stops toggling)

RY/BY#

Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read

cycle, and array data read cycle

Figure 22. Toggle Bit Timings (During Embedded Algorithms)

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

Erase

Erase Suspend

Read

Erase

Suspend

Program

Erase

Complete

WE#

Erase

Erase Suspend

Read

DQ6

DQ2

Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle

DQ2 and DQ6.

Figure 23. DQ2 vs. DQ6

Am29DS163D

43

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Temporary Sector/Sector Block Unprotect

Parameter

JEDEC

Std

t_VIDR

t_VHH

Description

All Speed Options

Unit

ns

V_IDRise and Fall Time (See Note)

V_HHRise and Fall Time (See Note)

Min

500

ns

RESET# Setup Time for Temporary

Sector/Sector Block Unprotect

t_RSP

Min

4

µs

RESET# Hold Time from RY/BY# High for

Temporary Sector/Sector Block Unprotect

t_RRB

Note: Not 100% tested.

V_ID

RESET#

V_SS, V_IL,

or V_IH

V_SS, V_IL,

or V_IH

t_VIDR

Program or Erase Command Sequence

CE#

WE#

t_RRB

t_RSP

RY/BY#

Figure 24. Temporary Sector/Sector Block

Unprotect Timing Diagram

44

Am29DS163D

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

V_ID

V_IH

RESET#

SA, A6,

A1, A0

Valid*

Status

Sector/Sector Block Protect or Unprotect

60h 60h

Verify

40h

Data

Sector/Sector Block Protect: 150 µs,

Sector/Sector Block Unprotect: 15 ms

1 µs

CE#

WE#

OE#

* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.

Figure 25. Sector/Sector Block Protect/Unprotect Timing Diagram

Am29DS163D

45

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Alternate CE# Controlled Erase and Program Operations

Parameter

JEDEC

t_AVAV

Std

t_WC

t_AS

t_AH

t_DS

t_DH

Description

100

120

Unit

ns

Write Cycle Time (Note 1)

Address Setup Time

Address Hold Time

Data Setup Time

Data Hold Time

Min

100

120

t_AVWL

t_ELAX

t_DVEH

t_EHDX

0

50

0

ns

Read Recovery Time Before Write

(OE# High to WE# Low)

t_GHEL

Min

0

ns

t_WLEL

t_EHWH

t_ELEH

t_EHEL

t_WS

t_WH

t_CP

WE# Setup Time

WE# Hold Time

Min

Typ

0

ns

CE# Pulse Width

CE# Pulse Width High

50

30

9

t_CPH

Byte

Programming Operation

(Note 2)

t_WHWH1

µs

Word

13

Accelerated Programming Operation,

Word or Byte (Note 2)

t_WHWH1

t_WHWH2

Notes:

t_WHWH1

t_WHWH2

Typ

7

2

µs

Sector Erase Operation (Note 2)

sec

1. Not 100% tested.

2. See “Erase And Programming Performance” on page 48 for more information.

46

Am29DS163D

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

555 for program

2AA for erase

PA for program

SA for sector erase

555 for chip erase

Data# Polling

Addresses

PA

t_WC

t_WH

t_AS

t_AH

WE#

OE#

t_GHEL

t_{WHWH1 or 2}

t_CP

CE#

Data

t_WS

t_CPH

t_DS

t_BUSY

t_DH

DQ7#

D_OUT

t_RH

A0 for program

55 for erase

PD for program

30 for sector erase

10 for chip erase

RESET#

RY/BY#

Notes:

1. Figure indicates last two bus cycles of a program or erase operation.

2. PA = program address, SA = sector address, PD = program data.

3. DQ7# is the complement of the data written to the device. D_OUTis the data written to the device.

4. Waveforms are for the word mode.

Figure 26. Alternate CE# Controlled Write (Erase/Program) Operation Timings

Am29DS163D

47

A D V A N C E I N F O R M A T I O N

ERASE AND PROGRAMMING PERFORMANCE

Parameter

Typ (Note 1) Max (Note 2)

Unit

sec

µs

Comments

Sector Erase Time

2

78

9

15

Excludes 00h programming

prior to erasure (Note 4)

Chip Erase Time

Byte Program Time

Word Program Time

Accelerated Byte/Word Program Time

270

340

210

80

13

7

µs

Excludes system level

overhead (Note 5)

µs

Byte Mode

Word Mode

28

14

Chip Program Time

(Note 3)

sec

40

Notes:

1. Typical program and erase times assume the following conditions: 25°C, 2.0 V V_CC, 1,000,000 cycles. Additionally,

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, V_CC= 2.2 V, 1,000,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See

Table 14 on page 27 for further information on command definitions.

6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTICS

Description

Min

Max

Input voltage with respect to V_SSon all pins except I/O pins

(including A9, OE#, and RESET#)

–1.0 V

11 V

Input voltage with respect to V_SSon all I/O pins

V_CCCurrent

–1.0 V

V_CC+ 1.0 V

+100 mA

–100 mA

Note: Includes all pins except V_CC. Test conditions: V_CC= 2.0 V, one pin at a time.

DATA RETENTION

Parameter Description

Test Conditions

Min

10

Unit

Years

150°C

125°C

Minimum Pattern Data Retention Time

20

48

Am29DS163D

A D V A N C E I N F O R M A T I O N

PHYSICAL DIMENSIONS

FBA048—48-Ball Fine-Pitch Ball Grid Array (FBGA)

6 x 8 mm package

Dwg rev AF; 10/99

Am29DS163D

49

A D V A N C E I N F O R M A T I O N

REVISION SUMMARY

Revision A (November 9, (2000)

Initial release.

Revision A+1 (November 8, 2004)

Global

Added cover page

Added Colophon

Updated Trademark

Added referenced links.

Ordering Information

Added temperature range for Pb-free Packages

Valid Combinations for FBGA Packages

Added new order number information

Added new Package Marking information

Colophon

The products described in this document are designed, developed and manufactured as contemplated for general use, including without limita-

tion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as con-

templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the

public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,

aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for

any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion LLC will not be liable

to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor

devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design

measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operat-

ing conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the

prior authorization by the respective government entity will be required for export of those products.

Trademarks

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

ExpressFlash is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

50

Am29DS163D


型号：	AM29DS163DT120WAK
厂家：	AMD
描述：	16 Megabit CMOS 1.8 Volt-only, Simultaneous Operation Flash Memory 16兆位CMOS 1.8伏只，同时操作闪存闪存
文件：	总50页 (文件大小：1690K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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