AM29F010-45ECB [AMD]
1 Megabit (128 K x 8-bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory; 1兆位（ 128千×8位） CMOS 5.0伏只，统一部门快闪记忆体
| 型号： | AM29F010-45ECB |
| 厂家： | 
AMD |
| 描述： | 1 Megabit (128 K x 8-bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory |
| 文件： | 总31页 (文件大小：349K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FINAL
Am29F010
1 Megabit (128 K x 8-bit)
CMOS 5.0 Volt-only, Uniform Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■ Single power supply operation
■ Embedded Algorithms
— 5.0 V ± 10% for read, erase, and program
— Embedded Erase algorithm automatically
pre-programs and erases the chip or any
combination of designated sector
operations
— Simplifies system-level power requirements
— Embedded Program algorithm automatically
programs and verifies data at specified address
■ High performance
— 45 ns maximum access time
■ Minimum 100,000 program/erase cycles
■ Low power consumption
guaranteed
— 30 mA max active read current
— 50 mA max program/erase current
— <25 µA typical standby current
■ Package options
— 32-pin PLCC
— 32-pin TSOP
— 32-pin PDIP
■ Flexible sector architecture
— Eight uniform sectors
■ Compatible with JEDEC standards
— Any combination of sectors can be erased
— Supports full chip erase
— Pinout and software compatible with
single-power-supply flash
■ Sector protection
— Superior inadvertent write protection
— Hardware-based feature that disables/re-
enables program and erase operations in any
combination of sectors
■ Data# Polling and Toggle Bits
— Provides a software method of detecting
program or erase cycle completion
— Sector protection/unprotection can be
implemented using standard PROM
programming equipment
Publication# 16736 Rev: G Amendment/+2
Issue Date: March 1998
GENERAL DESCRIPTION
The Am29F010 is a 1 Mbit, 5.0 Volt-only Flash memory
organized as 131,072 bytes. The Am29F010 is offered
in 32-pin PLCC, TSOP, and PDIP packages. The byte-
wide data appears on DQ0-DQ7. The device is de-
signed to be programmed in-system with the standard
Device erasure occurs by executing the erase com-
mand sequence. This invokes the Embedded Erase
algorithm—an internal algorithm that automatically pre-
programs the array (if it is not already programmed) be-
fore executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
system 5.0 Volt V
supply. A 12.0 volt V is not re-
CC
PP
quired for program or erase operations. The device can
also be programmed or erased in standard EPROM
programmers.
The host system can detect whether a program or
erase operation is complete by reading the DQ7 (Data#
Polling) and DQ6 (toggle) status bits. After a program
or erase cycle has been completed, the device is ready
to read array data or accept another command.
The standard device offers access times of 45, 55, 70,
90, and 120 ns, allowing high-speed microprocessors
to operate without wait states. To eliminate bus con-
tention the device has separate chip enable (CE#),
write enable (WE#) and output enable (OE) controls.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is erased
when shipped from the factory.
The device requires only a single 5.0 volt power sup-
ply for both read and write functions. Internally gener-
ated and regulated voltages are provided for the
program and erase operations.
The hardware data protection measures include a
detector automatically inhibits write operations
low VCC
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Com-
mands are written to the command register using stan-
dard microprocessor write timings. Register contents
serve as input to an internal state machine that controls
the erase and programming circuitry. Write cycles also
internally latch addresses and data needed for the pro-
gramming and erase operations. Reading data out of
the device is similar to reading from other Flash or
EPROM devices.
during power transitions. The hardware sector pro-
tection feature disables both program and erase oper-
ations in any combination of the sectors of memory,
and is implemented using standard EPROM program-
mers.
The system can place the device into the standby mode.
Power consumption is greatly reduced in this mode.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability, and cost
effectiveness. The device electrically erases all bits
within a sector simultaneously via Fowler-Nordheim
tunneling. The bytes are programmed one byte at a
time using the EPROM programming mechanism of
hot electron injection.
Device programming occurs by executing the program
command sequence. This invokes the Embedded
Program algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin.
2
Am29F010
PRODUCT SELECTOR GUIDE
Family Part Number
Am29F010
V
V
= 5.0 V ± 5%
= 5.0 V ± 10%
-45
-55 (P)
CC
Speed Option
-55 (J, E, F)
-70
70
70
30
-90
90
90
35
-120
120
120
50
CC
Max Access Time (ns)
CE# Access (ns)
45
45
25
55
55
30
OE# Access (ns)
Note: See the AC Characteristics section for full specifications.
BLOCK DIAGRAM
DQ0–DQ7
V
CC
Erase Voltage
Generator
Input/Output
Buffers
V
SS
State
Control
WE#
Command
Register
PGM Voltage
Generator
Data
Latch
Chip Enable
Output Enable
Logic
STB
CE#
OE#
Y-Decoder
Y-Gating
STB
V
Detector
Timer
CC
Cell Matrix
X-Decoder
A0–A16
16736G-1
Am29F010
3
CONNECTION DIAGRAMS
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
NC
A16
A15
A12
A7
2
WE#
NC
3
3
4
31 30
1 32
2
4
A14
A13
A8
A7
A6
5
6
A14
A13
29
28
5
A6
6
A5
A4
7
A8
27
26
25
24
23
22
21
A5
7
A9
8
A9
A4
8
A11
OE#
A10
CE#
DQ7
DQ6
PLCC
PDIP
A3
9
A11
OE#
A10
CE#
DQ7
A3
9
A2
10
11
12
13
A2
10
11
12
13
14
15
16
A1
A1
A0
A0
DQ0
DQ0
16 17
19 20
18
15
14
DQ1
DQ2
DQ5
DQ4
DQ3
V
SS
16736G-2
16736G-3
1
2
3
4
5
6
7
8
9
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
A13
A14
NC
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
WE#
V
Standard TSOP
CC
NC
A16
A15
A12
A7
A6
A5
A4
V
SS
10
DQ2
DQ1
DQ0
A0
A1
A2
11
12
13
14
15
16
A
3
16736G-4
OE#
A10
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
A13
A14
NC
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
WE#
V
CC
V
Reverse TSOP
9
NC
A16
A15
A12
A7
A6
A5
A4
SS
DQ2
DQ1
DQ0
A0
A1
A2
10
11
12
13
14
15
16
A
3
16736G-5
4
Am29F010
PIN CONFIGURATION
LOGIC SYMBOL
A0–A16
= 17 Addresses
DQ0–DQ7 = 8 Data Inputs/Outputs
17
CE#
OE#
WE#
VCC
= Chip Enable
= Output Enable
= Write Enable
A0–A16
8
DQ0–DQ7
CE#
OE#
WE#
= +5.0 Volt Single Power Supply
(See Product Selector Guide for speed
options and voltage supply tolerances)
VSS
NC
= Device Ground
= Pin Not Connected Internally
16736G-6
Am29F010
5
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of the elements below.
Am29F010
-70
E
C
B
OPTIONAL PROCESSING
Blank = Standard Processing
B = Burn-In
(Contact an AMD representative for more information.)
TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I
=
Industrial (–40°C to +85°C)
Extended (–55°C to +125°C)
E
=
PACKAGE TYPE
P
J
=
=
32-Pin Plastic DIP (PD 032)
32-Pin Rectangular Plastic Leaded
Chip Carrier (PL 032)
E
F
=
=
32-Pin Thin Small Outline Package
(TSOP) Standard Pinout (TS 032)
32-Pin Thin Small Outline Package
(TSOP) Reverse Pinout (TSR032)
SPEED OPTION
See Product Selector Guide and
Valid Combinations
DEVICE NUMBER/DESCRIPTION
Am29F010
1 Megabit (128 K x 8-Bit) CMOS Flash Memory
5.0 Volt-only Read, Program, and Erase
Valid Combinations
Valid Combinations
PC, PI, PE,
Valid Combinations list configurations planned to be sup-
ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
JC, JI, JE,
EC, EI, EE,
FC, FI, FE
AM29F010-45
AM29F010-55
PC5, PI5, PE5
V
= 5.0 V ± 5%
CC
AM29F010-55
= 5.0 V ± 10%
JC, JI, JE, EC, EI, EE, FC, FI, FE
V
CC
PC, PI, PE,
JC, JI, JE,
EC, EI, EE,
FC, FI, FE
AM29F010-70
AM29F010-90
AM29F010-120
6
Am29F010
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself
does not occupy any addressable memory location.
The register is composed of latches that store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. The appropriate device bus operations table
lists the inputs and control levels required, and the re-
sulting output. The following subsections describe
each of these operations in further detail.
Table 1. Am29F010 Device Bus Operations
Addresses
(Note 1)
Operation
CE#
L
OE#
L
WE#
H
DQ0–DQ7
Read
A
A
D
OUT
IN
IN
Write
L
H
L
D
IN
Standby
V
± 0.5 V
X
X
X
High-Z
High-Z
High-Z
CC
Output Disable
L
X
X
H
H
X
X
Hardware Reset
X
X
Temporary Sector Unprotect
X
X
A
D
IN
IN
Legend:
L = Logic Low = V , H = Logic High = V , V = 12.0 ± 0.5 V, X = Don’t Care, A = Addresses In, D = Data In, D = Data Out
IL
IH ID
IN
IN
OUT
Notes:
1. Addresses are A16:A0.
2. The sector protect and sector unprotect functions must be implemented via programming equipment. See the “Sector Pro-
tection/Unprotection” section.
Requirements for Reading Array Data
Writing Commands/Command Sequences
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output control
and gates array data to the output pins. WE# should re-
main at VIH.
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. The Sector Address Tables
indicate the address space that each sector occupies.
A “sector address” consists of the address bits required
to uniquely select a sector. See the “Command Defini-
tions” section for details on erasing a sector or the en-
tire chip.
The internal state machine is set for reading array
data upon device power-up, or after a hardware re-
set. This ensures that no spurious alteration of the
memory content occurs during the power transition.
No command is necessary in this mode to obtain
array data. Standard microprocessor read cycles that
assert valid addresses on the device address inputs
produce valid data on the device data outputs. The
device remains enabled for read access until the
command register contents are altered.
After the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the “Autoselect Mode” and “Autoselect
Command Sequence” sections for more information.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to the Read Operations Timings diagram for
the timing waveforms. ICC1 in the DC Characteristics
table represents the active current specification for
reading array data.
ICC2 in the DC Characteristics table represents the ac-
tive current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
Am29F010
7
The device enters the CMOS standby mode when the
CE# pin is held at VCC ± 0.5 V. (Note that this is a more
restricted voltage range than VIH.) The device enters
the TTL standby mode when CE# is held at VIH. The
device requires the standard access time (tCE) before
it is ready to read data.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and ICC
read specifications apply. Refer to “Write Operation
Status” for more information, and to each AC Charac-
teristics section in the appropriate data sheet for timing
diagrams.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
Standby Mode
ICC3 in the DC Characteristics tables represents the
standby current specification.
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, inde-
pendent of the OE# input.
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high imped-
ance state.
Table 2. Am29F010 Sector Addresses Table
A15 A14
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
A16
0
Address Range
00000h-03FFFh
04000h-07FFFh
08000h-0BFFFh
0C000h-0FFFFh
10000h-13FFFh
14000h-17FFFh
18000h-1BFFFh
1C000h-1FFFFh
0
0
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
0
1
1
1
1
Autoselect Mode
The autoselect mode provides manufacturer and de-
vice identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equipment
to automatically match a device to be programmed with
its corresponding programming algorithm. However,
the autoselect codes can also be accessed in-system
through the command register.
dress must appear on the appropriate highest order
address bits. Refer to the corresponding Sector Ad-
dress Tables. The Command Definitions table shows
the remaining address bits that are don’t care. When all
necessary bits have been set as required, the program-
ming equipment may then read the corresponding
identifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in the Command Defini-
tions table. This method does not require VID. See
“Command Definitions” for details on using the autose-
lect mode.
When using programming equipment, the autoselect
mode requires VID (11.5 V to 12.5 V) on address pin
A9. Address pins A6, A1, and A0 must be as shown in
Autoselect Codes (High Voltage Method) table. In ad-
dition, when verifying sector protection, the sector ad-
8
Am29F010
Table 3. Am29F010 Autoselect Codes (High Voltage Method)
A16 A13
to to
CE# OE# WE# A14 A10 A9
A8
to
A7
A5
to
A2
DQ7
to
DQ0
Description
Manufacturer ID: AMD
Device ID: Am29F010
A6
L
A1
L
A0
L
L
L
L
L
H
H
X
X
X
X
V
V
X
X
X
X
01h
20h
ID
ID
L
L
H
01h
(protected)
Sector Protection Verification
L
L
H
SA
X
V
X
L
X
H
L
ID
00h
(unprotected)
L = Logic Low = V , H = Logic High = V , SA = Sector Address, X = Don’t care.
IL
IH
gramming, which might otherwise be caused by spuri-
ous system level signals during VCC power-up and
power-down transitions, or from system noise.
Sector Protection/Unprotection
The hardware sector protection feature disables both
program and erase operations in any sector. The
hardware sector unprotection feature re-enables
both program and erase operations in previously pro-
tected sectors.
Low V
Write Inhibit
CC
When VCC is less than VLKO, the device does not ac-
cept any write cycles. This protects data during VCC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until VCC
is greater than VLKO. The system must provide the
proper signals to the control pins to prevent uninten-
Sector protection/unprotection must be implemented
using programming equipment. The procedure re-
quires a high voltage (VID) on address pin A9 and the
control pins. Details on this method are provided in a
supplement, publication number 20495. Contact an
AMD representative to obtain a copy of the appropriate
document.
tional writes when VCC is greater than VLKO
.
Write Pulse “Glitch” Protection
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE#
= VIL, CE# = VIH or WE# = VIH. To initiate a write cy-
cle, CE# and WE# must be a logical zero while OE#
is a logical one.
It is possible to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.
Hardware Data Protection
Power-Up Write Inhibit
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to the Command Defi-
nitions table). In addition, the following hardware data
protection measures prevent accidental erasure or pro-
If WE# = CE# = VIL and OE# = VIH during power
up, the device does not accept commands on the
rising edge of WE#. The internal state machine is
automatically reset to reading array data on
power-up.
Am29F010
9
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates device op-
erations. The Command Definitions table defines the
valid register command sequences. Writing incorrect
address and data values or writing them in the im-
proper sequence resets the device to reading array
data.
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
The Command Definitions table shows the address
and data requirements. This method is an alternative to
that shown in the Autoselect Codes (High Voltage
Method) table, which is intended for PROM program-
mers and requires VID on address bit A9.
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
“AC Characteristics” section.
The autoselect command sequence is initiated by
writing two unlock cycles, followed by the autoselect
command. The device then enters the autoselect
mode, and the system may read at any address any
number of times, without initiating another command
sequence.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or Em-
bedded Erase algorithm.
A read cycle at address XX00h or retrieves the manu-
facturer code. A read cycle at address XX01h returns
the device code. A read cycle containing a sector ad-
dress (SA) and the address 02h in returns 01h if that
sector is protected, or 00h if it is unprotected. Refer to
the Sector Address tables for valid sector addresses.
The system must issue the reset command to re-en-
able the device for reading array data if DQ5 goes high,
or while in the autoselect mode. See the “Reset Com-
mand” section, next.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
See also “Requirements for Reading Array Data” in the
“Device Bus Operations” section for more information.
The Read Operations table provides the read parame-
ters, and Read Operation Timings diagram shows the
timing diagram.
Byte Program Command Sequence
Programming is a four-bus-cycle operation. The pro-
gram command sequence is initiated by writing two un-
lock write cycles, followed by the program set-up
command. The program address and data are written
next, which in turn initiate the Embedded Program al-
gorithm. The system is not required to provide further
controls or timings. The device automatically provides
internally generated program pulses and verify the pro-
grammed cell margin. The Command Definitions take
shows the address and data requirements for the byte
program command sequence.
Reset Command
Writing the reset command to the device resets the de-
vice to reading array data. Address bits are don’t care
for this command.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ig-
nores reset commands until the operation is complete.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and ad-
dresses are no longer latched. The system can deter-
mine the status of the program operation by using
DQ7or DQ6. See “Write Operation Status” for informa-
tion on these status bits.
The reset command may be written between the se-
quence cycles in a program command sequence be-
fore programming begins. This resets the device to
reading array data. Once programming begins, how-
ever, the device ignores reset commands until the op-
eration is complete.
Any commands written to the device during the Em-
bedded Program Algorithm are ignored.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must
be written to return to reading array data.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempting to do so may halt
the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indicate the operation was suc-
cessful. However, a succeeding read will show that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to read-
ing array data.
10
Am29F010
Chip Erase Command Sequence
Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. The Command
Definitions table shows the address and data require-
ments for the chip erase command sequence.
START
Write Program
Command Sequence
Data Poll
from System
Embedded
Program
algorithm
in progress
Any commands written to the chip during the Embed-
ded Erase algorithm are ignored.
Verify Data?
Yes
No
The system can determine the status of the erase
operation by using DQ7 or DQ6. See “Write Opera-
tion Status” for information on these status bits.
When the Embedded Erase algorithm is complete,
the device returns to reading array data and ad-
dresses are no longer latched.
No
Increment Address
Last Address?
Yes
Figure 2 illustrates the algorithm for the erase opera-
tion. See the Erase/Program Operations tables in “AC
Characteristics” for parameters, and to the Chip/Sector
Erase Operation Timings for timing waveforms.
Programming
Completed
16736G-7
Sector Erase Command Sequence
Note: See the appropriate Command Definitions table for
program command sequence.
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two ad-
ditional unlock write cycles are then followed by the ad-
dress of the sector to be erased, and the sector erase
command. The Command Definitions table shows the
address and data requirements for the sector erase
command sequence.
Figure 1. Program Operation
The device does not require the system to preprogram
the memory prior to erase. The Embedded Erase algo-
rithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time be-
tween these additional cycles must be less than 50 µs,
otherwise the last address and command might not be
accepted, and erasure may begin. It is recommended
that processor interrupts be disabled during this time to
ensure all commands are accepted. The interrupts can
be re-enabled after the last Sector Erase command is
Am29F010
11
written. If the time between additional sector erase
commands can be assumed to be less than 50 µs, the
system need not monitor DQ3. Any command during
the time-out period resets the device to reading
array data. The system must rewrite the command se-
quence and any additional sector addresses and com-
mands.
START
Write Erase
Command Sequence
The system can monitor DQ3 to determine if the sector
erase timer has timed out. (See the “DQ3: Sector
Erase Timer” section.) The time-out begins from the ris-
ing edge of the final WE# pulse in the command se-
quence.
Data Poll
from System
Embedded
Erase
algorithm
in progress
Once the sector erase operation has begun, all other
commands are ignored.
No
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched. The system can determine the sta-
tus of the erase operation by using DQ7 or DQ6. Refer
to “Write Operation Status” for information on these
status bits.
Data = FFh?
Yes
Erasure Completed
Figure 2 illustrates the algorithm for the erase opera-
tion. Refer to the Erase/Program Operations tables in
the “AC Characteristics” section for parameters, and to
the Sector Erase Operations Timing diagram for timing
waveforms.
16736G-8
Notes:
1. See the appropriate Command Definitions table for erase
command sequence.
2. See “DQ3: Sector Erase Timer” for more information.
Figure 2. Erase Operation
12
Am29F010
Table 4. Am2F010 Command Definitions
Bus Cycles (Notes 2-3)
Third Fourth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
RA RD
XXXX F0
Command
Sequence
(Note 1)
First
Second
Fifth
Sixth
Read (Note 4)
1
1
4
4
Reset (Note 5)
Manufacturer ID
Device ID
5555
5555
AA 2AAA 55
5555
5555
90 XX00
90 XX01
01
20
AA 2AAA 55
Autoselect
(Note 6)
00
Sector Protect Verify
(Note 7)
(SA)
90
4
5555
AA 2AAA 55
5555
X02
01
Program
4
6
6
5555
5555
5555
AA 2AAA 55
AA 2AAA 55
AA 2AAA 55
5555
5555
5555
A0
80
80
PA
PD
AA
AA
Chip Erase
Sector Erase
5555
5555
2AAA 55
2AAA 55
5555
SA
10
30
Legend:
X = Don’t care
PD = Data to be programmed at location PA. Data latches on the
rising edge of WE# or CE# pulse, whichever happens first.
RA = Address of the memory location to be read.
SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A16–A14 uniquely select any sector.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed.
Addresses latch on the falling edge of the WE# or CE# pulse,
whichever happens later.
Notes:
1. See Table 1 for description of bus operations.
5. The Reset command is required to return to reading array
data when device is in the autoselect mode, or if DQ5 goes
high (while the device is providing status data).
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all command
bus cycles are write operations.
6. The fourth cycle of the autoselect command sequence is a
read operation.
4. No unlock or command cycles required when reading array
data.
7. The data is 00h for an unprotected sector and 01h for a
protected sector. See “Autoselect Command Sequence” for
more information.
Am29F010
13
WRITE OPERATION STATUS
The device provides several bits to determine the sta-
tus of a write operation: DQ3, DQ5, DQ6, and DQ7.
Table 5 and the following subsections describe the
functions of these bits. DQ7 and DQ6 each offer a
method for determining whether a program or erase
operation is complete or in progress. These three bits
are discussed first.
Table 5 shows the outputs for Data# Polling on DQ7.
Figure 3 shows the Data# Polling algorithm.
START
DQ7: Data# Polling
Read DQ7–DQ0
Addr = VA
The Data# Polling bit, DQ7, indicates to the host
system whether an Embedded Algorithm is in
progress or completed. Data# Polling is valid after
the rising edge of the final WE# pulse in the program
or erase command sequence.
Yes
DQ7 = Data?
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum pro-
grammed to DQ7. When the Embedded Program algo-
rithm is complete, the device outputs the datum
programmed to DQ7. The system must provide the
program address to read valid status information on
DQ7. If a program address falls within a protected sec-
tor, Data# Polling on DQ7 is active for approximately 2
µs, then the device returns to reading array data.
No
No
DQ5 = 1?
Yes
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase al-
gorithm is complete, Data# Polling produces a “1” on
DQ7. This is analogous to the complement/true datum
output described for the Embedded Program algorithm:
the erase function changes all the bits in a sector to “1”;
prior to this, the device outputs the “complement,” or
“0.” The system must provide an address within any of
the sectors selected for erasure to read valid status in-
formation on DQ7.
Read DQ7–DQ0
Addr = VA
Yes
DQ7 = Data?
After an erase command sequence is written, if all sec-
tors selected for erasing are protected, Data# Polling
on DQ7 is active for approximately 100 µs, then the de-
vice returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se-
lected sectors that are protected.
No
PASS
FAIL
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
When the system detects DQ7 has changed from the
complement to true data, it can read valid data at DQ7–
DQ0 on the following read cycles. This is because DQ7
may change asynchronously with DQ0–DQ6 while
Output Enable (OE#) is asserted low. The Data# Poll-
ing Timings (During Embedded Algorithms) figure in
the “AC Characteristics” section illustrates this.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
16736G-9
Figure 3. Data# Polling Algorithm
14
Am29F010
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete.
Toggle Bit I may be read at any address, and is valid
after the rising edge of the final WE# pulse in the com-
mand sequence (prior to the program or erase opera-
tion), and during the sector erase time-out.
START
Read DQ7–DQ0
During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address cause
DQ6 to toggle. (The system may use either OE# or
CE# to control the read cycles.) When the operation is
complete, DQ6 stops toggling.
Read DQ7–DQ0
1
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 tog-
gles for approximately 100 µs, then returns to reading
array data. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unpro-
tected sectors, and ignores the selected sectors that
are protected.
No
Toggle Bit
= Toggle?
Yes
No
If a program address falls within a protected sector,
DQ6 toggles for approximately 2 µs after the program
command sequence is written, then returns to reading
array data.
DQ5 = 1?
Yes
The Write Operation Status table shows the outputs for
Toggle Bit I on DQ6. Refer to Figure 4 for the toggle bit
algorithm, and to the Toggle Bit Timings figure in the
“AC Characteristics” section for the timing diagram.
(Notes
1, 2)
Read DQ7–DQ0
Twice
Reading Toggle Bit DQ6
Toggle Bit
= Toggle?
No
Refer to Figure 4 for the following discussion. When-
ever the system initially begins reading toggle bit sta-
tus, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, a
system would note and store the value of the toggle
bit after the first read. After the second read, the sys-
tem would compare the new value of the toggle bit
with the first. If the toggle bit is not toggling, the device
has completed the program or erase operation. The
system can read array data on DQ7–DQ0 on the fol-
lowing read cycle.
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Notes:
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is
high (see the section on DQ5). If it is, the system
should then determine again whether the toggle bit is
toggling, since the toggle bit may have stopped tog-
gling just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the
device did not complete the operation successfully, and
the system must write the reset command to return to
reading array data.
2. Recheck toggle bit because it may stop toggling as DQ5
changes to “1”. See text.
16736G-10
Figure 4. Toggle Bit Algorithm
gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles, de-
termining the status as described in the previous para-
graph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the
beginning of the algorithm when it returns to determine
the status of the operation (top of Figure 4).
The remaining scenario is that the system initially de-
termines that the toggle bit is toggling and DQ5 has not
Am29F010
15
tional sectors are selected for erasure, the entire time-
out also applies after each additional sector erase
command. When the time-out is complete, DQ3
switches from “0” to “1.” The system may ignore DQ3
if the system can guarantee that the time between ad-
ditional sector erase commands will always be less
than 50 µs. See also the “Sector Erase Command Se-
quence” section.
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a “1.” This is a failure
condition that indicates the program or erase cycle was
not successfully completed.
The DQ5 failure condition may appear if the system
tries to program a “1” to a location that is previously
programmed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the
device halts the operation, and when the operation has
exceeded the timing limits, DQ5 produces a “1.”
After the sector erase command sequence is written,
the system should read the status on DQ7 (Data# Poll-
ing) or DQ6 (Toggle Bit I) to ensure the device has ac-
cepted the command sequence, and then read DQ3. If
DQ3 is “1”, the internally controlled erase cycle has be-
gun; all further commands are ignored until the erase
operation is complete. If DQ3 is “0”, the device will ac-
cept additional sector erase commands. To ensure the
command has been accepted, the system software
should check the status of DQ3 prior to and following
each subsequent sector erase command. If DQ3 is
high on the second status check, the last command
might not have been accepted. Table 5 shows the out-
puts for DQ3.
Under both these conditions, the system must issue
the reset command to return the device to reading
array data.
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If addi-
Table 5. Write Operation Status
DQ7
DQ5
Operation
Embedded Program Algorithm
Embedded Erase Algorithm
Notes:
(Note 1)
DQ6
(Note 2)
DQ3
N/A
1
DQ7#
0
Toggle
Toggle
0
0
1. DQ7 requires a valid address when reading status information. Refer to the appropriate subsection for further details.
2. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “DQ5: Exceeded Timing Limits” for more information.
16
Am29F010
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –65°C to +125°C
20 ns
20 ns
+0.8 V
Ambient Temperature
with Power Applied . . . . . . . . . . . . . –55°C to +125°C
–0.5 V
–2.0 V
Voltage with Respect to Ground
VCC (Note 1). . . . . . . . . . . . . . . . . . . .–2.0 V to +7.0 V
A9 (Note 2). . . . . . . . . . . . . . . . . . . .–2.0 V to +12.5 V
All other pins (Note 1) . . . . . . . . . . . .–2.0 V to +7.0 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
20 ns
16736G-11
Notes:
Figure 5. Maximum Negative Overshoot
Waveform
1. Minimum DC voltage on input or I/O pin is –0.5 V. During
voltage transitions, inputs may overshoot V to –2.0 V
SS
for periods of up to 20 ns. See Figure 5. Maximum DC
voltage on input and I/O pins is V + 0.5 V. During volt-
CC
age transitions, input and I/O pins may overshoot to V
+ 2.0 V for periods up to 20 ns. See Figure 6.
CC
20 ns
V
2. Minimum DC input voltage on A9 pin is –0.5V. During
CC
+2.0 V
V
+0.5 V
voltage transitions, A9 pins may overshoot V to –2.0 V
SS
CC
for periods of up to 20 ns. See Figure 5. Maximum DC in-
put voltage on A9 is +12.5 V which may overshoot to 13.5
V for periods up to 20 ns.
2.0 V
3. No more than one output shorted at a time. Duration of
the short circuit should not be greater than one second.
20 ns
20 ns
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is
a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the op-
erational sections of this specification is not implied. Expo-
sure of the device to absolute maximum rating conditions for
extended periods may affect device reliability.
16736G-12
Figure 6. Maximum Positive Overshoot
Waveform
OPERATING RANGES
Commercial (C) Devices
Case Temperature (TA) . . . . . . . . . . . . . 0°C to +70°C
Industrial (I) Devices
Case Temperature (TA) . . . . . . . . . . . –40°C to +85°C
Extended (E) Devices
Case Temperature (TA) . . . . . . . . . . –55°C to +125°C
V
Supply Voltages
CC
VCC for ±5% devices . . . . . . . . . . .+4.75 V to +5.25 V
VCC for ±10% devices . . . . . . . . . .+4.50 V to +5.50 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
Am29F010
17
DC CHARACTERISTICS
TTL/NMOS Compatible
Parameter
Symbol
Parameter Description
Test Description
= V to V , V = V Max
Min
Max
±1.0
50
Unit
µA
µA
µA
mA
mA
mA
V
I
Input Load Current
V
V
V
LI
IN
SS
CC
CC
CC
I
A9 Input Load Current
Output Leakage Current
= V Max, A9 = 12.5 V
LIT
CC
OUT
CC
I
= V to V , V = V Max
±1.0
30
LO
SS
CC
CC
CC
I
I
I
V
V
V
Active Current (Note 1)
CE# = V OE# = V
V
= V Max
CC1
CC2
CC3
CC
CC
CC
IL,
IH, CC CC
Active Current (Notes 2, 3) CE# = V OE# = V
V
= V Max
50
IL,
IH, CC
CC
Standby Current
V
V
Max, CE# and OE# = V
1.0
0.8
CC = CC
IH
V
Input Low Voltage
–0.5
2.0
IL
V
Input High Voltage
V
+ 0.5
V
IH
CC
Voltage for Autoselect and
Temporary Sector Unprotect
V
V
= 5.0 V
11.5
12.5
0.45
V
ID
CC
V
Output Low Voltage
Output High Voltage
I
I
= 12 mA, V = V Min
V
V
V
OL
OL
CC
CC
V
= –2.5 mA, V = V Min
2.4
3.2
OH
OH
CC
CC
V
Low V Lock-out Voltage
4.2
LKO
CC
Notes:
1. The I current listed is typically less than 2 mA/MHz, with OE# at V .
CC
IH
2. I active while Embedded Program or Embedded Erase Algorithm is in progress.
CC
3. Not 100% tested.
18
Am29F010
DC CHARACTERISTICS (continued)
CMOS Compatible
Parameter
Symbol
Parameter Description
Input Load Current
Test Description
= V to V , V = V Max
Min
Max
±1.0
50
Unit
µA
I
V
V
V
LI
IN
SS
CC
CC
CC
I
A9 Input Load Current
Output Leakage Current
= V Max, A9 = 12.5 V
µA
LIT
CC
OUT
CC
I
= V to V , V = V Max
±1.0
30
µA
LO
SS
CC
CC
CC
I
I
V
V
Active Current (Note 1)
CE# = V OE# = V
V
= V Max
mA
mA
CC1
CC2
CC
CC
IL,
IH, CC
CC
Active Current (Notes 2, 3) CE# = V OE# = V
V
= V Max
50
IL,
IH, CC
CC
V
= V Max, CE# = V
± 0.5 V,
CC
CC
CC
I
V
Standby Current
100
µA
CC3
CC
OE# = V
IH
V
Input Low Voltage
–0.5
0.8
V
V
IL
V
Input High Voltage
0.7 x V
V
+ 0.5
IH
CC
CC
Voltage for Autoselect and
Temporary Sector Unprotect
V
V
= 5.0 V
CC
11.5
12.5
0.45
V
ID
V
Output Low Voltage
I
I
I
= 12 mA, V = V Min
V
V
V
V
OL
OL
OH
OH
CC
CC
V
V
V
= –2.5 mA, V = V Min
0.85 V
CC
OH1
OH2
LKO
CC
CC
Output High Voltage
= –100 µA, V = V Min
V
–0.4
CC
CC
CC
Low V Lock-out Voltage
3.2
4.2
CC
Notes:
1. The I current listed is typically less than 2 mA/MHz, with OE# at V .
CC
IH
2. I active while Embedded Program or Embedded Erase Algorithm is in progress.
CC
3. Not 100% tested.
Am29F010
19
TEST CONDITIONS
Table 6. Test Specifications
5.0 V
Test Condition
-45
All others Unit
Output Load
1 TTL gate
100
2.7 kΩ
Device
Under
Test
Output Load Capacitance, C
(including jig capacitance)
L
30
5
pF
C
L
Input Rise and Fall Times
Input Pulse Levels
20
ns
6.2 kΩ
0.0–3.0 0.45–2.4
V
Input timing measurement
reference levels
1.5
1.5
0.8
2.0
V
V
Output timing measurement
reference levels
Note: Diodes are IN3064 or equivalent
16736G-13
Figure 7. Test Setup
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
KS000010-PAL
20
Am29F010
AC CHARACTERISTICS
Read-only Operations Characteristics
Parameter
Symbol
JEDEC
Std.
Parameter Description
Test Setup
-45
-55
-70
-90
-120 Unit
t
t
t
Read Cycle Time (Note 1)
Min
45
55
70
90
120
120
ns
ns
AVAV
RC
CE# = V
OE# = V
IL
t
Address to Output Delay
Max
45
55
70
90
AVQV
ACC
IL
t
t
t
t
Chip Enable to Output Delay
Output Enable to Output Delay
OE# = V
Max
Max
45
25
55
30
70
30
90
35
120
50
ns
ns
ELQV
GLQV
CE
OE
IL
Chip Enable to Output High Z
(Notes 1, 2)
t
t
t
Max
10
10
15
15
20
20
20
30
30
ns
EHQZ
GHQZ
DF
DF
Output Enable to Output High Z
(Notes 1, 2)
t
Max
Min
Min
20
0
ns
ns
ns
Read
Output Enable Hold Time
(Note 1)
t
t
OEH
OH
Toggle and Data
Polling
10
Output Hold Time From
Addresses CE# or OE#,
Whichever Occurs First
t
Min
0
ns
AXQX
Notes:
1. Not 100% tested.
2. Output Driver Disable Time.
3. See Figure 7 and Table 6 for test specifications.
tRC
Addresses Stable
tACC
Addresses
CE#
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
16736G-14
Figure 8. Read Operations Timings
Am29F010
21
AC CHARACTERISTICS
Erase and Program Operations
Parameter Symbol
JEDEC
Standard
Parameter Description
Write Cycle Time (Note 1)
-45
-55
-70
70
0
-90
-120 Unit
t
t
t
t
t
t
t
t
t
t
Min
Min
Min
Min
Min
45
55
90
120
ns
ns
ns
ns
ns
AVAV
WC
AS
AH
DS
DH
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
AVWL
WLAX
DVWH
WHDX
35
20
45
20
45
30
0
45
45
50
50
Read Recover Time Before Write
(OE# High to WE# Low)
t
t
Min
0
ns
GHWL
GHWL
t
t
t
t
t
t
t
t
CE# Setup Time
Min
Min
Min
Min
0
0
ns
ns
ns
ns
ELWL
CS
CE# Hold Time
WHEH
WLWH
WHWL
CH
Write Pulse Width
Write Pulse Width High
25
30
35
20
45
50
WP
WPH
Byte Programming Operation
(Note 2)
t
t
t
Typ
14
µs
WHWH1
WHWH2
WHWH1
t
t
Sector Erase Operation (Note 2)
Typ
Min
1.0
50
sec
WHWH2
V
Set Up Time (Note 1)
µs
VCS
CC
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more informaiton.
22
Am29F010
AC CHARACTERISTICS
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tAS
tWC
Addresses
555h
PA
PA
PA
tAH
CE#
OE#
tCH
tGHWL
tWHWH1
tWP
WE#
tWPH
tCS
tDS
tDH
PD
DOUT
A0h
Status
Data
VCC
tVCS
16736G-13
Note: PA = program address, PD = program data, D
is the true data at the program address.
OUT
Figure 9. Program Operation Timings
Erase Command Sequence (last two cycles)
Read Status Data
VA
tAS
tWC
VA
Addresses
CE#
2AAh
SA
555h for chip erase
tAH
tGHWL
tCH
OE#
tWP
WE#
tWPH
tWHWH2
tCS
tDS
tDH
In
Data
VCC
Complete
55h
30h
Progress
10 for Chip Erase
tVCS
16736G-13
Note: SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).
Figure 10. Chip/Sector Erase Operation Timings
Am29F010
23
AC CHARACTERISTICS
tRC
VA
Addresses
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
WE#
tOEH
tDF
tOH
High Z
High Z
DQ7
Valid Data
Complement
Complement
True
DQ0–DQ6
Valid Data
Status Data
True
Status Data
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
16736G-15
Figure 11. Data# Polling Timings (During Embedded Algorithms)
tRC
Addresses
CE#
VA
tACC
tCE
VA
VA
VA
tCH
tOE
OE#
WE#
tOEH
tDF
tOH
High Z
DQ6
Valid Status
(first read)
Valid Status
Valid Status
Valid Data
(second read)
(stops toggling)
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read
cycle, and array data read cycle.
16736G-16
Figure 12. Toggle Bit Timings (During Embedded Algorithms)
24
Am29F010
AC CHARACTERISTICS
Erase and Program Operations
Alternate CE# Controlled Writes
Parameter Symbol
JEDEC
Standard
Parameter Description
Write Cycle Time (Note 1)
-45
-55
-70
70
0
-90
-120
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
45
55
90
120
AVAV
WC
AS
Address Setup Time
Address Hold Time
AVEL
ELAX
DVEH
EHDX
35
20
45
20
45
30
0
45
45
50
50
AH
Data Setup Time
DS
Data Hold Time
DH
Output Enable Setup Time (Note 1)
Read Recover Time Before Write
WE# Setup Time
0
OES
GHEL
WS
WH
CP
t
t
t
t
t
0
GHEL
WLEL
EHWH
ELEH
EHEL
0
WE# Hold Time
0
CE# Pulse Width
25
30
35
20
45
50
CE# Pulse Width High
CPH
Byte Programming Operation
(Note 2)
t
t
t
Typ
Typ
14
µs
WHWH1
WHWH2
WHWH1
WHWH2
Chip/Sector Erase Operation
(Note 2)
t
1.0
sec
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
Am29F010
25
AC CHARACTERISTICS
555 for program
PA for program
2AA for erase
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tWH
tAS
tAH
WE#
OE#
tGHEL
tWHWH1 or 2
tCP
CE#
Data
tWS
tCPH
tDS
tDH
DQ7#
DOUT
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
Notes:
1. PA = Program Address, PD = Program Data, SA = Sector Address, DQ7# = Complement of Data Input, D
= Array Data.
OUT
2. Figure indicates the last two bus cycles of the command sequence.
16736G-17
Figure 13. Alternate CE# Controlled Write Operation Timings
ERASE AND PROGRAMMING PERFORMANCE
Limits
Parameter
Typ (Note 1)
Max (Note 2)
Unit
Comments
Excludes 00h programming prior to
erasure (Note 4)
Chip/Sector Erase Time
1.0
15
sec
Byte Programming Time
14
1000
12.5
µs
Excludes system-level overhead
(Note 5)
Chip Programming Time (Note 3)
1.8
sec
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 5.0 V V , 100,000 cycles. Additionally,
CC
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, V = 4.5 V (4.75 V for -45, -55 PDIP), 100,000 cycles.
CC
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then
does the device set DQ5 = 1. See the section on DQ5 for further information.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 1
for further information on command definitions.
6. The device has a typical erase and program cycle endurance of 1,000,000 cycles. 100,000 cycles are guaranteed.
26
Am29F010
LATCHUP CHARACTERISTIC
Parameter Description
Input Voltage with respect to V on I/O pins
Min
Max
+ 1.0 V
–1.0 V
V
CC
SS
V
Current
–100 mA
+100 mA
CC
Note: Includes all pins except V . Test conditions: V = 5.0 Volt, one pin at a time.
CC
CC
TSOP PIN CAPACITANCE
Parameter
Symbol
Parameter Description
Test Conditions
Typ
6
Max
7.5
12
Unit
pF
C
Input Capacitance
V
V
V
= 0
IN
IN
C
Output Capacitance
Control Pin Capacitance
= 0
= 0
8.5
8
pF
OUT
OUT
C
10
pF
IN2
IN
Notes:
1. Sampled, not 100% tested.
2. Test conditions T = 25°C, f = 1.0 MHz.
A
PLCC AND PDIP PIN CAPACITANCE
Parameter
Symbol
Parameter Description
Input Capacitance
Test Conditions
Typ
4
Max
6
Unit
pF
C
V
V
V
= 0
IN
IN
C
Output Capacitance
= 0
8
12
12
pF
OUT
OUT
C
Control Pin Capacitance
= 0
PP
8
pF
IN2
Notes:
1. Sampled, not 100% tested.
2. Test conditions T = 25°C, f = 1.0 MHz.
A
DATA RETENTION
Parameter Description
Test Conditions
150°C
Min
10
Unit
Years
Years
Minimum Pattern Data Retention Time
20
125°C
Am29F010
27
PHYSICAL DIMENSIONS
PD 032
32-Pin Plastic DIP (measured in inches)
1.640
1.680
.600
.625
17
16
32
.008
.015
.530
.580
Pin 1 I.D.
.630
.700
.045
.065
0˚
10˚
.005 MIN
.140
.225
16-038-SB_AG
PD 032
DG75
SEATING PLANE
.090
.110
.015
.060
.014
.022
2-28-95 ae
.120
.160
PL 032
32-Pin Plastic Leaded Chip Carrier (measured in inches)
.485
.495
.447
.453
.009
.015
.042
.056
.125
.140
.585
.595
Pin 1 I.D.
.080
.095
.547
.553
SEATING
PLANE
.400
REF.
.490
.530
.013
.021
.050 REF.
16-038FPO-5
PL 032
DA79
.026
.032
TOP VIEW
SIDE VIEW
6-28-94 ae
28
Am29F010
PHYSICAL DIMENSIONS (continued)
TS 032
32-Pin Standard Thin Small Outline Package (measured in millimeters)
0.95
1.05
Pin 1 I.D.
1
7.90
8.10
0.50 BSC
0.05
0.15
18.30
18.50
19.80
20.20
0.08
16-038-TSOP-2
TS 032
DA95
1.20
MAX
0.20
0.10
0.21
4-4-95 ae
0°
5°
0.25MM (0.0098") BSC
0.50
0.70
Am29F010
29
PHYSICAL DIMENSIONS (continued)
TSR 032
32-Pin Standard Thin Small Outline Package (measured in millimeters)
0.95
1.05
Pin 1 I.D.
1
7.90
8.10
0.50 BSC
0.05
0.15
18.30
18.50
19.80
20.20
16-038-TSOP-2
TSR032
DA95
0.08
1.20
MAX
0.20
0.10
0.21
4-4-95 ae
0°
5°
0.25MM (0.0098") BSC
0.50
0.70
30
Am29F010
REVISION SUMMARY FOR AM29F010
Revision F+1
Erase and Programming Performance
Combined chip and sector erase specifications;
changed typical and maximum values. Added Note 6.
Product Selector Guide
There are now two VCC supply operating ranges avail-
able for the 55 ns speed option. The PDIP package is
only available in the ±5% VCC operating range. The
other packages are available in the ±10% operating
range.
Revision G
Global
Made formatting and layout consistent with other data
sheets. Used updated common tables and diagrams.
Ordering Information
Revision G+1
The 45 ns speed grade is now also available in PC con-
figuration (PDIP package, commercial temperature.)
Table 4, Command Definitions
Address bits A0–A14 are required for unlock cycles.
Therefore, addresses for second and fifth write cycles
are 2AAAh. Addresses for first, third, fourth, and sixth
cycles are 5555h. Read cycles are not affected. De-
leted Note 4 to reflect the correction.
Operating Ranges
VCC Supply Voltages: Changed to reflect the available
speed options.
AC Characteristics
Write/Erase/Program Operations: Corrected to indicate
tVLHT, tOESP, tWHWH1, and tWHWH2 are typical values,
Revision G+2
AC Characteristics
not minimum values. Changed value for tWHWH2
.
Erase/Program Operations; Erase and Program Oper-
ations Alternate CE# Controlled Writes: Corrected the
notes reference for tWHWH1 and tWHWH2. These param-
eters are 100% tested. Corrected the note reference
for tVCS. This parameter is not 100% tested.
AC Characteristics
Write/Erase/Program Operations, Alternate CE# Con-
trolled Writes: Corrected to indicate tWHWH1 and
tWHWH2 are typical values, not minimum values.
Changed value for tWHWH2
.
Trademarks
Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
Am29F010
31
相关型号：
©2020 ICPDF网 联系我们和版权申明