AM29LV010BT-55EIB [AMD]
1 Megabit (128 K x 8-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory; 1兆位（ 128千×8位） CMOS 3.0伏只统一部门快闪记忆体
| 型号： | AM29LV010BT-55EIB |
| 厂家： | 
AMD |
| 描述： | 1 Megabit (128 K x 8-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory |
| 文件： | 总7页 (文件大小：66K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADVANCE INFORMATION
Am29LV010B
1 Megabit (128 K x 8-Bit)
CMOS 3.0 Volt-only Uniform Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■ Single power supply operation
■ Unlock Bypass Mode Program Command
— Full voltage range: 2.7 to 3.6 volt read and write
operations for battery-powered applications
— Reduces overall programming time when
issuing multiple program command sequences
— Regulated voltage range: 3.0 to 3.6 volt read and
write operations and for compatibility with high
performance 3.3 volt microprocessors
■ Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
■ Manufactured on 0.35 µm process technology
■ High performance
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
— Full voltage range: access times as fast as 55 ns
— Regulated voltage range: access times as fast
as 45 ns
■ Minimum 1,000,000 write cycle guarantee per
sector
■ Package option
■ Ultra low power consumption (typical values at
5 MHz)
— 32-pin TSOP
— 200 nA Automatic Sleep mode current
— 200 nA standby mode current
— 7 mA read current
— 32-pin PLCC
■ Compatibility with JEDEC standards
— Pinout and software compatible with single-
power supply Flash
— 15 mA program/erase current
— Superior inadvertent write protection
■ Flexible sector architecture
— Eight 16 Kbyte
■ Data# Polling and toggle bits
— Provides a software method of detecting
program or erase operation completion
— Supports full chip erase
— Sector Protection features:
■ Erase Suspend/Erase Resume
Hardware method of locking a sector to prevent
any program or erase operations within that
sector
— Supports reading data from or programming
data to a sector that is not being erased
Sectors can be locked in-system or via
programming equipment
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Publication# 22140 Rev: A Amendment/0
Issue Date: April 1998
A D V A N C E I N F O R M A T I O N
GENERAL DESCRIPTION
The Am29LV010B is a 1 Mbit, 3.0 Volt-only Flash
memory device organized as 131,072 bytes. The
Am29LV010B has a uniform sector architecture.
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The device is offered in 32-pin PLCC and 32-pin TSOP
packages. The byte-wide (x8) data appears on DQ7–
DQ0. All read, erase, and program operations are
accomplished using only a single power supply. The
device can also be programmed in standard EPROM
programmers.
The host system can detect whether a program or
erase operation is complete by reading the DQ7 (Data#
Polling) and DQ6 (toggle) status bits. After a program
or erase cycle has been completed, the device is ready
to read array data or accept another command.
The standard Am29LV010B offers access times of 45,
55, 70, and 120 ns (90 and 100 ns parts are also avail-
able), allowing high speed microprocessors to operate
without wait states. To eliminate bus contention, the
device has separate chip enable (CE#), write enable
(WE#) and output enable (OE#) controls.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
VCC detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved in-system or via program-
ming equipment.
The device requires only a single power supply (2.7
V–3.6V) for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Com-
mands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The device offers two power-saving features. When ad-
dresses have been stable for a specified amount of
time, the device enters the automatic sleep mode.
The system can also place the device into the standby
mode. Power consumption is greatly reduced in both
these modes.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin. The Unlock Bypass mode facili-
tates faster programming times by requiring only two
write cycles to program data instead of four.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tun-
neling. The data is programmed using hot electron
injection.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the Embedded Erase
Am29LV010B
2
A D V A N C E I N F O R M A T I O N
PRODUCT SELECTOR GUIDE
Family Part Number
Am29LV010B
Regulated Voltage Range: V =3.0–3.6 V
-45R
CC
Speed Options
Max access time, ns (t
Full Voltage Range: V = 2.7–3.6 V
-55
-70
70
70
35
-120
120
120
50
CC
)
45
45
30
55
55
30
ACC
Max CE# access time, ns (t
)
CE
Max OE# access time, ns (t
)
OE
Note: See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
DQ0–DQ7
V
CC
Sector Switches
V
SS
Erase Voltage
Generator
Input/Output
Buffers
State
Control
WE#
Command
Register
PGM Voltage
Generator
Data
Latch
Chip Enable
Output Enable
Logic
STB
CE#
OE#
Y-Decoder
X-Decoder
Y-Gating
STB
V
Detector
Timer
CC
Cell Matrix
A0–A16
22140A-1
3
Am29LV010B
A D V A N C E I N F O R M A T I O N
CONNECTION DIAGRAMS
A11
A9
A8
OE#
A10
CE#
1
2
3
32
31
30
A13
A14
NC
WE#
VCC
NC
A16
A15
A12
A7
4
5
6
7
8
9
10
11
12
13
14
15
16
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
29
28
27
26
25
24
23
22
21
20
19
18
17
32-Pin Standard TSOP
A6
A5
A4
A1
A2
A3
1
2
3
A11
A9
A8
OE#
A10
CE#
32
31
30
4
5
6
7
8
9
10
11
12
13
14
15
16
A13
A14
NC
WE#
VCC
NC
A16
A15
A12
A7
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
29
28
27
26
25
24
23
22
21
20
19
18
17
32-Pin Reverse TSOP
A6
A5
A4
A1
A2
A3
4
3 2 1 32 31 30
A7
A6
5
6
A14
A13
29
28
A5
A4
7
A8
27
26
25
24
23
22
21
8
A9
PLCC
A3
9
A11
OE#
A10
CE#
DQ7
A2
10
11
12
13
A1
A0
DQ0
16 17
19 20
18
15
14
22140A-2
Am29LV010B
4
A D V A N C E I N F O R M A T I O N
PIN CONFIGURATION
LOGIC SYMBOL
A0–A16
= 17 addresses
17
DQ0–DQ7 = 8 data inputs/outputs
A0–A16
8
CE#
OE#
WE#
VCC
=
=
=
=
Chip enable
Output enable
Write enable
DQ0–DQ7
CE#
OE#
3.0 volt-only single power supply
(see Product Selector Guide for speed
options and voltage supply tolerances)
WE#
VSS
NC
=
=
Device ground
Pin not connected internally
22140A-3
5
Am29LV010B
A D V A N C E I N F O R M A T I O N
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combi-
nation) is formed by a combination of the elements below.
Am29LV010B
T
-45R
E
C
OPTIONAL PROCESSING
Blank = Standard Processing
B = Burn-in
(Contact an AMD representative for more information)
TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
E = Extended (–55°C to +125°C)
PACKAGE TYPE
E
F
J
=
=
=
32-Pin Thin Small Outline Package (TSOP)
Standard Pinout (TS 032)
32-Pin Thin Small Outline Package (TSOP)
Reverse Pinout (TSR032)
32-Pin Rectangular Plastic Leaded Chip
Carrier (PL 032)
SPEED OPTION
See Product Selector Guide and Valid Combinations
BOOT CODE SECTOR ARCHITECTURE
T = Top Sector
B = Bottom Sector
DEVICE NUMBER/DESCRIPTION
Am29LV010B
1 Megabit (128 K x 8-Bit) CMOS Flash Memory
3.0 Volt-only Read, Program, and Erase
Valid Combinations
Valid Combinations
EC, FC, JC
Valid Combinations list configurations planned to be sup-
ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
Am29LV010B-45R
Am29LV010B-55
Am29LV010B-70
Am29LV010B-120
EC, EI, EE,
FC, FI, FE,
JC, JI, JE
Am29LV010B
6
A D V A N C E I N F O R M A T I O N
Valid Combinations
REVISION SUMMARY
Revision A
Changes since publication number 21557A was
released: deleted the “R” designation from the 55 ns
option. Corrected the part numbers.
Split the Am29LV001B/Am29LV010B data sheet into
separate documents. The Am29LV001B data sheet
retains publication number 21557B and later; the
Am29LV010B data sheet has been reassigned publica-
tion number 22140.
Trademarks
Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
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Am29LV010B
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