AM29LV641GH55PCI [AMD]
64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O⑩ Control; 64兆位(4M ×16位) CMOS 3.0伏只统一部门快闪记忆体与VersatileI / O⑩控制型号: | AM29LV641GH55PCI |
厂家: | AMD |
描述: | 64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O⑩ Control |
文件: | 总55页 (文件大小:1145K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Am29LV641G
Data Sheet
RETIRED
PRODUCT
This product has been retired and is not recommended for designs. For new and current designs,
S29GL064A supersedes Am29LV641G and is the factory-recommended migration path. Please refer
to the S29GL064A datasheet for specifications and ordering information. Availability of this docu-
ment is retained for reference and historical purposes only.
June 2005
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that
originally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appro-
priate, and changes will be noted in a revision summary.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number 25295 Revision A Amendment +3 Issue Date June 14, 2005
THIS PAGE LEFT INTENTIONALLY BLANK.
ADVANCE INFORMATION
Am29LV641G
64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only
Uniform Sector Flash Memory with VersatileI/O™ Control
This product has been retired and is not recommended for designs. For new and current designs, S29GL064A supersedes Am29LV641G and is the factory-recommended migration path.
Please refer to the S29GL064A datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only.
DISTINCTIVE CHARACTERISTICS
■ Ultra low power consumption (typical values at 3.0 V,
ARCHITECTURAL ADVANTAGES
5 MHz)
■ Single power supply operation
— 9 mA typical active read current
— 26 mA typical erase/program current
— 200 nA typical standby mode current
— 2.7 to 3.6 volt read, erase, and program operations
■ SecSi™ (Secured Silicon) Sector region
— 128-word sector for permanent, secure identification
through an 8-word random Electronic Serial Number
■ Program and erase performance (VHH not applied to
the ACC input pin)
— May be programmed and locked at the factory or by
the customer
— Word program time: 7 µs typical
— Sector erase time: 0.6 s typical for each 32 Kword
sector
— Accessible through a command sequence
■ VersatileI/O™ control
— Device generates data output voltages and tolerates
data input voltages as determined by the voltage on
the VIO pin
SOFTWARE AND HARDWARE FEATURES
■ Hardware features
— Hardware reset input (RESET#): resets device for
■ Manufactured on 0.18 µm process technology
new operation
— WP# input: protects first or last 32 Kword sector
regardless of sector protection settings
(LV641GH/L only)
■ Flexible sector architecture
— One hundred twenty-eight 32 Kword sectors
■ Compatibility with JEDEC standards
— ACC input: Accelerates programming time for higher
— Pinout and software compatible with single-power
supply Flash standard
throughput during system production
■ Software features
■ Package options
— Program Suspend & Resume: read other sectors
— 48-pin TSOP and Reverse TSOP (LV641GH/L only)
— 63-ball Fine-Pitch BGA (LV640GU only)
before programming operation is completed
— Sector Group Protection: VCC-level method of
preventing program or erase operations within a
sector
— 64-ball Fortified BGA (LV640GU only)
■ Minimum 1 million erase cycle guarantee per sector
■ 20-year data retention at 125°C
— Temporary Sector Group Unprotect: VID-level method
of changing in previously locked sectors
— CFI (Common Flash Interface) compliant: allows host
system to identify and accommodate multiple flash
devices
PERFORMANCE CHARCTERISTICS
■ High performance
— Access time ratings as fast as 55 ns
— Erase Suspend/Erase Resume: read/program other
sectors before an erase operation is complete
— Data# Polling and toggle bits provide erase and
programming operation status
— Unlock Bypass Program command reduces overall
multiple-word programming time
Publication# 25295 Rev: A Amendment/+3
Issue Date: June 14, 2005
This document contains information on a product under development at Advance Micro Devices. The information is
intended to help you evaluate this product. Do not design in the product without contacting the factory. AMD reserves
the right to change or discontinue work on this proposed product without notice.
Refer to AMD’s Website (www.amd.com) for the latest information.
A D V A N C E I N F O R M A T I O N
GENERAL DESCRIPTION
The Am29LV641G are 64 Mbit, 3.0 volt (3.0 V to 3.6 V)
single power supply flash memory devices organized
as 4,194,304 words. Data appears on DQ15–DQ0.
These devices are designed to be programmed in-sys-
tem with the standard system 3.0 volt VCC supply. A
12.0 volt VPP is not required for program or erase oper-
ations. The device can also be programmed in stan-
dard EPROM programmers.
vice is ready to read array data or accept another
command.
The sector erase architecture allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
VCC detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of sectors of memory.
This can be achieved in-system or via programming
equipment.
Access times of 55 regulated volage and 70 ns full
voltage range are available for applications where VIO
≥ VCC. The Am29LV641GH/L is offered in 48-pin
TSOP and reverse TSOP packages. The
Am29LV640GU is offered in a 63-ball Fine-pitch BGA
package, and a 64-ball Fortified BGA. To eliminate bus
contention each device has separate chip enable
(CE#), write enable (WE#) and output enable (OE#)
controls.
The Erase Suspend/Erase Resume feature enables
the user to put erase on hold for any period of time to
read data from, or program data to, any sector that is
not selected for erasure. True background erase can
thus be achieved. The Program Suspend/Program
Resume feature enables the host system to pause a
program operation in a given sector to read any other
sector and then complete the program operation.
Each device requires only a single 3.0 volt power
supply (2.7 V to 3.6 V) for both read and write func-
tions. Internally generated and regulated voltages are
provided for the program and erase operations.
The device is entirely command set compatible with
the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timing. Register con-
tents serve as inputs to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data
needed for the programming and erase operations.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to
the system reset circuitry. A system reset would thus
also reset the device, enabling the system micropro-
cessor to read boot-up firmware from the Flash mem-
ory device.
The device offers a standby mode as a power-saving
feature. Once the system places the device into the
standby mode power consumption is greatly reduced.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin. The Unlock Bypass mode facili-
tates faster programming times by requiring only two
write cycles to program data instead of four.
The SecSi™ (Secured Silicon) Sector provides an
minimum 128-word area for code or data that can be
permanently protected. Once this sector is protected,
no further programming or erasing within the sector
can occur.
The Write Protect (WP#) feature protects the first or
last sector by asserting a logic low on the WP# pin.
The protected sector will still be protected even during
accelerated programming. (Am29LV641GH/L only)
Device erasure occurs by executing the erase com-
mand sequence. This initiates the Embedded Erase
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already pro-
grammed) before executing the erase operation. Dur-
ing erase, the device automatically times the erase
pulse widths and verifies proper cell margin.
The accelerated program (ACC) feature allows the
system to program the device at a much faster rate.
When ACC is pulled high to VHH, the device enters the
Unlock Bypass mode, enabling the user to reduce the
time needed to do the program operation. This feature
is intended to increase factory throughput during sys-
tem production, but may also be used in the field if de-
sired.
The VersatileI/O™ (VIO) control allows the host sys-
tem to set the voltage levels that the device generates
at its data outputs and the voltages tolerated at its
data inputs to the same voltage level that is asserted
on the VIO pin. This allows the device to operate in 1.8
V or 3 V system environment as required.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunnelling.
The data is programmed using hot electron injection.
The host system can detect whether a program or
erase operation is complete by reading the DQ7
(Data# Polling) or DQ6 (toggle) status bits. After a
program or erase cycle has been completed, the de-
5
Am29LV641G
June 14, 2005
A D V A N C E I N F O R M A T I O N
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5
Special Package Handling Instructions .................................... 7
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 10
Table 1. Device Bus Operations .....................................................10
DQ7: Data# Polling .................................................................30
Figure 6. Data# Polling Algorithm .................................................. 30
DQ6: Toggle Bit I ....................................................................30
Figure 7. Toggle Bit Algorithm........................................................ 31
DQ2: Toggle Bit II ................................................................... 32
Reading Toggle Bits DQ6/DQ2 ...............................................32
DQ5: Exceeded Timing Limits ................................................ 32
DQ3: Sector Erase Timer ....................................................... 32
Table 11. Write Operation Status ................................................... 33
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 34
Figure 8. Maximum Negative Overshoot Waveform ..................... 34
Figure 9. Maximum Positive Overshoot Waveform....................... 34
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 34
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 10. ICC1 Current vs. Time (Showing
Active and Automatic Sleep Currents) ........................................... 36
Figure 11. Typical ICC1 vs. Frequency............................................ 36
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 12. Test Setup.................................................................... 37
Table 12. Test Specifications ......................................................... 37
Key to Switching Waveforms. . . . . . . . . . . . . . . . 37
Figure 13. Input Waveforms and
Measurement Levels...................................................................... 37
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 38
Read-Only Operations ...........................................................38
Figure 14. Read Operation Timings ............................................... 38
Hardware Reset (RESET#) .................................................... 39
Figure 15. Reset Timings ............................................................... 39
Erase and Program Operations ..............................................40
Figure 16. Program Operation Timings.......................................... 41
Figure 17. Accelerated Program Timing Diagram.......................... 41
Figure 18. Chip/Sector Erase Operation Timings .......................... 42
Figure 19. Data# Polling Timings
VersatileI/O™ (V ) Control ....................................................10
IO
Requirements for Reading Array Data ...................................10
Writing Commands/Command Sequences ............................11
Accelerated Program Operation ......................................................11
Autoselect Functions .......................................................................11
Standby Mode ........................................................................ 11
Automatic Sleep Mode ...........................................................11
RESET#: Hardware Reset Pin ...............................................11
Output Disable Mode .............................................................. 12
Table 2. Sector Address Table ........................................................12
Autoselect Mode ..................................................................... 16
Table 3. Autoselect Codes, (High Voltage Method) ......................16
Sector Group Protection and Unprotection ............................. 17
Table 4. Sector Group Protection/Unprotection Address Table .....17
Write Protect (WP#) ................................................................18
Temporary Sector Group Unprotect ....................................... 18
Figure 1. Temporary Sector Group Unprotect Operation................ 18
Figure 2. In-System Sector Group Protect/Unprotect Algorithms ... 19
SecSi™ (Secured Silicon) Sector Flash Memory Region .......20
Table 5. SecSi Sector Contents ......................................................20
Figure 3. SecSi Sector Protect Verify.............................................. 21
Hardware Data Protection ......................................................21
Low VCC Write Inhibit .......................................................................21
Write Pulse “Glitch” Protection ........................................................21
Logical Inhibit ..................................................................................21
Power-Up Write Inhibit ....................................................................21
Common Flash Memory Interface (CFI). . . . . . . 21
Table 6. CFI Query Identification String.......................................... 22
Table 7. System Interface String..................................................... 22
Table 8. Device Geometry Definition .............................................. 22
Table 9. Primary Vendor-Specific Extended Query ........................ 24
Command Definitions . . . . . . . . . . . . . . . . . . . . . 24
Reading Array Data ................................................................24
Reset Command .....................................................................25
Autoselect Command Sequence ............................................25
Enter SecSi Sector/Exit SecSi Sector Command Sequence ..25
Word Program Command Sequence .....................................25
Unlock Bypass Command Sequence ..............................................26
Figure 4. Program Operation .......................................................... 26
Chip Erase Command Sequence ........................................... 26
Sector Erase Command Sequence ........................................27
Erase Suspend/Erase Resume Commands ........................... 27
Figure 5. Erase Operation............................................................... 28
Command Definitions ............................................................. 29
Table 10. Command Definitions...................................................... 29
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 30
(During Embedded Algorithms)...................................................... 43
Figure 20. Toggle Bit Timings
(During Embedded Algorithms)...................................................... 44
Figure 21. DQ2 vs. DQ6................................................................. 44
Temporary Sector Unprotect .................................................. 45
Figure 22. Temporary Sector Group Unprotect Timing Diagram ... 45
Figure 23. Sector Group Protect and Unprotect Timing Diagram .. 46
Alternate CE# Controlled Erase and Program Operations ..... 47
Figure 24. Alternate CE# Controlled Write
(Erase/Program) Operation Timings .............................................. 48
Erase And Programming Performance . . . . . . . 49
Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 49
TSOP & FBGA Pin Capacitance. . . . . . . . . . . . . . 49
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
FBE063—63-Ball Fine-Pitch Ball Grid Array
(FBGA) 11 x 12 mm package .................................................50
LAA064–64-Ball Fortified Ball Grid Array (Fortified BGA) 13 x 11
mm package ...........................................................................51
TS 048—48-Pin Standard TSOP ............................................52
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 53
June 14, 2005
Am29LV641G
6
A D V A N C E I N F O R M A T I O N
PRODUCT SELECTOR GUIDE
Part Number
Am29LV641G
Regulated Voltage Range VCC = 3.0–3.6 V
Standard Voltage Range VCC = 2.7–3.6 V
55R
Speed Option
70
70
70
35
Max Access Time (ns)
CE# Access Time (ns)
OE# Access Time (ns)
55
55
35
Note: See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
DQ15–DQ0
VCC
VSS
Sector Switches
VIO
Erase Voltage
Generator
Input/Output
Buffers
RESET#
WE#
State
WP#
Control
ACC
Command
Register
RY/BY#
PGM Voltage
Generator
Data
Latch
Chip Enable
Output Enable
Logic
STB
CE#
OE#
Y-Decoder
X-Decoder
Y-Gating
STB
VCC Detector
Timer
Cell Matrix
A21–A0
7
Am29LV641G
June 14, 2005
A D V A N C E I N F O R M A T I O N
CONNECTION DIAGRAMS
A15
A14
A13
A12
A11
A10
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
VIO
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
A8
48-Pin Standard TSOP
A21
A20
WE#
RESET#
ACC
WP#
A19
A18
A17
A7
A6
A5
A4
A3
A2
A1
OE#
VSS
CE#
A0
A15
A14
A13
A12
A11
A10
A9
A16
VIO
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
48-Pin Reverse TSOP
A8
A21
A20
WE#
RESET#
ACC
WP#
A19
A18
A17
A7
A6
A5
A4
A3
A2
A1
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
OE#
VSS
CE#
A0
June 14, 2005
Am29LV641G
8
A D V A N C E I N F O R M A T I O N
CONNECTION DIAGRAMS
63-Ball FBGA
Top View, Balls Facing Down
L8
M8
A8
B8
NC
NC
NC*
NC*
A7
B7
C7
D7
E7
F7
G7
H7
J7
K7
L7
M7
VSS
NC
NC
NC*
NC*
A13
A12
A14
A15
A16
VIO
DQ15
C6
A9
D6
A8
E6
F6
G6
H6
J6
K6
A10
A11
DQ7
DQ14
DQ13
DQ6
C5
D5
E5
F5
G5
H5
J5
K5
VCC
WE# RESET#
A21
A19
DQ5
DQ12
DQ4
C4
D4
E4
F4
G4
H4
J4
K4
RY/BY#
ACC
A18
A20
DQ2
DQ10
DQ11
DQ3
C3
A7
D3
E3
A6
F3
A5
G3
H3
J3
K3
A17
DQ0
DQ8
DQ9
DQ1
C2
A3
D2
A4
E2
A2
F2
A1
G2
A0
H2
J2
K2
L2
M2
A2
VSS
CE#
OE#
NC*
NC*
NC*
A1
B1
L1
M1
* Balls are shorted together via the substrate but not connected to the die.
NC*
NC*
NC*
NC*
9
Am29LV641G
June 14, 2005
A D V A N C E I N F O R M A T I O N
CONNECTION DIAGRAMS
64-Ball Fortified BGA
Top View, Balls Facing Down
A8
B8
C8
D8
E8
F8
G8
H8
RFU
RFU
RFU
VIO
VSS
RFU
RFU
RFU
A7
B7
C7
D7
E7
F7
G7
H7
A13
A12
A14
A15
A16
BYTE#
DQ15
VSS
A6
A9
B6
A8
C6
D6
E6
F6
G6
H6
DQ6
A10
A11
DQ7
DQ14
DQ13
A5
B5
C5
D5
E5
F5
G5
H5
WE# RESET#
A21
A19
DQ5
DQ12
VCC
DQ4
A4 B4
C4
D4
E4
F4
G4
H4
RY/BY# WP#/ACC A18
A20
DQ2
DQ10
DQ11
DQ3
A3
A7
B3
C3
A6
D3
A5
E3
F3
G3
H3
A17
DQ0
DQ8
DQ9
DQ1
A2
A3
B2
A4
C2
A2
D2
A1
E2
A0
F2
G2
H2
CE#
OE#
VSS
A1
B1
C1
D1
E1
F1
G1
H1
RFU
RFU
RFU
RFU
RFU
VIO
RFU
RFU
Special Package Handling Instructions
and/or data integrity may be compromised if the package
body is exposed to temperatures above 150°C for pro-
longed periods of time.
Special handling is required for Flash Memory products
in molded packages (TSOP and BGA) The package
June 14, 2005
Am29LV641G
10
A D V A N C E I N F O R M A T I O N
PIN DESCRIPTION
LOGIC SYMBOL
A21–A0
= 22 Addresses inputs
22
DQ15–DQ0 = 16 Data inputs/outputs
A21–A0
16
CE#
= Chip Enable input
DQ15–DQ0
CE#
OE#
WE#
WP#
ACC
OE#
= Output Enable input
= Write Enable input
WE#
WP#
= Hardware Write Protect input
= Acceleration Input
ACC
RY/BY#
RESET#
VCC
= Ready/Busy output
= Hardware Reset Pin input
RY/BY#
RESET#
VIO
= 3.0 volt-only single power supply
(see Product Selector Guide for
speed options and voltage
supply tolerances)
VIO
VSS
NC
= Output Buffer power
= Device Ground
= Pin Not Connected Internally
Note:WP#/ACC functionality is multiplexed for
Am29LV641GH/L devices. RY/BY# available only for
Am29LV640GU devices.
11
Am29LV641G
June 14, 2005
A D V A N C E I N F O R M A T I O N
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the following:
Am29LV641G
H
55R
WH
I
TEMPERATURE RANGE
Industrial (–40°C to +85°C)
I
=
PACKAGE TYPE
E
=
=
=
48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048)
48-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR048)
F
WH
63-Ball Fine-Pitch Ball Grid Array (FBGA)
0.80 mm pitch, 11 x 12 mm package (FBE063)
PC
=
64-Ball Fine-Pitch Ball Grid Array (Fortified BGA)
1.0 mm pitch, 13 x 11 mm package (LAA064)
SPEED OPTION
See Product Selector Guide and Valid Combinations
SECTOR ARCHITECTURE AND SECTOR WRITE PROTECTION (WP# = 0)
H
L
=
=
Uniform sector device, highest address sector protected
Uniform sector device, lowest address sector protected
DEVICE NUMBER/DESCRIPTION
Am29LV641G
64 Megabit (4 M x 16-Bit) CMOS Uniform Sector Flash Memory with VersatileIO™ Control
3.0 Volt-only Read, Program, and Erase
Valid Combinations for
TSOP and SSOP Packages
Valid Combinations for FBGA Packages
Package
Speed/
IO Range
Speed/VIO Range
V
Am29LV641GH73,
70 ns
Order Number
Marking
Am29LV641GL73
VIO = 2.7 V – 3.6 V
55ns
VIO = 3.0V –
3.6 V
EI, FI
Am29LV641GH53R,
Am29LV641GL53R
55 ns
Am29LV640GU53R
L640GU53R
V
IO = 3.0 V – 3.6 V
WHI
PCI
70 ns
IO = 2.7 V –
3.6 V
Marking Converstion
Am29LV640GU73
Am29LV640GU53R
Am29LV640GU73
L640GU73V
L640GU53N
L640GU73P
V
V
For the Am29LV641GH/L/AmLV640GU Enhanced-VIO device,
the last digit of the speed indicator specifies VIO range. Speed
grades ending in 3 (e.g. 93, 103, etc.) indicate a 3 Volt VIO
range; speed grades ending in 8 (e.g. 98, 108, etc.) indicate a
1.8 V VIO range.
I
55 ns
IO = 3.0 V –
3.6 V
70 ns
VIO = 2.7 V –
3.6 V
Valid Combinations
Valid Combinations list configurations planned to be sup-
ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
June 14, 2005
Am29LV641G
12
A D V A N C E I N F O R M A T I O N
DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the in-
puts and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Table 1. Device Bus Operations
Addresses
(Note 2)
DQ15–
DQ0
Operation
CE#
OE# WE# RESET#
ACC
X
Read
L
L
L
L
H
H
H
L
L
H
H
H
AIN
AIN
AIN
DOUT
Write (Program/Erase)
Accelerated Program
X
(Note 4)
(Note 4)
VHH
VCC
0.3 V
VCC
0.3 V
Standby
X
X
H
X
High-Z
Output Disable
Reset
L
H
X
H
X
H
L
X
X
X
X
High-Z
High-Z
X
SA, A6 = L,
A1 = H, A0 = L
Sector Group Protect (Note 2)
L
L
X
H
H
X
L
L
X
VID
VID
VID
X
X
X
(Note 4)
(Note 4)
(Note 4)
Sector Group Unprotect
(Note 2)
SA, A6 = H,
A1 = H, A0 = L
Temporary Sector Group
Unprotect
AIN
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 8.5–12.5 V, VHH = 11.5–12.5 V, X = Don’t Care, SA = Sector Address,
AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Addresses are A21:A0. Sector addresses are A21:A15.
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Group
Protection and Unprotection” section.
3. All sectors are unprotected when shipped from the factory (The SecSi Sector may be factory protected depending on version
ordered.)
4. DIN or DOUT as required by command sequence, data polling, or sector protect algorithm (see Figure 2).
VersatileI/O™ (VIO) Control
Requirements for Reading Array Data
The VersatileI/O (VIO) control allows the host system
to set the voltage levels that the device generates at
its data outputs and the voltages tolerated at its data
inputs to the same voltage level that is asserted on the
VIO pin. This allows the device to operate in 1.8 V or 3
V system environment as required.
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at VIH.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
data on the device data outputs. The device remains
For example, a VI/O of 1.65–1.95 volts allows for I/O at
the 3 volt level, driving and receiving signals to and
from other 3 V devices on the same bus.
13
Am29LV641G
June 14, 2005
A D V A N C E I N F O R M A T I O N
enabled for read access until the command register
contents are altered.
Standby Mode
When the system is not reading or writing to the de-
vice, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.
See “Requirements for Reading Array Data” for more
information. Refer to the AC Read-Only Operations
table for timing specifications and to Figure 14 for the
timing diagram. ICC1 in the DC Characteristics table
represents the active current specification for reading
array data.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at VCC ± 0.3 V.
(Note that this is a more restricted voltage range than
VIH.) If CE# and RESET# are held at VIH, but not within
VCC ± 0.3 V, the device will be in the standby mode,
but the standby current will be greater. The device re-
quires standard access time (tCE) for read access
when the device is in either of these standby modes,
before it is ready to read data.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
The device features an Unlock Bypass mode to facil-
itate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are re-
quired to program a word, instead of four. The “Word
Program Command Sequence” section has details on
programming data to the device using both standard
and Unlock Bypass command sequences.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
ICC3 in the DC Characteristics table represents the
standby current specification.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Table 2 indicates the address
space that each sector occupies.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device en-
ergy consumption. The device automatically enables
ICC2 in the DC Characteristics table represents the ac-
tive current specification for the write mode. The AC
Characteristics section contains timing specification
tables and timing diagrams for write operations.
this mode when addresses remain stable for tACC +
30 ns. The automatic sleep mode is independent of
the CE#, WE#, and OE# control signals. Standard ad-
dress access timings provide new data when ad-
dresses are changed. While in sleep mode, output
data is latched and always available to the system.
ICC4 in the DC Characteristics table represents the
automatic sleep mode current specification.
Accelerated Program Operation
The device offers accelerated program operations
through the ACC function. This function is primarily in-
tended to allow faster manufacturing throughput dur-
ing system production.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the RE-
SET# pin is driven low for at least a period of tRP, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
If the system asserts VHH on this pin, the device auto-
matically enters the aforementioned Unlock Bypass
mode, temporarily unprotects any protected sectors,
and uses the higher voltage on the pin to reduce the
time required for program operations. The system
would use a two-cycle program command sequence
as required by the Unlock Bypass mode. Removing
VHH from the ACC pin returns the device to normal op-
eration. Note that the ACC pin must not be at VHH for
operations other than accelerated programming, or
device damage may result.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VSS±0.3 V, the device
draws CMOS standby current (ICC4). If RESET# is held
at VIL but not within VSS±0.3 V, the standby current will
be greater.
Autoselect Functions
If the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in
this mode. Refer to the Autoselect Mode and Autose-
lect Command Sequence sections for more informa-
tion.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
June 14, 2005
Am29LV641G
14
A D V A N C E I N F O R M A T I O N
Refer to the AC Characteristics tables for RESET# pa-
rameters and to Figure 15 for the timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high
impedance state.
Table 2. Sector Address Table
8-bit Address Range
16-bit Address Range
(in hexadecimal)
Sector
SA0
A21
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A20
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A19
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A18
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
A17
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
A16
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
A15
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
(in hexadecimal)
000000–00FFFF
010000–01FFFF
020000–02FFFF
030000–03FFFF
040000–04FFFF
050000–05FFFF
060000–06FFFF
070000–07FFFF
080000–08FFFF
090000–09FFFF
0A0000–0AFFFF
0B0000–0BFFFF
0C0000–0CFFFF
0D0000–0DFFFF
0E0000–0EFFFF
0F0000–0FFFFF
100000–10FFFF
110000–11FFFF
120000–12FFFF
130000–13FFFF
140000–14FFFF
150000–15FFFF
160000–16FFFF
170000–17FFFF
180000–18FFFF
190000–19FFFF
1A0000–1AFFFF
1B0000–1BFFFF
1C0000–1CFFFF
1D0000–1DFFFF
1E0000–1EFFFF
000000–007FFF
008000–00FFFF
010000–017FFF
018000–01FFFF
020000–027FFF
028000–02FFFF
030000–037FFF
038000–03FFFF
040000–047FFF
048000–04FFFF
050000–057FFF
058000–05FFFF
060000–067FFF
068000–06FFFF
070000–077FFF
078000–07FFFF
080000–087FFF
088000–08FFFF
090000–097FFF
098000–09FFFF
0A0000–0A7FFF
0A8000–0AFFFF
0B0000–0B7FFF
0B8000–0BFFFF
0C0000–0C7FFF
0C8000–0CFFFF
0D0000–0D7FFF
0D8000–0DFFFF
0E0000–0E7FFF
0E8000–0EFFFF
0F0000–0F7FFF
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
15
Am29LV641G
June 14, 2005
A D V A N C E I N F O R M A T I O N
Table 2. Sector Address Table (Continued)
8-bit Address Range
16-bit Address Range
(in hexadecimal)
Sector
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
A21
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
A20
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
A19
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
A18
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
A17
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
A16
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
A15
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
(in hexadecimal)
1F0000–1FFFFF
200000–20FFFF
210000–21FFFF
220000–22FFFF
230000–23FFFF
240000–24FFFF
250000–25FFFF
260000–26FFFF
270000–27FFFF
280000–28FFFF
290000–29FFFF
2A0000–2AFFFF
2B0000–2BFFFF
2C0000–2CFFFF
2D0000–2DFFFF
2E0000–2EFFFF
2F0000–2FFFFF
300000–30FFFF
310000–31FFFF
320000–32FFFF
330000–33FFFF
340000–34FFFF
350000–35FFFF
360000–36FFFF
370000–37FFFF
380000–38FFFF
390000–39FFFF
3A0000–3AFFFF
3B0000–3BFFFF
3C0000–3CFFFF
3D0000–3DFFFF
3E0000–3EFFFF
3F0000–3FFFFF
400000–40FFFF
410000–41FFFF
0F8000–0FFFFF
100000–107FFF
108000–10FFFF
110000–117FFF
118000–11FFFF
120000–127FFF
128000–12FFFF
130000–137FFF
138000–13FFFF
140000–147FFF
148000–14FFFF
150000–157FFF
158000–15FFFF
160000–167FFF
168000–16FFFF
170000–177FFF
178000–17FFFF
180000–187FFF
188000–18FFFF
190000–197FFF
198000–19FFFF
1A0000–1A7FFF
1A8000–1AFFFF
1B0000–1B7FFF
1B8000–1BFFFF
1C0000–1C7FFF
1C8000–1CFFFF
1D0000–1D7FFF
1D8000–1DFFFF
1E0000–1E7FFF
1E8000–1EFFFF
1F0000–1F7FFF
1F8000–1FFFFF
200000–207FFF
208000–20FFFF
June 14, 2005
Am29LV641G
16
A D V A N C E I N F O R M A T I O N
Table 2. Sector Address Table (Continued)
8-bit Address Range
16-bit Address Range
(in hexadecimal)
Sector
SA66
SA67
SA68
SA69
SA70
SA71
SA72
SA73
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
SA85
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
SA95
SA96
SA97
SA98
SA99
SA100
A21
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A20
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
A19
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
A18
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
A17
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
A16
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
A15
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
(in hexadecimal)
420000–42FFFF
430000–43FFFF
440000–44FFFF
450000–45FFFF
460000–46FFFF
470000–47FFFF
480000–48FFFF
490000–49FFFF
4A0000–4AFFFF
4B0000–4BFFFF
4C0000–4CFFFF
4D0000–4DFFFF
4E0000–4EFFFF
4F0000–4FFFFF
500000–50FFFF
510000–51FFFF
520000–52FFFF
530000–53FFFF
540000–54FFFF
550000–55FFFF
560000–56FFFF
570000–57FFFF
580000–58FFFF
590000–59FFFF
5A0000–5AFFFF
5B0000–5BFFFF
5C0000–5CFFFF
5D0000–5DFFFF
5E0000–5EFFFF
5F0000–5FFFFF
600000–60FFFF
610000–61FFFF
620000–62FFFF
630000–63FFFF
640000–64FFFF
210000–217FFF
218000–21FFFF
220000–227FFF
228000–22FFFF
230000–237FFF
238000–23FFFF
240000–247FFF
248000–24FFFF
250000–257FFF
258000–25FFFF
260000–267FFF
268000–26FFFF
270000–277FFF
278000–27FFFF
280000–287FFF
288000–28FFFF
290000–297FFF
298000–29FFFF
2A0000–2A7FFF
2A8000–2AFFFF
2B0000–2B7FFF
2B8000–2BFFFF
2C0000–2C7FFF
2C8000–2CFFFF
2D0000–2D7FFF
2D8000–2DFFFF
2E0000–2E7FFF
2E8000–2EFFFF
2F0000–2F7FFF
2F8000–2FFFFF
300000–307FFF
308000–30FFFF
310000–317FFF
318000–31FFFF
320000–327FFF
17
Am29LV641G
June 14, 2005
A D V A N C E I N F O R M A T I O N
Table 2. Sector Address Table (Continued)
8-bit Address Range
16-bit Address Range
(in hexadecimal)
Sector
SA101
SA102
SA103
SA104
SA105
SA106
SA107
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
A21
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A20
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A19
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A18
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A17
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A16
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A15
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
(in hexadecimal)
650000–65FFFF
660000–66FFFF
670000–67FFFF
680000–68FFFF
690000–69FFFF
6A0000–6AFFFF
6B0000–6BFFFF
6C0000–6CFFFF
6D0000–6DFFFF
6E0000–6EFFFF
6F0000–6FFFFF
700000–70FFFF
710000–71FFFF
720000–72FFFF
730000–73FFFF
740000–74FFFF
750000–75FFFF
760000–76FFFF
770000–77FFFF
780000–78FFFF
790000–79FFFF
7A0000–7AFFFF
7B0000–7BFFFF
7C0000–7CFFFF
7D0000–7DFFFF
7E0000–7EFFFF
7F0000–7FFFFF
328000–32FFFF
330000–337FFF
338000–33FFFF
340000–347FFF
348000–34FFFF
350000–357FFF
358000–35FFFF
360000–367FFF
368000–36FFFF
370000–377FFF
378000–37FFFF
380000–387FFF
388000–38FFFF
390000–397FFF
398000–39FFFF
3A0000–3A7FFF
3A8000–3AFFFF
3B0000–3B7FFF
3B8000–3BFFFF
3C0000–3C7FFF
3C8000–3CFFFF
3D0000–3D7FFF
3D8000–3DFFFF
3E0000–3E7FFF
3E8000–3EFFFF
3F0000–3F7FFF
3F8000–3FFFFF
Note: All sectors are 32 Kwords in size.
June 14, 2005
Am29LV641G
18
A D V A N C E I N F O R M A T I O N
Table 3. In addition, when verifying sector protection,
Autoselect Mode
the sector address must appear on the appropriate
highest order address bits (see Table 2). Table 3
shows the remaining address bits that are don’t care.
When all necessary bits have been set as required,
the programming equipment may then read the corre-
sponding identifier code on DQ7–DQ0.
The autoselect mode provides manufacturer and de-
vice identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equip-
ment to automatically match a device to be pro-
grammed with its corresponding programming
algorithm. However, the autoselect codes can also be
accessed in-system through the command register.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 10. This method
does not require VID. Refer to the Autoselect Com-
mand Sequence section for more information.
When using programming equipment, the autoselect
mode requires VID (8.5 V to 12.5 V) on address pin A9.
Address pins A6, A1, and A0 must be as shown in
Table 3. Autoselect Codes, (High Voltage Method)
A21
to
A14
to
A8
to
A7
to
A5
to
DQ15
to
Description
CE# OE# WE#
A15
A10
A9
A7
A0
A6
A2
A1
A0
DQ0
Manufacturer ID:
AMD
VID
L
L
H
X
X
X
—
L
X
L
L
XX01h
VID
VID
Read Cycle 1
Read Cycle 2
L
L
L
L
H
H
X
X
X
X
X
—
L
L
X
L
L
H
H
22D7h
220Fh
0Eh
VID
Read Cycle 3
L
L
H
X
X
0Fh
L
L
H
XX00h
Sector Protection
Verification
01h (protected),
00h (unprotected)
VID
VID
L
L
L
L
H
H
SA
X
X
X
X
X
—
—
L
L
X
X
H
H
L
SecSi™ Sector
Indicator Bit (DQ7)
98h (factory locked),
18h (not factory locked)
H
SecSi™ Sector
XX98h (factory locked),
XX18h (not factory
locked)
Indicator Bit (DQ7),
WP# protects highest
address sector
L
L
L
L
H
H
X
X
X
X
VID
X
X
—
—
L
L
X
X
H
H
H
H
SecSi™ Sector
XX88h (factory locked),
XX08h (not factory
locked)
Indicator Bit (DQ7),
WP# protects lowest
address sector
VID
Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Note: SecSi™ Sector Indicator Bit (DQ7) exist only in the Am29LV641GH/L devices.
19
Am29LV641G
June 14, 2005
A D V A N C E I N F O R M A T I O N
Table 4. Sector Group Protection/Unprotection
Address Table
Sector Group Protection and
Unprotection
Sector Group
A21–A17
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
The hardware sector group protection feature disables
both program and erase operations in any sector
group. In this device, a sector group consists of four
adjacent sectors that are protected or unprotected at
the same time (see Table 4). The hardware sector
group unprotection feature re-enables both program
and erase operations in previously protected sector
groups. Sector group protection/unprotection can be
implemented via two methods.
SA0–SA3
SA4–SA7
SA8–SA11
SA12–SA15
SA16–SA19
SA20–SA23
SA24–SA27
SA28–SA31
SA32–SA35
SA36–SA39
SA40–SA43
SA44–SA47
SA48–SA51
SA52–SA55
SA56–SA59
SA60–SA63
SA64–SA67
SA68–SA71
SA72–SA75
SA76–SA79
SA80–SA83
SA84–SA87
SA88–SA91
SA92–SA95
SA96–SA99
SA100–SA103
SA104–SA107
SA108–SA111
SA112–SA115
SA116–SA119
SA120–SA123
SA124–SA127
The primary method requires VID on the RESET# pin
only, and can be implemented either in-system or via
programming equipment. Figure 2 shows the algo-
rithms and Figure 23 shows the timing diagram. This
method uses standard microprocessor bus cycle tim-
ing. For sector group unprotect, all unprotected sector
groups must first be protected prior to the first sector
group unprotect write cycle.
The alternate method intended only for programming
equipment requires VID on address pin A9 and OE#.
This method is compatible with programmer routines
written for earlier 3.0 volt-only AMD flash devices.
Publication number 22367 contains further details;
contact an AMD representative to request a copy.
The device is shipped with all sector groups unpro-
tected. AMD offers the option of programming and
protecting sector groups at its factory prior to shipping
the device through AMD’s ExpressFlash™ Service.
Contact an AMD representative for details.
It is possible to determine whether a sector group is
protected or unprotected. See the Autoselect Mode
section for details.
Note: All sector groups are 128 Kwords in size.
June 14, 2005
Am29LV641G
20
A D V A N C E I N F O R M A T I O N
Write Protect (WP#)
The Write Protect function provides a hardware
method of protecting the first or last sector without
using VID.
START
If the system asserts VIL on the WP# pin, the device
disables program and erase functions in the first or
last sector independently of whether those sectors
were protected or unprotected using the method de-
scribed in “Sector Group Protection and Unprotection”.
Note that if WP# is at VIL when the device is in the
standby mode, the maximum input load current is in-
creased. See the table in “DC Characteristics”.
RESET# = VID
(Note 1)
Perform Erase or
Program Operations
RESET# = VIH
If the system asserts VIH on the WP# pin, the device
reverts to whether the first or last sector was previ-
ously set to be protected or unprotected using the
method described in “Sector Group Protection and
Unprotection”.
Temporary Sector
Group Unprotect
Completed (Note 2)
Temporary Sector Group Unprotect
(Note: In this device, a sector group consists of four adjacent
sectors that are protected or unprotected at the same time
(see Table 4)).
Notes:
1. All protected sector groups unprotected (If WP# = VIL,
the first or last sector will remain protected).
This feature allows temporary unprotection of previ-
ously protected sector groups to change data in-sys-
tem. The Sector Group Unprotect mode is activated by
setting the RESET# pin to VID (8.5 V – 12.5 V). During
this mode, formerly protected sector groups can be
programmed or erased by selecting the sector group
addresses. Once VID is removed from the RESET#
pin, all the previously protected sector groups are
protected again. Figure 1 shows the algorithm, and
Figure 22 shows the timing diagrams, for this feature.
2. All previously protected sector groups are protected
once again.
Figure 1. Temporary Sector Group
Unprotect Operation
21
Am29LV641G
June 14, 2005
A D V A N C E I N F O R M A T I O N
START
START
PLSCNT = 1
PLSCNT = 1
Protect all sector
groups: The indicated
portion of the sector
group protect algorithm
must be performed for all
unprotected sector
groups prior to issuing
the first sector group
unprotect address
RESET# = VID
RESET# = VID
Wait 1 μs
Wait 1 μs
Temporary Sector
Group Unprotect
Mode
Temporary Sector
Group Unprotect
Mode
No
First Write
Cycle = 60h?
No
First Write
Cycle = 60h?
Yes
Yes
Set up sector
group address
All sector
groups
No
protected?
Sector Group Protect:
Write 60h to sector
group address with
A6 = 0, A1 = 1,
A0 = 0
Yes
Set up first sector
group address
Sector Group
Unprotect:
Wait 150 µs
Write 60h to sector
group address with
A6 = 1, A1 = 1,
A0 = 0
Verify Sector Group
Protect: Write 40h
to sector group
address twith A6 = 0,
A1 = 1, A0 = 0
Reset
PLSCNT = 1
Increment
PLSCNT
Wait 15 ms
Verify Sector Group
Unprotect: Write
40h to sector group
address with
A6 = 1, A1 = 1,
A0 = 0
Read from
sector group address
with A6 = 0,
A1 = 1, A0 = 0
Increment
PLSCNT
No
No
PLSCNT
= 25?
Read from
sector group
address with A6 = 1,
A1 = 1, A0 = 0
Data = 01h?
Yes
No
Yes
Set up
next sector group
address
Protect
another
sector group?
Yes
No
PLSCNT
= 1000?
Data = 00h?
Yes
Device failed
No
Yes
Remove VID
from RESET#
Last sector
group
verified?
No
Device failed
Write reset
command
Yes
Remove VID
from RESET#
Sector Group
Unprotect
Sector Group
Protect
Sector Group
Protect complete
Write reset
command
Algorithm
Algorithm
Sector Group
Unprotect complete
Figure 2. In-System Sector Group Protect/Unprotect Algorithms
Am29LV641G
June 14, 2005
22
A D V A N C E I N F O R M A T I O N
or following a hardware reset, the device reverts to
sending commands to sector SA0.
SecSi™ (Secured Silicon) Sector Flash
Memory Region
The SecSi (Secured Silicon) Sector feature provides a
Flash memory region that enables permanent part
identification through an Electronic Serial Number
(ESN). The SecSi Sector is 128 words in length, and
uses a SecSi Sector Indicator Bit (DQ7) to indicate
whether or not the SecSi Sector is locked when
shipped from the factory. This bit is permanently set at
the factory and cannot be changed, which prevents
cloning of a factory locked part. This ensures the secu-
rity of the ESN once the product is shipped to the field.
Factory Locked: SecSi Sector Programmed and
Protected At the Factory
In devices with an ESN, the SecSi Sector is protected
when the device is shipped from the factory. The SecSi
Sector cannot be modified in any way. A factory locked
device has an 8-word random ESN at addresses
000000h–000007h.
Customers may opt to have their code programmed by
AMD through the AMD ExpressFlash service. The de-
vices are then shipped from AMD’s factory with the
SecSi Sector permanently locked. Contact an AMD
representative for details on using AMD’s Express-
Flash service.
AMD offers the device with the SecSi Sector either
factory locked or customer lockable. The fac-
tory-locked version is always protected when shipped
from the factory, and has the SecSi (Secured Silicon)
Sector Indicator Bit permanently set to a “1.” The cus-
tomer-lockable version is shipped with the SecSi Sec-
tor unprotected, allowing customers to utilize that
sector in any manner they choose. The customer-lock-
able version also has the SecSi Sector Indicator Bit
permanently set to a “0.” Thus, the SecSi Sector Indi-
cator Bit prevents customer-lockable devices from
being used to replace devices that are factory locked.
Customer Lockable: SecSi Sector NOT
Programmed or Protected At the Factory
As an alternative to the factory-locked version, the de-
vice may be ordered such that the customer may pro-
gram and protect the 128-word SecSi sector.
Programming and protecting the SecSi Sector must be
used with caution since, once protected, there is no
procedure available for unprotecting the SecSi Sector
area and none of the bits in the SecSi Sector memory
space can be modified in any way.
The SecSi sector address space in this device is allo-
cated as follows:
Table 5. SecSi Sector Contents
The SecSi Sector area can be protected using one of
the following procedures:
SecSi Sector
Standard
ExpressFlash
Customer
Lockable
Address Range
Factory Locked Factory Locked
ESN or
determined by
customer
■ Write the three-cycle Enter SecSi Sector Region
command sequence, and then follow the in-system
sector protect algorithm as shown in Figure 2, ex-
cept that RESET# may be at either VIH or VID. This
allows in-system protection of the SecSi Sector
without raising any device pin to a high voltage.
Note that this method is only applicable to the SecSi
Sector.
000000h–000007h
000008h–00007Fh
ESN
Determined by
customer
Determined by
customer
Unavailable
*All Uniform Devices (not including Uniform High) such as Am29LV640GU
has its Sector starting at address 0.
The system accesses the SecSi Sector through a
command sequence (see “Enter SecSi Sector/Exit
SecSi Sector Command Sequence”). After the system
has written the Enter SecSi Sector command se-
quence, it may read the SecSi Sector by using the ad-
dresses normally occupied by the first sector (SA0).
This mode of operation continues until the system is-
sues the Exit SecSi Sector command sequence, or
until power is removed from the device. On power-up,
■ Write the three-cycle Enter SecSi Sector Region
command sequence, and then use the alternate
method of sector protection described in the “Sector
Group Protection and Unprotection” section.
Once the SecSi Sector is programmed, locked and
verified, the system must write the Exit SecSi Sector
Region command sequence to return to reading and
writing within the remainder of the array.
23
Am29LV641G
June 14, 2005
A D V A N C E I N F O R M A T I O N
data protection measures prevent accidental erasure
or programming, which might otherwise be caused by
spurious system level signals during VCC power-up
and power-down transitions, or from system noise.
START
If data = 00h,
SecSi Sector is
unprotected.
If data = 01h,
SecSi Sector is
protected.
Low VCC Write Inhibit
RESET# =
VIH or VID
When VCC is less than VLKO, the device does not ac-
cept any write cycles. This protects data during VCC
power-up and power-down. The command register
and all internal program/erase circuits are disabled,
and the device resets to the read mode. Subsequent
writes are ignored until VCC is greater than VLKO. The
system must provide the proper signals to the control
pins to prevent unintentional writes when VCC is
Wait 1 μs
Write 60h to
any address
Remove VIH or VID
from RESET#
Write 40h to SecSi
Sector address
with A6 = 0,
greater than VLKO
.
Write reset
command
A1 = 1, A0 = 0
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE#
or WE# do not initiate a write cycle.
SecSi Sector
Protect Verify
complete
Read from SecSi
Sector address
with A6 = 0,
Logical Inhibit
A1 = 1, A0 = 0
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Figure 3. SecSi Sector Protect Verify
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up,
the device does not accept commands on the rising
edge of WE#. The internal state machine is automati-
cally reset to the read mode on power-up.
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 10 for com-
mand definitions). In addition, the following hardware
COMMON FLASH MEMORY INTERFACE (CFI)
The Common Flash Interface (CFI) specification out-
lines device and host system software interrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire families of
devices. Software support can then be device-inde-
pendent, JEDEC ID-independent, and forward- and
backward-compatible for the specified flash device
families. Flash vendors can standardize their existing
interfaces for long-term compatibility.
CFI data at the addresses given in Tables 6–9. The
system must write the reset command to return the
device to reading array data.
For further information, please refer to the CFI Specifi-
cation and CFI Publication 100, available via the
World Wide Web at http://www.amd.com/flash/cfi. Al-
ternatively, contact an AMD representative for copies
of these documents.
This device enters the CFI Query mode when the sys-
tem writes the CFI Query command, 98h, to address
55h, any time the device is ready to read array data.
The system can read CFI information at the addresses
given in Tables 6–9. To terminate reading CFI data,
the system must write the reset command.
The system can also write the CFI query command
when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read
June 14, 2005
Am29LV641G
24
A D V A N C E I N F O R M A T I O N
Table 6. CFI Query Identification String
Description
Addresses (x16)
Data
10h
11h
12h
0051h
0052h
0059h
Query Unique ASCII string “QRY”
13h
14h
0002h
0000h
Primary OEM Command Set
15h
16h
0040h
0000h
Address for Primary Extended Table
17h
18h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
Address for Alternate OEM Extended Table (00h = none exists)
19h
1Ah
0000h
0000h
Table 7. System Interface String
Description
Addresses (x16)
Data
VCC Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Bh
0027h
VCC Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Ch
0036h
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
0000h
0000h
0003h
0000h
000Ah
0000h
0005h
0000h
0002h
0000h
VPP Min. voltage (00h = no VPP pin present)
VPP Max. voltage (00h = no VPP pin present)
Typical timeout per single byte/word write 2N µs
Typical timeout for Min. size buffer write 2N µs (00h = not supported)
Typical timeout per individual block erase 2N ms
Typical timeout for full chip erase 2N ms (00h = not supported)
Max. timeout for byte/word write 2N times typical
Max. timeout for buffer write 2N times typical
Max. timeout per individual block erase 2N times typical
Max. timeout for full chip erase 2N times typical (00h = not supported)
Table 8. Device Geometry Definition
Description
Addresses (x16)
Data
27h
0017h
Device Size = 2N byte
28h
29h
0001h
0000h
Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh
0000h
0000h
Max. number of byte in multi-byte write = 2N
(00h = not supported)
2Ch
0002h
Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
0007h
0000h
0020h
0000h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
25
Am29LV641G
June 14, 2005
A D V A N C E I N F O R M A T I O N
31h
32h
33h
34h
007Eh
0000h
0000h
0001h
Erase Block Region 2 Information (refer to CFI publication 100)
35h
36h
37h
38h
0000h
0000h
0000h
0000h
Erase Block Region 3 Information (refer to CFI publication 100)
Erase Block Region 4 Information (refer to CFI publication 100)
39h
3Ah
3Bh
3Ch
0000h
0000h
0000h
0000h
June 14, 2005
Am29LV641G
26
A D V A N C E I N F O R M A T I O N
Table 9. Primary Vendor-Specific Extended Query
Addresses (x16)
Data
Description
40h
41h
42h
0050h
0052h
0049h
Query-unique ASCII string “PRI”
43h
44h
0031h
0033h
Major version number, ASCII
Minor version number, ASCII
Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not Required
45h
0004h
Silicon Revision Number (Bits 5-2)
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
46h
47h
48h
49h
4Ah
4Bh
4Ch
0002h
0004h
0001h
0004h
0000h
0000h
0000h
Sector Protect
0 = Not Supported, X = Number of sectors in per group
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
Sector Protect/Unprotect scheme
04 = 29LV800 mode
Simultaneous Operation
00 = Not Supported, X = Number of Sectors in Bank
Burst Mode Type
00 = Not Supported, 01 = Supported
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
ACC (Acceleration) Supply Minimum
4Dh
00B5h
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
ACC (Acceleration) Supply Maximum
4Eh
4Fh
00C5h
00XXh
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
00h = Uniform sector device
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates device op-
erations. Table 10 defines the valid register command
sequences. Writing incorrect address and data val-
ues or writing them in the improper sequence may
place the device in an unknown state. A reset com-
mand is then required to return the device to reading
array data.
retrieve data. The device is ready to read array data
after completing an Embedded Program or Embedded
Erase algorithm.
After the device accepts an Erase Suspend command,
the device enters the erase-suspend-read mode, after
which the system can read data from any
non-erase-suspended sector. After completing a pro-
gramming operation in the Erase Suspend mode, the
system may once again read array data with the same
exception. See the Erase Suspend/Erase Resume
Commands section for more information.
All addresses are latched on the falling edge of WE#
or CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the AC Characteristics section for timing
diagrams.
The system must issue the reset command to return
the device to the read (or erase-suspend-read) mode
if DQ5 goes high during an active program or erase
operation, or if the device is in the autoselect mode.
See the next section, Reset Command, for more infor-
mation.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
27
Am29LV641G
June 14, 2005
A D V A N C E I N F O R M A T I O N
See also Requirements for Reading Array Data in the ■ A read cycle at address XX00h returns the manu-
Device Bus Operations section for more information.
The Read-Only Operations table provides the read pa-
rameters, and Figure 14 shows the timing diagram.
facturer code.
■ A read cycle at address XX01h returns the device
code.
■ A read cycle to an address containing a sector
group address (SA), and the address 02h on A7–A0
in word mode returns 01h if the sector group is pro-
tected, or 00h if it is unprotected. (Refer to Table 4
for valid sector addresses).
Reset Command
Writing the reset command resets the device to the
read or erase-suspend-read mode. Address bits are
don’t cares for this command.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to the read
mode. Once erasure begins, however, the device ig-
nores reset commands until the operation is complete.
The system must write the reset command to return to
the read mode (or erase-suspend-read mode if the de-
vice was previously in Erase Suspend).
Enter SecSi Sector/Exit SecSi Sector
Command Sequence
The reset command may be written between the
sequence cycles in a program command sequence
before programming begins. This resets the device to
the read mode. If the program command sequence is
written while the device is in the Erase Suspend mode,
writing the reset command returns the device to the
erase-suspend-read mode. Once programming be-
gins, however, the device ignores reset commands
until the operation is complete.
The SecSi Sector region provides a secured data area
containing an 8-word random Electronic Serial Num-
ber (ESN). The system can access the SecSi Sector
region by issuing the three-cycle Enter SecSi Sector
command sequence. The device continues to access
the SecSi Sector region until the system issues the
four-cycle Exit SecSi Sector command sequence. The
Exit SecSi Sector command sequence returns the de-
vice to normal operation. Table 10 shows the address
and data requirements for both command sequences.
See also “SecSi™ (Secured Silicon) Sector Flash
Memory Region” for further information.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command
must be written to return to the read mode. If the de-
vice entered the autoselect mode while in the Erase
Suspend mode, writing the reset command returns the
device to the erase-suspend-read mode.
Word Program Command Sequence
Programming is a four-bus-cycle operation. The pro-
gram command sequence is initiated by writing two
unlock write cycles, followed by the program set-up
command. The program address and data are written
next, which in turn initiate the Embedded Program al-
gorithm. The system is not required to provide further
controls or timings. The device automatically provides
internally generated program pulses and verifies the
programmed cell margin. Table 10 shows the address
and data requirements for the word program command
sequence.
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to the
read mode (or erase-suspend-read mode if the device
was in Erase Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and device codes,
and determine whether or not a sector is protected.
Table 10 shows the address and data requirements.
This method is an alternative to that shown in Table 3,
which is intended for PROM programmers and re-
quires VID on address pin A9. The autoselect com-
mand sequence may be written to an address that is
either in the read or erase-suspend-read mode. The
autoselect command may not be written while the de-
vice is actively programming or erasing.
When the Embedded Program algorithm is complete,
the device then returns to the read mode and ad-
dresses are no longer latched. The system can deter-
mine the status of the program operation by using
DQ7 or DQ6. Refer to the Write Operation Status sec-
tion for information on these status bits.
Any commands written to the device during the Em-
bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program
operation. The program command sequence should
be reinitiated once the device has returned to the read
mode, to ensure data integrity.
The autoselect command sequence is initiated by first
writing two unlock cycles. This is followed by a third
write cycle that contains the autoselect command. The
device then enters the autoselect mode. The system
may read at any address any number of times without
initiating another autoselect command sequence:
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
June 14, 2005
Am29LV641G
28
A D V A N C E I N F O R M A T I O N
from “0” back to a “1.” Attempting to do so may
cause the device to set DQ5 = 1, or cause the DQ7
and DQ6 status bits to indicate the operation was suc-
cessful. However, a succeeding read will show that the
data is still “0.” Only erase operations can convert a
“0” to a “1.”
START
Unlock Bypass Command Sequence
Write Program
Command Sequence
The unlock bypass feature allows the system to pro-
gram words to the device faster than using the stan-
dard program command sequence. The unlock
bypass command sequence is initiated by first writing
two unlock cycles. This is followed by a third write
cycle containing the unlock bypass command, 20h.
The device then enters the unlock bypass mode. A
two-cycle unlock bypass program command sequence
is all that is required to program in this mode. The first
cycle in this sequence contains the unlock bypass pro-
gram command, A0h; the second cycle contains the
program address and data. Additional data is pro-
grammed in the same manner. This mode dispenses
with the initial two unlock cycles required in the stan-
dard program command sequence, resulting in faster
total programming time. Table 10 shows the require-
ments for the command sequence.
Data Poll
from System
Embedded
Program
algorithm
in progress
Verify Data?
Yes
No
No
Increment Address
Last Address?
Yes
During the unlock bypass mode, only the Unlock By-
pass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com-
mand sequence. The first cycle must contain the data
90h. The second cycle must contain the data 00h. The
device then returns to the read mode.
Programming
Completed
Note: See Table 10 for program command sequence.
The device offers accelerated program operations
through the ACC pin. When the system asserts VHH on
the ACC pin, the device automatically enters the Un-
lock Bypass mode. The system may then write the
two-cycle Unlock Bypass program command se-
quence. The device uses the higher voltage on the
ACC pin to accelerate the operation. Note that the
ACC pin must not be at VHH for operations other than
accelerated programming, or device damage may re-
sult.
Figure 4. Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Table 10
shows the address and data requirements for the chip
erase command sequence.
Figure 4 illustrates the algorithm for the program oper-
ation. Refer to the Erase and Program Operations
table in the AC Characteristics section for parameters,
and Figure 16 for timing diagrams.
29
Am29LV641G
June 14, 2005
A D V A N C E I N F O R M A T I O N
When the Embedded Erase algorithm is complete, the
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses
are no longer latched. Note that while the Embedded
Erase operation is in progress, the system can read
data from the non-erasing sector. The system can de-
termine the status of the erase operation by reading
DQ7, DQ6, or DQ2 in the erasing sector. Refer to the
Write Operation Status section for information on
these status bits.
device returns to the read mode and addresses are no
longer latched. The system can determine the status
of the erase operation by using DQ7, DQ6 or DQ2.
Refer to the Write Operation Status section for infor-
mation on these status bits.
Any commands written during the chip erase operation
are ignored. However, note that a hardware reset im-
mediately terminates the erase operation. If that oc-
curs, the chip erase command sequence should be
reinitiated once the device has returned to reading
array data, to ensure data integrity.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other com-
mands are ignored. However, note that a hardware
reset immediately terminates the erase operation. If
that occurs, the sector erase command sequence
should be reinitiated once the device has returned to
reading array data, to ensure data integrity.
Figure 5 illustrates the algorithm for the erase opera-
tion. Refer to the Erase and Program Operations ta-
bles in the AC Characteristics section for parameters,
and Figure 18 section for timing diagrams.
Figure 5 illustrates the algorithm for the erase opera-
tion. Refer to the Erase and Program Operations ta-
bles in the AC Characteristics section for parameters,
and Figure 18 section for timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two ad-
ditional unlock cycles are written, and are then fol-
lowed by the address of the sector to be erased, and
the sector erase command. Table 10 shows the ad-
dress and data requirements for the sector erase com-
mand sequence.
Erase Suspend/Erase Resume
Commands
The Erase Suspend command, B0h, allows the sys-
tem to interrupt a sector erase operation and then read
data from, or program data to, any sector not selected
for erasure. This command is valid only during the
sector erase operation, including the 50 µs time-out
period during the sector erase command sequence.
The Erase Suspend command is ignored if written dur-
ing the chip erase operation or Embedded Program
algorithm.
The device does not require the system to preprogram
prior to erase. The Embedded Erase algorithm auto-
matically programs and verifies the entire memory for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
When the Erase Suspend command is written during
the sector erase operation, the device requires a max-
imum of 20 µs to suspend the erase operation. How-
ever, when the Erase Suspend command is written
during the sector erase time-out, the device immedi-
ately terminates the time-out period and suspends the
erase operation.
After the command sequence is written, a sector erase
time-out of 50 µs occurs. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time
between these additional cycles must be less than 50
µs, otherwise erasure may begin. Any sector erase
address and command following the exceeded
time-out may or may not be accepted. It is recom-
mended that processor interrupts be disabled during
this time to ensure all commands are accepted. The
interrupts can be re-enabled after the last Sector
Erase command is written. Any command other than
Sector Erase or Erase Suspend during the
time-out period resets the device to the read
mode. The system must rewrite the command se-
quence and any additional addresses and commands.
After the erase operation has been suspended, the
device enters the erase-suspend-read mode. The sys-
tem can read data from or program data to any sector
not selected for erasure. (The device “erase sus-
pends” all sectors selected for erasure.) Reading at
any address within erase-suspended sectors pro-
duces status information on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
Refer to the Write Operation Status section for infor-
mation on these status bits.
The system can monitor DQ3 to determine if the sec-
tor erase timer has timed out (See the section on DQ3:
Sector Erase Timer.). The time-out begins from the ris-
ing edge of the final WE# pulse in the command
sequence.
After an erase-suspended program operation is com-
plete, the device returns to the erase-suspend-read
mode. The system can determine the status of the
program operation using the DQ7 or DQ6 status bits,
just as in the standard word program operation.
June 14, 2005
Am29LV641G
30
A D V A N C E I N F O R M A T I O N
Refer to the Write Operation Status section for more
information.
In the erase-suspend-read mode, the system can also
issue the autoselect command sequence. Refer to the
Autoselect Mode and Autoselect Command Sequence
sections for details.
START
Write Erase
Command Sequence
(Notes 1, 2)
To resume the sector erase operation, the system
must write the Erase Resume command. The address
of the erase-suspended sector is required when writ-
ing this command. Further writes of the Resume com-
mand are ignored. Another Erase Suspend command
can be written after the chip has resumed erasing.
Data Poll to Erasing
Bank from System
Embedded
Erase
algorithm
in progress
No
Data = FFh?
Yes
Erasure Completed
Notes:
1. See Table 10 for erase command sequence.
2. See the section on DQ3 for information on the sector
erase timer.
Figure 5. Erase Operation
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A D V A N C E I N F O R M A T I O N
Command Definitions
Table 10. Command Definitions
Bus Cycles (Notes 2–5)
Command
Sequence
(Note 1)
First
Second
Third
Addr
Fourth
Fifth
Sixth
Addr Data Addr Data
Data
Addr
Data
Addr Data Addr Data
Read (Note 6)
Reset (Note 7)
Manufacturer ID
1
1
4
RA
XXX
555
RD
F0
AA
2AA
2AA
55
55
555
555
90
90
X00
X01
0001
22E7
(Note
X0E 220F X0F
16)
Device ID
4
4
4
555
555
555
AA
AA
AA
SecSi™ Sector Factory
Protect (Note 9)
(see
Note 9)
2AA
2AA
55
55
555
555
90
X03
Sector Group Protect Verify
(Note 10)
XX00/
XX01
90 (SA)X02
88
Enter SecSi Sector Region
Exit SecSi Sector Region
Program
3
4
4
3
555
555
555
555
AA
AA
AA
AA
2AA
2AA
2AA
2AA
55
55
55
55
555
555
555
555
90
A0
20
XXX
PA
00
PD
Unlock Bypass
Unlock Bypass Program (Note 11)
XXX
A0
PA
PD
00
55
55
2
Unlock Bypass Reset (Note 12)
Chip Erase
XXX
555
555
BA
90
AA
AA
B0
30
XXX
2AA
2AA
2
6
6
1
1
1
555
555
80
80
555
555
AA
AA
2AA
2AA
55
55
555
SA
10
30
Sector Erase
Erase Suspend (Note 13)
Erase Resume (Note 14)
CFI Query (Note 15)
BA
55
98
Legend:
X = Don’t care
PD = Data to be programmed at location PA. Data latches on the rising
edge of WE# or CE# pulse, whichever happens first.
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses
SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A21–A15 uniquely select any sector.
latch on the falling edge of the WE# or CE# pulse, whichever happens
later.
Notes:
1. See Table 1 for description of bus operations.
9. If WP# protects the highest address sector, the data is 98h for
factory locked and 18h for not factory locked. If WP# protects the
lowest address sector, the data is 88h for factory locked and 08h
for not factor locked.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the autoselect
command sequence, all bus cycles are write cycles.
10. The data is 00h for an unprotected sector group and 01h for a
protected sector group.
4. Data bits DQ15–DQ8 are don’t care in command sequences,
except for RD and PD.
11. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
5. Unless otherwise noted, address bits A21–A15 are don’t cares.
6. No unlock or command cycles required when device is in read
mode.
12. The Unlock Bypass Reset command is required to return to the
read mode when the device is in the unlock bypass mode.
7. The Reset command is required to return to the read mode (or to
the erase-suspend-read mode if previously in Erase Suspend)
when the device is in the autoselect mode, or if DQ5 goes high
(while the device is providing status information).
13. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation.
8. The fourth cycle of the autoselect command sequence is a read
cycle. Data bits DQ15–DQ8 are don’t care. See the Autoselect
Command Sequence section for more information.
14. The Erase Resume command is valid only during the Erase
Suspend mode.
15. Command is valid when device is ready to read array data or
when device is in autoselect mode.
16. Bottom boot = 2200 and top boot = 2201.
June 14, 2005
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32
A D V A N C E I N F O R M A T I O N
WRITE OPERATION STATUS
The device provides several bits to determine the status of
a program or erase operation: DQ2, DQ3, DQ5, DQ6, and
DQ7. Table 11 and the following subsections describe the
function of these bits. DQ7 and DQ6 each offer a method for
determining whether a program or erase operation is com-
plete or in progress.
in the AC Characteristics section shows the Data#
Polling timing diagram.
START
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system
whether an Embedded Program or Erase algorithm is in
progress or completed, or whether the device is in Erase
Suspend. Data# Polling is valid after the rising edge of the
final WE# pulse in the command sequence.
Read DQ7–DQ0
Addr = VA
During the Embedded Program algorithm, the device out-
puts on DQ7 the complement of the datum programmed to
DQ7. This DQ7 status also applies to programming during
Erase Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to
DQ7. The system must provide the program address to
read valid status information on DQ7. If a program address
falls within a protected sector, Data# Polling on DQ7 is ac-
tive for approximately 1 µs, then the device returns to the
read mode.
Yes
DQ7 = Data?
No
No
DQ5 = 1?
Yes
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase
algorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
The system must provide an address within any of the
sectors selected for erasure to read valid status infor-
mation on DQ7.
Read DQ7–DQ0
Addr = VA
Yes
DQ7 = Data?
After an erase command sequence is written, if all
sectors selected for erasing are protected, Data# Poll-
ing on DQ7 is active for approximately 100 µs, then
the device returns to the read mode. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se-
lected sectors that are protected. However, if the sys-
tem reads DQ7 at an address within a protected
sector, the status may not be valid.
No
PASS
FAIL
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is any sector address
within the sector being erased. During chip erase, a
valid address is any non-protected sector address.
Just prior to the completion of an Embedded Program
or Erase operation, DQ7 may change asynchronously
with DQ0–DQ6 while Output Enable (OE#) is asserted
low. That is, the device may change from providing
status information to valid data on DQ7. Depending on
when the system samples the DQ7 output, it may read
the status or valid data. Even if the device has com-
pleted the program or erase operation and DQ7 has
valid data, the data outputs on DQ0–DQ6 may be still
invalid. Valid data on DQ0–DQ7 will appear on suc-
cessive read cycles.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
Figure 6. Data# Polling Algorithm
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or com-
plete, or whether the device has entered the Erase
Suspend mode. Toggle Bit I may be read at any ad-
dress, and is valid after the rising edge of the final
WE# pulse in the command sequence (prior to the
Table 11 shows the outputs for Data# Polling on DQ7.
Figure 6 shows the Data# Polling algorithm. Figure 19
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June 14, 2005
A D V A N C E I N F O R M A T I O N
program or erase operation), and during the sector
erase time-out.
START
During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address cause
DQ6 to toggle. The system may use either OE# or
CE# to control the read cycles. When the operation is
complete, DQ6 stops toggling.
Read DQ7–DQ0
After an erase command sequence is written, if all sectors
selected for erasing are protected, DQ6 toggles for approxi-
mately 100 µs, then returns to reading array data. If not all
selected sectors are protected, the Embedded Erase algo-
rithm erases the unprotected sectors, and ignores the se-
lected sectors that are protected.
Read DQ7–DQ0
No
Toggle Bit
= Toggle?
The system can use DQ6 and DQ2 together to determine
whether a sector is actively erasing or is erase-suspended.
When the device is actively erasing (that is, the Embedded
Erase algorithm is in progress), DQ6 toggles. When the de-
vice enters the Erase Suspend mode, DQ6 stops toggling.
However, the system must also use DQ2 to determine
which sectors are erasing or erase-suspended. Alterna-
tively, the system can use DQ7 (see the subsection on
DQ7: Data# Polling).
Yes
No
DQ5 = 1?
Yes
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 μs after the program
command sequence is written, then returns to reading
array data.
Read DQ7–DQ0
Twice
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
Toggle Bit
= Toggle?
No
Table 11 shows the outputs for Toggle Bit I on DQ6.
Figure 7 shows the toggle bit algorithm. Figure 20 in
the “AC Characteristics” section shows the toggle bit
timing diagrams. Figure 21 shows the differences be-
tween DQ2 and DQ6 in graphical form. See also the
subsection on DQ2: Toggle Bit II.
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Figure 7. Toggle Bit Algorithm
Note: The system should recheck the toggle bit even if DQ5
= “1” because the toggle bit may stop toggling as DQ5
changes to “1.” See the subsections on DQ6 and DQ2 for
more information.
June 14, 2005
Am29LV641G
34
A D V A N C E I N F O R M A T I O N
the toggle bit and DQ5 through successive read cy-
DQ2: Toggle Bit II
cles, determining the status as described in the previ-
ous paragraph. Alternatively, it may choose to perform
other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to de-
termine the status of the operation (top of Figure 7).
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
DQ5: Exceeded Timing Limits
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. (The system may use either OE# or CE# to con-
trol the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus-
pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era-
sure. Thus, both status bits are required for sector and
mode information. Refer to Table 11 to compare out-
puts for DQ2 and DQ6.
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under these
conditions DQ5 produces a “1,” indicating that the program
or erase cycle was not successfully completed.
The device may output a “1” on DQ5 if the system tries
to program a “1” to a location that was previously pro-
grammed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the
device halts the operation, and when the timing limit
has been exceeded, DQ5 produces a “1.”
Under both these conditions, the system must write
the reset command to return to the read mode (or to
the erase-suspend-read mode if the device was previ-
ously in the erase-suspend-program mode).
Figure 7 shows the toggle bit algorithm in flowchart
form, and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the DQ6: Toggle Bit I subsection.
Figure 20 shows the toggle bit timing diagram. Figure
21 shows the differences between DQ2 and DQ6 in
graphical form.
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not
erasure has begun. (The sector erase timer does not
apply to the chip erase command.) If additional
sectors are selected for erasure, the entire time-out
also applies after each additional sector erase com-
mand. When the time-out period is complete, DQ3
switches from a “0” to a “1.” If the time between addi-
tional sector erase commands from the system can be
assumed to be less than 50 µs, the system need not
monitor DQ3. See also the Sector Erase Command
Sequence section.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 7 for the following discussion. When-
ever the system initially begins reading toggle bit sta-
tus, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically,
the system would note and store the value of the tog-
gle bit after the first read. After the second read, the
system would compare the new value of the toggle bit
with the first. If the toggle bit is not toggling, the device
has completed the program or erase operation. The
system can read array data on DQ7–DQ0 on the fol-
lowing read cycle.
After the sector erase command is written, the system
should read the status of DQ7 (Data# Polling) or DQ6
(Toggle Bit I) to ensure that the device has accepted
the command sequence, and then read DQ3. If DQ3 is
“1,” the Embedded Erase algorithm has begun; all fur-
ther commands (except Erase Suspend) are ignored
until the erase operation is complete. If DQ3 is “0,” the
device will accept additional sector erase commands.
To ensure the command has been accepted, the sys-
tem software should check the status of DQ3 prior to
and following each subsequent sector erase com-
mand. If DQ3 is high on the second status check, the
last command might not have been accepted.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys-
tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is tog-
gling, since the toggle bit may have stopped toggling
just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the de-
vice did not completed the operation successfully, and
the system must write the reset command to return to
reading array data.
Table 11 shows the status of DQ3 relative to the other
status bits.
The remaining scenario is that the system initially de-
termines that the toggle bit is toggling and DQ5 has
not gone high. The system may continue to monitor
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June 14, 2005
A D V A N C E I N F O R M A T I O N
Table 11. Write Operation Status
DQ7
DQ5
DQ2
Status
(Note 2)
DQ7#
0
DQ6
(Note 1)
DQ3
N/A
1
(Note 2)
Embedded Program Algorithm
Embedded Erase Algorithm
Erase
Erase-Suspend-Re
ad
Toggle
Toggle
0
0
No toggle
Toggle
Standard
Mode
1
No toggle
0
N/A
Toggle
Suspended Sector
Erase
Suspend
Mode
Non-EraseSuspended
Sector
Data
Data
Data
0
Data
N/A
Data
N/A
Erase-Suspend-Program
DQ7#
Toggle
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
Refer to the section on DQ5 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
June 14, 2005
Am29LV641G
36
A D V A N C E I N F O R M A T I O N
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C
20 ns
20 ns
+0.8 V
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . –65°C to +125°C
–0.5 V
–2.0 V
Voltage with Respect to Ground
VCC (Note 1) . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V
VIO. . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +5.5 V
20 ns
A9, OE#, ACC, and RESET#
(Note 2). . . . . . . . . . . . . . . . . . . .–0.5 V to +12.5 V
Figure 8. Maximum Negative
Overshoot Waveform
All other pins (Note 1) . . . . . . –0.5 V to VCC +0.5 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V.
During voltage transitions, input or I/O pins may
overshoot VSS to –2.0 V for periods of up to 20 ns.
Maximum DC voltage on input or I/O pins is VCC +0.5 V.
See Figure 8. During voltage transitions, input or I/O pins
may overshoot to VCC +2.0 V for periods up to 20 ns. See
Figure 9.
20 ns
VCC
+2.0 V
VCC
+0.5 V
2.0 V
2. Minimum DC input voltage on pins A9, OE#, ACC, and
RESET# is –0.5 V. During voltage transitions, A9, OE#,
ACC, and RESET# may overshoot VSS to –2.0 V for
periods of up to 20 ns. See Figure 8. Maximum DC input
voltage on pin A9, OE#, ACC, and RESET# is +12.5 V
which may overshoot to +14.0 V for periods up to 20 ns.
20 ns
20 ns
Figure 9. Maximum Positive
Overshoot Waveform
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This
is a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.
OPERATING RANGES
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C
V
CC Supply Voltages
VCC for all devices . . . . . . . . . . . . . . . . .2.7 V to 3.6 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
37
Am29LV641G
June 14, 2005
A D V A N C E I N F O R M A T I O N
DC CHARACTERISTICS
CMOS Compatible
Parameter
Symbol
Parameter Description
Input Load Current (Note 1)
Test Conditions
VIN = VSS to VCC
VCC = VCC max
VCC = VCC max; A9 = 12.5 V
OUT = VSS to VCC
VCC = VCC max
Min
Typ
Max
1.0
35
Unit
µA
,
ILI
ILIT
ILO
A9, ACC Input Load Current
Output Leakage Current
µA
V
,
1.0
µA
5 MHz
1 MHz
9
2
16
4
VCC Active Read Current
(Notes 2, 3)
ICC1
CE# = VIL, OE# = VIH
mA
ICC2
ICC3
ICC4
ICC5
VCC Active Write Current (Notes 3, 4) CE# = VIL, OE# = VIH, WE# = VIL
15
26
mA
µA
µA
µA
CE#, RESET# = VCC 0.3 V,
VCC Standby Current (Note 3)
WP# = VIH
0.2
0.2
0.2
5
5
5
VCC Reset Current (Note 3)
RESET# = VSS 0.3 V, WP# = VIH
VIH = VCC 0.3 V;
VIL = VSS 0.3 V, WP# = VIH
Automatic Sleep Mode (Notes 3, 5)
VIL
VIH
Input Low Voltage (Note 6)
Input High Voltage (Note 6)
–0.5
0.8
V
V
0.7 x VCC
VCC + 0.3
Voltage for ACC Program
Acceleration
VHH
VID
VCC = 3.0 V ± 10%
VCC = 3.0 V 10%
11.5
8.5
12.5
V
V
Voltage for Autoselect and Temporary
Sector Unprotect
12.5
0.45
VOL
VOH1
VOH2
VLKO
Output Low Voltage
IOL = 4.0 mA, VCC = VCC min
IOH = –2.0 mA, VCC = VCC min
IOH = –100 µA, VCC = VCC min
V
V
V
V
0.85 x VIO
VIO–0.4
2.3
Output High Voltage (Note 7)
Low VCC Lock-Out Voltage (Note 7)
2.5
Notes:
1. On the WP# pin only, the maximum input load current when WP# = VIL is ± 5.0 µA.
2. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.
3. Maximum ICC specifications are tested with VCC = VCCmax.
4. ICC active while Embedded Erase or Embedded Program is in progress.
5. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is
200 nA.
6. If VIO < VCC, maximum VIL for CE# is 0.3 x VIO. If VIO < VCC, minimum VIH for CE# is 0.3 x VIO.
7. Not 100% tested.
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38
A D V A N C E I N F O R M A T I O N
DC CHARACTERISTICS
Zero-Power Flash
25
20
15
10
5
0
0
500
1000
1500
2000
2500
3000
3500
4000
Time in ns
Note: Addresses are switching at 1 MHz
Figure 10. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
12
10
8
3.6 V
2.7 V
6
4
2
0
1
2
3
4
5
Frequency in MHz
Note: T = 25 °C
Figure 11. Typical ICC1 vs. Frequency
39
Am29LV641G
June 14, 2005
A D V A N C E I N F O R M A T I O N
TEST CONDITIONS
Table 12. Test Specifications
3.3 V
Test Condition
Output Load
55R
70R
Unit
1 TTL gate
2.7 kΩ
Device
Under
Test
Output Load Capacitance, CL
(including jig capacitance)
30
5
pF
Input Rise and Fall Times
Input Pulse Levels
ns
V
C
L
6.2 kΩ
0.0–3.0
Input timing measurement
reference levels (See Note)
1.5
V
V
Output timing measurement
reference levels
0.5 VIO
Note: Diodes are IN3064 or equivalent
Figure 12. Test Setup
Note: If VIO < VCC, the reference level is 0.5 VIO.
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
3.0 V
1.5 V
0.5 VIO V
Input
Measurement Level
Output
0.0 V
Note: If VIO < VCC, the input measurement reference level is 0.5 VIO.
Figure 13. Input Waveforms and
Measurement Levels
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40
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
Read-Only Operations
Parameter
Speed Options
JEDEC
tAVAV
Std.
tRC
Description
Test Setup
55R
55
70
70
70
70
Unit
ns
Read Cycle Time (Note 1)
Min
Max
Max
Max
Max
Max
tAVQV
tELQV
tGLQV
tEHQZ
tGHQZ
tACC
tCE
Address to Output Delay
CE#, OE# = VIL
OE# = VIL
55
ns
Chip Enable to Output Delay
55
ns
tOE
Output Enable to Output Delay
Chip Enable to Output High Z (Note 1)
Output Enable to Output High Z (Note 1)
30
16
16
ns
tDF
ns
tDF
ns
Output Hold Time From Addresses, CE# or
OE#, Whichever Occurs First
tAXQX
tOH
Min
Min
Min
0
0
ns
ns
ns
Read
Output Enable Hold
tOEH
Toggle and
Data# Polling
Time (Note 1)
10
Notes:
1. Not 100% tested.
2. See Figure 12 and Table 12 for test specifications.
tRC
Addresses Stable
tACC
Addresses
CE#
tRH
tRH
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
Figure 14. Read Operation Timings
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June 14, 2005
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
JEDEC
Std
Description
RESET# Pin Low (During Embedded Algorithms)
All Speed Options
Unit
tReady
Max
Max
20
μs
to Read Mode (See Note)
RESET# Pin Low (NOT During Embedded
Algorithms) to Read Mode (See Note)
tReady
500
ns
tRP
tRH
RESET# Pulse Width
Min
Min
Min
500
50
ns
ns
μs
Reset High Time Before Read (See Note)
RESET# Low to Standby Mode
tRPD
20
Note: Not 100% tested.
CE#, OE#
tRH
RESET#
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
CE#, OE#
RESET#
tRP
Figure 15. Reset Timings
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42
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
Erase and Program Operations
Parameter
Speed Options
JEDEC
tAVAV
Std.
tWC
tAS
Description
55R
70
Unit
ns
Write Cycle Time (Note 1)
Address Setup Time
Min
Min
Min
Min
55
70
tAVWL
0
ns
tASO
tAH
Address Setup Time to OE# low during toggle bit polling
Address Hold Time
15
40
ns
tWLAX
ns
Address Hold Time From CE# or OE# high
during toggle bit polling
tAHT
Min
0
ns
tDVWH
tWHDX
tDS
tDH
Data Setup Time
Min
Min
Min
40
0
ns
ns
ns
Data Hold Time
tOEPH
Output Enable High during toggle bit polling
20
Read Recovery Time Before Write
(OE# High to WE# Low)
tGHWL
tGHWL
Min
0
ns
tELWL
tWHEH
tCS
tCH
CE# Setup Time
Min
Min
Min
Min
Typ
Typ
Typ
Min
Min
0
0
ns
ns
ns
ns
µs
µs
sec
ns
µs
CE# Hold Time
tWLWH
tWP
Write Pulse Width
30
25
7
tWHDL
tWPH
Write Pulse Width High
tWHWH1
tWHWH1
tWHWH2
tWHWH1
tWHWH1
tWHWH2
tVHH
Word Programming Operation (Note 2)
Accelerated Word Programming Operation (Note 2)
Sector Erase Operation (Note 2)
VHH Rise and Fall Time (Note 1)
VCC Setup Time (Note 1)
4
0.6
250
50
tVCS
Notes:
1. Not 100% tested.
2. See the “Erase And Programming Performance” section for more information.
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A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tAS
PA
tWC
Addresses
555h
PA
PA
tAH
CE#
OE#
tCH
tWHWH1
tWP
WE#
tWPH
tCS
tDS
tDH
PD
DOUT
A0h
Status
Data
VCC
tVCS
Notes:
1. PA = program address, PD = program data, DOUT is the true data at the program address.
Illustration shows device in word mode.
Figure 16. Program Operation Timings
VHH
VIL or VIH
VIL or VIH
ACC
tVHH
tVHH
Figure 17. Accelerated Program Timing Diagram
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A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
Erase Command Sequence (last two cycles)
Read Status Data
VA
tAS
SA
tWC
VA
Addresses
CE#
2AAh
555h for chip erase
tAH
tCH
OE#
tWP
WE#
tWPH
tWHWH2
tCS
tDS
tDH
In
Data
VCC
Complete
55h
30h
Progress
10 for Chip Erase
tVCS
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”.
2. These waveforms are for the word mode.
Figure 18. Chip/Sector Erase Operation Timings
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A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
tRC
Addresses
VA
tACC
tCE
VA
VA
CE#
tCH
tOE
OE#
tOEH
WE#
tDF
tOH
High Z
High Z
DQ7
Valid Data
Complement
Complement
True
DQ6–DQ0
Status Data
True
Valid Data
Status Data
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
Figure 19. Data# Polling Timings
(During Embedded Algorithms)
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A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
tAHT
tAS
Addresses
tAHT
tASO
CE#
tOEH
WE#
tCEPH
tOEPH
OE#
tDH
Valid Data
tOE
Valid
Status
Valid
Status
Valid
Status
DQ6/DQ2
Valid Data
(first read)
(second read)
(stops toggling)
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status
read cycle, and array data read cycle
Figure 20. Toggle Bit Timings
(During Embedded Algorithms)
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase
Complete
WE#
Erase
Erase Suspend
Read
DQ6
DQ2
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle
DQ2 and DQ6.
Figure 21. DQ2 vs. DQ6
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A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
Temporary Sector Unprotect
Parameter
JEDEC
Std
Description
All Speed Options
Unit
tVIDR
VID Rise and Fall Time (See Note)
Min
Min
500
ns
RESET# Setup Time for Temporary Sector
Unprotect
tRSP
4
µs
Note: Not 100% tested.
VID
VID
RESET#
VSS, VIL,
or VIH
VSS, VIL,
or VIH
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
tRSP
Figure 22. Temporary Sector Group Unprotect Timing Diagram
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A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
V
ID
IH
V
RESET#
SA, A6,
A1, A0
Valid*
Valid*
Valid*
Status
Sector Group Protect or Unprotect
Verify
40h
Data
60h
60h
Sector Group Protect: 150 µs,
Sector Group Unprotect: 15 ms
1 µs
CE#
WE#
OE#
* For sector group protect, A6 = 0, A1 = 1, A0 = 0. For sector group unprotect, A6 = 1, A1 = 1, A0 = 0.
Figure 23. Sector Group Protect and Unprotect Timing Diagram
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A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
Alternate CE# Controlled Erase and Program Operations
Parameter
Speed Options
JEDEC
tAVAV
Std
tWC
tAS
Description
55R
70
Unit
ns
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
Min
Min
Min
Min
Min
55
70
tAVWL
tELAX
tDVEH
tEHDX
0
40
40
0
ns
tAH
tDS
tDH
ns
ns
ns
Read Recovery Time Before Write
(OE# High to WE# Low)
tGHEL
tGHEL
Min
0
ns
tWLEL
tEHWH
tELEH
tWS
tWH
WE# Setup Time
Min
Min
Min
Min
Typ
Typ
Typ
0
0
ns
ns
ns
ns
µs
µs
sec
WE# Hold Time
tCP
CE# Pulse Width
45
30
7
tEHEL
tCPH
CE# Pulse Width High
tWHWH1
tWHWH1
tWHWH2
tWHWH1
tWHWH1
tWHWH2
Word Programming Operation (Note 2)
Accelerated Word Programming Operation (Note 2)
Sector Erase Operation (Note 2)
4
0.6
Notes:
1. Not 100% tested.
2. See the “Erase And Programming Performance” section for more information.
June 14, 2005
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50
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
555 for program
2AA for erase
PA for program
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tWH
tAS
tAH
WE#
OE#
tGHEL
tWHWH1 or 2
tCP
CE#
Data
tWS
tCPH
tDS
tBUSY
tDH
DQ7#
DOUT
tRH
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.
4. Waveforms are for the word mode.
Figure 24. Alternate CE# Controlled Write (Erase/Program) Operation Timings
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A D V A N C E I N F O R M A T I O N
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ (Note 1)
Max (Note 2)
Unit
sec
sec
Comments
Sector Erase Time
Chip Erase Time
0.6
50
4
Excludes 00h programming
prior to erasure (Note 4)
Excludes system level
overhead (Note 5)
Word Program Time
7
210
µs
Accelerated Word Program Time
Chip Program Time (Note 3)
Notes:
4
120
54
µs
18
sec
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 1,000,000 cycles. Additionally, programming typicals
assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 3.0 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most words program faster than
the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 10 for further
information on command definitions.
6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Description
Min
Max
Input voltage with respect to VSS on all pins except I/O pins
(including A9, OE#, and RESET#)
–1.0 V
12.5 V
Input voltage with respect to VSS on all I/O pins
–1.0 V
VCC + 1.0 V
+100 mA
V
CC Current
–100 mA
Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.
TSOP & FBGA PIN CAPACITANCE
Parameter Symbol Parameter Description
Test Setup
Typ
Max
Unit
TSOP
6
7.5
CIN
COUT
CIN2
Input Capacitance
Output Capacitance
Control Pin Capacitance
VIN = 0
VOUT = 0
VIN = 0
Fine-pitch
BGA
4.2
8.5
5.4
7.5
3.9
5.0
12
6.5
9
TSOP
Fine-pitch
BGA
TSOP
Fine-pitch
BGA
4.7
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
DATA RETENTION
Parameter Description
Test Conditions
Min
10
Unit
Years
Years
150°C
125°C
Minimum Pattern Data Retention Time
20
June 14, 2005
Am29LV641G
52
A D V A N C E I N F O R M A T I O N
PHYSICAL DIMENSIONS
FBE063—63-Ball Fine-Pitch Ball Grid Array (FBGA) 11 x 12 mm package
Dwg rev AF; 10/99
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Am29LV641G
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A D V A N C E I N F O R M A T I O N
PHYSICAL DIMENSIONS
LAA064–64-Ball Fortified Ball Grid Array (Fortified BGA) 13 x 11 mm package
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Am29LV641G
June 14, 2005
A D V A N C E I N F O R M A T I O N
PHYSICAL DIMENSIONS
TS 048—48-Pin Standard TSOP
)
Dwg rev AA; 10/99
Note: For reference only. BSC is an ANSI standard for Basic Space Centering.
June 14, 2005
Am29LV641G
55
A D V A N C E I N F O R M A T I O N
REVISION SUMMARY
Customer Lockable: SecSi Sector NOT
Programmed or Protected at the factory.
Revision A (August 9, 2002)
Initial Release.
Added second bullet, SecSi sector-protect verify text
and figure 3.
Revision A+1 (August 28, 2002)
Common Flash Memory Interface (CFI)
Ordering Information
Changed wording in last sentence of third paragraph
from, “...the autoselect mode.” to “...reading array
data.”
Corrected order numbers and package markings.
Added Marking Convention explanation about En-
hanced-VIO markings.
Changed CFI website address.
Revision A+2 (October 18, 2002)
Command Definitions
Global
Changed wording in last sentence of first paragraph
from, “...resets the device to reading array data.” to
...”may place the device to an unknown state. A reset
command is then required to return the device to read-
ing array data.”
Added 55R speed grade and removed 90 and 100
speed grade throughout datasheet.
Connection Diagram
Removed the 56–pin SSOP package diagram.
TSOP Pin Capacitance
Added fine-pitch BGA capacitance.
Special Package Handling Instructions
Modified wording.
Revision A+3 (June 14, 2005)
Cover Page / Title Page
Ordering Information
Changed the VIO for 55R to equal 3.0 V–3.6 V and
added 55 ns to Valid Combinations table.
Added Spansion EOL cover page and EOL disclaimer
to AMD title page.
Trademarks
Copyright © 2001 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
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