AM29LV800BT-90FE_技术文档

Am29LV800B

Data Sheet

RETIRED

PRODUCT

This product has been retired and is not recommended for designs. For new and current designs,

S29AL008D supersedes Am29LV800B and is the factory-recommended migration path. Please refer

to the S29AL008D datasheet for specifications and ordering information. Availability of this docu-

ment is retained for reference and historical purposes only.

July 2003

The following document specifies Spansion memory products that are now offered by both Advanced

Micro Devices and Fujitsu. Although the document is marked with the name of the company that

originally developed the specification, these products will be offered to customers of both AMD and

Fujitsu.

Continuity of Specifications

There is no change to this datasheet as a result of offering the device as a Spansion product. Any

changes that have been made are the result of normal datasheet improvement and are noted in the

document revision summary, where supported. Future routine revisions will occur when appro-

priate, and changes will be noted in a revision summary.

For More Information

Please contact your local AMD or Fujitsu sales office for additional information about Spansion

memory solutions.

Publication Number 21490 Revision G Amendment 5 Issue Date May 25, 2005

THIS PAGE LEFT INTENTIONALLY BLANK.

P R E L I M I N A R Y ( D R A F T )

DQ3: Sector Erase Timer ..................................... 24

Product Selector Guide . . . . . . . . . . . . . . . . . . . . .6

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . .7

Special Handling Instructions for FBGA Package ..9

Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . 9

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Ordering Information . . . . . . . . . . . . . . . . . . . . . .10

Standard Products ................................................10

Device Bus Operations . . . . . . . . . . . . . . . . . . . . .11

Table 1. Am29LV800B Device Bus Operations ..........11

Word/Byte Configuration ......................................11

Requirements for Reading Array Data .................11

Writing Commands/Command Sequences ..........11

Program and Erase Operation Status ..................12

Standby Mode ......................................................12

Automatic Sleep Mode .........................................12

RESET#: Hardware Reset Pin .............................12

Output Disable Mode ............................................12

Table 2. Am29LV800BT Top Boot Block

Sector Addresses ........................................................13

Table 3. Am29LV800BB Bottom Boot Block

Sector Addresses ........................................................13

Autoselect Mode ...................................................14

Table 4. Am29LV800B Autoselect Codes

(High Voltage Method) ................................................14

Sector Protection/Unprotection ............................14

Temporary Sector Unprotect ................................14

Figure 1. Temporary Sector Unprotect Operation....... 15

Figure 2. In-System Sector Protect/

Sector Unprotect Algorithms ....................................... 16

Hardware Data Protection ....................................17

Command Definitions . . . . . . . . . . . . . . . . . . . . . 17

Reading Array Data ..............................................17

Reset Command ..................................................17

Autoselect Command Sequence ..........................17

Word/Byte Program Command Sequence ...........18

Figure 3. Program Operation ...................................... 18

Chip Erase Command Sequence .........................19

Sector Erase Command Sequence ......................19

Erase Suspend/Erase Resume Commands .........19

Figure 4. Erase Operation........................................... 20

Table 1. Am29LV800B Command Definitions .............21

Write Operation Status . . . . . . . . . . . . . . . . . . . . 22

DQ7: Data# Polling ...............................................22

Figure 5. Data# Polling Algorithm ............................... 22

RY/BY#: Ready/Busy# .........................................22

DQ6: Toggle Bit I ..................................................23

DQ2: Toggle Bit II .................................................23

Reading Toggle Bits DQ6/DQ2 ............................23

DQ5: Exceeded Timing Limits ..............................23

Figure 6. Toggle Bit Algorithm..................................... 24

Table 2. Write Operation Status ..................................25

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 26

Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 26

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 27

CMOS Compatible ............................................... 27

Figure 9. I

Current vs. Time (Showing Active and

CC1

Automatic Sleep Currents) .......................................... 28

Figure 10. Typical I vs. Frequency ........................ 28

CC1

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 11. Test Setup.................................................. 29

Table 3. Test Specifications ........................................29

Key to Switching Waveforms. . . . . . . . . . . . . . . . 29

Figure 12. Input Waveforms and

Measurement Levels................................................... 29

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 30

Read Operations .................................................. 30

Figure 13. Read Operations Timings .......................... 30

Hardware Reset (RESET#) .................................. 31

Figure 14. RESET# Timings........................................ 31

Word/Byte Configuration (BYTE#) ..................... 32

Figure 15. BYTE# Timings for Read Operations......... 32

Figure 16. BYTE# Timings for Write Operations......... 32

Erase/Program Operations ................................... 33

Figure 17. Program Operation Timings....................... 34

Figure 18. Chip/Sector Erase Operation Timings........ 35

Figure 19. Data# Polling Timings (During

Embedded Algorithms)................................................ 36

Figure 20. Toggle Bit Timings (During

Embedded Algorithms)................................................ 36

Figure 21. DQ2 vs. DQ6.............................................. 37

Temporary Sector Unprotect ................................ 37

Figure 22. Temporary Sector Unprotect

Timing Diagram........................................................... 37

Figure 23. Sector Protect/Unprotect

Timing Diagram........................................................... 38

Alternate CE# Controlled Erase/Program Operations

39

Figure 24. Alternate CE# Controlled Write

Operation Timings....................................................... 40

Erase and Programming Performance . . . . . . . 41

Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 41

TSOP and SO Pin Capacitance . . . . . . . . . . . . . . 41

Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Physical Dimensions* . . . . . . . . . . . . . . . . . . . . . 42

TS 048—48-Pin Standard TSOP ........................ 42

TSR048—48-Pin Reverse TSOP ........................ 43

FBB 048—48-Ball Fine-Pitch Ball Grid Array

(FBGA) 6 x 9 mm ................................................ 44

SO 044—44-Pin Small Outline Package ............. 45

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 46

1

6/1/05

P R E L I M I N A R Y ( D R A F T )

6/1/05

2

Am29LV800B

8 Megabit (1 M x 8-Bit/512 K x 16-Bit)

CMOS 3.0 Volt-only Boot Sector Flash Memory

For new designs, S29AL008D supersedes Am29LV800B and is the factory-recommended migration path for this device. Please refer to the S29AL008D Family Datasheet for specifications

and ordering information.

DISTINCTIVE CHARACTERISTICS

• Single power supply operation

• Embedded Algorithms

— 2.7 to 3.6 volt read and write operations for

battery-powered applications

— Embedded Erase algorithm automatically

preprograms and erases the entire chip or any

combination of designated sectors

— Embedded Program algorithm automatically

writes and verifies data at specified addresses

• Manufactured on 0.32 µm process

technology

— Compatible with 0.5 µm Am29LV800 device

• Minimum 1 million write cycle guarantee

per sector

• High performance

— Access times as fast as 70 ns

• 20-year data retention at 125°C

• Ultra low power consumption (typical

values at 5 MHz)

— Reliable operation for the life of the system

• Package option

— 48-ball FBGA

— 200 nA Automatic Sleep mode current

— 200 nA standby mode current

— 7 mA read current

— 48-pin TSOP

— 44-pin SO

— Known Good Die (KGD)

— 15 mA program/e+5rase current

(see publication number 21536)

• Flexible sector architecture

— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and

fifteen 64 Kbyte sectors (byte mode)

— One 8 Kword, two 4 Kword, one 16 Kword, and

fifteen 32 Kword sectors (word mode)

— Supports full chip erase

— Sector Protection features:

• Compatibility with JEDEC standards

— Pinout and software compatible with single-

power supply Flash

— Superior inadvertent write protection

• Data# Polling and toggle bits

— Provides a software method of detecting

program or erase operation completion

A hardware method of locking a sector to prevent

any program or erase operations within that sector

• Ready/Busy# pin (RY/BY#)

Sectors can be locked in-system or via

programming equipment

— Provides a hardware method of detecting

program or erase cycle completion

Temporary Sector Unprotect feature allows code

changes in previously locked sectors

• Erase Suspend/Erase Resume

— Suspends an erase operation to read data from,

or program data to, a sector that is not being

erased, then resumes the erase operation

• Unlock Bypass Program Command

— Reduces overall programming time when

issuing multiple program command sequences

• Hardware reset pin (RESET#)

• Top or bottom boot block configurations

available

— Hardware method to reset the device to reading

array data

This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This

Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.

Publication# 21490

Issue Date: May 25, 2005

Rev: G Amendment/+5

GENERAL DESCRIPTION

The Am29LV800B is an 8 Mbit, 3.0 volt-only Flash

memory organized as 1,048,576 bytes or 524,288

words. The device is offered in 48-ball FBGA, 44-pin

SO, and 48-pin TSOP packages. The device is also

available in Known Good Die (KGD) form. For more

information, refer to publication number 21536. The

word-wide data (x16) appears on DQ15–DQ0; the

byte-wide (x8) data appears on DQ7–DQ0. This

matically preprograms the array (if it is not already

programmed) before executing the erase operation.

During erase, the device automatically times the

erase pulse widths and verifies proper cell margin.

The host system can detect whether a program or

erase operation is complete by observing the RY/BY#

pin, or by reading the DQ7 (Data# Polling) and DQ6

(toggle) status bits. After a program or erase cycle

has been completed, the device is ready to read array

data or accept another command.

device requires only a single, 3.0 volt V

supply to

CC

perform read, program, and erase operations. A stan-

dard EPROM programmer can also be used to program

and erase the device.

The sector erase architecture allows memory

sectors to be erased and reprogrammed without

affecting the data contents of other sectors. The

device is fully erased when shipped from the factory.

This device is manufactured using AMD’s 0.32 µm

process technology, and offers all the features and

benefits of the Am29LV800, which was manufactured

using 0.5 µm process technology. In addition, the

Am29LV800B features unlock bypass programming

and in-system sector protection/unprotection.

Hardware data protection measures include a low

V

detector that automatically inhibits write opera-

CC

tions during power transitions. The hardware sector

protection feature disables both program and erase

operations in any combination of the sectors of

memory. This can be achieved in-system or via pro-

gramming equipment.

The standard device offers access times of 70, 90,

and 120 ns, allowing high speed microprocessors to

operate without wait states. To eliminate bus conten-

tion the device has separate chip enable (CE#), write

enable (WE#) and output enable (OE#) controls.

The Erase Suspend feature enables the user to put

erase on hold for any period of time to read data

from, or program data to, any sector that is not

selected for erasure. True background erase can thus

be achieved.

The device requires only a single 3.0 volt power

supply for both read and write functions. Internally

generated and regulated voltages are provided for

the program and erase operations.

The hardware RESET# pin terminates any opera-

tion in progress and resets the internal state machine

to reading array data. The RESET# pin may be tied to

the system reset circuitry. A system reset would thus

also reset the device, enabling the system micropro-

cessor to read the boot-up firmware from the Flash

memory.

The device is entirely command set compatible with

the JEDEC single-power-supply Flash standard.

Commands are written to the command register

using standard microprocessor write timings. Reg-

ister contents serve as input to an internal state-

machine that controls the erase and programming

circuitry. Write cycles also internally latch addresses

and data needed for the programming and erase

operations. Reading data out of the device is similar

to reading from other Flash or EPROM devices.

The device offers two power-saving features. When

addresses have been stable for a specified amount of

time, the device enters the automatic sleep mode.

The system can also place the device into the

standby mode. Power consumption is greatly

reduced in both these modes.

Device programming occurs by executing the

program command sequence. This initiates the

Embedded Program algorithm—an internal algo-

rithm that automatically times the program pulse

widths and verifies proper cell margin. The Unlock

Bypass mode facilitates faster programming times

by requiring only two write cycles to program data

instead of four.

AMD’s Flash technology combines years of Flash

memory manufacturing experience to produce the

highest levels of quality, reliability and cost effective-

ness. The device electrically erases all bits within

a sector simultaneously via Fowler-Nordheim tun-

neling. The data is programmed using hot electron

injection.

Device erasure occurs by executing the erase

command sequence. This initiates the Embedded

Erase algorithm—an internal algorithm that auto-

4

Am29LV800B

TABLE OF CONTENTS

Product Selector Guide . . . . . . . . . . . . . . . . . . . . .6

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . .7

Special Handling Instructions for FBGA Package ..9

Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . 9

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Ordering Information . . . . . . . . . . . . . . . . . . . . . .10

Standard Products ................................................10

Device Bus Operations . . . . . . . . . . . . . . . . . . . . .11

Table 1. Am29LV800B Device Bus Operations ..........11

Word/Byte Configuration ......................................11

Requirements for Reading Array Data .................11

Writing Commands/Command Sequences ..........11

Program and Erase Operation Status ..................12

Standby Mode ......................................................12

Automatic Sleep Mode .........................................12

RESET#: Hardware Reset Pin .............................12

Output Disable Mode ............................................12

Table 2. Am29LV800BT Top Boot Block

Sector Addresses ........................................................13

Table 3. Am29LV800BB Bottom Boot Block

Sector Addresses ........................................................13

Autoselect Mode ...................................................14

Table 4. Am29LV800B Autoselect Codes

(High Voltage Method) ................................................14

Sector Protection/Unprotection ............................14

Temporary Sector Unprotect ................................14

Figure 1. Temporary Sector Unprotect Operation....... 15

Figure 2. In-System Sector Protect/

Sector Unprotect Algorithms ....................................... 16

Hardware Data Protection ....................................17

Command Definitions . . . . . . . . . . . . . . . . . . . . . 17

Reading Array Data ..............................................17

Reset Command ..................................................17

Autoselect Command Sequence ..........................17

Word/Byte Program Command Sequence ...........18

Figure 3. Program Operation ...................................... 18

Chip Erase Command Sequence .........................19

Sector Erase Command Sequence ......................19

Erase Suspend/Erase Resume Commands .........19

Figure 4. Erase Operation........................................... 20

Table 1. Am29LV800B Command Definitions .............21

Write Operation Status . . . . . . . . . . . . . . . . . . . . 22

DQ7: Data# Polling ...............................................22

Figure 5. Data# Polling Algorithm ............................... 22

RY/BY#: Ready/Busy# .........................................22

DQ6: Toggle Bit I ..................................................23

DQ2: Toggle Bit II .................................................23

Reading Toggle Bits DQ6/DQ2 ............................23

DQ5: Exceeded Timing Limits ..............................23

Figure 6. Toggle Bit Algorithm..................................... 24

DQ3: Sector Erase Timer ..................................... 24

Table 2. Write Operation Status ..................................25

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 26

Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 26

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 27

CMOS Compatible ............................................... 27

Figure 9. I

Current vs. Time (Showing Active and

CC1

Automatic Sleep Currents) .......................................... 28

Figure 10. Typical I vs. Frequency ........................ 28

CC1

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 11. Test Setup.................................................. 29

Table 3. Test Specifications ........................................29

Key to Switching Waveforms. . . . . . . . . . . . . . . . 29

Figure 12. Input Waveforms and

Measurement Levels................................................... 29

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 30

Read Operations .................................................. 30

Figure 13. Read Operations Timings .......................... 30

Hardware Reset (RESET#) .................................. 31

Figure 14. RESET# Timings........................................ 31

Word/Byte Configuration (BYTE#) ..................... 32

Figure 15. BYTE# Timings for Read Operations......... 32

Figure 16. BYTE# Timings for Write Operations......... 32

Erase/Program Operations ................................... 33

Figure 17. Program Operation Timings....................... 34

Figure 18. Chip/Sector Erase Operation Timings........ 35

Figure 19. Data# Polling Timings (During

Embedded Algorithms)................................................ 36

Figure 20. Toggle Bit Timings (During

Embedded Algorithms)................................................ 36

Figure 21. DQ2 vs. DQ6.............................................. 37

Temporary Sector Unprotect ................................ 37

Figure 22. Temporary Sector Unprotect

Timing Diagram........................................................... 37

Figure 23. Sector Protect/Unprotect

Timing Diagram........................................................... 38

Alternate CE# Controlled Erase/Program Operations

39

Figure 24. Alternate CE# Controlled Write

Operation Timings....................................................... 40

Erase and Programming Performance . . . . . . . 41

Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 41

TSOP and SO Pin Capacitance . . . . . . . . . . . . . . 41

Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Physical Dimensions* . . . . . . . . . . . . . . . . . . . . . 42

TS 048—48-Pin Standard TSOP ........................ 42

TSR048—48-Pin Reverse TSOP ........................ 43

FBB 048—48-Ball Fine-Pitch Ball Grid Array

(FBGA) 6 x 9 mm ................................................ 44

SO 044—44-Pin Small Outline Package ............. 45

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 46

Am29LV800B

5

PRODUCT SELECTOR GUIDE

Family Part Number

Am29LV800B

Speed Options

Full Voltage Range: V_CC= 2.7–3.6 V

-70

-90

-120

Max access time, ns (t_ACC

)

70

30

90

35

120

50

Max CE# access time, ns (t_CE

)

Max OE# access time, ns (t_OE

)

Note: See “AC Characteristics” for full specifications.

BLOCK DIAGRAM

DQ0–DQ15 (A-1)

RY/BY#

V

CC

Sector Switches

SS

Erase Voltage

Generator

Input/Output

Buffers

RESET#

State

Control

WE#

BYTE#

Command

Register

PGM Voltage

Generator

Data

Latch

Chip Enable

Output Enable

Logic

STB

CE#

OE#

Y-Decoder

Y-Gating

STB

V

Detector

CC

Timer

Cell Matrix

X-Decoder

A0–

A18

6

Am29LV800B

CONNECTION DIAGRAMS

This device is also available in Known Good Die (KGD) form. Refer to publication number 21536 for

more information.

A15

A14

A13

A12

A11

A10

A9

A8

NC

1

2

3

4

5

6

7

8

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A16

BYTE#

V

SS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

WE#

RESET#

NC

DQ4

V

CC

Standard TSOP

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

NC

RY/BY#

A18

A17

A7

A6

A5

A4

A3

A2

A1

V

SS

CE#

A0

1

2

3

4

5

6

7

8

A15

A14

A13

A12

A11

A10

A9

A8

NC

48

A16

BYTE#

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

V

SS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

9

Reverse TSOP

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

WE#

RESET#

NC

DQ4

V

CC

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

NC

RY/BY#

A18

A17

A7

A6

A5

A4

A3

A2

V

SS

CE#

A0

A1

21490G-1

Am29LV800B

7

CONNECTION DIAGRAMS

This device is also available in Known Good Die (KGD) form. Refer to publication number 21536 for

more information.

RY/BY#

A18

A17

A7

1

2

3

4

5

6

7

8

9

44 RESET#

43 WE#

42 A8

41 A9

A6

40 A10

39 A11

38 A12

37 A13

36 A14

35 A15

34 A16

33 BYTE#

A5

A4

A3

A2

SO

A1 10

A0 11

CE# 12

V

13

32 V

SS

OE# 14

DQ0 15

DQ8 16

DQ1 17

DQ9 18

DQ2 19

DQ10 20

DQ3 21

DQ11 22

31 DQ15/A-1

30 DQ7

29 DQ14

28 DQ6

27 DQ13

26 DQ5

25 DQ12

24 DQ4

23 V

CC

FBGA

Top View, Balls Facing Down

A6

B6

C6

D6

E6

F6

G6

H6

A13

A12

A14

A15

A16

BYTE# DQ15/A-1

V

SS

A5

A9

B5

A8

C5

D5

E5

F5

G5

H5

A10

A11

DQ7

DQ14

DQ13

DQ6

A4

B4

C4

NC

D4

NC

E4

F4

G4

H4

WE#

RESET#

DQ5

DQ12

V

DQ4

CC

A3

B3

C3

D3

NC

E3

F3

G3

H3

RY/BY#

NC

A18

DQ2

DQ10

DQ11

DQ3

A2

A7

B2

C2

A6

D2

A5

E2

F2

G2

H2

A17

DQ0

DQ8

DQ9

DQ1

A1

A3

B1

A4

C1

A2

D1

A1

E1

A0

F1

G1

H1

CE#

OE#

V

SS

8

Am29LV800B

Flash memory devices in FBGA packages may be

damaged if exposed to ultrasonic cleaning methods.

The package and/or data integrity may be compro-

mised if the package body is exposed to temperatures

above 150°C for prolonged periods of time.

Special Handling Instructions for FBGA

Package

Special handling is required for Flash Memory prod-

ucts in FBGA packages.

NC

= Pin not connected internally

PIN CONFIGURATION

A0–A18 = 19 addresses

LOGIC SYMBOL

DQ0–DQ14= 15 data inputs/outputs

19

DQ15/A-1 = DQ15 (data input/output, word

A0–A18

16 or 8

mode),

DQ0–DQ15

(A-1)

A-1 (LSB address input, byte

mode)

CE#

OE#

BYTE#

CE#

= Selects 8-bit or 16-bit mode

= Chip enable

WE#

OE#

= Output enable

RESET#

BYTE#

WE#

= Write enable

RY/BY#

RESET# = Hardware reset pin, active low

RY/BY# = Ready/Busy# output

V

= 3.0 volt-only single power supply

(see Product Selector Guide for

speed

CC

SS

options and voltage supply

tolerances)

V

= Device ground

Am29LV800B

9

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Com-

bination) is formed by a combination of the elements below.

Am29LV800B

T

-70

E

C

TEMPERATURE RANGE

C

D

I

F

E

K

=

Commercial (0°C to +70°C)

Commercial (0°C to +70°C) with Pb-free package

Industrial (–40°C to +85°C)

Industrial (–40°C to +85°C) with Pb-free package

Extended (–55°C to +125°C)

Extended (–55°C to +125°C) with Pb-free package

PACKAGE TYPE

E

F

S

WB

=

48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048)

48-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR048)

44-Pin Small Outline Package (SO 044)

48-Ball Fine Pitch Ball Grid Array (FBGA)

0.80 mm pitch, 6 x 9 mm package (FBB048)

This device is also available in Known Good Die (KGD) form. See publication

number 21536 for more information.

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T

B

=

Top sector

Bottom sector

DEVICE NUMBER/DESCRIPTION

Am29LV800B

8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS Flash Memory

3.0 Volt-only Read, Program, and Erase

Valid Combinations for TSOP and SO Packages

Valid Combinations for FBGA Packages

Order Number Package Marking

AM29LV800BT-70,

AM29LV800BB-70

EC, EI, FC, FI, SC, SI,

ED, EF, SD, SF

WBC,

AM29LV800BT-90,

AM29LV800BB-90

AM29LV800BT-70,

AM29LV800BB-70

WBD, L800BT70V,

WBI, L800BB70V

WBF

C, D,

I, F

EC, EI, EE, ED, EF

FC, FI, FE,

SC, SI, SE, SD, SF, EK, SK

AM29LV800BT-120,

AM29LV800BB-120

AM29LV800BT-90,

AM29LV800BB-90

WBC, L800BT90V,

WBI, L800BB90V

WBD,

C, I,

D, F

K, E

WBF,

WBK,

WBE

AM29LV800BT-120,

AM29LV800BB-120

L800BT12V,

L800BB12V

Valid Combinations

Valid Combinations list configurations planned to be

supported in volume for this device. Consult the local

AMD sales office to confirm availability of specific

valid combinations and to check on newly released

combinations.

10

Am29LV800B

DEVICE BUS OPERATIONS

This section describes the requirements and use of

the device bus operations, which are initiated through

the internal command register. The command reg-

ister itself does not occupy any addressable memory

location. The register is composed of latches that

store the commands, along with the address and data

information needed to execute the command. The

contents of the register serve as inputs to the internal

state machine. The state machine outputs dictate the

function of the device. Table 1 lists the device bus

operations, the inputs and control levels they require,

and the resulting output. The following subsections

describe each of these operations in further detail.

Table 1. Am29LV800B Device Bus Operations

DQ8–DQ15

DQ0– BYTE# BYTE#

WE

Addresses

(Note 1)

Operation

CE# OE#

#

H

L

RESET#

DQ7

D_OUT

D_IN

= V_IH

D_OUT

D_IN

= V_IL

Read

Write

L

H

A_IN

DQ8–DQ14 = High-Z,

DQ15 = A-1

H

V_CC

0.3 V

±

V_CC±

0.3 V

Standby

X

High-Z High-Z

High-Z

Output Disable

Reset

L

H

X

H

X

H

L

X

High-Z High-Z

High-Z

X

Sector Address,

A6 = L, A1 = H,

A0 = L

Sector Protect (Note 2)

L

H

L

V_ID

D_IN

X

Sector Address,

A6 = H, A1 = H,

A0 = L

Sector Unprotect (Note 2)

L

H

X

L

V_ID

D_IN

X

Temporary Sector Unprotect

X

A_IN

D_IN

High-Z

Legend:

L = Logic Low = V_IL, H = Logic High = V_IH, V_ID= 12.0 ± 0.5 V, X = Don’t Care, A_IN= Address In, D_IN= Data In, D_OUT= Data Out

Notes:

1. Addresses are A18:A0 in word mode (BYTE# = V_IH), A18:A-1 in byte mode (BYTE# = V_IL).

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector

Protection/Unprotection” section.

memory content occurs during the power transition.

Word/Byte Configuration

No command is necessary in this mode to obtain

The BYTE# pin controls whether the device data I/O

array data. Standard microprocessor read cycles that

pins DQ15–DQ0 operate in the byte or word configu-

assert valid addresses on the device address inputs

ration. If the BYTE# pin is set at logic ‘1’, the device

produce valid data on the device data outputs. The

is in word configuration, DQ15–DQ0 are active and

device remains enabled for read access until the

controlled by CE# and OE#.

command register contents are altered.

If the BYTE# pin is set at logic ‘0’, the device is in byte

See “Reading Array Data” for more information. Refer

configuration, and only data I/O pins DQ0–DQ7 are

to the AC Read Operations table for timing specifica-

active and controlled by CE# and OE#. The data I/O

tions and to Figure 13 for the timing diagram. I

the DC Characteristics table represents the active

current specification for reading array data.

in

CC1

pins DQ8–DQ14 are tri-stated, and the DQ15 pin is

used as an input for the LSB (A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must

Writing Commands/Command Sequences

To write a command or command sequence (which

includes programming data to the device and erasing

sectors of memory), the system must drive WE# and

drive the CE# and OE# pins to V . CE# is the power

IL

control and selects the device. OE# is the output

control and gates array data to the output pins. WE#

CE# to V , and OE# to V .

IL

IH

should remain at V . The BYTE# pin determines

IH

For program operations, the BYTE# pin determines

whether the device accepts program data in bytes or

words. Refer to “Word/Byte Configuration” for more

information.

whether the device outputs array data in words or

bytes.

The internal state machine is set for reading array

data upon device power-up, or after a hardware

reset. This ensures that no spurious alteration of the

Am29LV800B

11

The device features an Unlock Bypass mode to facil-

itate faster programming. Once the device enters the

Unlock Bypass mode, only two write cycles are

required to program a word or byte, instead of four.

The “Word/Byte Program Command Sequence”

section has details on programming data to the

device using both standard and Unlock Bypass

command sequences.

In the DC Characteristics table, I

sents the standby current specification.

and I

repre-

CC4

CC3

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device

energy consumption. The device automatically

enables this mode when addresses remain stable for

t

+ 30 ns. The automatic sleep mode is indepen-

ACC

dent of the CE#, WE#, and OE# control signals. Stan-

dard address access timings provide new data when

addresses are changed. While in sleep mode, output

data is latched and always available to the system.

An erase operation can erase one sector, multiple sec-

tors, or the entire device. Tables 2 and 3 indicate the

address space that each sector occupies. A “sector

address” consists of the address bits required to

uniquely select a sector. The “Command Definitions”

section has details on erasing a sector or the entire

chip, or suspending/resuming the erase operation.

I

in the DC Characteristics table represents the

CC4

automatic sleep mode current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of

resetting the device to reading array data. When the

After the system writes the autoselect command

sequence, the device enters the autoselect mode.

The system can then read autoselect codes from the

internal register (which is separate from the memory

array) on DQ7–DQ0. Standard read cycle timings

apply in this mode. Refer to the “Autoselect Mode”

and “Autoselect Command Sequence” sections for

more information.

RESET# pin is driven low for at least a period of t ,

RP

the device immediately terminates any operation

in progress, tristates all output pins, and ignores all

read/write commands for the duration of the RESET#

pulse. The device also resets the internal state

machine to reading array data. The operation that

was interrupted should be reinitiated once the device

is ready to accept another command sequence, to

ensure data integrity.

I

in the DC Characteristics table represents the

CC2

active current specification for the write mode. The

“AC Characteristics” section contains timing specifica-

tion tables and timing diagrams for write operations.

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at V ±0.3 V, the device

Program and Erase Operation Status

During an erase or program operation, the system

may check the status of the operation by reading the

status bits on DQ7–DQ0. Standard read cycle timings

SS

draws CMOS standby current (I

). If RESET# is

CC4

held at V but not within V ±0.3 V, the standby

IL

SS

current will be greater.

The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash

memory, enabling the system to read the boot-up

firmware from the Flash memory.

and I

read specifications apply. Refer to “Write

CC

Operation Status” for more information, and to “AC

Characteristics” for timing diagrams.

Standby Mode

If RESET# is asserted during a program or erase

operation, the RY/BY# pin remains a “0” (busy) until

the internal reset operation is complete, which

When the system is not reading or writing to the

device, it can place the device in the standby mode.

In this mode, current consumption is greatly reduced,

and the outputs are placed in the high impedance

state, independent of the OE# input.

requires a time of t

(during Embedded Algo-

READY

rithms). The system can thus monitor RY/BY# to

determine whether the reset operation is complete. If

RESET# is asserted when a program or erase opera-

tion is not executing (RY/BY# pin is “1”), the reset

The device enters the CMOS standby mode when the

CE# and RESET# pins are both held at V ± 0.3 V.

(Note that this is a more restricted voltage range than

CC

operation is completed within a time of t

(not

READY

during Embedded Algorithms). The system can read

data t after the RESET# pin returns to V .

V .) If CE# and RESET# are held at V , but not

IH

RH

IH

within V ± 0.3 V, the device will be in the standby

CC

mode, but the standby current will be greater. The

Refer to the AC Characteristics tables for RESET#

parameters and to Figure 14 for the timing diagram.

device requires standard access time (t ) for read

CE

access when the device is in either of these standby

modes, before it is ready to read data.

Output Disable Mode

If the device is deselected during erasure or program-

ming, the device draws active current until the

operation is completed.

12

Am29LV800B

When the OE# input is at V , output from the device

IH

is disabled. The output pins are placed in the high

impedance state.

Table 2. Am29LV800BT Top Boot Block Sector Addresses

Address Range (in hexadecimal)

Sector Size

(Kbytes/

Kwords)

(x8)

(x16)

Sector

SA0

A18

0

A17

0

A16

0

A15

0

A14

X

0

A13

X

0

A12

X

Address Range

64/32

32/16

8/4

00000h–0FFFFh

10000h–1FFFFh

20000h–2FFFFh

30000h–3FFFFh

40000h–4FFFFh

50000h–5FFFFh

60000h–6FFFFh

70000h–7FFFFh

80000h–8FFFFh

90000h–9FFFFh

A0000h–AFFFFh

B0000h–BFFFFh

C0000h–CFFFFh

D0000h–DFFFFh

E0000h–EFFFFh

F0000h–F7FFFh

F8000h–F9FFFh

FA000h–FBFFFh

FC000h–FFFFFh

00000h–07FFFh

08000h–0FFFFh

10000h–17FFFh

18000h–1FFFFh

20000h–27FFFh

28000h–2FFFFh

30000h–37FFFh

38000h–3FFFFh

40000h–47FFFh

48000h–4FFFFh

50000h–57FFFh

58000h–5FFFFh

60000h–67FFFh

68000h–6FFFFh

70000h–77FFFh

78000h–7BFFFh

7C000h–7CFFFh

7D000h–7DFFFh

7E000h–7FFFFh

SA1

0

1

X

SA2

0

1

0

X

SA3

0

1

X

SA4

0

1

0

X

SA5

0

1

0

1

X

SA6

0

1

0

X

SA7

0

1

X

SA8

1

0

X

SA9

1

0

1

X

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

1

0

1

0

X

1

0

1

X

1

0

X

1

0

1

X

1

0

X

1

X

1

0

1

0

1

8/4

1

X

16/8

Table 3. Am29LV800BB Bottom Boot Block Sector Addresses

Address Range (in hexadecimal)

Sector Size

(Kbytes/

Kwords)

(x8)

(x16)

Sector

SA0

A18

0

A17

0

A16

0

A15

0

A14

0

A13

0

A12

X

Address Range

16/8

8/4

00000h–03FFFh

04000h–05FFFh

06000h–07FFFh

08000h–0FFFFh

10000h–1FFFFh

20000h–2FFFFh

30000h–3FFFFh

40000h–4FFFFh

50000h–5FFFFh

60000h–6FFFFh

70000h–7FFFFh

80000h–8FFFFh

90000h–9FFFFh

A0000h–AFFFFh

B0000h–BFFFFh

C0000h–CFFFFh

D0000h–DFFFFh

E0000h–EFFFFh

F0000h–FFFFFh

00000h–01FFFh

02000h–02FFFh

03000h–03FFFh

04000h–07FFFh

08000h–0FFFFh

10000h–17FFFh

18000h–1FFFFh

20000h–27FFFh

28000h–2FFFFh

30000h–37FFFh

38000h–3FFFFh

40000h–47FFFh

48000h–4FFFFh

50000h–57FFFh

58000h–5FFFFh

60000h–67FFFh

68000h–6FFFFh

70000h–77FFFh

78000h–7FFFFh

SA1

0

1

0

SA2

0

1

8/4

SA3

0

1

X

32/16

64/32

SA4

0

1

X

SA5

0

1

0

X

SA6

0

1

X

SA7

0

1

0

X

SA8

0

1

0

1

X

SA9

0

1

0

X

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

0

1

X

1

0

X

1

0

1

X

1

0

1

0

X

1

0

1

X

1

0

X

1

0

1

X

1

0

X

1

X

Note for Tables 2 and 3: Address range is A18:A-1 in byte

mode and A18:A0 in word mode. See “Word/Byte

Configuration” section.

Am29LV800B

13

Table 4. In addition, when verifying sector protection,

the sector address must appear on the appropriate

highest order address bits (see Tables 2 and 3). Table

4 shows the remaining address bits that are don’t

care. When all necessary bits have been set as

required, the programming equipment may then read

the corresponding identifier code on DQ7–DQ0.

Autoselect Mode

The autoselect mode provides manufacturer and

device identification, and sector protection verifica-

tion, through identifier codes output on DQ7–DQ0.

This mode is primarily intended for programming

equipment to automatically match a device to be pro-

grammed with its corresponding programming algo-

rithm. However, the autoselect codes can also be

accessed in-system through the command register.

To access the autoselect codes in-system, the host

system can issue the autoselect command via the

command register, as shown in Table 1. This method

When using programming equipment, the autoselect

does not require V . See “Command Definitions” for

ID

mode requires V (11.5 V to 12.5 V) on address pin

ID

details on using the autoselect mode.

A9. Address pins A6, A1, and A0 must be as shown in

Table 4. Am29LV800B Autoselect Codes (High Voltage Method)

A18 A11

to to

Mode CE# OE# WE# A12 A10 A9

A8

to

A7

A5

to

A2

DQ8

to

DQ15

DQ7

to

DQ0

Description

A6

A1

A0

Manufacturer ID: AMD

L

H

X

V_ID

X

L

X

L

X

01h

DAh

Device ID:

Am29LV800B

(Top Boot Block)

Word

Byte

Word

22h

X

V_ID

X

L

X

L

H

L

H

X

DAh

5Bh

Device ID:

Am29LV800B

(Bottom Boot

Block)

22h

X

V_ID

X

Byte

L

H

X

5Bh

01h

(protected)

Sector Protection

Verification

L

H

SA

V_ID

L

H

L

00h

(unprotected

)

X

L = Logic Low = V_IL, H = Logic High = V_IH, SA = Sector

Address, X = Don’t care.

timing. For sector unprotect, all unprotected sectors

must first be protected prior to the first sector unpro-

tect write cycle.

Sector Protection/Unprotection

The hardware sector protection feature disables both

program and erase operations in any sector. The

hardware sector unprotection feature re-enables both

program and erase operations in previously protected

sectors.

The alternate method intended only for programming

equipment requires V on address pin A9 and OE#.

ID

This method is compatible with programmer routines

written for earlier 3.0 volt-only AMD flash devices.

Publication number 20536 contains further details;

contact an AMD representative to request a copy.

The device is shipped with all sectors unprotected.

AMD offers the option of programming and protecting

sectors at its factory prior to shipping the device

through AMD’s ExpressFlash™ Service. Contact an

AMD representative for details.

Temporary Sector Unprotect

This feature allows temporary unprotection of previ-

ously protected sectors to change data in-system.

The Sector Unprotect mode is activated by setting the

It is possible to determine whether a sector is pro-

tected or unprotected. See “Autoselect Mode” for

details.

RESET# pin to V . During this mode, formerly pro-

ID

tected sectors can be programmed or erased by

Sector Protection/unprotection can be implemented

via two methods.

selecting the sector addresses. Once V is removed

ID

from the RESET# pin, all the previously protected

sectors are protected again. Figure 1 shows the algo-

rithm, and Figure 22 shows the timing diagrams, for

this feature.

The primary method requires V on the RESET# pin

ID

only, and can be implemented either in-system or via

programming equipment. Figure 2 shows the algo-

rithms and Figure 23 shows the timing diagram. This

method uses standard microprocessor bus cycle

14

Am29LV800B

START

RESET# = V_ID

(Note 1)

Perform Erase or

Program Operations

RESET# = V_IH

Temporary Sector

Unprotect Completed

(Note 2)

Notes:

1. All protected sectors unprotected.

2. All previously protected sectors are protected once

again.

Figure 1. Temporary Sector Unprotect Operation

Am29LV800B

15

START

Protect all sectors:

The indicated portion

of the sector protect

algorithm must be

performed for all

unprotected sectors

prior to issuing the

first sector

PLSCNT = 1

RESET# = V

ID

RESET# = V

ID

Wait 1 ms

unprotect address

No

First Write

Cycle = 60h?

No

First Write

Cycle = 60h?

Temporary Sector

Unprotect Mode

Temporary Sector

Unprotect Mode

Yes

Set up sector

address

No

All sectors

protected?

Sector Protect:

Write 60h to sector

address with

A6 = 0, A1 = 1,

A0 = 0

Yes

Set up first sector

address

Sector Unprotect:

Wait 150 μs

Write 60h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Verify Sector

Protect: Write 40h

to sector address

with A6 = 0,

Reset

PLSCNT = 1

Increment

PLSCNT

Wait 15 ms

A1 = 1, A0 = 0

Verify Sector

Unprotect: Write

40h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector address

with A6 = 0,

A1 = 1, A0 = 0

Increment

PLSCNT

No

PLSCNT

= 25?

Read from

sector address

with A6 = 1,

A1 = 1, A0 = 0

Data = 01h?

Yes

No

Yes

Set up

next sector

address

Yes

No

PLSCNT

= 1000?

Protect another

sector?

Data = 00h?

Yes

Device failed

No

Yes

Remove V

from RESET#

ID

No

Last sector

verified?

Device failed

Write reset

command

Yes

Remove V

from RESET#

ID

Sector Unprotect

Algorithm

Sector Protect

Algorithm

Sector Protect

complete

Write reset

command

Sector Unprotect

complete

Figure 2. In-System Sector Protect/

Sector Unprotect Algorithms

16

Am29LV800B

prevent unintentional writes when V is greater than

Hardware Data Protection

CC

V

.

LKO

The command sequence requirement of unlock cycles

for programming or erasing provides data protection

against inadvertent writes (refer to Table 1 for

command definitions). In addition, the following

hardware data protection measures prevent acci-

dental erasure or programming, which might other-

wise be caused by spurious system level signals

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE#

or WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE#

during V power-up and power-down transitions, or

CC

= V , CE# = V or WE# = V . To initiate a write

IL

IH

from system noise.

cycle, CE# and WE# must be a logical zero while OE#

is a logical one.

Low V

Write Inhibit

CC

When V

Power-Up Write Inhibit

is less than V

, the device does not

LKO

CC

accept any write cycles. This protects data during V

CC

If WE# = CE# = V and OE# = V during power up,

IL

IH

power-up and power-down. The command register

and all internal program/erase circuits are disabled,

and the device resets. Subsequent writes are ignored

the device does not accept commands on the rising

edge of WE#. The internal state machine is automat-

ically reset to reading array data on power-up.

until V

is greater than V

. The system must

CC

LKO

provide the proper signals to the control pins to

COMMAND DEFINITIONS

Writing specific address and data commands or

sequences into the command register initiates device

operations. Table 1 defines the valid register

command sequences. Writing incorrect address

and data values or writing them in the improper

sequence resets the device to reading array data.

Reset Command

Writing the reset command to the device resets the

device to reading array data. Address bits are don’t

care for this command.

The reset command may be written between the

sequence cycles in an erase command sequence

before erasing begins. This resets the device to

reading array data. Once erasure begins, however,

the device ignores reset commands until the opera-

tion is complete.

All addresses are latched on the falling edge of WE#

or CE#, whichever happens later. All data is latched

on the rising edge of WE# or CE#, whichever

happens first. Refer to the appropriate timing dia-

grams in the “AC Characteristics” section.

The reset command may be written between the

sequence cycles in a program command sequence

before programming begins. This resets the device to

reading array data (also applies to programming in

Erase Suspend mode). Once programming begins,

however, the device ignores reset commands until the

operation is complete.

Reading Array Data

The device is automatically set to reading array data

after device power-up. No commands are required to

retrieve data. The device is also ready to read array

data after completing an Embedded Program or

Embedded Erase algorithm.

The reset command may be written between the

sequence cycles in an autoselect command sequence.

Once in the autoselect mode, the reset command

must be written to return to reading array data (also

applies to autoselect during Erase Suspend).

After the device accepts an Erase Suspend command,

the device enters the Erase Suspend mode. The

system can read array data using the standard read

timings, except that if it reads at an address within

erase-suspended sectors, the device outputs status

data. After completing a programming operation in

the Erase Suspend mode, the system may once again

read array data with the same exception. See “Erase

Suspend/Erase Resume Commands” for more infor-

mation on this mode.

If DQ5 goes high during a program or erase opera-

tion, writing the reset command returns the device to

reading array data (also applies during Erase Sus-

pend).

Autoselect Command Sequence

The system must issue the reset command to re-

enable the device for reading array data if DQ5 goes

high, or while in the autoselect mode. See the “Reset

Command” section, next.

The autoselect command sequence allows the host

system to access the manufacturer and devices

codes, and determine whether or not a sector is pro-

tected. Table 1 shows the address and data require-

ments. This method is an alternative to that shown in

Table 4, which is intended for PROM programmers

See also “Requirements for Reading Array Data” in

the “Device Bus Operations” section for more infor-

mation. The Read Operations table provides the read

parameters, and Figure 13 shows the timing diagram.

and requires V on address bit A9.

ID

The autoselect command sequence is initiated by

writing two unlock cycles, followed by the autoselect

Am29LV800B

17

command. The device then enters the autoselect

mode, and the system may read at any address any

number of times, without initiating another command

sequence.

sequence is all that is required to program in this

mode. The first cycle in this sequence contains the

unlock bypass program command, A0h; the second

cycle contains the program address and data. Addi-

tional data is programmed in the same manner. This

mode dispenses with the initial two unlock cycles

required in the standard program command

sequence, resulting in faster total programming time.

Table 1 shows the requirements for the command

sequence.

A read cycle at address XX00h retrieves the manufac-

turer code. A read cycle at address XX01h in word

mode (or 02h in byte mode) returns the device code.

A read cycle containing a sector address (SA) and the

address 02h in word mode (or 04h in byte mode)

returns 01h if that sector is protected, or 00h if it is

unprotected. Refer to Tables 2 and 3 for valid sector

addresses.

During the unlock bypass mode, only the Unlock

Bypass Program and Unlock Bypass Reset commands

are valid. To exit the unlock bypass mode, the system

must issue the two-cycle unlock bypass reset

command sequence. The first cycle must contain the

data 90h; the second cycle the data 00h. Addresses

are don’t care for both cycles. The device then returns

to reading array data.

The system must write the reset command to exit the

autoselect mode and return to reading array data.

Word/Byte Program Command Sequence

The system may program the device by word or byte,

depending on the state of the BYTE# pin. Program-

ming is a four-bus-cycle operation. The program

command sequence is initiated by writing two unlock

write cycles, followed by the program set-up com-

mand. The program address and data are written

next, which in turn initiate the Embedded Program

algorithm. The system is not required to provide

further controls or timings. The device automatically

provides internally generated program pulses and

verifies the programmed cell margin. Table 1 shows

the address and data requirements for the byte

program command sequence.

Figure 3 illustrates the algorithm for the program

operation. See the Erase/Program Operations table in

“AC Characteristics” for parameters, and to Figure 17

for timing diagrams.

START

Write Program

When the Embedded Program algorithm is complete,

the device then returns to reading array data and

addresses are no longer latched. The system can

determine the status of the program operation by

using DQ7, DQ6, or RY/BY#. See “Write Operation

Status” for information on these status bits.

Command Sequence

Data Poll

from System

Embedded

Program

algorithm

in progress

Any commands written to the device during the

Embedded Program Algorithm are ignored. Note that

a hardware reset immediately terminates the pro-

gramming operation. The program command

sequence should be reinitiated once the device has

reset to reading array data, to ensure data integrity.

Verify Data?

No

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed

from a “0” back to a “1”. Attempting to do so may

halt the operation and set DQ5 to “1”, or cause the

Data# Polling algorithm to indicate the operation was

successful. However, a succeeding read will show that

the data is still “0”. Only erase operations can convert

a “0” to a “1”.

Yes

No

Increment Address

Last Address?

Yes

Programming

Completed

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to

program bytes or words to the device faster than

using the standard program command sequence. The

unlock bypass command sequence is initiated by first

writing two unlock cycles. This is followed by a third

write cycle containing the unlock bypass command,

20h. The device then enters the unlock bypass mode.

A two-cycle unlock bypass program command

Note: See Table 1 for program command sequence.

Figure 3. Program Operation

18

Am29LV800B

between additional sector erase commands can be

assumed to be less than 50 µs, the system need not

monitor DQ3. Any command other than Sector

Erase or Erase Suspend during the time-out

period resets the device to reading array data.

The system must rewrite the command sequence and

any additional sector addresses and commands.

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase

command sequence is initiated by writing two unlock

cycles, followed by a set-up command. Two additional

unlock write cycles are then followed by the chip

erase command, which in turn invokes the Embedded

Erase algorithm. The device does not require the

system to preprogram prior to erase. The Embedded

Erase algorithm automatically preprograms and veri-

fies the entire memory for an all zero data pattern

prior to electrical erase. The system is not required to

provide any controls or timings during these opera-

tions. Table 1 shows the address and data require-

ments for the chip erase command sequence.

The system can monitor DQ3 to determine if the

sector erase timer has timed out. (See the “DQ3:

Sector Erase Timer” section.) The time-out begins

from the rising edge of the final WE# pulse in the

command sequence.

Once the sector erase operation has begun, only the

Erase Suspend command is valid. All other com-

mands are ignored. Note that a hardware reset

during the sector erase operation immediately termi-

nates the operation. The Sector Erase command

sequence should be reinitiated once the device has

returned to reading array data, to ensure data integ-

rity.

Any commands written to the chip during the

Embedded Erase algorithm are ignored. Note that a

hardware reset during the chip erase operation

immediately terminates the operation. The Chip

Erase command sequence should be reinitiated once

the device has returned to reading array data, to

ensure data integrity.

When the Embedded Erase algorithm is complete, the

device returns to reading array data and addresses

are no longer latched. The system can determine the

status of the erase operation by using DQ7, DQ6,

DQ2, or RY/BY#. Refer to “Write Operation Status”

for information on these status bits.

The system can determine the status of the erase

operation by using DQ7, DQ6, DQ2, or RY/BY#. See

“Write Operation Status” for information on these

status bits. When the Embedded Erase algorithm is

complete, the device returns to reading array data

and addresses are no longer latched.

Figure 4 illustrates the algorithm for the erase opera-

tion. Refer to the Erase/Program Operations tables in

the “AC Characteristics” section for parameters, and

to Figure 18 for timing diagrams.

Figure 4 illustrates the algorithm for the erase opera-

tion. See the Erase/Program Operations tables in “AC

Characteristics” for parameters, and to Figure 18 for

timing diagrams.

Erase Suspend/Erase Resume Commands

Sector Erase Command Sequence

The Erase Suspend command allows the system to

interrupt a sector erase operation and then read data

from, or program data to, any sector not selected for

erasure. This command is valid only during the sector

erase operation, including the 50 µs time-out period

during the sector erase command sequence. The

Erase Suspend command is ignored if written during

the chip erase operation or Embedded Program algo-

rithm. Writing the Erase Suspend command during

the Sector Erase time-out immediately terminates

the time-out period and suspends the erase opera-

tion. Addresses are “don’t-cares” when writing the

Erase Suspend command.

Sector erase is a six bus cycle operation. The sector

erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two

additional unlock write cycles are then followed by the

address of the sector to be erased, and the sector

erase command. Table 1 shows the address and data

requirements for the sector erase command

sequence.

The device does not require the system to prepro-

gram the memory prior to erase. The Embedded

Erase algorithm automatically programs and verifies

the sector for an all zero data pattern prior to elec-

trical erase. The system is not required to provide any

controls or timings during these operations.

When the Erase Suspend command is written during

a sector erase operation, the device requires a

maximum of 20 µs to suspend the erase operation.

However, when the Erase Suspend command is

written during the sector erase time-out, the device

immediately terminates the time-out period and sus-

pends the erase operation.

After the command sequence is written, a sector

erase time-out of 50 µs begins. During the time-out

period, additional sector addresses and sector erase

commands may be written. Loading the sector erase

buffer may be done in any sequence, and the number

of sectors may be from one sector to all sectors. The

time between these additional cycles must be less

than 50 µs, otherwise the last address and command

might not be accepted, and erasure may begin. It is

recommended that processor interrupts be disabled

during this time to ensure all commands are

accepted. The interrupts can be re-enabled after the

last Sector Erase command is written. If the time

After the erase operation has been suspended, the

system can read array data from or program data to

any sector not selected for erasure. (The device

“erase suspends” all sectors selected for erasure.)

Normal read and write timings and command defini-

tions apply. Reading at any address within erase-sus-

pended sectors produces status data on DQ7–DQ0.

The system can use DQ7, or DQ6 and DQ2 together,

Am29LV800B

19

to determine if a sector is actively erasing or is erase-

suspended. See “Write Operation Status” for informa-

tion on these status bits.

START

After an erase-suspended program operation is com-

plete, the system can once again read array data

within non-suspended sectors. The system can deter-

mine the status of the program operation using the

DQ7 or DQ6 status bits, just as in the standard

program operation. See “Write Operation Status” for

more information.

Write Erase

Command Sequence

The system may also write the autoselect command

sequence when the device is in the Erase Suspend

mode. The device allows reading autoselect codes

even at addresses within erasing sectors, since the

codes are not stored in the memory array. When the

device exits the autoselect mode, the device reverts

to the Erase Suspend mode, and is ready for another

valid operation. See “Autoselect Command

Sequence” for more information.

Data Poll

from System

Embedded

Erase

algorithm

in progress

No

Data = FFh?

The system must write the Erase Resume command

(address bits are “don’t care”) to exit the erase

suspend mode and continue the sector erase opera-

tion. Further writes of the Resume command are

ignored. Another Erase Suspend command can be

written after the device has resumed erasing.

Yes

Erasure Completed

Notes:

1. See Table 1 for erase command sequence.

2. See “DQ3: Sector Erase Timer” for more information.

Figure 4. Erase Operation

20

Am29LV800B

Table 1. Am29LV800B Command Definitions

Bus Cycles (Notes 2-5)

First

Dat

Second

Dat

Third

Fourth

Fifth

Sixth

Dat

Command

Sequence

(Note 1)

Dat

a

Dat

a

Addr

a

Addr

a

Addr

Addr Data Addr

Addr

a

Read (Note 6)

Reset (Note 7)

1

RA

RD

F0

XXX

555

AAA

555

AAA

555

AAA

Word

Byte

Word

Byte

Word

Byte

2AA

555

2AA

555

2AA

555

AAA

555

AAA

555

AAA

Manufacturer ID

4

AA

55

90

X00

01

X01 22DA

X02 DA

X01 225B

Device ID,

Top Boot Block

Device ID,

Bottom Boot Block

X02

5B

XX00

XX01

00

(SA)

X02

Word

Byte

555

AAA

2AA

555

AAA

Sector Protect Verify

(Note 9)

4

AA

55

90

(SA)

X04

01

Word

Byte

Word

Byte

555

AAA

555

AAA

XXX

555

AAA

555

AAA

XXX

2AA

555

2AA

555

PA

555

AAA

555

AAA

Program

Unlock Bypass

4

3

AA

55

A0

20

PA

PD

Unlock Bypass Program (Note 10)

Unlock Bypass Reset (Note 11)

2

A0

90

PD

00

XXX

2AA

555

2AA

555

Word

555

AAA

555

AAA

555

AAA

555

AAA

2AA

555

2AA

555

AAA

Chip Erase

Byte

6

AA

55

80

AA

55

10

30

Word

Sector Erase

Byte

SA

Erase Suspend (Note 12)

Erase Resume (Note 13)

1

B0

30

Legend:

X = Don’t care

RA = Address of the memory location to be read.

RD = Data read from location RA during read operation.

PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse,

whichever happens later.

PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first.

SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A18–A12 uniquely select any sector.

Notes:

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

3. Except when reading array or autoselect data, all bus cycles are write operations.

4. Data bits DQ15–DQ8 are don’t cares for unlock and command cycles.

5. Address bits A18–A11 are don’t cares for unlock and command cycles, unless PA or SA required.

6. No unlock or command cycles required when reading array data.

7. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high

(while the device is providing status data).

8. The fourth cycle of the autoselect command sequence is a read cycle.

9. The data is 00h for an unprotected sector and 01h for a protected sector. See “Autoselect Command Sequence” for more

information.

10.The Unlock Bypass command is required prior to the Unlock Bypass Program command.

11.The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass

mode.

12.The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode.

The Erase Suspend command is valid only during a sector erase operation.

13.The Erase Resume command is valid only during the Erase Suspend mode.

Am29LV800B

21

WRITE OPERATION STATUS

The device provides several bits to determine the

status of a write operation: DQ2, DQ3, DQ5, DQ6,

DQ7, and RY/BY#. Table 2 and the following subsec-

tions describe the functions of these bits. DQ7,

RY/BY#, and DQ6 each offer a method for deter-

mining whether a program or erase operation is com-

plete or in progress. These three bits are discussed

first.

START

Read DQ7–DQ0

Addr = VA

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host

system whether an Embedded Algorithm is in

progress or completed, or whether the device is in

Erase Suspend. Data# Polling is valid after the rising

edge of the final WE# pulse in the program or erase

command sequence.

Yes

DQ7 = Data?

No

During the Embedded Program algorithm, the device

outputs on DQ7 the complement of the datum pro-

grammed to DQ7. This DQ7 status also applies to pro-

gramming during Erase Suspend. When the

Embedded Program algorithm is complete, the device

outputs the datum programmed to DQ7. The system

must provide the program address to read valid

status information on DQ7. If a program address falls

within a protected sector, Data# Polling on DQ7 is

active for approximately 1 µs, then the device returns

to reading array data.

No

DQ5 = 1?

Yes

Read DQ7–DQ0

Addr = VA

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase

algorithm is complete, or if the device enters the

Erase Suspend mode, Data# Polling produces a “1”

on DQ7. This is analogous to the complement/true

datum output described for the Embedded Program

algorithm: the erase function changes all the bits in a

sector to “1”; prior to this, the device outputs the

“complement,” or “0.” The system must provide an

address within any of the sectors selected for erasure

to read valid status information on DQ7.

Yes

DQ7 = Data?

No

PASS

FAIL

Notes:

After an erase command sequence is written, if all

sectors selected for erasing are protected, Data#

Polling on DQ7 is active for approximately 100 µs,

then the device returns to reading array data. If not

all selected sectors are protected, the Embedded

Erase algorithm erases the unprotected sectors, and

ignores the selected sectors that are protected.

1. VA = Valid address for programming. During a sector

erase operation, a valid address is an address within any

sector selected for erasure. During chip erase, a valid

address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

When the system detects DQ7 has changed from the

complement to true data, it can read valid data at

DQ7–DQ0 on the following read cycles. This is

because DQ7 may change asynchronously with DQ0–

DQ6 while Output Enable (OE#) is asserted low.

Figure 19, Data# Polling Timings (During

Embedded Algorithms), in the “AC Characteristics”

section illustrates this.

Figure 5. Data# Polling Algorithm

RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output pin

that indicates whether an Embedded Algorithm is in

progress or complete. The RY/BY# status is valid

after the rising edge of the final WE# pulse in the

command sequence. Since RY/BY# is an open-drain

output, several RY/BY# pins can be tied together in

Table 2 shows the outputs for Data# Polling on DQ7.

Figure 5 shows the Data# Polling algorithm.

parallel with a pull-up resistor to V

.

CC

22

Am29LV800B

If the output is low (Busy), the device is actively

erasing or programming. (This includes programming

in the Erase Suspend mode.) If the output is high

(Ready), the device is ready to read array data

(including during the Erase Suspend mode), or is in

the standby mode.

Toggle Bit II is valid after the rising edge of the final

WE# pulse in the command sequence.

DQ2 toggles when the system reads at addresses

within those sectors that have been selected for era-

sure. (The system may use either OE# or CE# to

control the read cycles.) But DQ2 cannot distinguish

whether the sector is actively erasing or is erase-sus-

pended. DQ6, by comparison, indicates whether the

device is actively erasing, or is in Erase Suspend, but

cannot distinguish which sectors are selected for era-

sure. Thus, both status bits are required for sector

and mode information. Refer to Table 2 to compare

outputs for DQ2 and DQ6.

Table 2 shows the outputs for RY/BY#. Figures 13, 14,

17 and 18 shows RY/BY# for read, reset, program,

and erase operations, respectively.

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded

Program or Erase algorithm is in progress or com-

plete, or whether the device has entered the Erase

Suspend mode. Toggle Bit I may be read at any

address, and is valid after the rising edge of the final

WE# pulse in the command sequence (prior to the

program or erase operation), and during the sector

erase time-out.

Figure 6 shows the toggle bit algorithm in flowchart

form, and the section “DQ2: Toggle Bit II” explains

the algorithm. See also the “DQ6: Toggle Bit I” sub-

section. Figure 20 shows the toggle bit timing dia-

gram. Figure 21 shows the differences between DQ2

and DQ6 in graphical form.

During an Embedded Program or Erase algorithm

operation, successive read cycles to any address

cause DQ6 to toggle. (The system may use either

OE# or CE# to control the read cycles.) When the

operation is complete, DQ6 stops toggling.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 6 for the following discussion. When-

ever the system initially begins reading toggle bit

status, it must read DQ7–DQ0 at least twice in a row

to determine whether a toggle bit is toggling. Typi-

cally, the system would note and store the value of

the toggle bit after the first read. After the second

read, the system would compare the new value of the

toggle bit with the first. If the toggle bit is not tog-

gling, the device has completed the program or erase

operation. The system can read array data on DQ7–

DQ0 on the following read cycle.

After an erase command sequence is written, if all

sectors selected for erasing are protected, DQ6

toggles for approximately 100 µs, then returns to

reading array data. If not all selected sectors are pro-

tected, the Embedded Erase algorithm erases the

unprotected sectors, and ignores the selected sectors

that are protected.

The system can use DQ6 and DQ2 together to deter-

mine whether a sector is actively erasing or is erase-

suspended. When the device is actively erasing (that

is, the Embedded Erase algorithm is in progress),

DQ6 toggles. When the device enters the Erase

Suspend mode, DQ6 stops toggling. However, the

system must also use DQ2 to determine which

sectors are erasing or erase-suspended. Alterna-

tively, the system can use DQ7 (see the subsection on

“DQ7: Data# Polling”).

However, if after the initial two read cycles, the

system determines that the toggle bit is still toggling,

the system also should note whether the value of DQ5

is high (see the section on DQ5). If it is, the system

should then determine again whether the toggle bit is

toggling, since the toggle bit may have stopped tog-

gling just as DQ5 went high. If the toggle bit is no

longer toggling, the device has successfully com-

pleted the program or erase operation. If it is still tog-

gling, the device did not completed the operation

successfully, and the system must write the reset

command to return to reading array data.

If a program address falls within a protected sector,

DQ6 toggles for approximately 1 µs after the program

command sequence is written, then returns to

reading array data.

The remaining scenario is that the system initially

determines that the toggle bit is toggling and DQ5

has not gone high. The system may continue to

monitor the toggle bit and DQ5 through successive

read cycles, determining the status as described in

the previous paragraph. Alternatively, it may choose

to perform other system tasks. In this case, the

system must start at the beginning of the algorithm

when it returns to determine the status of the opera-

tion (top of Figure 6).

DQ6 also toggles during the erase-suspend-program

mode, and stops toggling once the Embedded

Program algorithm is complete.

Table 2 shows the outputs for Toggle Bit I on DQ6.

Figure 6 shows the toggle bit algorithm. Figure 20 in

the “AC Characteristics” section shows the toggle bit

timing diagrams. Figure 21 shows the differences

between DQ2 and DQ6 in graphical form. See also the

subsection on “DQ2: Toggle Bit II”.

DQ5: Exceeded Timing Limits

DQ2: Toggle Bit II

DQ5 indicates whether the program or erase time has

exceeded a specified internal pulse count limit. Under

these conditions DQ5 produces a “1.” This is a failure

condition that indicates the program or erase cycle

was not successfully completed.

The “Toggle Bit II” on DQ2, when used with DQ6, indi-

cates whether a particular sector is actively erasing

(that is, the Embedded Erase algorithm is in

progress), or whether that sector is erase-suspended.

Am29LV800B

23

The DQ5 failure condition may appear if the system

tries to program a “1” to a location that is previously

programmed to “0.” Only an erase operation can

change a “0” back to a “1.” Under this condition,

the device halts the operation, and when the opera-

tion has exceeded the timing limits, DQ5 produces a

“1.”

START

Read DQ7–DQ0

Under both these conditions, the system must issue

the reset command to return the device to reading

array data.

(Note

Read DQ7–DQ0

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the

system may read DQ3 to determine whether or not

an erase operation has begun. (The sector erase

timer does not apply to the chip erase command.) If

additional sectors are selected for erasure, the entire

time-out also applies after each additional sector

erase command. When the time-out is complete, DQ3

switches from “0” to “1.” The system may ignore DQ3

if the system can guarantee that the time between

additional sector erase commands will always be less

than 50 µs. See also the “Sector Erase Command

Sequence” section.

No

Toggle Bit

= Toggle?

Yes

No

DQ5 = 1?

Yes

After the sector erase command sequence is written,

the system should read the status on DQ7 (Data#

Polling) or DQ6 (Toggle Bit I) to ensure the device has

accepted the command sequence, and then read

DQ3. If DQ3 is “1”, the internally controlled erase

cycle has begun; all further commands (other than

Erase Suspend) are ignored until the erase operation

is complete. If DQ3 is “0”, the device will accept addi-

tional sector erase commands. To ensure the

command has been accepted, the system software

should check the status of DQ3 prior to and following

each subsequent sector erase command. If DQ3 is

high on the second status check, the last command

might not have been accepted. Table 2 shows the

outputs for DQ3.

Read DQ7–DQ0

Twice

(Notes

1, 2)

Toggle Bit

= Toggle?

No

Yes

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Notes:

1. Read toggle bit twice to determine whether or not it is

toggling. See text.

2. Recheck toggle bit because it may stop toggling as DQ5

changes to “1”. See text.

Figure 6. Toggle Bit Algorithm

24

Am29LV800B

Table 2. Write Operation Status

DQ7

DQ5

DQ2

Operation

(Note 2)

DQ6

(Note 1)

DQ3

N/A

1

(Note 2)

RY/BY#

Embedded Program Algorithm

Embedded Erase Algorithm

DQ7#

0

Toggle

0

No toggle

Toggle

0

Standard

Mode

Reading within Erase

Suspended Sector

1

No toggle

0

N/A

Toggle

1

Erase

Suspend

Mode

Reading within Non-Erase

Suspended Sector

Data

0

Data

N/A

Data

N/A

1

0

Erase-Suspend-Program

DQ7#

Toggle

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

See “DQ5: Exceeded Timing Limits” for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further de-

tails.

Am29LV800B

25

Voltage with Respect to Ground

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages. . . . . . . . . . . . . .–65°C to +150°C

. . . . . . . . . . . . . . . .V (Note 1)–0.5 V to +4.0 V

CC

. . . . . . . . . . . . . . . . . . . . . . . . . . . A9, OE#, and

RESET# (Note 2) . . . . . . . . . . . .–0.5 V to +12.5 V

Ambient Temperature

with Power Applied. . . . . . . . . . . .–65°C to +125°C

. . . . . . All other pins (Note 1)–0.5 V to V +0.5 V

CC

Output Short Circuit Current (Note 3). . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may undershoot V_SSto –

2.0 V for periods of up to 20 ns. See Figure 7. Maximum DC voltage on input or I/O pins is V_CC+0.5 V. During voltage

transitions, input or I/O pins may overshoot to V_CC+2.0 V for periods up to 20 ns. See Figure 8.

2. Minimum DC input voltage on pins A9, OE#, and RESET# is –0.5 V. During voltage transitions, A9, OE#, and RESET# may

undershoot V_SSto –2.0 V for periods of up to 20 ns. See Figure 7. Maximum DC input voltage on pin A9 is +12.5 V which

may overshoot to 14.0 V for periods up to 20 ns.

3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one

second.

Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections

of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may

affect device reliability.

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (T ). . . . . . . . . 0°C to +70°C

A

Industrial (I) Devices

Ambient Temperature (T ). . . . . . . –40°C to +85°C

A

Extended (E) Devices

Ambient Temperature (T ). . . . . . –55°C to +125°C

A

V

Supply Voltages

CC

V

for regulated voltage range . . +3.0 V to +3.6 V

for full voltage range . . . . . . +2.7 V to +3.6 V

CC

Operating ranges define those limits between which the

functionality of the device is guaranteed.

20 ns

+0.8 V

V_CC

+2.0 V

–0.5 V

–2.0 V

V_CC

+0.5 V

2.0 V

20 ns

Figure 7. Maximum Negative Overshoot

Waveform

Figure 8. Maximum Positive Overshoot

Waveform

26

Am29LV800B

DC CHARACTERISTICS

CMOS Compatible

Parameter

Description

Test Conditions

V_IN= V_SSto V_CC

Min

Typ

Max

±1.0

35

Unit

µA

,

I_LI

I_LIT

I_LO

Input Load Current

V_CC= V_{CC max}

A9 Input Load Current

Output Leakage Current

V_CC= V_{CC max}; A9 = 12.5 V

µA

V_OUT= V_SSto V_CC

V_CC= V_{CC max}

,

±1.0

µA

5 MHz

1 MHz

5 MHz

1 MHz

7

2

7

2

12

4

CE# = V_IL,OE# ₌V_IH,

Byte Mode

V_CCActive Read Current

(Notes 1, 2)

I_CC1

mA

12

4

CE# = V_IL,OE# ₌V_IH,

Word Mode

V_CCActive Write Current

(Notes 2, 3, 5)

I_CC2

CE# = V_IL,OE# ₌V_IH

15

30

I_CC3

I_CC4

V_CCStandby Current (Note 2)

V_CCReset Current (Note 2)

CE#, RESET# = V_CC±0.3 V

RESET# = V_SS± 0.3 V

0.2

5

µA

Automatic Sleep Mode

(Notes 2, 4)

V_IH= V_CC± 0.3 V;

V_IL= V_SS± 0.3 V

I_CC5

0.2

5

µA

V_IL

Input Low Voltage

Input High Voltage

–0.5

0.8

V

V_IH

0.7 x V_CC

V_CC+ 0.3

Voltage for Autoselect and

Temporary Sector Unprotect

V_ID

V_CC= 3.3 V

11.5

12.5

0.45

V

V_OL

Output Low Voltage

I_OL= 4.0 mA, V_CC= V_{CC min}

I_OH= –2.0 mA, V_CC= V_{CC min}

I_OH= –100 µA, V_CC= V_{CC min}

V

V_OH1

V_OH2

0.85 V_CC

V_CC–0.4

Output High Voltage

Low V_CCLock-Out Voltage (Note

4)

V_LKO

2.3

2.5

V

Notes:

1. The I_CCcurrent listed is typically less than 2 mA/MHz, with OE# at V_IH. Typical V_CCis 3.0 V.

2. Maximum I_CCspecifications are tested with V_CC= V_CCmax

.

3. I_CCactive while Embedded Erase or Embedded Program is in progress.

4. Automatic sleep mode enables the low power mode when addresses remain stable for t_ACC+ 30 ns.

5. Not 100% tested.

Am29LV800B

27

DC CHARACTERISTICS (Continued)

Zero Power Flash

20

15

10

5

0

500

1000

1500

2000

2500

3000

3500

4000

Time in ns

Note: Addresses are switching at 1 MHz

Figure 9.

I

Current vs. Time (Showing Active and Automatic Sleep Currents)

CC1

10

8

3.6 V

2.7 V

6

4

2

0

1

2

3

4

5

Frequency in MHz

Note: T = 25 °C

Figure 10. Typical I

vs. Frequency

CC1

28

Am29LV800B

TEST CONDITIONS

Table 3. Test Specifications

-90,

3.3

Test Condition

-70

-120

Unit

2.7 kΩ

Output Load

1 TTL gate

Device

Under

Test

Output Load Capacitance, C_L

(including jig capacitance)

30

100

pF

C

L

6.2 kΩ

Input Rise and Fall Times

Input Pulse Levels

5

0.0–3.0

ns

V

Input timing measurement

reference levels

1.5

V

Output timing measurement

reference levels

Note: Diodes are IN3064 or equivalent

Figure 11. Test Setup

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Center Line is High Impedance State (High Z)

3.0 V

1.5 V

Input

Measurement Level

Output

0.0 V

Figure 12. Input Waveforms and

Measurement Levels

Am29LV800B

29

AC CHARACTERISTICS

Read Operations

Parameter

Speed Options

JEDEC

Std

Description

Read Cycle Time (Note 1)

Test Setup

Min

-70

-90

-120 Unit

t_AVAV

t_RC

70

90

120

ns

CE# = V_IL

OE# = V_IL

t_AVQV

t_ACC

Address to Output Delay

Max

90

t_ELQV

t_GLQV

t_EHQZ

t_GHQZ

t_CE

t_OE

t_DF

Chip Enable to Output Delay

OE# = V_IL

Max

Min

70

30

25

90

35

30

0

120

50

ns

Output Enable to Output Delay

Chip Enable to Output High Z (Note 1)

Output Enable to Output High Z (Note 1)

30

Read

Output Enable

Hold Time (Note 1)

t_OEH

Toggle and

Data# Polling

Min

10

0

ns

Output Hold Time From Addresses, CE# or OE#,

Whichever Occurs First (Note 1)

t_AXQX

t_OH

Notes:

1. Not 100% tested.

2. See Figure 11 and Table 3 for test specifications.

t

RC

Addresses Stable

ACC

Addresses

CE#

t

D

t

O

OE#

t

OEH

WE

t

CE

t

O

HIGH Z

Output Valid

Outputs

RESET#

RY/BY#

0 V

Figure 13. Read Operations Timings

30

Am29LV800B

AC CHARACTERISTICS

Hardware Reset (RESET#)

Parameter

JEDEC

Std

Description

Test Setup

Max

All Speed Options

Unit

RESET# Pin Low (During Embedded

Algorithms) to Read or Write (See Note)

t_READY

20

µs

RESET# Pin Low (NOT During Embedded

Algorithms) to Read or Write (See Note)

t_READY

Max

500

ns

t_RP

t_RH

t_RPD

t_RB

RESET# Pulse Width

Min

500

50

20

0

ns

µs

ns

RESET# High Time Before Read (See Note)

RESET# Low to Standby Mode

RY/BY# Recovery Time

Note: Not 100% tested.

RY/BY#

CE#, OE#

RESET#

t

RH

t

RP

t

Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

t

Ready

RY/BY#

t

RB

CE#, OE#

RESET#

t

RP

Figure 14. RESET# Timings

Am29LV800B

31

AC CHARACTERISTICS

Word/Byte Configuration (BYTE#)

Parameter

Speed Options

JEDEC

Std

t_{ELFL/ ELFH}

t_FLQZ

t_FHQV

Description

-70

-90

5

-120

Unit

ns

t

CE# to BYTE# Switching Low or High

BYTE# Switching Low to Output HIGH Z

BYTE# Switching High to Output Active

Max

Min

25

70

30

90

30

ns

120

ns

CE#

OE#

BYTE#

t_ELFL

Data Output

(DQ0–DQ14)

Data

Output

BYTE#

Switching

from word

to byte

DQ0–DQ14

mode

Address

Input

DQ15

Output

DQ15/A-1

t_FLQZ

t_ELFH

BYTE#

Switching

from byte

to word

Data

Data Output

DQ0–DQ14

DQ15/A-1

Output

(DQ0–DQ14)

mode

Address

Input

DQ15

Output

t_FHQ

V

Figure 15. BYTE# Timings for Read Operations

CE#

The falling edge of the last WE# signal

WE#

BYTE#

t_SET

(t_AS

)

t_HOLD(t_AH

)

Note: Refer to the Erase/Program Operations table for t_ASand t_AHspecifications.

Figure 16. BYTE# Timings for Write Operations

Am29LV800B

32

AC CHARACTERISTICS

Erase/Program Operations

Parameter

Speed Options

JEDEC

t_AVAV

Std

t_WC

t_AS

Description

Write Cycle Time (Note 1)

-70

-90

90

0

-120

Unit

ns

Min

70

120

t_AVWL

t_WLAX

t_DVWH

t_WHDX

Address Setup Time

Address Hold Time

Data Setup Time

ns

t_AH

45

35

45

0

50

ns

t_DS

t_DH

t_OES

ns

Data Hold Time

ns

Output Enable Setup Time

0

ns

Read Recovery Time Before Write

(OE# High to WE# Low)

t_GHWL

Min

0

ns

t_ELWL

t_WHEH

t_WLWH

t_WHWL

t_CS

t_CH

CE# Setup Time

CE# Hold Time

Min

Typ

Min

0

ns

t_WP

Write Pulse Width

Write Pulse Width High

35

30

9

50

t_WPH

Byte

t_WHWH1

t_WHWH2

t_WHWH1Programming Operation (Note 2)

t_WHWH2Sector Erase Operation (Note 2)

µs

Word

11

0.7

50

0

sec

µs

ns

t_VCS

t_RB

V_CCSetup Time (Note 1)

Recovery Time from RY/BY#

Program/Erase Valid to RY/BY# Delay

t_BUSY

90

ns

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

Am29LV800B

33

AC CHARACTERISTICS

Program Command Sequence (last two cycles)

Read Status Data (last two cycles)

t

AS

t

WC

Addresses

555h

PA

t

AH

CE#

OE#

t

C

t

WHWH1

t

W

WE#

t

WPH

t

CS

t

D

t

D

PD

Statu

D

OUT

A0h

Data

t

RB

BUSY

RY/BY#

V

CC

t

VCS

Notes:

1. PA = program address, PD = program data, D_OUTis the true data at the program address.

2. Illustration shows device in word mode.

Figure 17. Program Operation Timings

34

Am29LV800B

AC CHARACTERISTICS

Erase Command Sequence (last two cycles)

Read Status Data

VA

t

AS

SA

555h for chip erase

WC

Addresses

CE#

2AAh

VA

t

A

t

C

OE#

t

W

WE#

t

WP

WHWH

t

CS

t

D

t

D

In

Data

30h

10 for Chip Erase

Complete

55h

Progress

t

RB

BUSY

RY/BY#

t

VC

V

CC

Notes:

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).

2. Illustration shows device in word mode.

Figure 18. Chip/Sector Erase Operation Timings

Am29LV800B

35

AC CHARACTERISTICS

t

RC

VA

dresses

VA

t

ACC

t

CE

CE#

t

CH

t

OE

OE#

WE#

t

OEH

DF

t

OH

High

DQ7

Valid Data

Complement

Compleme

Tru

Q0–DQ6

Valid Data

Status

Tru

Status

t

BUS

RY/BY#

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data

ead cycle.

Figure 19. Data# Polling Timings (During Embedded Algorithms)

t

RC

Addresses

CE#

VA

t

ACC

t

CE

t

CH

t

OE

OE#

WE#

t

DF

OEH

t

OH

High

DQ6/DQ2

RY/BY#

Valid

(second read)

Valid

(stops toggling)

Valid Data

(first read)

t

BUS

Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status

read cycle, and array data read cycle.

Figure 20. Toggle Bit Timings (During Embedded Algorithms)

36

Am29LV800B

AC CHARACTERISTICS

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

Erase

Erase Suspend

Read

Erase

Suspend

Program

Erase

Complete

WE#

Erase

Erase Suspend

Read

DQ6

DQ2

Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an

erase-suspended sector.

Figure 21. DQ2 vs. DQ6

Temporary Sector Unprotect

Parameter

JEDEC

Std

Description

All Speed Options

Unit

t_VIDR

V_IDRise and Fall Time (See Note)

Min

500

ns

RESET# Setup Time for Temporary Sector

Unprotect

t_RSP

4

µs

Note: Not 100% tested.

12 V

RESET#

0 or 3 V

t

VIDR

Program or Erase Command Sequence

CE#

WE#

t

RSP

RY/BY#

Figure 22. Temporary Sector Unprotect

Timing Diagram

Am29LV800B

37

AC CHARACTERISTICS

V

ID

IH

V

RESET#

SA, A6,

A1, A0

Valid*

Status

Sector Protect/Unprotect

Verify

40h

Data

60h

Sector Protect: 150 μs

Sector Unprotect: 15 ms

1 μs

CE#

WE#

OE#

* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.

Figure 23. Sector Protect/Unprotect

Timing Diagram

38

Am29LV800B

AC CHARACTERISTICS

Alternate CE# Controlled Erase/Program Operations

Parameter

Speed Options

JEDEC

t_AVAV

t_AVEL

Std

t_WC

t_AS

Description

Write Cycle Time (Note 1)

Address Setup Time

Address Hold Time

-70

-90

90

0

-120

Unit

ns

Min

70

120

ns

t_ELAX

t_AH

45

35

45

0

50

ns

t_DVEH

t_EHDX

t_DS

Data Setup Time

ns

t_DH

t_OES

Data Hold Time

ns

Output Enable Setup Time

0

ns

Read Recovery Time Before Write

(OE# High to WE# Low)

t_GHEL

Min

0

ns

t_WLEL

t_EHWH

t_ELEH

t_EHEL

t_WS

t_WH

t_CP

WE# Setup Time

WE# Hold Time

Min

Typ

0

ns

CE# Pulse Width

CE# Pulse Width High

35

30

9

50

t_CPH

Byte

Programming Operation

(Note 2)

t_WHWH1

t_WHWH2

µs

Word

11

0.7

t_WHWH2

Notes:

Sector Erase Operation (Note 2)

sec

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

Am29LV800B

39

AC CHARACTERISTICS

555 for programPA for program

2AA for erase SA for sector erase

555 for chip erase

Data# Polling

Addresses

PA

t

WC

AS

t

AH

t

WH

WE#

OE#

t

GHEL

t

WHWH1 or

t

CP

CE#

t

WS

CPH

t

BUS

t

D

t

D

D_OUT

DQ7

Data

t

R

A0 for programPD for program

55 for erase

30 for sector erase

10 for chip erase

RESET#

RY/BY#

Notes:

1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, D_OUT= data written

to the device.

2. Figure indicates the last two bus cycles of command sequence.

3. Word mode address used as an example.

Figure 24. Alternate CE# Controlled Write Operation Timings

40

Am29LV800B

ERASE AND PROGRAMMING PERFORMANCE

Typ (Note

Parameter

1)

0.7

14

9

Max (Note 2)

Unit

s

Comments

Sector Erase Time

Chip Erase Time

15

Excludes 00h programming

prior to erasure

s

Byte Programming Time

Word Programming Time

300

360

27

µs

s

11

9

Excludes system level

overhead (Note 5)

Byte Mode

Word Mode

Chip Programming Time

(Note 3)

5.8

17

s

Notes:

1. Typical program and erase times assume the following conditions: 25°C, 3.0 V V_CC, 1,000,000 cycles. Additionally,

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, V_CC= 2.7 V, 1,000,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See

Table 1 for further information on command definitions.

6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTICS

Description

Min

Max

Input voltage with respect to V_SSon all pins except I/O pins

(including A9, OE#, and RESET#)

–1.0 V

12.5 V

Input voltage with respect to V_SSon all I/O pins

V_CCCurrent

–1.0 V

V_CC+ 1.0 V

+100 mA

–100 mA

Includes all pins except V_CC. Test conditions: V_CC= 3.0 V,

one pin at a time.

TSOP AND SO PIN CAPACITANCE

Parameter

Symbol

Parameter Description

Input Capacitance

Test Setup

V_IN= 0

Typ

6

Max

7.5

12

Unit

pF

C_IN

C_OUT

C_IN2

Output Capacitance

V_OUT= 0

V_IN= 0

8.5

7.5

pF

Control Pin Capacitance

9

pF

Notes:

1. Sampled, not 100% tested.

2. Test conditions T_A= 25°C, f = 1.0 MHz.

DATA RETENTION

Parameter

Test Conditions

Min

10

Unit

Years

150°C

125°C

Minimum Pattern Data Retention Time

20

Am29LV800B

41

PHYSICAL DIMENSIONS*

TS 048—48-Pin Standard TSOP

Dwg rev AA; 10/99

* For reference only. BSC is an ANSI standard for Basic

Space Centering.

42

Am29LV800B

PHYSICAL DIMENSIONS

TSR048—48-Pin Reverse TSOP

Dwg rev AA; 10/99

* For reference only. BSC is an ANSI standard for Basic

Space Centering.

Am29LV800B

43

PHYSICAL DIMENSIONS

FBB 048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 6 x 9 mm

Dwg rev AF; 10/99

44

Am29LV800B

PHYSICAL DIMENSIONS

SO 044—44-Pin Small Outline Package

Dwg rev AC; 10/99

45

Am29LV800B

In Note 2, the worst case endurance is now 1 million

cycles.

REVISION SUMMARY

Revision E (January 1998)

Distinctive Characteristics

Revision F (January 1999)

Global

Changed typical read and program/erase current

specifications.

Changed references for process technology to “0.32

µm.”

Device now has a guaranteed minimum endurance of

1,000,000 write cycles.

Replaced the 70R ns regulated voltage speed option

with 70 ns full voltage speed option.

In-System Sector Protect/Unprotect

Algorithm Figure

Distinctive Characteristics

Added 20-year data retention bullet.

Corrected A6 to 0, Changed wait specification to 150

µs on sector protect and 15 ms on sector unprotect.

Connection Diagrams

DC Characteristics

Reverse TSOP: Modified markings.

Changed typical read and program/erase current

specifications.

FBGA: Replaced Bump side (bottom) view with top

view.

AC Characteristics

Ordering Information

Alternate CE# Controlled Erase/Program Operations:

Valid Combinations for FBGA Packages: New Table.

DC Characteristics—CMOS Compatible

Changed t

options.

to 35 ns for 70R, 80, and 90 speed

CP

I

, I

: Added Note 2 “Maximum

CC1 CC2 CC3 CC4 CC5

Erase and Programming Performance

I

specifications are tested with V = V

”.

CC

CCmax

Device now has a guaranteed minimum endurance of

1,000,000 write cycles.

I

, I

: Deleted V = V

.

CC3 CC4

CC

CCmax

Physical Dimensions

Changed package drawing to FBB048.

Corrected dimensions for package length and width in

FBGA illustration (standalone data sheet version).

Revision F+1 (February 1999)

Revision E+1 (March 1998)

Physical Dimensions

In-System Sector Protect/Unprotect

Algorithms Figure

Corrected ball grid layout on FBB048 drawing. Added

“048” to drawing title.

In the sector protect algorithm, added a “Reset

PLSCNT=1” box in the path from “Protect another

sector?” back to setting up the next sector address.

Revision F+2 (February 1999)

Distinctive Characteristics, Operating

Ranges

DC Characteristics

Corrected to indicate that the V

all devices is 2.7–3.6 V.

voltage range for

CC

Changed Note 1 to indicate that OE# is at V for the

IH

listed current.

Revision F+3 (July 2, 1999)

Global

AC Characteristics

Erase/Program Operations; Alternate CE# Controlled

Erase/Program Operations: Corrected the notes

Added references to availability of device in Known

Good Die (KGD) form.

reference for t

and t

. These parameters

WHWH1

WHWH2

are 100% tested. Corrected the note reference for

. This parameter is not 100% tested.

Revision F+4 (July 26, 1999)

Global

t

VCS

Temporary Sector Unprotect Table

Added the 70R speed option, which is available in the

extended temperature range.

Added note reference for t

100% tested.

. This parameter is not

VIDR

Ordering Information

Figure 23, Sector Protect/Unprotect

Timing Diagram

Deleted the extended temperature range from the

FBGA valid combinations.

A valid address is not required for the first write cycle;

only the data 60h.

Revision G (November 10, 1999)

Ordering Information

Erase and Programming Performance

Deleted commercial and industrial temperature

ranges from the 70R speed option.

Am29LV800B

46

AC Characteristics—Figure 17. Program

Operations Timing and Figure 18.

Chip/Sector Erase Operations

Revision G+3 (June 4, 2004)

Ordering Information

Added Lead-free (Pb-free) options to the Tempera-

ture range breakout of the OPN table and to the Valid

Combinations table.

Deleted t

high.

and changed OE# waveform to start at

GHWL

Physical Dimensions

Revision G+4 (January 20, 2005)

Added migration statement to cover page and first

page of data sheet.

Replaced figures with more detailed illustrations.

Revision G+1 (July 7, 2000)

Added Colophon.

Ordering Information

Updated Trademark

Inserted dashes into ordering part numbers. Deleted

burn-in option.

Revision G+5 (May 25, 2005)

Updated migration statement on cover page and first

page of data sheet.

Revision G+2 (August 14, 2000)

Global

Updated trademarks.

Deleted 70R and 80 ns speed options and burn-in

option.

Colophon

The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary

industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that

includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal

injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control,

medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and

artificial satellite). Please note that Spansion LLC will not be liable to you and/or any third party for any claims or damages arising in connection with above-

mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such

failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels

and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on

export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country,

the prior authorization by the respective government entity will be required for export of those products.

Trademarks

Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only

and may be trademarks of their respective companies

47

Am29LV800B


型号：	AM29LV800BT-90FE
厂家：	AMD
描述：	8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory 8兆位（ 1一M× 8位/ 512的K× 16位） CMOS 3.0伏只引导扇区闪存闪存
文件：	总49页 (文件大小：1659K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AM29LV800BT-90FE [AMD]

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