AM29LV800BT120WBEB_技术文档

PRELIMINARY

Am29LV800B

8 Megabit (1 M x 8-Bit/512 K x 16-Bit)

CMOS 3.0 Volt-only Boot Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

■ Single power supply operation

■ Unlock Bypass Program Command

— Full voltage range: 2.7 to 3.6 volt read and write

operations for battery-powered applications

— Reduces overall programming time when

issuing multiple program command sequences

— Regulated voltage range: 3.0 to 3.6 volt read

and write operations and for compatibility with

high performance 3.3 volt microprocessors

■ Top or bottom boot block configurations

available

■ Embedded Algorithms

■ Manufactured on 0.35 µm process technology

— Embedded Erase algorithm automatically

preprograms and erases the entire chip or any

combination of designated sectors

— Compatible with 0.5 µm Am29LV800 device

■ High performance

— Embedded Program algorithm automatically

writes and verifies data at specified addresses

— Full voltage range: access times as fast as 80 ns

— Regulated voltage range: access times as fast

as 70 ns

■ Minimum 1,000,000 write cycle guarantee per

sector

■ Ultra low power consumption (typical values at

■ Package option

— 48-ball FBGA

— 48-pin TSOP

— 44-pin SO

5 MHz)

— 200 nA Automatic Sleep mode current

— 200 nA standby mode current

— 7 mA read current

— 15 mA program/erase current

■ Compatibility with JEDEC standards

— Pinout and software compatible with single-

power supply Flash

■ Flexible sector architecture

— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and

fifteen 64 Kbyte sectors (byte mode)

— Superior inadvertent write protection

— One 8 Kword, two 4 Kword, one 16 Kword, and

fifteen 32 Kword sectors (word mode)

■ Data# Polling and toggle bits

— Provides a software method of detecting

program or erase operation completion

— Supports full chip erase

— Sector Protection features:

■ Ready/Busy# pin (RY/BY#)

A hardware method of locking a sector to

prevent any program or erase operations within

that sector

— Provides a hardware method of detecting

program or erase cycle completion

■ Erase Suspend/Erase Resume

Sectors can be locked in-system or via

programming equipment

— Suspends an erase operation to read data from,

or program data to, a sector that is not being

erased, then resumes the erase operation

Temporary Sector Unprotect feature allows code

changes in previously locked sectors

■ Hardware reset pin (RESET#)

— Hardware method to reset the device to reading

array data

This document contains information on a product under development at Advanced Micro Devices. The information

is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed

product without notice.

Publication# 21490 Rev: E Amendment/+1

Issue Date: March 1998

Refer to AMD’s Website (www.amd.com) for the latest information.

P R E L I M I N A R Y

GENERAL DESCRIPTION

The Am29LV800B is an 8 Mbit, 3.0 volt-only Flash

memory organized as 1,048,576 bytes or 524,288

words. The device is offered in 48-ball FBGA, 44-pin

SO, and 48-pin TSOP packages. The word-wide data

(x16) appears on DQ15–DQ0; the byte-wide (x8) data

appears on DQ7–DQ0. This device requires only a

single, 3.0 volt V_CCsupply to perform read, program,

and erase operations. A standard EPROM pro-

grammer can also be used to program and erase the

device.

grams the array (if it is not already programmed) before

executing the erase operation. During erase, the device

automatically times the erase pulse widths and verifies

proper cell margin.

The host system can detect whether a program or

erase operation is complete by observing the RY/BY#

pin, or by reading the DQ7 (Data# Polling) and DQ6

(toggle) status bits. After a program or erase cycle

has been completed, the device is ready to read array

data or accept another command.

This device is manufactured using AMD’s 0.35 µm

process technology, and offers all the features and

benefits of the Am29LV800, which was manufactured

using 0.5 µm process technology. In addition, the

Am29LV800B features unlock bypass programming

and in-system sector protection/unprotection.

The sector erase architecture allows memory sectors

to be erased and reprogrammed without affecting the

data contents of other sectors. The device is fully

erased when shipped from the factory.

Hardware data protection measures include a low

detector that automatically inhibits write opera-

V_CC

The standard device offers access times of 70, 80, 90

and 120 ns, allowing high speed microprocessors to

operate without wait states. To eliminate bus conten-

tion the device has separate chip enable (CE#), write

enable (WE#) and output enable (OE#) controls.

tions during power transitions. The hardware sector

protection feature disables both program and erase

operations in any combination of the sectors of mem-

ory. This can be achieved in-system or via program-

ming equipment.

The device requires only a single 3.0 volt power sup-

ply for both read and write functions. Internally gener-

ated and regulated voltages are provided for the

program and erase operations.

The Erase Suspend feature enables the user to put

erase on hold for any period of time to read data from,

or program data to, any sector that is not selected for

erasure. True background erase can thus be achieved.

The device is entirely command set compatible with the

JEDEC single-power-supply Flash standard. Com-

mands are written to the command register using

standard microprocessor write timings. Register con-

tents serve as input to an internal state-machine that

controls the erase and programming circuitry. Write

cycles also internally latch addresses and data needed

for the programming and erase operations. Reading

data out of the device is similar to reading from other

Flash or EPROM devices.

The hardware RESET# pin terminates any operation

in progress and resets the internal state machine to

reading array data. The RESET# pin may be tied to the

system reset circuitry. A system reset would thus also

reset the device, enabling the system microprocessor

to read the boot-up firmware from the Flash memory.

The device offers two power-saving features. When

addresses have been stable for a specified amount of

time, the device enters the automatic sleep mode.

The system can also place the device into the standby

mode. Power consumption is greatly reduced in both

these modes.

Device programming occurs by executing the program

command sequence. This initiates the Embedded

Program algorithm—an internal algorithm that auto-

matically times the program pulse widths and verifies

proper cell margin. The Unlock Bypass mode facili-

tates faster programming times by requiring only two

write cycles to program data instead of four.

AMD’s Flash technology combines years of Flash

memory manufacturing experience to produce the

highest levels of quality, reliability and cost effective-

ness. The device electrically erases all bits within

a sector simultaneously via Fowler-Nordheim tun-

neling. The data is programmed using hot electron

injection.

Device erasure occurs by executing the erase command

sequence. This initiates the Embedded Erase algo-

rithm—an internal algorithm that automatically prepro-

2

Am29LV800B

P R E L I M I N A R Y

PRODUCT SELECTOR GUIDE

Family Part Number

Am29LV800B

Regulated Voltage Range: V =3.0–3.6 V

70R

CC

Speed Options

Max access time, ns (t

Full Voltage Range: V = 2.7–3.6 V

80

90

35

120

50

CC

)

70

30

80

30

ACC

Max CE# access time, ns (t

)

CE

Max OE# access time, ns (t

)

OE

Note: See “AC Characteristics” for full specifications.

BLOCK DIAGRAM

DQ0–DQ15 (A-1)

RY/BY#

V

CC

Sector Switches

V

SS

Erase Voltage

Generator

Input/Output

Buffers

RESET#

State

Control

WE#

BYTE#

Command

Register

PGM Voltage

Generator

Data

Latch

Chip Enable

Output Enable

Logic

STB

CE#

OE#

Y-Decoder

Y-Gating

STB

V

Detector

Timer

CC

Cell Matrix

X-Decoder

A0–A18

21490E-1

Am29LV800B

3

P R E L I M I N A R Y

CONNECTION DIAGRAMS

A15

A14

A13

A12

A11

A10

A9

A8

NC

1

2

3

4

5

6

7

8

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A16

BYTE#

V_SS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

DQ12

DQ4

V_CC

WE#

RESET#

NC

Standard TSOP

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

V_SS

CE#

A0

NC

RY/BY#

A18

A17

A7

A6

A5

A4

A3

A2

A1

1

2

3

4

5

6

7

8

A15

A14

A13

A12

A11

A10

A9

A8

NC

48

A16

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

BYTE#

V_SS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

V_CC

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

WE#

RESET#

NC

Reverse TSOP

NC

RY/BY#

A18

A17

A7

A6

A5

A4

A3

A2

A1

OE#

V_SS

CE#

A0

21490E-2

4

Am29LV800B

P R E L I M I N A R Y

CONNECTION DIAGRAMS

RY/BY#

A18

A17

A7

1

2

3

4

5

6

7

8

9

44 RESET#

43 WE#

42 A8

41 A9

A6

40 A10

A5

39 A11

A4

38 A12

A3

37 A13

A2

36 A14

A1 10

A0 11

CE# 12

V_SS13

35 A15

34 A16

SO

33 BYTE#

32 V_SS

OE# 14

DQ0 15

DQ8 16

DQ1 17

DQ9 18

DQ2 19

DQ10 20

DQ3 21

DQ11 22

31 DQ15/A-1

30 DQ7

29 DQ14

28 DQ6

27 DQ13

26 DQ5

25 DQ12

24 DQ4

23 V_CC

FBGA

Bump Side (Bottom) View

A1

A3

B1

A4

C1

A2

D1

A1

E1

A0

F1

G1

H1

CE#

OE#

V_SS

A2

A7

B2

C2

A6

D2

A5

E2

F2

G2

H2

A17

DQ0

DQ8

DQ9

DQ1

A3

B3

C3

D3

E3

F3

G3

H3

RY/BY#

NC

A18

NC

DQ2

DQ10

DQ11

DQ3

A4

B4

C4

D4

E4

F4

G4

H4

WE# RESET#

NC

DQ5

DQ12

V_CC

DQ4

A5

A9

B5

A8

C5

D5

E5

F5

G5

H5

A10

A11

DQ7

DQ14

DQ13

DQ6

A6

B6

C6

D6

E6

F6

G6

H6

A13

A12

A14

A15

A16

BYTE# DQ15/A-1 V_SS

21490E-3

Am29LV800B

5

P R E L I M I N A R Y

Flash memory devices in FBGA packages may be

Special Handling Instructions for FBGA

Package

damaged if exposed to ultrasonic cleaning methods.

The package and/or data integrity may be

compromised if the package body is exposed to

temperatures above 150°C for prolonged periods of

time.

Special handling is required for Flash Memory products

in FBGA packages.

PIN CONFIGURATION

LOGIC SYMBOL

A0–A18

= 19 addresses

19

DQ0–DQ14 = 15 data inputs/outputs

A0–A18

16 or 8

DQ15/A-1

=

DQ15 (data input/output, word mode),

A-1 (LSB address input, byte mode)

DQ0–DQ15

(A-1)

BYTE#

CE#

=

Selects 8-bit or 16-bit mode

Chip enable

CE#

OE#

Output enable

WE#

Write enable

RESET#

BYTE#

RESET#

RY/BY#

V_CC

Hardware reset pin, active low

Ready/Busy# output

RY/BY#

3.0 volt-only single power supply

(see Product Selector Guide for speed

options and voltage supply tolerances)

21490E-4

V_SS

NC

=

Device ground

Pin not connected internally

6

Am29LV800B

P R E L I M I N A R Y

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combi-

nation) is formed by a combination of the elements below.

Am29LV800B

T

70R

E

C

OPTIONAL PROCESSING

Blank = Standard Processing

B = Burn-in

(Contact an AMD representative for more information)

TEMPERATURE RANGE

C = Commercial (0°C to +70°C)

I = Industrial (–40°C to +85°C)

E = Extended (–55°C to +125°C)

PACKAGE TYPE

E

F

S

=

48-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 048)

48-Pin Thin Small Outline Package (TSOP)

Reverse Pinout (TSR048)

44-Pin Small Outline Package (SO 044)

WB = 48-ball Fine Pitch Ball Grid Array (FBGA)

0.80 mm pitch, 6 x 9 mm package

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T = Top Sector

B = Bottom Sector

DEVICE NUMBER/DESCRIPTION

Am29LV800B

8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS Flash Memory

3.0 Volt-only Read, Program, and Erase

Valid Combinations

Valid Combinations list configurations planned to be sup-

Am29LV800BT70R,

Am29LV800BB70R

ported in volume for this device. Consult the local AMD sales

office to confirm availability of specific valid combinations and

to check on newly released combinations.

EC, EI, FC, FI, SC, SI, WBC

Am29LV800BT80,

Am29LV800BB80

EC, EI, EE,

FC, FI, FE,

SC, SI, SE,

Am29LV800BT90,

Am29LV800BB90

WBC, WBI, WBE

Am29LV800BT120,

Am29LV800BB120

Am29LV800B

7

P R E L I M I N A R Y

DEVICE BUS OPERATIONS

This section describes the requirements and use of the

device bus operations, which are initiated through the

internal command register. The command register itself

does not occupy any addressable memory location.

The register is composed of latches that store the com-

mands, along with the address and data information

needed to execute the command. The contents of the

register serve as inputs to the internal state machine.

The state machine outputs dictate the function of the

device. Table 1 lists the device bus operations, the

inputs and control levels they require, and the resulting

output. The following subsections describe each of

these operations in further detail.

Table 1. Am29LV800B Device Bus Operations

DQ8–DQ15

BYTE#

= V

Addresses

(Note 1)

DQ0– BYTE#

Operation

CE# OE# WE# RESET#

DQ7

= V

IH

IL

Read

L

H

A

D

DQ8–DQ14 = High-Z,

DQ15 = A-1

IN

OUT

Write

L

H

L

H

A

D

IN

V

0.3 V

±

V

0.3 V

±

CC

Standby

X

High-Z High-Z

High-Z

Output Disable

Reset

L

H

X

H

X

H

L

X

High-Z High-Z

High-Z

X

Sector Address,

A6 = L, A1 = H,

A0 = L

Sector Protect (Note 2)

L

H

L

V

D

X

ID

IN

Sector Address,

A6 = H, A1 = H,

A0 = L

Sector Unprotect (Note 2)

L

H

X

L

V

D

X

ID

IN

Temporary Sector Unprotect

X

A

D

High-Z

IN

Legend:

L = Logic Low = V , H = Logic High = V , V = 12.0 ± 0.5 V, X = Don’t Care, A = Address In, D = Data In, D = Data Out

IL

IH

ID

IN

OUT

Notes:

1. Addresses are A18:A0 in word mode (BYTE# = V ), A18:A-1 in byte mode (BYTE# = V ).

IH

IL

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector

Protection/Unprotection” section.

should remain at V_IH. The BYTE# pin determines

whether the device outputs array data in words or

Word/Byte Configuration

The BYTE# pin controls whether the device data I/O

bytes.

pins DQ15–DQ0 operate in the byte or word configura-

tion. If the BYTE# pin is set at logic ‘1’, the device is in

word configuration, DQ15–DQ0 are active and control-

led by CE# and OE#.

The internal state machine is set for reading array

data upon device power-up, or after a hardware reset.

This ensures that no spurious alteration of the mem-

ory content occurs during the power transition. No

command is necessary in this mode to obtain array

data. Standard microprocessor read cycles that as-

sert valid addresses on the device address inputs pro-

duce valid data on the device data outputs. The

device remains enabled for read access until the com-

mand register contents are altered.

If the BYTE# pin is set at logic ‘0’, the device is in byte

configuration, and only data I/O pins DQ0–DQ7 are ac-

tive and controlled by CE# and OE#. The data I/O pins

DQ8–DQ14 are tri-stated, and the DQ15 pin is used as

an input for the LSB (A-1) address function.

Requirements for Reading Array Data

See “Reading Array Data” for more information. Refer

to the AC Read Operations table for timing specifica-

tions and to Figure 13 for the timing diagram. I_CC1in

the DC Characteristics table represents the active cur-

rent specification for reading array data.

To read array data from the outputs, the system must

drive the CE# and OE# pins to V_IL. CE# is the power

control and selects the device. OE# is the output con-

trol and gates array data to the output pins. WE#

8

Am29LV800B

P R E L I M I N A R Y

the standby current will be greater. The device requires

Writing Commands/Command Sequences

standard access time (t_CE) for read access when the

device is in either of these standby modes, before it is

ready to read data.

To write a command or command sequence (which in-

cludes programming data to the device and erasing

sectors of memory), the system must drive WE# and

CE# to V_IL, and OE# to V_IH.

If the device is deselected during erasure or program-

ming, the device draws active current until the

operation is completed.

For program operations, the BYTE# pin determines

whether the device accepts program data in bytes or

words. Refer to “Word/Byte Configuration” for more

information.

In the DC Characteristics table, I_CC3and I_CC4repre-

sents the standby current specification.

The device features an Unlock Bypass mode to facili-

tate faster programming. Once the device enters the Un-

lock Bypass mode, only two write cycles are required to

program a word or byte, instead of four. The “Word/Byte

Program Command Sequence” section has details on

programming data to the device using both standard and

Unlock Bypass command sequences.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device

energy consumption. The device automatically

enables this mode when addresses remain stable for

t_ACC+ 30 ns. The automatic sleep mode is

independent of the CE#, WE#, and OE# control

signals. Standard address access timings provide new

data when addresses are changed. While in sleep

mode, output data is latched and always available to

the system. I_CC4in the DC Characteristics table

represents the automatic sleep mode current

specification.

An erase operation can erase one sector, multiple sec-

tors, or the entire device. Tables 2 and 3 indicate the

address space that each sector occupies. A “sector ad-

dress” consists of the address bits required to uniquely

select a sector. The “Command Definitions” section

has details on erasing a sector or the entire chip, or

suspending/resuming the erase operation.

RESET#: Hardware Reset Pin

After the system writes the autoselect command se-

quence, the device enters the autoselect mode. The

system can then read autoselect codes from the inter-

nal register (which is separate from the memory array)

on DQ7–DQ0. Standard read cycle timings apply in this

mode. Refer to the “Autoselect Mode” and “Autoselect

Command Sequence” sections for more information.

The RESET# pin provides a hardware method of reset-

ting the device to reading array data. When the RE-

SET# pin is driven low for at least a period of t_RP, the

device immediately terminates any operation in

progress, tristates all output pins, and ignores all

read/write commands for the duration of the RESET#

pulse. The device also resets the internal state ma-

chine to reading array data. The operation that was in-

terrupted should be reinitiated once the device is ready

to accept another command sequence, to ensure data

integrity.

I_CC2in the DC Characteristics table represents the ac-

tive current specification for the write mode. The “AC

Characteristics” section contains timing specification

tables and timing diagrams for write operations.

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at V_SS±0.3 V, the device

draws CMOS standby current (I_CC4). If RESET# is held

at V_ILbut not within V_SS±0.3 V, the standby current will

be greater.

Program and Erase Operation Status

During an erase or program operation, the system may

check the status of the operation by reading the status

bits on DQ7–DQ0. Standard read cycle timings and I_CC

read specifications apply. Refer to “Write Operation

Status” for more information, and to “AC Characteris-

tics” for timing diagrams.

The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash

memory, enabling the system to read the boot-up

firmware from the Flash memory.

Standby Mode

If RESET# is asserted during a program or erase op-

eration, the RY/BY# pin remains a “0” (busy) until the

internal reset operation is complete, which requires a

time of t_READY(during Embedded Algorithms). The

system can thus monitor RY/BY# to determine

whether the reset operation is complete. If RESET# is

asserted when a program or erase operation is not ex-

ecuting (RY/BY# pin is “1”), the reset operation is

completed within a time of t_READY(not during Embed-

ded Algorithms). The system can read data t_RHafter

the RESET# pin returns to V_IH.

When the system is not reading or writing to the device,

it can place the device in the standby mode. In this

mode, current consumption is greatly reduced, and the

outputs are placed in the high impedance state, inde-

pendent of the OE# input.

The device enters the CMOS standby mode when the

CE# and RESET# pins are both held at V_CC± 0.3 V.

(Note that this is a more restricted voltage range than

V_IH.) If CE# and RESET# are held at V_IH, but not within

V

_CC± 0.3 V, the device will be in the standby mode, but

Am29LV800B

9

P R E L I M I N A R Y

Refer to the AC Characteristics tables for RESET# pa-

rameters and to Figure 14 for the timing diagram.

Output Disable Mode

When the OE# input is at V_IH, output from the device is

disabled. The output pins are placed in the high imped-

ance state.

Table 2. Am29LV800BT Top Boot Block Sector Address Table

Address Range (in hexadecimal)

Sector Size

(Kbytes/

(x8)

(x16)

Sector

SA0

A18

0

A17

0

A16

0

A15

0

A14

X

0

A13

X

0

A12

X

0

Kwords)

Address Range

64/32

32/16

8/4

00000h–0FFFFh

10000h–1FFFFh

20000h–2FFFFh

30000h–3FFFFh

40000h–4FFFFh

50000h–5FFFFh

60000h–6FFFFh

70000h–7FFFFh

80000h–8FFFFh

90000h–9FFFFh

A0000h–AFFFFh

B0000h–BFFFFh

C0000h–CFFFFh

D0000h–DFFFFh

E0000h–EFFFFh

F0000h–F7FFFh

F8000h–F9FFFh

FA000h–FBFFFh

FC000h–FFFFFh

00000h–07FFFh

08000h–0FFFFh

10000h–17FFFh

18000h–1FFFFh

20000h–27FFFh

28000h–2FFFFh

30000h–37FFFh

38000h–3FFFFh

40000h–47FFFh

48000h–4FFFFh

50000h–57FFFh

58000h–5FFFFh

60000h–67FFFh

68000h–6FFFFh

70000h–77FFFh

78000h–7BFFFh

7C000h–7CFFFh

7D000h–7DFFFh

7E000h–7FFFFh

SA1

0

1

SA2

0

1

0

SA3

0

1

SA4

0

1

0

SA5

0

1

0

1

SA6

0

1

0

SA7

0

1

SA8

1

0

SA9

1

0

1

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

8/4

1

X

16/8

10

Am29LV800B

P R E L I M I N A R Y

Table 3. Am29LV800BB Bottom Boot Block Sector Address Table

Address Range (in hexadecimal)

Sector Size

(Kbytes/

(x8)

(x16)

Sector

SA0

A18

0

A17

0

A16

0

A15

0

A14

0

A13

0

A12

X

0

Kwords)

Address Range

16/8

8/4

00000h–03FFFh

04000h–05FFFh

06000h–07FFFh

08000h–0FFFFh

10000h–1FFFFh

20000h–2FFFFh

30000h–3FFFFh

40000h–4FFFFh

50000h–5FFFFh

60000h–6FFFFh

70000h–7FFFFh

80000h–8FFFFh

90000h–9FFFFh

A0000h–AFFFFh

B0000h–BFFFFh

C0000h–CFFFFh

D0000h–DFFFFh

E0000h–EFFFFh

F0000h–FFFFFh

00000h–01FFFh

02000h–02FFFh

03000h–03FFFh

04000h–07FFFh

08000h–0FFFFh

10000h–17FFFh

18000h–1FFFFh

20000h–27FFFh

28000h–2FFFFh

30000h–37FFFh

38000h–3FFFFh

40000h–47FFFh

48000h–4FFFFh

50000h–57FFFh

58000h–5FFFFh

60000h–67FFFh

68000h–6FFFFh

70000h–77FFFh

78000h–7FFFFh

SA1

0

1

SA2

0

1

8/4

SA3

0

1

X

32/16

64/32

SA4

0

1

X

SA5

0

1

0

SA6

0

1

SA7

0

1

0

SA8

0

1

0

1

SA9

0

1

0

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Note for Tables 2 and 3: Address range is A18:A-1 in byte mode and A18:A0 in word mode. See “Word/Byte Configuration”

section for more information.

Autoselect Mode

The autoselect mode provides manufacturer and de-

vice identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This

mode is primarily intended for programming equipment

to automatically match a device to be programmed with

its corresponding programming algorithm. However,

the autoselect codes can also be accessed in-system

through the command register.

tor address must appear on the appropriate highest

order address bits (see Tables 2 and 3). Table 4 shows

the remaining address bits that are don’t care. When all

necessary bits have been set as required, the program-

ming equipment may then read the corresponding iden-

tifier code on DQ7–DQ0.

To access the autoselect codes in-system, the host

system can issue the autoselect command via the

command register, as shown in Table 5. This method

does not require V_ID. See “Command Definitions” for

details on using the autoselect mode.

When using programming equipment, the autoselect

mode requires V_ID(11.5 V to 12.5 V) on address pin A9.

Address pins A6, A1, and A0 must be as shown in Table

4. In addition, when verifying sector protection, the sec-

Am29LV800B

11

P R E L I M I N A R Y

Table 4. Am29LV800B Autoselect Codes (High Voltage Method)

A18 A11

to to

Mode CE# OE# WE# A12 A10 A9

A8

to

A7

A5

to

A2

DQ8

to

A0 DQ15

DQ7

to

DQ0

Description

A6

A1

Manufacturer ID: AMD

L

H

X

V

X

L

X

L

X

01h

ID

Device ID:

Am29LV800B

(Top Boot Block)

Word

Byte

22h

DAh

X

V

L

H

ID

L

H

X

DAh

5Bh

Device ID:

Am29LV800B

(Bottom Boot

Block)

Word

22h

X

V

X

H

L

ID

Byte

L

H

X

5Bh

01h

(protected)

X

Sector Protection Verification

L

H

SA

L

H

ID

00h

(unprotected)

L = Logic Low = V , H = Logic High = V , SA = Sector Address, X = Don’t care.

IL

IH

Sector Unprotect mode is activated by setting the RE-

SET# pin to V_ID. During this mode, formerly protected

sectors can be programmed or erased by selecting the

sector addresses. Once V_IDis removed from the RE-

SET# pin, all the previously protected sectors are

protected again. Figure 1 shows the algorithm, and

Figure 22 shows the timing diagrams, for this feature.

Sector Protection/Unprotection

The hardware sector protection feature disables both

program and erase operations in any sector. The hard-

ware sector unprotection feature re-enables both pro-

gram and erase operations in previously protected

sectors.

The device is shipped with all sectors unprotected.

AMD offers the option of programming and protecting

sectors at its factory prior to shipping the device

through AMD’s ExpressFlash™ Service. Contact an

AMD representative for details.

START

It is possible to determine whether a sector is protected

or unprotected. See “Autoselect Mode” for details.

RESET# = V

(Note 1)

ID

Sector Protection/unprotection can be implemented via

two methods.

Perform Erase or

Program Operations

The primary method requires V_IDon the RESET# pin

only, and can be implemented either in-system or via

programming equipment. Figure 2 shows the algo-

rithms and Figure 23 shows the timing diagram. This

method uses standard microprocessor bus cycle tim-

ing. For sector unprotect, all unprotected sectors must

first be protected prior to the first sector unprotect write

cycle.

RESET# = V

IH

Temporary Sector

Unprotect Completed

(Note 2)

The alternate method intended only for programming

equipment requires V_IDon address pin A9 and OE#.

This method is compatible with programmer routines

written for earlier 3.0 volt-only AMD flash devices. Pub-

lication number 20536 contains further details; contact

an AMD representative to request a copy.

21490E-5

Notes:

1. All protected sectors unprotected.

2. All previously protected sectors are protected once

again.

Temporary Sector Unprotect

Figure 1. Temporary Sector Unprotect Operation

This feature allows temporary unprotection of previ-

ously protected sectors to change data in-system. The

12

Am29LV800B

P R E L I M I N A R Y

START

Protect all sectors:

The indicated portion

of the sector protect

algorithm must be

performed for all

PLSCNT = 1

RESET# = V_ID

unprotected sectors

prior to issuing the

first sector

Wait 1 µs

unprotect address

No

First Write

No

First Write

Cycle = 60h?

Temporary Sector

Unprotect Mode

Temporary Sector

Unprotect Mode

Cycle = 60h?

Yes

Set up sector

address

No

All sectors

protected?

Sector Protect:

Write 60h to sector

address with

A6 = 0, A1 = 1,

A0 = 0

Yes

Set up first sector

address

Sector Unprotect:

Wait 150 µs

Write 60h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Verify Sector

Protect: Write 40h

to sector address

with A6 = 0,

Reset

PLSCNT = 1

Increment

PLSCNT

Wait 15 ms

A1 = 1, A0 = 0

Verify Sector

Unprotect: Write

40h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector address

with A6 = 0,

A1 = 1, A0 = 0

Increment

PLSCNT

No

PLSCNT

= 25?

Read from

sector address

with A6 = 1,

Data = 01h?

Yes

A1 = 1, A0 = 0

No

Yes

Set up

next sector

address

Yes

No

PLSCNT

= 1000?

Protect another

sector?

Data = 00h?

Yes

Device failed

No

Yes

Remove V_ID

from RESET#

No

Last sector

verified?

Device failed

Write reset

command

Yes

Remove V_ID

Sector Unprotect

Algorithm

from RESET#

Sector Protect

Algorithm

Sector Protect

complete

Write reset

command

Sector Unprotect

complete

21490E-6

Figure 2. In-System Sector Protect/Unprotect Algorithms

Am29LV800B

13

P R E L I M I N A R Y

proper signals to the control pins to prevent uninten-

tional writes when V_CCis greater than V_LKO

Hardware Data Protection

.

The command sequence requirement of unlock cycles

for programming or erasing provides data protection

against inadvertent writes (refer to Table 5 for com-

mand definitions). In addition, the following hardware

data protection measures prevent accidental erasure

or programming, which might otherwise be caused by

spurious system level signals during V_CCpower-up

and power-down transitions, or from system noise.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or

WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# =

V_IL, CE# = V_IHor WE# = V_IH. To initiate a write cycle,

CE# and WE# must be a logical zero while OE# is a

logical one.

Low V

Write Inhibit

CC

When V_CCis less than V_LKO, the device does not ac-

cept any write cycles. This protects data during V_CC

power-up and power-down. The command register and

all internal program/erase circuits are disabled, and the

device resets. Subsequent writes are ignored until V_CC

is greater than V_LKO. The system must provide the

Power-Up Write Inhibit

If WE# = CE# = V_ILand OE# = V_IHduring power up, the

device does not accept commands on the rising edge

of WE#. The internal state machine is automatically

reset to reading array data on power-up.

COMMAND DEFINITIONS

Writing specific address and data commands or se-

quences into the command register initiates device op-

erations. Table 5 defines the valid register command

sequences. Writing incorrect address and data val-

ues or writing them in the improper sequence resets

the device to reading array data.

Reset Command

Writing the reset command to the device resets the de-

vice to reading array data. Address bits are don’t care

for this command.

The reset command may be written between the se-

quence cycles in an erase command sequence before

erasing begins. This resets the device to reading array

data. Once erasure begins, however, the device ig-

nores reset commands until the operation is complete.

All addresses are latched on the falling edge of WE# or

CE#, whichever happens later. All data is latched on

the rising edge of WE# or CE#, whichever happens

first. Refer to the appropriate timing diagrams in the

“AC Characteristics” section.

The reset command may be written between the se-

quence cycles in a program command sequence be-

fore programming begins. This resets the device to

reading array data (also applies to programming in

Erase Suspend mode). Once programming begins,

however, the device ignores reset commands until the

operation is complete.

Reading Array Data

The device is automatically set to reading array data

after device power-up. No commands are required to

retrieve data. The device is also ready to read array

data after completing an Embedded Program or Em-

bedded Erase algorithm.

The reset command may be written between the se-

quence cycles in an autoselect command sequence.

Once in the autoselect mode, the reset command must

be written to return to reading array data (also applies

to autoselect during Erase Suspend).

After the device accepts an Erase Suspend com-

mand, the device enters the Erase Suspend mode.

The system can read array data using the standard

read timings, except that if it reads at an address

within erase-suspended sectors, the device outputs

status data. After completing a programming opera-

tion in the Erase Suspend mode, the system may

once again read array data with the same exception.

See “Erase Suspend/Erase Resume Commands” for

more information on this mode.

If DQ5 goes high during a program or erase operation,

writing the reset command returns the device to read-

ing array data (also applies during Erase Suspend).

Autoselect Command Sequence

The autoselect command sequence allows the host

system to access the manufacturer and devices codes,

and determine whether or not a sector is protected.

Table 5 shows the address and data requirements. This

method is an alternative to that shown in Table 4, which

is intended for PROM programmers and requires V_ID

on address bit A9.

The system must issue the reset command to re-ena-

ble the device for reading array data if DQ5 goes high,

or while in the autoselect mode. See the “Reset Com-

mand” section, next.

See also “Requirements for Reading Array Data” in the

“Device Bus Operations” section for more information.

The Read Operations table provides the read parame-

ters, and Figure 13 shows the timing diagram.

The autoselect command sequence is initiated by writ-

ing two unlock cycles, followed by the autoselect com-

14

Am29LV800B

P R E L I M I N A R Y

mand. The device then enters the autoselect mode,

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed

from a “0” back to a “1”. Attempting to do so may halt

the operation and set DQ5 to “1”, or cause the Data#

Polling algorithm to indicate the operation was suc-

cessful. However, a succeeding read will show that the

data is still “0”. Only erase operations can convert a “0”

to a “1”.

and the system may read at any address any number

of times, without initiating another command sequence.

A read cycle at address XX00h retrieves the manufac-

turer code. A read cycle at address XX01h in word

mode (or 02h in byte mode) returns the device code. A

read cycle containing a sector address (SA) and the

address 02h in word mode (or 04h in byte mode) re-

turns 01h if that sector is protected, or 00h if it is unpro-

tected. Refer to Tables 2 and 3 for valid sector

addresses.

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to pro-

gram bytes or words to the device faster than using the

standard program command sequence. The unlock by-

pass command sequence is initiated by first writing two

unlock cycles. This is followed by a third write cycle

containing the unlock bypass command, 20h. The de-

vice then enters the unlock bypass mode. A two-cycle

unlock bypass program command sequence is all that

is required to program in this mode. The first cycle in

this sequence contains the unlock bypass program

command, A0h; the second cycle contains the program

address and data. Additional data is programmed in

the same manner. This mode dispenses with the initial

two unlock cycles required in the standard program

command sequence, resulting in faster total program-

ming time. Table 5 shows the requirements for the com-

mand sequence.

The system must write the reset command to exit the

autoselect mode and return to reading array data.

Word/Byte Program Command Sequence

The system may program the device by word or byte,

depending on the state of the BYTE# pin. Program-

ming is a four-bus-cycle operation. The program com-

mand sequence is initiated by writing two unlock write

cycles, followed by the program set-up command. The

program address and data are written next, which in

turn initiate the Embedded Program algorithm. The

system is not required to provide further controls or tim-

ings. The device automatically provides internally gen-

erated program pulses and verifies the programmed

cell margin. Table 5 shows the address and data re-

quirements for the byte program command sequence.

During the unlock bypass mode, only the Unlock By-

pass Program and Unlock Bypass Reset commands

are valid. To exit the unlock bypass mode, the system

must issue the two-cycle unlock bypass reset com-

mand sequence. The first cycle must contain the data

90h; the second cycle the data 00h. Addresses are

don’t care for both cycles. The device then returns to

reading array data.

When the Embedded Program algorithm is complete,

the device then returns to reading array data and ad-

dresses are no longer latched. The system can deter-

mine the status of the program operation by using

DQ7, DQ6, or RY/BY#. See “Write Operation Status”

for information on these status bits.

Any commands written to the device during the Em-

bedded Program Algorithm are ignored. Note that a

hardware reset immediately terminates the program-

ming operation. The program command sequence

should be reinitiated once the device has reset to read-

ing array data, to ensure data integrity.

Figure 3 illustrates the algorithm for the program oper-

ation. See the Erase/Program Operations table in “AC

Characteristics” for parameters, and to Figure 17 for

timing diagrams.

Am29LV800B

15

P R E L I M I N A R Y

The system can determine the status of the erase op-

eration by using DQ7, DQ6, DQ2, or RY/BY#. See

“Write Operation Status” for information on these sta-

tus bits. When the Embedded Erase algorithm is com-

plete, the device returns to reading array data and

addresses are no longer latched.

START

Write Program

Command Sequence

Figure 4 illustrates the algorithm for the erase opera-

tion. See the Erase/Program Operations tables in “AC

Characteristics” for parameters, and to Figure 18 for

timing diagrams.

Data Poll

from System

Sector Erase Command Sequence

Embedded

Program

algorithm

in progress

Sector erase is a six bus cycle operation. The sector

erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two ad-

ditional unlock write cycles are then followed by the ad-

dress of the sector to be erased, and the sector erase

command. Table 5 shows the address and data re-

quirements for the sector erase command sequence.

Verify Data?

Yes

No

The device does not require the system to preprogram

the memory prior to erase. The Embedded Erase algo-

rithm automatically programs and verifies the sector for

an all zero data pattern prior to electrical erase. The

system is not required to provide any controls or tim-

ings during these operations.

No

Increment Address

Last Address?

Yes

Programming

Completed

After the command sequence is written, a sector erase

time-out of 50 µs begins. During the time-out period,

additional sector addresses and sector erase com-

mands may be written. Loading the sector erase buffer

may be done in any sequence, and the number of sec-

tors may be from one sector to all sectors. The time be-

tween these additional cycles must be less than 50 µs,

otherwise the last address and command might not be

accepted, and erasure may begin. It is recommended

that processor interrupts be disabled during this time to

ensure all commands are accepted. The interrupts can

be re-enabled after the last Sector Erase command is

written. If the time between additional sector erase

commands can be assumed to be less than 50 µs, the

system need not monitor DQ3. Any command other

than Sector Erase or Erase Suspend during the

time-out period resets the device to reading array

data. The system must rewrite the command sequence

and any additional sector addresses and commands.

21490E-7

Note: See Table 5 for program command sequence.

Figure 3. Program Operation

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase

command sequence is initiated by writing two unlock

cycles, followed by a set-up command. Two additional

unlock write cycles are then followed by the chip erase

command, which in turn invokes the Embedded Erase

algorithm. The device does not require the system to

preprogram prior to erase. The Embedded Erase algo-

rithm automatically preprograms and verifies the entire

memory for an all zero data pattern prior to electrical

erase. The system is not required to provide any con-

trols or timings during these operations. Table 5 shows

the address and data requirements for the chip erase

command sequence.

The system can monitor DQ3 to determine if the sector

erase timer has timed out. (See the “DQ3: Sector Erase

Timer” section.) The time-out begins from the rising

edge of the final WE# pulse in the command sequence.

Once the sector erase operation has begun, only the

Erase Suspend command is valid. All other commands

are ignored. Note that a hardware reset during the

sector erase operation immediately terminates the op-

eration. The Sector Erase command sequence should

be reinitiated once the device has returned to reading

array data, to ensure data integrity.

Any commands written to the chip during the Embed-

ded Erase algorithm are ignored. Note that a hardware

reset during the chip erase operation immediately ter-

minates the operation. The Chip Erase command se-

quence should be reinitiated once the device has

returned to reading array data, to ensure data integrity.

16

Am29LV800B

P R E L I M I N A R Y

When the Embedded Erase algorithm is complete, the

status bits, just as in the standard program operation.

See “Write Operation Status” for more information.

device returns to reading array data and addresses are

no longer latched. The system can determine the sta-

tus of the erase operation by using DQ7, DQ6, DQ2, or

RY/BY#. Refer to “Write Operation Status” for informa-

tion on these status bits.

The system may also write the autoselect command

sequence when the device is in the Erase Suspend

mode. The device allows reading autoselect codes

even at addresses within erasing sectors, since the

codes are not stored in the memory array. When the

device exits the autoselect mode, the device reverts to

the Erase Suspend mode, and is ready for another

valid operation. See “Autoselect Command Sequence”

for more information.

Figure 4 illustrates the algorithm for the erase opera-

tion. Refer to the Erase/Program Operations tables in

the “AC Characteristics” section for parameters, and to

Figure 18 for timing diagrams.

Erase Suspend/Erase Resume Commands

The system must write the Erase Resume command

(address bits are “don’t care”) to exit the erase suspend

mode and continue the sector erase operation. Further

writes of the Resume command are ignored. Another

Erase Suspend command can be written after the de-

vice has resumed erasing.

The Erase Suspend command allows the system to in-

terrupt a sector erase operation and then read data

from, or program data to, any sector not selected for

erasure. This command is valid only during the sector

erase operation, including the 50 µs time-out period

during the sector erase command sequence. The

Erase Suspend command is ignored if written during

the chip erase operation or Embedded Program algo-

rithm. Writing the Erase Suspend command during the

Sector Erase time-out immediately terminates the

time-out period and suspends the erase operation. Ad-

dresses are “don’t-cares” when writing the Erase Sus-

pend command.

START

Write Erase

Command Sequence

When the Erase Suspend command is written during a

sector erase operation, the device requires a maximum

of 20 µs to suspend the erase operation. However,

when the Erase Suspend command is written during

the sector erase time-out, the device immediately ter-

minates the time-out period and suspends the erase

operation.

Data Poll

from System

Embedded

Erase

algorithm

in progress

After the erase operation has been suspended, the

system can read array data from or program data to

any sector not selected for erasure. (The device “erase

suspends” all sectors selected for erasure.) Normal

read and write timings and command definitions apply.

Reading at any address within erase-suspended sec-

tors produces status data on DQ7–DQ0. The system

can use DQ7, or DQ6 and DQ2 together, to determine

if a sector is actively erasing or is erase-suspended.

See “Write Operation Status” for information on these

status bits.

No

Data = FFh?

Yes

Erasure Completed

21490E-8

Notes:

1. See Table 5 for erase command sequence.

After an erase-suspended program operation is com-

plete, the system can once again read array data within

non-suspended sectors. The system can determine the

status of the program operation using the DQ7 or DQ6

2. See “DQ3: Sector Erase Timer” for more information.

Figure 4. Erase Operation

Am29LV800B

17

P R E L I M I N A R Y

Table 5. Am29LV800B Command Definitions

Bus Cycles (Notes 2-5)

Command

Sequence

(Note 1)

First

Second

Third

Addr

Fourth

Fifth

Sixth

Addr Data Addr Data

Data Addr Data Addr Data Addr Data

Read (Note 6)

Reset (Note 7)

1

RA

XXX

555

RD

F0

Word

Byte

Word

Byte

Word

Byte

2AA

555

2AA

555

2AA

555

AAA

555

Manufacturer ID

4

AA

55

90

X00

01

AAA

555

X01 22DA

X02

DA

X01 225B

Device ID,

Top Boot Block

AAA

555

AAA

555

Device ID,

Bottom Boot Block

AAA

X02

5B

XX00

XX01

00

(SA)

X02

Word

Byte

555

2AA

555

Sector Protect Verify

(Note 9)

4

AA

55

90

(SA)

X04

AAA

01

Word

Byte

Word

Byte

555

AAA

555

2AA

555

2AA

555

PA

555

AAA

555

Program

4

3

AA

55

A0

20

PA

PD

Unlock Bypass

AAA

XXX

555

AAA

Unlock Bypass Program (Note 10)

Unlock Bypass Reset (Note 11)

2

A0

90

PD

00

XXX

2AA

555

2AA

555

Word

555

AAA

555

AAA

555

2AA

555

2AA

555

Chip Erase

Byte

6

AA

55

80

AA

55

10

30

AAA

555

AAA

Word

Sector Erase

Byte

SA

AAA

XXX

AAA

Erase Suspend (Note 12)

Erase Resume (Note 13)

1

B0

30

Legend:

X = Don’t care

PD = Data to be programmed at location PA. Data latches on the

rising edge of WE# or CE# pulse, whichever happens first.

RA = Address of the memory location to be read.

SA = Address of the sector to be verified (in autoselect mode) or

erased. Address bits A18–A12 uniquely select any sector.

RD = Data read from location RA during read operation.

PA = Address of the memory location to be programmed.

Addresses latch on the falling edge of the WE# or CE# pulse,

whichever happens later.

Notes:

1. See Table 1 for description of bus operations.

9. The data is 00h for an unprotected sector and 01h for a

protected sector. See “Autoselect Command Sequence” for

more information.

2. All values are in hexadecimal.

3. Except when reading array or autoselect data, all bus cycles

are write operations.

10. The Unlock Bypass command is required prior to the Unlock

Bypass Program command.

4. Data bits DQ15–DQ8 are don’t cares for unlock and

command cycles.

11. The Unlock Bypass Reset command is required to return to

reading array data when the device is in the unlock bypass

mode.

5. Address bits A18–A11 are don’t cares for unlock and

command cycles, unless PA or SA required.

12. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend

mode. The Erase Suspend command is valid only during a

sector erase operation.

6. No unlock or command cycles required when reading array

data.

7. The Reset command is required to return to reading array

data when device is in the autoselect mode, or if DQ5 goes

high (while the device is providing status data).

13. The Erase Resume command is valid only during the Erase

Suspend mode.

8. The fourth cycle of the autoselect command sequence is a

read cycle.

18

Am29LV800B

P R E L I M I N A R Y

WRITE OPERATION STATUS

The device provides several bits to determine the sta-

tus of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7,

and RY/BY#. Table 6 and the following subsections de-

scribe the functions of these bits. DQ7, RY/BY#, and

DQ6 each offer a method for determining whether a

program or erase operation is complete or in progress.

These three bits are discussed first.

Table 6 shows the outputs for Data# Polling on DQ7.

Figure 5 shows the Data# Polling algorithm.

START

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host system

whether an Embedded Algorithm is in progress or com-

pleted, or whether the device is in Erase Suspend.

Data# Polling is valid after the rising edge of the final

WE# pulse in the program or erase command se-

quence.

Read DQ7–DQ0

Addr = VA

Yes

DQ7 = Data?

During the Embedded Program algorithm, the device

outputs on DQ7 the complement of the datum pro-

grammed to DQ7. This DQ7 status also applies to pro-

gramming during Erase Suspend. When the

Embedded Program algorithm is complete, the device

outputs the datum programmed to DQ7. The system

must provide the program address to read valid status

information on DQ7. If a program address falls within a

protected sector, Data# Polling on DQ7 is active for ap-

proximately 1 µs, then the device returns to reading

array data.

No

DQ5 = 1?

Yes

Read DQ7–DQ0

Addr = VA

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase al-

gorithm is complete, or if the device enters the Erase

Suspend mode, Data# Polling produces a “1” on DQ7.

This is analogous to the complement/true datum output

described for the Embedded Program algorithm: the

erase function changes all the bits in a sector to “1”;

prior to this, the device outputs the “complement,” or

“0.” The system must provide an address within any of

the sectors selected for erasure to read valid status in-

formation on DQ7.

Yes

DQ7 = Data?

No

PASS

FAIL

After an erase command sequence is written, if all sec-

tors selected for erasing are protected, Data# Polling

on DQ7 is active for approximately 100 µs, then the de-

vice returns to reading array data. If not all selected

sectors are protected, the Embedded Erase algorithm

erases the unprotected sectors, and ignores the se-

lected sectors that are protected.

Notes:

1. VA = Valid address for programming. During a sector

erase operation, a valid address is an address within any

sector selected for erasure. During chip erase, a valid

address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because

When the system detects DQ7 has changed from the

complement to true data, it can read valid data at DQ7–

DQ7 may change simultaneously with DQ5.

following read cycles. This is because DQ7

DQ0 on the

21490E-9

may change asynchronously with DQ0–DQ6 while

Output Enable (OE#) is asserted low. Figure 19, Data#

Polling Timings (During Embedded Algorithms), in the

“AC Characteristics” section illustrates this.

Figure 5. Data# Polling Algorithm

Am29LV800B

19

P R E L I M I N A R Y

Table 6 shows the outputs for Toggle Bit I on DQ6. Fig-

RY/BY#: Ready/Busy#

ure 6 shows the toggle bit algorithm. Figure 20 in the

“AC Characteristics” section shows the toggle bit timing

diagrams. Figure 21 shows the differences between

DQ2 and DQ6 in graphical form. See also the subsec-

tion on “DQ2: Toggle Bit II”.

The RY/BY# is a dedicated, open-drain output pin that

indicates whether an Embedded Algorithm is in

progress or complete. The RY/BY# status is valid after

the rising edge of the final WE# pulse in the command

sequence. Since RY/BY# is an open-drain output, sev-

eral RY/BY# pins can be tied together in parallel with a

DQ2: Toggle Bit II

pull-up resistor to V_CC

.

The “Toggle Bit II” on DQ2, when used with DQ6, indi-

cates whether a particular sector is actively erasing

(that is, the Embedded Erase algorithm is in progress),

or whether that sector is erase-suspended. Toggle Bit

II is valid after the rising edge of the final WE# pulse in

the command sequence.

If the output is low (Busy), the device is actively erasing

or programming. (This includes programming in the

Erase Suspend mode.) If the output is high (Ready),

the device is ready to read array data (including during

the Erase Suspend mode), or is in the standby mode.

Table 6 shows the outputs for RY/BY#. Figures 13, 14,

17 and 18 shows RY/BY# for read, reset, program, and

erase operations, respectively.

DQ2 toggles when the system reads at addresses

within those sectors that have been selected for eras-

ure. (The system may use either OE# or CE# to control

the read cycles.) But DQ2 cannot distinguish whether

the sector is actively erasing or is erase-suspended.

DQ6, by comparison, indicates whether the device is

actively erasing, or is in Erase Suspend, but cannot

distinguish which sectors are selected for erasure.

Thus, both status bits are required for sector and mode

information. Refer to Table 6 to compare outputs for

DQ2 and DQ6.

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded

Program or Erase algorithm is in progress or complete,

or whether the device has entered the Erase Suspend

mode. Toggle Bit I may be read at any address, and is

valid after the rising edge of the final WE# pulse in the

command sequence (prior to the program or erase op-

eration), and during the sector erase time-out.

Figure 6 shows the toggle bit algorithm in flowchart

form, and the section “DQ2: Toggle Bit II” explains the

algorithm. See also the “DQ6: Toggle Bit I” subsection.

Figure 20 shows the toggle bit timing diagram. Figure

21 shows the differences between DQ2 and DQ6 in

graphical form.

During an Embedded Program or Erase algorithm op-

eration, successive read cycles to any address cause

DQ6 to toggle. (The system may use either OE# or

CE# to control the read cycles.) When the operation is

complete, DQ6 stops toggling.

After an erase command sequence is written, if all sec-

tors selected for erasing are protected, DQ6 toggles for

approximately 100 µs, then returns to reading array

data. If not all selected sectors are protected, the Em-

bedded Erase algorithm erases the unprotected sec-

tors, and ignores the selected sectors that are

protected.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 6 for the following discussion. Whenever

the system initially begins reading toggle bit status, it

must read DQ7–DQ0 at least twice in a row to determine

whether a toggle bit is toggling. Typically, the system

would note and store the value of the toggle bit after the

first read. After the second read, the system would com-

pare the new value of the toggle bit with the first. If the

toggle bit is not toggling, the device has completed the

program or erase operation. The system can read array

data on DQ7–DQ0 on the following read cycle.

The system can use DQ6 and DQ2 together to deter-

mine whether a sector is actively erasing or is erase-

suspended. When the device is actively erasing (that

is, the Embedded Erase algorithm is in progress), DQ6

toggles. When the device enters the Erase Suspend

mode, DQ6 stops toggling. However, the system must

also use DQ2 to determine which sectors are erasing

or erase-suspended. Alternatively, the system can use

DQ7 (see the subsection on “DQ7: Data# Polling”).

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the sys-

tem also should note whether the value of DQ5 is high

(see the section on DQ5). If it is, the system should

then determine again whether the toggle bit is toggling,

since the toggle bit may have stopped toggling just as

DQ5 went high. If the toggle bit is no longer toggling,

the device has successfully completed the program or

erase operation. If it is still toggling, the device did not

completed the operation successfully, and the system

must write the reset command to return to reading

array data.

If a program address falls within a protected sector,

DQ6 toggles for approximately 1 µs after the program

command sequence is written, then returns to reading

array data.

DQ6 also toggles during the erase-suspend-program

mode, and stops toggling once the Embedded Pro-

gram algorithm is complete.

20

Am29LV800B

P R E L I M I N A R Y

The remaining scenario is that the system initially de-

DQ5: Exceeded Timing Limits

termines that the toggle bit is toggling and DQ5 has not

gone high. The system may continue to monitor the

toggle bit and DQ5 through successive read cycles, de-

termining the status as described in the previous para-

graph. Alternatively, it may choose to perform other

system tasks. In this case, the system must start at the

beginning of the algorithm when it returns to determine

the status of the operation (top of Figure 6).

DQ5 indicates whether the program or erase time has

exceeded a specified internal pulse count limit. Under

these conditions DQ5 produces a “1.” This is a failure

condition that indicates the program or erase cycle was

not successfully completed.

The DQ5 failure condition may appear if the system

tries to program a “1” to a location that is previously

programmed to “0.” Only an erase operation can

change a “0” back to a “1.” Under this condition, the

device halts the operation, and when the operation has

exceeded the timing limits, DQ5 produces a “1.”

START

Under both these conditions, the system must issue

the reset command to return the device to reading

array data.

Read DQ7–DQ0

(Note 1)

DQ3: Sector Erase Timer

Read DQ7–DQ0

After writing a sector erase command sequence, the

system may read DQ3 to determine whether or not an

erase operation has begun. (The sector erase timer

does not apply to the chip erase command.) If additional

sectors are selected for erasure, the entire time-out also

applies after each additional sector erase command.

When the time-out is complete, DQ3 switches from “0”

to “1.” The system may ignore DQ3 if the system can

guarantee that the time between additional sector

erase commands will always be less than 50 µs. See

also the “Sector Erase Command Sequence” section.

No

Toggle Bit

= Toggle?

Yes

No

DQ5 = 1?

Yes

After the sector erase command sequence is written,

the system should read the status on DQ7 (Data# Poll-

ing) or DQ6 (Toggle Bit I) to ensure the device has ac-

cepted the command sequence, and then read DQ3. If

DQ3 is “1”, the internally controlled erase cycle has be-

gun; all further commands (other than Erase Suspend)

are ignored until the erase operation is complete. If

DQ3 is “0”, the device will accept additional sector

erase commands. To ensure the command has been

accepted, the system software should check the status

of DQ3 prior to and following each subsequent sector

erase command. If DQ3 is high on the second status

check, the last command might not have been ac-

cepted. Table 6 shows the outputs for DQ3.

(Notes

1, 2)

Read DQ7–DQ0

Twice

Toggle Bit

= Toggle?

No

Yes

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Notes:

1. Read toggle bit twice to determine whether or not it is

toggling. See text.

2. Recheck toggle bit because it may stop toggling as DQ5

changes to “1” . See text.

21490E-10

Figure 6. Toggle Bit Algorithm

Am29LV800B

21

P R E L I M I N A R Y

Table 6. Write Operation Status

DQ7

DQ5

DQ2

Operation

(Note 2)

DQ6

(Note 1)

DQ3

N/A

1

(Note 2)

RY/BY#

Embedded Program Algorithm

Embedded Erase Algorithm

DQ7#

0

Toggle

0

No toggle

Toggle

0

Standard

Mode

Reading within Erase

Suspended Sector

1

No toggle

0

N/A

Toggle

1

Erase

Suspend Reading within Non-Erase

Data

0

Data

N/A

Data

N/A

1

0

Mode

Suspended Sector

Erase-Suspend-Program

DQ7#

Toggle

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

See “DQ5: Exceeded Timing Limits” for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

22

Am29LV800B

P R E L I M I N A R Y

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C

20 ns

+0.8 V

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . –65°C to +125°C

–0.5 V

–2.0 V

Voltage with Respect to Ground

V_CC(Note 1) . . . . . . . . . . . . . . . .–0.5 V to +4.0 V

A9, OE#, and

RESET# (Note 2). . . . . . . . . . . .–0.5 V to +12.5 V

20 ns

All other pins (Note 1) . . . . . –0.5 V to V_CC+0.5 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

21490E-11

Notes:

Figure 7. Maximum Negative Overshoot

Waveform

1. Minimum DC voltage on input or I/O pins is –0.5 V. During

voltage transitions, input or I/O pins may undershoot V

to –2.0 V for periods of up to 20 ns. See Figure 7.

SS

Maximum DC voltage on input or I/O pins is V +0.5 V.

CC

During voltage transitions, input or I/O pins may overshoot

to V +2.0 V for periods up to 20 ns. See Figure 8.

CC

20 ns

2. Minimum DC input voltage on pins A9, OE#, and RESET#

is –0.5 V. During voltage transitions, A9, OE#, and

V

CC

RESET# may undershoot V to –2.0 V for periods of up

+2.0 V

SS

to 20 ns. See Figure 7. Maximum DC input voltage on pin

A9 is +12.5 V which may overshoot to 14.0 V for periods

up to 20 ns.

V

CC

+0.5 V

2.0 V

3. No more than one output may be shorted to ground at a

time. Duration of the short circuit should not be greater

than one second.

20 ns

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This is

a stress rating only; functional operation of the device at

these or any other conditions above those indicated in the

operational sections of this data sheet is not implied.

Exposure of the device to absolute maximum rating

conditions for extended periods may affect device reliability.

21490E-12

Figure 8. Maximum Positive Overshoot

Waveform

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (T_A) . . . . . . . . . . . 0°C to +70°C

Industrial (I) Devices

Ambient Temperature (T_A) . . . . . . . . . –40°C to +85°C

Extended (E) Devices

Ambient Temperature (T_A) . . . . . . . . –55°C to +125°C

V_CCSupply Voltages

V_CCfor regulated voltage range. . . . .+3.0 V to +3.6 V

V_CCfor full voltage range . . . . . . . . . .+2.7 V to +3.6 V

Operating ranges define those limits between which the func-

tionality of the device is guaranteed.

Am29LV800B

23

P R E L I M I N A R Y

DC CHARACTERISTICS

CMOS Compatible

Parameter

Description

Test Conditions

= V to V

Min

Typ

Max

±1.0

35

Unit

µA

V

,

CC

IN

SS

I

Input Load Current

LI

= V

CC

CC max

I

A9 Input Load Current

Output Leakage Current

V

= V

; A9 = 12.5 V

µA

LIT

CC

CC max

V

= V to V

,

CC

OUT

SS

I

±1.0

µA

LO

= V

CC

CC max

5 MHz

1 MHz

5 MHz

1 MHz

7

2

7

2

12

4

CE# = V OE#

Byte Mode

V

IL,

=

IH,

V

Active Read Current

CC

I

mA

CC1

(Note 1)

12

4

CE# = V OE#

V

IL,

Word Mode

V

Active Write Current

CC

I

CE# = V OE#

V

15

0.2

30

5

mA

µA

CC2

CC3

CC4

CC5

IL,

=

IH

(Notes 2 and 4)

V

= V

;

CC max

CC

V

Standby Current

Reset Current

CC

CE#, RESET# = V ±0.3 V

CC

V

= V

;

CC max

CC

V

5

RESET# = V ± 0.3 V

SS

V

= V ± 0.3 V;

CC

IH

IL

Automatic Sleep Mode (Note 3)

5

= V ± 0.3 V

SS

V

Input Low Voltage

Input High Voltage

–0.5

0.8

V

IL

V

0.7 x V

V

+ 0.3

IH

CC

Voltage for Autoselect and

Temporary Sector Unprotect

V

= 3.3 V

11.5

12.5

0.45

V

ID

CC

V

Output Low Voltage

I

= 4.0 mA, V = V

CC min

V

OL

OH

CC

V

= –2.0 mA, V = V

0.85 V

OH1

OH2

CC

CC min

CC

Output High Voltage

= –100 µA, V = V

V

–0.4

CC

Low V Lock-Out Voltage

(Note 4)

CC

V

2.3

2.5

V

LKO

Notes:

1. The I current listed is typically less than 2 mA/MHz, with OE# at V . Typical V is 3.0 V.

CC

IH

CC

2. I active while Embedded Erase or Embedded Program is in progress.

CC

3. Automatic sleep mode enables the low power mode when addresses remain stable for t

4. Not 100% tested.

+ 30 ns.

ACC

24

Am29LV800B

P R E L I M I N A R Y

DC CHARACTERISTICS (Continued)

Zero Power Flash

20

15

10

5

0

500

1000

1500

2000

2500

3000

3500

4000

Time in ns

Note: Addresses are switching at 1 MHz

21490E-13

Figure 9. I_CC1Current vs. Time (Showing Active and Automatic Sleep Currents)

10

8

3.6 V

2.7 V

6

4

2

0

1

2

3

4

5

Frequency in MHz

Note: T = 25 °C

21490E-14

Figure 10. Typical I_CC1vs. Frequency

Am29LV800B

25

P R E L I M I N A R Y

TEST CONDITIONS

Table 7. Test Specifications

3.3 V

70R,

80

90,

120

Test Condition

Unit

2.7 kΩ

Device

Under

Test

Output Load

1 TTL gate

Output Load Capacitance, C

(including jig capacitance)

L

30

100

pF

C

L

6.2 kΩ

Input Rise and Fall Times

Input Pulse Levels

5

0.0–3.0

ns

V

Input timing measurement

reference levels

1.5

V

Note: Diodes are IN3064 or equivalent

Output timing measurement

reference levels

21490E-15

Figure 11. Test Setup

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Center Line is High Impedance State (High Z)

KS000010-PAL

3.0 V

0.0 V

1.5 V

Input

Measurement Level

Output

21490E-16

Figure 12. Input Waveforms and Measurement Levels

26

Am29LV800B

P R E L I M I N A R Y

AC CHARACTERISTICS

Read Operations

Parameter

Speed Option

JEDEC

Std

Description

Test Setup

Min

70R

80

90

120 Unit

t

Read Cycle Time (Note 1)

Address to Output Delay

70

80

90

120

ns

AVAV

RC

CE# = V

IL

t

Max

70

80

90

AVQV

ACC

OE# = V

t

Chip Enable to Output Delay

OE# = V

Max

Min

70

30

25

80

30

25

90

35

30

120

50

ns

ELQV

GLQV

EHQZ

GHQZ

CE

IL

t

Output Enable to Output Delay

OE

t

Chip Enable to Output High Z (Note 1)

Output Enable to Output High Z (Note 1)

30

DF

t

30

DF

Read

0

Output Enable

Hold Time (Note 1)

t

OEH

Toggle and

Data# Polling

Min

10

ns

Output Hold Time From Addresses, CE# or

OE#, Whichever Occurs First (Note 1)

t

0

AXQX

OH

Notes:

1. Not 100% tested.

2. See Figure 11 and Table 7 for test specifications.

t_RC

Addresses Stable

t_ACC

Addresses

CE#

t_DF

t_OE

OE#

t_OEH

WE#

t_CE

t_OH

HIGH Z

Output Valid

Outputs

RESET#

RY/BY#

0 V

21490E-17

Figure 13. Read Operations Timings

Am29LV800B

27

P R E L I M I N A R Y

AC CHARACTERISTICS

Hardware Reset (RESET#)

Parameter

JEDEC

Std

Description

Test Setup

Max

All Speed Options

Unit

RESET# Pin Low (During Embedded

Algorithms) to Read or Write (See Note)

t

20

µs

READY

RESET# Pin Low (NOT During Embedded

Algorithms) to Read or Write (See Note)

t

Max

500

ns

READY

t

RESET# Pulse Width

Min

500

50

20

0

ns

µs

ns

RP

RESET# High Time Before Read (See Note)

RESET# Low to Standby Mode

RY/BY# Recovery Time

RH

t

RPD

t

RB

Note: Not 100% tested.

RY/BY#

CE#, OE#

RESET#

t_RH

t_RP

t_Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

t_Ready

RY/BY#

t_RB

CE#, OE#

RESET#

t_RP

21490E-18

Figure 14. RESET# Timings

28

Am29LV800B

P R E L I M I N A R Y

AC CHARACTERISTICS

Word/Byte Configuration (BYTE#)

Parameter

JEDEC

Std

Description

70R

80

90

120

Unit

ns

t

CE# to BYTE# Switching Low or High

BYTE# Switching Low to Output HIGH Z

BYTE# Switching High to Output Active

Max

Min

5

ELFL/ ELFH

25

70

25

80

30

90

30

ns

FLQZ

FHQV

120

ns

CE#

OE#

BYTE#

t

ELFL

Data Output

(DQ0–DQ14)

Data Output

(DQ0–DQ7)

BYTE#

Switching

from word

to byte

DQ0–DQ14

DQ15/A-1

Address

Input

DQ15

Output

mode

t

FLQZ

t

ELFH

BYTE#

Switching

from byte

to word

Data Output

(DQ0–DQ7)

Data Output

(DQ0–DQ14)

DQ0–DQ14

DQ15/A-1

mode

Address

Input

DQ15

Output

t

FHQV

21490E-19

Figure 15. BYTE# Timings for Read Operations

CE#

The falling edge of the last WE# signal

WE#

BYTE#

t

SET

(t

)

AS

t

(t

)

HOLD AH

Note: Refer to the Erase/Program Operations table for t and t specifications.

AS

AH

21490E-20

Figure 16. BYTE# Timings for Write Operations

Am29LV800B

29

P R E L I M I N A R Y

AC CHARACTERISTICS

Erase/Program Operations

Parameter

JEDEC

Std

Description

70R

80

90

120

Unit

ns

t

Write Cycle Time (Note 1)

Address Setup Time

Address Hold Time

Data Setup Time

Min

70

80

90

120

AVAV

WC

t

0

ns

AVWL

WLAX

AS

AH

DS

DH

t

45

35

45

35

45

50

ns

t

ns

DVWH

WHDX

t

Data Hold Time

0

ns

t

Output Enable Setup Time

ns

OES

Read Recovery Time Before Write

(OE# High to WE# Low)

t

Min

0

ns

GHWL

t

CE# Setup Time

Min

Typ

Min

0

ns

ELWL

WHEH

WLWH

WHWL

CS

CH

WP

t

CE# Hold Time

t

Write Pulse Width

Write Pulse Width High

35

50

t

30

9

WPH

Byte

t

Programming Operation (Note 2)

µs

WHWH1

WHWH2

WHWH1

Word

11

0.7

50

0

t

Sector Erase Operation (Note 2)

sec

µs

WHWH2

t

V

Setup Time (Note 1)

VCS

CC

t

Recovery Time from RY/BY#

ns

RB

t

Program/Erase Valid to RY/BY# Delay

90

ns

BUSY

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

30

Am29LV800B

P R E L I M I N A R Y

AC CHARACTERISTICS

Program Command Sequence (last two cycles)

Read Status Data (last two cycles)

t_AS

PA

t_WC

Addresses

555h

PA

t_AH

CE#

OE#

t_CH

t_GHWL

t_WHWH1

t_WP

WE#

Data

t_WPH

t_CS

t_DS

t_DH

PD

D_OUT

A0h

Status

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. PA = program address, PD = program data, D

is the true data at the program address.

OUT

2. Illustration shows device in word mode.

21490E-21

Figure 17. Program Operation Timings

Am29LV800B

31

P R E L I M I N A R Y

AC CHARACTERISTICS

Erase Command Sequence (last two cycles)

Read Status Data

VA

t_AS

SA

t_WC

VA

Addresses

CE#

2AAh

555h for chip erase

t_AH

t_GHWL

t_CH

OE#

t_WP

WE#

t_WPH

t_WHWH2

t_CS

t_DS

t_DH

In

Data

Complete

55h

30h

Progress

10 for Chip Erase

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).

2. Illustration shows device in word mode.

21490E-22

Figure 18. Chip/Sector Erase Operation Timings

32

Am29LV800B

P R E L I M I N A R Y

AC CHARACTERISTICS

t_RC

VA

Addresses

VA

t_ACC

t_CE

CE#

t_CH

t_OE

OE#

WE#

t_OEH

t_DF

t_OH

Complement

High Z

DQ7

Valid Data

Complement

Status Data

True

DQ0–DQ6

Valid Data

Status Data

True

t_BUSY

RY/BY#

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data

read cycle.

21490E-23

Figure 19. Data# Polling Timings (During Embedded Algorithms)

t_RC

Addresses

CE#

VA

t_ACC

t_CE

VA

t_CH

t_OE

OE#

WE#

t_OEH

t_DF

t_OH

High Z

DQ6/DQ2

RY/BY#

Valid Status

(first read)

Valid Status

Valid Data

(second read)

(stops toggling)

t_BUSY

Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read

cycle, and array data read cycle.

21490E-24

Figure 20. Toggle Bit Timings (During Embedded Algorithms)

Am29LV800B

33

P R E L I M I N A R Y

AC CHARACTERISTICS

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

Erase

Erase Suspend

Read

Erase

Suspend

Program

Erase

Complete

WE#

Erase

Erase Suspend

Read

DQ6

DQ2

Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an

erase-suspended sector.

21490E-25

Figure 21. DQ2 vs. DQ6

Temporary Sector Unprotect

Parameter

JEDEC

Std

Description

Rise and Fall Time (See Note)

ID

All Speed Options

Unit

t

V

Min

500

ns

VIDR

RESET# Setup Time for Temporary Sector

Unprotect

t

4

µs

RSP

Note: Not 100% tested.

12 V

RESET#

0 or 3 V

t_VIDR

Program or Erase Command Sequence

CE#

WE#

t_RSP

RY/BY#

21490E-26

Figure 22. Temporary Sector Unprotect Timing Diagram

34

Am29LV800B

P R E L I M I N A R Y

AC CHARACTERISTICS

V

ID

IH

RESET#

SA, A6,

A1, A0

Valid*

Sector Protect/Unprotect

60h 60h

Valid*

Status

Verify

40h

Data

Sector Protect: 100 µs

Sector Unprotect: 10 ms

1 µs

CE#

WE#

OE#

* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.

21490E-27

Figure 23. Sector Protect/Unprotect Timing Diagram

Am29LV800B

35

P R E L I M I N A R Y

AC CHARACTERISTICS

Alternate CE# Controlled Erase/Program Operations

Parameter

JEDEC

Std

Description

Write Cycle Time (Note 1)

Address Setup Time

Address Hold Time

70R

80

90

120

Unit

ns

t

Min

70

80

90

120

AVAV

AVEL

ELAX

DVEH

EHDX

WC

t

0

ns

AS

AH

DS

DH

t

45

35

45

35

45

50

ns

t

Data Setup Time

ns

t

Data Hold Time

0

ns

t

Output Enable Setup Time

ns

OES

Read Recovery Time Before Write

(OE# High to WE# Low)

t

Min

0

ns

GHEL

WLEL

GHEL

t

WE# Setup Time

WE# Hold Time

Min

Typ

0

ns

WS

t

EHWH

WH

t

CE# Pulse Width

CE# Pulse Width High

35

50

ELEH

EHEL

CP

t

30

9

CPH

Byte

Word

Programming Operation

(Note 2)

t

µs

WHWH1

11

0.7

t

Sector Erase Operation (Note 2)

sec

WHWH2

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

36

Am29LV800B

P R E L I M I N A R Y

AC CHARACTERISTICS

555 for program

PA for program

2AA for erase

SA for sector erase

555 for chip erase

Data# Polling

Addresses

PA

t_WC

t_WH

t_AS

t_AH

WE#

OE#

t_GHEL

t_{WHWH1 or 2}

t_CP

CE#

Data

t_WS

t_CPH

t_DS

t_BUSY

t_DH

DQ7#

D_OUT

t_RH

A0 for program

55 for erase

PD for program

30 for sector erase

10 for chip erase

RESET#

RY/BY#

Notes:

1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, D

device.

= data written to the

OUT

2. Figure indicates the last two bus cycles of command sequence.

3. Word mode address used as an example.

21490E-28

Figure 24. Alternate CE# Controlled Write Operation Timings

Am29LV800B

37

P R E L I M I N A R Y

ERASE AND PROGRAMMING PERFORMANCE

Parameter

Typ (Note 1)

Max (Note 2)

Unit

s

Comments

Sector Erase Time

Chip Erase Time

0.7

14

9

15

Excludes 00h programming

prior to erasure

s

Byte Programming Time

Word Programming Time

300

360

27

µs

s

11

9

Excludes system level

overhead (Note 5)

Byte Mode

Word Mode

Chip Programming Time

(Note 3)

5.8

17

s

Notes:

1. Typical program and erase times assume the following conditions: 25°C, 3.0 V V , 1,000,000 cycles. Additionally,

CC

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, V = 2.7 V, 1,000,000 cycles.

CC

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See

Table 5 for further information on command definitions.

6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTICS

Description

Min

Max

Input voltage with respect to V on all pins except I/O pins

(including A9, OE#, and RESET#)

SS

–1.0 V

12.5 V

Input voltage with respect to V on all I/O pins

–1.0 V

V

+ 1.0 V

CC

SS

V

Current

–100 mA

+100 mA

CC

Includes all pins except V . Test conditions: V = 3.0 V, one pin at a time.

CC

TSOP AND SO PIN CAPACITANCE

Parameter

Symbol

Parameter Description

Input Capacitance

Test Setup

Typ

6

Max

7.5

12

Unit

pF

C

V

= 0

IN

C

Output Capacitance

Control Pin Capacitance

V

= 0

8.5

7.5

pF

OUT

C

V

= 0

IN

9

pF

IN2

Notes:

1. Sampled, not 100% tested.

2. Test conditions T = 25°C, f = 1.0 MHz.

A

DATA RETENTION

Parameter

Test Conditions

150°C

Min

10

Unit

Years

Minimum Pattern Data Retention Time

125°C

20

38

Am29LV800B

P R E L I M I N A R Y

PHYSICAL DIMENSIONS*

TS 048—48-Pin Standard TSOP (measured in millimeters)

0.95

1.05

Pin 1 I.D.

1

48

11.90

12.10

0.50 BSC

24

25

0.05

0.15

18.30

18.50

19.80

20.20

16-038-TS48-2

TS 048

DT95

0.08

0.20

0.10

1.20

MAX

8-8-96 lv

0.21

0˚

5˚

0.25MM (0.0098") BSC

0.50

0.70

* For reference only. BSC is an ANSI standard for Basic Space Centering.

TSR048—48-Pin Reverse TSOP (measured in millimeters)

0.95

1.05

Pin 1 I.D.

1

48

11.90

12.10

0.50 BSC

24

25

0.05

0.15

18.30

18.50

19.80

20.20

SEATING PLANE

16-038-TS48

TSR048

DT95

0.08

0.20

8-8-96 lv

1.20

MAX

0.10

0.21

0˚

5˚

0.25MM (0.0098") BSC

0.50

0.70

* For reference only. BSC is an ANSI standard for Basic Space Centering.

Am29LV800B

39

P R E L I M I N A R Y

PHYSICAL DIMENSIONS

FGB—48-Ball Fine-Pitch Ball Grid Array (FBGA) 6 x 9 mm (measured in mm)

M

0.15

Z B M

8.80

9.20

DATUM B

5.80

6.20

M

0.15

Z B M

0.025

CHAMFER

INDEX

DATUM A

5.60

BSC

0.40

4.00

BSC

0.80

0.40 ± 0.08 (48x)

0.08

0.40

M

Z A

B

0.10 Z

0.25

0.45

DETAIL A

0.20 Z

1.20 MAX

DETAIL A

16-038-FGB-2

EG137

12-2-97 lv

40

Am29LV800B

P R E L I M I N A R Y

PHYSICAL DIMENSIONS

SO 044—44-Pin Small Outline Package (measured in millimeters)

44

23

13.10

13.50

15.70

16.30

1

22

1.27 NOM.

TOP VIEW

28.00

28.40

0.10

0.21

2.17

2.45

2.80

MAX.

0˚

8˚

SEATING

PLANE

0.60

1.00

0.35

0.50

0.10

0.35

END VIEW

SIDE VIEW

16-038-SO44-2

SO 044

DF83

8-8-96 lv

Am29LV800B

41

P R E L I M I N A R Y

REVISION SUMMARY FOR AM29LV800B

Revision E

Revision E+1

Distinctive Characteristics

Figure 2, In-System Sector Protect/Unprotect

Algorithms

Changed typical read and program/erase current spec-

ifications.

In the sector protect algorithm, added a “Reset

PLSCNT=1” box in the path from “Protect another sec-

tor?” back to setting up the next sector address.

Device now has a guaranteed minimum endurance of

1,000,000 write cycles.

DC Characteristics

Figure 1, In-System Sector Protect/Unprotect

Algorithm

Changed Note 1 to indicate that OE# is at V_IHfor the

listed current.

Corrected A6 to 0, Changed wait specification to 150

µs on sector protect and 15 ms on sector unprotect.

AC Characteristics

Erase/Program Operations; Alternate CE# Controlled

Erase/Program Operations: Corrected the notes refer-

ence for t_WHWH1and t_WHWH2. These parameters are

DC Characteristics

Changed typical read and program/erase current spec-

ifications.

100% tested. Corrected the note reference for t_VCS

This parameter is not 100% tested.

.

AC Characteristics

Alternate CE# Controlled Erase/Program Operations:

Changed t_CPto 35 ns for 70R, 80, and 90 speed

options.

Temporary Sector Unprotect Table

Added note reference for t_VIDR. This parameter is not

100% tested.

Erase and Programming Performance

Figure 23, Sector Protect/Unprotect Timing

Diagram

Device now has a guaranteed minimum endurance of

1,000,000 write cycles.

A valid address is not required for the first write cycle;

only the data 60h.

Physical Dimensions

Corrected dimensions for package length and width in

FBGA illustration (standalone data sheet version).

Erase and Programming Performance

In Note 2, the worst case endurance is now 1 million cy-

cles.

Trademarks

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

ExpressFlash is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

42

Am29LV800B


型号：	AM29LV800BT120WBEB
厂家：	AMD
描述：	8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory 8兆位（ 1一M× 8位/ 512的K× 16位） CMOS 3.0伏只引导扇区闪存闪存
文件：	总42页 (文件大小：535K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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