AM29PL160CB-65REI_技术文档

Am29PL160C

16 Megabit (2 M x 8-Bit/1 M x 16-Bit)

CMOS 3.0 Volt-only High Performance Page Mode Flash Memory

DISTINCTIVE CHARACTERISTICS

■ 16 Mbit Page Mode device

■ Sector Protection

— Byte (8-bit) or word (16-bit) mode selectable via

BYTE# pin

— A hardware method of locking a sector to prevent

any program or erase operations within that

sector

— Page size of 16 bytes/8 words: Fast page read

access from random locations within the page

— Sectors can be locked via programming

equipment

■ Single power supply operation

— Temporary Sector Unprotect command

sequence allows code changes in previously

locked sectors

— Full voltage range: 2.7 to 3.6 volt read and write

operations for battery-powered applications

— Regulated voltage range: 3.0 to 3.6 volt read

and write operations and for compatibility with

high performance 3.3 volt microprocessors

■ Minimum 1 million write cycles guarantee

per sector

■ 20-year data retention

■ 5 V-tolerant data, address, and control signals

■ High performance read access times

■ Manufactured on 0.32 µm process technology

■ Software command-set compatible with JEDEC

— Page access times as fast as 25 ns at industrial

temperature range

standard

— Backward compatible with Am29F and Am29LV

families

— Random access times as fast as 65 ns

■ Power consumption (typical values at 5 MHz)

— 30 mA read current

■ CFI (Common Flash Interface) compliant

— Provides device-specific information to the

system, allowing host software to easily

reconfigure for different Flash devices

— 20 mA program/erase current

— 1 µA standby mode current

■ Unlock Bypass Program Command

— 1 µA Automatic Sleep mode current

■ Flexible sector architecture

— Reduces overall programming time when

issuing multiple program command sequences

— Sector sizes: One 16 Kbyte, two 8 Kbyte, one

224 Kbyte, and seven sectors of 256 Kbytes

each

■ Erase Suspend/Erase Resume

— Suspends an erase operation to read data from,

or program data to, a sector that is not being

erased, then resumes the erase operation

— Supports full chip erase

■ Bottom boot block configuration only

■ Package Options

— 44-pin SO (mask-ROM compatible pinout)

— 48-pin TSOP

Publication# 22143 Rev: C Amendment/+4

Issue Date: June 12, 2002

This Data Sheet states AMD’s current specifications regarding the Products described herein. This Data Sheet may

be revised by subsequent versions or modifications due to changes in technical specifications.

Refer to AMD’s Website (www.amd.com) for the latest information.

GENERAL DESCRIPTION

The Am29PL160C is a 16 Mbit, 3.0 Volt-only Page

mode Flash memory device organized as 2,097,152

bytes or 1,048,576 words.The device is offered in a

44-pin SO or a 48-pin TSOP package. The word-wide

data (x16) appears on DQ15–DQ0; the byte-wide (x8)

data appears on DQ7–DQ0. This device can be pro-

grammed in-system or with in standard

verifies proper cell margin. The Unlock Bypass mode

facilitates faster programming times by requiring only

two write cycles to program data instead of four.

Device erasure occurs by executing the erase com-

mand sequence. This initiates the Embedded Erase

algorithm—an internal algorithm that automatically

preprograms the array (if it is not already programmed)

before executing the erase operation. During erase,

the device automatically times the erase pulse widths

and verifies proper cell margin.

EPROM programmers. A 12.0 V V or 5.0 V

are

PP

CC

not required for write or erase operations.

The device offers access times of 65, 70, 90, and 120

ns, allowing high speed microprocessors to operate

without wait states. To eliminate bus contention the de-

vice has separate chip enable (CE#), write enable

(WE#), and output enable (OE#) controls.

The host system can detect whether a program or

erase operation is complete by reading the DQ7

(Data# Polling) and DQ6 (toggle) status bits. After a

program or erase cycle has been completed, the de-

vice is ready to read array data or accept another

command.

The sector sizes are as follows: one 16 Kbyte, two

8 Kbyte, one 224 Kbyte and seven sectors of

256 Kbytes each. The device is available in both top

and bottom boot versions.

The sector erase architecture allows memory sec-

tors to be erased and reprogrammed without affecting

the data contents of other sectors. The device is fully

erased when shipped from the factory.

Page Mode Features

The device is AC timing, pinout, and package compat-

ible with 16 Mbit x 16 page mode Mask ROM. The

page size is 8 words or 16 bytes.

Hardware data protection measures include a low

V

detector that automatically inhibits write opera-

CC

tions during power transitions. The hardware sector

protection feature disables both program and erase

operations in any combination of the sectors of mem-

ory. This can be achieved in-system or via

programming equipment.

After initial page access is accomplished, the page

mode operation provides fast read access speed of

random locations within that page.

Standard Flash Memory Features

The Erase Suspend/Erase Resume feature enables

the user to put erase on hold for any period of time to

read data from, or program data to, any sector that is

not selected for erasure. True background erase can

thus be achieved.

The device requires only a single 3.0 volt power sup-

ply for both read and write functions. Internally

generated and regulated voltages are provided for the

program and erase operations.

The device is entirely command set compatible with

the JEDEC single-power-supply Flash standard.

Commands are written to the command register using

standard microprocessor write timings. Register con-

tents serve as input to an internal state-machine that

controls the erase and programming circuitry. Write cy-

cles also internally latch addresses and data needed

for the programming and erase operations. Reading

data out of the device is similar to reading from other

Flash or EPROM devices.

The device offers two power-saving features. When

addresses have been stable for a specified amount of

time, the device enters the automatic sleep mode.

The system can also place the device into the standby

mode. Power consumption is greatly reduced in both

these modes.

AMD’s Flash technology combines years of Flash

memory manufacturing experience to produce the

highest levels of quality, reliability and cost effective-

ness. The device electrically erases all bits within a

sector simultaneously via Fowler-Nordheim tunneling.

The data is programmed using hot electron injection.

Device programming occurs by executing the program

command sequence. This initiates the Embedded

Program algorithm—an internal algorithm that

automatically times the program pulse widths and

2

Am29PL160C

June 12, 2002

TABLE OF CONTENTS

Product Selector Guide . . . . . . . . . . . . . . . . . . . . .4

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . .5

Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . 6

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Ordering Information . . . . . . . . . . . . . . . . . . . . . . .7

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .8

Table 1. Am29PL160C Device Bus Operations ................................8

Word/Byte Configuration .......................................................... 8

Requirements for Reading Array Data ..................................... 8

Read Mode ............................................................................... 8

Random Read (Non-Page Mode Read) ............................................8

Page Mode Read ...................................................................... 9

Table 2. Word Mode ..........................................................................9

Table 3. Byte Mode ...........................................................................9

Writing Commands/Command Sequences ............................ 10

Program and Erase Operation Status .................................... 10

Standby Mode ........................................................................ 10

Automatic Sleep Mode ........................................................... 10

Output Disable Mode .............................................................. 10

Table 4. Sector Address Table, Bottom Boot (Am29PL160CB) ......11

Autoselect Mode ..................................................................... 12

Table 5. Am29PL160C Autoselect Codes (High Voltage Method) ..12

Sector Protection/Unprotection ............................................... 12

Common Flash Memory Interface (CFI). . . . . . . 13

Table 6. CFI Query Identification String ..........................................13

Table 7. System Interface String .....................................................14

Table 8. Device Geometry Definition ..............................................14

Table 9. Primary Vendor-Specific Extended Query ........................15

Hardware Data Protection. . . . . . . . . . . . . . . . . . 15

DQ5: Exceeded Timing Limits ................................................22

Figure 4. Toggle Bit Algorithm........................................................ 23

DQ3: Sector Erase Timer .......................................................23

Table 11. Write Operation Status ................................................... 24

Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 25

Figure 5. Maximum Negative Overshoot Waveform ...................... 25

Figure 6. Maximum Positive Overshoot Waveform........................ 25

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 25

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 7. I

Current vs. Time (Showing Active and Automatic

CC1

Sleep Currents).............................................................................. 27

Figure 8. Typical I vs. Frequency ............................................. 27

CC1

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 9. Test Setup....................................................................... 28

Table 12. Test Specifications ......................................................... 28

Key to Switching Waveforms . . . . . . . . . . . . . . . 28

Figure 10. Input Waveforms and Measurement Levels ................. 28

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 11. Conventional Read Operations Timings ....................... 30

Figure 12. Page Read Timings ...................................................... 30

Figure 13. BYTE# Timings for Read Operations............................ 31

Figure 14. BYTE# Timings for Write Operations............................ 31

Figure 15. Program Operation Timings.......................................... 33

Figure 16. AC Waveforms for Chip/Sector Erase Operations........ 34

Figure 17. Data# Polling Timings (During Embedded Algorithms). 34

Figure 18. Toggle Bit Timings (During Embedded Algorithms)...... 35

Figure 19. DQ2 vs. DQ6 for Erase and

Erase Suspend Operations............................................................ 35

Figure 20. Alternate CE# Controlled Write Operation Timings ...... 37

Erase and Programming Performance . . . . . . . 38

Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 38

TSOP and SO Pin Capacitance . . . . . . . . . . . . . . 38

Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 39

TS 048—48-Pin Standard Thin Small Outline Package ......... 39

SO 044—44-Pin Small Outline Package, Standard Pinout .... 40

SOR044—44-Pin Small Outline Package, Reverse Pinout .... 41

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 42

Revision A (August 1998) .......................................................42

Revision A+1 (September 1998) ............................................42

Revision B (January 1999) .....................................................42

Revision B+1 (February 1999) ................................................42

Revision B+2 (March 5, 1999) ................................................42

Revision B+3 (May 14, 1999) .................................................42

Revision B+4 (June 25, 1999) ................................................42

Revision B+5 (July 26, 1999) ..................................................42

Revision B+6 (September 2, 1999) ........................................ 42

Revision B+7 (February 4, 2000) ............................................42

Revision C (February 21, 2000) .............................................. 42

Revision C+1 (June 20, 2000) ................................................42

Revision C+2 (June 28, 2000) ................................................42

Revision C+3 (November 14, 2000) ....................................... 42

Revision C+4 (June 12, 2002) ................................................42

Low V Write Inhibit ......................................................................15

CC

Write Pulse “Glitch” Protection ........................................................15

Logical Inhibit ..................................................................................15

Power-Up Write Inhibit ....................................................................15

Command Definitions . . . . . . . . . . . . . . . . . . . . . .16

Reading Array Data ................................................................ 16

Reset Command ..................................................................... 16

Autoselect Command Sequence ............................................ 16

Word/Byte Program Command Sequence ............................. 16

Unlock Bypass Command Sequence ..............................................17

Figure 1. Program Operation .......................................................... 17

Chip Erase Command Sequence ........................................... 17

Sector Erase Command Sequence ........................................ 18

Erase Suspend/Erase Resume Commands ........................... 18

Temporary Unprotect Enable/Disable Command Sequence .. 19

Figure 2. Erase Operation............................................................... 19

Command Definitions ............................................................. 20

Table 10. Am29PL160C Command Definitions ..............................20

Write Operation Status . . . . . . . . . . . . . . . . . . . . 21

DQ7: Data# Polling ................................................................. 21

Figure 3. Data# Polling Algorithm ................................................... 21

DQ6: Toggle Bit ...................................................................... 22

DQ2: Toggle Bit ...................................................................... 22

Reading Toggle Bits DQ6/DQ2 .............................................. 22

June 12, 2002

Am29PL160C

3

PRODUCT SELECTOR GUIDE

Family Part Number

Am29PL160C

-70R

Regulated Voltage Range: V =3.0–3.6 V

-65R

CC

Speed Option

Full Voltage Range: V = 2.7–3.6 V

-90

90

30

-120

120

30

CC

Max access time, ns (t

)

65

25

70

25

ACC

Max CE# access time, ns (t

)

CE

Max page access time, ns (t

)

PACC

Max OE# access time, ns (t

)

30

OE

Note: See “AC Characteristics” for full specifications.

BLOCK DIAGRAM

DQ0–DQ15

V

CC

V

SS

Erase Voltage

Generator

Input/Output

Buffers

State

Control

WE#

BYTE#

Command

Register

PGM Voltage

Generator

Data

Latch

Chip Enable

Output Enable

Logic

STB

CE#

OE#

Y-Decoder

Y-Gating

STB

V

Detector

Timer

CC

Cell Matrix

X-Decoder

A0–A19

A-1

4

Am29PL160C

June 12, 2002

CONNECTION DIAGRAMS

BYTE#

A16

A15

A14

A13

A12

A11

A10

A9

1

2

3

4

5

6

7

8

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

NC

V_SS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

9

A8

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

48-pin Standard TSOP

A19

WE#

NC

A18

A17

A7

A6

A5

A4

A3

A2

A1

A0

CE#

V_CC

V_SS

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

V_SS

NC

WE#

1

2

3

4

5

6

7

8

9

44 NC

NC

A19

A8

1

2

3

4

5

6

7

8

9

44 WE#

43 A18

42 A17

41 A7

A18

A17

A7

43 A19

42 A8

41 A9

A9

A6

40 A10

39 A11

38 A12

37 A13

36 A14

35 A15

34 A16

33 BYTE#

32 V_SS

A10

A11

A12

A13

A14

A15 10

A16 11

40 A6

A5

39 A5

A4

38 A4

A3

37 A3

A2

36 A2

A1 10

A0 11

35 A1

44-Pin

Standard SO

44-Pin

Reverse SO

34 A0

CE# 12

V_SS13

BYTE# 12

V_SS13

DQ15/A-1 14

DQ7 15

33 CE#

32 V_SS

31 OE#

30 DQ0

29 DQ8

28 DQ1

27 DQ9

26 DQ2

25 DQ10

24 DQ3

23 DQ11

OE# 14

DQ0 15

DQ8 16

DQ1 17

DQ9 18

DQ2 19

DQ10 20

DQ3 21

DQ11 22

31 DQ15/A-1

30 DQ7

29 DQ14

28 DQ6

27 DQ13

26 DQ5

25 DQ12

24 DQ4

23 V_CC

DQ14 16

DQ6 17

DQ13 18

DQ5 19

DQ12 20

DQ4 21

V_CC22

June 12, 2002

Am29PL160C

5

PIN CONFIGURATION

LOGIC SYMBOL

A0–A19

= 20 address inputs

20

DQ0–DQ15 = 16 data inputs/outputs

A0–A19

16 or 8

DQ15/A-1

BYTE#

=

In word mode, functions as DQ15

(MSB data input/output)

In byte mode, functions as A-1

(LSB address input)

DQ0–DQ15

(A-1)

CE#

OE#

Byte enable input

When low, enables byte mode

When high, enables word mode

WE#

BYTE#

CE#

OE#

WE#

=

Chip Enable input

Output Enable input

Write Enable input

V

3.0 volt-only single power supply

CC

(see Product Selector Guide for speed

options and voltage supply tolerances)

V

=

Device ground

SS

NC

Pin not connected internally

6

Am29PL160C

June 12, 2002

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combi-

nation) is formed by a combination of the elements below.

Am29PL160C

B

-65R

S

I

TEMPERATURE RANGE

Industrial (–40°C to +85°C)

I

=

PACKAGE TYPE

E

=

48-Pin Standard Thin Small Outline Package (TS 048)

(bottom boot devices only)

S

=

44-Pin Small Outline Package, Standard Pinout (SO 044)

44-Pin Small Outline Package, Reverse Pinout (SOR044)

SK

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

B

=

Bottom Sector

DEVICE NUMBER/DESCRIPTION

Am29PL160C

16 Megabit (1 M x 16-Bit)

CMOS 3.0 Volt-only High Performance Page Mode Flash Memory

Valid Combinations

(Bottom Boot)

Voltage Range

Valid Combinations list configurations planned to be sup-

ported in volume for this device. Consult the local AMD sales

office to confirm availability of specific valid combinations and

to check on newly released combinations.

AM29PL160CB-65R

V

= 3.0–3.6 V

= 2.7–3.6 V

CC

AM29PL160CB-70R

AM29PL160CB-90

AM29PL160CB-120

EI, SI, SKI

June 12, 2002

Am29PL160C

7

DEVICE BUS OPERATIONS

This section describes the requirements and use of the

device bus operations, which are initiated through the

internal command register. The command register it-

self does not occupy any addressable memory

location. The register is composed of latches that store

the commands, along with the address and data infor-

mation needed to execute the command. The contents

of the register serve as inputs to the internal state ma-

chine. The state machine outputs dictate the function

of the device. Table 1 lists the device bus operations,

the inputs and control levels they require, and the re-

sulting output. The following subsections describe

each of these operations in further detail.

Table 1. Am29PL160C Device Bus Operations

DQ8–DQ15

BYTE#

= V

Addresses

(Note 1)

DQ0–

DQ7

BYTE#

Operation

CE#

OE# WE#

= V

IH

IL

Read

Write

L

H

L

A

D

DQ8–DQ14 = High-Z,

DQ15 = A-1

IN

OUT

H

A

D

IN

V

0.3 V

±

CC

Standby

X

H

X

H

X

High-Z

Output Disable

L

X

High-Z

Legend:

L = Logic Low = V , H = Logic High = V , V = 12.0 ± 0.5 V, X = Don’t Care, A = Address In, D = Data In, D = Data Out

IL

IH

ID

IN

OUT

Notes:

1. Addresses are A19:A0 in word mode (BYTE# = V ), A19:A-1 in byte mode (BYTE# = V ).

IH

IL

2. The sector protect and sector unprotect functions must be implemented via programming equipment. See the “Sector

Protection/Unprotection” section.

Standard microprocessor read cycles that assert valid

Word/Byte Configuration

addresses on the device address inputs produce valid

The BYTE# pin controls whether the device data I/O

data on the device data outputs. The device remains

pins DQ15–DQ0 operate in the byte or word configura-

enabled for read access until the command register

tion. If the BYTE# pin is set at logic ‘1’, the device is in

contents are altered.

word configuration, DQ15–DQ0 are active and con-

trolled by CE# and OE#.

See “Reading Array Data” for more information. Refer

to the AC Read Operations table for timing specifica-

If the BYTE# pin is set at logic ‘0’, the device is in byte

configuration, and only data I/O pins DQ0–DQ7 are

active and controlled by CE# and OE#. The data I/O

pins DQ8–DQ14 are tri-stated, and the DQ15 pin is

used as an input for the LSB (A-1) address function.

tions and to Figure 11 for the timing diagram. I

in

CC1

the DC Characteristics table represents the active cur-

rent specification for reading array data.

Read Mode

Random Read (Non-Page Mode Read)

Requirements for Reading Array Data

The device has two control functions which must be

satisfied in order to obtain data at the outputs. CE# is

the power control and should be used for device selec-

tion. OE# is the output control and should be used to

gate data to the output pins if the device is selected.

To read array data from the outputs, the system must

drive the CE# and OE# pins to V . CE# is the power

IL

control and selects the device. OE# is the output control

and gates array data to the output pins. WE# should re-

main at V . The BYTE# pin determines whether the

IH

device outputs array data in words or bytes.

Address access time (t

) is equal to the delay from

ACC

stable addresses to valid output data. The chip enable

The internal state machine is set for reading array data

upon device power-up, or after a reset command

(when not executing a program or erase operation).

This ensures that no spurious alteration of the memory

content occurs during the power transition. No com-

mand is necessary in this mode to obtain array data.

access time (t ) is the delay from the stable ad-

CE

dresses and stable CE# to valid data at the output

pins. The output enable access time is the delay from

the falling edge of OE# to valid data at the output pins

(assuming the addresses have been stable for at least

t

–t time).

ACC OE

8

Am29PL160C

June 12, 2002

Table 2. Word Mode

Page Mode Read

The Am29PL160C is capable of fast Page mode read

and is compatible with the Page mode Mask ROM

read operation. This mode provides faster read access

speed for random locations within a page. The Page

size of the Am29PL160C device is 8 words, or 16

bytes, with the appropriate Page being selected by the

higher address bits A3–A19 and the LSB bits A0–A2

(in the word mode) and A-1 to A2 (in the byte mode)

determining the specific word/byte within that page.

This is an asynchronous operation with the micropro-

cessor supplying the specific word or byte location.

Word

A2

0

A1

0

A0

0

Word 0

Word 1

Word 2

Word 3

Word 4

Word 5

Word 6

Word 7

0

1

0

1

0

1

0

1

0

1

0

The random or initial page access is equal to t

or

ACC

1

t

and subsequent Page read accesses (as long as

CE

the locations specified by the microprocessor falls

within that Page) is equivalent to t . When CE# is

Table 3. Byte Mode

PACC

deasserted and reasserted for a subsequent access,

the access time is t or t . Here again, CE# selects

Byte

A2

0

1

A1

0

1

0

1

A0

0

1

0

1

0

1

0

1

A-1

0

ACC

CE

the device and OE# is the output control and should be

used to gate data to the output pins if the device is se-

lected. Fast Page mode accesses are obtained by

keeping A3–A19 constant and changing A0 to A2 to

select the specific word, or changing A-1 to A2 to se-

lect the specific byte, within that page.

Byte 0

Byte 1

Byte 2

Byte 3

Byte 4

Byte 5

Byte 6

Byte 7

Byte 8

Byte 9

Byte 10

Byte 11

Byte 12

Byte 13

Byte 14

Byte 15

1

0

1

0

The following tables determine the specific word and

byte within the selected page:

1

0

1

0

1

0

1

0

1

0

1

June 12, 2002

Am29PL160C

9

bits on DQ7–DQ0. Standard read cycle timings and

read specifications apply. Refer to “Write Opera-

tion Status” for more information, and to “AC

Characteristics” for timing diagrams.

Writing Commands/Command Sequences

I

CC

To write a command or command sequence (which in-

cludes programming data to the device and erasing

sectors of memory), the system must drive WE# and

CE# to V , and OE# to V .

IL

IH

Standby Mode

For program operations, the BYTE# pin determines

whether the device accepts program data in bytes

or words. Refer to “Word/Byte Configuration” for

more information.

When the system is not reading or writing to the de-

vice, it can place the device in the standby mode. In

this mode, current consumption is greatly reduced,

and the outputs are placed in the high impedance

state, independent of the OE# input.

The device features an Unlock Bypass mode to facili-

tate faster programming. Once the device enters the

Unlock Bypass mode, only two write cycles are required

to program a word or byte, instead of four. The

“Word/Byte Program Command Sequence” section has

details on programming data to the device using both

standard and Unlock Bypass command sequences.

The device enters the CMOS standby mode when the

CE# pin is both held at V ± 0.3 V. (Note that this is a

CC

more restricted voltage range than V .) If CE# is held

IH

at V , but not within V ± 0.3 V, the device will be in

IH

CC

the standby mode, but the standby current will be

greater. The device requires standard access time

(t ) for read access when the device is in either of

these standby modes, before it is ready to read data.

An erase operation can erase one sector, multiple sec-

tors, or the entire device. Table 4 indicates the address

space that each sector occupies. A “sector address”

consists of the address bits required to uniquely select

a sector. The “Command Definitions” section has de-

tails on erasing a sector or the entire chip, or

suspending/resuming the erase operation.

CE

If the device is deselected during erasure or program-

ming, the device draws active current until the

operation is completed.

Automatic Sleep Mode

After the system writes the autoselect command se-

quence, the device enters the autoselect mode. The

system can then read autoselect codes from the internal

register (which is separate from the memory array) on

DQ7–DQ0. Standard read cycle timings apply in this

mode. Refer to the “Autoselect Mode” and “Autoselect

Command Sequence” sections for more information.

The automatic sleep mode minimizes Flash device en-

ergy consumption. The device automatically enables this

mode when addresses remain stable for tACC + 30 ns.

The automatic sleep mode is independent of the CE#,

WE#, and OE# control signals. Standard address access

timings provide new data when addresses are changed.

While in sleep mode, output data is latched and always

available to the system. Note that during Automatic Sleep

mode, OE# must be at VIH before the device reduces

current to the stated sleep mode specification.

I

in the DC Characteristics table represents the ac-

CC2

tive current specification for the write mode. The “AC

Characteristics” section contains timing specification

tables and timing diagrams for write operations.

Output Disable Mode

Program and Erase Operation Status

When the OE# input is at V , output from the device is

disabled. The output pins are placed in the high imped-

ance state.

IH

During an erase or program operation, the system may

check the status of the operation by reading the status

10

Am29PL160C

June 12, 2002

Table 4. Sector Address Table, Bottom Boot (Am29PL160CB)

Sector Size

(Kbytes/

Address Range (in hexadecimal)

Sector A19 A18 A17 A16 A15 A14 A13 A12

Kwords)

Byte Mode (x8)

000000–003FFF

004000–005FFF

006000–007FFF

008000–03FFFF

040000–07FFFF

080000–0BFFFF

0C0000–0FFFFF

100000–13FFFF

140000–17FFFF

180000–1BFFFF

1C0000–1FFFFF

Word Mode (x16)

00000–01FFF

02000–02FFF

03000–03FFF

04000–1FFFF

20000–3FFFF

40000–5FFFF

60000–7FFFF

80000–9FFFF

A0000–BFFFF

C0000–DFFFF

E0000–FFFFF

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

0

1

16/8

8/4

01000–11111

224/112

256/128

X

June 12, 2002

Am29PL160C

11

Table 5. In addition, when verifying sector protection,

the sector address must appear on the appropriate

highest order address bits (Table 4). Table 5 shows the

remaining address bits that are don’t care. When all

necessary bits have been set as required, the pro-

gramming equipment may then read the

corresponding identifier code on DQ7-DQ0.

Autoselect Mode

The autoselect mode provides manufacturer and de-

vice identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This

mode is primarily intended for programming equipment

to automatically match a device to be programmed

with its corresponding programming algorithm. How-

ever, the autoselect codes can also be accessed in-

system through the command register.

To access the autoselect codes in-system, the host

system can issue the autoselect command via the

command register, as shown in Table 10. This method

When using programming equipment, the autoselect

does not require V . See “Command Definitions” for

ID

mode requires V (11.5 V to 12.5 V) on address pin

ID

details on using the autoselect mode.

A9. Address pins A6, A1, and A0 must be as shown in

Table 5. Am29PL160C Autoselect Codes (High Voltage Method)

A19 A11

to to

Mode CE# OE# WE# A12 A10 A9

A8

to

A7

A5

to

A2

DQ8

to

A0 DQ15

DQ7

to

DQ0

Description

A6

A1

Manufacturer ID: AMD

L

H

X

V

X

L

X

L

X

01h

45h

ID

Device ID:

Am29PL160C

(Bottom Boot Block)

Word

Byte

22h

X

V

L

H

ID

L

H

X

45h

01h

(protected)

Sector Protection Verification

L

H

SA

X

V

X

H

L

ID

00h

(unprotected)

X

L = Logic Low = V , H = Logic High = V , SA = Sector Address, X = Don’t care.

IL

IH

Note: The autoselect codes may also be accessed in-system via command sequences. See Table 10.

It is possible to determine whether a sector is protected

or unprotected. See “Autoselect Mode” for details.

Sector Protection/Unprotection

The hardware sector protection feature disables both

program and erase operations in any sector.

The hardware sector unprotection feature re-enables

both program and erase operations in previously

protected sectors.

Sector protection and unprotection must be imple-

mented using programming equipment. The procedure

requires V on address pin A9 and OE#. Details on

ID

this method are provided in a supplement, publication

number 22239. Contact an AMD representative to re-

quest a copy.

The device is shipped with all sectors unprotected.

AMD offers the option of programming and protecting

sectors at its factory prior to shipping the device

through AMD’s ExpressFlash™ Service. Contact an

AMD representative for details.

The device features a temporary unprotect command

sequence to allow changing array data in-system. See

“Temporary Unprotect Enable/Disable Command Se-

quence” for more information.

12

Am29PL160C

June 12, 2002

can read CFI information at the addresses given in Ta-

bles 6–9. To terminate reading CFI data, the system

must write the reset command.

COMMON FLASH MEMORY INTERFACE

(CFI)

The Common Flash Interface (CFI) specification out-

lines device and host system software interrogation

handshake, which allows specific vendor-specified

software algorithms to be used for entire families of de-

vices. Software support can then be device-

independent, JEDEC ID-independent, and forward-

and backward-compatible for the specified flash de-

vice families. Flash vendors can standardize their

existing interfaces for long-term compatibility.

The system can also write the CFI query command

when the device is in the autoselect mode. The device

enters the CFI query mode, and the system can read

CFI data at the addresses given in Tables 6–9. The

system must write the reset command to return the de-

vice to the autoselect mode.

For further information, please refer to the CFI Specifi-

cation and CFI Publication 100, available via the World

Wide Web at http://www.amd.com/products/nvd/over-

view/cfi.html. Alternatively, contact an AMD

representative for copies of these documents.

This device enters the CFI Query mode when the sys-

tem writes the CFI Query command, 98h, to address

55h in word mode (or address AAh in byte mode), any

time the device is ready to read array data. The system

Table 6. CFI Query Identification String

Addresses

(Word Mode)

(Byte Mode)

Data

Description

10h

11h

12h

20h

22h

24h

0051h

0052h

0059h

Query Unique ASCII string “QRY”

13h

14h

26h

28h

0002h

0000h

Primary OEM Command Set

15h

16h

2Ah

2Ch

0040h

0000h

Address for Primary Extended Table

17h

18h

2Eh

30h

0000h

Alternate OEM Command Set (00h = none exists)

Address for Alternate OEM Extended Table (00h = none exists)

19h

1Ah

32h

34h

0000h

June 12, 2002

Am29PL160C

13

Table 7. System Interface String

Data Description

Addresses

(Word Mode)

Addresses

(Byte Mode)

V

Min. (write/erase)

CC

1Bh

36h

0027h

D7–D4: volt, D3–D0: 100 millivolt

1Ch

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

38h

3Ah

3Ch

3Eh

40h

42h

44h

46h

48h

4Ah

4Ch

0036h

0000h

0004h

0000h

000Ah

0000h

0005h

0000h

0004h

0000h

V

Max. (write/erase), D7–D4: volt, D3–D0: 100 millivolt

CC

PP

Min. voltage (00h = no V pin present)

PP

Max. voltage (00h = no V pin present)

PP

N

Typical timeout per single byte/word write 2 µs

N

Typical timeout for Min. size buffer write 2 µs (00h = not supported)

N

Typical timeout per individual block erase 2 ms

N

Typical timeout for full chip erase 2 ms (00h = not supported)

N

Max. timeout for byte/word write 2 times typical

N

Max. timeout for buffer write 2 times typical

N

Max. timeout per individual block erase 2 times typical

N

Max. timeout for full chip erase 2 times typical (00h = not supported)

Table 8. Device Geometry Definition

Addresses

(Word Mode)

(Byte Mode)

Data

Description

N

27h

4Eh

0015h

Device Size = 2 byte

28h

29h

50h

52h

0002h

0000h

Flash Device Interface description (refer to CFI publication 100)

N

2Ah

2Bh

54h

56h

0000h

Max. number of bytes in multi-byte write = 2

(00h = not supported)

2Ch

58h

0004h

Number of Erase Block Regions within device

2Dh

2Eh

2Fh

30h

5Ah

5Ch

5Eh

60h

0000h

0040h

0000h

Erase Block Region 1 Information

(refer to the CFI specification or CFI publication 100)

31h

32h

33h

34h

62h

64h

66h

68h

0001h

0000h

0020h

0000h

Erase Block Region 2 Information

Erase Block Region 3 Information

Erase Block Region 4 Information

35h

36h

37h

38h

6Ah

6Ch

6Eh

70h

0000h

0080h

0003h

39h

3Ah

3Bh

3Ch

72h

74h

76h

78h

0006h

0000h

0004h

14

Am29PL160C

June 12, 2002

Table 9. Primary Vendor-Specific Extended Query

Addresses

(Word Mode)

(Byte Mode)

Data

Description

40h

41h

42h

80h

82h

84h

0050h

0052h

0049h

Query-unique ASCII string “PRI”

43h

44h

86h

88h

0031h

0030h

Major version number, ASCII

Minor version number, ASCII

Address Sensitive Unlock

0 = Required, 1 = Not Required

45h

46h

47h

48h

8Ah

8Ch

8Eh

90h

0000h

0002h

0001h

Erase Suspend

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

Sector Protect

0 = Not Supported, X = Number of sectors in per group

Sector Temporary Unprotect

00 = Not Supported, 01 = Supported

Sector Protect/Unprotect scheme

49h

4Ah

4Bh

4Ch

92h

94h

96h

98h

0004h

0000h

0002h

01 = 29F040 mode, 02 = 29F016 mode,

03 = 29F400 mode, 04 = 29LV800A mode

Simultaneous Operation

00 = Not Supported, 01 = Supported

Burst Mode Type

00 = Not Supported, 01 = 4 Word Linear Burst, 02 = 8 Word Linear Burst,

03 = 32 Linear Burst, 04 = 4 Word Interleave Burst

Page Mode Type

00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

vide the proper signals to the control pins to prevent

HARDWARE DATA PROTECTION

unintentional writes when V is greater than V

.

CC

LKO

The command sequence requirement of unlock cycles

for programming or erasing provides data protection

against inadvertent writes (refer to Table 10 for com-

mand definitions). In addition, the following hardware

data protection measures prevent accidental erasure

or programming, which might otherwise be caused by

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or

WE# do not initiate a write cycle.

Logical Inhibit

spurious system level signals during V

and power-down transitions, or from system noise.

power-up

Write cycles are inhibited by holding any one of OE# =

CC

V , CE# = V or WE# = V . To initiate a write cycle,

IL

IH

CE# and WE# must be a logical zero while OE# is a

logical one.

Low V Write Inhibit

CC

When V

is less than V

, the device does not ac-

LKO

CC

Power-Up Write Inhibit

cept any write cycles. This protects data during V

CC

power-up and power-down. The command register

and all internal program/erase circuits are disabled,

and the device resets. Subsequent writes are ignored

If WE# = CE# = V and OE# = V during power up,

IL

IH

the device does not accept commands on the rising

edge of WE#. The internal state machine is automati-

cally reset to reading array data on power-up.

until V

is greater than V

. The system must pro-

CC

LKO

June 12, 2002

Am29PL160C

15

COMMAND DEFINITIONS

Writing specific address and data commands or se-

quences into the command register initiates device

operations. Table 10 defines the valid register com-

mand sequences. Writing incorrect address and

data values or writing them in the improper se-

quence resets the device to reading array data.

The reset command may be written between the se-

quence cycles in an autoselect command sequence.

Once in the autoselect mode, the reset command must

be written to return to reading array data (also applies

to autoselect during Erase Suspend).

If DQ5 goes high during a program or erase operation,

writing the reset command returns the device to read-

ing array data (also applies during Erase Suspend).

All addresses are latched on the falling edge of WE# or

CE#, whichever happens later. All data is latched on

the rising edge of WE# or CE#, whichever happens

first. Refer to the appropriate timing diagrams in the

“AC Characteristics” section.

Autoselect Command Sequence

The autoselect command sequence allows the host

system to access the manufacturer and devices

codes, and determine whether or not a sector is pro-

tected. Table 10 shows the address and data

requirements. This method is an alternative to that

shown in Table 5, which is intended for PROM pro-

Reading Array Data

The device is automatically set to reading array data

after device power-up. No commands are required to

retrieve data. The device is also ready to read array

data after completing an Embedded Program or Em-

bedded Erase algorithm.

grammers and requires V on address bit A9.

ID

The autoselect command sequence is initiated by writ-

ing two unlock cycles, followed by the autoselect

command. The device then enters the autoselect mode,

and the system may read at any address any number of

times, without initiating another command sequence.

After the device accepts an Erase Suspend command,

the device enters the Erase Suspend mode. The sys-

tem can read array data using the standard read

timings, except that if it reads at an address within

erase-suspended sectors, the device outputs status

data. After completing a programming operation in the

Erase Suspend mode, the system may once again

read array data with the same exception. See “Erase

Suspend/Erase Resume Commands” for more infor-

mation on this mode.

A read cycle at address XX00h retrieves the

manufacturer code. A read cycle at address XX01h re-

turns the device code. A read cycle containing a sector

address (SA) and the address 02h in word mode (or

04h in byte mode) returns 01h if that sector is pro-

tected, or 00h if it is unprotected. Refer to Table 4 for

valid sector addresses.

The system must issue the reset command to re-en-

able the device for reading array data if DQ5 goes

high, or while in the autoselect mode. See the “Reset

Command” section, next.

The system must write the reset command to exit the

autoselect mode and return to reading array data.

Word/Byte Program Command Sequence

See also “Requirements for Reading Array Data” in the

“Device Bus Operations” section for more information.

The Read Operations table provides the read parame-

ters, and Figure 11 shows the timing diagram.

The system may program the device by word or byte,

depending on the state of the BYTE# pin. Program-

ming is a four-bus-cycle operation. The program

command sequence is initiated by writing two unlock

write cycles, followed by the program set-up com-

mand. The program address and data are written next,

which in turn initiate the Embedded Program algo-

rithm. The system is not required to provide further

controls or timings. The device automatically gener-

ates the program pulses and verifies the programmed

cell margin. Table 10 shows the address and data re-

quirements for the byte program command sequence.

Reset Command

Writing the reset command to the device resets the de-

vice to reading array data. Address bits are don’t care

for this command.

The reset command may be written between the se-

quence cycles in an erase command sequence before

erasing begins. This resets the device to reading array

data. Once erasure begins, however, the device ig-

nores reset commands until the operation is complete.

When the Embedded Program algorithm is complete,

the device then returns to reading array data and ad-

dresses are no longer latched. The system can

determine the status of the program operation by using

DQ7 or DQ6. See “Write Operation Status” for infor-

mation on these status bits.

The reset command may be written between the se-

quence cycles in a program command sequence

before programming begins. This resets the device to

reading array data (also applies to programming in

Erase Suspend mode). Once programming begins,

however, the device ignores reset commands until the

operation is complete.

Any commands written to the device during the Em-

bedded Program Algorithm are ignored.

16

Am29PL160C

June 12, 2002

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed

from a “0” back to a “1”. Attempting to do so may

halt the operation and set DQ5 to “1,” or cause the

Data# Polling algorithm to indicate the operation was

successful. However, a succeeding read will show that

the data is still “0”. Only erase operations can convert

a “0” to a “1”.

START

Write Program

Command Sequence

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to pro-

gram bytes or words to the device faster than using the

standard program command sequence. The unlock

bypass command sequence is initiated by first writing

two unlock cycles. This is followed by a third write

cycle containing the unlock bypass command, 20h.

The device then enters the unlock bypass mode. A

two-cycle unlock bypass program command sequence

is all that is required to program in this mode. The first

cycle in this sequence contains the unlock bypass pro-

gram command, A0h; the second cycle contains the

program address and data. Additional data is pro-

grammed in the same manner. This mode dispenses

with the initial two unlock cycles required in the stan-

dard program command sequence, resulting in faster

total programming time. Table 10 shows the require-

ments for the command sequence.

Data Poll

from System

Embedded

Program

algorithm

in progress

Verify Data?

Yes

No

Increment Address

Last Address?

Yes

Programming

Completed

During the unlock bypass mode, only the Unlock By-

pass Program and Unlock Bypass Reset commands

are valid. To exit the unlock bypass mode, the system

must issue the two-cycle unlock bypass reset com-

mand sequence. The first cycle must contain the data

90h; the second cycle the data 00h. Addresses are

don’t care for both cycles. The device then returns to

reading array data.

Note: See Table 10 for program command sequence.

Figure 1. Program Operation

Chip Erase Command Sequence

Figure 1 illustrates the algorithm for the program oper-

ation. See the Program/Erase Operations table in “AC

Characteristics” for parameters, and to Figure 15 for

timing diagrams.

Chip erase is a six bus cycle operation. The chip erase

command sequence is initiated by writing two unlock

cycles, followed by a set-up command. Two additional

unlock write cycles are then followed by the chip erase

command, which in turn invokes the Embedded Erase

algorithm. The device does not require the system to

preprogram prior to erase. The Embedded Erase algo-

rithm automatically preprograms and verifies the entire

memory for an all zero data pattern prior to electrical

erase. The system is not required to provide any con-

trols or timings during these operations. Table 10

shows the address and data requirements for the chip

erase command sequence.

Any commands written to the chip during the Embed-

ded Erase algorithm are ignored.

The system can determine the status of the erase op-

eration by using DQ7, DQ6, or DQ2. See “Write

Operation Status” for information on these status bits.

When the Embedded Erase algorithm is complete, the

June 12, 2002

Am29PL160C

17

device returns to reading array data and addresses

are no longer latched.

Figure 2 illustrates the algorithm for the erase opera-

tion. Refer to the Program/Erase Operations tables in

the “AC Characteristics” section for parameters, and to

Figure 16 for timing diagrams.

Figure 2 illustrates the algorithm for the erase opera-

tion. See the Program/Erase Operations tables in “AC

Characteristics” for parameters, and to Figure 16 for

timing diagrams.

Erase Suspend/Erase Resume Commands

The Erase Suspend command allows the system to in-

terrupt a sector erase operation and then read data

from, or program data to, any sector not selected for

erasure. This command is valid only during the sector

erase operation, including the 50 µs time-out period

during the sector erase command sequence. The

Erase Suspend command is ignored if written during

the chip erase operation or Embedded Program algo-

rithm. Writing the Erase Suspend command during the

Sector Erase time-out immediately terminates the

time-out period and suspends the erase operation. Ad-

dresses are “don’t-cares” when writing the Erase

Suspend command.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector

erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two ad-

ditional unlock write cycles are then followed by the

address of the sector to be erased, and the sector

erase command. Table 10 shows the address and data

requirements for the sector erase command sequence.

The device does not require the system to preprogram

the memory prior to erase. The Embedded Erase algo-

rithm automatically programs and verifies the sector

for an all zero data pattern prior to electrical erase. The

system is not required to provide any controls or tim-

ings during these operations.

When the Erase Suspend command is written during a

sector erase operation, the device requires a maxi-

mum of 20 µs to suspend the erase operation.

However, when the Erase Suspend command is writ-

ten during the sector erase time-out, the device

immediately terminates the time-out period and sus-

pends the erase operation.

After the command sequence is written, a sector erase

time-out of 50 µs begins. During the time-out period,

additional sector addresses and sector erase com-

mands may be written. Loading the sector erase buffer

may be done in any sequence, and the number of sec-

tors may be from one sector to all sectors. The time

between these additional cycles must be less than 50

µs, otherwise the last address and command might not

be accepted, and erasure may begin. It is recom-

mended that processor interrupts be disabled during

this time to ensure all commands are accepted. The in-

terrupts can be re-enabled after the last Sector Erase

command is written. If the time between additional

sector erase commands can be assumed to be less

than 50 µs, the system need not monitor DQ3. Any

command other than Sector Erase or Erase Sus-

pend during the time-out period resets the device

to reading array data. The system must rewrite the

command sequence and any additional sector ad-

dresses and commands.

After the erase operation has been suspended, the

system can read array data from or program data to

any sector not selected for erasure. (The device “erase

suspends” all sectors selected for erasure.) Normal

read and write timings and command definitions apply.

Reading at any address within erase-suspended sec-

tors produces status data on DQ7–DQ0. The system

can use DQ7, or DQ6 and DQ2 together, to determine

if a sector is actively erasing or is erase-suspended.

See “Write Operation Status” for information on these

status bits.

After an erase-suspended program operation is com-

plete, the system can once again read array data

within non-suspended sectors. The system can deter-

mine the status of the program operation using the

DQ7 or DQ6 status bits, just as in the standard

program operation. See “Write Operation Status” for

more information.

The system can monitor DQ3 to determine if the sector

erase timer has timed out. (See the “DQ3: Sector Erase

Timer” section.) The time-out begins from the rising

edge of the final WE# pulse in the command sequence.

The system may also write the autoselect command

sequence when the device is in the Erase Suspend

mode. The device allows reading autoselect codes

even at addresses within erasing sectors, since the

codes are not stored in the memory array. When the

device exits the autoselect mode, the device reverts to

the Erase Suspend mode, and is ready for another

valid operation. See “Autoselect Command Sequence”

for more information.

Once the sector erase operation has begun, only the

Erase Suspend command is valid. All other commands

are ignored.

When the Embedded Erase algorithm is complete, the

device returns to reading array data and addresses

are no longer latched. The system can determine the

status of the erase operation by using DQ7, DQ6, or

DQ2. (Refer to “Write Operation Status” for information

on these status bits.)

The system must write the Erase Resume command

(address bits are “don’t care”) to exit the erase sus-

18

Am29PL160C

June 12, 2002

pend mode and continue the sector erase operation.

Further writes of the Resume command are ignored.

Another Erase Suspend command can be written after

the device has resumed erasing.

START

Temporary Unprotect Enable/Disable

Command Sequence

Write Erase

Command Sequence

The temporary unprotect command sequence is a

four-bus-cycle operation. The sequence is initiated by

writing two unlock write cycles. A third write cycle sets

up the command. The fourth and final write cycle en-

ables or disables the temporary unprotect feature. If

the temporary unprotect feature is enabled, all sectors

are temporarily unprotected. The system may program

or erase data as needed. When the system writes the

temporary unprotect disable command sequence, all

sectors return to their previous protected or unpro-

tected settings. See Table 10 for more information.

Data Poll

from System

Embedded

Erase

algorithm

in progress

No

Data = FFh?

Yes

Erasure Completed

Notes:

1. See Table 10 for erase command sequence.

2. See “DQ3: Sector Erase Timer” for more information.

Figure 2. Erase Operation

June 12, 2002

Am29PL160C

19

Command Definitions

Table 10. Am29PL160C Command Definitions

Bus Cycles (Notes 2–5)

Command

Sequence

(Note 1)

First

Second

Third

Addr

Fourth

Fifth

Sixth

Addr Data Addr Data

Data Addr Data Addr Data Addr Data

Read (Note 6)

Reset (Note 7)

1

RA

RD

F0

XXX

555

AAA

555

AAA

Word

2AA

555

2AA

555

AAA

555

Manufacturer ID

4

AA

55

90

X00

01

Byte

Word

Byte

X01

X02

2245

45

Device ID,

Bottom Boot Block

AAA

XX00

XX01

00

(SA)

X02

Word

Byte

555

2AA

555

Sector Protect Verify

(Note 9)

4

AA

55

90

(SA)

X04

AAA

01

Word

Byte

Word

Byte

Word

Byte

55

CFI Query (Note 10)

1

4

3

98

AA

555

AAA

555

AAA

XXX

555

AAA

555

AAA

XXX

555

AAA

555

AAA

2AA

555

2AA

555

PA

555

AAA

555

Program

55

A0

20

PA

PD

Unlock Bypass

AAA

Unlock Bypass Program (Note 11)

Unlock Bypass Reset (Note 12)

2

A0

90

PD

00

XXX

2AA

555

2AA

555

Word

555

AAA

555

AAA

555

2AA

555

2AA

555

Chip Erase

6

AA

55

80

AA

55

10

30

Byte

Word

Byte

AAA

Sector Erase

SA

AAA

Erase Suspend (Note 13)

Erase Resume (Note 14)

1

B0

30

Word

Byte

Word

Byte

2AA

555

2AA

555

AAA

555

Temporary Unprotect Enable

4

AA

55

E0

XXX

01

00

Temporary Unprotect

Disable

AAA

Legend:

X = Don’t care

PD = Data to be programmed at location PA. Data latches on the

rising edge of WE# or CE# pulse, whichever happens first.

RA = Address of the memory location to be read.

RD = Data read from location RA during read operation.

SA = Address of the sector to be verified (in autoselect mode) or

erased. Address bits A19–A12 uniquely select any sector.

PA = Address of the memory location to be programmed. Addresses

latch on the falling edge of the WE# or CE# pulse, whichever

happens later.

Notes:

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

9. The data is 00h for an unprotected sector and 01h for a protected

sector. See “Autoselect Command Sequence” for more

information.

3. Except for the read cycle and the fourth cycle of the autoselect

command sequence, all bus cycles are write cycles.

10. Command is valid when device is ready to read array data or

when device is in autoselect mode.

4. Data bits DQ15–DQ8 are don’t cares for unlock and command

cycles.

11. The Unlock Bypass command is required prior to the Unlock

Bypass Program command.

5. Address bits A19–A11 are don’t cares for unlock and command

cycles, unless SA or PA required.

12. The Unlock Bypass Reset command is required to return to

reading array data when the device is in the unlock bypass

mode.

6. No unlock or command cycles required when reading array data.

7. The Reset command is required to return to reading array data

when device is in the autoselect mode, or if DQ5 goes high (while

the device is providing status data).

13. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode.

The Erase Suspend command is valid only during a sector erase

operation.

8. The fourth cycle of the autoselect command sequence is a read

cycle.

14. The Erase Resume command is valid only during the Erase Sus-

pend mode.

20

Am29PL160C

June 12, 2002

WRITE OPERATION STATUS

The device provides several bits to determine the sta-

tus of a write operation: DQ2, DQ3, DQ5, DQ6, and

DQ7. Table 11 and the following subsections describe

the functions of these bits. DQ7 and DQ6 each offer a

method for determining whether a program or erase

operation is complete or in progress. These three bits

are discussed first.

DQ6 while Output Enable (OE#) is asserted low. See

Figure 16 in the “AC Characteristics” section.

Table 11 shows the outputs for Data# Polling on DQ7.

Figure 3 shows the Data# Polling algorithm.

START

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host

system whether an Embedded Algorithm is in progress

or completed, or whether the device is in Erase

Suspend. Data# Polling is valid after the rising edge

of the final WE# pulse in the program or erase com-

mand sequence.

Read DQ7–DQ0

Addr = VA

During the Embedded Program algorithm, the device

outputs on DQ7 the complement of the datum pro-

grammed to DQ7. This DQ7 status also applies to

programming during Erase Suspend. When the Em-

bedded Program algorithm is complete, the device

outputs the datum programmed to DQ7. The system

must provide the program address to read valid status

information on DQ7. If a program address falls within a

protected sector, Data# Polling on DQ7 is active for

approximately 1 µs, then the device returns to reading

array data.

Yes

DQ7 = Data?

No

DQ5 = 1?

Yes

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase

algorithm is complete, or if the device enters the Erase

Suspend mode, Data# Polling produces a “1” on DQ7.

This is analogous to the complement/true datum out-

put described for the Embedded Program algorithm:

the erase function changes all the bits in a sector to

“1”; prior to this, the device outputs the “complement,”

or “0.” The system must provide an address within any

of the sectors selected for erasure to read valid status

information on DQ7.

Read DQ7–DQ0

Addr = VA

Yes

DQ7 = Data?

No

After an erase command sequence is written, if all sec-

tors selected for erasing are protected, Data# Polling

on DQ7 is active for approximately 100 µs, then the

device returns to reading array data. If not all selected

sectors are protected, the Embedded Erase algorithm

erases the unprotected sectors, and ignores the se-

lected sectors that are protected.

PASS

FAIL

Notes:

1. VA = Valid address for programming. During a sector

erase operation, a valid address is an address within any

sector selected for erasure. During chip erase, a valid

address is any non-protected sector address.

When the system detects DQ7 has changed from the

complement to true data, it can read valid data at

DQ7–DQ0 on the following read cycles. This is be-

cause DQ7 may change asynchronously with DQ0–

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5

Figure 3. Data# Polling Algorithm

June 12, 2002

Am29PL160C

21

DQ2 toggles when the system reads at addresses

within those sectors that have been selected for

erasure. (The system may use either OE# or CE# to

control the read cycles.) But DQ2 cannot distinguish

whether the sector is actively erasing or is erase-sus-

pended. DQ6, by comparison, indicates whether the

device is actively erasing, or is in Erase Suspend, but

cannot distinguish which sectors are selected for era-

sure. Thus, both status bits are required for sector and

mode information. Refer to Table 11 to compare outputs

for DQ2 and DQ6.

DQ6: Toggle Bit

Toggle Bit I on DQ6 indicates whether an Embedded

Program or Erase algorithm is in progress or complete,

or whether the device has entered the Erase Suspend

mode. Toggle Bit I may be read at any address, and is

valid after the rising edge of the final WE# pulse in the

command sequence (prior to the program or erase op-

eration), and during the sector erase time-out.

During an Embedded Program or Erase algorithm op-

eration, successive read cycles to any address cause

DQ6 to toggle. (The system may use either OE# or

CE# to control the read cycles.) When the operation is

complete, DQ6 stops toggling.

Figure 4 shows the toggle bit algorithm in flowchart

form, and the section “Reading Toggle Bits DQ6/DQ2”

explains the algorithm. See also the DQ6: Toggle Bit

subsection. Figure 18 shows the toggle bit timing dia-

gram. Figure 19 shows the differences between DQ2

and DQ6 in graphical form.

After an erase command sequence is written, if all

sectors selected for erasing are protected, DQ6 tog-

gles for approximately 100 µs, then returns to reading

array data. If not all selected sectors are protected,

the Embedded Erase algorithm erases the unpro-

tected sectors, and ignores the selected sectors that

are protected.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 4 for the following discussion. When-

ever the system initially begins reading toggle bit

status, it must read DQ7–DQ0 at least twice in a row to

determine whether a toggle bit is toggling. Typically,

the system would note and store the value of the tog-

gle bit after the first read. After the second read, the

system would compare the new value of the toggle bit

with the first. If the toggle bit is not toggling, the device

has completed the program or erase operation. The

system can read array data on DQ7–DQ0 on the fol-

lowing read cycle.

The system can use DQ6 and DQ2 together to deter-

mine whether a sector is actively erasing or is erase-

suspended. When the device is actively erasing (that

is, the Embedded Erase algorithm is in progress), DQ6

toggles. When the device enters the Erase Suspend

mode, DQ6 stops toggling. However, the system must

also use DQ2 to determine which sectors are erasing

or erase-suspended. Alternatively, the system can use

DQ7 (see the subsection on “DQ7: Data# Polling”).

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the sys-

tem also should note whether the value of DQ5 is high

(see the section on DQ5). If it is, the system should

then determine again whether the toggle bit is toggling,

since the toggle bit may have stopped toggling just as

DQ5 went high. If the toggle bit is no longer toggling,

the device has successfully completed the program or

erase operation. If it is still toggling, the device did not

complete the operation successfully, and the system

must write the reset command to return to reading

array data.

If a program address falls within a protected sector,

DQ6 toggles for approximately 1 µs after the program

command sequence is written, then returns to reading

array data.

DQ6 also toggles during the erase-suspend-program

mode, and stops toggling once the Embedded Pro-

gram algorithm is complete.

Table 11 shows the outputs for Toggle Bit I on DQ6.

Figure 4 shows the toggle bit algorithm in flowchart

form, and the section “Reading Toggle Bits DQ6/DQ2”

explains the algorithm. Figure 18 in the “AC Character-

istics” section shows the toggle bit timing diagrams.

Figure 19 shows the differences between DQ2 and

DQ6 in graphical form. See also the subsection on

“DQ2: Toggle Bit”.

The remaining scenario is that the system initially de-

termines that the toggle bit is toggling and DQ5 has not

gone high. The system may continue to monitor the

toggle bit and DQ5 through successive read cycles,

determining the status as described in the previous

paragraph. Alternatively, it may choose to perform

other system tasks. In this case, the system must start

at the beginning of the algorithm when it returns to de-

termine the status of the operation (top of Figure 4).

DQ2: Toggle Bit

The “Toggle Bit II” on DQ2, when used with DQ6, indi-

cates whether a particular sector is actively erasing

(that is, the Embedded Erase algorithm is in progress),

or whether that sector is erase-suspended. Toggle Bit

II is valid after the rising edge of the final WE# pulse in

the command sequence.

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has

exceeded a specified internal pulse count limit. Under

these conditions DQ5 produces a “1.” This is a failure

22

Am29PL160C

June 12, 2002

condition that indicates the program or erase cycle

was not successfully completed.

The DQ5 failure condition may appear if the system

tries to program a “1” to a location that is previously

programmed to “0.” Only an erase operation can

change a “0” back to a “1.” Under this condition, the

device halts the operation, and when the operation has

exceeded the timing limits, DQ5 produces a “1.”

START

Read DQ7–DQ0

Under both these conditions, the system must issue

the reset command to return the device to reading

array data.

Read DQ7–DQ0

(Note 1)

No

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the

system may read DQ3 to determine whether or not an

erase operation has begun. (The sector erase timer

does not apply to the chip erase command.) If addi-

tional sectors are selected for erasure, the entire time-

out also applies after each additional sector erase

command. When the time-out is complete, DQ3

switches from “0” to “1.” The system may ignore DQ3

if the system can guarantee that the time between ad-

ditional sector erase commands will always be less than

50 µs. See also the “Write Operation Status” section.

Toggle Bit

= Toggle?

Yes

No

DQ5 = 1?

Yes

After the sector erase command sequence is written,

the system should read the status on DQ7 (Data# Poll-

ing) or DQ6 (Toggle Bit I) to ensure the device has

accepted the command sequence, and then read

DQ3. If DQ3 is “1”, the internally controlled erase cycle

has begun; all further commands (other than Erase

Suspend) are ignored until the erase operation is com-

plete. If DQ3 is “0”, the device will accept additional

sector erase commands. To ensure the command has

been accepted, the system software should check the

status of DQ3 prior to and following each subsequent

sector erase command. If DQ3 is high on the second

status check, the last command might not have been

accepted. Table 11 shows the outputs for DQ3.

Read DQ7–DQ0

Twice

(Notes

1, 2)

Toggle Bit

= Toggle?

No

Yes

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Notes:

1. Read toggle bit twice to determine whether or not it is

toggling. See text.

2. Recheck toggle bit because it may stop toggling as DQ5

changes to “1”. See text.

Figure 4. Toggle Bit Algorithm

June 12, 2002

Am29PL160C

23

Table 11. Write Operation Status

DQ7

DQ5

DQ2

Operation

(Note 2)

DQ7#

0

DQ6

(Note 1)

DQ3

N/A

1

(Note 2)

Embedded Program Algorithm

Embedded Erase Algorithm

Toggle

0

No toggle

Toggle

Standard

Mode

Reading within Erase

Suspended Sector

1

No toggle

0

N/A

Toggle

Erase

Suspend

Mode

Reading within Non-Erase

Suspended Sector

Data

0

Data

N/A

Data

N/A

Erase-Suspend-Program

DQ7#

Toggle

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

See “DQ5: Exceeded Timing Limits” for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

24

Am29PL160C

June 12, 2002

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . -65°C to +150°C

20 ns

Ambient Temperature

with Power Applied . . . . . . . . . . . . . -65°C to +125°C

+0.8 V

Voltage with Respect to Ground

–0.5 V

–2.0 V

V

(Note 1). . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V

CC

A9 and OE# (Note 2) . . . . . . . . . .–0.5 V to +13.0 V

All other pins (Note 1). . . . . . . . . . .–0.5 V to +5.5 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

20 ns

Figure 5. Maximum Negative

Overshoot Waveform

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V. During

voltage transitions, input at I/O pins may overshoot V to

SS

-2.0 V for periods of up to 20 ns. Maximum DC voltage on

output and I/O pins is V + 0.5 V. During voltage

CC

transitions output pins may overshoot to V + 2.0 V for

CC

periods up to 20 ns.

20 ns

2. Minimum DC input voltage on pins A9 and OE# is –0.5 V.

During voltage transitions, A9 and OE# may overshoot

V

CC

V

to -2.0 V for periods of up to 20 ns. Maximum DC

SS

+2.0 V

input voltage on pin A9 and OE# is +13.0 V which may

overshoot to 14.0 V for periods up to 20 ns.

V

CC

+0.5 V

3. No more than one output may be shorted to ground at a

time. Duration of the short circuit should not be greater

than one second.

2.0 V

20 ns

4. Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device.

This is a stress rating only; functional operation of the de-

vice at these or any other conditions above those indi-

cated in the operational sections of this data sheet is not

implied. Exposure of the device to absolute maximum rat-

ing conditions for extended periods may affect device re-

liability.

Figure 6. Maximum Positive

Overshoot Waveform

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (T ) . . . . . . . . . . . 0°C to +70°C

A

Industrial (I) Devices

Ambient Temperature (T ) . . . . . . . . . –40°C to +85°C

A

V

Supply Voltages

CC

for regulated voltage range. . . . . . .3.0 V to 3.6 V

for full voltage range. . . . . . . . . . . .2.7 V to 3.6 V

Operating ranges define those limits between which the func-

tionality of the device is guaranteed.

June 12, 2002

Am29PL160C

25

DC CHARACTERISTICS

CMOS Compatible

Parameter

Symbol

Description

Test Conditions

= V to 5.5 V,

Min

Typ

Max

±1.0

35

Unit

µA

V

IN

SS

I

Input Load Current

LI

= V

CC

CC max

I

A9 Input Load Current

Output Leakage Current

V

= V

; A9 = 12.5 V

µA

LIT

CC

CC max

V

= V to 5.5 V,

OUT

SS

I

±1.0

µA

LO

= V

CC

CC max

V

Active Read Current

CC

I

CE# = V OE# = V

30

20

50

30

mA

CC1

IL,

IH

(Notes 1, 2)

V

Active Write Current

CC

I

CE# = V OE# = V

mA

µA

CC2

IL,

IH

(Notes 2, 4, 5)

I

V

Standby Current (Note 2)

CE# = V ±0.3 V

1

8

5

CC3

CC

OE# = V

5

IH

IL

Automatic Sleep Mode

(Notes 2, 3, 6)

V

= V ± 0.3 V;

CC

IH

IL

I

µA

CC4

= V ± 0.3 V

SS

20

0.8

5.5

V

Input Low Voltage

Input High Voltage

–0.5

V

IL

V

0.7 x V

IH

CC

Voltage for Autoselect and

Temporary Sector Unprotect

V

= 3.3 V

11.5

12.5

0.45

V

ID

CC

V

Output Low Voltage

I

= 4.0 mA, V = V

CC CC min

OL

OH

V

= –2.0 mA, V = V

0.85 x V

CC

OH1

OH2

CC

CC min

Output High Voltage

V

= –100 µA, V = V

V

–0.4

CC

Low V Lock-Out Voltage

(Note 4)

CC

V

2.3

2.5

LKO

Notes:

1. The I current listed is typically less than 2 mA/MHz, with OE# at V . Typical V is 3.0 V.

CC

IH

2. Maximum I specifications are tested with V

= V max.

CC

3. The Automatic Sleep Mode current is dependent on the state of OE#.

4. I active while Embedded Erase or Embedded Program is in progress.

CC

5. Automatic sleep mode enables the low power mode when addresses remain stable for t

current is 200 nA.

+ 30 ns. Typical sleep mode

ACC

6. Not 100% tested.

26

Am29PL160C

June 12, 2002

DC CHARACTERISTICS (Continued)

Zero Power Flash

25

20

15

10

5

0

500

1000

1500

2000

2500

3000

3500

4000

Time in ns

Note: Addresses are switching at 1 MHz

Figure 7.

I

Current vs. Time (Showing Active and Automatic Sleep Currents)

CC1

10

8

3.6 V

2.7 V

6

4

2

0

1

2

3

4

5

Frequency in MHz

Note: T = 25 °C

Figure 8. Typical I

vs. Frequency

CC1

June 12, 2002

Am29PL160C

27

TEST CONDITIONS

Table 12. Test Specifications

3.3 V

-70R,

-90, -120 Unit

Test Condition

Output Load

-65R

2.7 kΩ

Device

Under

Test

1 TTL gate

100

Output Load Capacitance, C

(including jig capacitance)

L

30

pF

C

L

6.2 kΩ

Input Rise and Fall Times

Input Pulse Levels

5

ns

V

0.0–3.0

1.5

Input timing measurement

reference levels

V

Note: Diodes are IN3064 or equivalent

Output timing measurement

reference levels

1.5

Figure 9. Test Setup

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Center Line is High Impedance State (High Z)

3.0 V

0.0 V

1.5 V

Input

Measurement Level

Output

Figure 10. Input Waveforms and Measurement Levels

28

Am29PL160C

June 12, 2002

AC CHARACTERISTICS

Read Operations

Parameter

Speed Options

JEDEC

Std

Description

Test Setup

-65R

-70R

-90

-120

Unit

t

Read Cycle Time

Min

65

70

90

120

ns

AVAV

RC

CE#=V ,

IL

t

Address Access Time

Max

65

70

90

120

ns

AVQV

ACC

OE#=V

IL

t

Chip Enable to Output Delay

Page Access Time

OE#=V

Max

65

25

70

25

90

30

120

30

ns

ELQV

CE

IL

t

PACC

t

Output Enable to Output Valid

Chip Enable to Output High Z

Output Enable to Output High Z

30

GLQV

EHQZ

GHQZ

OE

t

20

0

DF

t

Read

Output Enable

t

OEH

Toggle and

Data# Polling

Hold Time (Note 1)

10

0

ns

t

Output Hold Time from Addresses

Min

AXQX

OH

Notes:

1. Not 100% tested.

2. See Figure 9 and Table 12 for test specifications.

June 12, 2002

Am29PL160C

29

AC CHARACTERISTICS

t_RC

Addresses Stable

Addresses

CE#

t_ACC

t_DF

t_OE

OE#

WE#

t_OEH

t_CE

t_OH

HIGH Z

Output Valid

Outputs

0 V

Figure 11. Conventional Read Operations Timings

Same Page

A3-A19

A-1-A2

Ad

Aa

t_ACC

Ab

t_PACC

Ac

t_PACC

Data Bus

Qa

Qb

Qc

Qd

CE#

OE#

Note: Word Configuration: Toggle A0, A1, A2. Byte Configuration: Toggle A-1, A0, A1, A2.

Figure 12. Page Read Timings

30

Am29PL160C

June 12, 2002

AC CHARACTERISTICS

Word/Byte Configuration (BYTE#)

Parameter

Speed Options

JEDEC

Std

Description

-65R

-70R

-90

-120

Unit

ns

t

CE# to BYTE# Switching Low or High

BYTE# Switching Low to Output HIGH Z

BYTE# Switching High to Output Active

Max

Min

5

ELFL/ ELFH

25

65

25

70

30

90

30

ns

FLQZ

FHQV

120

ns

CE#

OE#

BYTE#

t

ELFL

Data Output

(DQ0–DQ14)

Data Output

(DQ0–DQ7)

BYTE#

DQ0–DQ14

DQ15/A-1

Switching

from word

to byte

Address

Input

DQ15

Output

mode

t

FLQZ

t

ELFH

BYTE#

Switching

from byte

to word

Data Output

(DQ0–DQ7)

Data Output

(DQ0–DQ14)

DQ0–DQ14

DQ15/A-1

mode

Address

Input

DQ15

Output

t

FHQV

Figure 13. BYTE# Timings for Read Operations

CE#

The falling edge of the last WE# signal

WE#

BYTE#

t

SET

(t

)

AS

t

(t

)

HOLD AH

Note: Refer to the Erase/Program Operations table for t and t specifications.

AS

AH

Figure 14. BYTE# Timings for Write Operations

June 12, 2002

Am29PL160C

31

AC CHARACTERISTICS

Program/Erase Operations

Parameter

Speed Options

Unit

JEDEC

Std

Description

-65R

-70R

-90

-120

t

Write Cycle Time (Note 1)

Address Setup Time

Address Hold Time

Data Setup Time

Min

65

70

90

120

ns

AVAV

WC

t

0

AVWL

WLAX

AS

AH

DS

DH

t

45

35

45

35

45

50

t

DVWH

WHDX

t

Data Hold Time

0

t

Output Enable Setup Time

OES

Read Recovery Time Before Write

(OE# High to WE# Low)

t

Min

0

ns

GHWL

t

CE# Setup Time

Min

Typ

Min

0

ns

µs

ELWL

WHEH

WLWH

WHWL

CS

t

CE# Hold Time

CH

t

Write Pulse Width

Write Pulse Width High

35

50

WP

t

30

7

WPH

Byte

t

Programming Operation (Note 2)

Sector Erase Operation (Note 2)

WHWH1

WHWH2

WHWH1

Word

9

5

sec

µs

WHWH2

t

V

Setup Time (Note 1)

50

VCS

CC

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

32

Am29PL160C

June 12, 2002

AC CHARACTERISTICS

Program Command Sequence (last two cycles)

Read Status Data (last two cycles)

t_AS

t_WC

Addresses

555h

PA

t_AH

CE#

OE#

t_CH

t_GHWL

t_WHWH1

t_WP

WE#

t_WPH

t_CS

t_DS

t_DH

PD

D_OUT

A0h

Status

Data

V_CC

t_VCS

Notes:

1. PA = program address, PD = program data, D

is the true data at the program address.

OUT

2. Illustration shows device in word mode.

Figure 15. Program Operation Timings

June 12, 2002

Am29PL160C

33

AC CHARACTERISTICS

Erase Command Sequence (last two cycles)

Read Status Data

VA

t_AS

SA

t_WC

VA

Addresses

CE#

2AAh

555h for chip erase

t_AH

t_GHWL

t_CH

OE#

t_WP

WE#

t_WPH

t_WHWH2

t_CS

t_DS

t_DH

In

Data

V_CC

Complete

55h

30h

Progress

10 for Chip Erase

t_VCS

Notes:

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).

2. Illustration shows device in word mode.

Figure 16. AC Waveforms for Chip/Sector Erase Operations

t_RC

Addresses

CE#

VA

t_ACC

t_CE

VA

t_CH

t_OE

OE#

WE#

t_OEH

t_DF

t_OH

High Z

DQ7

Valid Data

Complement

True

DQ0–DQ6

Status Data

True

Valid Data

Status Data

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data

read cycle

Figure 17. Data# Polling Timings (During Embedded Algorithms)

34

Am29PL160C

June 12, 2002

AC CHARACTERISTICS

t_RC

VA

Addresses

VA

t_ACC

t_CE

CE#

t_CH

t_OE

OE#

WE#

t_OEH

t_DF

t_OH

High Z

DQ6/DQ2

Valid Status

(first read)

Valid Status

Valid Data

(second read)

(stops toggling)

Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status

read cycle, and array data read cycle

Figure 18. Toggle Bit Timings (During Embedded Algorithms)

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

Erase

Erase Suspend

Read

Erase

Suspend

Program

Erase

Complete

WE#

Erase

Erase Suspend

Read

DQ6

DQ2

Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an

erase-suspended sector.

Figure 19. DQ2 vs. DQ6 for Erase and

Erase Suspend Operations

June 12, 2002

Am29PL160C

35

AC CHARACTERISTICS

Alternate CE# Controlled Erase/Program Operations

Parameter

Speed Options

JEDEC

Std

Description

-65R

-70R

-90

-120

Unit

ns

t

Write Cycle Time (Note 1)

Address Setup Time

Address Hold Time

Data Setup Time

Min

65

70

90

120

AVAV

AVEL

ELAX

WC

t

0

ns

AS

AH

DS

DH

t

45

35

45

35

45

50

ns

t

ns

DVEH

EHDX

t

Data Hold Time

0

ns

t

Output Enable Setup Time

ns

OES

Read Recovery Time Before Write

(OE# High to WE# Low)

t

Min

0

ns

GHEL

WLEL

GHEL

t

WE# Setup Time

WE# Hold Time

Min

Typ

0

ns

WS

t

EHWH

WH

t

CE# Pulse Width

CE# Pulse Width High

35

50

ELEH

EHEL

CP

t

30

7

CPH

Byte

Word

Programming Operation

(Note 2)

t

µs

WHWH1

9

Sector Erase Operation (Note 2)

5

sec

WHWH2

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

36

Am29PL160C

June 12, 2002

AC CHARACTERISTICS

555 for program

PA for program

2AA for erase

SA for sector erase

555 for chip erase

Data# Polling

Addresses

PA

t_WC

t_WH

t_AS

t_AH

WE#

OE#

t_GHEL

t_{WHWH1 or 2}

t_CP

CE#

Data

t_WS

t_CPH

t_DS

t_DH

DQ7#

D_OUT

A0 for program

55 for erase

PD for program

30 for sector erase

10 for chip erase

Notes:

1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, D

device.

= data written to the

OUT

2. Figure indicates the last two bus cycles of the command sequence.

3. Word mode address used as an example.

Figure 20. Alternate CE# Controlled Write Operation Timings

June 12, 2002

Am29PL160C

37

ERASE AND PROGRAMMING PERFORMANCE

Parameter

Typ (Note 1)

Max (Note 2)

Unit

s

Comments

Sector Erase Time

Chip Erase Time

5

40

7

60

Excludes 00h programming

prior to erasure (Note 4)

s

Byte Programming Time

Word Programming Time

300

360

42

µs

s

9

Excludes system level

overhead (Note 5)

Byte Mode

Word Mode

14

9

Chip Programming Time

(Note 3)

27

s

Notes:

1. Typical program and erase times assume the following conditions: 25°C, 3.0 V V , 1,000,000 cycles. Additionally,

CC

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, V = 2.7 V, 1,000,000 cycles.

CC

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See

Table 10 for further information on command definitions.

6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTICS

Description

Min

Max

Input voltage with respect to V on all pins except I/O pins

(including A9 and OE#)

SS

–1.0 V

12.5 V

Input voltage with respect to V on all I/O pins

–1.0 V

V

+ 1.0 V

SS

CC

V

Current

–100 mA

+100 mA

CC

Includes all pins except V . Test conditions: V = 3.0 V, one pin at a time.

CC

TSOP AND SO PIN CAPACITANCE

Parameter

Symbol

Parameter Description

Input Capacitance

Test Setup

= 0

Typ

6

Max

7.5

12

Unit

pF

C

V

IN

C

Output Capacitance

V

= 0

OUT

8.5

7.5

8

pF

OUT

TSOP

SO

9

pF

C

Control Pin Capacitance

V

= 0

IN

IN2

10

pF

Notes:

1. Sampled, not 100% tested.

2. Test conditions T = 25°C, f = 1.0 MHz.

A

DATA RETENTION

Parameter

Test Conditions

150°C

Min

Unit

10

20

Years

Minimum Pattern Data Retention Time

125°C

* For reference only. BSC is an ANSI standard for Basic Space Centering.

38

Am29PL160C

June 12, 2002

PHYSICAL DIMENSIONS

TS 048—48-Pin Standard Thin Small Outline Package

Dwg rev AA; 10/99

June 12, 2002

Am29PL160C

39

PHYSICAL DIMENSIONS

SO 044—44-Pin Small Outline Package, Standard Pinout

Dwg rev AC; 10/99

40

Am29PL160C

June 12, 2002

PHYSICAL DIMENSIONS

SOR044—44-Pin Small Outline Package, Reverse Pinout

Dwg rev AC; 10/99

June 12, 2002

Am29PL160C

41

Physical Dimensions

REVISION SUMMARY

Restored section.

Revision A (August 1998)

Revision B+6 (September 2, 1999)

Initial release.

Connection Diagrams

Revision A+1 (September 1998)

Corrected the pinouts of pins 1, 2, 43, and 44 on the

reverse SO diagram.

Sector Protection/Unprotection

Added reference to Temporary Unprotect Enable/Dis-

able command sequence.

Revision B+7 (February 4, 2000)

Global

Common Flash Memory Interface (CFI)

Added 48-pin TSOP.

Deleted reference to upper address bits in word mode.

Revision C (February 21, 2000)

Revision B (January 1999)

Ordering Information

Global

The “preliminary” designation has been removed from

the document. Parameters are now stable, and only

speed, package, and temperature range combinations

are expected to change in future data sheet revisions.

Deleted commercial temperature rating.

DC Characteristics

Corrected I

test condition for OE# to V .

IH

CC1

Added dash to ordering part numbers.

Revision B+1 (February 1999)

Revision C+1 (June 20, 2000)

DC Characteristics

Replaced TBDs for I

with specifications.

Global

CC4

Deleted the SOR44 package. Deleted references to

top boot configuration.

Revision B+2 (March 5, 1999)

Distinctive Characteristics

Product Selector Guide, Ordering Information

In the first subbullet under the Flexible Sector Architec-

ture bullet, deleted the reference to “one 8 Kbyte”

sector.

Added -90R speed option.

Revision C+2 (June 28, 2000)

Command Definitions

Revision B+3 (May 14, 1999)

Command Definitions table: Corrected address in the

sixth cycle of the chip erase command sequence from

2AA to AAA.

Global

Deleted the 60R speed option and added the 65R

speed option.

Revision C+3 (November 14, 2000)

Common Flash Memory Interface (CFI)

Corrected the data for the following CFI hex addreses:

38, 39, 3C, 4C.

Added table of contents.

Revision C+4 (June 12, 2002)

Absolute Maximum Ratings

Global

Corrected the maximum rating for all other pins to +5.5

V.

Deleted references to hardware reset (RESET#) input.

Added reverse pinout SO package. Deleted 90R

speed option.

Revision B+4 (June 25, 1999)

Changed data sheet status to preliminary. Deleted the

70 ns, full voltage range speed option.

TSOP and SO Pin Capacitance

Added TSOP pin capacitance.

Revision B+5 (July 26, 1999)

Global

Added the reverse pinout SO package. Deleted the

TSOP package.

42

Am29PL160C

June 12, 2002

Trademarks

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

ExpressFlash is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

June 12, 2002

Am29PL160C

43


型号：	AM29PL160CB-65REI
厂家：	AMD
描述：	16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS 3.0 Volt-only High Performance Page Mode Flash Memory 16兆位（2M ×8位/ 1的M× 16位） CMOS 3.0伏只高性能页模式闪存闪存内存集成电路光电二极管
文件：	总44页 (文件大小：946K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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