AM29SL400CT120WAC_技术文档

Am29SL400C

Data Sheet

The following document contains information on Spansion memory products. Although the document

is marked with the name of the company that originally developed the specification, Spansion will

continue to offer these products to existing customers.

Continuity of Specifications

There is no change to this data sheet as a result of offering the device as a Spansion product. Any

changes that have been made are the result of normal data sheet improvement and are noted in the

document revision summary, where supported. Future routine revisions will occur when appropriate,

and changes will be noted in a revision summary.

Continuity of Ordering Part Numbers

Spansion continues to support existing part numbers beginning with “Am” and “MBM”. To order these

products, please use only the Ordering Part Numbers listed in this document.

For More Information

Please contact your local sales office for additional information about Spansion memory solutions.

Publication Number Am29SL400C_00 Revision A Amendment 6 Issue Date January 23, 2007

THIS PAGE LEFT INTENTIONALLY BLANK.

DATA SHEET

Am29SL400C

4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 1.8

Volt-only Super Low Voltage Flash Memory

Distinctive Characteristics

■ Single power supply operation

■ Embedded Algorithms

— 1.65 to 2.2 V for read, program, and erase operations

— Ideal for battery-powered applications

— Embedded Erase algorithm automatically

preprograms and erases the entire chip or any

combination of designated sectors

■ Manufactured on 0.32 µm process technology

— Embedded Program algorithm automatically writes

and verifies data at specified addresses

■ High performance

— Access times as fast as 100 ns

■ Minimum 1,000,000 erase cycle guarantee per

■ Ultra low power consumption (typical values at

sector

5 MHz)

■ 20-year data retention at 125°C

— 1 µA Automatic Sleep Mode current

— 1 µA standby mode current

— 5 mA read current

■ Package option

— 48-ball FBGA

— 48-pin TSOP

— 20 mA program/erase current

■ Compatibility with JEDEC standards

■ Flexible sector architecture

— Pinout and software compatible with single-power

supply Flash

— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and seven

64 Kbyte sectors (byte mode)

— Superior inadvertent write protection

— One 8 Kword, two 4 Kword, one 16 Kword, and seven

32 Kword sectors (word mode)

■ Data# Polling and toggle bits

— Supports full chip erase

— Provides a software method of detecting program or

erase operation completion

— Sector Protection features:

A hardware method of locking a sector to prevent any

program or erase operations within that sector

Sectors can be locked in-system or via programming

equipment

■ Ready/Busy# pin (RY/BY#)

— Provides a hardware method of detecting program or

erase cycle completion

Temporary Sector Unprotect feature allows code

changes in previously locked sectors

■ Erase Suspend/Erase Resume

— Suspends an erase operation to read data from, or

program data to, a sector that is not being erased,

then resumes the erase operation

■ Unlock Bypass Program Command

— Reduces overall programming time when issuing

multiple program command sequences

■ Hardware reset pin (RESET#)

— Hardware method to reset the device to reading array

data

■ Top or bottom boot block configurations

available

Publication# Am29SL400C_00 Rev: A

Amendment: 6 Issue Date: January 23, 2007

This Data Sheet states AMD’s current specifications regarding the Products described herein. This Data Sheet may

be revised by subsequent versions or modifications due to changes in technical specifications.

D A T A S H E E T

General Description

The Am29SL400C is an 4Mbit, 1.8 V volt-only Flash memory

organized as 524,288 bytes or 262,144 words. The device is

offered in 48-pin TSOP and 48-ball FBGA packages. The

word-wide data (x16) appears on DQ15–DQ0; the byte-wide

(x8) data appears on DQ7–DQ0. This device is designed to

be programmed and erased in-system with a single 1.8 volt

V_CCsupply. No V_PPis required for write or erase operations.

The device can also be programmed in standard EPROM

programmers.

The host system can detect whether a program or erase op-

eration is complete by observing the RY/BY# pin, or by read-

ing the DQ7 (Data# Polling) and DQ6 (toggle) status bits.

After a program or erase cycle has been completed, the de-

vice is ready to read array data or accept another command.

The sector erase architecture allows memory sectors to be

erased and reprogrammed without affecting the data con-

tents of other sectors. The device is fully erased when

shipped from the factory.

The standard device offers access times of 100, 110, 120,

and 150 ns, allowing high speed microprocessors to operate

without wait states. To eliminate bus contention the device

has separate chip enable (CE#), write enable (WE#) and

output enable (OE#) controls.

Hardware data protection measures include a low V_CCde-

tector that automatically inhibits write operations during

power transitions. The hardware sector protection feature

disables both program and erase operations in any combina-

tion of the sectors of memory. This can be achieved in-sys-

tem or via programming equipment.

The device requires only a single 1.8 volt power supply for

both read and write functions. Internally generated and regu-

lated voltages are provided for the program and erase opera-

tions.

The Erase Suspend feature enables the user to put erase

on hold for any period of time to read data from, or program

data to, any sector that is not selected for erasure. True

background erase can thus be achieved.

The device is entirely command set compatible with the

JEDEC single-power-supply Flash standard. Commands

are written to the command register using standard micro-

processor write timings. Register contents serve as input to

an internal state-machine that controls the erase and pro-

gramming circuitry. Write cycles also internally latch ad-

dresses and data needed for the programming and erase

operations. Reading data out of the device is similar to read-

ing from other Flash or EPROM devices.

The hardware RESET# pin terminates any operation in

progress and resets the internal state machine to reading

array data. The RESET# pin may be tied to the system reset

circuitry. A system reset would thus also reset the device,

enabling the system microprocessor to read the boot-up

firmware from the Flash memory.

The device offers two power-saving features. When ad-

dresses have been stable for a specified amount of time, the

device enters the automatic sleep mode. The system can

also place the device into the standby mode. Power con-

sumption is greatly reduced in both these modes.

Device programming occurs by executing the program com-

mand sequence. This initiates the Embedded Program al-

gorithm—an internal algorithm that automatically times the

program pulse widths and verifies proper cell margin. The

Unlock Bypass mode facilitates faster programming times

by requiring only two write cycles to program data instead of

four.

AMD’s Flash technology combines years of Flash memory

manufacturing experience to produce the highest levels of

quality, reliability and cost effectiveness. The device electri-

cally erases all bits within a sector simultaneously via

Fowler-Nordheim tunneling. The data is programmed using

hot electron injection.

Device erasure occurs by executing the erase command se-

quence. This initiates the Embedded Erase algorithm—an

internal algorithm that automatically preprograms the array

(if it is not already programmed) before executing the erase

operation. During erase, the device automatically times the

erase pulse widths and verifies proper cell margin.

2

Am29SL400C

Am29SL400C_00_A6 January 23, 2007

D A T A S H E E T

TABLE OF CONTENTS

Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . .3

Product Selector Guide . . . . . . . . . . . . . . . . . . . . .4

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 5

Special Handling Instructions for FBGA Packages 6

Ordering Information . . . . . . . . . . . . . . . . . . . . . . .8

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 9

Table 1. Am29SL400C Device Bus Operations ............9

Word/Byte Configuration ........................................9

Requirements for Reading Array Data ...................9

Writing Commands/Command Sequences ............9

Program and Erase Operation Status ..................10

Standby Mode ......................................................10

Automatic Sleep Mode .........................................10

RESET#: Hardware Reset Pin .............................10

Output Disable Mode ............................................10

Table 2. Am29SL400CT Top Boot Block

Reading Toggle Bits DQ6/DQ2 ............................ 20

Figure 6. Toggle Bit Algorithm..................................... 21

DQ5: Exceeded Timing Limits .............................. 21

DQ3: Sector Erase Timer ..................................... 21

Table 6. Write Operation Status ..................................22

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 23

Figure 7. Maximum Negative Overshoot Waveform ... 23

Figure 8. Maximum Positive Overshoot Waveform..... 23

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 9. I_CC1Current vs. Time (Showing Active and Au-

tomatic Sleep Currents)............................................... 25

Figure 10. Typical I_CC1vs. Frequency ........................ 25

Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 11. Test Setup.................................................. 26

Table 7. Test Specifications ........................................26

Key to Switching Waveforms ................................ 26

Figure 12. Input Waveforms

and Measurement Levels............................................ 26

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 13. Read Operations Timings .......................... 27

Figure 14. RESET# Timings........................................ 28

Figure 15. BYTE# Timings for Read Operations......... 29

Figure 16. BYTE# Timings for Write Operations......... 29

Figure 17. Program Operation Timings....................... 31

Figure 18. Chip/Sector Erase Operation Timings........ 32

Figure 19. Data# Polling Timings

(During Embedded Algorithms)................................... 33

Figure 20. Toggle Bit Timings

(During Embedded Algorithms)................................... 33

Figure 21. DQ2 vs. DQ6.............................................. 34

Temporary Sector Unprotect ................................ 34

Figure 22. Temporary Sector Unprotect

Timing Diagram........................................................... 34

Figure 23. Sector Protect/Unprotect Timing Diagram . 35

Figure 24. Alternate CE# Controlled

Write Operation Timings.............................................. 37

Erase and Programming Performance . . . . . . . . 38

Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 39

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 40

TS048—48-Pin Standard TSOP .......................... 40

FBA048—48-Ball Fine-Pitch Ball Grid Array (FBGA)

6 x 8 mm Package ................................................ 41

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 42

Sector Address Table ..................................................11

Table 3. Am29SL400CB Bottom Boot Block

Sector Address Table ..................................................11

Autoselect Mode ...................................................11

Table 4. Am29SL400C Autoselect Codes

(High Voltage Method) ................................................12

Sector Protection/Unprotection ............................12

Temporary Sector Unprotect ................................12

Figure 2. Temporary Sector Unprotect Operation....... 14

Hardware Data Protection ....................................14

Command Definitions . . . . . . . . . . . . . . . . . . . . . 15

Reading Array Data ..............................................15

Reset Command ..................................................15

Autoselect Command Sequence ..........................15

Word/Byte Program Command Sequence ...........15

Figure 3. Program Operation ...................................... 16

Chip Erase Command Sequence .........................16

Sector Erase Command Sequence ......................16

Figure 4. Erase Operation........................................... 17

Command Definitions ...........................................18

Table 5. Am29SL400C Command Definitions ............18

Write Operation Status . . . . . . . . . . . . . . . . . . . . .19

DQ7: Data# Polling ...............................................19

Figure 5. Data# Polling Algorithm ............................... 19

RY/BY#: Ready/Busy# .........................................19

DQ6: Toggle Bit I ..................................................20

DQ2: Toggle Bit II .................................................20

January 23, 2007 Am29SL400C_00_A6

Am29SL400C

3

D A T A S H E E T

PRODUCT SELECTOR GUIDE

Family Part Number

Am29SL400C

Regulated Voltage Range V_CC= 1.7–2.2 V

Standard Voltage Range V_CC= 1.65–2.2 V

-100R

Speed Options

-110

-120

120

50

-150

150

65

Max access time, ns (t_ACC

Max CE# access time, ns (t_CE

Max OE# access time, ns (t_OE

)

100

35

110

45

)

Note: See “AC Characteristics” for full specifications.

BLOCK DIAGRAM

DQ0–DQ15 (A-1)

RY/BY#

V_CC

Sector Switches

V_SS

Erase Voltage

Generator

Input/Output

Buffers

RESET#

State

Control

WE#

BYTE#

Command

Register

PGM Voltage

Generator

Data

Latch

Chip Enable

Output Enable

Logic

STB

CE#

OE#

Y-Decoder

Y-Gating

STB

V_CCDetector

Timer

Cell Matrix

X-Decoder

A0–A17

4

Am29SL400C

Am29SL400C_00_A6 January 23, 2007

D A T A S H E E T

CONNECTION DIAGRAMS

A15

A14

A13

A12

A11

A10

A9

1

2

3

4

5

6

7

8

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A16

BYTE#

V_SS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

V_CC

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

V_SS

CE#

A0

A8

NC

WE#

RESET#

NC

RY/BY#

NC

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

Standard TSOP

A17

A7

A6

A5

A4

A3

A2

A1

January 23, 2007 Am29SL400C_00_A6

Am29SL400C

5

D A T A S H E E T

CONNECTION DIAGRAM

48-Ball FBGA

(Top View, Balls Facing Down)

A6

B6

C6

D6

E6

F6

G6

H6

A13

A12

A14

A15

A16

BYTE# DQ15/A-1 V_SS

A5

A9

B5

A8

C5

D5

E5

F5

G5

H5

A10

A11

DQ7

DQ14

DQ13

DQ6

A4

B4

C4

D4

E4

F4

G4

H4

WE# RESET#

NC

DQ5

DQ12

V_CC

DQ4

A3

B3

C3

D3

E3

F3

G3

H3

RY/BY#

NC

DQ2

DQ10

DQ11

DQ3

A2

A7

B2

C2

A6

D2

A5

E2

F2

G2

H2

A17

DQ0

DQ8

DQ9

DQ1

A1

A3

B1

A4

C1

A2

D1

A1

E1

A0

F1

G1

H1

CE#

OE#

V_SS

package and/or data integrity may be compromised if the

^{package body is exposed to temperatures about 150}°C for

prolonged periods of time.

Special Handling Instructions for FBGA

Packages

Special handling is required for Flash Memory products in

molded packages (TSOP, BGA, PLCC, PDIP, SSOP). The

6

Am29SL400C

Am29SL400C_00_A6 January 23, 2007

D A T A S H E E T

PIN CONFIGURATION

LOGIC SYMBOL

A0–A17

=

18 addresses

DQ0–DQ14 = 15 data inputs/outputs

18

DQ15/A-1

=

DQ15 (data input/output, word mode),

A-1 (LSB address input, byte mode)

A0–A17

16 or 8

DQ0–DQ15

(A-1)

BYTE#

CE#

=

Selects 8-bit or 16-bit mode

Chip enable

CE#

OE#

Output enable

WE#

Write enable

WE#

RESET#

RY/BY#

Hardware reset pin, active low

Ready/Busy# output

1.65–2.2 V single power supply

Device ground

RESET#

BYTE#

RY/BY#

V

CC

SS

NC

Pin not connected internally

January 23, 2007 Am29SL400C_00_A6

Am29SL400C

7

D A T A S H E E T

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed

by a combination of the elements below.

Am29SL400C

T

100R

E

C

TEMPERATURE RANGE

C

D

F

I

=

Commercial (0°C to +70°C)

Commercial (0°C to +70°C) with Pb-free Package

Industrial (-40°C to +85°C) with Pb-free Package

Industrial (–40°C to +85°C)

PACKAGE TYPE

WA = 48-Ball Fine-Pitch Ball Grid Array (FBGA)

0.80 mm pitch, 6 x 8 mm package (FBA048)

48-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS048)

E

=

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T

B

=

Top Sector

Bottom Sector

DEVICE NUMBER/DESCRIPTION

Am29SL400C

4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS Flash Memory

1.8 Volt-only Read, Program, and Erase

Valid Combinations for TSOP Packages

Order Number

Valid Combinations for FBGA Packages

Order Number Package Marking

AM29SL400CT100R,

AM29SL400CB100R

AM29SL400CT100R,

AM29SL400CB100R

A400CT10R,

A400CB10R

AM29SL400CT110,

AM29SL400CB110

AM29SL400CT110,

AM29SL400CB110

A400CT11V,

A400CB11V

WAC

WAI

EC, EI,

ED, EF

C, I,

D, F

WAD,

WAF

AM29SL400CT120,

AM29SL400CB120

AM29SL400CT120,

AM29SL400CB120

A400CT12V,

A400CB12V

AM29SL400CT150,

AM29SL400CB150

AM29SL400CT150,

AM29SL400CB150

A400CT15V,

A400CB15V

Valid Combinations

Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to

confirm availability of specific valid combinations and to check on newly released combinations.

8

Am29SL400C

Am29SL400C_00_A6 January 23, 2007

D A T A S H E E T

DEVICE BUS OPERATIONS

This section describes the requirements and use of the de-

vice bus operations, which are initiated through the internal

command register. The command register itself does not oc-

cupy any addressable memory location. The register is com-

posed of latches that store the commands, along with the

address and data information needed to execute the com-

mand. The contents of the register serve as inputs to the in-

ternal state machine. The state machine outputs dictate the

function of the device. Table 1 lists the device bus opera-

tions, the inputs and control levels they require, and the re-

sulting output. The following subsections describe each of

these operations in further detail.

Table 1. Am29SL400C Device Bus Operations

DQ8–DQ15

BYTE#

Addresses

(Note 1)

DQ0–

DQ7

BYTE#

= V_IH

Operation

CE#

L

OE# WE# RESET#

= V_IL

Read

Write

L

H

L

H

A_IN

D_OUT

D_IN

D_OUT

D_IN

DQ8–DQ14 = High-Z,

DQ15 = A-1

L

H

V_CC

0.2 V

±

V_CC±

0.2 V

Standby

X

High-Z

Output Disable

Reset

L

H

X

H

X

H

L

X

High-Z

X

Sector Address, A6

= L, A1 = H,

A0 = L

Sector Protect (Note 2)

L

H

L

V_ID

D_IN

X

Sector Address, A6

= H, A1 = H,

A0 = L

Sector Unprotect (Note 2)

L

H

X

L

V_ID

D_IN

X

Temporary Sector Unprotect

X

A_IN

D_IN

High-Z

Legend:

L = Logic Low = V_IL, H = Logic High = V_IH, V_ID= 10 ± 1.0 V, X = Don’t Care, A_IN= Address In, D_IN= Data In, D_OUT= Data Out

Notes:

1. Addresses are A17:A0 in word mode (BYTE# = V_IH), A17:A-1 in byte mode (BYTE# = V_IL).

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector

Protection/Unprotection” section.

that no spurious alteration of the memory content occurs

Word/Byte Configuration

during the power transition. No command is necessary in

The BYTE# pin controls whether the device data I/O pins

this mode to obtain array data. Standard microprocessor

DQ15–DQ0 operate in the byte or word configuration. If the

read cycles that assert valid addresses on the device ad-

BYTE# pin is set at logic ‘1’, the device is in word configura-

dress inputs produce valid data on the device data outputs.

tion, DQ15–DQ0 are active and controlled by CE# and OE#.

The device remains enabled for read access until the com-

mand register contents are altered.

If the BYTE# pin is set at logic ‘0’, the device is in byte con-

figuration, and only data I/O pins DQ0–DQ7 are active and

controlled by CE# and OE#. The data I/O pins DQ8–DQ14

are tri-stated, and the DQ15 pin is used as an input for the

LSB (A-1) address function.

See Reading Array Data‚ on page 15 for more information.

Refer to the AC Read Operations table for timing specifica-

tions and to Figure 14‚ on page 28 for the timing diagram.

I_CC1in the DC Characteristics table represents the active

current specification for reading array data.

Requirements for Reading Array Data

Writing Commands/Command Sequences

To read array data from the outputs, the system must drive

the CE# and OE# pins to V_IL. CE# is the power control and

selects the device. OE# is the output control and gates array

data to the output pins. WE# should remain at V_IH. The

BYTE# pin determines whether the device outputs array

data in words or bytes.

To write a command or command sequence (which includes

programming data to the device and erasing sectors of

memory), the system must drive WE# and CE# to V_IL, and

OE# to V_IH.

For program operations, the BYTE# pin determines whether

the device accepts program data in bytes or words. Refer

to Word/Byte Configuration‚ on page 9 for more information.

The internal state machine is set for reading array data upon

device power-up, or after a hardware reset. This ensures

January 23, 2007 Am29SL400C_00_A6

Am29SL400C

9

D A T A S H E E T

The device features an Unlock Bypass mode to facilitate

If the device is deselected during erasure or programming,

the device draws active current until the operation is com-

pleted.

faster programming. Once the device enters the Unlock By-

pass mode, only two write cycles are required to program a

word or byte, instead of four. The Word/Byte Program Com-

mand Sequence‚ on page 15 has details on programming

data to the device using both standard and Unlock Bypass

command sequences.

I_CC3in DC Characteristics‚ on page 24 represents the

standby current specification.

Automatic Sleep Mode

An erase operation can erase one sector, multiple sectors, or

the entire device. Table 2 on page 11 and Table 3 on

page 11 indicate the address space that each sector occu-

pies. A sector address consists of the address bits required

to uniquely select a sector. Command Definitions‚ on

page 18 has details on erasing a sector or the entire chip, or

suspending/resuming the erase operation.

The automatic sleep mode minimizes Flash device energy

consumption. The device automatically enables this mode

when addresses remain stable for t_ACC+ 50 ns. The auto-

matic sleep mode is independent of the CE#, WE#, and OE#

control signals. Standard address access timings provide

new data when addresses are changed. While in sleep

mode, output data is latched and always available to the sys-

tem. I_CC4in the DC Characteristics table represents the au-

tomatic sleep mode current specification.

After the system writes the autoselect command sequence,

the device enters the autoselect mode. The system can then

read autoselect codes from the internal register (which is

separate from the memory array) on DQ7–DQ0. Standard

read cycle timings apply in this mode. Refer to Autoselect

Mode‚ on page 11 and Autoselect Command Sequence‚ on

page 15 for more information.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of resetting

the device to reading array data. When the RESET# pin is

driven low for at least a period of t_RP, the device immedi-

ately terminates any operation in progress, tristates all out-

put pins, and ignores all read/write commands for the

duration of the RESET# pulse. The device also resets the in-

ternal state machine to reading array data. The operation

that was interrupted should be reinitiated once the device is

ready to accept another command sequence, to ensure data

integrity.

I_CC2in the DC Characteristics table represents the active

current specification for the write mode. The AC Character-

istics‚ on page 28 contains timing specification tables and

timing diagrams for write operations.

Program and Erase Operation Status

During an erase or program operation, the system may

check the status of the operation by reading the status bits

on DQ7–DQ0. Standard read cycle timings and I_CCread

specifications apply. Refer to Write Operation Status‚ on

page 19 for more information, and to AC Characteristics‚ on

page 28 for timing diagrams.

Current is reduced for the duration of the RESET# pulse.

When RESET# is held at V_SS0.2 V, the device draws

CMOS standby current (I_CC4). If RESET# is held at V_ILbut

not within V_SS0.2 V, the standby current is greater.

The RESET# pin may be tied to the system reset circuitry. A

system reset would thus also reset the Flash memory, en-

abling the system to read the boot-up firmware from the

Flash memory.

Standby Mode

When the system is not reading or writing to the device, it

can place the device in the standby mode. In this mode, cur-

rent consumption is greatly reduced, and the outputs are

placed in the high impedance state, independent of the OE#

input.

If RESET# is asserted during a program or erase operation,

the RY/BY# pin remains a 0 (busy) until the internal reset op-

eration is complete, which requires a time of t_READY(during

Embedded Algorithms). The system can thus monitor

RY/BY# to determine whether the reset operation is com-

plete. If RESET# is asserted when a program or erase oper-

ation is not executing (RY/BY# pin is 1), the reset operation

is completed within a time of t_READY(not during Embedded

Algorithms). The system can read data t_RHafter the RE-

SET# pin returns to V_IH.

The device enters the CMOS standby mode when the CE#

and RESET# pins are both held at V_CC± 0.2 V. (Note that

this is a more restricted voltage range than V_IH.) If CE# and

RESET# are held at V_IH, but not within V_CC± 0.2 V, the de-

vice will be in the standby mode, but the standby current will

be greater. The device requires standard access time (t_CE

)

for read access when the device is in either of these standby

modes, before it is ready to read data.

Refer to the AC Characteristics tables for RESET# parame-

ters and to Figure 15‚ on page 29 for the timing diagram.

The device also enters the standby mode when the RESET#

pin is driven low. Refer to the next section, RESET#: Hard-

ware Reset Pin.

Output Disable Mode

When the OE# input is at V_IH, output from the device is dis-

abled. The output pins are placed in the high impedance

state.

10

Am29SL400C

Am29SL400C_00_A6 January 23, 2007

D A T A S H E E T

Table 2. Am29SL400CT Top Boot Block Sector Address Table

Address Range (in hexadecimal)

Sector Size

(Kbytes/

(x8)

(x16)

Sector

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

A17

0

A16

0

A15

0

A14

X

0

A13

X

A12

X

Kwords)

Address Range

64/32

32/16

8/4

00000h–0FFFFh

10000h–1FFFFh

20000h–2FFFFh

30000h–3FFFFh

40000h–4FFFFh

50000h–5FFFFh

60000h–6FFFFh

70000h–77FFFh

78000h–79FFFh

7A000h–7BFFFh

7C000h–7FFFFh

00000h–07FFFh

08000h–0FFFFh

10000h–17FFFh

18000h–1FFFFh

20000h–27FFFh

28000h–2FFFFh

30000h–37FFFh

38000h–3BFFFh

3C000h–3CFFFh

3D000h–3DFFFh

3E000h–3FFFFh

0

1

X

0

1

0

X

0

1

X

1

0

X

1

0

1

X

1

0

X

1

X

1

0

1

0

1

8/4

1

X

16/8

Table 3. Am29SL400CB Bottom Boot Block Sector Address Table

Address Range (in hexadecimal)

Sector Size

(Kbytes/

(x8)

(x16)

Sector

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

A17

0

A16

0

A15

0

A14

0

A13

0

A12

X

Kwords)

Address Range

16/8

8/4

00000h–03FFFh

04000h–05FFFh

06000h–07FFFh

08000h–0FFFFh

10000h–1FFFFh

20000h–2FFFFh

30000h–3FFFFh

40000h–4FFFFh

50000h–5FFFFh

60000h–6FFFFh

70000h–7FFFFh

00000h–01FFFh

02000h–02FFFh

03000h–03FFFh

04000h–07FFFh

08000h–0FFFFh

10000h–17FFFh

18000h–1FFFFh

20000h–27FFFh

28000h–2FFFFh

30000h–37FFFh

38000h–3FFFFh

0

1

0

1

8/4

0

1

X

32/16

64/32

0

1

X

0

1

0

X

0

1

X

1

0

X

1

0

1

X

1

0

X

1

X

Note for Tables 2 and 3: Address range is A17:A-1 in byte mode and A17:A0 in word mode. See “Word/Byte Configuration” section for more

information.

appear on the appropriate highest order address bits (see

Autoselect Mode

Table 2 on page 11 and Table 3 on page 11). Table 4 shows

The autoselect mode provides manufacturer and device

the remaining address bits that are don’t care. When all nec-

identification, and sector protection verification, through

essary bits have been set as required, the programming

identifier codes output on DQ7–DQ0. This mode is primarily

equipment may then read the corresponding identifier code

intended for programming equipment to automatically match

on DQ7–DQ0.

a device to be programmed with its corresponding program-

To access the autoselect codes in-system, the host system

can issue the autoselect command via the command regis-

ter, as shown in Table 5 on page 18. This method does not

require V_ID. See Command Definitions‚ on page 18 for de-

tails on using the autoselect mode.

ming algorithm. However, the autoselect codes can also be

accessed in-system through the command register.

When using programming equipment, the autoselect mode

requires V_IDon address pin A9. Address pins A6, A1, and

A0 must be as shown in Table 4 on page 12. In addition,

when verifying sector protection, the sector address must

January 23, 2007 Am29SL400C_00_A6

Am29SL400C

11

D A T A S H E E T

Table 4. Am29SL400C Autoselect Codes (High Voltage Method)

A17t A11

to

WE# A12 A10

A8

to

A7

A5

to

A2

DQ8

to

DQ15

DQ7

to

DQ0

o

Description

Mode

CE#

L

OE#

A9

A6

A1

A0

Manufacturer ID: AMD

L

H

X

V_ID

X

L

X

L

X

01h

70h

Device ID:

Am29SL400C

(Top Boot Block)

Word

Byte

Word

Byte

L

22h

X

V_ID

L

H

L

H

X

22h

X

70h

F1h

Device ID:

Am29SL400C

(Bottom Boot Block)

X

V_ID

X

F1h

X

01h (protected)

Sector Protection Verification

L

H

SA

V_ID

L

H

L

00h

(unprotected)

X

L = Logic Low = V_IL, H = Logic High = V_IH, SA = Sector Address, X = Don’t care.

factory prior to shipping the device through AMD’s Express-

Flash™ Service. Contact an AMD representative for details.

Sector Protection/Unprotection

The hardware sector protection feature disables both pro-

gram and erase operations in any sector. The hardware sec-

tor unprotection feature re-enables both program and erase

operations in previously protected sectors. Sector protec-

tion/unprotection can be implemented via two methods.

It is possible to determine whether a sector is protected or

unprotected. See Autoselect Mode‚ on page 11 for details.

Temporary Sector Unprotect

This feature allows temporary unprotection of previously pro-

tected sectors to change data in-system. The Sector Unpro-

tect mode is activated by setting the RESET# pin to V_ID.

During this mode, formerly protected sectors can be pro-

grammed or erased by selecting the sector addresses. Once

V_IDis removed from the RESET# pin, all the previously pro-

tected sectors are protected again. Figure 3‚ on page 16

shows the algorithm, and Figure 22 shows the timing dia-

grams, for this feature.

Sector protection/unprotection requires V_IDon the RESET#

pin only, and can be implemented either in-system or via

programming equipment. Figure 2‚ on page 14 shows the al-

gorithms and Figure 24‚ on page 37 shows the timing dia-

gram. This method uses standard microprocessor bus cycle

timing. For sector unprotect, all unprotected sectors must

first be protected prior to the first sector unprotect write cy-

cle.

The device is shipped with all sectors unprotected. AMD of-

fers the option of programming and protecting sectors at its

12

Am29SL400C

Am29SL400C_00_A6 January 23, 2007

D A T A S H E E T

START

Protect all sectors:

The indicated portion

of the sector protect

algorithm must be

performed for all

PLSCNT = 1

RESET# = V_ID

unprotected sectors

prior to issuing the

first sector

Wait 1 μs

unprotect address

No

First Write

Cycle = 60h?

No

First Write

Cycle = 60h?

Temporary Sector

Unprotect Mode

Temporary Sector

Unprotect Mode

Yes

Set up sector

address

No

All sectors

protected?

Sector Protect:

Write 60h to sector

address with

A6 = 0, A1 = 1,

A0 = 0

Yes

Set up first sector

address

Sector Unprotect:

Wait 150 µs

Write 60h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Verify Sector

Protect: Write 40h

to sector address

with A6 = 0,

Reset

PLSCNT = 1

Increment

PLSCNT

Wait 15 ms

A1 = 1, A0 = 0

Verify Sector

Unprotect: Write

40h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector address

with A6 = 0,

A1 = 1, A0 = 0

Increment

PLSCNT

No

PLSCNT

= 25?

Read from

sector address

with A6 = 1,

Data = 01h?

Yes

A1 = 1, A0 = 0

No

Yes

Set up

next sector

address

Yes

No

PLSCNT

= 1000?

Protect another

sector?

Data = 00h?

Yes

Device failed

No

Yes

Remove V_ID

from RESET#

No

Last sector

verified?

Device failed

Write reset

command

Yes

Remove V_ID

Sector Unprotect

Algorithm

from RESET#

Sector Protect

Algorithm

Sector Protect

complete

Write reset

command

Sector Unprotect

complete

Figure 1. In-System Sector Protect/

Unprotect Algorithms

January 23, 2007 Am29SL400C_00_A6

Am29SL400C

13

D A T A S H E E T

definitions). In addition, the following hardware data protec-

tion measures prevent accidental erasure or programming,

which might otherwise be caused by spurious system level

signals during V_CCpower-up and power-down transitions, or

from system noise.

START

RESET# = V_ID

(Note 1)

Low V

Write Inhibit

CC

When V_CCis less than V_LKO, the device does not accept any

write cycles. This protects data during V_CCpower-up and

power-down. The command register and all internal pro-

gram/erase circuits are disabled, and the device resets. Sub-

Perform Erase or

Program Operations

sequent writes are ignored until V_CCis greater than V_LKO

.

The system must provide the proper signals to the control

pins to prevent unintentional writes when V_CCis greater than

RESET# = V_IH

V_LKO

.

Write Pulse “Glitch” Protection

Temporary Sector

Unprotect Completed

(Note 2)

Noise pulses of less than 5 ns (typical) on OE#, CE# or WE#

do not initiate a write cycle.

Logical Inhibit

Notes:

Write cycles are inhibited by holding any one of OE# = V_IL,

CE# = V_IHor WE# = V_IH. To initiate a write cycle, CE# and

WE# must be a logical zero while OE# is a logical one.

1. All protected sectors unprotected.

2. All previously protected sectors are protected once again.

Power-Up Write Inhibit

Figure 2. Temporary Sector Unprotect Operation

If WE# = CE# = V_ILand OE# = V_IHduring power up, the de-

vice does not accept commands on the rising edge of WE#.

The internal state machine is automatically reset to reading

array data on power-up.

Hardware Data Protection

The command sequence requirement of unlock cycles for

programming or erasing provides data protection against in-

advertent writes (refer to Table 5 on page 18 for command

14

Am29SL400C

Am29SL400C_00_A6 January 23, 2007

D A T A S H E E T

COMMAND DEFINITIONS

Writing specific address and data commands or sequences

into the command register initiates device operations.

Table 5 on page 18 defines the valid register command se-

quences. Writing incorrect address and data values or

writing them in the improper sequence resets the device to

reading array data.

If DQ5 goes high during a program or erase operation, writ-

ing the reset command returns the device to reading array

data (also applies during Erase Suspend).

Autoselect Command Sequence

The autoselect command sequence allows the host system

to access the manufacturer and devices codes, and deter-

mine whether or not a sector is protected. Table 5 on

page 18 shows the address and data requirements. This

method is an alternative to that shown in Table 4 on page 12,

which is intended for PROM programmers and requires V_ID

on address bit A9.

All addresses are latched on the falling edge of WE# or CE#,

whichever happens later. All data is latched on the rising

edge of WE# or CE#, whichever happens first. Refer to the

appropriate timing diagrams in the AC Characteristics sec-

tion.

Reading Array Data

The autoselect command sequence is initiated by writing two

unlock cycles, followed by the autoselect command. The de-

vice then enters the autoselect mode, and the system may

read at any address any number of times, without initiating

another command sequence. A read cycle at address

XX00h retrieves the manufacturer code. A read cycle at ad-

dress 01h in word mode (or 02h in byte mode) returns the

device code. A read cycle containing a sector address (SA)

and the address 02h in word mode (or 04h in byte mode) re-

turns 01h if that sector is protected, or 00h if it is unpro-

tected. Refer to Table 2 on page 11 and Table 3 on page 11

for valid sector addresses.

The device is automatically set to reading array data after

device power-up. No commands are required to retrieve

data. The device is also ready to read array data after com-

pleting an Embedded Program or Embedded Erase algo-

rithm.

After the device accepts an Erase Suspend command, the

device enters the Erase Suspend mode. The system can

read array data using the standard read timings, except that

if it reads at an address within erase-suspended sectors, the

device outputs status data. After completing a programming

operation in the Erase Suspend mode, the system may once

again read array data with the same exception. See “Erase

Suspend/Erase Resume Commands” for more information

on this mode.

The system must write the reset command to exit the au-

toselect mode and return to reading array data.

Word/Byte Program Command Sequence

The system must issue the reset command to re-enable the

device for reading array data if DQ5 goes high, or while in

the autoselect mode. See the Reset Command‚ on page 15

section, next.

The system may program the device by word or byte, de-

pending on the state of the BYTE# pin. Programming is a

four-bus-cycle operation. The program command sequence

is initiated by writing two unlock write cycles, followed by the

program set-up command. The program address and data

are written next, which in turn initiate the Embedded Pro-

gram algorithm. The system is not required to provide further

controls or timings. The device automatically generates the

program pulses and verifies the programmed cell margin.

Table 5 on page 18 shows the address and data require-

ments for the byte program command sequence.

See also Requirements for Reading Array Data‚ on page 9

for more information. The Read Operations table provides

the read parameters, and Figure 14‚ on page 28 shows the

timing diagram.

Reset Command

Writing the reset command to the device resets the device to

reading array data. Address bits are don’t care for this com-

mand.

When the Embedded Program algorithm is complete, the de-

vice then returns to reading array data and addresses are no

longer latched. The system can determine the status of the

program operation by using DQ7, DQ6, or RY/BY#. See

Write Operation Status‚ on page 19 for information on these

status bits.

The reset command may be written between the sequence

cycles in an erase command sequence before erasing be-

gins. This resets the device to reading array data. Once era-

sure begins, however, the device ignores reset commands

until the operation is complete.

Any commands written to the device during the Embedded

Program Algorithm are ignored. Note that a hardware reset

immediately terminates the programming operation. The

Byte Program command sequence should be reinitiated

once the device has reset to reading array data, to ensure

data integrity.

The reset command may be written between the sequence

cycles in a program command sequence before program-

ming begins. This resets the device to reading array data

(also applies to programming in Erase Suspend mode).

Once programming begins, however, the device ignores

reset commands until the operation is complete.

Programming is allowed in any sequence and across sector

boundaries. A bit cannot be programmed from a 0 back

to a 1. Attempting to do so may halt the operation and set

DQ5 to 1, or cause the Data# Polling algorithm to indicate

the operation was successful. However, a succeeding read

will show that the data is still 0. Only erase operations can

convert a 0 to a 1.

The reset command may be written between the sequence

cycles in an autoselect command sequence. Once in the au-

toselect mode, the reset command must be written to return

to reading array data (also applies to autoselect during

Erase Suspend).

January 23, 2007 Am29SL400C_00_A6

Am29SL400C

15

D A T A S H E E T

Unlock Bypass Command Sequence

Chip Erase Command Sequence

The unlock bypass feature allows the system to program

bytes or words to the device faster than using the standard

program command sequence. The unlock bypass command

sequence is initiated by first writing two unlock cycles. This is

followed by a third write cycle containing the unlock bypass

command, 20h. The device then enters the unlock bypass

mode. A two-cycle unlock bypass program command se-

quence is all that is required to program in this mode. The

first cycle in this sequence contains the unlock bypass pro-

gram command, A0h; the second cycle contains the pro-

gram address and data. Additional data is programmed in

the same manner. This mode dispenses with the initial two

unlock cycles required in the standard program command

sequence, resulting in faster total programming time. Table 5

on page 18 shows the requirements for the command se-

quence.

Chip erase is a six bus cycle operation. The chip erase com-

mand sequence is initiated by writing two unlock cycles, fol-

lowed by a set-up command. Two additional unlock write

cycles are then followed by the chip erase command, which

in turn invokes the Embedded Erase algorithm. The device

does not require the system to preprogram prior to erase.

The Embedded Erase algorithm automatically preprograms

and verifies the entire memory for an all zero data pattern

prior to electrical erase. The system is not required to pro-

vide any controls or timings during these operations. Table 5

on page 18 shows the address and data requirements for

the chip erase command sequence.

Any commands written to the chip during the Embedded

Erase algorithm are ignored. Note that a hardware reset

during the chip erase operation immediately terminates the

operation. The Chip Erase command sequence should be

reinitiated once the device has returned to reading array

data, to ensure data integrity The system can determine the

status of the erase operation by using DQ7, DQ6, DQ2, or

RY/BY#. See Write Operation Status‚ on page 19 for infor-

mation on these status bits. When the Embedded Erase al-

gorithm is complete, the device returns to reading array data

and addresses are no longer latched.

During the unlock bypass mode, only the Unlock Bypass

Program and Unlock Bypass Reset commands are valid. To

exit the unlock bypass mode, the system must issue the

two-cycle unlock bypass reset command sequence. The first

cycle must contain the data 90h; the second cycle the data

00h. Addresses are don’t cares. The device then returns to

reading array data.

Figure 3‚ on page 16 illustrates the algorithm for the program

operation. See Erase/Program Operations‚ on page 30 for

parameters, and Figure 17‚ on page 31 for timing diagrams.

Figure 4‚ on page 17 illustrates the algorithm for the erase

operation. See Erase/Program Operations‚ on page 30 for

parameters, and to Figure 18 for timing diagrams.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector erase

command sequence is initiated by writing two unlock cycles,

followed by a set-up command. Two additional unlock write

cycles are then followed by the address of the sector to be

erased, and the sector erase command. Table 5 on page 18

shows the address and data requirements for the sector

erase command sequence.

START

Write Program

Command Sequence

The device does not require the system to preprogram the

memory prior to erase. The Embedded Erase algorithm au-

tomatically programs and verifies the sector for an all zero

data pattern prior to electrical erase. The system is not re-

quired to provide any controls or timings during these opera-

tions.

Data Poll

from System

Embedded

Program

algorithm

in progress

Verify Data?

No

After the command sequence is written, a sector erase

time-out of 50 µs begins. During the time-out period, addi-

tional sector addresses and sector erase commands may be

written. Loading the sector erase buffer may be done in any

sequence, and the number of sectors may be from one sec-

tor to all sectors. The time between these additional cycles

must be less than 50 µs, otherwise the last address and

command might not be accepted, and erasure may begin. It

is recommended that processor interrupts be disabled dur-

ing this time to ensure all commands are accepted. The in-

terrupts can be re-enabled after the last Sector Erase

command is written. If the time between additional sector

erase commands can be assumed to be less than 50 µs, the

system need not monitor DQ3. Any command other than

Sector Erase or Erase Suspend during the time-out pe-

riod resets the device to reading array data. The system

must rewrite the command sequence and any additional

sector addresses and commands.

Yes

No

Increment Address

Last Address?

Yes

Programming

Completed

Note: See Table 5 for program command sequence.

Figure 3. Program Operation

16

Am29SL400C

Am29SL400C_00_A6 January 23, 2007

D A T A S H E E T

The system can monitor DQ3 to determine if the sector

After an erase-suspended program operation is complete,

the system can once again read array data within non-sus-

pended sectors. The system can determine the status of the

program operation using the DQ7 or DQ6 status bits, just as

in the standard program operation. See Write Operation

Status‚ on page 19 for more information.

erase timer has timed out. (See the “DQ3: Sector Erase

Timer” section.) The time-out begins from the rising edge of

the final WE# pulse in the command sequence.

Once the sector erase operation has begun, only the Erase

Suspend command is valid. All other commands are ig-

nored. Note that a hardware reset during the sector erase

operation immediately terminates the operation. The Sector

Erase command sequence should be reinitiated once the

device has returned to reading array data, to ensure data in-

tegrity.

The system may also write the autoselect command se-

quence when the device is in the Erase Suspend mode. The

device allows reading autoselect codes even at addresses

within erasing sectors, since the codes are not stored in the

memory array. When the device exits the autoselect mode,

the device reverts to the Erase Suspend mode, and is ready

for another valid operation. See Autoselect Command Se-

quence‚ on page 15 for more information.

When the Embedded Erase algorithm is complete, the de-

vice returns to reading array data and addresses are no

longer latched. The system can determine the status of the

erase operation by using DQ7, DQ6, DQ2, or RY/BY#. (Re-

fer to Write Operation Status‚ on page 19 for information on

these status bits.)

The system must write the Erase Resume command (ad-

dress bits are “don’t care”) to exit the erase suspend mode

and continue the sector erase operation. Further writes of

the Resume command are ignored. Another Erase Suspend

command can be written after the device has resumed eras-

ing.

Figure 4 illustrates the algorithm for the erase operation.

Refer to the Erase/Program Operations‚ on page 30 for pa-

rameters, and to Figure 18‚ on page 32 for timing diagrams.

Erase Suspend/Erase Resume Commands

The Erase Suspend command allows the system to interrupt

a sector erase operation and then read data from, or pro-

gram data to, any sector not selected for erasure. This com-

mand is valid only during the sector erase operation,

including the 50 µs time-out period during the sector erase

command sequence. The Erase Suspend command is ig-

nored if written during the chip erase operation or Embedded

Program algorithm. Writing the Erase Suspend command

during the Sector Erase time-out immediately terminates the

time-out period and suspends the erase operation. Ad-

dresses are don’t-cares when writing the Erase Suspend

command.

START

Write Erase

Command Sequence

Data Poll

from System

When the Erase Suspend command is written during a sec-

tor erase operation, the device requires a maximum of 20 µs

to suspend the erase operation. However, when the Erase

Suspend command is written during the sector erase

time-out, the device immediately terminates the time-out pe-

riod and suspends the erase operation.

Embedded

Erase

algorithm

in progress

No

Data = FFh?

After the erase operation has been suspended, the system

can read array data from or program data to any sector not

selected for erasure. (The device erase suspends all sectors

selected for erasure.) Normal read and write timings and

command definitions apply. Reading at any address within

erase-suspended sectors produces status data on

DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 to-

gether, to determine if a sector is actively erasing or is

erase-suspended. See Write Operation Status‚ on page 19

for information on these status bits.

Yes

Erasure Completed

Notes:

1. See Table 5 on page 18 for erase command sequence.

2. See DQ3: Sector Erase Timer‚ on page 21 for more information.

Figure 4. Erase Operation

January 23, 2007 Am29SL400C_00_A6

Am29SL400C

17

D A T A S H E E T

Command Definitions

Table 5. Am29SL400C Command Definitions

Bus Cycles (Notes 2-5)

Command

Sequence

(Note 1)

First

Second

Third

Addr

Fourth

Fifth

Sixth

Addr Data Addr Data

Data Addr Data Addr Data Addr Data

Read (Note 6)

Reset (Note 7)

1

RA

XXX

555

RD

F0

Word

2AA

555

2AA

555

2AA

555

AAA

555

Manufacturer ID

4

AA

55

90

X00

01

Byte

Word

Byte

Word

Byte

AAA

555

X01

X02

X01

X02

70h

FIh

Device ID,

Top Boot Block

AAA

555

AAA

555

Device ID,

Bottom Boot Block

AAA

FIh

XX00

XX01

00

(SA)

X02

Word

Byte

555

2AA

555

Sector Protect Verify

(Note 9)

4

AA

55

90

(SA)

X04

AAA

01

Word

Byte

Word

Byte

555

AAA

555

2AA

555

2AA

555

PA

555

AAA

555

Program

Unlock Bypass

4

3

AA

55

A0

20

PA

PD

AAA

XXX

555

AAA

Unlock Bypass Program (Note 10)

Unlock Bypass Reset (Note 11)

2

A0

90

PD

00

XXX

2AA

555

2AA

555

Word

555

AAA

555

AAA

555

2AA

555

2AA

555

Chip Erase

6

AA

55

80

AA

55

10

30

Byte

Word

Byte

AAA

555

AAA

Sector Erase

SA

AAA

XXX

AAA

Erase Suspend (Note 12)

Erase Resume (Note 13)

1

B0

30

Legend:

X = Don’t care

PD = Data to be programmed at location PA. Data latches on the rising

edge of WE# or CE# pulse, whichever happens first.

RA = Address of the memory location to be read.

RD = Data read from location RA during read operation.

SA = Address of the sector to be verified (in autoselect mode) or

erased. Address bits A17–A12 uniquely select any sector.

PA = Address of the memory location to be programmed. Addresses

latch on the falling edge of the WE# or CE# pulse, whichever happens

later.

Notes:

8. The fourth cycle of the autoselect command sequence is a read

cycle.

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

9. The data is 00h for an unprotected sector and 01h for a protected

sector. See “Autoselect Command Sequence” for more

information.

3. Except when reading array or autoselect data, all bus cycles are

write operations.

10. The Unlock Bypass command is required prior to the Unlock

Bypass Program command.

4. Data bits DQ15–DQ8 are don’t cares for unlock and command

cycles.

11. The Unlock Bypass Reset command is required to return to

reading array data when the device is in the unlock bypass mode.

5. Address bits A17–A11 are don’t cares for unlock and command

cycles, unless SA or PA required.

12. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode.

The Erase Suspend command is valid only during a sector erase

operation.

6. No unlock or command cycles required when reading array data,

unless SA or PA required.

7. The Reset command is required to return to reading array data

when device is in the autoselect mode, or if DQ5 goes high (while

the device is providing status data).

13. The Erase Resume command is valid only during the Erase Suspend

mode.

18

Am29SL400C

Am29SL400C_00_A6 January 23, 2007

D A T A S H E E T

WRITE OPERATION STATUS

The device provides several bits to determine the status of a

write operation: DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#.

Table 6 on page 22 and the following subsections describe

the functions of these bits. DQ7, RY/BY#, and DQ6 each

offer a method for determining whether a program or erase

operation is complete or in progress. These three bits are

discussed first.

START

Read DQ7–DQ0

Addr = VA

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host system

whether an Embedded Algorithm is in progress or com-

pleted, or whether the device is in Erase Suspend. Data#

Polling is valid after the rising edge of the final WE# pulse in

the program or erase command sequence.

Yes

DQ7 = Data?

During the Embedded Program algorithm, the device out-

puts on DQ7 the complement of the datum programmed to

DQ7. This DQ7 status also applies to programming during

Erase Suspend. When the Embedded Program algorithm is

complete, the device outputs the datum programmed to

DQ7. The system must provide the program address to read

valid status information on DQ7. If a program address falls

within a protected sector, Data# Polling on DQ7 is active for

approximately 1 µs, then the device returns to reading array

data.

No

DQ5 = 1?

Yes

During the Embedded Erase algorithm, Data# Polling pro-

duces a 0 on DQ7. When the Embedded Erase algorithm is

complete, or if the device enters the Erase Suspend mode,

Data# Polling produces a 1 on DQ7. This is analogous to the

complement/true datum output described for the Embedded

Program algorithm: the erase function changes all the bits in

a sector to 1; prior to this, the device outputs the comple-

ment, or 0. The system must provide an address within any

of the sectors selected for erasure to read valid status infor-

mation on DQ7.

Read DQ7–DQ0

Addr = VA

Yes

DQ7 = Data?

No

After an erase command sequence is written, if all sectors

selected for erasing are protected, Data# Polling on DQ7 is

active for approximately 100 µs, then the device returns to

reading array data. If not all selected sectors are protected,

the Embedded Erase algorithm erases the unprotected sec-

tors, and ignores the selected sectors that are protected.

PASS

FAIL

Notes:

1. VA = Valid address for programming. During a sector erase

operation, a valid address is an address within any sector

selected for erasure. During chip erase, a valid address is any

non-protected sector address.

When the system detects DQ7 has changed from the com-

plement to true data, it can read valid data at DQ7–DQ0 on

the following read cycles. This is because DQ7 may change

asynchronously with DQ0–DQ6 while Output Enable (OE#)

is asserted low. Figure 19‚ on page 33 Data# Polling Timings

(During Embedded Algorithms), illustrates this.

2. DQ7 should be rechecked even if DQ5 = 1 because DQ7 may

change simultaneously with DQ5.

Figure 5. Data# Polling Algorithm

Table 6 on page 22 shows the outputs for Data# Polling on

DQ7. Figure 5 shows the Data# Polling algorithm.

RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output pin that indi-

cates whether an Embedded Algorithm is in progress or

complete. The RY/BY# status is valid after the rising edge of

the final WE# pulse in the command sequence. Since

RY/BY# is an open-drain output, several RY/BY# pins can be

tied together in parallel with a pull-up resistor to V_CC

.

January 23, 2007 Am29SL400C_00_A6

Am29SL400C

19

D A T A S H E E T

If the output is low (Busy), the device is actively erasing or

DQ2: Toggle Bit II

programming. (This includes programming in the Erase Sus-

pend mode.) If the output is high (Ready), the device is

ready to read array data (including during the Erase Sus-

pend mode), or is in the standby mode.

The “Toggle Bit II” on DQ2, when used with DQ6, indicates

whether a particular sector is actively erasing (that is, the

Embedded Erase algorithm is in progress), or whether that

sector is erase-suspended. Toggle Bit II is valid after the ris-

ing edge of the final WE# pulse in the command sequence.

The device toggles DQ2 with each OE# or CE# read cycle.

Table 6 on page 22 shows the outputs for RY/BY#.

Figure 14‚ on page 28, Figure 17‚ on page 31, and

Figure 18‚ on page 32 shows RY/BY# for reset, program,

and erase operations, respectively.

DQ2 toggles when the system reads at addresses within

those sectors that have been selected for erasure. But DQ2

cannot distinguish whether the sector is actively erasing or is

erase-suspended. DQ6, by comparison, indicates whether

the device is actively erasing, or is in Erase Suspend, but

cannot distinguish which sectors are selected for erasure.

Thus, both status bits are required for sector and mode infor-

mation. Refer to Table 6 on page 22 to compare outputs for

DQ2 and DQ6.

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded Pro-

gram or Erase algorithm is in progress or complete, or

whether the device has entered the Erase Suspend mode.

Toggle Bit I may be read at any address, and is valid after the

rising edge of the final WE# pulse in the command sequence

(prior to the program or erase operation), and during the sec-

tor erase time-out.

Figure 6‚ on page 21 shows the toggle bit algorithm in flow-

chart form, and the section DQ2: Toggle Bit II‚ on page 20

explains the algorithm. See also the DQ6: Toggle Bit I sub-

section. Figure 20‚ on page 33 shows the toggle bit timing di-

agram. Figure 21‚ on page 34 shows the differences

between DQ2 and DQ6 in graphical form.

During an Embedded Program or Erase algorithm operation,

successive read cycles to any address cause DQ6 to toggle

(The system may use either OE# or CE# to control the read

cycles). When the operation is complete, DQ6 stops tog-

gling.

Reading Toggle Bits DQ6/DQ2

After an erase command sequence is written, if all sectors

selected for erasing are protected, DQ6 toggles for approxi-

mately 100 µs, then returns to reading array data. If not all

selected sectors are protected, the Embedded Erase algo-

rithm erases the unprotected sectors, and ignores the se-

lected sectors that are protected.

Refer to Figure 6‚ on page 21 for the following discussion.

Whenever the system initially begins reading toggle bit sta-

tus, it must read DQ7–DQ0 at least twice in a row to deter-

mine whether a toggle bit is toggling. Typically, the system

would note and store the value of the toggle bit after the first

read. After the second read, the system would compare the

new value of the toggle bit with the first. If the toggle bit is not

toggling, the device has completed the program or erase op-

eration. The system can read array data on DQ7–DQ0 on

the following read cycle.

The system can use DQ6 and DQ2 together to determine

whether a sector is actively erasing or is erase-suspended.

When the device is actively erasing (that is, the Embedded

Erase algorithm is in progress), DQ6 toggles. When the de-

vice enters the Erase Suspend mode, DQ6 stops toggling.

However, the system must also use DQ2 to determine which

sectors are erasing or erase-suspended. Alternatively, the

system can use DQ7 (see the subsection on DQ7: Data#

Polling‚ on page 19).

However, if after the initial two read cycles, the system deter-

mines that the toggle bit is still toggling, the system also

should note whether the value of DQ5 is high (see the sec-

tion on DQ5). If it is, the system should then determine again

whether the toggle bit is toggling, since the toggle bit may

have stopped toggling just as DQ5 went high. If the toggle bit

is no longer toggling, the device has successfully completed

the program or erase operation. If it is still toggling, the de-

vice did not completed the operation successfully, and the

system must write the reset command to return to reading

array data.

If a program address falls within a protected sector, DQ6 tog-

gles for approximately 1 µs after the program command se-

quence is written, then returns to reading array data.

DQ6 also toggles during the erase-suspend-program mode,

and stops toggling once the Embedded Program algorithm is

complete.

Table 6 on page 22 shows the outputs for Toggle Bit I on

DQ6. Figure 6‚ on page 21 shows the toggle bit algorithm.

Figure 20‚ on page 33 shows the toggle bit timing diagrams.

Figure 21 shows the differences between DQ2 and DQ6 in

graphical form. See also the subsection on DQ2: Toggle Bit

II‚ on page 20.

The remaining scenario is that the system initially deter-

mines that the toggle bit is toggling and DQ5 has not gone

high. The system may continue to monitor the toggle bit and

DQ5 through successive read cycles, determining the status

as described in the previous paragraph. Alternatively, it may

choose to perform other system tasks. In this case, the sys-

tem must start at the beginning of the algorithm when it re-

turns to determine the status of the operation (top of

Figure 6‚ on page 21).

20

Am29SL400C

Am29SL400C_00_A6 January 23, 2007

D A T A S H E E T

DQ5: Exceeded Timing Limits

START

DQ5 indicates whether the program or erase time has ex-

ceeded a specified internal pulse count limit. Under these

conditions DQ5 produces a 1. This is a failure condition that

indicates the program or erase cycle was not successfully

completed.

Read DQ7–DQ0

The DQ5 failure condition may appear if the system tries to

program a 1 to a location that is previously programmed to

“0.” Only an erase operation can change a 0 back to a 1.

Under this condition, the device halts the operation, and

when the operation has exceeded the timing limits, DQ5 pro-

duces a 1.

(Note 1)

Read DQ7–DQ0

Under both these conditions, the system must issue the

reset command to return the device to reading array data.

No

Toggle Bit

= Toggle?

DQ3: Sector Erase Timer

Yes

After writing a sector erase command sequence, the system

may read DQ3 to determine whether or not an erase opera-

tion has begun. (The sector erase timer does not apply to

the chip erase command.) If additional sectors are selected

for erasure, the entire time-out also applies after each addi-

tional sector erase command. When the time-out is com-

plete, DQ3 switches from 0 to 1. If the time between

additional sector erase commands from the system can be

assumed to be less than 50 µs, the system need not monitor

DQ3. See also Sector Erase Command Sequence‚ on

page 16.

No

DQ5 = 1?

Yes

(Notes

1, 2)

Read DQ7–DQ0

Twice

After the sector erase command sequence is written, the

system should read the status on DQ7 (Data# Polling) or

DQ6 (Toggle Bit I) to ensure the device has accepted the

command sequence, and then read DQ3. If DQ3 is 1, the in-

ternally controlled erase cycle has begun; all further com-

mands (other than Erase Suspend) are ignored until the

erase operation is complete. If DQ3 is 1, the device will ac-

cept additional sector erase commands. To ensure the com-

mand has been accepted, the system software should check

the status of DQ3 prior to and following each subsequent

sector erase command. If DQ3 is high on the second status

check, the last command might not have been accepted.

Table 6 on page 22 shows the outputs for DQ3.

Toggle Bit

= Toggle?

No

Yes

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Notes:

1. Read toggle bit twice to determine whether or not it is toggling.

See text.

2. Recheck toggle bit because it may stop toggling as DQ5

changes to 1. See text.

Figure 6. Toggle Bit Algorithm

January 23, 2007 Am29SL400C_00_A6

Am29SL400C

21

D A T A S H E E T

Table 6. Write Operation Status

DQ7

DQ5

DQ2

Operation

(Note 2)

DQ6

(Note 1)

DQ3

N/A

1

(Note 2)

RY/BY#

Embedded Program Algorithm

Embedded Erase Algorithm

DQ7#

0

Toggle

0

No toggle

Toggle

0

Standard

Mode

Reading within Erase

Suspended Sector

1

No toggle

0

N/A

Toggle

1

Erase

Suspend

Mode

Reading within Non-Erase

Suspended Sector

Data

0

Data

N/A

Data

N/A

1

0

Erase-Suspend-Program

DQ7#

Toggle

Notes:

1. DQ5 switches to 1 when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See DQ5:

Exceeded Timing Limits‚ on page 21 for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

22

Am29SL400C

Am29SL400C_00_A6 January 23, 2007

D A T A S H E E T

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . . . . . . –65°C to +150°C

20 ns

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . . . . . . –65°C to +125°C

0.0 V

Voltage with Respect to Ground

–0.5 V

–2.0 V

V_CC(Note 1) . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +2.5 V

A9, OE#,

and RESET# (Note 2) . . . . . . . . . . . . . . . .–0.5 V to +11.0 V

20 ns

All other pins (Note 1) . . . . . . . . . . . . . –0.5 V to V_CC+0.5 V

Output Short Circuit Current (Note 3) . . . . . . . . . . . 100 mA

Figure 7. Maximum Negative Overshoot Waveform

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage

transitions, input or I/O pins may overshoot V_SSto –2.0 V for

periods of up to 20 ns. See Figure 7. Maximum DC voltage on

input or I/O pins is V_CC+0.5 V. During voltage transitions, input

or I/O pins may overshoot to V_CC+2.0 V for periods up to 20 ns.

See Figure 8.

20 ns

2. Minimum DC input voltage on pins A9, OE#, and RESET# is –0.5

V. During voltage transitions, A9, OE#, and RESET# may

overshoot V_SSto –2.0 V for periods of up to 20 ns. See.

Maximum DC input voltage on pin A9 is +11.0 V which may

overshoot to 12.5 V for periods up to 20 ns.

V_CC

+2.0 V

V_CC

+0.5 V

3. No more than one output may be shorted to ground at a time.

Duration of the short circuit should not be greater than one

second.

2.0 V

20 ns

Stresses above those listed under “Absolute Maximum Ratings” may

cause permanent damage to the device. This is a stress rating only;

functional operation of the device at these or any other conditions

above those indicated in the operational sections of this data sheet is

not implied. Exposure of the device to absolute maximum rating

conditions for extended periods may affect device reliability.

Figure 8. Maximum Positive Overshoot Waveform

V

Supply Voltages

CC

OPERATING RANGES

Commercial (C) Devices

V_CCfor full voltage range . . . . . . . . . . . . . +1.65 V to +2.2 V

V_CCfor regulated voltage range. . . . . . . . +1.70 V to +2.2 V

Ambient Temperature (T_A) . . . . . . . . . . . . . . . . 0°C to +70°C

Industrial (I) Devices

Note: Operating ranges define those limits between which the func-

tionality of the device is guaranteed.

Ambient Temperature (T_A) . . . . . . . . . . . . . . –40°C to +85°C

January 23, 2007 Am29SL400C_00_A6

Am29SL400C

23

D A T A S H E E T

DC CHARACTERISTICS

CMOS Compatible

Parameter

Description

Test Conditions

Min

Typ

Max

±1.0

35

Unit

µA

V

_IN= V_SSto V_CC

,

I_LI

Input Load Current

_CC= V_{CC max}

I_LIT

I_LO

A9 Input Load Current

Output Leakage Current

V_CC= V_{CC max}; A9 = 11.0 V

µA

V

_OUT= V_SSto V_CC

,

±1.0

µA

_CC= V_{CC max}

5 MHz

1 MHz

5 MHz

1 MHz

5

1

5

1

10

3

CE# = V_IL,OE# ₌V_IH,

Byte Mode

V_CCActive Read Current

(Notes 1, 2)

I_CC1

mA

10

3

CE# = V_IL,OE# ₌V_IH,

Word Mode

V_CCActive Write Current

(Notes 2, 3, 5)

I_CC2

CE# = V_IL,OE# ₌V_IH

20

25

I_CC3

I_CC4

V_CCStandby Current (Note 2)

V_CCReset Current (Note 2)

CE#, RESET# = V_CC± 0.2 V

RESET# = V_SS± 0.2 V

V_IH= V_CC± 0.2 V;

1

5

µA

Automatic Sleep Mode

(Notes 2, 3)

I_CC5

1

5

µA

V

_IL= V_SS± 0.2 V

V_IL

V_IH

Input Low Voltage

Input High Voltage

–0.5

0.2 x V_CC

V_CC+ 0.3

V

0.8 x V_CC

Voltage for Autoselect and

Temporary Sector Unprotect

V_ID

V

_CC= 2.0 V

9.0

11.0

V

V_OL1

V_OL2

V_OH1

V_OH2

I

_OL= 2.0 mA, V_CC= V_{CC min}

0.25

0.1

V

Output Low Voltage

Output High Voltage

I_OL= 100 μA, V_CC= V_{CC min}

I_OH= –2.0 mA, V_CC= V_{CC min}

I_OH= –100 μA, V_CC= V_{CC min}

0.7 x V_CC

V_CC–0.1

Low V_CCLock-Out Voltage

(Note 4)

V_LKO

1.2

1.5

V

Notes:

1. The I_CCcurrent listed is typically less than 1 mA/MHz, with OE# at V_IH. Typical V_CCis 2.0 V.

2. The maximum I_CCspecifications are tested with V_CC= V_CCmax.

3. I_CCactive while Embedded Erase or Embedded Program is in progress.

4. Automatic sleep mode enables the low power mode when addresses remain stable for t_ACC+ 50 ns.

5. Not 100% tested.

24

Am29SL400C

Am29SL400C_00_A6 January 23, 2007

D A T A S H E E T

DC CHARACTERISTICS (Continued)

Zero Power Flash

20

15

10

5

0

500

1000

1500

2000

2500

3000

3500

4000

Time in ns

Note: Addresses are switching at 1 MHz

Figure 9. I_CC1Current vs. Time (Showing Active and Automatic Sleep Currents)

10

8

6

2.2 V

4

1.8 V

2

0

1

2

3

4

5

Frequency in MHz

Note: T = 25 °C

Figure 10. Typical I_CC1vs. Frequency

January 23, 2007 Am29SL400C_00_A6

Am29SL400C

25

D A T A S H E E T

TEST CONDITIONS

Table 7. Test Specifications

Test Condition

All Speed Options

Unit

Output Load Capacitance, C_L

30

pF

(including jig capacitance)

Input Rise and Fall Times

Input Pulse Levels

Device

Under

Test

5

ns

V

0.0–2.0

C

L

Input timing measurement

reference levels

1.0

V

Output timing measurement

reference levels

Figure 11. Test Setup

Key to Switching Waveforms

WAVEFORM

INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Center Line is High Impedance State (High Z)

2.0 V

0.0 V

1.0 V

Input

Measurement Level

Output

Figure 12. Input Waveforms

and Measurement Levels

26

Am29SL400C

Am29SL400C_00_A6 January 23, 2007

D A T A S H E E T

AC CHARACTERISTICS

Read Operations

Parameter

Speed Options

JEDEC

Std.

Description

Read Cycle Time (Note 1)

Test Setup

-100R

-110

-120

-150

Unit

t_AVAV

t_RC

Min

100

110

120

150

ns

CE# = V_IL

OE# = V_IL

t_AVQV

t_ACC

Address to Output Delay

Max

100

110

120

150

ns

t_ELQV

t_GLQV

t_EHQZ

t_GHQZ

t_CE

t_OE

t_DF

Chip Enable to Output Delay

OE# = V_IL

Max

Min

100

35

110

45

120

50

150

65

ns

Output Enable to Output Delay

Chip Enable to Output High Z (Note 1)

Output Enable to Output High Z (Note 1)

16

0

Read

Output Enable

t_OEH

Toggle and

Data# Polling

Hold Time (Note 1)

Min

30

0

ns

Output Hold Time From Addresses, CE# or OE#,

Whichever Occurs First (Note 1)

t_AXQX

t_OH

Notes:

1. Not 100% tested.

2. See Figure 11‚ on page 26 and Table 7 on page 26 for test specifications.

t_RC

Addresses Stable

t_ACC

Addresses

CE#

t_DF

t_OE

OE#

t_OEH

WE#

t_CE

t_OH

HIGH Z

Output Valid

Outputs

RESET#

RY/BY#

0 V

Figure 13. Read Operations Timings

January 23, 2007 Am29SL400C_00_A6

Am29SL400C

27

D A T A S H E E T

AC CHARACTERISTICS

Hardware Reset (RESET#)

Parameter

JEDEC

Std

Description

Test Setup

All Speed Options

Unit

RESET# Pin Low (During Embedded Algorithms) to

Read or Write (See Note)

t_READY

Max

20

µs

RESET# Pin Low (NOT During Embedded

Algorithms) to Read or Write (See Note)

t_READY

500

ns

t_RP

t_RH

t_RPD

t_RB

RESET# Pulse Width

Min

500

200

20

ns

µs

ns

RESET# High Time Before Read (See Note)

RESET# Low to Standby Mode

RY/BY# Recovery Time

0

Note: Not 100% tested.

RY/BY#

CE#, OE#

RESET#

t_RH

t_RP

t_Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

t_Ready

RY/BY#

t_RB

CE#, OE#

RESET#

t_RP

Figure 14. RESET# Timings

28

Am29SL400C

Am29SL400C_00_A6 January 23, 2007

D A T A S H E E T

AC CHARACTERISTICS

Word/Byte Configuration (BYTE#)

Parameter

Speed Options

JEDEC

Std

Description

-100R

-110

-120

-150

Unit

ns

t

_ELFL/t_ELFH

CE# to BYTE# Switching Low or High

BYTE# Switching Low to Output HIGH Z

BYTE# Switching High to Output Active

Max

Min

10

t_FLQZ

t_FHQV

50

55

60

ns

100

110

120

150

ns

CE#

OE#

BYTE#

t_ELFL

Data Output

(DQ0–DQ14)

Data Output

(DQ0–DQ7)

BYTE#

DQ0–DQ14

Switching

from word

to byte

mode

Address

Input

DQ15

Output

DQ15/A-1

t_FLQZ

t_ELFH

BYTE#

Switching

from byte to

word mode

Data Output

(DQ0–DQ7)

Data Output

(DQ0–DQ14)

DQ0–DQ14

DQ15/A-1

Address

Input

DQ15

Output

t_FHQV

Figure 15. BYTE# Timings for Read Operations

CE#

The falling edge of the last WE# signal

WE#

BYTE#

t_SET

(t_AS

)

t_HOLD(t_AH

)

Note: Refer to the Erase/Program Operations table for t_ASand t_AHspecifications.

Figure 16. BYTE# Timings for Write Operations

Am29SL400C

January 23, 2007 Am29SL400C_00_A6

29

D A T A S H E E T

AC CHARACTERISTICS

Erase/Program Operations

Parameter

Speed Options

JEDEC

t_AVAV

Std

t_WC

t_AS

Description

Write Cycle Time (Note 1)

-100R

-110

-120

-150

Unit

ns

Min

100

110

120

150

t_AVWL

t_WLAX

t_DVWH

t_WHDX

Address Setup Time

Address Hold Time

Data Setup Time

0

ns

t_AH

50

55

60

70

ns

t_DS

ns

t_DH

t_OES

Data Hold Time

0

ns

Output Enable Setup Time

ns

Read Recovery Time Before Write

(OE# High to WE# Low)

t_GHWL

Min

0

ns

t_ELWL

t_WHEH

t_WLWH

t_WHWL

t_CS

t_CH

CE# Setup Time

Min

Typ

Min

Max

0

ns

CE# Hold Time

t_WP

Write Pulse Width

Write Pulse Width High

50

55

60

70

t_WPH

30

10

12

2

Byte

t_WHWH1

t_WHWH1Programming Operation (Notes 1, 2)

t_WHWH2Sector Erase Operation (Notes 1, 2)

µs

Word

t_WHWH2

sec

µs

t_VCS

t_RB

V_CCSetup Time

50

0

Recovery Time from RY/BY#

Program/Erase Valid to RY/BY# Delay

ns

t_BUSY

200

ns

Notes:

1. Not 100% tested.

2. See the Erase and Programming Performance‚ on page 38 section for more information.

30

Am29SL400C

Am29SL400C_00_A6 January 23, 2007

D A T A S H E E T

AC CHARACTERISTICS

Program Command Sequence (last two cycles)

Read Status Data (last two cycles)

t_AS

PA

t_WC

Addresses

555h

PA

t_AH

CE#

OE#

t_CH

t_WHWH1

t_WP

WE#

Data

t_WPH

t_CS

t_DS

t_DH

PD

D_OUT

A0h

Status

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. PA = program address, PD = program data, D_OUTis the true data at the program address.

2. Illustration shows device in word mode.

Figure 17. Program Operation Timings

January 23, 2007 Am29SL400C_00_A6

Am29SL400C

31

D A T A S H E E T

AC CHARACTERISTICS

Erase Command Sequence (last two cycles)

Read Status Data

VA

t_AS

SA

t_WC

VA

Addresses

CE#

2AAh

555h for chip erase

t_AH

t_CH

OE#

t_WP

WE#

t_WPH

t_WHWH2

t_CS

t_DS

t_DH

In

Data

Complete

55h

30h

Progress

10 for Chip Erase

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation Status‚ on page 19.

2. Illustration shows device in word mode.

Figure 18. Chip/Sector Erase Operation Timings

32

Am29SL400C

Am29SL400C_00_A6 January 23, 2007

D A T A S H E E T

AC CHARACTERISTICS

t_RC

Addresses

VA

t_ACC

t_CE

VA

CE#

t_CH

t_OE

OE#

WE#

t_OEH

t_DF

t_OH

High Z

DQ7

Valid Data

Complement

Status Data

True

DQ0–DQ6

Valid Data

Status Data

True

t_BUSY

RY/BY#

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.

Figure 19. Data# Polling Timings

(During Embedded Algorithms)

t_RC

Addresses

CE#

VA

t_ACC

t_CE

VA

t_CH

t_OE

OE#

WE#

t_OEH

t_DF

t_OH

High Z

DQ6/DQ2

RY/BY#

Valid Status

(first read)

Valid Status

Valid Data

(second read)

(stops toggling)

t_BUSY

Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and

array data read cycle.

Figure 20. Toggle Bit Timings

(During Embedded Algorithms)

January 23, 2007 Am29SL400C_00_A6

Am29SL400C

33

D A T A S H E E T

AC CHARACTERISTICS

Enter

Erase

Enter Erase

Suspend Program

Embedded

Erase

Resume

Suspend

Erasing

Erase

Erase Suspend

Read

Erase

Suspend

Program

Erase

Complete

WE#

Erase

Erase Suspend

Read

DQ6

DQ2

Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an erase-suspended sector.

Figure 21. DQ2 vs. DQ6

Temporary Sector Unprotect

Parameter

JEDEC

Std

Description

V_IDRise and Fall Time

All Speed Options

Unit

t_VIDR

Min

500

ns

RESET# Setup Time for Temporary Sector

Unprotect

t_RSP

4

µs

10 V

RESET#

0 or 1.8 V

t_VIDR

0 or 1.8 V

t_VIDR

Program or Erase Command Sequence

CE#

WE#

t_RSP

RY/BY#

Figure 22. Temporary Sector Unprotect

Timing Diagram

34

Am29SL400C

Am29SL400C_00_A6 January 23, 2007

D A T A S H E E T

AC CHARACTERISTICS

V_ID

V_IH

RESET#

SA, A6,

A1, A0

Valid*

Sector Protect/Unprotect

60h 60h

Valid*

Status

Verify

40h

Data

Sector Protect: 150 µs

Sector Unprotect: 15 ms

1 µs

CE#

WE#

OE#

* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.

Figure 23. Sector Protect/Unprotect Timing Diagram

January 23, 2007 Am29SL400C_00_A6

Am29SL400C

35

D A T A S H E E T

AC CHARACTERISTICS

Alternate CE# Controlled Erase/Program Operations

Parameter

Speed Options

Description

JEDEC

t_AVAV

Std

t_WC

t_AS

-100R

-110

-120

-150

Unit

ns

Write Cycle Time (Note 1)

Address Setup Time

Address Hold Time

Data Setup Time

Min

100

110

120

150

t_AVEL

0

ns

t_ELAX

t_DVEH

t_EHDX

t_AH

50

55

60

70

ns

t_DS

ns

t_DH

t_OES

Data Hold Time

0

ns

Output Enable Setup Time

ns

Read Recovery Time Before Write

(OE# High to WE# Low)

t_GHEL

Min

0

ns

t_WLEL

t_EHWH

t_ELEH

t_EHEL

t_WS

t_WH

t_CP

WE# Setup Time

WE# Hold Time

Min

Typ

0

ns

CE# Pulse Width

CE# Pulse Width High

50

55

60

70

t_CPH

30

10

12

2

Byte

Programming Operation

(Notes 1, 2)

t_WHWH1

µs

Word

t_WHWH2

Notes:

t_WHWH2Sector Erase Operation (Notes 1, 2)

sec

1. Not 100% tested.

2. See the Erase and Programming Performance‚ on page 38 sec-

tion for more information.

36

Am29SL400C

Am29SL400C_00_A6 January 23, 2007

D A T A S H E E T

AC CHARACTERISTICS

555 for program

2AA for erase

PA for program

SA for sector erase

555 for chip erase

Data# Polling

Addresses

PA

t_WC

t_AS

t_AH

t_WH

WE#

t_GHEL

OE#

t_{WHWH1 or 2}

t_CP

CE#

t_WS

t_CPH

t_DS

t_BUSY

t_DH

DQ7#

D_OUT

Data

t_RH

A0 for program

55 for erase

PD for program

30 for sector erase

10 for chip erase

RESET#

RY/BY#

Notes:

1. PA = program address, PD = program data, DQ7# = complement of the data written, D_OUT= data written

2. Figure indicates the last two bus cycles of command sequence.

3. Word mode address used as an example.

Figure 24. Alternate CE# Controlled

Write Operation Timings

January 23, 2007 Am29SL400C_00_A6

Am29SL400C

37

D A T A S H E E T

ERASE AND PROGRAMMING PERFORMANCE

Parameter

Typ (Note 1)

Max (Note 2)

Unit

s

Comments

Sector Erase Time

Chip Erase Time

2

38

10

12

5

15

Excludes 00h programming prior to

erasure (Note 4)

s

Byte Programming Time

Word Programming Time

300

360

40

µs

s

Excludes system level overhead

(Note 5)

Byte Mode

Word Mode

Chip Programming Time

(Note 3)

3.5

30

s

Notes:

1. Typical program and erase times assume the following conditions: 25°C, 2.0 V V , 1,000,000 cycles. Additionally, programming typicals assume

CC

checkerboard pattern.

2. Under worst case conditions of 90°C, V_CC= 1.8 V, 1,000,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than

the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 5 on page 18

for further information on command definitions.

6. The device has a minimum guaranteed erase and program cycle endurance of 1,000,000 cycles.

38

Am29SL400C

Am29SL400C_00_A6 January 23, 2007

D A T A S H E E T

LATCHUP CHARACTERISTICS

Description

Min

Max

Input voltage with respect to V_SSon all pins except I/O pins

(including A9, OE#, and RESET#)

–1.0 V

11.0 V

Input voltage with respect to V_SSon all I/O pins

–0.5 V

V_CC+ 0.5 V

+100 mA

V

_CCCurrent

–100 mA

Includes all pins except V_CC. Test conditions: V_CC= 1.8 V, one pin at a time.

TSOP PIN AND BGA PACKAGE CAPACITANCE

Parameter Symbol

Parameter Description

Test Setup

Typ

6

Max

7.5

5.0

12

Unit

pF

TSOP

C_IN

Input Capacitance

V_IN= 0

V_OUT= 0

V_IN= 0

Fine-pitch BGA

TSOP

4.2

8.5

5.4

7.5

3.9

C_OUT

Output Capacitance

Fine-pitch BGA

TSOP

6.5

9

C_IN2

Control Pin Capacitance

Fine-pitch BGA

4.7

Notes:

1. Sampled, not 100% tested.

2. Test conditions T_A= 25°C, f = 1.0 MHz.

DATA RETENTION

Parameter

Test Conditions

Min

10

Unit

Years

150°C

125°C

Minimum Pattern Data Retention Time

20

January 23, 2007 Am29SL400C_00_A6

Am29SL400C

39

D A T A S H E E T

PHYSICAL DIMENSIONS

TS048—48-Pin Standard TSOP

Dwg rev AA; 10/99

40

Am29SL400C

Am29SL400C_00_A6 January 23, 2007

D A T A S H E E T

PHYSICAL DIMENSIONS

FBA048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 6 x 8 mm Package

Dwg rev AF; 10/99

January 23, 2007 Am29SL400C_00_A6

Am29SL400C

41

D A T A S H E E T

REVISION SUMMARY

Distinctive Characteristics

Revision A (August 14, 2002)

Initial Release.

Updated Automatic Sleep Mode and standby mode current

values.

Revision A+1 (August 28, 2002)

Sector Protection/Unprotection

Pin Configuration

Updated V_CClow-end value.

Ordering Information

Changed beginning of second paragraph from, “The primary

method....” to read, “Sector protection/unprotection.”

Deleted third paragraph.

Changed WB package type to WA.

DC Characteristics, CMOS Compatible

FBB048—48-Ball Fine-Pitch Ball Grid Array (FBGA)

6 x 8 mm package

Updated V_CCStandby and Reset currents Typ values, and

Automatic Sleep Mode Typ value.

Changed number in row D in table from 9.00 mm to 8.0 mm.

Revision A+2 (February 5, 2003)

Global

Revision A+4 (March 18, 2003)

Ordering Information, Valid Combinations

Removed dashes from Order Numbers.

Changed fastest speed option from 103 ns to 100 ns, regu-

lated voltage, added 110 ns speed option standard voltage.

Revision A+5 (March 3, 2005)

General Description

Ordering Information

Changed first sentenced to indicate 48-pin TSOP package

option.

Added Commercial and Industrial Pb-free Package tempera-

tures.

Command Definitions, Table 5

Valid Combinations for TSOP package

Added two package codes.

Removed TBD markers from device ID, Top Boot Block to

70h.

Removed TBD markers from device ID, Bottom Boot Block to

FIh.

Valid Combination for FBGA package

Added two package codes.

Changed address bits A18–A11 to A17–A11.

Physical Dimensions, 48-pin TSOP

Global

Added Colophon. Updated Trademark information.

Changed from Reverse to Standard TSOP package.

Revision A6 (January 23, 2007)

AC Characteristics

Revision A+3 (February 26, 2003)

Global

Erase and Program Operations table: Changed t_BUSYto a

maximum specification.

Added 110 ns speed option.

Colophon

The products described in this document are designed, developed and manufactured as contemplated for general use, including without limita-

tion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as con-

templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the

public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,

aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for

any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion Inc. will not be liable

to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor

devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design

measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating

conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign

Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au-

thorization by the respective government entity will be required for export of those products.

Trademarks

marks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are

for identification purposes only and may be trademarks of their respective companies.

thereof are trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners.

42

Am29SL400C

Am29SL400C_00_A6 January 23, 2007


型号：	AM29SL400CT120WAC
厂家：	AMD
描述：	4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 1.8 Volt-only Super Low Voltage Flash Memory 4兆位（ 512K的×8位/ 256千×16位） CMOS 1.8伏只超低电压闪存闪存内存集成电路
文件：	总44页 (文件大小：850K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AM29SL400CT120WAC [AMD]

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