AM29SL800CB100ECB
更新时间:2024-09-18 02:12:56
品牌:AMD
描述:8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 1.8 Volt-only Super Low Voltage Flash Memory
AM29SL800CB100ECB 概述
8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 1.8 Volt-only Super Low Voltage Flash Memory 8兆位( 1一M× 8位/ 512的K× 16位) CMOS 1.8伏只超低电压闪存
AM29SL800CB100ECB 数据手册
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Am29SL800C
8 Megabit (1 M x 8-Bit/512 K x 16-Bit)
CMOS 1.8 Volt-only Super Low Voltage Flash Memory
DISTINCTIVE CHARACTERISTICS
■ Single power supply operation
■ Top or bottom boot block configurations
available
— 1.8 to 2.2 V for read, program, and erase
operations
■ Embedded Algorithms
— Ideal for battery-powered applications
■ Manufactured on 0.32 µm process technology
— Compatible with 0.35 µm Am29SL800B device
■ High performance
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
— Access times as fast as 100 ns
■ Minimum 1,000,000 write cycle guarantee per
■ Ultra low power consumption (typical values at
sector
5 MHz)
■ Package option
— 48-pin TSOP
— 48-ball FBGA
— 65 nA Automatic Sleep Mode current
— 65 nA standby mode current
— 5 mA read current
— 10 mA program/erase current
■ Compatibility with JEDEC standards
— Pinout and software compatible with single-
power supply Flash
■ Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
fifteen 64 Kbyte sectors (byte mode)
— Superior inadvertent write protection
— One 8 Kword, two 4 Kword, one 16 Kword, and
fifteen 32 Kword sectors (word mode)
■ Data# Polling and toggle bits
— Provides a software method of detecting
program or erase operation completion
— Supports full chip erase
— Sector Protection features:
■ Ready/Busy# pin (RY/BY#)
A hardware method of locking a sector to
prevent any program or erase operations within
that sector
— Provides a hardware method of detecting
program or erase cycle completion
■ Erase Suspend/Erase Resume
Sectors can be locked in-system or via
programming equipment
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
■ Hardware reset pin (RESET#)
■ Unlock Bypass Program Command
— Hardware method to reset the device to reading
array data
— Reduces overall programming time when
issuing multiple program command sequences
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Publication# 22230 Rev: A Amendment/0
Issue Date: August 1998
Refer to AMD’s Website (www.amd.com) for the latest information.
P R E L I M I N A R Y
GENERAL DESCRIPTION
The Am29SL800C is an 8 Mbit, 1.8 V volt-only Flash
memory organized as 1,048,576 bytes or 524,288
words. The device is offered in 48-pin TSOP and 48-
ball FBGA packages. The word-wide data (x16)
appears on DQ15–DQ0; the byte-wide (x8) data
appears on DQ7–DQ0. This device is designed to be
programmed and erased in-system with a single 1.8
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data
or accept another command.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
volt V supply. No V is for write or erase operations.
CC
PP
The device can also be programmed in standard
EPROM programmers.
The standard device offers access times of 100, 120,
and 150 ns, allowing high speed microprocessors to
operate without wait states. To eliminate bus contention
the device has separate chip enable (CE#), write
enable (WE#) and output enable (OE#) controls.
Hardware data protection measures include a low
V
detector that automatically inhibits write opera-
CC
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved in-system or via program-
ming equipment.
The device requires only a single 1.8 volt power sup-
ply for both read and write functions. Internally gener-
ated and regulated voltages are provided for the
program and erase operations.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Com-
mands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When ad-
dresses have been stable for a specified amount of
time, the device enters the automatic sleep mode.
The system can also place the device into the standby
mode. Power consumption is greatly reduced in both
these modes.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin. The Unlock Bypass mode facili-
tates faster programming times by requiring only two
write cycles to program data instead of four.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within
a sector simultaneously via Fowler-Nordheim tun-
neling. The data is programmed using hot electron
injection.
Device erasure occurs by executing the erase command
sequence. This initiates the Embedded Erase algo-
rithm—an internal algorithm that automatically prepro-
grams the array (if it is not already programmed) before
executing the erase operation. During erase, the device
automatically times the erase pulse widths and verifies
proper cell margin.
2
Am29SL800C
P R E L I M I N A R Y
PRODUCT SELECTOR GUIDE
Family Part Number
Speed Options
Am29SL800C
100
100
100
35
120
120
120
50
150
150
150
65
Max access time, ns (t
)
ACC
Max CE# access time, ns (t
)
CE
Max OE# access time, ns (t
)
OE
Note: See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
DQ0–DQ15 (A-1)
RY/BY#
V
CC
Sector Switches
V
SS
Erase Voltage
Generator
Input/Output
Buffers
RESET#
State
Control
WE#
BYTE#
Command
Register
PGM Voltage
Generator
Data
Latch
Chip Enable
Output Enable
Logic
STB
CE#
OE#
Y-Decoder
Y-Gating
STB
V
Detector
Timer
CC
Cell Matrix
X-Decoder
A0–A18
22230A-1
Am29SL800C
3
P R E L I M I N A R Y
CONNECTION DIAGRAMS
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DQ12
DQ4
VCC
WE#
RESET#
NC
Standard TSOP
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
NC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
WE#
RESET#
NC
Reverse TSOP
NC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
OE#
VSS
CE#
A0
22230A-2
4
Am29SL800C
P R E L I M I N A R Y
CONNECTION DIAGRAMS
48-Ball FBGA (Bottom View)
A1
A3
B1
C1
A2
D1
A1
E1
A0
F1
G1
H1
A4
CE#
OE#
VSS
A2
A7
B2
C2
A6
D2
A5
E2
F2
G2
H2
A17
DQ0
DQ8
DQ9
DQ1
A3
B3
C3
D3
E3
F3
G3
H3
RY/BY#
NC
A18
NC
DQ2
DQ10
DQ11
DQ3
A4
B4
C4
D4
E4
F4
G4
H4
WE# RESET#
NC
NC
DQ5
DQ12
VCC
DQ4
A5
A9
B5
A8
C5
D5
E5
F5
G5
H5
A10
A11
DQ7
DQ14
DQ13
DQ6
A6
B6
C6
D6
E6
F6
G6
H6
A13
A12
A14
A15
A16
BYTE# DQ15/A-1 VSS
22230A-3
Flash memory devices in FBGA packages may be
damaged if exposed to ultrasonic cleaning methods.
The package and/or data integrity may be compromised
if the package body is exposed to temperatures above
150°C for prolonged periods of time.
Special Handling Instructions for FBGA
Packages
Special handling is required for Flash Memory products
in FBGA packages.
Am29SL800C
5
P R E L I M I N A R Y
PIN CONFIGURATION
LOGIC SYMBOL
A0–A18
= 19 addresses
19
DQ0–DQ14 = 15 data inputs/outputs
A0–A18
16 or 8
DQ15/A-1
=
DQ15 (data input/output, word mode),
A-1 (LSB address input, byte mode)
DQ0–DQ15
(A-1)
BYTE#
CE#
=
=
=
=
=
=
=
=
=
Selects 8-bit or 16-bit mode
Chip enable
CE#
OE#
OE#
Output enable
WE#
WE#
Write enable
RESET#
BYTE#
RESET#
RY/BY#
Hardware reset pin, active low
Ready/Busy# output
1.8–2.2 V single power supply
Device ground
RY/BY#
V
V
CC
SS
22230A-4
NC
Pin not connected internally
6
Am29SL800C
P R E L I M I N A R Y
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combi-
nation) is formed by a combination of the elements below.
Am29SL800C
T
100
E
C
OPTIONAL PROCESSING
Blank = Standard Processing
B = Burn-in
(Contact an AMD representative for more information)
TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
PACKAGE TYPE
E
=
48-Pin Thin Small Outline Package (TSOP)
Standard Pinout (TS 048)
F
=
48-Pin Thin Small Outline Package (TSOP)
Reverse Pinout (TSR048)
WB = 48-ball Fine-Pitch Ball Grid Array (FBGA)
0.80 mm pitch, 6 x 9 mm package
SPEED OPTION
See Product Selector Guide and Valid Combinations
BOOT CODE SECTOR ARCHITECTURE
T = Top Sector
B = Bottom Sector
DEVICE NUMBER/DESCRIPTION
Am29SL800C
8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS Flash Memory
1.8 Volt-only Read, Program, and Erase
Valid Combinations
Valid Combinations
Am29SL800CT100,
Valid Combinations list configurations planned to be sup-
ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
Am29SL800CB100
Am29SL800CT120,
Am29SL800CB120
EC, EI, FC, FI, WBC, WBI
Am29SL800CT150,
Am29SL800CB150
Am29SL800C
7
P R E L I M I N A R Y
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register it-
self does not occupy any addressable memory loca-
tion. The register is composed of latches that store the
commands, along with the address and data informa-
tion needed to execute the command. The contents of
the register serve as inputs to the internal state ma-
chine. The state machine outputs dictate the function of
the device. Table 1 lists the device bus operations, the
inputs and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Table 1. Am29SL800C Device Bus Operations
DQ8–DQ15
BYTE#
= V
Addresses
(Note 1)
DQ0– BYTE#
Operation
CE# OE# WE# RESET#
DQ7
= V
IH
IL
Read
L
L
H
H
A
D
D
DQ8–DQ14 = High-Z,
DQ15 = A-1
IN
OUT
OUT
Write
L
H
L
H
A
D
D
IN
IN
IN
V
0.3 V
±
V
0.3 V
±
CC
CC
Standby
X
X
X
High-Z High-Z
High-Z
Output Disable
Reset
L
H
X
H
X
H
L
X
X
High-Z High-Z
High-Z High-Z
High-Z
High-Z
X
Sector Address,
A6 = L, A1 = H,
A0 = L
Sector Protect (Note 2)
L
H
L
V
D
X
X
X
ID
IN
Sector Address,
A6 = H, A1 = H,
A0 = L
Sector Unprotect (Note 2)
L
H
X
L
V
V
D
D
X
ID
ID
IN
Temporary Sector Unprotect
X
X
A
D
High-Z
IN
IN
IN
Legend:
L = Logic Low = V , H = Logic High = V , V = 10 ± 1.0 V, X = Don’t Care, A = Address In, D = Data In, D = Data Out
OUT
IL
IH
ID
IN
IN
Notes:
1. Addresses are A18:A0 in word mode (BYTE# = V ), A18:A-1 in byte mode (BYTE# = V ).
IH
IL
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector
Protection/Unprotection” section.
The internal state machine is set for reading array data
Word/Byte Configuration
upon device power-up, or after a hardware reset. This en-
The BYTE# pin controls whether the device data I/O pins
sures that no spurious alteration of the memory content oc-
DQ15–DQ0 operate in the byte or word configuration. If the
curs during the power transition. No command is
BYTE# pin is set at logic ‘1’, the device is in word configu-
necessary in this mode to obtain array data. Standard mi-
ration, DQ15–DQ0 are active and controlled by CE# and
croprocessor read cycles that assert valid addresses on
OE#.
the device address inputs produce valid data on the device
If the BYTE# pin is set at logic ‘0’, the device is in byte con-
figuration, and only data I/O pins DQ0–DQ7 are active and
controlled by CE# and OE#. The data I/O pins DQ8–DQ14
are tri-stated, and the DQ15 pin is used as an input for the
LSB (A-1) address function.
data outputs. The device remains enabled for read access
until the command register contents are altered.
See “Reading Array Data” for more information. Refer to
the AC Read Operations table for timing specifications and
to Figure 13 for the timing diagram. I
in the DC Charac-
CC1
teristics table represents the active current specification for
reading array data.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive
the CE# and OE# pins to V . CE# is the power control and
selects the device. OE# is the output control and gates
Writing Commands/Command Sequences
IL
To write a command or command sequence (which in-
cludes programming data to the device and erasing sectors
of memory), the system must drive WE# and CE# to V ,
array data to the output pins. WE# should remain at V .
IH
The BYTE# pin determines whether the device outputs
array data in words or bytes.
IL
and OE# to V .
IH
8
Am29SL800C
P R E L I M I N A R Y
For program operations, the BYTE# pin determines
If the device is deselected during erasure or programming,
the device draws active current until the operation is com-
pleted.
whether the device accepts program data in bytes or
words. Refer to “Word/Byte Configuration” for more infor-
mation.
I
in the DC Characteristics table represents the standby
CC3
The device features an Unlock Bypass mode to facilitate
faster programming. Once the device enters the Unlock
Bypass mode, only two write cycles are required to pro-
gram a word or byte, instead of four. The “Word/Byte Pro-
gram Command Sequence” section has details on
programming data to the device using both standard and
Unlock Bypass command sequences.
current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy
consumption. The device automatically enables this mode
when addresses remain stable for t
automatic sleep mode is independent of the CE#, WE#,
and OE# control signals. Standard address access timings
provide new data when addresses are changed. While in
sleep mode, output data is latched and always available to
+ 50 ns. The
ACC
An erase operation can erase one sector, multiple sectors,
or the entire device. Tables 2 and 3 indicate the address
space that each sector occupies. A “sector address” con-
sists of the address bits required to uniquely select a sector.
The “Command Definitions” section has details on erasing
a sector or the entire chip, or suspending/resuming the
erase operation.
the system. I
in the DC Characteristics table represents
CC4
the automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting
the device to reading array data. When the RESET# pin is
After the system writes the autoselect command se-
quence, the device enters the autoselect mode. The sys-
tem can then read autoselect codes from the internal
register (which is separate from the memory array) on
DQ7–DQ0. Standard read cycle timings apply in this mode.
Refer to the Autoselect Mode and Autoselect Command
Sequence sections for more information.
driven low for at least a period of t , the device immedi-
RP
ately terminates any operation in progress, tristates all
output pins, and ignores all read/write commands for the
duration of the RESET# pulse. The device also resets the
internal state machine to reading array data. The operation
that was interrupted should be reinitiated once the device is
ready to accept another command sequence, to ensure
data integrity.
I
in the DC Characteristics table represents the active
CC2
current specification for the write mode. The “AC Charac-
teristics” section contains timing specification tables and
timing diagrams for write operations.
Current is reduced for the duration of the RESET# pulse.
When RESET# is held at V ±0.3 V, the device draws
SS
CMOS standby current (I
). If RESET# is held at V but
CC4
IL
Program and Erase Operation Status
not within V ±0.3 V, the standby current will be greater.
SS
During an erase or program operation, the system may
check the status of the operation by reading the status bits
on DQ7–DQ0. Standard read cycle timings and I read
specifications apply. Refer to “Write Operation Status” for
more information, and to “AC Characteristics” for timing di-
agrams.
The RESET# pin may be tied to the system reset circuitry.
A system reset would thus also reset the Flash memory,
enabling the system to read the boot-up firmware from the
Flash memory.
CC
If RESET# is asserted during a program or erase opera-
tion, the RY/BY# pin remains a “0” (busy) until the internal
reset operation is complete, which requires a time of
Standby Mode
When the system is not reading or writing to the device, it
can place the device in the standby mode. In this mode,
current consumption is greatly reduced, and the outputs
are placed in the high impedance state, independent of the
OE# input.
t
(during Embedded Algorithms). The system can
READY
thus monitor RY/BY# to determine whether the reset oper-
ation is complete. If RESET# is asserted when a program
or erase operation is not executing (RY/BY# pin is “1”), the
reset operation is completed within a time of t
(not
READY
during Embedded Algorithms). The system can read data
after the RESET# pin returns to V .
The device enters the CMOS standby mode when the CE#
t
RH
IH
and RESET# pins are both held at V ± 0.3 V. (Note that
CC
this is a more restricted voltage range than V .) If CE# and
Refer to the AC Characteristics tables for RESET# param-
eters and to Figure 14 for the timing diagram.
IH
RESET# are held at V , but not within V ± 0.3 V, the de-
IH
CC
vice will be in the standby mode, but the standby current will
be greater. The device requires standard access time (t
Output Disable Mode
)
CE
for read access when the device is in either of these
standby modes, before it is ready to read data.
When the OE# input is at V , output from the device is dis-
abled. The output pins are placed in the high impedance
state.
IH
The device also enters the standby mode when the RE-
SET# pin is driven low. Refer to the next section, RESET#:
Hardware Reset Pin.
Am29SL800C
9
P R E L I M I N A R Y
Table 2. Am29SL800CT Top Boot Block Sector Address Table
Address Range (in hexadecimal)
Sector Size
(Kbytes/
(x8)
(x16)
Sector
SA0
A18
0
A17
0
A16
0
A15
0
A14
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
A13
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
A12
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
Kwords)
Address Range
Address Range
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
32/16
8/4
00000h–0FFFFh
10000h–1FFFFh
20000h–2FFFFh
30000h–3FFFFh
40000h–4FFFFh
50000h–5FFFFh
60000h–6FFFFh
70000h–7FFFFh
80000h–8FFFFh
90000h–9FFFFh
A0000h–AFFFFh
B0000h–BFFFFh
C0000h–CFFFFh
D0000h–DFFFFh
E0000h–EFFFFh
F0000h–F7FFFh
F8000h–F9FFFh
FA000h–FBFFFh
FC000h–FFFFFh
00000h–07FFFh
08000h–0FFFFh
10000h–17FFFh
18000h–1FFFFh
20000h–27FFFh
28000h–2FFFFh
30000h–37FFFh
38000h–3FFFFh
40000h–47FFFh
48000h–4FFFFh
50000h–57FFFh
58000h–5FFFFh
60000h–67FFFh
68000h–6FFFFh
70000h–77FFFh
78000h–7BFFFh
7C000h–7CFFFh
7D000h–7DFFFh
7E000h–7FFFFh
SA1
0
0
0
1
SA2
0
0
1
0
SA3
0
0
1
1
SA4
0
1
0
0
SA5
0
1
0
1
SA6
0
1
1
0
SA7
0
1
1
1
SA8
1
0
0
0
SA9
1
0
0
1
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
8/4
1
1
1
1
1
1
X
16/8
10
Am29SL800C
P R E L I M I N A R Y
Table 3. Am29SL800CB Bottom Boot Block Sector Address Table
Address Range (in hexadecimal)
Sector Size
(Kbytes/
(x8)
(x16)
Sector
SA0
A18
0
A17
0
A16
0
A15
0
A14
0
A13
0
A12
X
0
Kwords)
Address Range
Address Range
16/8
8/4
00000h–03FFFh
04000h–05FFFh
06000h–07FFFh
08000h–0FFFFh
10000h–1FFFFh
20000h–2FFFFh
30000h–3FFFFh
40000h–4FFFFh
50000h–5FFFFh
60000h–6FFFFh
70000h–7FFFFh
80000h–8FFFFh
90000h–9FFFFh
A0000h–AFFFFh
B0000h–BFFFFh
C0000h–CFFFFh
D0000h–DFFFFh
E0000h–EFFFFh
F0000h–FFFFFh
00000h–01FFFh
02000h–02FFFh
03000h–03FFFh
04000h–07FFFh
08000h–0FFFFh
10000h–17FFFh
18000h–1FFFFh
20000h–27FFFh
28000h–2FFFFh
30000h–37FFFh
38000h–3FFFFh
40000h–47FFFh
48000h–4FFFFh
50000h–57FFFh
58000h–5FFFFh
60000h–67FFFh
68000h–6FFFFh
70000h–77FFFh
78000h–7FFFFh
SA1
0
0
0
0
0
1
SA2
0
0
0
0
0
1
1
8/4
SA3
0
0
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
32/16
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
SA4
0
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA5
0
0
1
0
SA6
0
0
1
1
SA7
0
1
0
0
SA8
0
1
0
1
SA9
0
1
1
0
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Note for Tables 2 and 3: Address range is A18:A-1 in byte mode and A18:A0 in word mode. See “Word/Byte Configuration”
section for more information.
Am29SL800C
11
P R E L I M I N A R Y
when verifying sector protection, the sector address
Autoselect Mode
must appear on the appropriate highest order address
bits (see Tables 2 and 3). Table 4 shows the remaining
address bits that are don’t care. When all necessary bits
have been set as required, the programming equipment
may then read the corresponding identifier code on
DQ7–DQ0.
The autoselect mode provides manufacturer and de-
vice identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equipment
to automatically match a device to be programmed with
its corresponding programming algorithm. However,
the autoselect codes can also be accessed in-system
through the command register.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 5. This method
When using programming equipment, the autoselect
does not require V . See “Command Definitions” for
ID
mode requires V on address pin A9. Address pins A6,
ID
details on using the autoselect mode.
A1, and A0 must be as shown in Table 4. In addition,
Table 4. Am29SL800C Autoselect Codes (High Voltage Method)
A18 A11
to to
Mode CE# OE# WE# A12 A10 A9
A8
to
A7
A5
to
A2
DQ8
to
DQ15
DQ7
to
DQ0
Description
A6
A1 A0
Manufacturer ID: AMD
L
L
L
L
H
H
X
X
V
X
X
L
X
X
L
L
X
01h
ID
Device ID:
Am29SL800C
(Top Boot Block)
Word
Byte
Word
Byte
22h
EAh
X
X
V
L
L
L
H
ID
L
L
L
L
L
L
H
H
H
X
22h
X
EAh
6Bh
6Bh
Device ID:
Am29SL800C
(Bottom Boot Block)
X
X
X
V
V
X
X
X
X
L
H
L
ID
01h
(protected)
X
X
Sector Protection Verification
L
L
H
SA
L
H
ID
00h
(unprotected)
L = Logic Low = V , H = Logic High = V , SA = Sector Address, X = Don’t care.
IL
IH
an AMD representative to request the document con-
taining further details.
Sector Protection/Unprotection
The hardware sector protection feature disables both
program and erase operations in any sector. The hard-
ware sector unprotection feature re-enables both pro-
gram and erase operations in previously protected
sectors. Sector protection/unprotection can be imple-
mented via two methods.
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.
The primary method requires V on the RESET# pin
It is possible to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.
ID
only, and can be implemented either in-system or via
programming equipment. Figure 1 shows the algo-
rithms and Figure 23 shows the timing diagram. This
method uses standard microprocessor bus cycle tim-
ing. For sector unprotect, all unprotected sectors must
first be protected prior to the first sector unprotect write
cycle.
Temporary Sector Unprotect
This feature allows temporary unprotection of previ-
ously protected sectors to change data in-system. The
Sector Unprotect mode is activated by setting the RE-
SET# pin to V . During this mode, formerly protected
ID
sectors can be programmed or erased by selecting the
The alternate method intended only for programming
sector addresses. Once V is removed from the RE-
equipment requires V on address pin A9 and OE#.
ID
ID
SET# pin, all the previously protected sectors are
protected again. Figure 2 shows the algorithm, and
Figure 22 shows the timing diagrams, for this feature.
This method is compatible with programmer routines
written for earlier 3.0 volt-only AMD flash devices. Pub-
lication number 21622 contains further details. Contact
12
Am29SL800C
P R E L I M I N A R Y
START
START
Protect all sectors:
The indicated portion
of the sector protect
algorithm must be
performed for all
PLSCNT = 1
PLSCNT = 1
RESET# = VID
RESET# = VID
unprotected sectors
prior to issuing the
first sector
Wait 1 µs
Wait 1 µs
unprotect address
No
First Write
No
First Write
Cycle = 60h?
Temporary Sector
Unprotect Mode
Temporary Sector
Unprotect Mode
Cycle = 60h?
Yes
Yes
Set up sector
address
No
All sectors
protected?
Sector Protect:
Write 60h to sector
address with
A6 = 0, A1 = 1,
A0 = 0
Yes
Set up first sector
address
Sector Unprotect:
Wait 150 µs
Write 60h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Verify Sector
Protect: Write 40h
to sector address
with A6 = 0,
Reset
PLSCNT = 1
Increment
PLSCNT
Wait 15 ms
A1 = 1, A0 = 0
Verify Sector
Unprotect: Write
40h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Read from
sector address
with A6 = 0,
A1 = 1, A0 = 0
Increment
PLSCNT
No
No
PLSCNT
= 25?
Read from
sector address
with A6 = 1,
Data = 01h?
Yes
A1 = 1, A0 = 0
No
Yes
Set up
next sector
address
Yes
No
PLSCNT
= 1000?
Protect another
sector?
Data = 00h?
Yes
Device failed
No
Yes
Remove VID
from RESET#
No
Last sector
verified?
Device failed
Write reset
command
Yes
Remove VID
Sector Unprotect
Algorithm
from RESET#
Sector Protect
Algorithm
Sector Protect
complete
Write reset
command
Sector Unprotect
complete
22230A-5
Figure 1. In-System Sector Protect/Unprotect Algorithms
Am29SL800C
13
P R E L I M I N A R Y
mand definitions). In addition, the following hardware
data protection measures prevent accidental erasure
or programming, which might otherwise be caused by
START
spurious system level signals during V power-up and
CC
power-down transitions, or from system noise.
RESET# = V
(Note 1)
ID
Low V
Write Inhibit
CC
When V
is less than V
, the device does not ac-
LKO
CC
cept any write cycles. This protects data during V
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
CC
Perform Erase or
Program Operations
device resets. Subsequent writes are ignored until V
CC
is greater than V
. The system must provide the
RESET# = V
IH
LKO
proper signals to the control pins to prevent uninten-
tional writes when V is greater than V
.
CC
LKO
Temporary Sector
Unprotect Completed
(Note 2)
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
22230A-6
Write cycles are inhibited by holding any one of OE#
Notes:
1. All protected sectors unprotected.
= V , CE# = V or WE# = V . To initiate a write cy-
cle, CE# and WE# must be a logical zero while OE#
is a logical one.
IL
IH
IH
2. All previously protected sectors are protected once
again.
Power-Up Write Inhibit
Figure 2. Temporary Sector Unprotect Operation
If WE# = CE# = V and OE# = V during power
IL
IH
up, the device does not accept commands on the
rising edge of WE#. The internal state machine is
automatically reset to reading array data on
power-up.
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 5 for com-
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates device op-
erations. Table 5 defines the valid register command
sequences. Writing incorrect address and data val-
ues or writing them in the improper sequence resets
the device to reading array data.
read timings, except that if it reads at an address
within erase-suspended sectors, the device outputs
status data. After completing a programming opera-
tion in the Erase Suspend mode, the system may
once again read array data with the same exception.
See “Erase Suspend/Erase Resume Commands” for
more information on this mode.
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
“AC Characteristics” section.
The system must issue the reset command to re-ena-
ble the device for reading array data if DQ5 goes high,
or while in the autoselect mode. See the “Reset Com-
mand” section, next.
See also “Requirements for Reading Array Data” in the
“Device Bus Operations” section for more information.
The Read Operations table provides the read parame-
ters, and Figure 13 shows the timing diagram.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or Em-
bedded Erase algorithm.
Reset Command
Writing the reset command to the device resets the de-
vice to reading array data. Address bits are don’t care
for this command.
After the device accepts an Erase Suspend com-
mand, the device enters the Erase Suspend mode.
The system can read array data using the standard
14
Am29SL800C
P R E L I M I N A R Y
The reset command may be written between the se-
5 shows the address and data requirements for the
byte program command sequence.
quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ig-
nores reset commands until the operation is complete.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and ad-
dresses are no longer latched. The system can deter-
mine the status of the program operation by using DQ7,
DQ6, or RY/BY#. See “Write Operation Status” for in-
formation on these status bits.
The reset command may be written between the se-
quence cycles in a program command sequence be-
fore programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.
Any commands written to the device during the Em-
bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program-
ming operation. The Byte Program command se-
quence should be reinitiated once the device has reset
to reading array data, to ensure data integrity.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempting to do so may halt
the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indicate the operation was suc-
cessful. However, a succeeding read will show that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to read-
ing array data (also applies during Erase Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
Table 5 shows the address and data requirements. This
method is an alternative to that shown in Table 4, which
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to pro-
gram bytes or words to the device faster than using the
standard program command sequence. The unlock by-
pass command sequence is initiated by first writing two
unlock cycles. This is followed by a third write cycle
containing the unlock bypass command, 20h. The de-
vice then enters the unlock bypass mode. A two-cycle
unlock bypass program command sequence is all that
is required to program in this mode. The first cycle in
this sequence contains the unlock bypass program
command, A0h; the second cycle contains the program
address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program
command sequence, resulting in faster total program-
ming time. Table 5 shows the requirements for the com-
mand sequence.
is intended for PROM programmers and requires V
on address bit A9.
ID
The autoselect command sequence is initiated by writ-
ing two unlock cycles, followed by the autoselect com-
mand. The device then enters the autoselect mode,
and the system may read at any address any number
of times, without initiating another command sequence.
A read cycle at address XX00h retrieves the manufac-
turer code. A read cycle at address 01h in word mode
(or 02h in byte mode) returns the device code. A read
cycle containing a sector address (SA) and the address
02h in word mode (or 04h in byte mode) returns 01h if
that sector is protected, or 00h if it is unprotected. Refer
to Tables 2 and 3 for valid sector addresses.
During the unlock bypass mode, only the Unlock By-
pass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com-
mand sequence. The first cycle must contain the data
90h; the second cycle the data 00h. Addresses are
don’t cares. The device then returns to reading array
data.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Word/Byte Program Command Sequence
The system may program the device by word or byte,
depending on the state of the BYTE# pin. Program-
ming is a four-bus-cycle operation. The program com-
mand sequence is initiated by writing two unlock write
cycles, followed by the program set-up command. The
program address and data are written next, which in
turn initiate the Embedded Program algorithm. The
system is not required to provide further controls or tim-
ings. The device automatically generates the program
pulses and verifies the programmed cell margin. Table
Figure 3 illustrates the algorithm for the program oper-
ation. See the Erase/Program Operations table in “AC
Characteristics” for parameters, and to Figure 17 for
timing diagrams.
Am29SL800C
15
P R E L I M I N A R Y
The system can determine the status of the erase op-
eration by using DQ7, DQ6, DQ2, or RY/BY#. See
“Write Operation Status” for information on these sta-
tus bits. When the Embedded Erase algorithm is com-
plete, the device returns to reading array data and
addresses are no longer latched.
START
Write Program
Command Sequence
Figure 4 illustrates the algorithm for the erase opera-
tion. See the Erase/Program Operations tables in “AC
Characteristics” for parameters, and to Figure 18 for
timing diagrams.
Data Poll
from System
Sector Erase Command Sequence
Embedded
Program
algorithm
in progress
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two un-
lock cycles, followed by a set-up command. Two addi-
tional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command. Table 5 shows the address and data
requirements for the sector erase command sequence.
Verify Data?
Yes
No
The device does not require the system to preprogram
the memory prior to erase. The Embedded Erase algo-
rithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
No
Increment Address
Last Address?
Yes
Programming
Completed
After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time be-
tween these additional cycles must be less than 50 µs,
otherwise the last address and command might not be
accepted, and erasure may begin. It is recommended
that processor interrupts be disabled during this time to
ensure all commands are accepted. The interrupts can
be re-enabled after the last Sector Erase command is
written. If the time between additional sector erase
commands can be assumed to be less than 50 µs, the
system need not monitor DQ3. Any command other
than Sector Erase or Erase Suspend during the
time-out period resets the device to reading array
data. The system must rewrite the command sequence
and any additional sector addresses and commands.
22230A-7
Note: See Table 5 for program command sequence.
Figure 3. Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Table 5 shows
the address and data requirements for the chip erase
command sequence.
The system can monitor DQ3 to determine if the sector
erase timer has timed out. (See the “DQ3: Sector Erase
Timer” section.) The time-out begins from the rising
edge of the final WE# pulse in the command sequence.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands
are ignored. Note that a hardware reset during the
sector erase operation immediately terminates the op-
eration. The Sector Erase command sequence should
be reinitiated once the device has returned to reading
array data, to ensure data integrity.
Any commands written to the chip during the Embed-
ded Erase algorithm are ignored. Note that a hardware
reset during the chip erase operation immediately ter-
minates the operation. The Chip Erase command se-
quence should be reinitiated once the device has
returned to reading array data, to ensure data integrity.
16
Am29SL800C
P R E L I M I N A R Y
When the Embedded Erase algorithm is complete, the
the Erase Suspend mode, and is ready for another
valid operation. See “Autoselect Command Sequence”
for more information.
device returns to reading array data and addresses are
no longer latched. The system can determine the sta-
tus of the erase operation by using DQ7, DQ6, DQ2, or
RY/BY#. (Refer to “Write Operation Status” for informa-
tion on these status bits.)
The system must write the Erase Resume command
(address bits are “don’t care”) to exit the erase suspend
mode and continue the sector erase operation. Further
writes of the Resume command are ignored. Another
Erase Suspend command can be written after the de-
vice has resumed erasing.
Figure 4 illustrates the algorithm for the erase opera-
tion. Refer to the Erase/Program Operations tables in
the “AC Characteristics” section for parameters, and to
Figure 18 for timing diagrams.
Erase Suspend/Erase Resume Commands
START
The Erase Suspend command allows the system to in-
terrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the 50 µs time-out period
during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program algo-
rithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
time-out period and suspends the erase operation. Ad-
dresses are “don’t-cares” when writing the Erase Sus-
pend command.
Write Erase
Command Sequence
Data Poll
from System
Embedded
Erase
algorithm
in progress
When the Erase Suspend command is written during a
sector erase operation, the device requires a maximum
of 20 µs to suspend the erase operation. However,
when the Erase Suspend command is written during
the sector erase time-out, the device immediately ter-
minates the time-out period and suspends the erase
operation.
No
Data = FFh?
Yes
Erasure Completed
After the erase operation has been suspended, the
system can read array data from or program data to
any sector not selected for erasure. (The device “erase
suspends” all sectors selected for erasure.) Normal
read and write timings and command definitions apply.
Reading at any address within erase-suspended sec-
tors produces status data on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
See “Write Operation Status” for information on these
status bits.
22230A-8
Notes:
1. See Table 5 for erase command sequence.
2. See “DQ3: Sector Erase Timer” for more information.
Figure 4. Erase Operation
After an erase-suspended program operation is com-
plete, the system can once again read array data within
non-suspended sectors. The system can determine
the status of the program operation using the DQ7 or
DQ6 status bits, just as in the standard program oper-
ation. See “Write Operation Status” for more informa-
tion.
The system may also write the autoselect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to
Am29SL800C
17
P R E L I M I N A R Y
Table 5. Am29SL800C Command Definitions
Bus Cycles (Notes 2-5)
Command
Sequence
(Note 1)
First
Second
Third
Addr
Fourth
Fifth
Sixth
Addr Data Addr Data
Data Addr Data Addr Data Addr Data
Read (Note 6)
Reset (Note 7)
1
1
RA
XXX
555
AAA
555
AAA
555
AAA
RD
F0
Word
Byte
Word
Byte
Word
Byte
2AA
555
2AA
555
2AA
555
555
AAA
555
Manufacturer ID
4
4
4
AA
AA
AA
55
55
55
90
90
90
X00
01
X01 22EA
X02
X01 226B
Device ID,
Top Boot Block
AAA
555
EA
Device ID,
Bottom Boot Block
X02
AAA
6B
XX00
XX01
00
(SA)
X02
Word
Byte
555
2AA
555
555
Sector Protect Verify
(Note 9)
4
AA
55
90
(SA)
X04
AAA
AAA
01
Word
Byte
Word
Byte
555
AAA
555
2AA
555
2AA
555
PA
555
AAA
555
Program
4
3
AA
AA
55
55
A0
20
PA
PD
Unlock Bypass
AAA
XXX
XXX
555
AAA
Unlock Bypass Program (Note 10)
Unlock Bypass Reset (Note 11)
2
2
A0
90
PD
00
XXX
2AA
555
2AA
555
Word
555
AAA
555
555
AAA
555
2AA
555
2AA
555
555
Chip Erase
Byte
6
6
AA
AA
55
55
80
80
AA
AA
55
55
10
30
AAA
555
AAA
Word
Sector Erase
Byte
SA
AAA
XXX
XXX
AAA
AAA
Erase Suspend (Note 12)
Erase Resume (Note 13)
1
1
B0
30
Legend:
X = Don’t care
PD = Data to be programmed at location PA. Data latches on the
rising edge of WE# or CE# pulse, whichever happens first.
RA = Address of the memory location to be read.
SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A18–A12 uniquely select any sector.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed.
Addresses latch on the falling edge of the WE# or CE# pulse,
whichever happens later.
Notes:
1. See Table 1 for description of bus operations.
9. The data is 00h for an unprotected sector and 01h for a
protected sector. See “Autoselect Command Sequence” for
more information.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles
are write operations.
10. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
4. Data bits DQ15–DQ8 are don’t cares for unlock and
command cycles.
11. The Unlock Bypass Reset command is required to return to
reading array data when the device is in the unlock bypass
mode.
5. Address bits A18–A11 are don’t cares for unlock and
command cycles, unless SA or PA required.
12. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend
mode. The Erase Suspend command is valid only during a
sector erase operation.
6. No unlock or command cycles required when reading array
data, unless SA or PA required.
7. The Reset command is required to return to reading array
data when device is in the autoselect mode, or if DQ5 goes
high (while the device is providing status data).
13. The Erase Resume command is valid only during the Erase
Suspend mode.
8. The fourth cycle of the autoselect command sequence is a
read cycle.
18
Am29SL800C
P R E L I M I N A R Y
WRITE OPERATION STATUS
The device provides several bits to determine the sta-
tus of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7,
and RY/BY#. Table 6 and the following subsections de-
scribe the functions of these bits. DQ7, RY/BY#, and
DQ6 each offer a method for determining whether a
program or erase operation is complete or in progress.
These three bits are discussed first.
Table 6 shows the outputs for Data# Polling on DQ7.
Figure 5 shows the Data# Polling algorithm.
START
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system
whether an Embedded Algorithm is in progress or com-
pleted, or whether the device is in Erase Suspend.
Data# Polling is valid after the rising edge of the final
WE# pulse in the program or erase command sequence.
Read DQ7–DQ0
Addr = VA
Yes
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum pro-
grammed to DQ7. This DQ7 status also applies to pro-
gramming during Erase Suspend. When the
Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for ap-
proximately 1 µs, then the device returns to reading
array data.
DQ7 = Data?
No
No
DQ5 = 1?
Yes
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase al-
gorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
This is analogous to the complement/true datum output
described for the Embedded Program algorithm: the
erase function changes all the bits in a sector to “1”;
prior to this, the device outputs the “complement,” or
“0.” The system must provide an address within any of
the sectors selected for erasure to read valid status in-
formation on DQ7.
Read DQ7–DQ0
Addr = VA
Yes
DQ7 = Data?
No
After an erase command sequence is written, if all sec-
tors selected for erasing are protected, Data# Polling
on DQ7 is active for approximately 100 µs, then the de-
vice returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se-
lected sectors that are protected.
PASS
FAIL
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
When the system detects DQ7 has changed from the
complement to true data, it can read valid data at DQ7–
DQ0 on the following read cycles. This is because DQ7
may change asynchronously with DQ0–DQ6 while
Output Enable (OE#) is asserted low. Figure 19, Data#
Polling Timings (During Embedded Algorithms), in the
“AC Characteristics” section illustrates this.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
22230A-9
Figure 5. Data# Polling Algorithm
Am29SL800C
19
P R E L I M I N A R Y
Table 6 shows the outputs for Toggle Bit I on DQ6. Fig-
RY/BY#: Ready/Busy#
ure 6 shows the toggle bit algorithm. Figure 20 in the
“AC Characteristics” section shows the toggle bit timing
diagrams. Figure 21 shows the differences between
DQ2 and DQ6 in graphical form. See also the subsec-
tion on DQ2: Toggle Bit II.
The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, sev-
eral RY/BY# pins can be tied together in parallel with a
DQ2: Toggle Bit II
pull-up resistor to V
.
CC
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence. The device toggles DQ2 with
each OE# or CE# read cycle.
If the output is low (Busy), the device is actively erasing
or programming. (This includes programming in the
Erase Suspend mode.) If the output is high (Ready),
the device is ready to read array data (including during
the Erase Suspend mode), or is in the standby mode.
Table 6 shows the outputs for RY/BY#. Figures 14, 17
and 18 shows RY/BY# for reset, program, and erase
operations, respectively.
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for eras-
ure. But DQ2 cannot distinguish whether the sector is
actively erasing or is erase-suspended. DQ6, by com-
parison, indicates whether the device is actively eras-
ing, or is in Erase Suspend, but cannot distinguish
which sectors are selected for erasure. Thus, both sta-
tus bits are required for sector and mode information.
Refer to Table 6 to compare outputs for DQ2 and DQ6.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or erase op-
eration), and during the sector erase time-out.
Figure 6 shows the toggle bit algorithm in flowchart
form, and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the DQ6: Toggle Bit I subsection.
Figure 20 shows the toggle bit timing diagram. Figure
21 shows the differences between DQ2 and DQ6 in
graphical form.
During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address cause
DQ6 to toggle (The system may use either OE# or CE#
to control the read cycles). When the operation is com-
plete, DQ6 stops toggling.
Reading Toggle Bits DQ6/DQ2
After an erase command sequence is written, if all sec-
tors selected for erasing are protected, DQ6 toggles for
approximately 100 µs, then returns to reading array
data. If not all selected sectors are protected, the Em-
bedded Erase algorithm erases the unprotected sec-
tors, and ignores the selected sectors that are
protected.
Refer to Figure 6 for the following discussion. Whenever
the system initially begins reading toggle bit status, it
must read DQ7–DQ0 at least twice in a row to determine
whether a toggle bit is toggling. Typically, the system
would note and store the value of the toggle bit after the
first read. After the second read, the system would com-
pare the new value of the toggle bit with the first. If the
toggle bit is not toggling, the device has completed the
program or erase operation. The system can read array
data on DQ7–DQ0 on the following read cycle.
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is erase-
suspended. When the device is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on DQ7: Data# Polling).
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys-
tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is toggling,
since the toggle bit may have stopped toggling just as
DQ5 went high. If the toggle bit is no longer toggling,
the device has successfully completed the program or
erase operation. If it is still toggling, the device did not
completed the operation successfully, and the system
must write the reset command to return to reading
array data.
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 µs after the program
command sequence is written, then returns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
20
Am29SL800C
P R E L I M I N A R Y
The remaining scenario is that the system initially de-
DQ5: Exceeded Timing Limits
termines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles, de-
termining the status as described in the previous para-
graph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the
beginning of the algorithm when it returns to determine
the status of the operation (top of Figure 6).
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a “1.” This is a failure
condition that indicates the program or erase cycle was
not successfully completed.
The DQ5 failure condition may appear if the system
tries to program a “1” to a location that is previously pro-
grammed to “0.” Only an erase operation can change
a “0” back to a “1.” Under this condition, the device
halts the operation, and when the operation has ex-
ceeded the timing limits, DQ5 produces a “1.”
START
Under both these conditions, the system must issue the
reset command to return the device to reading array
data.
Read DQ7–DQ0
(Note 1)
DQ3: Sector Erase Timer
Read DQ7–DQ0
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If additional
sectors are selected for erasure, the entire time-out also
applies after each additional sector erase command.
When the time-out is complete, DQ3 switches from “0” to
“1.” If the time between additional sector erase com-
mands from the system can be assumed to be less than
50 µs, the system need not monitor DQ3. See also the
“Sector Erase Command Sequence” section.
No
Toggle Bit
= Toggle?
Yes
No
DQ5 = 1?
Yes
After the sector erase command sequence is written,
the system should read the status on DQ7 (Data# Poll-
ing) or DQ6 (Toggle Bit I) to ensure the device has ac-
cepted the command sequence, and then read DQ3. If
DQ3 is “1”, the internally controlled erase cycle has be-
gun; all further commands (other than Erase Suspend)
are ignored until the erase operation is complete. If
DQ3 is “0”, the device will accept additional sector
erase commands. To ensure the command has been
accepted, the system software should check the status
of DQ3 prior to and following each subsequent sector
erase command. If DQ3 is high on the second status
check, the last command might not have been ac-
cepted. Table 6 shows the outputs for DQ3.
(Notes
1, 2)
Read DQ7–DQ0
Twice
Toggle Bit
= Toggle?
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Notes:
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQ5
changes to “1” . See text.
22230A-10
Figure 6. Toggle Bit Algorithm
Am29SL800C
21
P R E L I M I N A R Y
Table 6. Write Operation Status
DQ7
DQ5
DQ2
Operation
(Note 2)
DQ6
(Note 1)
DQ3
N/A
1
(Note 2)
RY/BY#
Embedded Program Algorithm
Embedded Erase Algorithm
DQ7#
0
Toggle
Toggle
0
0
No toggle
Toggle
0
0
Standard
Mode
Reading within Erase
Suspended Sector
1
No toggle
0
N/A
Toggle
1
Erase
Suspend Reading within Non-Erase
Data
Data
Data
0
Data
N/A
Data
N/A
1
0
Mode
Suspended Sector
Erase-Suspend-Program
DQ7#
Toggle
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “DQ5: Exceeded Timing Limits” for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
22
Am29SL800C
P R E L I M I N A R Y
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C
20 ns
20 ns
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . –65°C to +125°C
0.0 V
–0.5 V
–2.0 V
Voltage with Respect to Ground
V
(Note 1) . . . . . . . . . . . . . . . .–0.5 V to +2.5 V
CC
A9, OE#,
20 ns
and RESET# (Note 2) . . . . . . . .–0.5 V to +11.0 V
All other pins (Note 1) . . . . . –0.5 V to V +0.5 V
CC
Output Short Circuit Current (Note 3) . . . . . . 100 mA
22230A-11
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V. During
Figure 7. Maximum Negative Overshoot
Waveform
voltage transitions, input or I/O pins may overshoot V to
SS
–2.0 V for periods of up to 20 ns. See Figure 7. Maximum
DC voltage on input or I/O pins is V +0.5 V. During
CC
voltage transitions, input or I/O pins may overshoot to V
+2.0 V for periods up to 20 ns. See Figure 8.
CC
2. Minimum DC input voltage on pins A9, OE#, and RESET#
is –0.5 V. During voltage transitions, A9, OE#, and
20 ns
RESET# may overshoot V to –2.0 V for periods of up to
V
SS
CC
+2.0 V
20 ns. See Figure 7. Maximum DC input voltage on pin A9
is +11.0 V which may overshoot to 12.5 V for periods up
to 20 ns.
V
CC
+0.5 V
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.
2.0 V
20 ns
20 ns
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is
a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.
22230A-12
Figure 8. Maximum Positive Overshoot
Waveform
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (T ) . . . . . . . . . . . 0°C to +70°C
A
Industrial (I) Devices
Ambient Temperature (T ) . . . . . . . . . –40°C to +85°C
A
V
Supply Voltages
CC
V
, all speed options . . . . . . . . . . . .+1.8 V to +2.2 V
CC
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
Am29SL800C
23
P R E L I M I N A R Y
DC CHARACTERISTICS
CMOS Compatible
Parameter
Description
Test Conditions
= V to V
Min
Typ
Max
±1.0
35
Unit
µA
V
V
,
CC
IN
SS
I
Input Load Current
LI
= V
CC
CC max
I
A9 Input Load Current
Output Leakage Current
V
= V
; A9 = 11.0 V
µA
LIT
CC
CC max
V
V
= V to V
,
OUT
SS
CC
I
±1.0
µA
LO
= V
CC
CC max
5 MHz
1 MHz
5 MHz
1 MHz
5
1
5
1
10
3
CE# = V OE#
Byte Mode
V
V
IL,
=
=
IH,
IH,
V
Active Read Current
CC
I
I
mA
mA
CC1
(Notes 1, 2)
10
3
CE# = V OE#
IL,
Word Mode
V
Active Write Current
CC
CE# = V OE#
V
20
25
CC2
IL,
=
IH
(Notes 2, 3, 5)
I
I
V
V
Standby Current (Note 2)
Reset Current (Note 2)
CE#, RESET# = V ±0.3 V
1
1
5
5
µA
µA
CC3
CC4
CC
CC
CC
RESET# = V ± 0.3 V
SS
Automatic Sleep Mode
(Notes 2, 3)
V
V
= V ± 0.3 V;
CC
IH
IL
I
1
5
µA
CC5
= V ± 0.3 V
SS
V
Input Low Voltage
Input High Voltage
–0.5
0.2 x V
V
V
IL
CC
V
0.8 x V
V
+ 0.3
IH
CC
CC
Voltage for Autoselect and
Temporary Sector Unprotect
V
V
= 2.0 V
9.0
11.0
V
V
ID
CC
V
V
I
I
I
I
= 2.0 mA, V = V
0.25
0.1
OL1
OL2
OH1
OH2
OL
OL
OH
OH
CC
CC min
Output Low Voltage
Output High Voltage
= 100 µA, V = V
CC
CC min
V
V
= –2.0 mA, V = V
0.7 x V
CC
V
V
CC
CC min
= –100 µA, V = V
V
–0.1
CC
CC
CC min
Low V Lock-Out Voltage
CC
V
1.2
1.5
LKO
(Note 4)
Notes:
1. The I current listed is typically less than 1 mA/MHz, with OE# at V . Typical V is 2.0 V.
CC
IL
CC
2. The maximum I specifications are tested with V = V max.
CC
CC
CC
3.
I
active while Embedded Erase or Embedded Program is in progress.
CC
4. Automatic sleep mode enables the low power mode when addresses remain stable for t
5. Not 100% tested.
+ 50 ns.
ACC
24
Am29SL800C
P R E L I M I N A R Y
DC CHARACTERISTICS (Continued)
Zero Power Flash
20
15
10
5
0
0
500
1000
1500
2000
2500
3000
3500
4000
Time in ns
Note: Addresses are switching at 1 MHz
22230A-13
Figure 9.
I
Current vs. Time (Showing Active and Automatic Sleep Currents)
CC1
10
8
6
2.2 V
4
1.8 V
2
0
1
2
3
4
5
Frequency in MHz
Note: T = 25 °C
22230A-14
Figure 10. Typical I
vs. Frequency
CC1
Am29SL800C
25
P R E L I M I N A R Y
TEST CONDITIONS
Table 7. Test Specifications
Test Condition
100
120, 150 Unit
Output Load
1 TTL gate
Device
Under
Test
Output Load Capacitance, C
L
30
100
pF
(including jig capacitance)
Input Rise and Fall Times
Input Pulse Levels
5
0.0–2.0
ns
C
L
V
Input timing measurement
reference levels
1.0
1.0
V
V
Output timing measurement
reference levels
22230A-15
Figure 11. Test Setup
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
KS000010-PAL
2.0 V
0.0 V
1.0 V
1.0 V
Input
Measurement Level
Output
22230A-16
Figure 12. Input Waveforms and Measurement Levels
26
Am29SL800C
P R E L I M I N A R Y
AC CHARACTERISTICS
Read Operations
Parameter
Speed Option
JEDEC
Std
Description
Test Setup
100
120
150
Unit
t
t
Read Cycle Time (Note 1)
Address to Output Delay
Min
100
100
120
150
150
ns
AVAV
RC
CE# = V
OE# = V
IL
IL
t
t
Max
120
ns
AVQV
ACC
t
t
Chip Enable to Output Delay
OE# = V
Max
Max
Max
Max
Min
100
35
120
50
60
60
0
150
65
ns
ns
ns
ns
ns
ELQV
GLQV
EHQZ
GHQZ
CE
IL
t
t
t
Output Enable to Output Delay
OE
t
Chip Enable to Output High Z (Note 1)
Output Enable to Output High Z (Note 1)
50
60
DF
DF
t
t
50
60
Read
Output Enable
t
OEH
Toggle and
Data# Polling
Hold Time (Note 1)
Min
Min
30
0
ns
ns
Output Hold Time From Addresses, CE# or
OE#, Whichever Occurs First (Note 1)
t
t
OH
AXQX
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 7 for test specifications.
tRC
Addresses Stable
tACC
Addresses
CE#
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0 V
22230A-17
Figure 13. Read Operations Timings
Am29SL800C
27
P R E L I M I N A R Y
AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
JEDEC
Std
Description
Test Setup
Max
All Speed Options
Unit
RESET# Pin Low (During Embedded
Algorithms) to Read or Write (see Note)
t
20
µs
READY
RESET# Pin Low (NOT During Embedded
Algorithms) to Read or Write (see Note)
t
Max
500
ns
READY
t
RESET# Pulse Width
Min
Min
Min
Min
500
200
20
ns
ns
µs
ns
RP
t
RESET# High Time Before Read (see Note)
RESET# Low to Standby Mode
RY/BY# Recovery Time
RH
t
RPD
t
0
RB
Note: Not 100% tested.
RY/BY#
CE#, OE#
RESET#
tRH
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRP
22230A-18
Figure 14. RESET# Timings
28
Am29SL800C
P R E L I M I N A R Y
AC CHARACTERISTICS
Word/Byte Configuration (BYTE#)
Parameter
JEDEC
Std
Description
CE# to BYTE# Switching Low or High
100
120
10
150
Unit
ns
t
t
t
t
Max
Max
Min
ELFL/ ELFH
BYTE# Switching Low to Output HIGH Z
BYTE# Switching High to Output Active
50
60
60
ns
FLQZ
FHQV
100
120
150
ns
CE#
OE#
BYTE#
t
ELFL
Data Output
(DQ0–DQ14)
Data Output
(DQ0–DQ7)
BYTE#
DQ0–DQ14
DQ15/A-1
Switching
from word
to byte
Address
Input
DQ15
Output
mode
t
FLQZ
t
ELFH
BYTE#
BYTE#
Switching
from byte
to word
Data Output
(DQ0–DQ7)
Data Output
(DQ0–DQ14)
DQ0–DQ14
DQ15/A-1
mode
Address
Input
DQ15
Output
t
FHQV
22230A-19
Figure 15. BYTE# Timings for Read Operations
CE#
The falling edge of the last WE# signal
WE#
BYTE#
t
SET
(t
)
AS
t
(t
)
HOLD AH
Note: Refer to the Erase/Program Operations table for t and t specifications.
AS
AH
22230A-20
Figure 16. BYTE# Timings for Write Operations
Am29SL800C
29
P R E L I M I N A R Y
AC CHARACTERISTICS
Erase/Program Operations
Parameter
JEDEC
Std
Description
Write Cycle Time (Note 1)
100
120
120
0
150
Unit
ns
t
t
Min
Min
Min
Min
Min
Min
100
150
AVAV
WC
t
t
Address Setup Time
Address Hold Time
Data Setup Time
ns
AVWL
WLAX
DVWH
WHDX
AS
AH
DS
DH
t
t
50
50
60
60
0
70
70
ns
t
t
ns
t
t
Data Hold Time
ns
t
Output Enable Setup Time
0
ns
OES
Read Recovery Time Before Write
(OE# High to WE# Low)
t
t
Min
0
ns
GHWL
GHWL
t
t
CE# Setup Time
Min
Min
Min
Min
Typ
Typ
Typ
Min
Min
Min
0
0
ns
ns
ns
ns
ELWL
WHEH
WLWH
WHWL
CS
CH
WP
t
t
t
CE# Hold Time
t
Write Pulse Width
Write Pulse Width High
50
60
30
10
12
2
70
t
t
WPH
Byte
t
t
Programming Operation (Notes 1, 2)
µs
WHWH1
WHWH1
Word
t
t
Sector Erase Operation (Notes 1, 2)
sec
µs
WHWH2
WHWH2
t
V
Setup Time
50
0
VCS
CC
t
Recovery Time from RY/BY#
ns
RB
t
Program/Erase Valid to RY/BY# Delay
200
ns
BUSY
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
30
Am29SL800C
P R E L I M I N A R Y
AC CHARACTERISTICS
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tAS
PA
tWC
Addresses
555h
PA
PA
tAH
CE#
OE#
tCH
tGHWL
tWHWH1
tWP
WE#
Data
tWPH
tCS
tDS
tDH
PD
DOUT
A0h
Status
tBUSY
tRB
RY/BY#
VCC
tVCS
Notes:
1. PA = program address, PD = program data, D
is the true data at the program address.
OUT
2. Illustration shows device in word mode.
22230A-21
Figure 17. Program Operation Timings
Am29SL800C
31
P R E L I M I N A R Y
AC CHARACTERISTICS
Erase Command Sequence (last two cycles)
Read Status Data
VA
tAS
SA
tWC
VA
Addresses
CE#
2AAh
555h for chip erase
tAH
tGHWL
tCH
OE#
tWP
WE#
tWPH
tWHWH2
tCS
tDS
tDH
In
Data
Complete
55h
30h
Progress
10 for Chip Erase
tBUSY
tRB
RY/BY#
VCC
tVCS
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).
2. Illustration shows device in word mode.
22230A-22
Figure 18. Chip/Sector Erase Operation Timings
32
Am29SL800C
P R E L I M I N A R Y
AC CHARACTERISTICS
tRC
VA
Addresses
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
WE#
tOEH
tDF
tOH
Complement
High Z
High Z
DQ7
Valid Data
Complement
Status Data
True
DQ0–DQ6
Valid Data
Status Data
True
tBUSY
RY/BY#
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
22230A-23
Figure 19. Data# Polling Timings (During Embedded Algorithms)
tRC
Addresses
CE#
VA
tACC
tCE
VA
VA
VA
tCH
tOE
OE#
WE#
tOEH
tDF
tOH
High Z
DQ6/DQ2
RY/BY#
Valid Status
(first read)
Valid Status
Valid Status
Valid Data
(second read)
(stops toggling)
tBUSY
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read
cycle, and array data read cycle.
22230A-24
Figure 20. Toggle Bit Timings (During Embedded Algorithms)
Am29SL800C
33
P R E L I M I N A R Y
AC CHARACTERISTICS
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase
Complete
WE#
Erase
Erase Suspend
Read
DQ6
DQ2
Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an
erase-suspended sector.
22230A-25
Figure 21. DQ2 vs. DQ6
Temporary Sector Unprotect
Parameter
JEDEC
Std
Description
Rise and Fall Time
ID
All Speed Options
Unit
t
V
Min
Min
500
ns
VIDR
RESET# Setup Time for Temporary Sector
Unprotect
t
4
µs
RSP
10 V
RESET#
0 or 1.8 V
0 or 1.8 V
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
tRSP
RY/BY#
22230A-26
Figure 22. Temporary Sector Unprotect Timing Diagram
34
Am29SL800C
P R E L I M I N A R Y
AC CHARACTERISTICS
VID
VIH
RESET#
SA, A6,
A1, A0
Valid*
Sector Protect/Unprotect
60h 60h
Valid*
Valid*
Status
Verify
40h
Data
Sector Protect: 150 µs
Sector Unprotect: 15 ms
1 µs
CE#
WE#
OE#
* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
22230A-27
Figure 23. Sector Protect/Unprotect Timing Diagram
Am29SL800C
35
P R E L I M I N A R Y
AC CHARACTERISTICS
Alternate CE# Controlled Erase/Program Operations
Parameter
JEDEC
Std
Description
Write Cycle Time (Note 1)
100
120
120
0
150
Unit
ns
t
t
t
Min
Min
Min
Min
Min
Min
100
150
AVAV
AVEL
ELAX
DVEH
EHDX
WC
t
Address Setup Time
Address Hold Time
Data Setup Time
ns
AS
AH
DS
DH
t
t
50
50
60
60
0
70
70
ns
t
t
ns
t
t
Data Hold Time
ns
t
Output Enable Setup Time
0
ns
OES
Read Recovery Time Before Write
(OE# High to WE# Low)
t
t
t
Min
0
ns
GHEL
WLEL
GHEL
t
WE# Setup Time
WE# Hold Time
Min
Min
Min
Min
Typ
Typ
Typ
0
0
ns
ns
ns
ns
WS
t
t
EHWH
WH
t
t
CE# Pulse Width
CE# Pulse Width High
50
60
30
10
12
2
70
ELEH
EHEL
CP
t
t
CPH
Byte
Programming Operation
(Notes 1, 2)
t
t
µs
WHWH1
WHWH1
Word
t
t
Sector Erase Operation (Notes 1, 2)
sec
WHWH2
WHWH2
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
36
Am29SL800C
P R E L I M I N A R Y
AC CHARACTERISTICS
555 for program
PA for program
2AA for erase
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tWH
tAS
tAH
WE#
OE#
tGHEL
tWHWH1 or 2
tCP
CE#
Data
tWS
tCPH
tDS
tBUSY
tDH
DQ7#
DOUT
tRH
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. PA = program address, PD = program data, DQ7# = complement of the data written, D
2. Figure indicates the last two bus cycles of command sequence.
3. Word mode address used as an example.
= data written
OUT
22230A-28
Figure 24. Alternate CE# Controlled Write Operation Timings
Am29SL800C
37
P R E L I M I N A R Y
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ (Note 1)
Max (Note 2)
Unit
s
Comments
Sector Erase Time
Chip Erase Time
2
15
Excludes 00h programming
prior to erasure (Note 4)
38
10
12
10
7
s
Byte Programming Time
Word Programming Time
300
360
80
µs
µs
s
Excludes system level
overhead (Note 5)
Byte Mode
Word Mode
Chip Programming Time
(Note 3)
60
s
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 2.0 V V , 1,000,000 cycles. Additionally,
CC
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, V = 1.8 V, 1,000,000 cycles.
CC
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See
Table 5 for further information on command definitions.
6. The device has a minimum guaranteed erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Description
Min
Max
Input voltage with respect to V on all pins except I/O pins
(including A9, OE#, and RESET#)
SS
–1.0 V
11.0 V
Input voltage with respect to V on all I/O pins
–0.5 V
V
+ 0.5 V
SS
CC
V
Current
–100 mA
+100 mA
CC
Includes all pins except V . Test conditions: V = 1.8 V, one pin at a time.
CC
CC
TSOP PIN CAPACITANCE
Parameter
Symbol
Parameter Description
Input Capacitance
Test Setup
Typ
6
Max
7.5
12
Unit
pF
C
V
= 0
IN
IN
C
Output Capacitance
Control Pin Capacitance
V
= 0
8.5
7.5
pF
OUT
OUT
C
V
= 0
9
pF
IN2
IN
Notes:
1. Sampled, not 100% tested.
2. Test conditions T = 25°C, f = 1.0 MHz.
A
DATA RETENTION
Parameter
Test Conditions
150°C
Min
10
Unit
Years
Years
Minimum Pattern Data Retention Time
125°C
20
38
Am29SL800C
P R E L I M I N A R Y
PHYSICAL DIMENSIONS*
TS 048—48-Pin Standard TSOP (measured in millimeters)
0.95
1.05
Pin 1 I.D.
1
48
11.90
12.10
0.50 BSC
24
25
0.05
0.15
18.30
18.50
19.80
20.20
16-038-TS48-2
TS 048
DA101
0.08
0.20
0.10
0.21
1.20
MAX
8-8-94 ae
0°
5°
0.25MM (0.0098") BSC
0.50
0.70
* For reference only. BSC is an ANSI standard for Basic Space Centering
TSR048—48-Pin Reverse TSOP (measured in millimeters)
0.95
1.05
Pin 1 I.D.
1
48
11.90
12.10
0.50 BSC
24
25
0.05
0.15
18.30
18.50
19.80
20.20
SEATING PLANE
16-038-TS48
TSR048
DA104
0.08
0.20
8-8-94 ae
1.20
MAX
0.10
0.21
0°
5°
0.25MM (0.0098") BSC
0.50
0.70
* For reference only. BSC is an ANSI standard for Basic Space Centering.
Am29SL800C
39
P R E L I M I N A R Y
PHYSICAL DIMENSIONS
FGB048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 6 x 9 mm (measured in millimeters)
M
0.15
Z B M
8.80
9.20
DATUM B
5.80
6.20
M
0.15
Z B M
0.025
CHAMFER
INDEX
DATUM A
5.60
BSC
0.40
4.00
BSC
0.80
0.40 ± 0.08 (48x)
0.08
0.40
M
Z A
B
0.10 Z
0.25
0.45
DETAIL A
0.20 Z
1.20 MAX
DETAIL A
16-038-FGB-2
EG137
12-2-97 lv
40
Am29SL800C
P R E L I M I N A R Y
Trademarks
Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
Am29SL800C
41
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AM29SL800CB100FC | AMD | 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 1.8 Volt-only Super Low Voltage Flash Memory | 获取价格 | |
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AM29SL800CB100FD | SPANSION | Flash, 1MX8, 100ns, PDSO48, REVERSE, TSOP-48 | 获取价格 | |
AM29SL800CB100FF | SPANSION | Flash, 1MX8, 100ns, PDSO48, REVERSE, TSOP-48 | 获取价格 | |
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AM29SL800CB100FIB | AMD | 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 1.8 Volt-only Super Low Voltage Flash Memory | 获取价格 |
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