AM29SL800DT120EF
更新时间:2024-09-18 06:44:29
品牌:AMD
描述:8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 1.8 Volt-only Super Low Voltage Flash Memory
AM29SL800DT120EF 概述
8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 1.8 Volt-only Super Low Voltage Flash Memory 8兆位( 1一M× 8位/ 512的K× 16位) CMOS 1.8伏只超低电压闪存
AM29SL800DT120EF 数据手册
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Data Sheet
The following document contains information on Spansion memory products. Although the document
is marked with the name of the company that originally developed the specification, Spansion will
continue to offer these products to existing customers.
Continuity of Specifications
There is no change to this data sheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal data sheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
Spansion continues to support existing part numbers beginning with “Am” and “MBM”. To order these
products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local sales office for additional information about Spansion memory solutions.
Publication Number 27546 Revision A Amendment 6 Issue Date January 23, 2007
THIS PAGE LEFT INTENTIONALLY BLANK.
DATA SHEET
Am29SL800D
8 Megabit (1 M x 8-Bit/512 K x 16-Bit)
CMOS 1.8 Volt-only Super Low Voltage Flash Memory
DISTINCTIVE CHARACTERISTICS
Single Power Supply Operation
Embedded Algorithms
— 1.65 to 2.2 V for read, program, and erase
operations
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Ideal for battery-powered applications
Manufactured on 0.23 µm Process Technology
— Compatible with 0.32 µm Am29SL800C device
High Performance
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
Minimum 1,000,000 Erase Cycle Guarantee Per
Sector
— Access times as fast as 90 ns
20-Year Data Retention at 125°C
Package Option
Ultra Low Power Consumption (Typical Values at
5 MHz)
— 48-pin TSOP
— 0.2 µA Automatic Sleep Mode current
— 0.2 µA standby mode current
— 5 mA read current
— 48-ball FBGA
Compatibility with JEDEC Standards
— 15 mA program/erase current
— Pinout and software compatible with single-
power supply Flash
Flexible Sector Architecture
— Superior inadvertent write protection
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
fifteen 64 Kbyte sectors (byte mode)
Data# Polling and Toggle Bits
— One 8 Kword, two 4 Kword, one 16 Kword, and
fifteen 32 Kword sectors (word mode)
— Provides a software method of detecting program
or erase operation completion
— Supports full chip erase
Ready/Busy# Pin (RY/BY#)
— Sector Protection Features:
— Provides a hardware method of detecting
program or erase cycle completion
A hardware method of locking a sector to prevent any
program or erase operations within that sector
Erase Suspend/Erase Resume
Sectors can be locked in-system or via programming
equipment
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
Hardware Reset Pin (RESET#)
Unlock Bypass Program Command
— Hardware method to reset the device to reading
array data
— Reduces overall programming time when issuing
multiple program command sequences
Top or Bottom Boot Block Configurations
Available
Publication# 27546 Rev: A Amendment/6
Issue Date: January 23, 2007
This Data Sheet states AMD’s current specifications regarding the Products described herein. This Data Sheet may
be revised by subsequent versions or modifications due to changes in technical specifications.
D A T A S H E E T
GENERAL DESCRIPTION
The Am29SL800D is an 8 Mbit, 1.8 V volt-only Flash-
memory organized as 1,048,576 bytes or 524,288
words. The device is offered in 48-pin TSOP and 48-
ball FBGA packages. The word-wide data (x16)
appears on DQ15–DQ0; the byte-wide (x8) data
appears on DQ7–DQ0. This device is designed to be
programmed and erased in-system with a single 1.8
During erase, the device automatically times the erase
pulse widths and verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data
or accept another command.
volt V supply. No V is for write or erase operations.
CC
PP
The device can also be programmed in standard
EPROM programmers.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
The standard device offers access times of 90, 100,
120, and 150 ns, allowing high speed microprocessors
to operate without wait states. To eliminate bus conten-
tion, the device has separate chip enable (CE#), write
enable (WE#) and output enable (OE#) controls.
Hardware data protection measures include a low
V
detector that automatically inhibits write opera-
CC
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of
memory. This can be achieved in-system or via pro-
gramming equipment.
The device requires only a single 1.8 volt power
supply for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Com-
mands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin. The Unlock Bypass mode facili-
tates faster programming times by requiring only two
write cycles to program data instead of four.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the automatic sleep mode.
The system can also place the device into the standby
mode. Power consumption is greatly reduced in both
these modes.
Device erasure occurs by executing the erase
command sequence. This initiates the Embedded
Erase algorithm—an internal algorithm that automati-
cally preprograms the array (if it is not already
programmed) before executing the erase operation.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunneling.
The data is programmed using hot electron injection.
2
Am29SL800D
27546A6 January 23, 2007
D A T A S H E E T
TABLE OF CONTENTS
Table 6. Write Operation Status ..................................................... 23
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 24
Figure 7. Maximum Negative Overshoot Waveform ...................... 24
Figure 8. Maximum Positive Overshoot Waveform........................ 24
Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 24
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 7. CMOS Compatible ........................................................... 25
Zero Power Flash ................................................................... 26
Figure 9. ICC1 Current vs. Time (Showing Active and Automatic
Product Selector Guide . . . . . . . . . . . . . . . . . . . . .4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . .5
Special Handling Instructions for FBGA Packages .................. 5
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . .6
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Ordering Information . . . . . . . . . . . . . . . . . . . . . . .7
Standard Products .................................................................... 7
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 8
Table 1. Am29SL800D Device Bus Operations ................................8
Word/Byte Configuration .......................................................... 8
Requirements for Reading Array Data ..................................... 8
Writing Commands/Command Sequences .............................. 8
Program and Erase Operation Status ...................................... 9
Standby Mode .......................................................................... 9
Automatic Sleep Mode ............................................................. 9
RESET#: Hardware Reset Pin ................................................. 9
Output Disable Mode .............................................................. 10
Table 2. Am29SL800DT Top Boot Block Sector Address Table .....10
Table 3. Am29SL800DB Bottom Boot Block Sector Address Table 11
Autoselect Mode ..................................................................... 12
Table 4. Am29SL800D Autoselect Code (High Voltage Method) ...12
Sector Protection/Unprotection ............................................... 12
Temporary Sector Unprotect .................................................. 12
Figure 1. In-System Sector Protect/Unprotect Algorithms .............. 13
Figure 2. Temporary Sector Unprotect Operation........................... 14
Hardware Data Protection ...................................................... 14
Command Definitions . . . . . . . . . . . . . . . . . . . . . 14
Reading Array Data ................................................................ 14
Reset Command ..................................................................... 14
Autoselect Command Sequence ............................................ 15
Word/Byte Program Command Sequence ............................. 15
Figure 3. Program Operation .......................................................... 16
Chip Erase Command Sequence ........................................... 16
Sector Erase Command Sequence ........................................ 16
Erase Suspend/Erase Resume Commands ........................... 17
Figure 4. Erase Operation............................................................... 18
Table 5. Am29SL800D Command Definitions ................................19
Write Operation Status . . . . . . . . . . . . . . . . . . . . .20
DQ7: Data# Polling ................................................................. 20
Figure 5. Data# Polling Algorithm ................................................... 20
RY/BY#: Ready/Busy# ........................................................... 21
DQ6: Toggle Bit I .................................................................... 21
DQ2: Toggle Bit II ................................................................... 21
Reading Toggle Bits DQ6/DQ2 .............................................. 21
Figure 6. Toggle Bit Algorithm......................................................... 22
DQ5: Exceeded Timing Limits ................................................ 22
DQ3: Sector Erase Timer ....................................................... 22
Sleep Currents).............................................................................. 26
Figure 10. Typical ICC1 vs. Frequency ........................................... 26
Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 11. Test Setup..................................................................... 27
Table 8. Test Specifications ........................................................... 27
Table 9. Key to Switching Waveforms ........................................... 27
Figure 12. Input Waveforms and Measurement Levels ................. 27
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 10. Read Operations ............................................................ 28
Figure 13. Read Operations Timings ............................................. 28
Table 11. Hardware Reset (RESET#) ............................................ 29
Figure 14. RESET# Timings .......................................................... 29
Table 12. Word/Byte Configuration (BYTE#) ................................. 30
Figure 15. BYTE# Timings for Read Operations............................ 30
Figure 16. BYTE# Timings for Write Operations............................ 30
Table 13. Erase/Program Operations ............................................ 31
Figure 17. Program Operation Timings.......................................... 32
Figure 18. Chip/Sector Erase Operation Timings .......................... 33
Figure 19. Data# Polling Timings (During Embedded Algorithms). 34
Figure 20. Toggle Bit Timings (During Embedded Algorithms)...... 34
Figure 21. DQ2 vs. DQ6................................................................. 35
Table 14. Temporary Sector Unprotect .......................................... 35
Figure 22. Temporary Sector Unprotect Timing Diagram .............. 35
Figure 23. Sector Protect/Unprotect Timing Diagram .................... 36
Table 15. Alternate CE# Controlled Erase/Program Operations .... 37
Figure 24. Alternate CE# Controlled Write Operation Timings ...... 38
Erase and Programming Performance . . . . . . . 39
Table 16. Erase and Programming Performance ........................... 39
Table 17. Latchup Characteristics .................................................. 39
Table 18. TSOP Pin Capacitance .................................................. 39
Table 19. Data Retention ............................................................... 39
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 40
TS 048—48-Pin Standard TSOP ............................................ 40
FBA048—48-Ball Fine-Pitch Ball Grid Array (FBGA)
8.15 X 6.15 mm Package ....................................................... 41
FBC048—48-Ball Fine-Pitch Ball Grid Array (FBGA)
9 x 8 mm Package .................................................................. 42
VBK048—48 Ball Fine-Pitch Ball Grid Array (FBGA) ............. 43
8.15 x 6.15 mm .......................................................................43
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 44
January 23, 2007 27546A6
Am29SL800D
3
D A T A S H E E T
PRODUCT SELECTOR GUIDE
Family Part Number
Am29SL800D
90
Speed Options
(Note 2)
90 (Note 2)
90 (Note 2)
30
100
120
120
120
50
150
150
150
65
Max access time, ns (tACC
)
100
100
35
Max CE# access time, ns (tCE
)
Max OE# access time, ns (tOE
)
Notes:
1. See “AC Characteristics” for full specifications.
2. VCC min. = 1.7 V
BLOCK DIAGRAM
DQ0–DQ15 (A-1)
RY/BY#
VCC
Sector Switches
VSS
Erase Voltage
Generator
Input/Output
Buffers
RESET#
State
Control
WE#
BYTE#
Command
Register
PGM Voltage
Generator
Data
Latch
Chip Enable
Output Enable
Logic
STB
CE#
OE#
Y-Decoder
Y-Gating
STB
VCC Detector
Timer
Cell Matrix
X-Decoder
A0–A18
4
Am29SL800D
27546A6 January 23, 2007
D A T A S H E E T
CONNECTION DIAGRAMS
A15
A14
A13
A12
A11
A10
A9
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
A8
NC
NC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
WE#
RESET#
NC
Standard TSOP
NC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
48-Ball FBGA
(Top View, Balls Facing Down)
A6
B6
C6
D6
E6
F6
G6
H6
A13
A12
A14
A15
A16
BYTE# DQ15/A-1 VSS
A5
A9
B5
A8
C5
D5
E5
F5
G5
H5
A10
A11
DQ7
DQ14
DQ13
DQ6
A4
B4
C4
D4
E4
F4
G4
H4
WE# RESET#
NC
NC
DQ5
DQ12
VCC
DQ4
A3
B3
C3
D3
E3
F3
G3
H3
RY/BY#
NC
A18
NC
DQ2
DQ10
DQ11
DQ3
A2
A7
B2
C2
A6
D2
A5
E2
F2
G2
H2
A17
DQ0
DQ8
DQ9
DQ1
A1
A3
B1
A4
C1
A2
D1
A1
E1
A0
F1
G1
H1
CE#
OE#
VSS
and/or data integrity may be compromised if the
package body is exposed to temperatures about 150°C
for prolonged periods of time.
Special Handling Instructions for FBGA
Packages
Special handling is required for Flash Memory products
in molded packages (TSOP and BGA). The package
January 23, 2007 27546A6
Am29SL800D
5
D A T A S H E E T
PIN CONFIGURATION
LOGIC SYMBOL
A0–A18
= 19 addresses
19
DQ0–DQ14 = 15 data inputs/outputs
A0–A18
16 or 8
DQ15/A-1
=
DQ15 (data input/output, word mode),
A-1 (LSB address input, byte mode)
DQ0–DQ15
(A-1)
BYTE#
CE#
=
=
=
=
=
=
=
=
=
Selects 8-bit or 16-bit mode
Chip enable
CE#
OE#
OE#
Output enable
WE#
WE#
Write enable
RESET#
BYTE#
RESET#
RY/BY#
Hardware reset pin, active low
Ready/Busy# output
1.65–2.2 V single power supply
Device ground
RY/BY#
V
V
CC
SS
NC
Pin not connected internally
6
Am29SL800D
27546A6 January 23, 2007
D A T A S H E E T
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combi-
nation) is formed by a combination of the elements below.
Am29SL800D
T
-100
E
C
TEMPERATURE RANGE
C
D
I
=
=
=
=
Commercial (0°C to +70°C)
Commercial (0°C to +70°C) with Pb-free package
Industrial (–40°C to +85°C)
Industrial (–40°C to +85°C) with Pb-free package
F
PACKAGE TYPE
E
=
48-Pin Thin Small Outline Package (TSOP)
Standard Pinout (TS 048)
VU
=
48-ball Fine-Pitch Ball Grid Array (FBGA)
0.80mm pitch, 8.15 x 6.15 mm package (VBK048)
WA
WC
=
=
48-Ball Fine-Pitch Ball Grid Array (FBGA)
0.80 mm pitch, 8.15 x 6.15 mm package (FBA048)
48-Ball Fine-Pitch Ball Grid Array (FBGA)
0.80 mm pitch, 9 x 8 mm package (FBC048)
SPEED OPTION
See Product Selector Guide and Valid Combinations
BOOT CODE SECTOR ARCHITECTURE
T
B
=
=
Top Sector
Bottom Sector
DEVICE NUMBER/DESCRIPTION
Am29SL800D
8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS Flash Memory
1.8 Volt-only Read, Program, and Erase
Valid Combinations
Valid Combinations for FBGA Packages
Order Number Package Marking
WAC, WAD A800DT90U,
Valid Combinations list configurations planned to be supported in vol-
ume for this device. Consult the local AMD sales office to confirm
availability of specific valid combinations and to check on newly re-
leased combinations.
WAI, WAF A800DB90U
AM29SL800DT90,
AM29SL800DB90
WCC, WCD, A800DT90P,
WCI, WCF A800DB90P
Valid Combinations for TSOP Packages
AM29SL800DT90,
AM29SL800DB90
WAC, WAD A800DT10U,
WAI, WAF A800DB10U
AM29SL800DT100,
AM29SL800DB100
AM29SL800DT100,
WCC, WCD, A800DT10P,
WCI, WCF A800DB10P
AM29SL800DB100
EC, EI, ED, EF
AM29SL800DT120,
WAC, WAD A800DT12U,
WAI, WAF A800DB12U
C, I,
D, F
AM29SL800DB120
AM29SL800DT120,
AM29SL800DB120
AM29SL800DT150,
AM29SL800DB150
WCC, WCD, A800DT12P,
WCI, WCF A800DB12P
WAC, WAD A800DT15U,
WAI, WAF A800DB15U
AM29SL800DT150,
AM29SL800DB150
WCC, WCD, A800DT15P,
WCI, WCF A800DB15P
A800DT12V
VUF
Am29SL800DT120
A800DB12V
January 23, 2007 27546A6
Am29SL800D
7
D A T A S H E E T
tion needed to execute the command. The contents of
DEVICE BUS OPERATIONS
the register serve as inputs to the internal state
machine. The state machine outputs dictate the func-
tion of the device. Table 1 lists the device bus
operations, the inputs and control levels they require,
and the resulting output. The following subsections
describe each of these operations in further detail.
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is composed of latches that store the
commands, along with the address and data informa-
Table 1. Am29SL800D Device Bus Operations
DQ8–DQ15
BYTE#
Addresses
(Note 1)
DQ0–
DQ7
BYTE#
= VIH
Operation
CE#
L
OE# WE# RESET#
= VIL
Read
Write
L
H
L
H
H
AIN
AIN
DOUT
DIN
DOUT
DIN
DQ8–DQ14 = High-Z,
DQ15 = A-1
L
H
VCC
0.2 V
±
VCC ±
0.2 V
Standby
X
X
X
High-Z
High-Z
High-Z
Output Disable
Reset
L
H
X
H
X
H
L
X
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
X
Sector Address, A6 =
L, A1 = H,
Sector Protect (Note)
L
H
L
VID
DIN
X
X
A0 = L
Sector Address, A6 =
H, A1 = H,
Sector Unprotect (Note)
L
H
X
L
VID
VID
DIN
DIN
X
X
A0 = L
Temporary Sector Unprotect
X
X
AIN
DIN
High-Z
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 10 ± 1.0 V, X = Don’t Care, AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Addresses are A18:A0 in word mode (BYTE# = VIH), A18:A-1 in byte mode (BYTE# = VIL).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment.
ensures that no spurious alteration of the memory
Word/Byte Configuration
content occurs during the power transition. No
The BYTE# pin controls whether the device data I/O
command is necessary in this mode to obtain array
pins DQ15–DQ0 operate in the byte or word configura-
data. Standard microprocessor read cycles that assert
tion. If the BYTE# pin is set at logic ‘1’, the device is in
valid addresses on the device address inputs produce
word configuration, DQ15–DQ0 are active and con-
valid data on the device data outputs. The device
trolled by CE# and OE#.
remains enabled for read access until the command
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE# and OE#. The data I/O
pins DQ8–DQ14 are tri-stated, and the DQ15 pin is
used as an input for the LSB (A-1) address function.
register contents are altered.
See Reading Array Data‚ on page 14 for more informa-
tion. Refer to the AC Read Operations table for timing
specifications and to Figure 13, on page 28 for the
timing diagram. I
in the DC Characteristics table
CC1
represents the active current specification for reading
array data.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V . CE# is the power
control and selects the device. OE# is the output
control and gates array data to the output pins. WE#
Writing Commands/Command Sequences
To write a command or command sequence (which
includes programming data to the device and erasing
sectors of memory), the system must drive WE# and
IL
should remain at V . The BYTE# pin determines
IH
whether the device outputs array data in words or
bytes.
CE# to V , and OE# to V .
IL
IH
For program operations, the BYTE# pin determines
whether the device accepts program data in bytes or
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
8
Am29SL800D
27546A6 January 23, 2007
D A T A S H E E T
words. Refer to Word/Byte Configuration‚ on page 8
for more information.
The device also enters the standby mode when the
RESET# pin is driven low. Refer to the next section,
RESET#: Hardware Reset Pin.
The device features an Unlock Bypass mode to facili-
tate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are
required to program a word or byte, instead of four. The
Word/Byte Program Command Sequence‚ on page 15
has details on programming data to the device using
both standard and Unlock Bypass command
sequences.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
I
in Table 7 on page 25 represents the standby
CC3
current specification.
Automatic Sleep Mode
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Tables 2 and 3 indicate the
address space that each sector occupies. A “sector
address” consists of the address bits required to
uniquely select a sector. The Command Definitions‚ on
page 14 has details on erasing a sector or the entire
chip, or suspending/resuming the erase operation.
The automatic sleep mode minimizes Flash device
energy consumption. The device automatically enables
this mode when addresses remain stable for t
+ 50
ACC
ns. The automatic sleep mode is independent of the
CE#, WE#, and OE# control signals. Standard address
access timings provide new data when addresses are
changed. While in sleep mode, output data is latched
and always available to the system. I
page 25 represents the automatic sleep mode current
specification.
in Table 7 on
After the system writes the autoselect command
sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the
internal register (which is separate from the memory
array) on DQ7–DQ0. Standard read cycle timings apply
in this mode. Refer to the Autoselect Mode‚ on page 12
and Autoselect Command Sequence‚ on page 15 sec-
tions for more information.
CC4
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of reset-
ting the device to reading array data. When the
RESET# pin is driven low for at least a period of t , the
RP
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state
machine to reading array data. The operation that was
interrupted should be reinitiated once the device is
ready to accept another command sequence, to
ensure data integrity.
I
in the DC Characteristics table represents the
CC2
active current specification for the write mode. AC
Characteristics‚ on page 28 contains timing specifica-
tion tables and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status
Current is reduced for the duration of the RESET#
bits on DQ7–DQ0. Standard read cycle timings and I
CC
pulse. When RESET# is held at V
0.2 V, the device
read specifications apply. Refer to Write Operation
Status‚ on page 20 for more information, and to “AC
Characteristics” for timing diagrams.
SS
draws CMOS standby current (I
). If RESET# is held
CC4
at V but not within V
0.2 V, the standby current is
IL
SS
greater.
Standby Mode
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, inde-
pendent of the OE# input.
If RESET# is asserted during a program or erase oper-
ation, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at V ± 0.2 V.
(Note that this is a more restricted voltage range than
time of t
(during Embedded Algorithms). The
CC
READY
system can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
V .) If CE# and RESET# are held at V , but not within
IH
IH
V
± 0.2 V, the device will be in the standby mode, but
CC
the standby current will be greater. The device requires
standard access time (t ) for read access when the
within a time of t
(not during Embedded Algo-
CE
READY
device is in either of these standby modes, before it is
ready to read data.
rithms). The system can read data t
after the
RH
RESET# pin returns to V .
IH
January 23, 2007 27546A6
Am29SL800D
9
D A T A S H E E T
Refer to the Table 10 on page 28 for RESET# parame-
Output Disable Mode
When the OE# input is at V , output from the device is
disabled. The output pins are placed in the high imped-
ance state.
ters and to Figure 14, on page 29 for the timing
diagram.
IH
Table 2. Am29SL800DT Top Boot Block Sector Address Table
Address Range (in hexadecimal)
Sector Size
(Kbytes/
(x8)
(x16)
Sector
SA0
A18
0
A17
0
A16
0
A15
0
A14
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
A13
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
A12
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
Kwords)
Address Range
Address Range
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
32/16
8/4
00000h–0FFFFh
10000h–1FFFFh
20000h–2FFFFh
30000h–3FFFFh
40000h–4FFFFh
50000h–5FFFFh
60000h–6FFFFh
70000h–7FFFFh
80000h–8FFFFh
90000h–9FFFFh
A0000h–AFFFFh
B0000h–BFFFFh
C0000h–CFFFFh
D0000h–DFFFFh
E0000h–EFFFFh
F0000h–F7FFFh
F8000h–F9FFFh
FA000h–FBFFFh
FC000h–FFFFFh
00000h–07FFFh
08000h–0FFFFh
10000h–17FFFh
18000h–1FFFFh
20000h–27FFFh
28000h–2FFFFh
30000h–37FFFh
38000h–3FFFFh
40000h–47FFFh
48000h–4FFFFh
50000h–57FFFh
58000h–5FFFFh
60000h–67FFFh
68000h–6FFFFh
70000h–77FFFh
78000h–7BFFFh
7C000h–7CFFFh
7D000h–7DFFFh
7E000h–7FFFFh
SA1
0
0
0
1
SA2
0
0
1
0
SA3
0
0
1
1
SA4
0
1
0
0
SA5
0
1
0
1
SA6
0
1
1
0
SA7
0
1
1
1
SA8
1
0
0
0
SA9
1
0
0
1
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
8/4
1
1
1
1
1
1
X
16/8
10
Am29SL800D
27546A6 January 23, 2007
D A T A S H E E T
Table 3. Am29SL800DB Bottom Boot Block Sector Address Table
Address Range (in hexadecimal)
Sector Size
(Kbytes/
(x8)
(x16)
Sector
SA0
A18
0
A17
0
A16
0
A15
0
A14
0
A13
0
A12
X
0
Kwords)
Address Range
Address Range
16/8
8/4
00000h–03FFFh
04000h–05FFFh
06000h–07FFFh
08000h–0FFFFh
10000h–1FFFFh
20000h–2FFFFh
30000h–3FFFFh
40000h–4FFFFh
50000h–5FFFFh
60000h–6FFFFh
70000h–7FFFFh
80000h–8FFFFh
90000h–9FFFFh
A0000h–AFFFFh
B0000h–BFFFFh
C0000h–CFFFFh
D0000h–DFFFFh
E0000h–EFFFFh
F0000h–FFFFFh
00000h–01FFFh
02000h–02FFFh
03000h–03FFFh
04000h–07FFFh
08000h–0FFFFh
10000h–17FFFh
18000h–1FFFFh
20000h–27FFFh
28000h–2FFFFh
30000h–37FFFh
38000h–3FFFFh
40000h–47FFFh
48000h–4FFFFh
50000h–57FFFh
58000h–5FFFFh
60000h–67FFFh
68000h–6FFFFh
70000h–77FFFh
78000h–7FFFFh
SA1
0
0
0
0
0
1
SA2
0
0
0
0
0
1
1
8/4
SA3
0
0
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
32/16
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
SA4
0
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA5
0
0
1
0
SA6
0
0
1
1
SA7
0
1
0
0
SA8
0
1
0
1
SA9
0
1
1
0
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Note for Tables 2 and 3: Address range is A18:A-1 in byte mode and A18:A0 in word mode. See “Word/Byte Configuration” section for more
information.
January 23, 2007 27546A6
Am29SL800D
11
D A T A S H E E T
address must appear on the appropriate highest order
Autoselect Mode
address bits (see Table 2 on page 10 and Table 3 on
page 11). Table 4 shows the remaining address bits
that are don’t care. When all necessary bits have been
set as required, the programming equipment may then
read the corresponding identifier code on DQ7–DQ0.
The autoselect mode provides manufacturer and
device identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equipment
to automatically match a device to be programmed with
its corresponding programming algorithm. However,
the autoselect codes can also be accessed in-system
through the command register.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 5 on page 19.
This method does not require VID. See Command
Definitions‚ on page 14 for details on using the autose-
lect mode.
When using programming equipment, the autoselect
mode requires VID on address pin A9. Address pins
A6, A1, and A0 must be as shown in Table 4. In addi-
tion, when verifying sector protection, the sector
Table 4. Am29SL800D Autoselect Code (High Voltage Method)
A18 A11
to to
WE# A12 A10
A8
to
A7
A5
to
A2
DQ8
to
DQ15
DQ7
to
DQ0
Description
Mode
CE#
L
OE#
A9
A6
A1
A0
Manufacturer ID: AMD
L
L
H
H
X
X
VID
X
X
L
X
X
L
L
X
01h
Device ID:
Am29SL800D
(Top Boot Block)
Word
L
22h
EAh
X
X
VID
L
L
L
L
H
H
Byte
Word
Byte
L
L
L
L
L
L
H
H
H
X
22h
X
EAh
6Bh
Device ID:
Am29SL800D
(Bottom Boot Block)
X
X
X
VID
X
X
X
X
6Bh
X
01h (protected)
Sector Protection Verification
L
L
H
SA
VID
L
H
L
00h
(unprotected)
X
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.
Sector Protection/Unprotection
The hardware sector protection feature disables both
program and erase operations in any sector. The hard-
ware sector unprotection feature re-enables both
program and erase operations in previously protected
sectors. Sector protection/unprotection can be imple-
mented via two methods.
It is possible to determine whether a sector is protected
or unprotected. See Autoselect Mode‚ on page 12 for
details.
Temporary Sector Unprotect
This feature allows temporary unprotection of previ-
ously protected sectors to change data in-system. The
Sector Unprotect mode is activated by setting the
Sector Protection/ Unprotection requires V on the
ID
RESET# pin only, and can be implemented either in-
system or via programming equipment. Figure 1, on
page 13 shows the algorithms and Figure 23, on page
36 shows the timing diagram. For sector unprotect, all
unprotected sectors must first be protected prior to the
first sector unprotect write cycle.
RESET# pin to V . During this mode, formerly pro-
ID
tected sectors can be programmed or erased by
selecting the sector addresses. Once V is removed
ID
from the RESET# pin, all the previously protected
sectors are protected again. Figure 2, on page 14
shows the algorithm, and Figure 22, on page 35 shows
the timing diagrams, for this feature.
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
12
Am29SL800D
27546A6 January 23, 2007
D A T A S H E E T
START
START
Protect all sectors:
The indicated portion
of the sector protect
algorithm must be
performed for all
unprotected sectors
prior to issuing the
first sector
PLSCNT = 1
PLSCNT = 1
RESET# = V
ID
RESET# = V
Wait 1 ms
ID
Wait 1 ms
unprotect address
No
First Write
Cycle = 60h?
No
First Write
Cycle = 60h?
Temporary Sector
Unprotect Mode
Temporary Sector
Unprotect Mode
Yes
Yes
Set up sector
address
No
All sectors
protected?
Sector Protect:
Write 60h to sector
address with
A6 = 0, A1 = 1,
A0 = 0
Yes
Set up first sector
address
Sector Unprotect:
Write 60h to sector
address with
Wait 150 µs
A6 = 1, A1 = 1,
A0 = 0
Verify Sector
Protect: Write 40h
to sector address
with A6 = 0,
Reset
PLSCNT = 1
Increment
PLSCNT
Wait 15 ms
A1 = 1, A0 = 0
Verify Sector
Unprotect: Write
40h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Read from
sector address
with A6 = 0,
A1 = 1, A0 = 0
Increment
PLSCNT
No
No
PLSCNT
= 25?
Read from
sector address
with A6 = 1,
Data = 01h?
Yes
A1 = 1, A0 = 0
No
Yes
Set up
next sector
address
Yes
No
PLSCNT
= 1000?
Protect another
sector?
Data = 00h?
Yes
Device failed
No
Yes
Remove V
from RESET#
ID
No
Last sector
verified?
Device failed
Write reset
command
Yes
Remove V
from RESET#
ID
Sector Unprotect
Algorithm
Sector Protect
Algorithm
Sector Protect
complete
Write reset
command
Sector Unprotect
complete
Figure 1. In-System Sector Protect/Unprotect Algorithms
January 23, 2007 27546A6
Am29SL800D
13
D A T A S H E E T
for command definitions). In addition, the following
hardware data protection measures prevent accidental
erasure or programming, which might otherwise be
START
caused by spurious system level signals during V
CC
power-up and power-down transitions, or from system
noise.
RESET# = VID
(Note 1)
Low V
Write Inhibit
CC
When V
is less than V
, the device does not
LKO
CC
Perform Erase or
Program Operations
accept any write cycles. This protects data during V
CC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
RESET# = VIH
device resets. Subsequent writes are ignored until V
CC
is greater than V
. The system must provide the
LKO
proper signals to the control pins to prevent uninten-
tional writes when V is greater than V
.
CC
LKO
Temporary Sector
Unprotect Completed
(Note 2)
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Notes:
Write cycles are inhibited by holding any one of OE# =
1. All protected sectors unprotected.
V , CE# = V or WE# = V . To initiate a write cycle,
IL
IH
IH
2. All previously protected sectors are protected once again.
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
Figure 2. Temporary Sector Unprotect Operation
If WE# = CE# = V and OE# = V during power up, the
IL
IH
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 5 on page 19
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The
system can read array data using the standard read
timings, except that if it reads at an address within
erase-suspended sectors, the device outputs status
data. After completing a programming operation in the
Erase Suspend mode, the system may once again
read array data with the same exception. See Erase
Suspend/Erase Resume Commands‚ on page 17 for
more information on this mode.
COMMAND DEFINITIONS
Writing specific address and data commands or
sequences into the command register initiates device
operations. Table 5 on page 19 defines the valid reg-
ister command sequences. Writing incorrect address
and data values or writing them in the improper
sequence may place the device in an unknown state. A
reset command is then required to return the device to
reading array data.
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
AC Characteristics‚ on page 28 section.
The system must issue the reset command to re-
enable the device for reading array data if DQ5 goes
high, or while in the autoselect mode. See Reset Com-
mand‚ on page 14.
See also Requirements for Reading Array Data‚ on
page 8 for more information. Table 10 on page 28 pro-
vides the read parameters, and Figure 12, on page 27
shows the timing diagram.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or
Embedded Erase algorithm.
Reset Command
Writing the reset command to the device resets the
device to reading array data. Address bits are don’t
care for this command.
14
Am29SL800D
27546A6 January 23, 2007
D A T A S H E E T
The reset command may be written between the
The program address and data are written next, which
in turn initiate the Embedded Program algorithm. The
system is not required to provide further controls or tim-
ings. The device automatically generates the program
pulses and verifies the programmed cell margin.
Table 5 on page 19 shows the address and data
requirements for the byte program command
sequence.
sequence cycles in an erase command sequence
before erasing begins. This resets the device to reading
array data. Once erasure begins, however, the device
ignores reset commands until the operation is
complete.
The reset command may be written between the
sequence cycles in a program command sequence
before programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and
addresses are no longer latched. The system can
determine the status of the program operation by using
DQ7, DQ6, or RY/BY#. See Table on page 20 for infor-
mation on these status bits.
The reset command may be written between the
sequence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
Any commands written to the device during the
Embedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program-
ming operation. The Byte Program command
sequence should be reinitiated once the device has
reset to reading array data, to ensure data integrity.
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to
reading array data (also applies during Erase
Suspend).
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempting to do so may halt
the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indicate the operation was suc-
cessful. However, a succeeding read will show that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
Table 5 on page 19 shows the address and data
requirements. This method is an alternative to that
shown in Table 4 on page 12, which is intended for
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to
program bytes or words to the device faster than using
the standard program command sequence. The unlock
bypass command sequence is initiated by first writing
two unlock cycles. This is followed by a third write cycle
containing the unlock bypass command, 20h. The
device then enters the unlock bypass mode. A two-
cycle unlock bypass program command sequence is all
that is required to program in this mode. The first cycle
in this sequence contains the unlock bypass program
command, A0h; the second cycle contains the program
address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program
command sequence, resulting in faster total program-
ming time. Table 5 on page 19 shows the requirements
for the command sequence.
PROM programmers and requires V on address bit
A9.
ID
The autoselect command sequence is initiated by
writing two unlock cycles, followed by the autoselect
command. The device then enters the autoselect
mode, and the system may read at any address any
number of times, without initiating another command
sequence. A read cycle at address XX00h retrieves the
manufacturer code. A read cycle at address 01h in
word mode (or 02h in byte mode) returns the device
code. A read cycle containing a sector address (SA)
and the address 02h in word mode (or 04h in byte
mode) returns 01h if that sector is protected, or 00h if it
is unprotected. Refer to Table 2 on page 10 and Table 3
on page 11 for valid sector addresses.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
During the unlock bypass mode, only the Unlock
Bypass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset
command sequence. The first cycle must contain the
data 90h; the second cycle the data 00h. Addresses
are don’t cares. The device then returns to reading
array data.
Word/Byte Program Command Sequence
The system may program the device by word or byte,
depending on the state of the BYTE# pin. Program-
ming is a four-bus-cycle operation. The program
command sequence is initiated by writing two unlock
write cycles, followed by the program set-up command.
January 23, 2007 27546A6
Am29SL800D
15
D A T A S H E E T
Figure 3 illustrates the algorithm for the program oper-
ation. See Table 13 on page 31 for parameters, and to
Figure 17, on page 32 for timing diagrams.
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Table 5 on
page 19 shows the address and data requirements for
the chip erase command sequence.
START
Write Program
Command Sequence
Data Poll
from System
Embedded
Program
algorithm
in progress
Any commands written to the chip during the
Embedded Erase algorithm are ignored. Note that a
hardware reset during the chip erase operation imme-
diately terminates the operation. The Chip Erase
command sequence should be reinitiated once the
device has returned to reading array data, to ensure
data integrity.
Verify Data?
No
Yes
The system can determine the status of the erase oper-
ation by using DQ7, DQ6, DQ2, or RY/BY#. See “Write
Operation Status” for information on these status bits.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched.
No
Increment Address
Last Address?
Yes
Programming
Completed
Figure 4, on page 18 illustrates the algorithm for the
erase operation. See Table 13 on page 28 for parame-
ters, and to Figure 10, on page 26 for timing diagrams.
1. See Table 5 for program command sequence.
Sector Erase Command Sequence
Figure 3. Program Operation
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command. Table 5 shows the address and data
requirements for the sector erase command sequence.
The device does not require the system to preprogram
the memory prior to erase. The Embedded Erase algo-
rithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or
timings during these operations.
After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of
sectors may be from one sector to all sectors. The time
between these additional cycles must be less than 50
µs, otherwise the last address and command might not
be accepted, and erasure may begin. It is recom-
mended that processor interrupts be disabled during
16
Am29SL800D
27546A6 January 23, 2007
D A T A S H E E T
this time to ensure all commands are accepted. The
time-out period and suspends the erase operation.
Addresses are “don’t-cares” when writing the Erase
Suspend command.
interrupts can be re-enabled after the last Sector Erase
command is written. If the time between additional
sector erase commands can be assumed to be less
than 50 µs, the system need not monitor DQ3. Any
command other than Sector Erase or Erase
Suspend during the time-out period resets the
device to reading array data. The system must
rewrite the command sequence and any additional
sector addresses and commands.
When the Erase Suspend command is written during a
sector erase operation, the device requires a maximum
of 20 µs to suspend the erase operation. However,
when the Erase Suspend command is written during
the sector erase time-out, the device immediately ter-
minates the time-out period and suspends the erase
operation.
The system can monitor DQ3 to determine if the sector
erase timer has timed out. (See DQ3: Sector Erase
Timer‚ on page 22.) The time-out begins from the rising
edge of the final WE# pulse in the command sequence.
After the erase operation has been suspended, the
system can read array data from or program data to
any sector not selected for erasure. (The device “erase
suspends” all sectors selected for erasure.) Normal
read and write timings and command definitions apply.
Reading at any address within erase-suspended
sectors produces status data on DQ7–DQ0. The
system can use DQ7, or DQ6 and DQ2 together, to
determine if a sector is actively erasing or is erase-sus-
pended. See Write Operation Status‚ on page 20 for
information on these status bits.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands
are ignored. Note that a hardware reset during the
sector erase operation immediately terminates the
operation. The Sector Erase command sequence
should be reinitiated once the device has returned to
reading array data, to ensure data integrity.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched. The system can determine the
status of the erase operation by using DQ7, DQ6, DQ2,
or RY/BY#. (Refer to Write Operation Status‚ on
page 20 for information on these status bits.)
After an erase-suspended program operation is com-
plete, the system can once again read array data within
non-suspended sectors. The system can determine
the status of the program operation using the DQ7 or
DQ6 status bits, just as in the standard program oper-
ation. See Write Operation Status‚ on page 20 for
more information.
Figure 4, on page 18 illustrates the algorithm for the
erase operation. Refer to the Table 16 on page 39for
parameters, and to Figure 18, on page 33 for timing
diagrams.
The system may also write the autoselect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to
the Erase Suspend mode, and is ready for another
valid operation. See Autoselect Command Sequence‚
on page 15 for more information.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to
interrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the 50 µs time-out period
during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program algo-
rithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
The system must write the Erase Resume command
(address bits are don’t care) to exit the erase suspend
mode and continue the sector erase operation. Further
writes of the Resume command are ignored. Another
Erase Suspend command can be written after the
device has resumed erasing.
January 23, 2007 27546A6
Am29SL800D
17
D A T A S H E E T
START
Write Erase
Command Sequence
Data Poll
from System
Embedded
Erase
algorithm
in progress
No
Data = FFh?
Yes
Erasure Completed
Notes:
1. See Table 5 for erase command sequence.
2. See “DQ3: Sector Erase Timer” for more information.
Figure 4. Erase Operation
18
Am29SL800D
27546A6 January 23, 2007
D A T A S H E E T
Table 5. Am29SL800D Command Definitions
Bus Cycles (Notes 2-5)
Command
Sequence
(Note 1)
First
Second
Third
Addr
Fourth
Fifth
Sixth
Addr Data Addr Data
Data Addr Data Addr Data Addr Data
Read (Note 6)
Reset (Note 7)
1
1
RA
XXX
555
RD
F0
Word
Byte
Word
Byte
Word
Byte
2AA
555
2AA
555
2AA
555
555
AAA
555
Manufacturer ID
4
4
4
AA
AA
AA
55
55
55
90
90
90
X00
01
AAA
555
X01
X02
X01
X02
22EA
EA
Device ID,
Top Boot Block
AAA
555
AAA
555
226B
6B
Device ID,
Bottom Boot Block
AAA
AAA
XX00
XX01
00
(SA)
X02
Word
Byte
Word
Byte
555
AAA
555
2AA
555
2AA
555
555
AAA
555
Sector Protect Verify
(Note 9)
4
4
AA
AA
55
55
90
90
(SA)
X04
01
TBD
TBD
TBD
TBD
X03
X04
PA
Extension
AAA
AAA
Word
Byte
Word
Byte
555
AAA
555
2AA
555
2AA
555
PA
555
AAA
555
Program
Unlock Bypass
4
3
AA
AA
55
55
A0
20
PD
AAA
XXX
XXX
555
AAA
Unlock Bypass Program (Note 10)
Unlock Bypass Reset (Note 11)
2
2
A0
90
PD
00
XXX
2AA
555
2AA
555
Word
555
AAA
555
555
AAA
555
2AA
555
2AA
555
555
Chip Erase
6
6
AA
AA
55
55
80
80
AA
AA
55
55
10
30
Byte
Word
Byte
AAA
555
AAA
Sector Erase
SA
AAA
XXX
XXX
AAA
AAA
Erase Suspend (Note 12)
Erase Resume (Note 13)
1
1
B0
30
Legend:
X = Don’t care
PD = Data to be programmed at location PA. Data latches on the
rising edge of WE# or CE# pulse, whichever happens first.
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A18–A12 uniquely select any sector.
PA = Address of the memory location to be programmed. Addresses
latch on the falling edge of the WE# or CE# pulse, whichever
happens later.
Notes:
1. See Table 1 for description of bus operations.
9. The data is 00h for an unprotected sector and 01h for a protected
sector. See “Autoselect Command Sequence” for more
information.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles are
write operations.
10. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
4. Data bits DQ15–DQ8 are don’t cares for unlock and command
cycles.
11. The Unlock Bypass Reset command is required to return to
reading array data when the device is in the unlock bypass mode.
5. Address bits A18–A11 are don’t cares for unlock and command
cycles, unless SA or PA required.
12. The system may read and program in non-erasing sectors, or enter the
autoselect mode, when in the Erase Suspend mode. The Erase Suspend
command is valid only during a sector erase operation.
6. No unlock or command cycles required when reading array data,
unless SA or PA required.
13. The Erase Resume command is valid only during the Erase Suspend
mode.
7. The Reset command is required to return to reading array data
when device is in the autoselect mode, or if DQ5 goes high (while
the device is providing status data).
8. The fourth cycle of the autoselect command sequence is a read
cycle.
January 23, 2007 27546A6
Am29SL800D
19
D A T A S H E E T
WRITE OPERATION STATUS
The device provides several bits to determine the
status of a write operation: DQ2, DQ3, DQ5, DQ6,
DQ7, and RY/BY#. Table 6 and the following subsec-
tions describe the functions of these bits. DQ7,
RY/BY#, and DQ6 each offer a method for determining
whether a program or erase operation is complete or in
progress. These three bits are discussed first.
page 34, Data# Polling Timings (During Embedded
Algorithms), illustrates this.
Table 6 on page 23 shows the outputs for Data# Polling
on DQ7. Figure 5 shows the Data# Polling algorithm.
START
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host
system whether an Embedded Algorithm is in progress
or completed, or whether the device is in Erase Sus-
pend. Data# Polling is valid after the rising edge of the
final WE# pulse in the program or erase command
sequence.
Read DQ7–DQ0
Addr = VA
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum pro-
grammed to DQ7. This DQ7 status also applies to
programming during Erase Suspend. When the
Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for
approximately 1 µs, then the device returns to reading
array data.
Yes
DQ7 = Data?
No
No
DQ5 = 1?
Yes
During the Embedded Erase algorithm, Data# Polling
produces a 0 on DQ7. When the Embedded Erase
algorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a 1 on DQ7.
This is analogous to the complement/true datum output
described for the Embedded Program algorithm: the
erase function changes all the bits in a sector to 1; prior
to this, the device outputs the complement, or 0. The
system must provide an address within any of the
sectors selected for erasure to read valid status infor-
mation on DQ7.
Read DQ7–DQ0
Addr = VA
Yes
DQ7 = Data?
No
PASS
FAIL
After an erase command sequence is written, if all
sectors selected for erasing are protected, Data#
Polling on DQ7 is active for approximately 100 µs, then
the device returns to reading array data. If not all
selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores
the selected sectors that are protected.
Notes:
1. VA = Valid address for programming. During a sector erase
operation, a valid address is an address within any sector
selected for erasure. During chip erase, a valid address is any
non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may
change simultaneously with DQ5.
When the system detects DQ7 has changed from the
complement to true data, it can read valid data at DQ7–
DQ0 on the following read cycles. This is because DQ7
may change asynchronously with DQ0–DQ6 while
Output Enable (OE#) is asserted low. Figure 19, on
Figure 5. Data# Polling Algorithm
20
Am29SL800D
27546A6 January 23, 2007
D A T A S H E E T
Table 6 on page 23 shows the outputs for Toggle Bit I
RY/BY#: Ready/Busy#
on DQ6. Figure 6, on page 22 shows the toggle bit
algorithm. Figure 20, on page 34 shows the toggle bit
timing diagrams. Figure 21, on page 35 shows the dif-
ferences between DQ2 and DQ6 in graphical form. See
also the subsection on DQ2: Toggle Bit II.
The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output,
several RY/BY# pins can be tied together in parallel
DQ2: Toggle Bit II
with a pull-up resistor to V
.
CC
The Toggle Bit II on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence. The device toggles DQ2 with
each OE# or CE# read cycle.
If the output is low (Busy), the device is actively erasing
or programming. (This includes programming in the
Erase Suspend mode.) If the output is high (Ready),
the device is ready to read array data (including during
the Erase Suspend mode), or is in the standby mode.
Table 6 on page 23 shows the outputs for RY/BY#.
Figure 14, on page 29, Figure 17, on page 32, and
Figure 18, on page 33 shows RY/BY# for reset, pro-
gram, and erase operations, respectively.
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. But DQ2 cannot distinguish whether the sector is
actively erasing or is erase-suspended. DQ6, by com-
parison, indicates whether the device is actively
erasing, or is in Erase Suspend, but cannot distinguish
which sectors are selected for erasure. Thus, both
status bits are required for sector and mode informa-
tion. Refer to Table 6 on page 23 to compare outputs
for DQ2 and DQ6.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or erase
operation), and during the sector erase time-out.
Figure 6, on page 22 shows the toggle bit algorithm in
flowchart form, and the section DQ2: Toggle Bit II
explains the algorithm. See also the DQ6: Toggle Bit I
subsection. Figure 20, on page 34 shows the toggle bit
timing diagram. Figure 21, on page 35 shows the differ-
ences between DQ2 and DQ6 in graphical form.
During an Embedded Program or Erase algorithm
operation, successive read cycles to any address
cause DQ6 to toggle (The system may use either OE#
or CE# to control the read cycles). When the operation
is complete, DQ6 stops toggling.
Reading Toggle Bits DQ6/DQ2
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 toggles
for approximately 100 µs, then returns to reading array
data. If not all selected sectors are protected, the
Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are
protected.
Refer to Figure 6, on page 22 for the following discus-
sion. Whenever the system initially begins reading
toggle bit status, it must read DQ7–DQ0 at least twice
in a row to determine whether a toggle bit is toggling.
Typically, the system would note and store the value of
the toggle bit after the first read. After the second read,
the system would compare the new value of the toggle
bit with the first. If the toggle bit is not toggling, the
device has completed the program or erase operation.
The system can read array data on DQ7–DQ0 on the
following read cycle.
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is erase-
suspended. When the device is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on DQ7: Data# Polling).
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is
high (see the section on DQ5). If it is, the system
should then determine again whether the toggle bit is
toggling, since the toggle bit may have stopped tog-
gling just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the
device did not completed the operation successfully,
and the system must write the reset command to return
to reading array data.
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 µs after the program
command sequence is written, then returns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded
Program algorithm is complete.
January 23, 2007 27546A6
Am29SL800D
21
D A T A S H E E T
The remaining scenario is that the system initially
DQ5: Exceeded Timing Limits
determines that the toggle bit is toggling and DQ5 has
not gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles,
determining the status as described in the previous
paragraph. Alternatively, it may choose to perform
other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to
determine the status of the operation (top of Figure 6).
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a 1. This is a failure
condition that indicates the program or erase cycle was
not successfully completed.
The DQ5 failure condition may appear if the system
tries to program a 1 to a location that is previously pro-
grammed to 0. Only an erase operation can change
a 0 back to a 1. Under this condition, the device halts
the operation, and when the operation has exceeded
the timing limits, DQ5 produces a 1.
START
Under both these conditions, the system must issue the
reset command to return the device to reading array
data.
Read DQ7–DQ0
Read DQ7–DQ0
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If addi-
tional sectors are selected for erasure, the entire time-
out also applies after each additional sector erase com-
mand. When the time-out is complete, DQ3 switches
from 0 to 1. If the time between additional sector erase
commands from the system can be assumed to be less
than 50 µs, the system need not monitor DQ3. See also
Sector Erase Command Sequence‚ on page 16.
No
Toggle Bit
= Toggle?
Yes
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Twice
After the sector erase command sequence is written,
the system should read the status on DQ7 (Data#
Polling) or DQ6 (Toggle Bit I) to ensure the device has
accepted the command sequence, and then read DQ3.
If DQ3 is 1, the internally controlled erase cycle has
begun; all further commands (other than Erase Sus-
pend) are ignored until the erase operation is complete.
If DQ3 is 0, the device will accept additional sector
erase commands. To ensure the command has been
accepted, the system software should check the status
of DQ3 prior to and following each subsequent sector
erase command. If DQ3 is high on the second status
check, the last command might not have been
accepted. Figure 6 shows the outputs for DQ3.
Toggle Bit
= Toggle?
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Notes:
1. Read toggle bit twice to determine whether or not it is toggling.
See text.
2. Recheck toggle bit because it may stop toggling as DQ5 changes
to “1”. See text
Figure 6. Toggle Bit Algorithm
22
Am29SL800D
27546A6 January 23, 2007
D A T A S H E E T
Table 6. Write Operation Status
DQ7
DQ5
DQ2
Operation
(Note 2)
DQ6
(Note 1)
DQ3
N/A
1
(Note 2)
RY/BY#
Embedded Program Algorithm
Embedded Erase Algorithm
DQ7#
0
Toggle
Toggle
0
0
No toggle
Toggle
0
0
Standard
Mode
Reading within Erase
Suspended Sector
1
No toggle
0
N/A
Toggle
1
Erase
Suspend
Mode
Reading within Non-Erase
Suspended Sector
Data
Data
Data
0
Data
N/A
Data
N/A
1
0
Erase-Suspend-Program
DQ7#
Toggle
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See “DQ5:
Exceeded Timing Limits for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
January 23, 2007 27546A6
Am29SL800D
23
D A T A S H E E T
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages...............................–65°C to +150°C
20 ns
20 ns
Ambient Temperature
with Power Applied............................–65°C to +125°C
0.0 V
Voltage with Respect to Ground
–0.5 V
–2.0 V
V
(Note 1)................................–0.5 V to +2.5 V
CC
A9, OE#,
and RESET# (Note 2)................–0.5 V to +11.0 V
20 ns
Figure 7. Maximum Negative Overshoot Waveform
All other pins (Note 1)........... –0.5 V to V +0.5 V
CC
Output Short Circuit Current (Note 3) ............. 100 mA
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage
transitions, input or I/O pins may overshoot VSS to –2.0 V for
periods of up to 20 ns. See Figure 7. Maximum DC voltage on
input or I/O pins is VCC +0.5 V. During voltage transitions, input
or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns.
See Figure 8.
20 ns
VCC
+2.0 V
2. Minimum DC input voltage on pins A9, OE#, and RESET# is –0.5
V. During voltage transitions, A9, OE#, and RESET# may
overshoot VSS to –2.0 V for periods of up to 20 ns. See Maximum
DC input voltage on pin A9 is +11.0 V which may overshoot to
12.5 V for periods up to 20 ns.
VCC
+0.5 V
2.0 V
20 ns
20 ns
3. No more than one output may be shorted to ground at a time.
Duration of the short circuit should not be greater than one
second.
Figure 8. Maximum Positive Overshoot Waveform
Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other conditions
above those indicated in the operational sections of this data sheet is
not implied. Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (T ).......................0°C to +70°C
A
Industrial (I) Devices
Ambient Temperature (T )...................–40°C to +85°C
A
V
V
V
Supply Voltages
CC
CC
CC
, 90ns speed option ...................+1.70 V to +2.2 V
, All other speed options............+1.65 V to +2.2 V
Operating ranges define those limits between which the functionality
of the device is guaranteed.
24
Am29SL800D
27546A6 January 23, 2007
D A T A S H E E T
DC CHARACTERISTICS
Table 7. CMOS Compatible
Parameter
Description
Test Conditions
Min
Typ
Max
±1.0
35
Unit
µA
V
V
IN = VSS to VCC
,
ILI
Input Load Current
CC = VCC max
ILIT
ILO
A9 Input Load Current
Output Leakage Current
VCC = VCC max; A9 = 11.0 V
µA
V
V
OUT = VSS to VCC
,
±1.0
µA
CC = VCC max
5 MHz
1 MHz
5 MHz
1 MHz
5
1
5
1
10
3
CE# = VIL, OE# = VIH,
Byte Mode
VCC Active Read Current
(Notes 1, 2)
ICC1
mA
10
3
CE# = VIL, OE# = VIH,
Word Mode
VCC Active Write Current
(Notes 2, 3, 5)
ICC2
CE# = VIL, OE# = VIH
15
30
mA
ICC3
ICC4
VCC Standby Current (Note 2)
VCC Reset Current (Note 2)
CE#, RESET# = VCC ± 0.2 V
RESET# = VSS ± 0.2 V
VIH = VCC ± 0.2 V;
0.2
0.2
5
5
µA
µA
Automatic Sleep Mode
(Notes 2, 3)
ICC5
0.2
5
µA
V
IL = VSS ± 0.2 V
VIL
VIH
Input Low Voltage
Input High Voltage
–0.5
0.3 x VCC
VCC + 0.3
V
V
0.7 x VCC
Voltage for Autoselect and
Temporary Sector Unprotect
VID
V
CC = 2.0 V
9.0
11.0
V
VOL1
VOL2
VOH1
VOH2
VLKO
I
OL = 2.0 mA, VCC = VCC min
IOL = 100 μA, VCC = VCC min
OH = –2.0 mA, VCC = VCC min
IOH = –100 μA, VCC = VCC min
0.25
0.1
V
V
V
V
V
Output Low Voltage
I
0.85 x VCC
VCC–0.1
1.2
Output High Voltage
Low VCC Lock-Out Voltage (Note 4)
1.5
Notes:
1. The ICC current listed is typically less than 1 mA/MHz, with OE# at VIH. Typical VCC is 2.0 V.
2. The maximum ICC specifications are tested with VCC = VCCmax.
3. ICC active while Embedded Erase or Embedded Program is in progress.
4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 50 ns.
5. Not 100% tested.
January 23, 2007 27546A6
Am29SL800D
25
D A T A S H E E T
DC CHARACTERISTICS (Continued)
Zero Power Flash
20
15
10
5
0
0
500
1000
1500
2000
2500
3000
3500
4000
Time in ns
Note: Addresses are switching at 1 MHz
Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
10
8
6
2.2 V
4
1.8 V
2
0
1
2
3
4
5
Frequency in MHz
Note: T = 25 °C
Figure 10. Typical ICC1 vs. Frequency
26
Am29SL800D
27546A6 January 23, 2007
D A T A S H E E T
TEST CONDITIONS
Table 8. Test Specifications
-90,
-120,
Test Condition
-100
-150
Unit
Output Load
1 TTL gate
Device
Under
Test
Output Load Capacitance, CL
(including jig capacitance)
30
100
pF
Input Rise and Fall Times
Input Pulse Levels
5
0.0–2.0
ns
V
C
L
Input timing measurement
reference levels
1.0
1.0
V
V
Output timing measurement
reference levels
Figure 11. Test Setup
Table 9. Key to Switching Waveforms
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
2.0 V
0.0 V
1.0 V
1.0 V
Input
Measurement Level
Output
Figure 12. Input Waveforms and Measurement Levels
January 23, 2007 27546A6
Am29SL800D
27
D A T A S H E E T
AC CHARACTERISTICS
Table 10. Read Operations
Parameter
Speed Options
JEDEC
Std
Description
Test Setup
-90
-100
-120
-150
Unit
90
(Note 3)
tAVAV
tRC
Read Cycle Time (Note 1)
Address to Output Delay
Chip Enable to Output Delay
Min
Max
Max
100
120
150
ns
CE# = VIL
OE# = VIL
90
(Note 3)
tAVQV
tACC
100
120
150
ns
ns
90
(Note 3)
tELQV
tCE
OE# = VIL
100
35
120
50
150
65
tGLQV
tEHQZ
tGHQZ
tOE
tDF
tDF
Output Enable to Output Delay
Chip Enable to Output High Z (Note 1)
Output Enable to Output High Z (Note 1)
Max
Max
Max
Min
30
ns
ns
ns
ns
16
16
0
Read
Output Enable
Hold Time (Note 1)
tOEH
Toggle and
Data# Polling
Min
Min
30
0
ns
ns
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First (Note 1)
tAXQX
tOH
Notes:
1. Not 100% tested.
2. See Figure 11, on page 27 and Table 8 on page 27 for test specifications
3. VCC min. = 1.7V
.
t
RC
Addresses Stable
Addresses
CE#
t
ACC
t
D
t
OE
OE#
t
OEH
WE#
t
CE
t
O
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0 V
Figure 13. Read Operations Timings
28
Am29SL800D
27546A6 January 23, 2007
D A T A S H E E T
AC CHARACTERISTICS
Table 11. Hardware Reset (RESET#)
Parameter
JEDEC
Std
Description
All Speed Options
Unit
RESET# Pin Low (During Embedded Algorithms) to Read or Write
tREADY
Max
20
µs
(see Note)
RESET# Pin Low (NOT During Embedded Algorithms) to Read or
Write (see Note)
tREADY
Max
500
ns
tRP
tRH
tRPD
tRB
RESET# Pulse Width
RESET# High Time Before Read (see Note)
RESET# Low to Standby Mode
RY/BY# Recovery Time
Min
Min
Min
Min
500
200
20
ns
ns
µs
ns
0
Note: Not 100% tested.
RY/BY#
CE#, OE#
RESET#
t
RH
t
RP
t
Ready
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
t
Ready
RY/BY#
t
RB
CE#, OE#
RESET#
t
RP
Figure 14. RESET# Timings
January 23, 2007 27546A6
Am29SL800D
29
D A T A S H E E T
AC CHARACTERISTICS
Table 12. Word/Byte Configuration (BYTE#)
Parameter
Speed Options
JEDEC
Std
Description
CE# to BYTE# Switching Low or High
BYTE# Switching Low to Output HIGH Z
BYTE# Switching High to Output Active
-90
-100
-120
-150
Unit
ns
t
ELFL/tELFH
Max
Max
Min
10
tFLQZ
tFHQV
50
90
50
60
60
ns
100
120
150
ns
CE#
OE#
BYTE#
tELFL
Data Output
(DQ0–DQ14)
Data
BYTE#
Switching
from word
to byte
DQ0–DQ14
Output
mode
Address
Input
DQ15
Output
DQ15/A-1
tFLQZ
tELFH
BYTE#
BYTE#
Switching
from byte to
word mode
Data
Data Output
(DQ0–DQ14)
DQ0–DQ14
DQ15/A-1
Output
Address
Input
DQ15
Output
tFHQV
Figure 15. BYTE# Timings for Read Operations
CE#
The falling edge of the last WE# signal
WE#
BYTE#
tSET
(tAS
)
tHOLD (tAH
)
Note: Refer to the Erase/Program Operations table for tAS and tAH specifications.
Figure 16. BYTE# Timings for Write Operations
30
Am29SL800D
27546A6 January 23, 2007
D A T A S H E E T
AC CHARACTERISTICS
Table 13. Erase/Program Operations
Parameter
Speed Options
JEDEC
tAVAV
Std
tWC
tAS
Description
Write Cycle Time (Note 1)
-90
-100
-120
-150
Unit
ns
Min
Min
Min
Min
Min
Min
90
100
120
150
tAVWL
tWLAX
tDVWH
tWHDX
Address Setup Time
Address Hold Time
Data Setup Time
0
ns
tAH
45
45
50
50
60
60
70
70
ns
tDS
ns
tDH
tOES
Data Hold Time
0
0
ns
Output Enable Setup Time
ns
Read Recovery Time Before Write
(OE# High to WE# Low)
tGHWL
tGHWL
Min
0
ns
tELWL
tWHEH
tWLWH
tWHWL
tCS
tCH
CE# Setup Time
Min
Min
Min
Min
Typ
Typ
Typ
Min
Min
Max
0
0
ns
ns
ns
ns
CE# Hold Time
tWP
Write Pulse Width
Write Pulse Width High
45
50
60
70
tWPH
30
5
Byte
tWHWH1
tWHWH1 Programming Operation (Notes 1, 2)
µs
Word
7
tWHWH2
tWHWH2 Sector Erase Operation (Notes 1, 2)
0.7
50
0
sec
µs
tVCS
tRB
VCC Setup Time
Recovery Time from RY/BY#
Program/Erase Valid to RY/BY# Delay
ns
tBUSY
200
ns
Notes:
1. Not 100% tested.
2. See the Table 16 on page 39 for more information.
January 23, 2007 27546A6
Am29SL800D
31
D A T A S H E E T
AC CHARACTERISTICS
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
t
t
AS
WC
Addresses
555h
PA
PA
PA
t
AH
CE#
OE#
t
CH
t
WHWH1
t
WP
WE#
t
WPH
t
CS
t
DS
t
D
PD
DOUT
A0h
Status
Data
t
t
RB
BUSY
RY/BY#
V
CC
t
VCS
Notes:
1. PA = program address, PD = program data, DOUT is the true data at the program address.
2. Illustration shows device in word mode.
Figure 17. Program Operation Timings
32
Am29SL800D
27546A6 January 23, 2007
D A T A S H E E T
AC CHARACTERISTICS
Erase Command Sequence (last two cycles)
Read Status Data
VA
t
AS
tWC
VA
Addresses
CE#
2AAh
SA
555h for chip erase
t
AH
t
t
CH
OE#
t
W
WE#
t
t
WP
WHWH
t
CS
t
D
D
In
Data
Complete
55h
30h
Progress
10 for Chip Erase
t
t
RB
BUSY
RY/BY#
t
VCS
V
CC
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).
2. Illustration shows device in word mode.
Figure 18. Chip/Sector Erase Operation Timings
January 23, 2007 27546A6
Am29SL800D
33
D A T A S H E E T
AC CHARACTERISTICS
tRC
VA
Addresses
VA
VA
t
ACC
t
CE
CE#
t
CH
t
OE
OE#
WE#
t
tDF
OH
OEH
t
High Z
High Z
DQ7
Valid Data
Complement
Complement
Status Data
True
DQ0–DQ6
Valid Data
Status Data
True
tBUSY
RY/BY#
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
Figure 19. Data# Polling Timings (During Embedded Algorithms)
tRC
Addresses
CE#
VA
ACC
VA
VA
VA
t
t
CE
t
CH
t
OE
OE#
WE#
t
tDF
OH
OEH
t
High Z
DQ6/DQ2
RY/BY#
Valid Status
(first read)
Valid Status
Valid Status
Valid Data
(second read)
(stops toggling)
t
BUS
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and
array data read cycle.
Figure 20. Toggle Bit Timings (During Embedded Algorithms)
34
Am29SL800D
27546A6 January 23, 2007
D A T A S H E E T
AC CHARACTERISTICS
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Complete
Erase
Erase Suspend
Read
Erase
Suspend
Program
WE#
Erase
Erase Suspend
Read
DQ6
DQ2
Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an erase-suspended sector.
Figure 21. DQ2 vs. DQ6
Table 14. Temporary Sector Unprotect
Parameter
JEDEC
Std
Description
VID Rise and Fall Time
All Speed Options
Unit
tVIDR
Min
Min
500
ns
RESET# Setup Time for Temporary Sector
Unprotect
tRSP
4
µs
10 V
RESET#
0 or 1.8 V
0 or 1.8 V
tVIDR
t
VIDR
Program or Erase Command Sequence
CE#
WE#
tRSP
RY/BY#
Figure 22. Temporary Sector Unprotect Timing Diagram
January 23, 2007 27546A6
Am29SL800D
35
D A T A S H E E T
AC CHARACTERISTICS
V
ID
IH
V
RESET#
SA, A6,
A1, A0
Valid*
Sector Protect/Unprotect
60h 60h
Valid*
Valid*
Status
Verify
40h
Data
Sector Protect: 150 µs
Sector Unprotect: 15 ms
1 µs
CE#
WE#
OE#
* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
Figure 23. Sector Protect/Unprotect Timing Diagram
36
Am29SL800D
27546A6 January 23, 2007
D A T A S H E E T
AC CHARACTERISTICS
Table 15. Alternate CE# Controlled Erase/Program Operations
Parameter
JEDEC
Speed Options
Std
tWC
tAS
Description
-90
-100
-120
-150
Unit
ns
tAVAV
tAVEL
tELAX
tDVEH
tEHDX
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
Min
Min
Min
Min
Min
Min
90
100
120
150
0
ns
tAH
45
45
50
50
60
60
70
70
ns
tDS
ns
tDH
tOES
Data Hold Time
0
0
ns
Output Enable Setup Time
ns
Read Recovery Time Before Write
(OE# High to WE# Low)
tGHEL
tGHEL
Min
0
ns
tWLEL
tEHWH
tELEH
tEHEL
tWS
tWH
tCP
WE# Setup Time
WE# Hold Time
Min
Min
Min
Min
Typ
Typ
Typ
0
0
ns
ns
ns
ns
CE# Pulse Width
CE# Pulse Width High
45
50
60
70
tCPH
30
5
Byte
Programming Operation
(Notes 1, 2)
tWHWH1
tWHWH1
µs
Word
7
tWHWH2
tWHWH2 Sector Erase Operation (Notes 1, 2)
0.7
sec
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
January 23, 2007 27546A6
Am29SL800D
37
D A T A S H E E T
AC CHARACTERISTICS
555 for program
PA for program
2AA for erase
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
t
t
WC
AS
t
AH
t
WH
WE#
OE#
t
GHEL
t
WHWH1 or 2
t
t
CP
CE#
Data
t
WS
CPH
DS
t
BUS
t
t
DH
DQ7#
DOUT
t
RH
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. PA = program address, PD = program data, DQ7# = complement of the data written, DOUT = data written
2. Figure indicates the last two bus cycles of command sequence.
3. Word mode address used as an example.
Figure 24. Alternate CE# Controlled Write Operation Timings
38
Am29SL800D
27546A6 January 23, 2007
D A T A S H E E T
ERASE AND PROGRAMMING PERFORMANCE
Table 16. Erase and Programming Performance
Parameter
Typ (Note 1)
Max (Note 2)
Unit
s
Comments
Sector Erase Time
Chip Erase Time
0.7
14
5
15
Excludes00hprogrammingprior
to erasure (Note 4)
s
Byte Programming Time
150
210
16
µs
µs
s
Word Programming Time
Byte Mode
Word Mode
7
Excludes system level overhead
(Note 5)
5.3
3.7
Chip Programming Time
(Note 3)
11
s
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 2.0 V VCC, 1,000,000 cycles. Additionally, programming typicals
assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 1.8 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster
than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 5 for further
information on command definitions.
6. The device has a minimum guaranteed erase and program cycle endurance of 1,000,000 cycles.
Table 17. Latchup Characteristics
Description
Min
Max
Input voltage with respect to VSS on all pins except I/O pins
(including A9, OE#, and RESET#)
–1.0 V
11.0 V
Input voltage with respect to VSS on all I/O pins
–0.5 V
VCC + 0.5 V
+100 mA
V
CC Current
–100 mA
Includes all pins except VCC. Test conditions: VCC = 1.8 V, one pin at a time.
Table 18. TSOP Pin Capacitance
Parameter Symbol
Parameter Description
Input Capacitance
Test Setup
VIN = 0
Typ
6
Max
7.5
12
Unit
pF
CIN
COUT
CIN2
Output Capacitance
Control Pin Capacitance
VOUT = 0
VIN = 0
8.5
7.5
pF
9
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
Table 19. Data Retention
Parameter
Test Conditions
150°C
Min
10
Unit
Years
Years
Minimum Pattern Data Retention Time
125°C
20
January 23, 2007 27546A6
Am29SL800D
39
D A T A S H E E T
PHYSICAL DIMENSIONS
TS 048—48-Pin Standard TSOP
Dwg rev AA; 10/99
40
Am29SL800D
27546A6 January 23, 2007
D A T A S H E E T
PHYSICAL DIMENSIONS
FBA048—48-Ball Fine-Pitch Ball Grid Array (FBGA)
8.15 X 6.15 mm Package
Dwg rev AF; 10/99
January 23, 2007 27546A6
Am29SL800D
41
D A T A S H E E T
PHYSICAL DIMENSIONS
FBC048—48-Ball Fine-Pitch Ball Grid Array (FBGA)
9 x 8 mm Package
Dwg rev AF; 10/99
42
Am29SL800D
27546A6 January 23, 2007
D A T A S H E E T
PHYSICAL DIMENSIONS
VBK048—48 Ball Fine-Pitch Ball Grid Array (FBGA)
8.15 x 6.15 mm
0.10 (4X)
D1
A
D
6
5
4
3
2
1
7
e
SE
E1
E
H
G
F
E
D
C
B
A
INDEX MARK
6
B
A1 CORNER
PIN A1
7
fb
SD
CORNER
10
f
f
0.08M
0.15M
C
C
TOP VIEW
A
B
BOTTOM VIEW
0.10C
0.08C
A2
A
SEATING PLANE
C
A1
SIDE VIEW
NOTES
:
PACKAGE
JEDEC
VBK 048
1.DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
2.ALL DIMENSIONS ARE IN MILLIMETERS
N/A
.
8.15 mm
x
6.15 mm NOM
3.BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEP
AS NOTED).
T
PACKAG
E
SYMBOL
MIN
NOM
MAX
NOTE
4.
e
REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
A2
D
---
---
1.00 OVERALL THICKNESS
--- BALL HEIGHT
0.76 BODY THICKNESS
BODY SIZE
5.SYMBOL "MD" IS THE BALL ARTORWIXM SIZE IN THE
"D" DIRECTION.
0.18
0.62
---
SYMBOL "ME" IS THE BALL NCOMLAUTMRIX SIZE IN THE
"E" DIRECTION.
---
8.15 BSC.
6.15 BSC.
5.60 BSC.
4.00 BSC.
8
N IS THE TOTAL NUMBER OF SOLDER BALLS.
E
BODY SIZE
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN PLANE PARALLEL TO DATUM C.
D1
E1
MD
ME
N
BALL FOOTPRINT
BALL FOOTPRINT
A
SD AND SE ARE MEASURED WITH RETSOPEDCATTUMS
AND AND DEFINE THE POSOIFTITOHNE CENTER
A
B
ROW MATRIX SIZE
ROW MATRIX SIZE
TOTAL BALL COUNT
0.43 BALL DIAMETER
BALL PITCH
D
DIRECTION
DIRECTION
SOLDER BALL IN THE OUTER ROW.
6
E
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
THE OUTER ROW PARALLEL TO THEEDDOIRMENSION,
RESPECTIVELY, SD OR SE = 0.000.
48
fb
e
0.35
---
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, SD OR SE = e/2
0.80 BSC.
0.40 BSC.
---
SD
/
SE
SOLDER BALL PLACEMEN
T
8.NOT USED.
DEPOPULATED SOLDER BALLS
9."+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3338 \ 16-038.25b
January 23, 2007 27546A6
Am29SL800D
43
D A T A S H E E T
REVISION SUMMARY
Revision A (February 4, 2003)
Initial release.
Revision A+4 (April 27, 2005)
Added VBK048 package.
Added Colophon.
Updated Trademark.
Revision A+1 (March 17, 2003)
Ordering Information
Revision A+5 (February 17, 2006)
Global
Corrected typo in table.
Corrected typo to OPNs.
Removed Reverse TSOP throughout.
Revision A+2 (June 10, 2004)
Ordering Information
Revision A6 (January 23, 2007)
Erase and Program Operations table
Added Pb-free package OPNs.
Changed t
to a maximum specification.
BUSY
Revision A+3 (October 27, 2004)
Updated V values
CC
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limita-
tion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as con-
templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion Inc. will not be liable
to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating
conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign
Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au-
thorization by the respective government entity will be required for export of those products.
Trademarks
Copyright © 2003–2005 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trade-
marks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are
for identification purposes only and may be trademarks of their respective companies.
Copyright © 2006–2007 Spansion Inc. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, HD-SIM, and combinations
thereof are trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners.
44
Am29SL800D
27546A6 January 23, 2007
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