AM41PDS3224DB40IS [AMD]
32 Megabit (2 M x 16-Bit) CMOS 1.8 Volt-only, Simultaneous Operation, Page Mode Flash Memory and 4 Mbit (512 K x 8-Bit/256 K x 16-Bit) Static RAM; 32兆位(2M ×16位) CMOS 1.8伏只,同时操作页面模式闪存和4兆位( 512K的×8位/ 256千×16位),静态RAM型号: | AM41PDS3224DB40IS |
厂家: | AMD |
描述: | 32 Megabit (2 M x 16-Bit) CMOS 1.8 Volt-only, Simultaneous Operation, Page Mode Flash Memory and 4 Mbit (512 K x 8-Bit/256 K x 16-Bit) Static RAM |
文件: | 总59页 (文件大小:1001K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Am41PDS3224D
Data Sheet
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Publication Number 26085 Revision A Amendment +1 Issue Date May 13, 2003
PRELIMINARY
Am41PDS3224D
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
Am29PDS322D 32 Megabit (2 M x 16-Bit) CMOS 1.8 Volt-only, Simultaneous Operation,
Page Mode Flash Memory and 4 Mbit (512 K x 8-Bit/256 K x 16-Bit) Static RAM
DISTINCTIVE CHARACTERISTICS
—
—
—
—
24 mA active read current at 10 MHz for initial page read
0.5 mA active read current at 10 MHz for intra-page read
1 mA active read current at 20 MHz for intra-page read
200 nA in standby or automatic sleep mode
MCP Features
■ Power supply voltage of 1.8 to 2.2 volt
■ High performance
—
Access time as fast as 100 ns flash, 70 ns SRAM
■ Minimum 1 million write cycles guaranteed per sector
■ 20 year data retention at 125°C
■ Package
—
73-Ball FBGA
—
Reliable operation for the life of the system
■ Operating Temperature
SOFTWARE FEATURES
—
–40°C to +85°C
■ Data Management Software (DMS)
Flash Memory Features
—
AMD-supplied software manages data programming,
enabling EEPROM emulation
ARCHITECTURAL ADVANTAGES
—
Eases historical sector erase flash limitations
■ Simultaneous Read/Write operations
■ Erase Suspend/Erase Resume
■ Data# Polling and Toggle Bits
■ Unlock Bypass Program command
—
Data can be continuously read from one bank while
executing erase/program functions in other bank.
Zero latency between read and write operations
—
—
Reduces overall programming time when issuing multiple
program command sequences
■ Page Mode Operation
—
4 word page allows fast asynchronous reads
HARDWARE FEATURES
■ Dual Bank architecture
■ Any combination of sectors can be erased
■ Ready/Busy# output (RY/BY#)
■ Hardware reset pin (RESET#)
■ WP#/ACC input pin
—
One 4 Mbit bank and one 28 Mbit bank
■ SecSi (Secured Silicon) Sector: Extra 64 KByte sector
—
Factory locked and identifiable: 16 byte Electronic Serial
Number available for factory secure, random ID; verifiable
as factory locked through autoselect function. ExpressFlash
option allows entire sector to be available for
—
Write protect (WP#) function allows protection of two
outermost boot sectors, regardless of sector protect status
Acceleration (ACC) function accelerates program timing
factory-secured data
—
—
Customer lockable: Can be read, programmed, or erased
just like other sectors. Once locked, data cannot be changed
■ Sector protection
—
Hardware method of locking a sector, either in-system or
using programming equipment, to prevent any program or
erase operation within that sector
■ Zero Power Operation
Sophisticated power management circuits reduce power
consumed during inactive periods to nearly zero.
—
—
Temporary Sector Unprotect allows changing data in
protected sectors in-system
■ Top or bottom boot block
■ Manufactured on 0.23 µm process technology
■ Compatible with JEDEC standards
SRAM Features
■ Power dissipation
—
Pinout and software compatible with single-power-supply
flash standard
—
—
Operating: 2 mA typical
Standby: 0.5 µA typical
PERFORMANCE CHARACTERISTICS
■ CE1s# and CE2s Chip Select
■ High performance
■ Power down features using CE1s# and CE2s
■ Data retention supply voltage: 1.0 to 2.2 volt
■ Byte data control: LB#s (DQ7–DQ0), UB#s (DQ15–DQ8)
—
Random access time of 100 ns at 1.8 V to 2.2 V VCC
■ Ultra low power consumption (typical values)
2.5 mA active read current at 1 MHz for initial page read
—
Publication# 26085 Rev: A Amendment/+1
Issue Date: May 13, 2002
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Refer to AMD’s Website (www.amd.com) for the latest information.
P R E L I M I N A R Y
GENERAL DESCRIPTION
The Am29PDS322D is a 32 Mbit, 1.8 V-only Flash
memory organized as 2,097,152 words of 16 bits
each. The device is designed to be programmed in
system with standard system 1.8 V VCC supply. This
device can also be reprogrammed in standard
EPROM programmers.
other flash sector, or may permanently lock their own
code there.
DMS (Data Management Software) allows systems
to easily take advantage of the advanced architecture
of the simultaneous read/write product line by allowing
removal of EEPROM devices. DMS will also allow the
system software to be simplified, as it will perform all
functions necessary to modify data in file structures,
as opposed to single-byte modifications. To write or
update a particular piece of data (a phone number or
configuration data, for example), the user only needs
to state which piece of data is to be updated, and
where the updated data is located in the system. This
is an advantage compared to systems where
user-written software must keep track of the old data
location, status, logical to physical translation of the
data onto the Flash memory device (or memory de-
vices), and more. Using DMS, user-written software
does not need to interface with the Flash memory di-
rectly. Instead, the user's software accesses the Flash
memory by calling one of only six functions. AMD pro-
vides this software to simplify system design and soft-
ware integration efforts.
The Am29PDS322D offers fast page access time of
40 ns with random access time of 100 ns (at 1.8 V to
2.2 V VCC), allowing operation of high-speed micropro-
cessors without wait states. To eliminate bus conten-
tion the device has separate chip enable (CE), write
enable (WE), and output enable (OE) controls. The
page size is 4 words.
The device requires only a single 1.8 volt power sup-
ply for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
Simultaneous Read/Write Operations with
Zero Latency
The Simultaneous Read/Write architecture provides
simultaneous operation by dividing the memory
space into two banks. The device can improve overall
system performance by allowing a host system to pro-
gram or erase in one bank, then immediately and si-
multaneously read from the other bank, with zero
latency. This releases the system from waiting for the
completion of program or erase operations.
The device offers complete compatibility with the
JEDEC single-power-supply Flash command set
standard. Commands are written to the command
register using standard microprocessor write timings.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
The device is divided as shown in the following table:
The host system can detect whether a program or
erase operation is complete by using the device sta-
tus bits: RY/BY# pin, DQ7 (Data# Polling) and
DQ6/DQ2 (toggle bits). After a program or erase cycle
has been completed, the device automatically returns
to the read mode.
Bank 1 Sectors
Quantity Size
Bank 2 Sectors
Quantity
Size
8
7
4 Kwords
56
32 Kwords
32 Kwords
The sector erase architecture allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
4 Mbits total
28 Mbits total
Am29PDS322D Features
The SecSi (Secured Silicon) Sector is an extra 64
KByte sector capable of being permanently locked by
AMD or customers. The SecSi Indicator Bit (DQ7) is
permanently set to a 1 if the part is factory locked,
and set to a 0 if customer lockable. This way, cus-
tomer lockable parts can never be used to replace a
factory locked part.
Hardware data protection measures include a low
VCC detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved in-system or via program-
ming equipment.
Factory locked parts provide several options. The
SecSi Sector may store a secure, random 16 byte
ESN (Electronic Serial Number), customer code (pro-
grammed through AMD’s ExpressFlash service), or
both. Customer Lockable parts may utilize the SecSi
Sector as bonus space, reading and writing like any
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the automatic sleep mode.
The system can also place the device into the
standby mode. Power consumption is greatly re-
duced in both modes.
2
Am41PDS3224D
May 13, 2002
P R E L I M I N A R Y
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
MCP Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . 5
Flash Memory Block Diagram. . . . . . . . . . . . . . . . 6
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 7
Special Package Handling Instructions .................................... 7
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
MCP Device Bus Operations. . . . . . . . . . . . . . . . 10
Table 1. Device Bus Operations—SRAM Word Mode, CIOs = VCC 10
Table 2. Device Bus Operations—SRAM Byte Mode, CIOs = VSS 11
Flash Device Bus Operations . . . . . . . . . . . . . . . 12
Requirements for Reading Array Data ................................... 12
Read Mode ............................................................................. 12
Random Read (Non-Page Mode Read) .............................. 12
Page Mode Read .................................................................... 12
Table 3. Page Word Mode ..............................................................12
Writing Commands/Command Sequences ............................ 12
Accelerated Program Operation .......................................... 12
Autoselect Functions ........................................................... 13
Simultaneous Read/Write Operations with Zero Latency ....... 13
Standby Mode ........................................................................ 13
Automatic Sleep Mode ........................................................... 13
RESET#: Hardware Reset Pin ............................................... 13
Output Disable Mode .............................................................. 14
Table 4. Am29PDS322DT Top Boot Sector Addresses ..................14
Table 5. Am29PDS322DT Top Boot SecSi Sector Address ...........15
Table 6. Am29PDS322DB Bottom Boot Sector Addresses ............15
Am29PDS322DB Bottom Boot SecSi Sector Address.................... 17
Autoselect Mode ..................................................................... 17
Sector/Sector Block Protection and Unprotection .................. 17
Table 8. Top Boot Sector/Sector Block Addresses for Protection/Un-
protection ........................................................................................17
Table 9. Bottom Boot Sector/Sector Block Addresses for Protec-
tion/Unprotection .............................................................................18
Write Protect (WP#) ................................................................ 18
Temporary Sector/Sector Block Unprotect ............................. 18
Figure 1. Temporary Sector Unprotect Operation........................... 19
Figure 2. In-System Sector/Sector Block Protect and Unprotect Algo-
rithms .............................................................................................. 20
SecSi (Secured Silicon) Sector Flash Memory Region .......... 21
Factory Locked: SecSi Sector Programmed and Protected
at the Factory ...................................................................... 21
Hardware Data Protection ...................................................... 21
Low VCC Write Inhibit ........................................................... 21
Write Pulse “Glitch” Protection ............................................ 22
Logical Inhibit ...................................................................... 22
Power-Up Write Inhibit ......................................................... 22
Flash Command Definitions . . . . . . . . . . . . . . . . 22
Reading Array Data ................................................................ 22
Reset Command ..................................................................... 22
Autoselect Command Sequence ............................................ 22
Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 23
Word Program Command Sequence ..................................... 23
Unlock Bypass Command Sequence .................................. 23
Figure 3. Unlock Bypass Algorithm................................................. 24
Figure 4. Program Operation .......................................................... 24
Chip Erase Command Sequence ...........................................24
Sector Erase Command Sequence ........................................ 25
Erase Suspend/Erase Resume Commands ...........................25
Figure 5. Erase Operation.............................................................. 26
Table 10. Am29PDS322D Command Definitions ........................... 27
Flash Write Operation Status . . . . . . . . . . . . . . . 28
DQ7: Data# Polling .................................................................28
Figure 6. Data# Polling Algorithm .................................................. 28
RY/BY#: Ready/Busy# ............................................................ 29
DQ6: Toggle Bit I .................................................................... 29
Figure 7. Toggle Bit Algorithm........................................................ 29
DQ2: Toggle Bit II ...................................................................30
Reading Toggle Bits DQ6/DQ2 ...............................................30
DQ5: Exceeded Timing Limits ................................................30
DQ3: Sector Erase Timer .......................................................30
Table 11. Write Operation Status ................................................... 31
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 32
Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 32
Industrial (I) Devices ............................................................32
VCCf/VCCs Supply Voltage ................................................... 32
Flash DC Characteristics . . . . . . . . . . . . . . . . . . 33
CMOS Compatible ..................................................................33
SRAM DC and Operating Characteristics . . . . . 34
Figure 10. ICC1 Current vs. Time (Showing Active and Automatic
Sleep Currents).............................................................................. 35
Figure 11. Typical ICC1 vs. Frequency............................................ 35
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 12. Test Setup.................................................................... 36
Table 12. Test Specifications ......................................................... 36
Key To Switching Waveforms . . . . . . . . . . . . . . . 36
Figure 13. Input Waveforms and Measurement Levels ................. 36
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 37
SRAM CE#s Timing ................................................................37
Figure 14. Timing Diagram for Alternating
Between SRAM to Flash................................................................ 37
Figure 15. Conventional Read Operation Timings......................... 38
Figure 16. Page Mode Read Timings ............................................ 39
Hardware Reset (RESET#) .................................................... 40
Figure 17. Reset Timings............................................................... 40
Flash Erase and Program Operations ....................................41
Figure 18. Program Operation Timings.......................................... 42
Figure 19. Accelerated Program Timing Diagram.......................... 42
Figure 20. Chip/Sector Erase Operation Timings .......................... 43
Figure 21. Back-to-back Read/Write Cycle Timings ...................... 44
Figure 22. Data# Polling Timings (During Embedded Algorithms). 44
Figure 23. Toggle Bit Timings (During Embedded Algorithms)...... 45
Figure 24. DQ2 vs. DQ6................................................................. 45
Temporary Sector/Sector Block Unprotect ............................. 46
Figure 25. Temporary Sector/Sector Block Unprotect
Timing Diagram.............................................................................. 46
Figure 26. Sector/Sector Block Protect and Unprotect
Timing Diagram.............................................................................. 47
Alternate CE#f Controlled Erase and Program Operations ....48
Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program) Op-
eration Timings............................................................................... 49
SRAM AC Characteristics . . . . . . . . . . . . . . . . . . 50
Read Cycle .............................................................................50
Figure 28. SRAM Read Cycle—Address Controlled...................... 50
Figure 29. SRAM Read Cycle........................................................ 51
May 13, 2002
Am41PDS3224D
3
P R E L I M I N A R Y
Write Cycle ............................................................................. 52
SRAM Data Retention . . . . . . . . . . . . . . . . . . . . . 56
Figure 33. CE1#s Controlled Data Retention Mode....................... 56
Figure 34. CE2s Controlled Data Retention Mode......................... 56
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 57
FLB073—73-Ball Fine-Pitch Grid Array 8 x 11.6 mm .............57
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 58
Revision A (February 18, 2002) .............................................. 58
Revision A+1 (May 13, 2002) .................................................58
Figure 30. SRAM Write Cycle—WE# Control ................................. 52
Figure 31. SRAM Write Cycle—CE1#s Control .............................. 53
Figure 32. SRAM Write Cycle—UB#s and LB#s Control................ 54
Flash Erase And Programming Performance . . 55
Flash Latchup Characteristics . . . . . . . . . . . . . . 55
Package Pin Capacitance . . . . . . . . . . . . . . . . . . 55
Flash Data Retention . . . . . . . . . . . . . . . . . . . . . . 55
4
Am41PDS3224D
May 13, 2002
P R E L I M I N A R Y
PRODUCT SELECTOR GUIDE
Part Number
Am41PDS3224D
Flash Memory
SRAM
10, 11
70
Standard Voltage Range: VCC
Speed Options
= 1.8–2.2 V
10
100
100
35
11
110
110
40
Max Access Time (ns)
CE# Access (ns)
70
OE# Access (ns)
35
Max Page Address Access Time (ns)
40
45
N/A
MCP BLOCK DIAGRAM
VCC
f
VSS
RY/BY#
A20 to A0
A20 to A0
WP#/ACC
RESET#
CE#f
32 M Bit
Flash Memory
DQ15 to DQ0
DQ15 to DQ0
VCCs/VCCQ VSS/VSSQ
A17 to A0
SA
4 M Bit
Static RAM
LB#s
UB#s
WE#
DQ15 to DQ0
OE#
CE1#s
CE2s
CIOs
May 13, 2002
Am41PDS3224D
5
P R E L I M I N A R Y
FLASH MEMORY BLOCK DIAGRAM
OE#
V
V
CC
SS
Upper Bank Address
A20–A0
Upper Bank
X-Decoder
RY/BY#
A20–A0
RESET#
STATE
CONTROL
&
COMMAND
REGISTER
WE#
CE#
Status
DQ15–DQ0
Control
DQ15–DQ0
X-Decoder
Lower Bank
A20–A0
Lower Bank Address
OE#
6
Am41PDS3224D
May 13, 2002
P R E L I M I N A R Y
CONNECTION DIAGRAM
73-Ball FBGA
Top View
Flash only
SRAM only
A1
A10
NC
NC
B1
B5
B6
B10
NC
NC
NC
NC
Shared
C5
C1
C3
C4
C6
C7
C8
NC
A7
LB# WP#/ACC WE#
A8
A11
D2
A3
D3
A6
D4
D5
D6
D7
A19
E7
A9
D8
A12
E8
A13
F8
D9
A15
E9
NC
F9
NC
UB# RESET# CE2s
E5
E2
A2
E3
A5
E4
E6
A18 RY/BY# A20
F1
NC
G1
NC
F2
A1
F3
A4
F4
A17
G4
DQ1
F7
F10
A10
G7
DQ6
H7
A14
G8
SA
NC
G2
A0
G3
G9 G10
V
SS
A16
H9
NC
J9
NC
H2
CE#f
J2
H3
OE#
J3
H4
DQ9
J4
H5
DQ3
J5
H6
DQ4
J6
H8
DQ13 DQ15
J7
DQ12
K7
J8
DQ7
K8
V
CC
f
V s
CC
CE1#s DQ0
DQ10
K4
V
SS
K3
K5
K6
DQ8
DQ2
DQ11 CIOs
DQ5
DQ14
L1
NC
M1
NC
L5
L6
L10
NC
NC
NC
M10
NC
SSOP). The package and/or data integrity may be
compromised if the package body is exposed to tem-
peratures above 150°C for prolonged periods of time.
Special Package Handling Instructions
Special handling is required for Flash Memory prod-
ucts in molded packages (TSOP, BGA, PLCC, PDIP,
May 13, 2002
Am41PDS3224D
7
P R E L I M I N A R Y
PIN DESCRIPTION
LOGIC SYMBOL
A17–A0
A20–A18
SA
= 18 Address Inputs (Common)
18
= 3 Address Inputs (Flash)
A17–A0
= Highest Order Address Pin (SRAM)
Byte mode
A20–A18
SA
DQ15–DQ0
CE#f
= 16 Data Inputs/Outputs (Common)
= Chip Enable (Flash)
16 or 8
CE#f
DQ15–DQ0
RY/BY#
CE1#s
CE2s
= Chip Enable 1 (SRAM)
CE1#s
CE2s
= Chip Enable 2 (SRAM)
OE#
= Output Enable (Common)
= Write Enable (Common)
= Ready/Busy Output (Flash)
= Upper Byte Control (SRAM)
= Lower Byte Control (SRAM)
OE#
WE#
WE#
RY/BY#
UB#s
WP#/ACC
RESET#
UB#s
LB#s
CIOs
= I/O Configuration (SRAM)
CIOs = VIH = Word mode (x16),
CIOs = VIL = Byte mode (x8)
LB#s
CIOs
RESET#
= Hardware Reset Pin, Active Low
WP#/ACC
= Hardware Write Protect/
Acceleration Pin (Flash)
V
CCf
= Flash 1.8 volt-only single power
supply (see Product Selector Guide
for speed options and voltage sup-
ply tolerances)
VCC
VSS
NC
s
= SRAM Power Supply
= Device Ground (Common)
= Pin Not Connected Internally
8
Am41PDS3224D
May 13, 2002
P R E L I M I N A R Y
ORDERING INFORMATION
The order number (Valid Combination) is formed by the following:
Am41PDS322
4
D
T
10
I
T
TAPE AND REEL
T
S
=
=
7 inches
13 inches
TEMPERATURE RANGE
Industrial (–40°C to +85°C)
I
=
SPEED OPTION
See “Product Selector Guide” on page 5
BOOT CODE SECTOR ARCHITECTURE
T
B
=
=
Top sector
Bottom sector
PROCESS TECHNOLOGY
0.23 µm
D
=
SRAM DEVICE DENSITY
4 Mbits
4
=
AMD DEVICE NUMBER/DESCRIPTION
Am41PDS3224D
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
Am29PDS322D 32 Megabit (2 M x 16-Bit) CMOS 1.8 Volt-only, Simultaneous Operation,
Page Mode Flash Memory and 4 Mbit (512 K x 8-Bit/256 K x 16-Bit) Static RAM
Valid Combinations
Valid Combinations
Valid Combinations list configurations planned to be supported in vol-
ume for this device. Consult the local AMD sales office to confirm
availability of specific valid combinations and to check on newly re-
leased combinations
Order Number
Package Marking
Am41PDS3224DT10I
Am41PDS3224DB10I
M410000077
M410000078
T, S
Am41PDS3224DT11I
Am41PDS3224DB11I
M410000079
M41000007A
May 13, 2002
Am41PDS3224D
9
P R E L I M I N A R Y
MCP DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the
commands, along with the address and data informa-
tion needed to execute the command. The contents of
the register serve as inputs to the internal state ma-
chine. The state machine outputs dictate the function
of the device. Tables 1–2 list the device bus opera-
tions, the inputs and control levels they require, and
the resulting output. The following subsections de-
scribe each of these operations in further detail.
Table 1. Device Bus Operations—SRAM Word Mode, CIOs = VCC
Operation
(Notes 1, 2)
LB#s
(Note 3) (Note 3)
UB#s
WP#/ACC DQ7–
DQ15–
DQ8
CE#f CE1#s CE2s OE# WE# SA
Addr.
RESET#
(Note 4)
DQ0
H
X
H
X
H
X
X
L
X
L
X
L
Read from Flash
Write to Flash
Standby
L
L
H
X
H
L
X
X
X
AIN
X
X
X
X
X
X
H
L/H
DOUT
DOUT
L
AIN
X
H
(Note 4)
H
DIN
DIN
VCC
0.3 V
±
VCC ±
0.3 V
X
High-Z High-Z
High-Z High-Z
High-Z High-Z
H
H
H
H
X
X
X
X
L
X
L
Output Disable
L
L
H
H
L/H
X
H
X
H
X
L
Flash Hardware
Reset
X
L
X
X
X
X
X
X
X
L
L/H
X
SADD,
A6 = L,
A1 = H,
A0 = L
Sector Protect
(Note 5)
H
L
X
X
VID
L/H
DIN
X
X
H
X
L
X
L
SADD,
A6 = H,
A1 = H,
A0 = L
Sector Unprotect
(Note 5)
L
X
H
H
X
L
L
X
H
X
X
X
X
X
X
X
VID
VID
H
(Note 6)
(Note 6)
X
DIN
DIN
X
H
X
X
L
Temporary Sector
Unprotect
X
High-Z
L
H
L
L
L
DOUT
High-Z
DOUT
DIN
DOUT
DOUT
High-Z
DIN
Read from SRAM
Write to SRAM
L
L
H
H
AIN
H
L
L
H
X
L
X
AIN
H
L
L
H
L/H
High-Z
DIN
DIN
H
High-Z
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 9–11 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = SRAM Address Input, Byte Mode,
SADD = Flash Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Other operations except for those indicated in this column are inhibited.
2. Do not apply CE#f = VIL, CE1#s = VIL and CE2s = VIH at the same time.
3. Don’t care or open LB#s or UB#s.
4. If WP#/ACC = VIL , the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed.
If WP#/ACC = VACC (9V), the program time will be reduced by 40%.
5. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector Block Protection
and Unprotection” section.
6. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection depends
on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. If
WP#/ACC = VHH, all sectors will be unprotected.
10
Am41PDS3224D
May 13, 2002
P R E L I M I N A R Y
Table 2. Device Bus Operations—SRAM Byte Mode, CIOs = VSS
Operation
(Notes 1, 2)
LB#s
(Note 3) (Note 3)
UB#s
WP#/ACC DQ7– DQ15–
CE#f CE1#s CE2s OE# WE# SA
Addr.
RESET#
(Note 4)
DQ0
DQ8
H
X
H
X
H
X
L
X
L
Read from Flash
Write to Flash
L
L
H
L
X
X
AIN
X
X
X
X
H
L/H
DOUT
DOUT
X
L
L
H
AIN
H
(Note 3)
DIN
DIN
X
L
VCC
0.3 V
±
VCC ±
0.3 V
Standby
X
H
X
X
H
X
X
SA
X
X
X
X
X
DNU
X
X
DNU
X
H
High-Z High-Z
High-Z High-Z
High-Z High-Z
Output Disable
L
H
X
L
H
L/H
L/H
H
X
H
Flash Hardware
Reset
X
L
L
X
SADD,
A6 = L,
A1 = H,
A0 = L
Sector Protect (Note
5)
H
L
X
X
X
VID
L/H
DIN
X
X
H
X
L
X
L
SADD,
A6 = H,
A1 = H,
A0 = L
Sector Unprotect
(Note 5)
L
H
X
L
X
X
X
X
X
X
VID
(Note 6)
(Note 6)
DIN
X
H
X
L
X
L
Temporary Sector
Unprotect
X
X
AIN
VID
DIN
High-Z
Read from SRAM
Write to SRAM
H
H
H
H
L
H
L
SA
SA
AIN
AIN
X
X
X
X
H
H
X
X
DOUT
DIN
High-Z
High-Z
L
X
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 9–11 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = SRAM Address Input, Byte Mode,
SADD = Flash Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out, DNU = Do Not Use
Notes:
1. Other operations except for those indicated in this column are inhibited.
2. Do not apply CE#f = VIL, CE1#s = VIL and CE2s = VIH at the same time.
3. Don’t care or open LB#s or UB#s.
4. If WP#/ACC = VIL , the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed.
If WP#/ACC = VACC (9V), the program time will be reduced by 40%.
5. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector Block Protection
and Unprotection” section.
6. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection depends on
whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. If WP#/ACC =
VHH, all sectors will be unprotected.
May 13, 2002
Am41PDS3224D
11
P R E L I M I N A R Y
within that Page) are equivalent to tPACC. When CE# is
FLASH DEVICE BUS OPERATIONS
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE#f and OE# pins to VIL. CE#f is the power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at VIH.
deasserted and reasserted for a subsequent access,
the access time is tACC or tCE. Here again, CE# selects
the device and OE# is the output control and should be
used to gate data to the output pins if the device is se-
lected. Fast Page mode accesses are obtained by
keeping A20–A2 constant and changing A1–A0 to se-
lect the specific word within that page. See Figure 16
for timing specifications.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
data on the device data outputs. Each bank remains
enabled for read access until the command register
contents are altered.
The following table determines the specific word within
the selected page:
Table 3. Page Word Mode
Word
Word 0
Word 1
Word 2
Word 3
A1
0
A0
0
0
1
1
0
See “Requirements for Reading Array Data” for more
information. Refer to the AC Read-Only Operations
table for timing specifications and to Figure 15 for the
timing diagram. ICC1 in the DC Characteristics table
represents the active current specification for reading
array data.
1
1
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
Read Mode
Random Read (Non-Page Mode Read)
The device features an Unlock Bypass mode to facil-
itate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are re-
quired to program a word, instead of four. The “Word
Program Command Sequence” section has details on
programming data to the device using both standard
and Unlock Bypass command sequences.
The device has two control functions which must be
satisfied in order to obtain data at the outputs. CE# is
the power control and should be used for device selec-
tion. OE# is the output control and should be used to
gate data to the output pins if the device is selected.
Address access time (tACC) is equal to the delay from
stable addresses to valid output data. The chip enable
access time (tCE) is the delay from the stable ad-
dresses and stable CE# to valid data at the output
pins. The output enable access time is the delay from
the falling edge of OE# to valid data at the output pins
(assuming the addresses have been stable for at least
tACC–tOE time).
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Table 3 indicates the address
space that each sector occupies.
ICC2f in the DC Characteristics table represents the ac-
tive current specification for the write mode. The Mea-
surements performed by placing a 50Ω termination on
the data pin with a bias of VCC/2. The time from OE#
high to the data bus driven to VCC/2 is taken as tDFAC
Characteristics. section contains timing specification
tables and timing diagrams for write operations.
Page Mode Read
The device is capable of fast Page mode read and is
compatible with the Page mode Mask ROM read oper-
ation. This mode provides faster read access speed
for random locations within a page. The Page size of
the device is 4 words. The appropriate Page is se-
lected by the higher address bits A20–A0 and the LSB
bits A1–A0 determine the specific word within that
page. This is an asynchronous operation with the mi-
croprocessor supplying the specific word location.
Accelerated Program Operation
The device offers accelerated program operations
through the ACC function. This is one of two functions
provided by the WP#/ACC pin. This function is prima-
rily intended to allow faster manufacturing throughput
at the factory.
The random or initial page access is equal to tACC or
tCE and subsequent Page read accesses (as long as
the locations specified by the microprocessor fall
If the system asserts VHH on this pin, the device auto-
matically enters the aforementioned Unlock Bypass
mode, temporarily unprotects any protected sectors,
12
Am41PDS3224D
May 13, 2002
P R E L I M I N A R Y
and uses the higher voltage on the pin to reduce the this mode when addresses remain stable for tACC
+
time required for program operations. The system
would use a two-cycle program command sequence
as required by the Unlock Bypass mode. Removing
VHH from the ACC pin returns the device to normal op-
eration.
30 ns. The automatic sleep mode is independent of
the CE#, WE#, and OE# control signals. Standard ad-
dress access timings provide new data when ad-
dresses are changed. While in sleep mode, output
data is latched and always available to the system.
Automatic sleep mode current is drawn when CE# =
VSS ± 0.3 V and all inputs are held at VCC ± 0.3 V. If
CE# and RESET# voltages are not held within these
tolerances, the automatic sleep mode current will be
greater.
Autoselect Functions
If the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ15–DQ0. Standard read cycle timings apply in
this mode. Refer to the Autoselect Mode and Autose-
lect Command Sequence sections for more
information.
ICC5f in the Flash DC Characteristics table represents
the automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the RE-
SET# pin is driven low for at least a period of tRP, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
Simultaneous Read/Write Operations with
Zero Latency
This device is capable of reading data from one bank
of memory while programming or erasing in the other
bank of memory. An erase operation may also be sus-
pended to read from or program to another location
within the same bank (except the sector being
erased). Figure 21 shows how read and write cycles
may be initiated for simultaneous operation with zero
latency. ICC6 and ICC7 in the Flash DC Characteristics
table represent the current specifications for
read-while-program and read-while-erase,
respectively.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VSS ± 0.3 V, the de-
vice draws CMOS standby current (ICC3f). If RESET#
is held at VIL but not within VSS ± 0.3 V, the standby
current will be greater.
Standby Mode
When the system is not reading or writing to the de-
vice, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase op-
eration, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of tREADY (during Embedded Algorithms). The
system can thus monitor RY/BY# to determine
whether the reset operation is complete. If RESET# is
asserted when a program or erase operation is not ex-
ecuting (RY/BY# pin is “1”), the reset operation is com-
pleted within a time of tREADY (not during Embedded
Algorithms). The system can read data tRH after the
RESET# pin returns to VIH.
The device enters the CMOS standby mode when the
CE#f and RESET# pins are both held at VCC ± 0.3 V.
(Note that this is a more restricted voltage range than
VIH.) If CE#f and RESET# are held at VIH, but not
within VCC ± 0.3 V, the device will be in the standby
mode, but the standby current will be greater. The de-
vice requires standard access time (tCE) for read
access when the device is in either of these standby
modes, before it is ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
Refer to the AC Characteristics tables for RESET# pa-
rameters and to Figure 17 for the timing diagram.
ICC3 in the Flash DC Characteristics table represents
the standby current specification.
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high
impedance state.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device en-
ergy consumption. The device automatically enables
May 13, 2002
Am41PDS3224D
13
P R E L I M I N A R Y
Table 4. Am29PDS322DT Top Boot Sector Addresses
Sector Address
A20–A12
Sector Size
(Kwords)
(x16)
Address Range
Bank
Sector
SA0
000000xxx
000001xxx
000010xxx
000011xxx
000100xxx
000101xxx
000110xxx
000111xxx
001000xxx
001001xxx
001010xxx
001011xxx
001100xxx
001101xxx
001110xxx
001111xxx
010000xxx
010001xxx
010010xxx
010011xxx
010100xxx
010101xxx
010110xxx
010111xxx
011000xxx
011001xxx
011010xxx
011011xxx
011100xxx
011101xxx
011110xxx
011111xxx
100000xxx
100001xxx
100010xxx
100011xxx
100100xxx
100101xxx
100110xxx
100111xxx
101000xxx
101001xxx
101010xxx
101011xxx
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
000000h–07FFFh
008000h–0FFFFh
010000h–17FFFh
018000h–01FFFFh
020000h–027FFFh
028000h–02FFFFh
030000h–037FFFh
038000h–03FFFFh
040000h–047FFFh
048000h–04FFFFh
050000h–057FFFh
058000h–05FFFFh
060000h–067FFFh
068000h–06FFFFh
070000h–077FFFh
078000h–07FFFFh
080000h–087FFFh
088000h–08FFFFh
090000h–097FFFh
098000h–09FFFFh
0A0000h–0A7FFFh
0A8000h–0AFFFFh
0B0000h–0B7FFFh
0B8000h–0BFFFFh
0C0000h–0C7FFFh
0C8000h–0CFFFFh
0D0000h–0D7FFFh
0D8000h–0DFFFFh
0E0000h–0E7FFFh
0E8000h–0EFFFFh
0F0000h–0F7FFFh
0F8000h–0FFFFFh
100000h–107FFFh
108000h–10FFFFh
110000h–117FFFh
118000h–11FFFFh
120000h–127FFFh
128000h–12FFFFh
130000h–137FFFh
138000h–13FFFFh
140000h–147FFFh
148000h–14FFFFh
150000h–157FFFh
158000h–15FFFFh
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
14
Am41PDS3224D
May 13, 2002
P R E L I M I N A R Y
Table 4. Am29PDS322DT Top Boot Sector Addresses (Continued)
Sector Address
A20–A12
Sector Size
(Kwords)
(x16)
Address Range
Bank
Sector
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
101100xxx
101101xxx
101110xxx
101111xxx
110000xxx
110001xxx
110010xxx
110011xxx
110100xxx
110101xxx
110110xxx
110111xxx
111000xxx
111001xxx
111010xxx
111011xxx
111100xxx
111101xxx
111110xxx
111111000
111111001
111111010
111111011
111111100
111111101
111111110
111111111
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4
160000h–167FFFh
168000h–16FFFFh
170000h–177FFFh
178000h–17FFFFh
180000h–187FFFh
188000h–18FFFFh
190000h–197FFFh
198000h–19FFFFh
1A0000h–1A7FFFh
1A8000h–1AFFFFh
1B0000h–1B7FFFh
1B8000h–1BFFFFh
1C0000h–1C7FFFh
1C8000h–1CFFFFh
1D0000h–1D7FFFh
1D8000h–1DFFFFh
1E0000h–1E7FFFh
1E8000h–1EFFFFh
1F0000h–1F7FFFh
1F8000h–1F8FFFh
1F9000h–1F9FFFh
1FA000h–1FAFFFh
1FB000h–1FBFFFh
1FC000h–1FCFFFh
1FD000h–1FDFFFh
1FE000h–1FEFFFh
1FF000h–1FFFFFh
4
4
4
4
4
4
4
Table 5. Am29PDS322DT Top Boot SecSi Sector Address
Sector Address A20–A12
111111xxx
Sector Size
(x16) Address Range
32
1F8000h–1FFFFh
Table 6. Am29PDS322DB Bottom Boot Sector Addresses
Sector Address
A20–A12
Sector Size
(Kwords)
(x16)
Address Range
Bank
Sector
SA0
000000000
000000001
000000010
000000011
000000100
000000101
000000110
000000111
000001xxx
000010xxx
000011xxx
000100xxx
000101xxx
000110xxx
000111xxx
4
4
000000h–000FFFh
001000h–001FFFh
002000h–002FFFh
003000h–003FFFh
004000h–004FFFh
005000h–005FFFh
006000h–006FFFh
007000h–007FFFh
008000h–00FFFFh
010000h–017FFFh
018000h–01FFFFh
020000h–027FFFh
028000h–02FFFFh
030000h–037FFFh
038000h–03FFFFh
SA1
SA2
4
SA3
4
SA4
4
SA5
4
SA6
4
SA7
4
SA8
32
32
32
32
32
32
32
SA9
SA10
SA11
SA12
SA13
SA14
May 13, 2002
Am41PDS3224D
15
P R E L I M I N A R Y
Table 6. Am29PDS322DB Bottom Boot Sector Addresses (Continued)
Sector Address
A20–A12
Sector Size
(Kwords)
(x16)
Address Range
Bank
Sector
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
001000xxx
001001xxx
001010xxx
001011xxx
001100xxx
001101xxx
001110xxx
001111xxx
010000xxx
010001xxx
010010xxx
010011xxx
010100xxx
010101xxx
010110xxx
010111xxx
011000xxx
011001xxx
011010xxx
011011xxx
011100xxx
011101xxx
011110xxx
011111xxx
100000xxx
100001xxx
100010xxx
100011xxx
100100xxx
100101xxx
100110xxx
100111xxx
101000xxx
101001xxx
101010xxx
101011xxx
101100xxx
101101xxx
101110xxx
101111xxx
111000xxx
110001xxx
110010xxx
110011xxx
110100xxx
110101xxx
110110xxx
110111xxx
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
040000h–047FFFh
048000h–04FFFFh
050000h–057FFFh
058000h–05FFFFh
060000h–067FFFh
068000h–06FFFFh
070000h–077FFFh
078000h–07FFFFh
080000h–087FFFh
088000h–08FFFFh
090000h–097FFFh
098000h–09FFFFh
0A0000h–0A7FFFh
0A8000h–0AFFFFh
0B0000h–0B7FFFh
0B8000h–0BFFFFh
0C0000h–0C7FFFh
0C8000h–0CFFFFh
0D0000h–0D7FFFh
0D8000h–0DFFFFh
0E0000h–0E7FFFh
0E8000h–0EFFFFh
0F0000h–0F7FFFh
0F8000h–0FFFFFh
100000h–107FFFh
108000h–10FFFFh
110000h–117FFFh
118000h–11FFFFh
120000h–127FFFh
128000h–12FFFFh
130000h–137FFFh
138000h–13FFFFh
140000h–147FFFh
148000h–14FFFFh
150000h–157FFFh
158000h–15FFFFh
160000h–167FFFh
168000h–16FFFFh
170000h–177FFFh
178000h–17FFFFh
180000h–187FFFh
188000h–18FFFFh
190000h–197FFFh
198000h–19FFFFh
1A0000h–1A7FFFh
1A8000h–1AFFFFh
1B0000h–1B7FFFh
1B8000h–1BFFFFh
16
Am41PDS3224D
May 13, 2002
P R E L I M I N A R Y
Table 6. Am29PDS322DB Bottom Boot Sector Addresses (Continued)
Sector Address
A20–A12
Sector Size
(Kwords)
(x16)
Address Range
Bank
Sector
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
111000xxx
111001xxx
111010xxx
111011xxx
111100xxx
111101xxx
111110xxx
111111xxx
32
32
32
32
32
32
32
32
1C0000h–1C7FFFh
1C8000h–1CFFFFh
1D0000h–1D7FFFh
1D8000h–1DFFFFh
1E0000h–1E7FFFh
1E8000h–1EFFFFh
1F0000h–1F7FFFh
1F8000h–1FFFFFh
Table 7. Am29PDS322DB Bottom Boot SecSi Sector Address
Sector Address
(x16)
A20–A12
Sector Size
Address Range
000000xxx
32
00000h-07FFFh
Table 8. Top Boot Sector/Sector Block Addresses
for Protection/Unprotection
Autoselect Mode
The autoselect mode provides manufacturer and de-
vice identification, and sector protection verification,
through identifier codes output on DQ15–DQ0. This
mode is primarily intended for programming equip-
ment to automatically match a device to be
programmed with its corresponding programming
algorithm.
Sector
Group
Sector/
Sector Block Size
Sectors
SA0
A20–A12
000000XXX
00001XXXX
0001XXXXX
0010XXXXX
0011XXXXX
0100XXXXX
0101XXXXX
0110XXXXX
0111XXXXX
1000XXXXX
1001XXXXX
1010XXXXX
1011XXXXX
1100XXXXX
1101XXXXX
1110XXXXX
111100XXX
111111000
SGA0
SGA1
64 (1x64) Kbytes
192 (3x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
192 (3x64) Kbytes
8 Kbytes
SA1–SA3
SA4–SA7
SA8–SA11
SA12–SA15
SA16–SA19
SA20–SA23
SA24–SA27
SA28–SA31
SA32–SA35
SA36–SA39
SA40–SA43
SA44–SA47
SA48–SA51
SA52–SA55
SA56–SA59
SA60–SA62
SA63
SGA2
SGA3
SGA4
The autoselect codes can also be accessed in-system
through the command register. The host system can
issue the autoselect command via the command regis-
ter, as shown in Table 10. This method does not
require VID. Refer to the Autoselect Command Se-
quence section for more information.
SGA5
SGA6
SGA7
SGA8
SGA9
SGA10
SGA11
SGA12
SGA13
SGA14
SGA15
SGA16
SGA17
SGA18
SGA19
SGA20
SGA21
SGA22
SGA23
SGA24
Sector/Sector Block Protection and
Unprotection
(Note: For the following discussion, the term “sector”
applies to both sectors and sector blocks. A sector
block consists of two or more adjacent sectors that are
protected or unprotected at the same time (see Tables
8 and 9).
SA64
111111001
8 Kbytes
SA65
111111010
8 Kbytes
SA66
111111011
8 Kbytes
SA67
111111100
8 Kbytes
SA68
111111101
8 Kbytes
SA69
111111110
8 Kbytes
SA70
111111111
8 Kbytes
May 13, 2002
Am41PDS3224D
17
P R E L I M I N A R Y
Table 9. Bottom Boot Sector/Sector Block
Addresses for Protection/Unprotection
It is possible to determine whether a sector is pro-
tected or unprotected. See the Autoselect Mode
section for details.
Sector
Sector/Sector
Group
Sectors
SA70
A20–A12
111111XXX
11110XXXX
1110XXXXX
1101XXXXX
1100XXXXX
1011XXXXX
1010XXXXX
1001XXXXX
1000XXXXX
0111XXXXX
0110XXXXX
0101XXXXX
0100XXXXX
0011XXXXX
0010XXXXX
0001XXXXX
000011XXX
000000111
000000110
000000101
000000100
000000011
000000010
000000001
000000000
Block Size
64 (1x64) Kbytes
192 (3x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
192 (3x64) Kbytes
8 Kbytes
Write Protect (WP#)
SGA0
SGA1
SA69–SA67
SA66–SA63
SA62–SA59
SA58–SA55
SA54–SA51
SA50–SA47
SA46–SA43
SA42–SA39
SA38–SA35
SA34–SA31
SA30–SA27
SA26–SA23
SA22–SA19
SA18–SA15
SA14–SA11
SA10–SA8
SA7
The Write Protect function provides a hardware
method of protecting certain boot sectors without
using VID. This function is one of two provided by the
WP#/ACC pin.
SGA2
SGA3
SGA4
SGA5
If the system asserts VIL on the WP#/ACC pin, the de-
vice disables program and erase functions in the two
“outermost” 8 Kbyte boot sectors independently of
whether those sectors were protected or unprotected
using the method described in “Sector/Sector Block
Protection and Unprotection”. The two outermost 8
Kbyte boot sectors are the two sectors containing the
lowest addresses in a top-boot-configured device, or
the two sectors containing the highest addresses in a
top-boot-configured device.
SGA6
SGA7
SGA8
SGA9
SGA10
SGA11
SGA12
SGA13
SGA14
SGA15
SGA16
SGA17
SGA18
SGA19
SGA20
SGA21
SGA22
SGA23
SGA24
If the system asserts VIH on the WP#/ACC pin, the de-
vice reverts to whether the two outermost 8 Kbyte boot
sectors were last set to be protected or unprotected.
That is, sector protection or unprotection for these two
sectors depends on whether they were last protected
or unprotected using the method described in “Sec-
tor/Sector Block Protection and Unprotection”.
SA6
8 Kbytes
SA5
8 Kbytes
SA4
8 Kbytes
SA3
8 Kbytes
SA2
8 Kbytes
SA1
8 Kbytes
Note that the WP#/ACC pin must not be left floating or
unconnected; inconsistent behavior of the device may
result.
SA0
8 Kbytes
The hardware sector protection feature disables both
program and erase operations in any sector. The hard-
ware sector unprotection feature re-enables both
program and erase operations in previously protected
sectors.
Temporary Sector/Sector Block Unprotect
(Note: For the following discussion, the term “sector”
applies to both sectors and sector blocks. A sector
block consists of two or more adjacent sectors that are
protected or unprotected at the same time (see Table
8).
Sector protection and unprotection requires VID on the
RESET# pin only, and can be implemented either
in-system or via programming equipment. Figure 2
shows the algorithms and Figure 26 shows the timing
diagram. This method uses standard microprocessor
bus cycle timing. For sector unprotect, all unprotected
sectors must first be protected prior to the first sector
unprotect write cycle.
This feature allows temporary unprotection of previ-
ously protected sectors to change data in-system. The
Sector Unprotect mode is activated by setting the RE-
SET# pin to VID (9 V – 11 V). During this mode,
formerly protected sectors can be programmed or
erased by selecting the sector addresses. Once VID is
removed from the RESET# pin, all the previously pro-
tected sectors are protected again. Figure 1 shows the
algorithm, and Figure 25 shows the timing diagrams,
for this feature.
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.
18
Am41PDS3224D
May 13, 2002
P R E L I M I N A R Y
START
RESET# = VID
(Note 1)
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector
Unprotect Completed
(Note 2)
Notes:
1. All protected sectors unprotected (If WP#/ACC = VIL,
outermost boot sectors will remain protected).
2. All previously protected sectors are protected once
again.
Figure 1. Temporary Sector Unprotect Operation
May 13, 2002
Am41PDS3224D
19
P R E L I M I N A R Y
START
START
Protect all sectors:
The indicated portion
of the sector protect
algorithm must be
performed for all
PLSCNT = 1
PLSCNT = 1
RESET# = VID
RESET# = VID
unprotected sectors
prior to issuing the
first sector
Wait 1 µs
Wait 1 µs
unprotect address
No
No
First Write
First Write
Cycle = 60h?
Temporary Sector
Unprotect Mode
Temporary Sector
Unprotect Mode
Cycle = 60h?
Yes
Yes
Set up sector
address
No
All sectors
protected?
Sector Protect:
Write 60h to sector
address with
A6 = 0, A1 = 1,
A0 = 0
Yes
Set up first sector
address
Sector Unprotect:
Wait 150 µs
Write 60h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Verify Sector
Protect: Write 40h
to sector address
with A6 = 0,
Reset
PLSCNT = 1
Increment
PLSCNT
Wait 15 ms
A1 = 1, A0 = 0
Verify Sector
Unprotect: Write
40h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Read from
sector address
with A6 = 0,
A1 = 1, A0 = 0
Increment
PLSCNT
No
No
PLSCNT
= 25?
Read from
sector address
with A6 = 1,
Data = 01h?
Yes
A1 = 1, A0 = 0
No
Yes
Set up
next sector
address
Yes
No
PLSCNT
= 1000?
Protect another
sector?
Data = 00h?
Yes
Device failed
No
Yes
Remove VID
from RESET#
No
Last sector
verified?
Device failed
Write reset
command
Yes
Remove VID
Sector Unprotect
Algorithm
from RESET#
Sector Protect
Algorithm
Sector Protect
complete
Write reset
command
Sector Unprotect
complete
Note: The term “sector” in the figure applies to both sectors and sector blocks.
Figure 2. In-System Sector/Sector Block Protect and Unprotect Algorithms
20
Am41PDS3224D
May 13, 2002
P R E L I M I N A R Y
Customers may opt to have their code programmed by
SecSi (Secured Silicon) Sector Flash
Memory Region
AMD through the AMD ExpressFlash service. AMD
programs the customer’s code, with or without the ran-
dom ESN. The devices are then shipped from AMD’s
factory with the permanently locked. Contact an AMD
representative for details on using AMD’s Express-
Flash service.
The SecSi (Secured Silicon) Sector feature provides a
Flash memory region that enables permanent part
identification through an Electronic Serial Number
(ESN). The SecSi Sector is 64 KBytes in length, and
uses a SecSi Sector Indicator Bit (DQ7) to indicate
whether or not the SecSi Sector is locked when
shipped from the factory. This bit is permanently set at
the factory and cannot be changed, which prevents
cloning of a factory locked part. This ensures the secu-
rity of the ESN once the product is shipped to the field.
Customer Lockable: SecSi Sector NOT
Programmed or Protected at the Factory
If the security feature is not required, the SecSi Sector
can be treated as an additional Flash memory space,
expanding the size of the available Flash array by 64
Kbytes. The SecSi Sector can be read, programmed,
and erased as often as required. The SecSi Sector area
can be protected using one of the following procedures:
AMD offers the device with the SecSi Sector either
factory locked or customer lockable. The fac-
tory-locked version is always protected when shipped
from the factory, and has the SecSi (Secured Silicon)
Sector Indicator Bit permanently set to a “1.” The cus-
tomer-lockable version is shipped with the SecSi Sec-
tor unprotected, allowing customers to utilize that
sector in any manner they choose. The customer-lock-
able version also has the SecSi Sector Indicator Bit
permanently set to a “0.” Thus, the SecSi Sector Indi-
cator Bit prevents customer-lockable devices from
being used to replace devices that are factory locked.
■ Write the three-cycle Enter SecSi Sector Region
command sequence, and then follow the in-system
sector protect algorithm as shown in Figure 2, ex-
cept that RESET# may be at either VIH or VID. This
allows in-system protection of the SecSi Sector
without raising any device pin to a high voltage.
Note that this method is only applicable to the SecSi
Sector.
■ Write the three-cycle Enter SecSi Sector Region
command sequence, and then use the alternate
method of sector protection described in the “Sec-
tor/Sector Block Protection and Unprotection” sec-
tion.
The system accesses the SecSi Sector through a
command sequence (see “Enter SecSi Sector/Exit
SecSi Sector Command Sequence”). After the system
has written the Enter SecSi Sector command se-
quence, it may read the SecSi Sector by using the ad-
dresses normally occupied by the first sector (SA0).
This mode of operation continues until the system is-
sues the Exit SecSi Sector command sequence, or
until power is removed from the device. On power-up,
or following a hardware reset, the device reverts to
sending commands to the boot sectors instead of the
SecSi sector
Once the SecSi Sector is locked and verified, the sys-
tem must write the Exit SecSi Sector Region
command sequence to return to reading and writing
the remainder of the array.
The SecSi Sector protection must be used with cau-
tion since, once protected, there is no procedure
available for unprotecting the SecSi Sector area and
none of the bits in the SecSi Sector memory space
can be modified in any way.
Factory Locked: SecSi Sector Programmed and
Protected at the Factory
Hardware Data Protection
In a factory locked device, the SecSi Sector is pro-
tected when the device is shipped from the factory.
The SecSi Sector cannot be modified in any way. The
device is available preprogrammed with one of the
following:
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 10 for com-
mand definitions). In addition, the following hardware
data protection measures prevent accidental erasure
or programming, which might otherwise be caused by
spurious system level signals during VCC power-up
and power-down transitions, or from system noise.
■ A random, secure ESN only
■ Customer code through the ExpressFlash service
■ Both a random, secure ESN and customer code
through the ExpressFlash service.
Low VCC Write Inhibit
In devices that have an ESN, a Bottom Boot device
will have the 16-byte ESN in the lowest addressable
memory area at addresses 000000h–000007h. In the
Top Boot device the starting address of the ESN will
be at the bottom of the lowest 8 Kbyte boot sector at
addresses 1F8000h–1F8007h.
When VCC is less than VLKO, the device does not ac-
cept any write cycles. This protects data during VCC
power-up and power-down. The command register
and all internal program/erase circuits are disabled,
and the device resets to reading array data. Subse-
quent writes are ignored until VCC is greater than VLKO
.
May 13, 2002
Am41PDS3224D
21
P R E L I M I N A R Y
The system must provide the proper signals to the
control pins to prevent unintentional writes when VCC
is greater than VLKO
CE#f and WE# must be a logical zero while OE# is a
logical one.
.
Power-Up Write Inhibit
Write Pulse “Glitch” Protection
If WE# = CE#f = VIL and OE# = VIH during power up,
the device does not accept commands on the rising
edge of WE#. The internal state machine is automati-
cally reset to reading array data on power-up.
Noise pulses of less than 5 ns (typical) on OE#, CE#f
or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
VIL, CE#f = VIH or WE# = VIH. To initiate a write cycle,
FLASH COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates device op-
erations. Table 10 defines the valid register command
sequences. Writing incorrect address and data val-
ues or writing them in the improper sequence resets
the device to reading array data.
Reset Command
Writing the reset command resets the device to the
read or erase-suspend-read mode. Address bits are
don’t cares for this command.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to the read
mode. Once erasure begins, however, the device ig-
nores reset commands until the operation is complete.
All addresses are latched on the falling edge of WE#
or CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the AC Characteristics section for timing
diagrams.
The reset command may be written between the
sequence cycles in a program command sequence
before programming begins. This resets the device to
the read mode. If the program command sequence is
written while the device is in the Erase Suspend mode,
writing the reset command returns the device to the
erase-suspend-read mode. Once programming be-
gins, however, the device ignores reset commands
until the operation is complete.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is ready to read array data
after completing an Embedded Program or Embedded
Erase algorithm.
After the device accepts an Erase Suspend command,
the device enters the erase-suspend-read mode, after
which the system can read data from any
non-erase-suspended sector. After completing a pro-
gramming operation in the Erase Suspend mode, the
system may once again read array data with the same
exception. See the Erase Suspend/Erase Resume
Commands section for more information.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command
must be written to return to the read mode. If the de-
vice entered the autoselect mode while in the Erase
Suspend mode, writing the reset command returns the
device to the erase-suspend-read mode.
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to the
read mode (or erase-suspend-read mode if the device
was in Erase Suspend).
The system must issue the reset command to return
the device to the read (or erase-suspend-read) mode
if DQ5 goes high during an active program or erase
operation, or if the device is in the autoselect mode.
See the next section, Reset Command, for more infor-
mation.
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and device codes,
and determine whether or not a sector is protected.
Table 10 shows the address and data requirements.
The autoselect command sequence may be written to
an address that is either in the read or
erase-suspend-read mode. The autoselect command
may not be written while the device is actively pro-
gramming or erasing.
See also Requirements for Reading Array Data in the
MCP Device Bus Operations section for more informa-
tion. The Read-Only Operations table provides the
read parameters, and Figure 15 shows the timing dia-
gram.
22
Am41PDS3224D
May 13, 2002
P R E L I M I N A R Y
The autoselect command sequence is initiated by writ-
mine the status of the program operation by using
DQ7, DQ6, or RY/BY#. Refer to the Flash Write Oper-
ation Status section for information on these status
bits.
ing two unlock cycles, followed by the autoselect
command. The device then enters the autoselect mode,
and the system may read any number of autoselect
codes without reinitiating the command sequence.
Any commands written to the device during the Em-
bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program
operation. The program command sequence should
be reinitiated once the device has returned to the read
mode, to ensure data integrity.
Table 10 shows the address and data requirements for
the command sequence. To determine sector protec-
tion information, the system must write to the appropri-
ate sector group address (SGA). Tables 4 and 6 show
the address range associated with each sector.
The system must write the reset command to return to
the read mode (or erase-suspend-read mode if the de-
vice was previously in Erase Suspend).
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from “0” back to a “1.” Attempting to do so may
cause the device to set DQ5 = 1, or cause the DQ7
and DQ6 status bits to indicate the operation was suc-
cessful. However, a succeeding read will show that the
data is still “0.” Only erase operations can convert a
“0” to a “1.”
Enter SecSi Sector/Exit SecSi Sector
Command Sequence
The SecSi Sector region provides a secured data area
containing an 16-byte random Electronic Serial Num-
ber (ESN). The system can access the SecSi Sector
region by issuing the three-cycle Enter SecSi Sector
command sequence. The device continues to access
the SecSi Sector region until the system issues the
four-cycle Exit SecSi Sector command sequence. The
Exit SecSi Sector command sequence returns the de-
vice to normal operation. Table 10 shows the address
and data requirements for both command sequences.
See also “SecSi (Secured Silicon) Sector Flash Mem-
ory Region” for further information. Note that a hard-
ware reset (RESET#=VIL) will reset the device to
reading array data.
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to pro-
gram words to the device faster than using the stan-
dard program command sequence. The unlock
bypass command sequence is initiated by first writing
two unlock cycles. This is followed by a third write
cycle containing the unlock bypass command, 20h.
The device then enters the unlock bypass mode. A
two-cycle unlock bypass program command sequence
is all that is required to program in this mode. The first
cycle in this sequence contains the unlock bypass pro-
gram command, A0h; the second cycle contains the
program address and data. Additional data is pro-
grammed in the same manner. This mode dispenses
with the initial two unlock cycles required in the stan-
dard program command sequence, resulting in faster
total programming time. Table 10 shows the require-
ments for the command sequence.
Word Program Command Sequence
Programming is a four-bus-cycle operation. The pro-
gram command sequence is initiated by writing two
unlock write cycles, followed by the program set-up
command. The program address and data are written
next, which in turn initiate the Embedded Program al-
gorithm. The system is not required to provide further
controls or timings. The device automatically provides
internally generated program pulses and verifies the
programmed cell margin. Table 10 shows the address
and data requirements for the program command se-
quence.
During the unlock bypass mode, only the Unlock By-
pass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com-
mand sequence. The first cycle must contain the data
90h. The second cycle must contain the data 00h. The
device then returns to reading array data. See Figure
3 for the unlock bypass algorithm.
When the Embedded Program algorithm is complete,
the device then returns to the read mode and ad-
dresses are no longer latched. The system can deter-
May 13, 2002
Am41PDS3224D
23
P R E L I M I N A R Y
Figure 4 illustrates the algorithm for the program oper-
ation. Refer to the Flash Erase and Program Opera-
tions table in the AC Characteristics section for
parameters, and Figure 18 for timing diagrams.
Start
555h/AAh
Set
Unlock
Bypass
Mode
2AAh/55h
START
555h/20h
Write Program
Command Sequence
XXXh/A0h
Program Address/Program Data
Data Poll
from System
Embedded
Program
algorithm
Data#Polling Device
in progress
Verify Data?
No
No
In
Verify Byte?
Yes
Unlock
Bypass
Program
Yes
No
No
Increment
Address
Last Address
?
Increment Address
Last Address?
Yes
Yes
Programming Completed
(BA)XXXh/90h
Programming
Completed
Reset
Unlock
Bypass
Mode
Note: See Table 10 for program command sequence.
XXXh/00h
Figure 4. Program Operation
Figure 3. Unlock Bypass Algorithm
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Table 10
shows the address and data requirements for the chip
erase command sequence.
The device offers accelerated program operations
through the WP#/ACC pin. When the system asserts
VHH on the WP#/ACC pin, the device automatically en-
ters the Unlock Bypass mode. The system may then
write the two-cycle Unlock Bypass program command
sequence. The device uses the higher voltage on the
WP#/ACC pin to accelerate the operation. Note that
the WP#/ACC pin must not be at VHH any operation
other than accelerated programming, or device dam-
age may result. In addition, the WP#/ACC pin must not
be left floating or unconnected; inconsistent behavior
of the device may result.
24
Am41PDS3224D
May 13, 2002
P R E L I M I N A R Y
When the Embedded Erase algorithm is complete, the ing edge of the final WE# pulse in the command
device returns to the read mode and addresses are no
longer latched. The system can determine the status
of the erase operation by using DQ7, DQ6, DQ2, or
RY/BY#. Refer to the Flash Write Operation Status
section for information on these status bits.
sequence.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses
are no longer latched. Note that while the Embedded
Erase operation is in progress, the system can read
data from the non-erasing sector. The system can de-
termine the status of the erase operation by reading
DQ7, DQ6, DQ2, or RY/BY# in the erasing sector.
Refer to the Flash Write Operation Status section for
information on these status bits.
Any commands written during the chip erase operation
are ignored. However, note that a hardware reset im-
mediately terminates the erase operation. If that oc-
curs, the chip erase command sequence should be
reinitiated once the device has returned to reading
array data, to ensure data integrity.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other com-
mands are ignored. However, note that a hardware
reset immediately terminates the erase operation. If
that occurs, the sector erase command sequence
should be reinitiated once the device has returned to
reading array data, to ensure data integrity.
Figure 5 illustrates the algorithm for the erase opera-
tion. Refer to the Flash Erase and Program Opera-
tions tables in the AC Characteristics section for
parameters, and Figure 20 section for timing dia-
grams.
Sector Erase Command Sequence
Figure 5 illustrates the algorithm for the erase opera-
tion. Refer to the Flash Erase and Program Opera-
tions tables in the AC Characteristics section for
parameters, and Figure 20 section for timing dia-
grams.
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two ad-
ditional unlock cycles are written, and are then fol-
lowed by the address of the sector to be erased, and
the sector erase command. Table 10 shows the ad-
dress and data requirements for the sector erase com-
mand sequence.
Erase Suspend/Erase Resume
Commands
The Erase Suspend command, B0h, allows the sys-
tem to interrupt a sector erase operation and then read
data from, or program data to, any sector not selected
for erasure. This command is valid only during the
sector erase operation, including the 50 µs time-out
period during the sector erase command sequence.
The Erase Suspend command is ignored if written dur-
ing the chip erase operation or Embedded Program
algorithm.
The device does not require the system to preprogram
prior to erase. The Embedded Erase algorithm auto-
matically programs and verifies the entire memory for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
After the command sequence is written, a sector erase
time-out of 50 µs occurs. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time
between these additional cycles must be less than 50
µs, otherwise erasure may begin. Any sector erase
address and command following the exceeded
time-out may or may not be accepted. It is recom-
mended that processor interrupts be disabled during
this time to ensure all commands are accepted. The
interrupts can be re-enabled after the last Sector
Erase command is written. Any command other than
Sector Erase or Erase Suspend during the
time-out period resets the device to the read
mode. The system must rewrite the command se-
quence and any additional addresses and commands.
When the Erase Suspend command is written during
the sector erase operation, the device requires a max-
imum of 20 µs to suspend the erase operation. How-
ever, when the Erase Suspend command is written
during the sector erase time-out, the device immedi-
ately terminates the time-out period and suspends the
erase operation.
After the erase operation has been suspended, the
device enters the erase-suspend-read mode. The sys-
tem can read data from or program data to any sector
not selected for erasure. (The device “erase sus-
pends” all sectors selected for erasure.) Note that un-
lock bypass programming is not allowed when the
device is erase-suspended.
Reading at any address within erase-suspended sec-
tors produces status information on DQ7–DQ0. The
system can use DQ7, or DQ6 and DQ2 together, to
determine if a sector is actively erasing or is
The system can monitor DQ3 to determine if the sec-
tor erase timer has timed out (See the section on DQ3:
Sector Erase Timer.). The time-out begins from the ris-
May 13, 2002
Am41PDS3224D
25
P R E L I M I N A R Y
erase-suspended. Refer to the Flash Write Operation
Status section for information on these status bits.
After an erase-suspended program operation is com-
plete, the device returns to the erase-suspend-read
mode. The system can determine the status of the
program operation using the DQ7 or DQ6 status bits,
just as in the standard word program operation.
Refer to the Flash Write Operation Status section for
more information.
START
Write Erase
Command Sequence
(Notes 1, 2)
In the erase-suspend-read mode, the system can also
issue the autoselect command sequence. Refer to the
Autoselect Mode and Autoselect Command Sequence
sections for details.
Data Poll to Erasing
Bank from System
Embedded
Erase
To resume the sector erase operation, the system
must write the Erase Resume command. The address
of the erase-suspended sector is required when writ-
ing this command. Further writes of the Resume com-
mand are ignored. Another Erase Suspend command
can be written after the chip has resumed erasing.
algorithm
in progress
No
Data = FFh?
Yes
Erasure Completed
Notes:
1. See Table 10 for erase command sequence.
2. See the section on DQ3 for information on the sector
erase timer.
Figure 5. Erase Operation
26
Am41PDS3224D
May 13, 2002
P R E L I M I N A R Y
Table 10. Am29PDS322D Command Definitions
Bus Cycles (Notes 2–5)
Command
Sequence
(Note 1)
First
Second
Third
Addr
Fourth
Fifth
Sixth
Addr Data Addr Data
Data
Addr
Data
Addr Data Addr Data
Read (Note 6)
Reset (Note 7)
Manufacturer ID
1
1
4
RA
XXX
555
RD
F0
AA
2AA
2AA
55
55
555
555
90
90
X00
X01
0001
227E
2201/
X0E 2206 X0F
2200
Device ID (Note 9)
4
4
4
555
555
555
AA
AA
AA
SecSi Sector Factory
Protect (Note 10)
2AA
2AA
55
55
555
555
90
90
X03
80/00
Sector Group Protect Verify
(Note 11)
(SGA)
X02
XX00/
XX01
Enter SecSi Sector Region
Exit SecSi Sector Region
Program
3
4
4
3
555
555
555
555
AA
AA
AA
AA
2AA
2AA
2AA
2AA
55
55
55
55
555
555
555
555
88
90
A0
20
XXX
PA
00
PD
Unlock Bypass
Unlock Bypass Program (Note 12)
XXX
A0
PA
PD
2
Unlock Bypass Reset (Note 13)
Chip Erase
XXX
555
555
BA
90
AA
AA
B0
30
XXX
2AA
2AA
00
55
55
2
6
6
1
1
555
555
80
80
555
555
AA
AA
2AA
2AA
55
55
555
SA
10
30
Sector Erase
Erase Suspend (Note 14)
Erase Resume (Note 15)
BA
Legend:
X = Don’t care
PD = Data to be programmed at location PA. Data latches on the rising
edge of WE# or CE# pulse, whichever happens first.
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses
SGA = Address of the sector group to be verified (in autoselect mode)
or erased. Address bits A20–A12 uniquely select any sector.
latch on the falling edge of the WE# or CE# pulse, whichever happens
later.
Notes:
1. See Table 1 for description of bus operations.
9. The device ID must be read across the fourth, fifth and sixth
cycles. The sixth cycle specifies 2201h for top boot or 2200h for
bottom boot.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth and fifth cycle of the
autoselect command sequence, all bus cycles are write cycles.
10. The data is 80h for factory locked and 00h for not factory locked.
11. The data is 00h for an unprotected sector group and 01h for a
protected sector group.
4. Data bits DQ15–DQ8 are don’t care in command sequences,
except for RD and PD.
12. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
5. Unless otherwise noted, address bits A20–A12 are don’t cares in
unlock sequence.
13. The Unlock Bypass Reset command is required to return to the
read mode when the device is in the unlock bypass mode.
6. No unlock or command cycles required when device is in read
mode.
14. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
7. The Reset command is required to return to the read mode (or to
the erase-suspend-read mode if previously in Erase Suspend)
when the device is in the autoselect mode, or if DQ5 goes high
(while the device is providing status information).
15. The Erase Resume command is valid only during the Erase
Suspend mode, and requires the bank address.
8. The fourth cycle of the autoselect command sequence is a read
cycle. The system must provide the bank address to obtain the
manufacturer ID, device ID, or SecSi Sector factory protect
information. Data bits DQ15–DQ8 are don’t care. See the
Autoselect Command Sequence section for more information.
May 13, 2002
Am41PDS3224D
27
P R E L I M I N A R Y
FLASH WRITE OPERATION STATUS
The device provides several bits to determine the sta-
tus of a program or erase operation: DQ2, DQ3, DQ5,
DQ6, and DQ7. Table 11 and the following subsec-
tions describe the function of these bits. DQ7 and DQ6
each offer a method for determining whether a pro-
gram or erase operation is complete or in progress.
The device also provides a hardware-based output
signal, RY/BY#, to determine whether an Embedded
Program or Erase operation is in progress or has been
completed.
pleted the program or erase operation and DQ7 has
valid data, the data outputs on DQ6–DQ0 may be still
invalid. Valid data on DQ7–DQ0 will appear on suc-
cessive read cycles.
Table 11 shows the outputs for Data# Polling on DQ7.
Figure 6 shows the Data# Polling algorithm. Figure 22
in the Flash AC Characteristics section shows the
Data# Polling timing diagram.
DQ7: Data# Polling
START
The Data# Polling bit, DQ7, indicates to the host sys-
tem whether an Embedded Program or Erase
algorithm is in progress or completed, or whether a
bank is in Erase Suspend. Data# Polling is valid after
the rising edge of the final WE# pulse in the command
sequence.
Read DQ7–DQ0
Addr = VA
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum pro-
grammed to DQ7. This DQ7 status also applies to
programming during Erase Suspend. When the Em-
bedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for
approximately 1 µs, then that bank returns to reading
array data.
Yes
DQ7 = Data?
No
No
DQ5 = 1?
Yes
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase
algorithm is complete, or if the bank enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
The system must provide an address within any of the
sectors selected for erasure to read valid status infor-
mation on DQ7.
Read DQ7–DQ0
Addr = VA
Yes
DQ7 = Data?
After an erase command sequence is written, if all
sectors selected for erasing are protected, Data# Poll-
ing on DQ7 is active for approximately 100 µs, then
the bank returns to reading array data. If not all se-
lected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores
the selected sectors that are protected. However, if the
system reads DQ7 at an address within a protected
sector, the status may not be valid.
No
PASS
FAIL
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is any sector address
within the sector being erased. During chip erase, a
valid address is any non-protected sector address.
Just prior to the completion of an Embedded Program
or Erase operation, DQ7 may change asynchronously
with DQ0–DQ6 while Output Enable (OE#) is asserted
low. That is, the device may change from providing
status information to valid data on DQ7. Depending on
when the system samples the DQ7 output, it may read
the status or valid data. Even if the device has com-
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
Figure 6. Data# Polling Algorithm
28
Am41PDS3224D
May 13, 2002
P R E L I M I N A R Y
Table 11 shows the outputs for Toggle Bit I on DQ6.
RY/BY#: Ready/Busy#
Figure 7 shows the toggle bit algorithm. Figure 23 in
the “Measurements performed by placing a 50Ω termi-
nation on the data pin with a bias of VCC/2. The time
from OE# high to the data bus driven to VCC/2 is taken
as tDFAC Characteristics.” section shows the toggle bit
timing diagrams. Figure 24 shows the differences be-
tween DQ2 and DQ6 in graphical form. See also the
subsection on DQ2: Toggle Bit II.
The RY/BY# is a dedicated, open-drain output pin
which indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, sev-
eral RY/BY# pins can be tied together in parallel with a
pull-up resistor to VCC
.
If the output is low (Busy), the device is actively eras-
ing or programming. (This includes programming in
the Erase Suspend mode.) If the output is high
(Ready), the device is in the read mode, the standby
mode, or the device is in the erase-suspend-read
mode.
START
Table 11 shows the outputs for RY/BY#.
Read DQ7–DQ0
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or com-
plete, or whether the device has entered the Erase
Suspend mode. Toggle Bit I may be read at any ad-
dress, and is valid after the rising edge of the final
WE# pulse in the command sequence (prior to the
program or erase operation), and during the sector
erase time-out.
Read DQ7–DQ0
No
Toggle Bit
= Toggle?
Yes
During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address cause
DQ6 to toggle. The system may use either OE# or
CE# to control the read cycles. When the operation is
complete, DQ6 stops toggling.
No
DQ5 = 1?
Yes
After an erase command sequence is written, if all sectors
selected for erasing are protected, DQ6 toggles for approxi-
mately 100 µs, then returns to reading array data. If not all
selected sectors are protected, the Embedded Erase algo-
rithm erases the unprotected sectors, and ignores the se-
lected sectors that are protected.
Read DQ7–DQ0
Twice
The system can use DQ6 and DQ2 together to determine
whether a sector is actively erasing or is erase-suspended.
When the device is actively erasing (that is, the Embedded
Erase algorithm is in progress), DQ6 toggles. When the de-
vice enters the Erase Suspend mode, DQ6 stops toggling.
However, the system must also use DQ2 to determine
which sectors are erasing or erase-suspended. Alterna-
tively, the system can use DQ7 (see the subsection on
DQ7: Data# Polling).
Toggle Bit
= Toggle?
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 µs after the program
command sequence is written, then returns to reading
array data.
Note: The system should recheck the toggle bit even if
DQ5 = “1” because the toggle bit may stop toggling as DQ5
changes to “1.” See the subsections on DQ6 and DQ2 for
more information.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
Figure 7. Toggle Bit Algorithm
May 13, 2002
Am41PDS3224D
29
P R E L I M I N A R Y
the toggle bit and DQ5 through successive read cy-
DQ2: Toggle Bit II
cles, determining the status as described in the previ-
ous paragraph. Alternatively, it may choose to perform
other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to de-
termine the status of the operation (top of Figure 7).
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
DQ5: Exceeded Timing Limits
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. (The system may use either OE# or CE# to con-
trol the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus-
pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era-
sure. Thus, both status bits are required for sector and
mode information. Refer to Table 11 to compare out-
puts for DQ2 and DQ6.
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under these
conditions DQ5 produces a “1,” indicating that the program
or erase cycle was not successfully completed.
The device may output a “1” on DQ5 if the system tries
to program a “1” to a location that was previously pro-
grammed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the
device halts the operation, and when the timing limit
has been exceeded, DQ5 produces a “1.”
Under both these conditions, the system must write
the reset command to return to the read mode (or to
the erase-suspend-read mode if the device was previ-
ously in the erase-suspend-program mode).
Figure 7 shows the toggle bit algorithm in flowchart
form, and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the DQ6: Toggle Bit I subsection.
Figure 23 shows the toggle bit timing diagram. Figure
24 shows the differences between DQ2 and DQ6 in
graphical form.
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not
erasure has begun. (The sector erase timer does not
apply to the chip erase command.) If additional
sectors are selected for erasure, the entire time-out
also applies after each additional sector erase com-
mand. When the time-out period is complete, DQ3
switches from a “0” to a “1.” If the time between addi-
tional sector erase commands from the system can be
assumed to be less than 50 µs, the system need not
monitor DQ3. See also the Sector Erase Command
Sequence section.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 7 for the following discussion. When-
ever the system initially begins reading toggle bit sta-
tus, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically,
the system would note and store the value of the tog-
gle bit after the first read. After the second read, the
system would compare the new value of the toggle bit
with the first. If the toggle bit is not toggling, the device
has completed the program or erase operation. The
system can read array data on DQ7–DQ0 on the fol-
lowing read cycle.
After the sector erase command is written, the system
should read the status of DQ7 (Data# Polling) or DQ6
(Toggle Bit I) to ensure that the device has accepted
the command sequence, and then read DQ3. If DQ3 is
“1,” the Embedded Erase algorithm has begun; all fur-
ther commands (except Erase Suspend) are ignored
until the erase operation is complete. If DQ3 is “0,” the
device will accept additional sector erase commands.
To ensure the command has been accepted, the sys-
tem software should check the status of DQ3 prior to
and following each subsequent sector erase com-
mand. If DQ3 is high on the second status check, the
last command might not have been accepted.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys-
tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is tog-
gling, since the toggle bit may have stopped toggling
just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the de-
vice did not completed the operation successfully, and
the system must write the reset command to return to
reading array data.
Table 11 shows the status of DQ3 relative to the other
status bits.
The remaining scenario is that the system initially de-
termines that the toggle bit is toggling and DQ5 has
not gone high. The system may continue to monitor
30
Am41PDS3224D
May 13, 2002
P R E L I M I N A R Y
Table 11. Write Operation Status
DQ7
DQ5
DQ2
Status
(Note 2)
DQ6
(Note 1)
DQ3
N/A
1
(Note 2)
RY/BY#
Embedded Program Algorithm
Embedded Erase Algorithm
Erase
Erase-Suspend-
Read
DQ7#
0
Toggle
Toggle
0
0
No toggle
Toggle
0
0
Standard
Mode
1
No toggle
0
N/A
Toggle
1
Suspended Sector
Erase
Suspend
Mode
Non-Erase
Suspended Sector
Data
Data
Data
0
Data
N/A
Data
N/A
1
0
Erase-Suspend-Program
DQ7#
Toggle
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
Refer to the section on DQ5 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
May 13, 2002
Am41PDS3224D
31
P R E L I M I N A R Y
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –55°C to +125°C
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . .–40°C to +85°C
Ambient Temperature
with Power Applied . . . . . . . . . . . . . . –40°C to +85°C
VCCf/VCCs Supply Voltage
Voltage with Respect to Ground
VCCf/VCCs for standard voltage range . . 1.8 V to 2.2 V
VCCf/VCCs (Note 1) . . . . . . . . . . . .–0.3 V to +2.5 V
RESET# (Note 2) . . . . . . . . . . . . . –0.5 V to +11 V
WP#/ACC . . . . . . . . . . . . . . . . . .–0.5 V to +10.5 V
All other pins (Note 1) . . . . . . –0.5 V to VCC +0.5 V
Output Short Circuit Current (Note 3) . . . . . . 100 mA
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V.
During voltage transitions, input or I/O pins may
overshoot VSS to –2.0 V for periods of up to 20 ns.
Maximum DC voltage on input or I/O pins is VCC +0.5 V.
See Figure 8. During voltage transitions, input or I/O pins
may overshoot to VCC +2.0 V for periods up to 20 ns. See
Figure 9.
2. Minimum DC input voltage on pins OE#, RESET#, and
WP#/ACC is –0.5 V. During voltage transitions, OE#,
WP#/ACC, and RESET# may overshoot VSS to –2.0 V
for periods of up to 20 ns. See Figure 8. Maximum DC
input voltage on pin RESET# is +12.5 V which may
overshoot to +14.0 V for periods up to 20 ns. Maximum
DC input voltage on WP#/ACC is +9.5 V which may
overshoot to +12.0 V for periods up to 20 ns.
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This
is a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.
20 ns
20 ns
20 ns
+0.8 V
VCC
+2.0 V
–0.5 V
–2.0 V
VCC
+0.5 V
2.0 V
20 ns
20 ns
20 ns
Figure 8. Maximum Negative
Overshoot Waveform
Figure 9. Maximum Positive
Overshoot Waveform
32
Am41PDS3224D
May 13, 2002
P R E L I M I N A R Y
FLASH DC CHARACTERISTICS
CMOS Compatible
Parameter
Parameter Description
Symbol
Test Conditions
Min
Typ
Max
Unit
ILI
Input Load Current
VIN = VSS to VCC, VCC = VCC max
VCC = VCC max; RESET# = 12.5 V
VOUT = VSS to VCC, VCC = VCC max
VCC = VCC max, WP#/ACC = VACC max
1 MHz
±1.0
35
µA
µA
µA
µA
ILIT
ILO
ILIA
RESET# Input Load Current
Output Leakage Current
ACC Input Leakage Current
±1.0
35
2.5
24
15
3
Flash VCC Active Inter-Page Read Current
(Notes 1, 2)
I
CC1f
CE#f = VIL, OE# = VIH,
mA
10 MHz
28
ICC2
ICC3
ICC4
f
f
Flash VCC Active Write Current (Notes 2, 3) CE#f = VIL, OE# = VIH
30
mA
µA
VCCf = VCC max, CE#f,
Flash VCC Standby Current (Note 2)
0.2
0.1
5
5
RESET# = VCC ± 0.3 V
VCCf = VCC max, WP#/ACC = VCCf ± 0.3 V,
RESET# = VSS ± 0.3 V
f
f
Flash VCC Reset Current (Note 2)
µA
µA
VCCf = VCC max, CE#f = VSS ± 0.3 V;
RESET# = VCC ± 0.3 V,
VIN = VCC ± 0.3 V or VSS ± 0.3 V
Flash VCC Automatic Sleep Mode Current
(Notes 2, 4)
ICC5
0.2
5
Flash VCC Active Read-While-Program
Current (Notes 1, 2, 5)
I
CC6f
CE#f = VIL, OE# = VIH
CE#f = VIL, OE# = VIH
30
30
55
55
mA
mA
Flash VCC Active Read-While-Erase Current
(Notes 1, 2, 5)
ICC7
f
Flash VCC Active
I
CC8f
Program-While-Erase-Suspended Current CE#f = VIL, OE# = VIH
(Note 2)
17
35
mA
mA
10 MHz
20 MHz
0.5
1
1
2
ICC9
f
Flash VCC Active Intra-Page Read Current CE#f = VIL, OE# = VIH
IACC
VIL
WP#/ACC Accelerated Program Current
Input Low Voltage
VCC = VCCMax, WP#/ACC = VACCMax
12
20
mA
V
–0.5
0.2 x VCC
VCC + 0.3
VIH
Input High Voltage
0.8 x VCC
V
Voltage for WP#/ACC Program Acceleration
and Sector Protection/Unprotection
V
ACC/VHH
8.5
9
9.5
V
Voltage for Sector Protection, Autoselect and
Temporary Sector Unprotect
VID
11
V
V
VOL
VOH1
VOH2
VLKO
Output Low Voltage
IOL = 4.0 mA, VCCf = VCCs = VCC min
0.1
IOH = –2.0 mA, VCCf = VCCs = VCC min
IOH = –100 µA, VCC = VCC min
0.85 x VCC
VCC–0.1
1.2
Output High Voltage
V
V
Flash Low VCC Lock-Out Voltage (Note 5)
1.5
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.
2. Maximum ICC specifications are tested with VCC = VCCmax.
3. ICC active while Embedded Erase or Embedded Program is in progress.
4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 200 nA.
5. Not 100% tested.
May 13, 2002
Am41PDS3224D
33
P R E L I M I N A R Y
SRAM DC AND OPERATING CHARACTERISTICS
Parameter
Symbol
Parameter Description
Input Leakage Current
Test Conditions
Min
–1.0
–1.0
Typ
Max
1.0
Unit
µA
ILI
VIN = VSS to VCC
CE1#s = VIH, CE2s = VIL or OE# =
ILO
Output Leakage Current
1.0
µA
V
IH or WE# = VIL, VIO= VSS to VCC
IIO = 0 mA, CE1#s = VIL, CE2s =
WE# = VIH, VIN = VIH or VIL
ICC
Operating Power Supply Current
2
2
mA
mA
Cycle time = 1 µs, 100% duty,
IIO = 0 mA, CE1#s ≤ 0.2 V,
CE2 ≥ VCC – 0.2 V, VIN ≤ 0.2 V or
VIN ≥ VCC – 0.2 V
ICC1s
Average Operating Current
Average Operating Current
Cycle time = Min., IIO = 0 mA,
100% duty, CE1#s = VIL, CE2s =
VIH, VIN = VIL = or VIH
ICC2s
17
mA
VOL
VOH
Output Low Voltage
Output High Voltage
IOL = 2.1 mA
0.2
V
V
IOH = –0.1 mA
1.4
0.5
CE1#s ≥ VCC – 0.2 V, CE2 ≥ VCC
0.2 V (CE1#s controlled) or CE2 ≤
0.2 V (CE2s controlled), CIOs =
–
ISB1
Standby Current (CMOS)
8
µA
VSS or VCC, Other input = 0 ~ VCC
Note: Typical values measured at VCC = 2.0 V, TA = 25°C. Not 100% tested.
34
Am41PDS3224D
May 13, 2002
P R E L I M I N A R Y
FLASH DC CHARACTERISTICS
Zero-Power Flash
25
20
15
10
5
0
0
500
1000
1500
2000
2500
3000
3500
4000
Time in ns
Note: Addresses are switching at 1 MHz
Figure 10. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
18
15
12
9
2.0 V
6
3
0
1
2
3
4
5
6
7
8
Frequency in MHz
Note: T = 25 °C
Figure 11. Typical ICC1 vs. Frequency
May 13, 2002
Am41PDS3224D
35
P R E L I M I N A R Y
TEST CONDITIONS
Table 12. Test Specifications
3.3 V
Test Condition
100, 110 ns Unit
1 TTL gate
Output Load
2.7 kΩ
Device
Under
Test
Output Load Capacitance, CL
(including jig capacitance)
30
pF
Input Rise and Fall Times
Input Pulse Levels
5
ns
V
C
L
6.2 kΩ
2.0
Input timing measurement reference
levels
1.0
1.0
V
V
Output timing measurement
reference levels
Note: Diodes are IN3064 or equivalent
Figure 12. Test Setup
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
2.0 V
0.0 V
1.0 V
1.0 V
Input
Measurement Level
Output
Figure 13. Input Waveforms and Measurement Levels
36
Am41PDS3224D
May 13, 2002
P R E L I M I N A R Y
AC CHARACTERISTICS
SRAM CE#s Timing
Parameter
Test Setup
AllSpeeds
Unit
JEDEC
Std
Description
—
tCCR
CE#s Recover Time
—
Min
0
ns
CE#f
tCCR
tCCR
CE1#s
CE2s
tCCR
tCCR
Figure 14. Timing Diagram for Alternating
Between SRAM to Flash
May 13, 2002
Am41PDS3224D
37
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
Read-Only Operations
Parameter
Speed Option
JEDEC
tAVAV
Std
tRC
Description
Test Setup
10
100
100
40
11
110
110
45
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time (Note 1)
Address to Output Delay
Page Read Cycle
Min
Max
Min
tAVQV
tACC
tPRC
CE#, OE# = VIL
tPACC Page Address to Output Delay
CE#, OE# = VIL
OE# = VIL
Max
Max
Max
Max
Max
40
45
tELQV
tGLQV
tEHQZ
tGHQZ
tCE
tOE
tDF
tDF
Chip Enable to Output Delay
100
35
110
45
Output Enable to Output Delay
Chip Enable to Output High Z (Notes 1, 3)
Output Enable to Output High Z (Notes 1, 3)
16
16
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First
tAXQX
tOH
Min
Min
Min
0
0
ns
ns
ns
Read
Output Enable Hold
tOEH
Toggle and
Data# Polling
Time (Note 1)
10
Notes:
1. Not 100% tested.
2. See Figure 12 and Table 12 for test specifications.
3. Measurements performed by placing a 50Ω termination on the data pin with a bias of VCC/2. The time from OE# high to the
data bus driven to VCC/2 is taken as tDFAC Characteristics.
tRC
Addresses Stable
tACC
Addresses
CE#f
tRH
tRH
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0 V
Figure 15. Conventional Read Operation Timings
38
Am41PDS3224D
May 13, 2002
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
Same page Addresses
A20 to A2
A1 to A0
Aa
Ab
Ac
Ad
tRC
tPRC
tPRC
tACC
tCE
CE#
tOE
OE#
tOEH
tDF
tPACC
tOH
tPACC
tOH
tPACC
tOH
WE#
tOH
Dd
High-Z
Output
Da
Db
Dc
Figure 16. Page Mode Read Timings
May 13, 2002
Am41PDS3224D
39
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
Description
All Speeds
Unit
JEDEC
Std
RESET# Pin Low (During Embedded Algorithms)
to Read Mode (See Note)
tReady
Max
20
µs
ns
RESET# Pin Low (NOT During Embedded
Algorithms) to Read Mode (See Note)
tReady
Max
500
tRP
tRH
tRPD
tRB
RESET# Pulse Width
Min
Min
Min
Min
500
200
20
ns
ns
µs
ns
Reset High Time Before Read (See Note)
RESET# Low to Standby Mode
RY/BY# Recovery Time
0
Note: Not 100% tested.
RY/BY#
CE#f, OE#
RESET#
tRH
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#f, OE#
RESET#
tRP
Figure 17. Reset Timings
40
Am41PDS3224D
May 13, 2002
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
Flash Erase and Program Operations
Parameter
Speed Options
Unit
JEDEC
tAVAV
Std
tWC
tAS
Description
10
11
Write Cycle Time (Note 1)
Address Setup Time (WE# to Address)
Min
Min
100
110
ns
ns
tAVWL
0
15
60
0
Address Setup Time to OE# or CE#f Low During Toggle Bit
Polling
tASO
tAH
Min
Min
Min
ns
ns
ns
tWLAX
Address Hold Time (WE# to Address)
Address Hold Time From CE#f or OE# High During Toggle Bit
Polling
tAHT
tDVWH
tWHDX
tDS
tDH
Data Setup Time
Data Hold Time
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Typ
60
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
Read
OE# Hold Time
0
tOEH
Toggle and Data# Polling
20
20
0
tOEPH
tGHEL
tGHWL
tWS
Output Enable High During Toggle Bit Polling
Read Recovery Time Before Write (OE# High to CE#f Low)
Read Recovery Time Before Write (OE# High to WE# Low)
WE# Setup Time (CE#f to WE#)
tGHEL
tGHWL
tWLEL
tELWL
tEHWH
tWHEH
tWLWH
tELEH
tWHDL
0
0
tCS
CE#f Setup Time (WE# to CE#f)
0
tWH
WE# Hold Time (CE#f to WE#)
0
tCH
CE#f Hold Time (CE#f to WE#)
0
tWP
Write Pulse Width
60
60
60
0
tCP
CE#f Pulse Width
tWPH
tSR/W
Write Pulse Width High
Latency Between Read and Write Operations
tWHWH1
tWHWH1
tWHWH2
tWHWH1 Programming Operation (Note 2)
11
Accelerated Programming Operation,
Word or Byte (Note 2)
tWHWH1
Typ
5
µs
tWHWH2 Sector Erase Operation (Note 2)
Typ
Min
Min
Max
1
50
0
sec
µs
tVCS
tRB
VCCf Setup Time (Note 1)
Write Recovery Time From RY/BY#
Program/Erase Valid To RY/BY# Delay
ns
tBUSY
90
ns
Notes:
1. Not 100% tested.
2. See the “Flash Erase And Programming Performance” section for more information.
May 13, 2002
Am41PDS3224D
41
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tAS
PA
tWC
Addresses
555h
PA
PA
tAH
CE#f
OE#
tCH
tGHWL
tWHWH1
tWP
WE#
tWPH
tCS
tDS
tDH
PD
DOUT
A0h
Status
Data
tBUSY
tRB
RY/BY#
VCC
f
tVCS
Notes:
1. PA = program address, PD = program data, DOUT is the true data at the program address.
Figure 18. Program Operation Timings
VHH
VIL or VIH
WP#/ACC
VIL or VIH
tVHH
tVHH
Figure 19. Accelerated Program Timing Diagram
42
Am41PDS3224D
May 13, 2002
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
Erase Command Sequence (last two cycles)
Read Status Data
VA
tAS
tWC
VA
Addresses
CE#f
2AAh
SADD
555h for chip erase
tAH
tGHWL
tCH
OE#
tWP
WE#
tWPH
tWHWH2
tCS
tDS
tDH
In
Data
Complete
55h
30h
Progress
10 for Chip Erase
tBUSY
tRB
RY/BY#
tVCS
VCC
f
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Flash Write Operation Status”).
Figure 20. Chip/Sector Erase Operation Timings
May 13, 2002
Am41PDS3224D
43
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
tWC
Valid PA
tWC
tRC
tWC
Valid PA
Valid RA
Valid PA
Addresses
tAH
tCPH
tACC
tCE
CE#f
tCP
tOE
OE#
tOEH
tGHWL
tWP
WE#
tDF
tWPH
tDS
tOH
tDH
Valid
Out
Valid
In
Valid
In
Valid
In
Data
tSR/W
WE# Controlled Write Cycle
Read Cycle
CE#f Controlled Write Cycles
Figure 21. Back-to-back Read/Write Cycle Timings
tRC
Addresses
CE#f
VA
tACC
tCE
VA
VA
tCH
tOE
OE#
WE#
tOEH
tDF
tOH
High Z
High Z
DQ7
Valid Data
Complement
Complement
True
DQ6–DQ0
Status Data
True
Valid Data
Status Data
tBUSY
RY/BY#
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
Figure 22. Data# Polling Timings (During Embedded Algorithms)
44
Am41PDS3224D
May 13, 2002
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
tAHT
tAS
Addresses
CE#f
tAHT
tASO
tCEPH
tOEH
WE#
tOEPH
OE#
tDH
Valid Data
tOE
Valid
Status
Valid
Status
Valid
Status
DQ6/DQ2
RY/BY#
Valid Data
(first read)
(second read)
(stops toggling)
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status
read cycle, and array data read cycle
Figure 23. Toggle Bit Timings (During Embedded Algorithms)
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase
Complete
WE#
Erase
Erase Suspend
Read
DQ6
DQ2
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE#f to
toggle DQ2 and DQ6.
Figure 24. DQ2 vs. DQ6
May 13, 2002
Am41PDS3224D
45
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
Temporary Sector/Sector Block Unprotect
Parameter
All Speed Options
Unit
JEDEC
Std
tVIDR
tVHH
Description
VID Rise and Fall Time (See Note)
VHH Rise and Fall Time (See Note)
Min
Min
500
500
ns
ns
RESET# Setup Time for Temporary
Sector/Sector Block Unprotect
tRSP
Min
Min
4
4
µs
µs
RESET# Hold Time from RY/BY# High for
Temporary Sector/Sector Block Unprotect
tRRB
Note: Not 100% tested.
VID
VID
RESET#
VSS, VIL,
or VIH
VSS, VIL,
or VIH
tVIDR
tVIDR
Program or Erase Command Sequence
CE#f
WE#
tRRB
tRSP
RY/BY#
Figure 25. Temporary Sector/Sector Block Unprotect
Timing Diagram
46
Am41PDS3224D
May 13, 2002
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
VID
VIH
RESET#
SADD, A6,
A1, A0
Valid*
60h
Valid*
Valid*
Status
Sector/Sector Block Protect or Unprotect
Verify
40h
Data
60h
Sector/Sector Block Protect: 150 µs,
Sector/Sector Block Unprotect: 15 ms
1 µs
CE#f
WE#
OE#
* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
Figure 26. Sector/Sector Block Protect and Unprotect
Timing Diagram
May 13, 2002
Am41PDS3224D
47
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
Alternate CE#f Controlled Erase and Program Operations
Parameter
Speed Options
Unit
JEDEC
tAVAV
Std
tWC
tAS
Description
10
11
Write Cycle Time (Note 1)
Address Setup Time (WE# to Address)
Min
Min
100
110
ns
ns
tAVWL
0
15
60
0
Address Setup Time to CE#f Low During Toggle
Bit Polling
tASO
tAH
Min
Min
Min
ns
ns
ns
tELAX
Address Hold Time
Address Hold time from CE#f or OE# High During
Toggle Bit Polling
tAHT
tDVEH
tEHDX
tDS
tDH
Data Setup Time
Data Hold Time
Min
Min
60
0
ns
ns
Read Recovery Time Before Write
(OE# High to WE# Low)
tGHEL
tGHEL
Min
0
ns
tWLEL
tEHWH
tELEH
tWS
tWH
WE# Setup Time
Min
Min
Min
Min
Typ
0
ns
ns
ns
ns
µs
WE# Hold Time
0
tCP
CE#f Pulse Width
60
60
16
tEHEL
tCPH
CE#f Pulse Width High
Programming Operation (Note 2)
tWHWH1
tWHWH1
Accelerated Programming Operation,
Word or Byte (Note 2)
tWHWH1
tWHWH2
Notes:
tWHWH1
tWHWH2
Typ
Typ
5
1
µs
Sector Erase Operation (Note 2)
sec
1. Not 100% tested.
2. See the “Flash Erase And Programming Performance” section for more information.
48
Am41PDS3224D
May 13, 2002
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
555 for program
2AA for erase
PA for program
SADD for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tAS
tAH
tWH
WE#
tGHEL
OE#
tWHWH1 or 2
tCP
CE#f
tWS
tCPH
tDS
tBUSY
tDH
DQ7#
DOUT
Data
tRH
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.
Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program) Operation Timings
May 13, 2002
Am41PDS3224D
49
P R E L I M I N A R Y
SRAM AC CHARACTERISTICS
Read Cycle
Parameter
Description
Symbol
10, 11
Unit
tRC
tAA
CO1, tCO2
tOE
Read Cycle Time
Min
Max
Max
Max
Max
Min
70
70
70
35
70
10
10
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
Chip Enable to Output
Output Enable Access Time
LB#s, UB#s to Access Time
t
tBA
tLZ1, tLZ2
tBLZ
Chip Enable (CE1#s Low and CE2s High) to Low-Z Output
UB#, LB# Enable to Low-Z Output
Min
tOLZ
Output Enable to Low-Z Output
Min
t
HZ1, tHZ2
tBHZ
Chip Disable to High-Z Output
Max
Max
Max
Min
25
25
25
10
UB#s, LB#s Disable to High-Z Output
Output Disable to High-Z Output
tOHZ
tOH
Output Data Hold from Address Change
tRC
Address
tAA
tOH
Data Valid
Data Out
Previous Data Valid
Note: CE1#s = OE# = VIL, CE2s = WE# = VIH, UB#s and/or LB#s = VIL
Figure 28. SRAM Read Cycle—Address Controlled
50
Am41PDS3224D
May 13, 2002
P R E L I M I N A R Y
SRAM AC CHARACTERISTICS
tRC
Address
tAA
tCO1
tOH
CS#1
CS2
tCO2
tBA
tHZ
UB#, LB#
OE#
tBHZ
tOE
tOLZ
tBLZ
tLZ
tOHZ
Data Out
High-Z
Data Valid
Figure 29. SRAM Read Cycle
Notes:
1. WE# = VIH, if CIOs is low, ignore UB#s/LB#s timing.
2. HZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output
t
voltage levels.
3. At any given temperature and voltage condition, tHZ (Max.) is less than tLZ (Min.) both for a given device and from device to device
interconnection.
May 13, 2002
Am41PDS3224D
51
P R E L I M I N A R Y
SRAM AC CHARACTERISTICS
Write Cycle
Parameter
Description
Symbol
10, 11
Unit
tWC
tCw
tAS
Write Cycle Time
Min
Min
Min
Min
Min
Min
Min
Min
Max
Min
Min
min
70
60
0
ns
ns
ns
ns
ns
ns
ns
Chip Enable to End of Write
Address Setup Time
tAW
tBW
tWP
tWR
Address Valid to End of Write
UB#s, LB#s to End of Write
Write Pulse Time
60
60
50
0
Write Recovery Time
0
tWHZ
Write to Output High-Z
ns
20
30
0
tDW
tDH
tOW
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
ns
ns
ns
5
tWC
Address
tCW
(See Note 2)
tWR (See Note 3)
CS1#s
CS2s
tAW
tCW
(See Note 2)
tBW
UB#s, LB#s
WE#
tWP
(See Note 5)
tAS
(See Note 4)
tDH
tDW
Data In
High-Z
Data Valid
High-Z
tWHZ
tOW
Data Undefined
Data Out
Notes:
1. WE# controlled, if CIOs is low, ignore UB#s and LB#s timing.
2.
3.
4.
t
CW is measured from CE1#s going low to the end of write.
WR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high.
AS is measured from the address valid to the beginning of write.
t
t
5. A write occurs during the overlap (tWP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when
asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A
write ends at the earliest transition when CE1#s goes high and WE# goes high. The tWP is measured from the beginning of write
to the end of write.
Figure 30. SRAM Write Cycle—WE# Control
52
Am41PDS3224D
May 13, 2002
P R E L I M I N A R Y
SRAM AC CHARACTERISTICS
tWC
Address
tAS (See Note 2 )
tCW
tWR (See Note 4)
(See Note 3)
CE1#s
tAW
CE2s
tBW
UB#s, LB#s
tWP
(See Note 5)
WE#
tDW
tDH
Data Valid
Data In
Data Out
High-Z
High-Z
Notes:
1. CE1#s controlled, if CIOs is low, ignore UB#s and LB#s timing.
2.
3.
4.
t
CW is measured from CE1#s going low to the end of write.
WR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high.
AS is measured from the address valid to the beginning of write.
t
t
5. A write occurs during the overlap (tWP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when
asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A
write ends at the earliest transition when CE1#s goes high and WE# goes high. The tWP is measured from the beginning of write
to the end of write.
Figure 31. SRAM Write Cycle—CE1#s Control
May 13, 2002
Am41PDS3224D
53
P R E L I M I N A R Y
SRAM AC CHARACTERISTICS
tWC
Address
CE1#s
tCW
(See Note 2)
tWR (See Note 3)
tAW
tCW (See Note 2)
CE2s
tBW
UB#s, LB#s
tAS
tWP
(See Note 5)
(See Note 4)
WE#
Data In
tDW
tDH
Data Valid
Data Out
High-Z
High-Z
Notes:
1. UB#s and LB#s controlled, CIOs must be high.
2.
3.
4.
t
CW is measured from CE1#s going low to the end of write.
WR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high.
AS is measured from the address valid to the beginning of write.
t
t
5. A write occurs during the overlap (tWP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when
asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A
write ends at the earliest transition when CE1#s goes high and WE# goes high. The tWP is measured from the beginning of write
to the end of write.
Figure 32. SRAM Write Cycle—UB#s and LB#s Control
54
Am41PDS3224D
May 13, 2002
P R E L I M I N A R Y
FLASH ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ (Note 1) Max (Note 2)
Unit
sec
sec
Comments
Sector Erase Time
Chip Erase Time
1
10
Excludes 00h programming
prior to erasure (Note 4)
93
Excludes system level
overhead (Note 5)
Word Program Time
16
5
360
µs
µs
Accelerated Byte/Word Program Time
Chip Program Time
Word Mode
20
100
(Note 3)
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 2.0 V VCC, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 1.8 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table
10 for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.
FLASH LATCHUP CHARACTERISTICS
Description
Min
Max
Input voltage with respect to VSS on all pins except I/O pins
(including OE#, and RESET#)
–1.0 V
12.5 V
Input voltage with respect to VSS on all I/O pins
VCC Current
–1.0 V
VCC + 1.0 V
+100 mA
–100 mA
Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.
PACKAGE PIN CAPACITANCE
Parameter
Symbol
Test Setup
Typ
Max
Unit
Description
CIN
Input Capacitance
VIN = 0
VOUT = 0
VIN = 0
VIN = 0
11
12
14
17
14
16
16
20
pF
pF
pF
pF
COUT
CIN2
Output Capacitance
Control Pin Capacitance
WP#/ACC Pin Capacitance
CIN3
Note: 7.Test conditions TA = 25°C, f = 1.0 MHz.
FLASH DATA RETENTION
Parameter Description
Test Conditions
Min
10
Unit
Years
Years
150°C
125°C
Minimum Pattern Data Retention Time
20
May 13, 2002
Am41PDS3224D
55
P R E L I M I N A R Y
SRAM DATA RETENTION
Parameter
Symbol
Parameter Description
Min
Typ
Max
2.2
3
Unit
V
Test Setup
VDR
VCC for Data Retention
Data Retention Current
CS1#s ≥ VCC – 0.2 V (Note 1)
1.0
VCC = 3.0 V, CE1#s ≥ VCC – 0.2 V
(Note 1)
0.5
(Note 2)
IDR
µA
tSDR
tRDR
Data Retention Set-Up Time
Recovery Time
0
ns
ns
See data retention waveforms
tRC
Notes:
1. CE1#s ≥ VCC – 0.2 V, CE2s ≥ VCC – 0.2 V (CE1#s controlled) or CE2s ≤ 0.2 V (CE2s controlled), CIOs = VSS or VCC
.
2. Typical values are not 100% tested.
Data Retention Mode
tRDR
tSDR
VCC
1.8V
1.4V
VDR
CE1#s ≥ VCC
-0.2 V
CE1#s
GND
Figure 33. CE1#s Controlled Data Retention Mode
Data Retention Mode
VCC
1.8 V
CE2s
tSDR
tRDR
VDR
<
CE2s 0.2 V
0.4 V
GND
Figure 34. CE2s Controlled Data Retention Mode
56
Am41PDS3224D
May 13, 2002
P R E L I M I N A R Y
PHYSICAL DIMENSIONS
FLB073—73-Ball Fine-Pitch Grid Array 8 x 11.6 mm
May 13, 2002
Am41PDS3224D
57
P R E L I M I N A R Y
REVISION SUMMARY
Figure 30, SRAM Write Cycle—WE# Control
Corrected tBW in Data Out waveform to tWHZ
Revision A (February 18, 2002)
Initial release.
.
Revision A+1 (May 13, 2002)
Distinctive Characteristics
Modified text in “High Performance” bullet. Deleted
reference to 48-ball FBGA package.
Trademarks
Copyright © 2002 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
58
Am41PDS3224D
May 13, 2002
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