AM79C961KC [AMD]
PCnetTM-ISA+ Jumperless Single-Chip Ethernet Controller for ISA; PCnetTM -ISA +无跳线单芯片以太网控制器ISA
| 型号： | AM79C961KC |
| 厂家： | 
AMD |
| 描述： | PCnetTM-ISA+ Jumperless Single-Chip Ethernet Controller for ISA |
| 文件： | 总173页 (文件大小：1041K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
Advanced
Micro
Am79C961
PCnetTM-ISA+ Jumperless Single-Chip Ethernet Controller
for ISA
Devices
DISTINCTIVE CHARACTERISTICS
■ Single-chip Ethernet controller for the Industry
Standard Architecture (ISA) and Extended
Industry Standard Architecture (EISA) buses
■ Look Ahead Packet Processing (LAPP) allows
protocol analysis to begin before end of
receive frame
■ Supports IEEE 802.3/ANSI 8802-3 and Ethernet
■ Supports 4 DMA channels on chip
■ Supports 16 I/O locations
standards
■ Direct interface to the ISA or EISA bus
■ Supports 16 boot PROM locations
■ Software compatible with AMD’s Am7990
■ Provides integrated Attachment Unit Interface
(AUI) and 10BASE-T transceiver with 2 modes
of port selection:
LANCE register and descriptor architecture
■ Low power, CMOS design with sleep mode
allows reduced power consumption for critical
battery powered applications
— Automatic selection of AUI or 10BASE-T
— Software selection of AUI or 10BASE-T
■ Individual 136-byte transmit and 128-byte
receive FIFOs provide packet buffering for
increased system latency, and support the
following features:
■ Automatic Twisted Pair receive polarity
detection and automatic correction of the
receive polarity
■ Supports bus-master and shared-memory
— Automatic retransmission with no FIFO
reload
architectures to fit in any PC application
■ Supports edge and level-sensitive interrupts
— Automatic receive stripping and transmit
padding (individually programmable)
■ DMA Buffer Management Unit for reduced CPU
intervention which allows higher throughput by
by-passing the platform DMA
— Automatic runt packet rejection
— Automatic deletion of received collision
frames
■ JTAG Boundary Scan (IEEE 1149.1) test access
port interface for board level production test
■ Dynamic transmit FCS generation program-
■ Integrated Manchester Encoder/Decoder
mable on a frame-by-frame basis
■ Supports the following types of network
■ Single +5 V power supply
interfaces:
■ Internal/external loopback capabilities
— AUI to external 10BASE2, 10BASE5,
10BASE-T or 10BASE-F MAU
■ Supports 8K, 16K, 32K, and 64K Boot PROMs
or Flash for diskless node applications
— Internal 10BASE-T transceiver with Smart
Squelch to Twisted Pair medium
■ Supports Microsoft’s Plug and Play System
configuration for jumperless designs
■ Supports LANCE General Purpose Serial
■ Supports staggered AT bus drive for reduced
Interface (GPSI)
noise and ground bounce
■ 132-pin PQFP package
■ Supports 8 interrupts on chip
GENERAL DESCRIPTION
The PCnet-ISA+ controller, a single-chip Ethernet con-
troller, is a highly integrated system solution for the
PC-AT Industry Standard Architecture (ISA ) architec-
ture. It is designed to provide flexibility and compatibility
with any existing PC application. This highly integrated
132-pin VLSI device is specifically designed to reduce
parts count and cost, and addresses applications where
higher system throughput is desired. The PCnet-ISA+
controller is fabricated with AMD’s advanced low-power
CMOS process to provide low standby current for power
sensitive applications.
ThePCnet-ISA+ controllerisaDMA-baseddevicewitha
dual architecture that can be configured in two different
operating modes to suit a particular PC application. In
the Bus Master Mode all transfers are performed using
Publication# 18183 Rev. B Amendment/0
This document contains information on a product under development at Advanced Micro Devices, Inc.
The information is intended to help you to evaluate this product. AMD reserves the right to change or
discontinue work on this proposed product without notice.
1-475
Issue Date: April 1994
AMD
P R E L I M I N A R Y
the integrated DMA controller. This configuration en-
hances system performance by allowing the
PCnet-ISA+ controller to bypass the platform DMA con-
troller and directly address the full 24-bit memory space.
The implementation of Bus Master Mode allows mini-
mum parts count for the majority of PC applications. The
PCnet-ISA+ controller can be configured to perform
Shared Memory operations for compatibility with low-
end machines, such as PC/XTs that do not support Bus
Master and high-end machines that require local packet
buffering for increased system latency.
External remote boot and Ethernet physical address
PROMs and Electrically Erasable Proms are also
supported.
This advanced Ethernet controller has the built-in capa-
bility of automatically selecting either the AUI port or the
Twisted Pair transceiver. Only one interface is active at
any one time. The individual 136-byte transmit and
128-byte receive FIFOs optimize system overhead, pro-
viding sufficient latency during packet transmission and
reception, and minimizing intervention during normal
network error recovery. The integrated Manchester en-
coder/decodereliminatestheneedforanexternalSerial
Interface Adapter (SIA) in the node system. If support
for an external encoding/decoding scheme is desired,
the embedded General Purpose Serial Interface (GPSI)
allows direct access to/from the MAC. In addition, the
device provides programmable on-chip LED drivers for
transmit, receive, collision, receive polarity, link integrity
and activity, or jabber status. The PCnet-ISA+ controller
also provides an External Address Detection Interface
(EADI ) to allow external hardware address filtering in
internetworking applications.
The PCnet-ISA+ controller is designed to directly inter-
face with the ISA or EISA system bus. It contains an ISA
Plug and Play bus interface unit, DMA Buffer Manage-
ment Unit, 802.3 Media Access Control function,
individual 136-byte transmit and 128-byte receive
FIFOs, IEEE 802.3 defined Attachment Unit Interface
(AUI), and a Twisted Pair Transceiver Media Attach-
ment Unit. The PCnet-ISA+ controller is also register
compatible with the LANCE (Am7990) Ethernet control-
ler and PCnet-ISA. The DMA Buffer Management Unit
supports the LANCE descriptor software model.
RELATED PRODUCTS
Part No.
Description
Am79C98
Am79C100
Am7996
Twisted Pair Ethernet Transceiver (TPEX)
Twisted Pair Ethernet Transceiver Plus (TPEX+)
IEEE 802.3/Ethernet/Cheapernet Transceiver
Integrated Multiport Repeater Plus (IMR+ )
Am79C981
Am79C987
Am79C940
Am79C90
Am79C960
Am79C965
Am79C970
Hardware Implemented Management Information Base (HIMIB )
Media Access Controller for Ethernet (MACE )
CMOS Local Area Network Controller for Ethernet (C-LANCE)
PCnet-ISA Single-Chip Ethernet Controller (for ISA bus)
PCnet-32 Single-Chip 32-Bit Ethernet Controller (for 386, 486, VL local buses)
PCnet-PCI Single-Chip Ethernet Controller (for PCI bus)
1-476
Am79C961
P R E L I M I N A R Y
AMD
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of:
AM79C961
K
C
\W
ALTERNATE PACKAGING OPTION
\W = Trimmed and Formed (PQB132)
OPTIONAL PROCESSING
Blank = Standard Processing
TEMPERATURE RANGE
C = Commercial (0° to +70°C)
PACKAGE TYPE (per Prod. Nomenclature/16-038)
K = Molded Carrier Ring Plastic Quad Flat Pack
(PQB132)
SPEED
Not Applicable
DEVICE NUMBER/DESCRIPTION
Am79C961
Valid Combinations
Valid Combinations
AM79C961 KC, KC\W
The Valid Combinations table lists configurations
planned to be supported in volume for this device.
Consult the local AMD sales office to confirm
availability of specific valid combinations and to
check on newly released combinations.
1-477
Am79C961
AMD
TABLE OF CONTENTS
P R E L I M I N A R Y
DISTINCTIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-475
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-475
RELATED PRODUCTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-476
ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-477
BLOCK DIAGRAM: BUS MASTER MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-484
CONNECTION DIAGRAM: BUS MASTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-484
PIN DESIGNATIONS: BUS MASTER
LISTED BY PIN NUMBER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-486
LISTED BY PIN NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-487
LISTED BY GROUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-488
PIN DESCRIPTION: BUS MASTER MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-490
ISA INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-490
BOARD INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-491
BLOCK DIAGRAM: SHARED MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-493
CONNECTION DIAGRAM: SHARED MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-494
PIN DESIGNATIONS: SHARED MEMORY
LISTED BY PIN NUMBER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-495
LISTED BY PIN NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-496
LISTED BY GROUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-497
PIN DESCRIPTION: SHARED MEMORY MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-499
ISA INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-499
BOARD INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-500
PIN DESCRIPTION: NETWORK INTERFACES (mode independent) . . . . . . . . . . . . . . . . 1-502
AUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-502
TWISTED PAIR INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-502
IEEE 1149.1 TEST ACCESS PORT INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-502
PIN DESCRIPTION: POWER SUPPLIES (mode independent) . . . . . . . . . . . . . . . . . . . . . 1-502
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-503
BUS MASTER MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-503
SHARED MEMORY MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-505
NETWORK INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-505
PLUG AND PLAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-507
DETAILED FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-514
EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-514
SERIAL EEPROM BYTE MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-515
PLUG AND PLAY REGISTER MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-517
PLUG AND PLAY REGISTER LOCATIONS DETAILED DESCRIPTION . . . . . . . . . . . 1-518
SHARED MEMORY CONFIGURATION BITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-520
USE WITHOUT EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-521
EXTERNAL SCAN CHAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-521
FLASH PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-521
OPTIONAL IEEE ADDRESS PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-521
EISA CONFIGURATION REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-521
1-478
Am79C961
P R E L I M I N A R Y
AMD
BUS INTERFACE UNIT (BIU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-521
DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-521
1. Initialization Block DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-521
2. Descriptor DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-522
3. Burst-Cycle DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-522
BUFFER MANAGEMENT UNIT (BMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-522
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-522
Reinitialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-522
Buffer Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-522
Descriptor Rings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-522
Descriptor Ring Access Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-523
Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-523
Transmit Descriptor Table Entry (TDTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-525
Receive Descriptor Table Entry (RDTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-526
MEDIA ACCESS CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-527
Transmit and Receive Message Data Encapsulation . . . . . . . . . . . . . . . . . . . . . . . 1-527
Media Access Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-528
MANCHESTER ENCODER/DECODER (MENDEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-530
External Crystal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-530
External Clock Drive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-530
MENDEC Transmit Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-530
Transmitter Timing and Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-530
Receive Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-531
Input Signal Conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-531
Clock Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-531
PLL Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-531
Carrier Tracking and End of Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-532
Data Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-532
Differential Input Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-532
Collision Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-532
Jitter Tolerance Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-532
Attachment Unit Interface (AUI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-532
TWISTED PAIR TRANSCEIVER (T-MAU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-532
Twisted Pair Transmit Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-533
Twisted Pair Receive Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-533
Link Test Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-533
Polarity Detection and Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-533
Twisted Pair Interface Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-534
Collision Detect Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-534
Signal Quality Error (SQE) Test (Heartbeat) Function . . . . . . . . . . . . . . . . . . . . . . 1-534
Jabber Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-534
Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-534
EADI (External Address Detection Interface ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-534
GENERAL PURPOSE SERIAL INTERFACE (GPSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-536
IEEE 1149.1 TEST ACCESS PORT INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-537
Boundary Scan Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-537
1-479
Am79C961
AMD
P R E L I M I N A R Y
TAP FSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-537
Supported Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-537
Instruction Register and Decoding Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-537
Boundary Scan Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-537
Other Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-537
POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-538
ACCESS OPERATIONS (SOFTWARE)
I/O Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-538
I/O Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-538
IEEE Address Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-538
Boot PROM Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-538
Static RAM Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-538
BUS CYCLES (HARDWARE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-538
Bus Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-539
Refresh Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-539
Address PROM Cycles External PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-539
Ethernet Controller Register Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-540
RESET Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-540
ISA Configuration Register Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-540
Boot PROM Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-540
Current Master Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-540
Master Mode Memory Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-541
Master Mode Memory Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-541
Shared Memory Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-541
Address PROM Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-541
Ethernet Controller Register Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-542
RESET Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-542
ISA Configuration Register Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-542
Boot PROM Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-542
Static RAM Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-542
TRANSMIT OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-544
Transmit Function Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-544
Automatic Pad Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-544
Transmit FCS Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-544
Transmit Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-544
Loss of Carrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-545
RECEIVE OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-545
Receive Function Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-545
Automatic Pad Stripping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-546
Receive FCS Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-546
Receive Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-546
LOOPBACK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-547
LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-548
PCnet-ISA+ CONTROLLER REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-549
REGISTER ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-549
CONTROL AND STATUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-549
1-480
Am79C961
P R E L I M I N A R Y
AMD
CSR0: PCnet-ISA+ Controller Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-549
CSR1: IADR[15:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-551
CSR2: IADR[23:16] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-551
CSR3: Interrupt Masks and Deferral Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-551
CSR4: Test and Features Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-552
CSR6: RCV/XMT Descriptor Table Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-554
CSR8: Logical Address Filter, LADRF[15:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-554
CSR9: Logical Address Filter, LADRF[31:16] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-554
CSR10: Logical Address Filter, LADRF[47:32] . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-554
CSR11: Logical Address Filter, LADRF[63:48] . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-554
CSR12: Physical Address Register, PADR[15:0] . . . . . . . . . . . . . . . . . . . . . . . . . 1-554
CSR13: Physical Address Register, PADR[31:16] . . . . . . . . . . . . . . . . . . . . . . . . 1-555
CSR14: Physical Address Register, PADR[47:32] . . . . . . . . . . . . . . . . . . . . . . . . 1-555
CSR15: Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-555
CSR16: Initialization Block Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-557
CSR17: Initialization Block Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-557
CSR18–19: Current Receive Buffer Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-557
CSR20–21: Current Transmit Buffer Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-557
CSR22–23: Next Receive Buffer Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-557
CSR24–25: Base Address of Receive Ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-557
CSR26–27: Next Receive Descriptor Address . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-558
CSR28–29: Current Receive Descriptor Address . . . . . . . . . . . . . . . . . . . . . . . . . 1-558
CSR30–31: Base Address of Transmit Ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-558
CSR32–33: Next Transmit Descriptor Address . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-558
CSR34–35: Current Transmit Descriptor Address . . . . . . . . . . . . . . . . . . . . . . . . . 1-558
CSR36–37: Next Next Receive Descriptor Address . . . . . . . . . . . . . . . . . . . . . . . 1-558
CSR38–39: Next Next Transmit Descriptor Address . . . . . . . . . . . . . . . . . . . . . . . 1-558
CSR40–41: Current Receive Status and Byte Count . . . . . . . . . . . . . . . . . . . . . . 1-558
CSR42–43: Current Transmit Status and Byte Count . . . . . . . . . . . . . . . . . . . . . . 1-558
CSR44–45: Next Receive Status and Byte Count . . . . . . . . . . . . . . . . . . . . . . . . . 1-559
CSR46: Poll Time Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-559
CSR47: Polling Interval . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-559
CSR48–49: Temporary Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-559
CSR50–51: Temporary Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-559
CSR52–53: Temporary Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-559
CSR54–55: Temporary Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-559
CSR56–57: Temporary Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-560
CSR58–59: Temporary Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-560
CSR60–61: Previous Transmit Descriptor Address . . . . . . . . . . . . . . . . . . . . . . . . 1-560
CSR62–63: Previous Transmit Status and Byte Count . . . . . . . . . . . . . . . . . . . . . 1-560
CSR64–65: Next Transmit Buffer Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-560
CSR66–67: Next Transmit Status and Byte Count . . . . . . . . . . . . . . . . . . . . . . . . 1-560
CSR68–69: Transmit Status Temporary Storage . . . . . . . . . . . . . . . . . . . . . . . . . 1-560
CSR70–71: Temporary Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-560
CSR72: Receive Ring Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-561
CSR74: Transmit Ring Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-561
CSR76: Receive Ring Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-561
1-481
Am79C961
AMD
P R E L I M I N A R Y
CSR78: Transmit Ring Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-561
CSR80: Burst and FIFO Threshold Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-561
CSR82: Bus Activity Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-561
CSR84–85: DMA Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-562
CSR86: Buffer Byte Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-563
CSR88–89: Chip ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-563
CSR92: Ring Length Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-563
CSR94: Transmit Time Domain Reflectometry Count . . . . . . . . . . . . . . . . . . . . . . 1-563
CSR96–97: Bus Interface Scratch Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-563
CSR98–99: Bus Interface Scratch Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-563
CSR104–105: SWAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-563
CSR108–109: Buffer Management Scratch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-564
CSR112: Missed Frame Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-564
CSR114: Receive Collision Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-564
CSR124: Buffer Management Unit Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-564
ISA BUS CONFIGURATION REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-564
ISACSR0: Master Mode Read Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-565
ISACSR1: Master Mode Write Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-565
ISACSR2: Miscellaneous Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-565
ISACSR3: EEPROM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-566
ISACSR4: Link Integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-567
ISACSR5: Default: RCV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-567
ISACSR6: Default: RCVPOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-568
ISACSR7: Default: XMT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-568
ISACSR8: Software Configuration (Read-Only Register) . . . . . . . . . . . . . . . . . . . . 1-569
INITIALIZATION BLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-569
RLEN and TLEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-569
RDRA and TDRA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-570
LADRF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-570
PADR
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-570
MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-570
RECEIVE DESCRIPTORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-571
RMD0
RMD1
RMD2
RMD3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-571
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-571
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-572
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-572
TRANSMIT DESCRIPTORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-572
TMD0
TMD1
TMD2
TMD3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-572
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-572
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-573
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-573
REGISTER SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-575
SYSTEM APPLICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-578
ISA BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-578
Compatibility Consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-578
1-482
Am79C961
P R E L I M I N A R Y
AMD
Bus Masters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-578
Shared Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-578
OPTIONAL ADDRESS PROM INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-582
BOOT PROM INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-582
STATIC RAM INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-582
AUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-582
EEPROM INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-582
10BASE-T INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-582
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-584
OPERATING RANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-584
DC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-584
SWITCHING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-587
BUS MASTER MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-587
SHARED MEMORY MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-591
EADI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-595
JTAG (IEEE 1149.1) INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-595
GPSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-596
AUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-597
10BASE-T INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-598
SERIAL EEPROM INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-598
KEY TO SWITCHING WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-699
SWITCHING TEST CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-600
SWITCHING WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-602
BUS MASTER MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-602
SHARED MEMORY MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-612
GPSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-622
EADI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-623
JTAG (IEEE 1149.1) INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-623
AUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-624
10BASE-T INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-627
APPENDIX A: PCnet-ISA+ COMPATIBLE MEDIA INTERFACE MODULES
10BASE-T FILTERS and TRANSFORMERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-629
AUI ISOLATION TRANSFORMERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-629
MANUFACTURER CONTACT INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-630
APPENDIX B: LAYOUT RECOMMENDATION FOR REDUCING NOISE
DECOUPLING LOW-PASS RC FILTER DESIGN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-631
APPENDIX C: SAMPLE CONFIGURATION FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-633
APPENDIX D: ALTERNATIVE METHOD FOR INITIALIZATION . . . . . . . . . . . . . . . . . . . . . 1-635
APPENDIX E: INTRODUCTION TO THE CONCEPT OF LOOK AHEAD PACKET
PROCESSING (LAPP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-636
APPENDIX F: SOME CHARACTERISTICS OF THE XXC56 SERIAL EEPROMs . . . . . . . 1-646
1-483
Am79C961
AMD
P R E L I M I N A R Y
BLOCK DIAGRAM: BUS MASTER MODE
AEN
DACK[3, 5-7]
DRQ[3, 5-7]
IOCHRDY
IOCS16
DXCVR/EAR
802.3
MAC
Core
RCV
FIFO
IOR
CI+/-
IOW
ISA Bus
DI+/-
Encoder/
Decoder
(PLS) &
AUI Port
IRQ[3, 4, 5, 9, 10,
Interface
11, 12]
XTAL1
XTAL2
Unit
MASTER
MEMR
DO+/-
XMT
FIFO
MEMW
REF
RXD+/-
RESET
10BASE-T
MAU
TXD+/-
SBHE
TXPD+/-
BALE
FIFO
Control
IRQ15/APCS
SD[0-15]
BPCS
LED[0-3]
Private
Bus
Control
Buffer
Management
Unit
LA[17-23]
SA[0-19]
PRDB[0-7]
SLEEP
TDO
TMS
TDI
SHFBUSY
EEDO
EEDI
JTAG
Port
Control
EEPROM
Interface
Unit
EESK
EECS
TCK
DVDD[1-7]
18183B-1
DVSS[1-13]
AVDD[1-4]
AVSS[1-2]
1-484
Am79C961
P R E L I M I N A R Y
AMD
CONNECTION DIAGRAM: BUS MASTER
DVSS3
MASTER
DRQ7
DRQ6
DRQ5
DVSS10
DACK7
DACK6
DACK5
LA17
LA18
LA19
LA20
DVSS4
LA21
LA22
LA23
SBHE
DVDD3
SA0
SA1
SA2
DVSS5
SA3
SA4
1
2
3
4
5
6
7
8
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
XTAL2
AVSS2
XTAL1
AVDD3
TXD+
TXPD+
TXD-
TXPD-
AVDD4
RXD+
RXD-
DVSS13
SD15
SD7
SD14
SD6
DVSS9
SD13
SD5
SD12
SD4
DVDD7
SD11
SD3
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
Top Side View
SD10
SD2
DVSS8
SD9
SD1
SD8
SD0
SLEEP
DVDD6
SA5
SA6
SA7
SA8
SA9
DVSS6
SA10
SA11
18183B-2
1-485
Am79C961
AMD
P R E L I M I N A R Y
PIN DESIGNATIONS: BUS MASTER
Listed by Pin Number
Pin #
Name
Pin #
Name
Pin #
Name
RXD-
1
DVSS3
MASTER
DRQ7
DRQ6
DRQ5
DVSS10
DACK7
DACK6
DACK5
LA17
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
IOCHRDY
MEMW
MEMR
DVSS11
IRQ15/APCS
IRQ12/FlashWE
IRQ11
DVDD5
IRQ10
IOCS16
BALE
89
2
90
RXD+
3
91
AVDD4
TXPD-
TXD-
4
92
5
93
6
94
TXPD+
TXD+
7
95
8
96
AVDD3
XTAL1
AVSS2
XTAL2
AVSS1
DO-
9
97
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
98
LA18
99
LA19
IRQ3
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
LA20
IRQ4
DVSS4
LA21
IRQ5
DO+
REF
AVDD1
DI-
LA22
DVSS12
DRQ3
DACK3
IOR
LA23
DI+
SBHE
DVDD3
SA0
CI-
CI+
IOW
AVDD2
DXCVR/EAR
LED3
SA1
IRQ9
SA2
RESET
DVDD6
SLEEP
SD0
DVSS5
SA3
LED2
DVSS1
LED1
SA4
SA5
SD8
LED0
SA6
SD1
DVDD1
PRDB7
PRDB6
PRDB5
PRDB4
DVSS2
PRDB3
PRDB2/EEDO
PRDB1/EEDI
PRDB0/EESK
SHFBUSY
BPCS
SA7
SD9
SA8
DVSS8
SD2
SA9
DVSS6
SA10
SA11
DVDD4
SA12
SA13
SA14
SA15
DVSS7
SA16
SA17
SA18
SA19
AEN
SD10
SD3
SD11
DVDD7
SD4
SD12
SD5
SD13
DVSS9
SD6
EECS
TDI
SD14
TDO
SD7
TMS
SD15
TCK
DVSS13
DVDD2
1-486
Am79C961
P R E L I M I N A R Y
AMD
Pin #
PIN DESIGNATIONS: BUS MASTER
Listed by Pin Name
Pin #
Name
SA13
Name
Pin #
Name
127
45
36
37
38
40
41
42
43
22
24
25
26
27
28
29
30
18
69
71
75
77
80
82
85
87
74
76
79
81
84
86
70
72
125
68
131
128
129
130
93
95
92
94
97
99
AEN
44
103
108
96
91
100
98
55
126
106
107
62
9
EECS
SA14
SA15
SA16
SA17
SA18
SA19
SA2
AVDD1
AVDD2
AVDD3
AVDD4
AVSS1
AVSS2
BALE
IOCHRDY
IOCS16
IOR
54
63
64
IOW
53
IRQ10
IRQ11
IRQ12/FlashWE
IRQ15/APCS
IRQ3
51
50
49
SA3
BPCS
56
SA4
CI-
57
SA5
CI+
IRQ4
58
SA6
DACK3
DACK5
DACK6
DACK7
DI-
IRQ5
65
SA7
IRQ9
10
SA8
8
LA17
11
SA9
7
LA18
12
SBHE
SD0
104
105
101
102
61
5
LA19
13
DI+
LA20
15
SD1
DO-
LA21
16
SD10
SD11
SD12
SD13
SD14
SD15
SD2
DO+
LA22
17
DRQ3
LA23
114
113
111
110
2
DRQ5
LED0
DRQ6
4
LED1
DRQ7
3
LED2
DVDD1
DVDD2
DVDD3
DVDD4
DVDD5
DVDD6
DVDD7
DVSS1
DVSS10
DVSS11
DVSS12
DVSS13
DVSS2
DVSS3
DVSS4
DVSS5
DVSS6
DVSS7
DVSS8
DVSS9
DXCVR/EAR
115
132
19
34
52
67
78
112
6
LED3
MASTER
MEMR
MEMW
PRDB0/EESK
PRDB1/EEDI
PRDB2/EEDO
PRDB3
PRDB4
PRDB5
PRDB6
PRDB7
REF
47
SD3
46
SD4
124
123
122
121
119
118
117
116
59
SD5
SD6
SD7
SD8
SD9
SHFBUSY
SLEEP
TCK
48
60
88
120
1
TDI
66
TDO
RESET
RXD-
89
TMS
14
23
31
39
73
83
109
90
TXD-
TXD+
TXPD-
TXPD+
XTAL1
XTAL2
RXD+
20
SA0
21
SA1
32
SA10
33
SA11
35
SA12
1-487
Am79C961
AMD
P R E L I M I N A R Y
PIN DESIGNATIONS: BUS MASTER
Listed by Group
Pin Name
Pin Function
I/O
Driver
ISA Bus Interface
AEN
Address Enable
I
I
BALE
Bus Address Latch Enable
DMA Acknowledge
DMA Request
DACK[3, 5-7]
DRQ[3, 5-7]
IOCHRDY
IOCS16
I
O
I/O
O
I
TS3
OD3
OD3
I/O Channel Ready
I/O Chip Select 16
I/O Read Select
IOR
IOW
I/O Write Select
I
IRQ[3, 4, 5, 9, 10, 11, 12, 15]
LA[17-23]
MASTER
MEMR
Interrupt Request
O
I/O
O
O
O
I
TS3/OD3
TS3
Unlatched Address Bus
Master Transfer in Progress
Memory Read Select
Memory Write Select
Memory Refresh Active
System Reset
OD3
TS3
MEMW
TS3
REF
RESET
I
SA[0-19]
SBHE
System Address Bus
System Byte High Enable
System Data Bus
I/O
I/O
I/O
TS3
TS3
TS3
SD[0-15]
Board Interfaces
IRQ15/APCS
IRQ15 or Address PROM
Chip Select
O
O
I/O
O
O
O
O
I/O
I
TS1
TS1
TS1
TS2
TS2
TS2
TS2
TS1
BPCS
Boot PROM Chip Select
Disable Transceiver
LED0/LNKST
DXCVR/EAR
LED0
LED1
LED1/SFBD/RCVACT
LED2/SRD/RXDATPOL
LED3/SRDCLK/XMTACT
PROM Data Bus
LED2
LED3
PRDB[3-7]
SLEEP
XTAL1
Sleep Mode
Crystal Input
I
XTAL2
Crystal Output
O
O
SHFBUSY
Read access from EEPROM
in process
PRDB(0)/EESK
PRDB(1)/EEDI
PRDB(2)/EEDO
EECS
Serial Shift Clock
I/O
I/O
I/O
O
Serial Shift Data In
Serial Shift Data Out
EEPROM Chip Select
1-488
Am79C961
P R E L I M I N A R Y
AMD
PIN DESIGNATIONS: BUS MASTER (continued)
Listed by Group
Pin Name
Pin Function
I/O
Driver
Attachment Unit Interface (AUI)
CI±
Collision Inputs
I
I
DI±
Receive Data
Transmit Data
DO±
O
Twisted Pair Transceiver Interface (10BASE-T)
RXD±
10BASE-T Receive Data
I
TXD±
10BASE-T Transmit Data
10BASE-T Predistortion Control
O
O
TXPD±
IEEE 1149.1 Test Access Port Interface (JTAG)
TCK
Test Clock
I
I
TDI
Test Data Input
Test Data Output
Test Mode Select
TDO
O
I
TS2
TMS
Power Supplies
AVDD
AVSS
DVDD
DVSS
Analog Power [1-4]
Analog Ground [1-2]
Digital Power [1-7]
Digital Ground [1-13]
Output Driver Types
Name
Type
IOL (mA)
IOH (mA)
pF
TS1
Tri-State
4
–1
50
50
TS2
TS3
OD3
Tri-State
Tri-State
12
24
24
–4
–3
–3
120
120
Open Drain
1-489
Am79C961
AMD
P R E L I M I N A R Y
Because of the operation of the Plug and Play registers,
the DMA Channels on the PCnet-ISA+ must be attached
to specific DRQ and DACK signals on the PC/AT bus.
PIN DESCRIPTION: BUS MASTER MODE
These pins are part of the bus master mode. In order to
understand the pin descriptions, definition of some
terms from a draft of IEEE P996 are included.
IOCHRDY
I/O Channel Ready
Input/Output
When the PCnet-ISA+ controller is being accessed,
IOCHRDY HIGH indicates that valid data exists on the
data bus for reads and that data has been latched for
writes. When the PCnet-ISA+ controller is the Current
Master on the ISA bus, it extends the bus cycle as long
as IOCHRDY is LOW.
IEEE P996 Terminology
Alternate Master: Any device that can take control of
the bus through assertion of the MASTER signal. It has
theabilitytogenerateaddressesandbuscontrolsignals
in order to perform bus operations. All Alternate Mas-
ters must be 16 bit devices and drive SBHE.
Bus Ownership: The Current Master possesses bus
ownership and can assert any bus control, address and
data lines.
IOCS16
I/O Chip Select 16
Output
When an I/O read or write operation is performed, the
PCnet-ISA+ controller will drive the IOCS16 pin LOW to
indicate that the chip supports a 16-bit operation at this
address. (If the motherboard does not receive this sig-
nal, then the motherboard will convert a 16-bit access to
two 8-bit accesses.)
Current Master: The Permanent Master, Temporary
Master or Alternate Master which currently has owner-
ship of the bus.
Permanent Master: Each P996 bus will have a device
known as the Permanent Master that provides certain
signals and bus control functions as described in Sec-
tion 3.5 (of the IEEE P996 spec), “Permanent Master”.
The Permanent Master function can reside on a Bus
Adapter or on the backplane itself.
The PCnet-ISA+ controller follows the IEEE P996 speci-
fication that recommends this function be implemented
as a pure decode of SA0-9 and AEN, with no depend-
ency on IOR, or IOW; however, some PC/AT clone
systems are not compatible with this approach. For this
reason, the PCnet-ISA+ controller is recommended to
be configured to run 8-bit I/O on all machines. Since
dataismovedbymemorycyclesthereisvirtuallynoper-
formance loss incurred by running 8-bit I/O and
compatibility problems are virtually eliminated. The
PCnet-ISA+ controller can be configured to run 8-bit-
only I/O by clearing Bit 0 in Plug and Play register F0.
Temporary Master: A device that is capable of gener-
ating a DMA request to obtain control of the bus and
directly asserting only the memory and I/O strobes dur-
ing bus transfer. Addresses are generated by the DMA
device on the Permanent Master.
ISA Interface
AEN
IOR
Address Enable
Input
I/O Read
Input
This signal must be driven LOW when the bus performs
an I/O access to the device.
IOR is driven LOW by the host to indicate that an Input/
Output Read operation is taking place. IOR is only valid
if the AEN signal is LOW and the external address
matches the PCnet-ISA+ controller’s predefined I/O ad-
dress location. If valid, IOR indicates that a slave read
operation is to be performed.
BALE
Used to latch the LA20–23 address lines.
DACK 3, 5-7
DMA Acknowledge
Input
IOW
Asserted LOW when the Permanent Master acknowl-
edges a DMA request. When DACK is asserted the
PCnet-ISA+ controller becomes the Current Master by
asserting the MASTER signal.
I/O Write
Input
IOW is driven LOW by the host to indicate that an Input/
Output Write operation is taking place. IOW is only valid
if AEN signal is LOW and the external address matches
the PCnet-ISA+ controller’s predefined I/O address
location. If valid, IOW indicates that a slave write opera-
tion is to be performed.
DRQ 3, 5-7
DMA Request
Output
When the PCnet-ISA+ controller needs to perform a
DMA transfer, it asserts DRQ. The Permanent Master
acknowledges DRQ with assertion of DACK. When the
PCnet-ISA+ controller does not need the bus it deas-
serts DRQ.
1-490
Am79C961
P R E L I M I N A R Y
AMD
IRQ 3, 4, 5, 9, 10, 11, 12, 15
MEMW
Interrupt Request
Output
Memory Write
Input/Output
An attention signal which indicates that one or more of
the following status flags is set: BABL, MISS, MERR,
RINT, IDON, RCVCCO, JAB, MPCO, or TXDATSTRT.
All status flags have a mask bit which allows for
suppression of IRQ assertion. These flags have the fol-
lowing meaning:
MEMW goes LOW to perform a memory write
operation.
REF
Memory Refresh
Input
When REF is asserted, a memory refresh is active. The
PCnet-ISA+ controller uses this signal to mask inadver-
tent DMA Acknowledge assertion during memory
refresh periods. If DACK is asserted when REF is ac-
tive, DACK assertion is ignored. REF is monitored to
eliminate a bus arbitration problem observed on some
ISA platforms.
BABL
Babble
RCVCCO
JAB
Receive Collision Count Overflow
Jabber
MISS
Missed Frame
MERR
MPCO
RINT
Memory Error
RESET
Missed Packet Count Overflow
Receive Interrupt
Initialization Done
Transmit Start
Reset
Input
When RESET is asserted HIGH the PCnet-ISA+ control-
ler performs an internal system reset. RESET must be
held for a minimum of 10 XTAL1 periods before being
deasserted. While in a reset state, the PCnet-ISA+ con-
troller will tristate or deassert all outputs to predefined
reset levels. The PCnet-ISA+ controller resets itself
upon power-up.
IDON
TXDATSTRT
Because of the operation of the Plug and Play registers,
the interrupts on the PCnet-ISA+ must be attached to
specific IRQ signals on the PC/AT bus.
SA0-19
System Address Bus
LA17-23
Unlatched Address Bus
Input/Output
Input/Output
This bus contains address information, which is stable
during a bus operation, regardless of the source.
SA17-19 contain the same values as the unlatched ad-
dress LA17-19. When the PCnet-ISA+ controller is the
Current Master, SA0-19 will be driven actively. When
the PCnet-ISA+ controller is not the Current Master, the
SA0-19 lines are continuously monitored to determine if
an address match exists for I/O slave transfers or Boot
PROM accesses.
The unlatched address bus is driven by the PCnet-ISA+
controller during bus master cycle.
The functions of these unlatched address pins will
change when GPSI mode is invoked. The following ta-
ble shows the pin configuration in GPSI mode. Please
refer to the section on General Purpose Serial Interface
for detailed information on accessing this mode.
Pin
Number
Pin Function in
Bus Master Mode
Pin Function in
GPSI Mode
SBHE
System Byte High Enable
Input/Output
10
11
12
13
15
16
17
LA17
LA18
LA19
LA20
LA21
LA22
LA23
RXDAT
SRDCLK
RXCRS
CLSN
This signal indicates the high byte of the system data
bus is to be used. SBHE is driven by the PCnet-ISA+
controller when performing bus mastering operations.
SD0-15
System Data Bus
STDCLK
TXEN
Input/Output
These pins are used to transfer data to and from the
PCnet-ISA+ controller to system resources via the ISA
data bus. SD0-15 is driven by the PCnet-ISA+ controller
when performing bus master writes and slave read op-
erations. Likewise, the data on SD0-15 is latched by the
PCnet-ISA+ controller when performing bus master
reads and slave write operations.
TXDAT
MASTER
Master Mode
Input/Output
This signal indicates that the PCnet-ISA+ controller has
become the Current Master of the ISA bus. After the
PCnet-ISA+ controller has received a DMA Acknowl-
edge (DACK) in response to a DMA Request (DRQ), the
Ethernet controller asserts the MASTER signal to indi-
cate to the Permanent Master that the PCnet-ISA+
controller is becoming the Current Master.
Board Interface
IRQ12/FlashWE
Flash Write Enable
Output
Optional interface to the Flash memory boot PROM
Write Enable.
MEMR
Memory Read
Input/Output
MEMR goes LOW to perform a memory read operation.
1-491
Am79C961
AMD
P R E L I M I N A R Y
IRQ15/APCS
PRDB3-7
Private Data Bus
Address PROM Chip Select
Output
Input/Output
When programmed as APCS in Plug and Play Register
F0, this signal is asserted when the external Address
PROM is read. When an I/O read operation is per-
formed on the first 16 bytes in the PCnet-ISA+
controller’sI/Ospace, APCSis asserted. The outputs of
the external Address PROM drive the PROM Data Bus.
The PCnet-ISA+ controller buffers the contents of the
PROM data bus and drives them on the lower eight bits
of the System Data Bus.
This is the data bus for the Boot PROM and the Address
PROM.
PRDB2/EEDO
Private data bus bit 2/Data Out Input/Output
A multifunction pin which serves as PRDB2 of the pri-
vate data bus and, when ISACSR3 bit 4 is set, changes
to become DATA OUT from the EEPROM.
PRDB1/EEDI
Private data bus bit 1/Data In Input/Output
When programmed to IRQ15 (default), this pin has the
same function as IRQ 3, 4, 5, 9, 10, 11, or 12.
A multifunction pin which serves as PRDB1 of the pri-
vate data bus and, when ISACSR3 bit 4 is set, changes
to become DATA In to the EEPROM.
BPCS
Boot PROM Chip Select
Output
This signal is asserted when the Boot PROM is read. If
SA0-19 lines match a predefined address block and
MEMR is active and REF inactive, the BPCS signal will
be asserted. The outputs of the external Boot PROM
drive the PROM Data Bus. The PCnet-ISA+ controller
buffers the contents of the PROM data bus and drives
them on the lower eight bits of the System Data Bus.
PRDB0/EESK
Private data bus bit 0/
Serial Clock
Input/Output
A multifunction pin which serves as PRDB0 of the pri-
vate data bus and, when ISACSR3 bit 4 is set, changes
to become Serial Clock to the EEPROM.
SHFBUSY
Input/Output
DXCVR/EAR
An output from PCnet-ISA+ which indicates that a read
from the external EEPROM is in progress. It is active
only when the hardware reconfigure is running (when
data is being shifted out of the EEPROM due to a hard-
ware RESET or the EELOAD command being issued).
This pin should have a pull-up resistor (10 KΩ) to VCC.
Disable Transceiver/
External Address Reject
Input/Output
This pin disables the transceiver. The DXCVR output is
configured in the initialization sequence. A HIGH level
indicates the Twisted Pair port is active and the AUI port
is inactive, or SLEEP mode has been entered. A LOW
levelindicatestheAUIportisactiveandtheTwistedPair
port is inactive.
EECS
EEPROM CHIPSELECT
Output
This signal is asserted when read or write accesses are
being performed to the EEPROM. It is controlled by
ISACSR3. It is driven at Reset during EEPROM Read.
If EADI mode is selected, this pin becomes the EAR
input.
The incoming frame will be checked against the inter-
nally active address detection mechanisms and the
result of this check will be OR’d with the value on the
EAR pin. The EAR pin is defined as REJECT. (See the
EADI section for details regarding the function and tim-
ing of this signal.)
SLEEP
Sleep
Input
When SLEEP pin is asserted (active LOW), the
PCnet-ISA+ controller performs an internal system reset
and proceeds into a power savings mode. All outputs
will be placed in their normal reset condition. All
PCnet-ISA+ controller inputs will be ignored except for
the SLEEP pin itself. Deassertion of SLEEP results in
wake-up. The system must delay the starting of the net-
work controller by 0.5 seconds to allow internal analog
circuits to stabilize.
LED0-3
LED Drivers
Output
These pins sink 12 mA each for driving LEDs. Their
meaning is software configurable (see section The ISA
Bus Configuration Registers) and they are active LOW.
When EADI mode is selected, the pins named LED1,
LED2, and LED3 change in function while LED0 contin-
ues to indicate 10BASE-T Link Status.
XTAL1
Crystal Connection
Input
The internal clock generator uses a 20 MHz crystal that
is attached to pins XTAL1 and XTAL2. Alternatively, an
external 20 MHz CMOS-compatible clock signal can be
used to drive this pin. Refer to the section on External
Crystal Characteristics for more details.
LED
EADI Function
SF/BD
1
2
3
SRD
SRDCLK
XTAL2
Crystal Connection
Output
The internal clock generator uses a 20 MHz crystal that
is attached to pins XTAL1 and XTAL2. If an external
clock is used, this pin should be left unconnected.
1-492
Am79C961
P R E L I M I N A R Y
AMD
BLOCK DIAGRAM: SHARED MEMORY MODE
AEN
DXCVR/EAR
802.3
MAC
Core
IOCHRDY
RCV
FIFO
IOR
CI+/-
IOW
IRQ[3, 4, 5, 9, 10,
11, 12]
ISA Bus
Interface
Unit
DI+/-
Encoder/
Decoder
(PLS) &
AUI Port
XTAL1
XTAL2
IOCS16
MEMR
DO+/-
XMT
FIFO
MEMW
REF
RXD+/-
RESET
10BASE-T
MAU
TXD+/-
SA[0-15]
TXPD+/-
SBHE
FIFO
Control
IRQ15/APCS
SD[0-15]
BPCS
Private
Bus
Control
LED[0-3]
PRAB[0-15]
PRDB[0-7]
SROE
Buffer
Management
Unit
SRWE
SMA
SLEEP
BPAM
SMAM
SHFBUSY
TDO
TMS
TDI
JTAG
Port
Control
EEPROM
Interface
Unit
EEDO
EEDI
EESK
EECS
TCK
18183B-3
DVDD[1-7]
DVSS[1-13]
AVDD[1-4]
AVSS[1-2]
1-493
Am79C961
AMD
P R E L I M I N A R Y
CONNECTION DIAGRAM: SHARED MEMORY
DVSS3
SMA
SA0
SA1
SA2
1
2
3
4
5
6
7
8
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
XTAL2
AVSS2
XTAL1
AVDD3
TXD+
TXPD+
TXD-
TXPD-
AVDD4
RXD+
RXD-
DVSS13
SD15
SD7
SD14
SD6
DVSS9
SD13
SD5
SD12
SD4
DVDD7
SD11
SD3
DVSS10
SA3
SA4
SA5
SA6
SA7
SA8
SA9
DVSS4
SA10
SA11
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
Top Side View
SA12
SBHE
DVDD3
PRAB0
PRAB1
PRAB2
DVSS5
PRAB3
PRAB4
PRAB5
PRAB6
PRAB7
PRAB8
PRAB9
DVSS6
PRAB10
PRAB11
SD10
SD2
DVSS8
SD9
SD1
SD8
SD0
SLEEP
DVDD6
18183B-4
1-494
Am79C961
P R E L I M I N A R Y
AMD
PIN DESIGNATIONS: SHARED MEMORY
Listed by Pin Number
Pin #
Name
Pin #
Name
Pin #
Name
RXD-
1
DVSS3
SMA
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
IOCHRDY
MEMW
MEMR
DVSS11
IRQ15
IRQ12
IRQ11
DVDD5
IRQ10
IOCS16
BPAM
IRQ3
89
2
90
RXD+
AVDD4
TXPD-
TXD-
3
SA0
91
4
SA1
92
5
SA2
93
6
DVSS10
SA3
94
TXPD+
TXD+
AVDD3
XTAL1
AVSS2
XTAL2
AVSS1
DO-
7
95
8
SA4
96
9
SA5
97
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
SA6
98
SA7
99
SA8
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
SA9
IRQ4
DVSS4
SA10
IRQ5
DO+
REF
AVDD1
DI-
SA11
DVSS12
SROE
SMAM
IOR
SA12
DI+
SBHE
DVDD3
PRAB0
PRAB1
PRAB2
DVSS5
PRAB3
PRAB4
PRAB5
PRAB6
PRAB7
PRAB8
PRAB9
DVSS6
PRAB10
PRAB11
DVDD4
PRAB12
PRAB13
PRAB14
PRAB15
DVSS7
SA13
CI-
CI+
IOW
AVDD2
IRQ9
DXCVR/EAR
LED3
RESET
DVDD6
SLEEP
SD0
LED2
DVSS1
LED1
SD8
LED0
SD1
DVDD1
PRDB7
PRDB6
PRDB5
PRDB4
DVSS2
PRDB3
PRDB2/EEDO
PRDB1/EEDI
PRDB0/EESK
SHFBUSY
BPCS
SD9
DVSS8
SD2
SD10
SD3
SD11
DVDD7
SD4
SD12
SD5
SD13
DVSS9
SD6
EECS
TDI
SA14
SD14
SD7
TDO
SA15
TMS
SRWE
AEN
SD15
DVSS13
TCK
DVDD2
1-495
Am79C961
AMD
P R E L I M I N A R Y
PIN DESIGNATIONS: SHARED MEMORY
Listed by Pin Name
Name
Pin #
Name
Pin #
Name
SA13
Pin #
AEN
44
IRQ15
49
40
41
42
5
AVDD1
AVDD2
AVDD3
AVDD4
AVSS1
AVSS2
BPAM
BPCS
103
108
96
IRQ3
56
SA14
SA15
SA2
IRQ4
57
IRQ5
58
91
IRQ9
65
SA3
7
100
98
LED0
114
113
111
110
47
SA4
8
LED1
SA5
9
55
LED2
SA6
10
11
12
13
18
69
71
75
77
80
82
85
87
74
76
79
81
84
86
70
72
125
68
2
126
106
107
104
105
101
102
115
132
19
LED3
SA7
CI-
MEMR
MEMW
PRAB0
PRAB1
PRAB10
PRAB11
PRAB12
PRAB13
PRAB14
PRAB15
PRAB2
PRAB3
PRAB4
PRAB5
PRAB6
PRAB7
PRAB8
PRAB9
PRDB0/DO
PRDB1/DI
PRDB2/SCLK
PRDB3
PRDB4
PRDB5
PRDB6
PRDB7
REF
SA8
CI+
46
SA9
DI-
20
SBHE
SD0
DI+
21
DO-
32
SD1
DO+
33
SD10
SD11
SD12
SD13
SD14
SD15
SD2
DVDD1
DVDD2
DVDD3
DVDD4
DVDD5
DVDD6
DVDD7
DVSS1
DVSS10
DVSS11
DVSS12
DVSS13
DVSS2
DVSS3
DVSS4
DVSS5
DVSS6
DVSS7
DVSS8
DVSS9
DXCVR/EAR
EECS
35
36
37
34
38
52
22
67
24
78
25
SD3
112
6
26
SD4
27
SD5
48
28
SD6
60
29
SD7
88
30
SD8
120
1
124
123
122
121
119
118
117
116
59
SD9
SHFBUSY
SLEEP
SMA
SMAM
SROE
SRWE
TCK
14
23
31
62
61
43
131
128
129
130
93
95
92
94
97
99
39
73
83
109
127
45
TDI
RESET
RXD-
66
TDO
IOCHRDY
IOCS16
IOR
89
TMS
54
RXD+
90
TXD-
TXD+
TXPD-
TXPD+
XTAL1
XTAL2
63
SA0
3
IOW
64
SA1
4
IRQ10
IRQ11
IRQ12
53
SA10
15
51
SA11
16
50
SA12
17
1-496
Am79C961
P R E L I M I N A R Y
AMD
PIN DESIGNATIONS: SHARED MEMORY
Listed by Group
Pin Name
Pin Function
I/O
Driver
ISA Bus Interface
AEN
Address Enable
I
O
O
I
IOCHRDY
I/O Channel Ready
I/O Chip Select 16
I/O Read Select
OD3
OD3
IOCS16
IOR
IOW
I/O Write Select
I
IRQ[3, 4, 5, 9, 10, 11, 12, 15]
Interrupt Request
Memory Read Select
Memory Write Select
Memory Refresh Active
System Reset
O
I
TS3/OD3
MEMR
MEMW
I
REF
I
RESET
I
SA[0-15]
SBHE
System Address Bus
System Byte High Enable
System Data Bus
I
I
SD[0-15]
Board Interfaces
I/O
TS3
IRQ15/APCS
BPCS
IRQ15 or Address PROM Chip Select
Boot PROM Chip Select
Boot PROM Address Match
Disable Transceiver
O
O
I
TS1
TS1
BPAM
DXCVR/EAR
LED0
I/O
O
O
O
O
I/O
I/O
I
TS1
TS2
TS2
TS2
TS2
TS3
TS1
LED0/LNKST
LED1
LED1/SFBD/RCVACT
LED2/SRD/RXDATD01
LED3/SRDCLK/XMTACT
PRivate Address Bus
LED2
LED3
PRAB[0-15]
PRDB[3-7]
SLEEP
PRivate Data Bus
Sleep Mode
SMA
Shared Memory Architecture
Shared Memory Address Match
Static RAM Output Enable
Static RAM Write Enable
Crystal Oscillator Input
Crystal Oscillator OUTPUT
Read access from EEPROM in process
Serial Shift Clock
I
SMAM
I
SROE
O
O
I
TS3
TS1
SRWE
XTAL1
XTAL2
O
O
I/O
I/O
I/O
O
SHFBUSY
PRDB(0)/EESK
PRDB(1)/EEDI
PRDB(2)/EEDO
EECS
Serial Shift Data In
Serial Shift Data Out
EEPROM Chip Select
1-497
Am79C961
AMD
P R E L I M I N A R Y
PIN DESIGNATIONS: SHARED MEMORY (continued)
Listed by Group
Pin Name
Pin Function
I/O
Driver
Attachment Unit Interface (AUI)
CI±
Collision Inputs
I
I
DI±
Receive Data
Transmit Data
DO±
O
Twisted Pair Transceiver Interface (10BASE–T)
RXD±
10BASE-T Receive Data
I
TXD±
10BASE-T Transmit Data
10BASE-T Predistortion Control
O
O
TXPD±
IEEE 1149.1 Test Access Port Interface (JTAG)
TCK
Test Clock
I
I
TDI
Test Data Input
Test Data Output
Test Mode Select
TDO
O
I
TS2
TMS
Power Supplies
AVDD
AVSS
DVDD
DVSS
Analog Power [1-4]
Analog Ground [1-2]
Digital Power [1-7]
Digital Ground [1-13]
Output Driver Types
Name
Type
IOL (mA)
IOH (mA)
pF
TS1
Tri-State
4
–1
50
50
TS2
TS3
OD3
Tri-State
Tri-State
12
24
24
–4
–3
–3
120
120
Open Drain
1-498
Am79C961
P R E L I M I N A R Y
AMD
which allows for suppression of IRQ assertion. These
flags have the following meaning:
PIN DESCRIPTION:
SHARED MEMORY MODE
BABL
Babble
ISA Interface
RCVCCO
JAB
Receive Collision Count Overflow
Jabber
AEN
Address Enable
Input
MISS
Missed Frame
This signal must be driven LOW when the bus performs
an I/O access to the device.
MERR
MPCO
RINT
Memory Error
Missed Packet Count Overflow
Receive Interrupt
Initialization Done
Transmit Start
IOCHRDY
I/O Channel Ready
When the PCnet-ISA+ controller is being accessed, a
HIGH on IOCHRDY indicates that valid data exists on
the data bus for reads and that data has been latched for
writes.
Output
IDON
TXSTRT
MEMR
Memory Read
Input
IOCS16
I/O Chip Select 16
Input/Output
MEMR goes LOW to perform a memory read operation.
When an I/O read or write operation is performed, the
PCnet-ISA+ controller will drive this pin LOW to indicate
that the chip supports a 16-bit operation at this address.
(Ifthemotherboarddoesnotreceivethissignal, thenthe
motherboard will convert a 16-bit access to two 8-bit
accesses.)
MEMW
Memory Write
Input
MEMW goes LOW to perform a memory write
operation.
RESET
Reset
The PCnet-ISA+ controller follows the IEEE P996 speci-
fication that recommends this function be implemented
as a pure decode of SA0-9 and AEN, with no depend-
ency on IOR, or IOW; however, some PC/AT clone
systems are not compatible with this approach. For this
reason, the PCnet-ISA+ controller is recommended to
be configured to run 8-bit I/O on all machines. Since
dataismovedbymemorycyclesthereisvirtuallynoper-
formance loss incurred by running 8-bit I/O and
compatibility problems are virtually eliminated. The
PCnet-ISA+ controller can be configured to run 8-bit-
only I/O by clearing Bit 0 in Plug and Play Register F0.
Input
When RESET is asserted HIGH, the PCnet-ISA+ con-
troller performs an internal system reset. RESET must
beheldforaminimumof10XTAL1periodsbeforebeing
deasserted. While in a reset state, the PCnet-ISA+ con-
troller will tristate or deassert all outputs to predefined
reset levels. The PCnet-ISA+ controller resets itself
upon power-up.
SA0-15
System Address Bus
Input
This bus carries the address inputs from the system ad-
dress bus. Address data is stable during command
active cycle.
IOR
I/O Read
Input
To perform an Input/Output Read operation on the de-
vice IOR must be asserted. IOR is only valid if the AEN
signal is LOW and the external address matches the
PCnet-ISA+ controller ’s predefined I/O address loca-
tion. If valid, IOR indicates that a slave read operation is
to be performed.
SBHE
System Bus High Enable
Input
This signal indicates the HIGH byte of the system data
bus is to be used. There is a weak pull-up resistor on this
pin. If the PCnet-ISA+ controller is installed in an 8-bit
only system like the PC/XT, SBHE will always be HIGH
and the PCnet-ISA+ controller will perform only 8-bit op-
erations. TheremustbeatleastoneLOWgoingedgeon
this signal before the PCnet-ISA+ controller will perform
16-bit operations.
IOW
I/O Write
Input
To perform an Input/Output write operation on the de-
vice IOW must be asserted. IOW is only valid if AEN
signal is LOW and the external address matches the
PCnet-ISA+ controller’s predefined I/O address loca-
tion. If valid, IOW indicates that a slave write operation
is to be performed.
SD0-15
System Data Bus
Input/Output
This bus is used to transfer data to and from the
PCnet-ISA+ controller to system resources via the ISA
data bus. SD0-15 is driven by the PCnet-ISA+ controller
when performing slave read operations.
IRQ3, 4, 5, 9, 10, 11, 15
Interrupt Request
Output
Likewise, the data on SD0-15 is latched by the
PCnet-ISA+ controller when performing slave write
operations.
An attention signal which indicates that one or more of
the following status flags is set: BABL, MISS, MERR,
RINT, IDONorTXSTRT. Allstatusflagshaveamaskbit
1-499
Am79C961
AMD
P R E L I M I N A R Y
BOARD INTERFACE
LED
EADI Function
SF/BD
APCS/IRQ15
1
2
3
Address PROM Chip Select
Output
SRD
This signal is asserted when the external Address
PROM is read. When an I/O read operation is per-
formed on the first 16 bytes in the PCnet-ISA+
controller’sI/Ospace, APCSis asserted. The outputs of
the external Address PROM drive the PROM Data Bus.
The PCnet-ISA+ controller buffers the contents of the
PROM data bus and drives them on the lower eight bits
of the System Data Bus. IOCS16 is not asserted during
this cycle.
SRDCLK
PRAB0-15
Private Address Bus
Input/Output
The Private Address Bus is the address bus used to
drive the Address PROM, Remote Boot PROM, and
SRAM. PRAB10-15arerequiredtobebufferedbyaBus
Buffer with ABOE as its control and SA10-15 as its
inputs.
BPAM
Boot PROM Address Match
Input
PRDB3-7
Private Data Bus
This pin indicates a Boot PROM access cycle. If no Boot
PROM is installed, this pin has a default value of HIGH
and thus may be left connected to VDD
Input/Output
This is the data bus for the static RAM, the Boot PROM,
and the Address PROM.
.
BPCS
PRDB2/EEDO
Private Data Bus Bit 2/Data Out Input/Output
Boot PROM Chip Select
Output
This signal is asserted when the Boot PROM is read. If
BPAM is active and MEMR is active, the BPCS signal
will be asserted. The outputs of the external Boot
PROM drive the PROM Data Bus. The PCnet-ISA+ con-
troller buffers the contents of the PROM data bus and
drives them on the System Data Bus. IOCS16 is not as-
serted during this cycle. If 16-bit cycles are performed, it
istheresponsibilityofexternallogictoassertMEMCS16
signal.
A multifunction pin which serves as PRDB2 of the pri-
vate data bus and, when ISACSR3 bit 4 is set, changes
to become DATA OUT from the EEPROM.
PRDB1/EEDI
Private Data Bus Bit 1/Data In Input/Output
A multifunction pin which serves as PRDB1 of the pri-
vate data bus and, when ISACSR3 bit 4 is set, changes
to become DATA In to the EEPROM.
DXCVR/EAR
PRDB0/EESK
Disable Transceiver/
Private Data Bus Bit 0/
External Address Reject
Input/Output
Serial Clock
Input/Output
This pin disables the transceiver. The DXCVR output is
configured in the initialization sequence. A high level in-
dicates the Twisted Pair Interface is active and the AUI
is inactive, or SLEEP mode has been entered. A low
level indicates the AUI is active and the Twisted Pair in-
terface is inactive.
A multifunction pin which serves as PRDB0 of the pri-
vate data bus and, when ISACSR3 bit 4 is set, changes
to become Serial Clock to the EEPROM.
SHFBUSY
Shift Busy
Input/Output
An output from PCnet-ISA+ which indicates that a read
from the external EEPROM is in progress. It is active
only when the hardware reconfigure is running (when
data is being shifted out of the EEPROM due to a hard-
ware RESET or the EELOAD command being issued).
If EADI mode is selected, this pin becomes the EAR
input.
The incoming frame will be checked against the inter-
nally active address detection mechanisms and the
result of this check will be OR’d with the value on the
EAR pin. The EAR pin is defined as REJECT. (See the
EADI section for details regarding the function and tim-
ing of this signal.)
SHFBUSY should be connected to VCC with a 10K Ω
resistor.
EECS
EEPROM CHIPSELECT
LED0-3
Output
LED Drivers
Output
This signal is asserted when read or write accesses are
being performed to the EEPROM. It is controlled by
ISACSR3. It is driven at Reset during EEPROM Read.
These pins sink 12 mA each for driving LEDs. Their
meaning is software configurable (see section The ISA
Bus Configuration Registers) and they are active LOW.
SLEEP
When EADI mode is selected, the pins named LED1,
LED2, and LED3 change in function while LED0 contin-
ues to indicate 10BASE-T Link Status. The DXCVR
input becomes the EAR input.
Sleep
Input
When SLEEP input is asserted (active LOW), the
PCnet-ISA+ controller performs an internal system reset
1-500
Am79C961
P R E L I M I N A R Y
AMD
and proceeds into a power savings mode. All outputs
will be placed in their normal reset condition. All
PCnet-ISA+ controller inputs will be ignored except for
the SLEEP pin itself. Deassertion of SLEEP results in
wake-up. The system must delay the starting of the
network controller by 0.5 seconds to allow internal ana-
log circuits to stabilize.
When Flash boot ROM option is not selected, this pin
becomes IRQ12.
SRWE/WE
Static RAM Write Enable/
Write Enable
Output
This pin (SRWE) directly controls the external SRAM’s
WE pin when
implemented.
a Flash memory device is not
SMA
Shared Memory Architecture Input
When a Flash memory device is implemented, this pin
becomes a global write enable (WE) pin.
This pin is sampled after the hardware RESET se-
quence. The pin must be pulled permanently LOW for
operation in the shared memory mode.
XTAL1
Crystal Connection
Input
SMAM
The internal clock generator uses a 20 MHz crystal that
is attached to pins XTAL1 and XTAL2. Alternatively, an
external 20 MHz CMOS-compatible clock signal can be
used to drive this pin. Refer to the section on External
Crystal Characteristics for more details.
Shared Memory Address Match Input
This pin indicates an access to shared memory when
active. The type of access is decided by MEMR or
MEMW.
SROE
XTAL2
Static RAM Output Enable
Output
Crystal Connection
Output
This pin directly controls the external SRAM’s OE pin.
The internal clock generator uses a 20 MHz crystal that
is attached to pins XTAL1 and XTAL2. If an external
clock is used, this pin should be left unconnected.
SRCS/IRQ12
Static RAM Chip Select
Output
This pin directly controls the external SRAM’s chip se-
lect (CS) pin when the Flash boot ROM option is
selected.
Am79C961
1-501
AMD
P R E L I M I N A R Y
PIN DESCRIPTION:
TDO
Test Data Output
Output
NETWORK INTERFACES
This is the test data output path from the PCnet-ISA+
controller. TDO is tri-stated when JTAG port is inactive.
AUI
CI+, CI–
TMS
Control Input
Input
Test Mode Select
Input
This is a differential input pair used to detect Collision
(Signal Quality Error Signal).
This is a serial input bit stream used to define the spe-
cific boundary scan test to be executed. If left
unconnected, this pin has a default value of HIGH.
DI+, DI–
Data In
Input
PIN DESCRIPTION:
POWER SUPPLIES
This is a differential receive data input pair to the PCnet-
ISA+ controller.
All power pins with a “D” prefix are digital pins connected
to the digital circuitry and digital I/O buffers. All power
pins with an “A” prefix are analog power pins connected
to the analog circuitry. Not all analog pins are quiet and
special precaution must be taken when doing board lay-
out. Some analog pins are more noisy than others and
must be separated from the other analog pins.
DO+, DO–
Data Out
Output
This is a differential transmit data output pair from the
PCnet-ISA+ controller.
Twisted Pair Interface
RXD+, RXD–
AVDD1–4
Analog Power (4 Pins)
Power
Receive Data
Input
Supplies power to analog portions of the PCnet-ISA+
controller. Specialattentionshouldbepaidtotheprinted
circuit board layout to avoid excessive noise on these
lines.
This is the 10BASE-T port differential receive input pair.
TXD+, TXD–
Transmit Data
Output
These are the 10BASE-T port differential transmit
drivers.
AVSS1–2
Analog Ground (2 Pins)
Power
Supplies ground reference to analog portions of
PCnet-ISA+ controller. Special attention should be paid
to the printed circuit board layout to avoid excessive
noise on these lines.
TXP+, TXP–
Transmit Predistortion Control Output
These are 10BASE-T transmit waveform pre-distortion
control differential outputs.
DVDD1–7
PIN DESCRIPTION:
Digital Power (7 Pins)
Power
Supplies power to digital portions of PCnet-ISA+ control-
ler. Four pins are used by Input/Output buffer drivers
and two are used by the internal digital circuitry.
IEEE 1149.1 (JTAG) TEST ACCESS PORT
TCK
Test Clock
Input
This is the clock input for the boundary scan test mode
operation. TCK can operate up to 10 MHz. TCK does
not have an internal pullup resistor and must be con-
nected to a valid TTL level of high or low. TCK must not
be left unconnected.
DVSS1–13
Digital Ground (13 Pins)
Power
Supplies ground reference to digital portions of
PCnet-ISA+ controller. Ten pins are used by Input/Out-
put buffer drivers and two are used by the internal digital
circuitry.
TDI
Test Data Input
Input
This is the test data input path to the PCnet-ISA+ control-
ler. If left unconnected, this pin has a default value of
HIGH.
1-502
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AMD
The PCnet-ISA+ controller’s advanced bus mastering
architecture also provides high data throughput and low
CPU utilization for even better performance.
FUNCTIONAL DESCRIPTION
The PCnet-ISA+ controller is a highly integrated system
solution for the PC-AT ISA architecture. It provides an
Ethernet controller, AUI port, and 10BASE-T trans-
ceiver. The PCnet-ISA+ controller can be directly
interfaced to an ISA system bus. The PCnet-ISA+ con-
troller contains an ISA bus interface unit, DMA Buffer
Management Unit, 802.3 Media Access Control func-
tion, separate 136-byte transmit and 128-byte receive
FIFOs, IEEE defined Attachment Unit Interface (AUI),
and Twisted-Pair Transceiver Media Attachment Unit.
In addition, a Sleep function has been incorporated
which provides low standby current for power sensitive
applications.
To offer greater flexibility, the PCnet-ISA+ controller has
a shared memory mode to meet varying application
needs. The shared memory architecture is compatible
with very low-end machines, such as PC/XTs that do not
support bus mastering, and very high end machines
which require local packet buffering for increased sys-
tem latency.
The network interface provides an Attachment Unit In-
terface and Twisted-Pair Transceiver functions. Only
one interface is active at any particular time. The AUI
allows for connection via isolation transformer to
10BASE5 and 10BASE2, thick and thin based coaxial
cables. The Twisted-Pair Transceiver interface allows
for connection of unshielded twisted-pair cables as
specified by the Section 14 supplement to IEEE 802.3
Standard (Type 10BASE-T).
The PCnet-ISA+ controller is register compatible with
the LANCE (Am7990) Ethernet controller and
PCnet-ISA (Am79C960). The DMA Buffer Manage-
ment Unit supports the LANCE descriptor software
model and the PCnet-ISA+ controller is software com-
patible with the Novell NE2100 and NE1500T add-in
cards.
Bus Master Mode
External remote boot PROMs and Ethernet physical ad-
dress PROMs are supported. The location of the I/O
registers, Ethernet address PROM, and the boot PROM
are determined by the programming of the registers in-
ternal to PCnet-ISA+. These registers are loaded at
RESET from the EEPROM.
System Interface
The PCnet-ISA+ controller has two fundamental operat-
ing modes, Bus Master and Shared Memory. The
selection of either the Bus Master mode or the Shared
Memory mode must be done through hard wiring; it is
not software configurable. The Bus Master mode pro-
vides an Am7990 (LANCE) compatible Ethernet
controller, an Ethernet Address EEPROM or PROM, a
Boot PROM, and a set of device configuration registers.
Normally, the Ethernet physical address will be stored in
the EEPROM with the other configuration data. This re-
duces the parts count, board space requirements, and
powerconsumption. Theoptiontouseastandardparal-
lel 8 bit PROM is provided to manufactures who are
concerned about the non-volatile nature of EEPROMs.
The optional Boot PROM is in memory address space
and is expected to be 8–64K. On-chip address com-
parators control device selection based on the value of
the EEPROM.
The PCnet-ISA+ controller’s bus master architecture
brings to system manufacturers (adapter card and
motherboard makers alike) something they have not
been able to enjoy with other architectures—a low-cost
system solution that provides the lowest parts count and
highest performance. As a bus-mastering device, costly
and power-hungry external SRAMs are not needed for
packet buffering. This results in lower system cost due
to fewer components, less real-estate and less power.
The address PROM, board configuration registers, and
the Ethernet controller occupy 24 bytes of I/O space and
can be located on 16 different starting addresses.
Data buffers are located in system memory and can be
accessed by the PCnet-ISA+ controller when the device
becomes the Current Master.
Am79C961
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P R E L I M I N A R Y
BPCS
CE
OE
PRDB[0-7]
D[0-7]
16-Bit System Data
SD[0-15]
Boot
PROM
PRDB[2]/EEDO
PRDB[1]/EEDI
PRDB[0]/EESK
PCnet-ISA+
Controller
A[0-15]
ISA
Bus
24-Bit System
Address
DO
DI
SK
CS
SA[0-19]
LA[17-23]
EEPROM
SHFBUSY
EECS
VCC
ORG
VCC
18183B-6
Bus Master Block Diagram
Plug and Play Compatible
1-504
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A[0-4]
D[0-7]
BPCS
IEEE
Address
PROM
PRDB[0-7]
SD[0-15]
G
16-Bit
System
Data
PRDB[0]/EESK
PRDB[1]/EEDI
PRDB[2]/EEDO
EECS
PCnet-ISA+
Controller
A[0-15]
D[0-7]
WE
CS
SA[0-19]
LA[17-23]
24-Bit
System
Address
Flash
SHFBUSY
IRQ15/APCS IRQ12/FlashWE
ISA
Bus
OE
VCC
SK
DI
EEPROM
DO
CS
VCC
ORG
18183B-7
Bus Master Block Diagram
Plug and Play Compatible with Flash Support
This raises performance to more than 400% of what
could be achieved with 8-bit cycles. Converting boot
PROM accesses to 16-bit cycles allows the two memory
resources to be in the same 128 Kbyte block of memory
without a clash between two devices with different data
widths.
Shared Memory Mode
System Interface
The Shared Memory mode is the other fundamental op-
erating mode available on the PCnet-ISA+ controller.
ThePCnet-ISA+ controllerusesthesamedescriptorand
buffer architecture as the LANCE, but these data struc-
tures are stored in static RAM controlled by the
PCnet-ISA+ controller. The static RAM is visible as a
memory resource to the PC. The other resources look
the same as in the Bus Master mode.
The PCnet-ISA+ controller uses an internal address
comparator to perform SRAM prefetches on the Private
Data Bus; the SA0-15 signals are used internally to de-
termine whether a SRAM read cycle prefetch is a match
or a miss.
The Boot PROM is selected by an external device which
drives the Boot PROM Address Match (BPAM) input to
the PCnet-ISA+ controller. The PCnet-ISA+ controller
can perform two 8-bit accesses from the 8-bit Boot
PROM and presents 16-bits of data. The shared mem-
ory works the same way, with an external device
generating Shared Memory Address Match and the
PCnet-ISA+ controller performing the read or write and
the 8 to 16-bit data conversion.
Access to the Ethernet controller registers, board con-
figuration registers, and Address PROM is done with
on-chip address comparators.
Network Interface
The PCnet-ISA+ controller can be connected to an IEEE
802.3 network via one of two network interface ports.
The Attachment Unit Interface (AUI) provides an IEEE
802.3 compliant differential interface to a remote MAU
or an on-board transceiver. The 10BASE-T interface
provides a twisted-pair Ethernet port. The PCnet-ISA+
controller provides three modes of network interface
Converting shared memory accesses from 8-bit cycles
to 16-bit cycles allows use of the much faster 16-bit cy-
cle timing while cutting the number of bus cycles in half.
Am79C961
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selection: automatic selection, software selection, and
jumper selection of AUI or 10BASE-T interface.
both AUI and 10BASE-T interfaces are connected, the
10BASE-T interface is selected over AUI. If the
PCnet-ISA+ controller is initialized for software selection
of network interface, it will read the PORTSEL [1:0] bits
in the Mode register (CSR15.8 and CSR15.7) to deter-
mine which interface needs to be activated.
In the automatic selection mode, the PCnet-ISA+ con-
troller will select the interface that is connected to the
network by checking the Link Status state machine. If
A[0-15]
Boot
PROM
CE
OE
D[0-7]
BPCS
PRDB[0-7]
PRAB(0:15)
SD[0-15]
SA[0-15]
PCnet-ISA+
Controller
16-Bit
System Data
2
PRDB[2]/EEDO
PRDB[1]/EEDI
PRDB[0]/EESK
EECS
DO
1
DI
EEPROM
24-Bit System
Address
0
VCC
SK
CS
SMAM
ORG
SHFBUSY
BPAM
ISA
Bus
SROE
SRWE
A[0-15]
D[0-7]
WE
SRAM
CS
OE
VCC
SHFBUSY
CLK
BPAM
SMAM
SIN
External
Glue
SA[16]
Logic
LA[17-23]
MEMCS16
18183B-9
Shared Memory Block Diagram
Plug and Play Compatible
1-506
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AMD
A[0-15]
D[0-7]
Flash
WE
CS
PRDB[0-7]
PRAB[0-15]
OE
BPCS
SROE
SD[0-15]
PCnet-ISA+
16-Bit
System Data
Controller
PRDB[2]/EEDO
PRDB[1]/EEDI
DO
DI
24-Bit System
Address
EEPROM
SA[0-19]
SK
CS
VCC
PRDB[0]/EESK
EECS
ORG
SRWE
IRQ12/SRCS
ISA
Bus
SHFBUSY SRAM BPAM
OE
A[0-15]
SRAM
WE
CS
D[0-7]
SIN
MEMCS16
CLK
VCC
External
BPAM
SRAM
Glue
Logic
SHFBUSY
SA[16]
LA[17-23]
18183B-10
Shared Memory Block Diagram
Plug and Play Compatible with Flash Memory Support
PLUG AND PLAY
Operation
If the PCnet-ISA+ ethernet controller is used to boot off
the network, the device will come up active at RESET,
otherwise it will come up inactive. Information stored in
the serial EEPROM is used to identify the card and to
describe the system resources required by the card,
such as I/O space, Memory space, IRQs and DMA
channels. This information is stored in a standardized
Read Only format. Operation of the Plug and Play sys-
tem is shown as follows.
Plug and Play is a standardized method of configuring
jumperless adapter cards in a system. Plug and Play is a
Microsoft standard and is based on a central software
configuration program, either in the operating system or
elsewhere, which is responsible for configuring all Plug
and Play cards in a system. Plug and Play is fully sup-
ported by the PCnet-ISA+ ethernet controller.
For a copy of the Microsoft Plug and Play specification
contactMicrosoftInc. Thisspecificationshouldberefer-
enced in addition to PCnet-ISA+ Technical Reference
Manual and this data sheet.
Am79C961
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either reading the READ_DATA PORT or writing to the
■ Isolate the Plug and Play card
■ Read the cards resource data
■ Identify the card
WRITE_DATA PORT. Once the ADDRESS PORT has
been written, any number of reads or writes can occur
without having to rewrite the ADDRESS PORT.
■ Configure its resources
The ADDRESS PORT is also the address to which the
initiation key is written to, which is described later.
The Plug and Play mode of operation allows the follow-
ing benefits to the end user.
WRITE_DATA PORT
■ Eliminates all jumpers or dip switches from the
The WRITE_DATA PORT is the address to which all
writes to the internal Plug and Play registers occur. The
destination of the data written to the WRITE_DATA
PORT is determined by the last value written to the
ADDRESS PORT.
adapter card
■ Ease of use is greatly enhanced
■ Allows the ability to uniquely address identical
cards in a system, without conflict
■ Allows the software configuration program or OS
to read out the system resource requirements
required by the card
READ_DATA PORT
The READ_DATA PORT is used to read information
from the internal Plug and Play registers. The register to
be read is determined by the last value of theADDRESS
PORT.
■ Defines a mechanism to set or modify the current
configuration of each card
■ Maintain backward compatability with other ISA
The I/O address of the READ_DATA PORT is set by
writing the chosen I/O location to Plug and Play Register
0. The isolation protocol can determine that the address
chosen is free from conflict with other devices I/O ports.
bus adapters
Auto-Configuration Ports
Three 8 bit I/O ports are used by the Plug and Play con-
figuration software on each Plug and Play device to
communicate with the Plug and Play registers. The
ports are listed in the table below. The software configu-
ration space is defined as a set of 8 bit registers. These
registers are used by the Plug and Play software con-
figuration to issue commands, access the resource
information, checkstatus, andconfigurethePCnet-ISA+
controller hardware.
Initiation Key
The PCnet-ISA+ controller is disabled at reset when op-
erating in Plug and Play mode. It will not respond to any
memory or I/O accesses, nor will the PCnet-ISA+ con-
troller drive any interrupts or DMA channels.
The initiation key places the PCnet-ISA+ device into the
configurationmode. Thisisdonebywritingapredefined
pattern to the ADDRESS PORT. If the proper sequence
of I/O writes are detected by the PCnet-ISA+ device, the
Plug and Play auto-configuration ports are enabled.
Thissequencemustbesequential, i.e., anyotherI/Oac-
cess to this I/O port will reset the state machine which is
checking the pattern. Interrupts should be disabled dur-
ing this time to eliminate any extraneous I/O cycles.
Port
Name
Location
Type
ADDRESS
0X279 (Printer Status Port)
Write-only
WRITE-DATA 0xA79 (Printer status port
+ 0x0800)
Write-only
Read-only
READ-DATA
Relocatable in range
0x0203-0x03FF
The exact sequence for the initiation key is listed below
in hexadecimal.
6A, B5, DA, ED, F6, FB, 7D, BE
DF, 6F, 37, 1B, 0D, 86, C3, 61
B0, 58, 2C, 16, 8B, 45, A2, D1
E8, 74, 3A, 9D, CE, E7, 73, 39
The address and Write_DATA ports are located at fixed,
predefined I/O addresses. The Write_Data port is lo-
cated at an alias of the Address port. All three
auto-configuration ports use a 12-bit ISA address
decode.
The READ_DATA port is relocatable within the range
0x203–0x3FF by
WRITE_DATA port.
a
command written to the
Isolation Protocol
A simple algorithm is used to isolate each Plug and Play
card. This algorithm uses the signals on the ISA bus and
requires lock-step operation between the Plug and Play
hardware and the isolation software.
ADDRESS PORT
The internal Plug and Play registers are accessed by
writing the address to the ADDRESS PORT and then
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Check-
sum
Serial
Number
Vendor
ID
State
Isolation
Byte Byte Byte Byte Byte Byte Byte Byte Byte
Shift
0
3
2
1
0
3
2
1
0
Read from serial
isolation register
Get one bit from
serial identifier
18183B-12
Shifting of Serial Identifier
Yes
No
ID bit = “1H”
The shift order for all Plug and Play serial isolation and
resource data is defined as bit[0], bit[1], and so on
through bit[7].
Leave SD in
high-impedance
Drive “55H”
on SD[7:0]
No
Hardware Protocol
SD[1:0] = “01”
Yes
The isolation protocol can be invoked by the Plug and
Play software at any time. The initiation key, described
earlier, puts all cards into configuration mode. The hard-
ware on each card expects 72 pairs of I/O read
accessestotheREAD_DATAport. Thecard’sresponse
to these reads depends on the value of each bit of the
serial identifier which is being examined one bit at a time
in the sequence shown above.
Wait for next read from serial isolation register
Drive “AAH”
Leave SD in
on SD[7:0]
high-impedance
If the current bit of the serial identifier is a “1”, then the
card will drive the data bus to 0x55 to complete the first
I/O read cycle. If the bit is “0”, then the card puts its data
bus driver into high impedance. All cards in high imped-
ance will check the data bus during the I/O read cycle to
sense if another card is driving D[ 1:0] to “01”. During the
second I/O read, the card(s) that drove the 0x55, will
now drive a 0xAA. All high impedance cards will check
the data bus to sense if another card is driving D[ 1:0] to
“10”. Between pairs of Reads, the software should wait
at least 30 µs.
No
SD[1:0] = “10”
After I/O read
ID = 0;
completes, fetch
next ID bit from
serial identifier
Yes
other card
ID = 1
State
Sleep
Read all 72 bits
from serial
identifier
No
Yes
If a high impedance card sensed another card driving
the data bus with the appropriate data during both cy-
cles, then that card ceases to participate in the current
iteration of card isolation. Such cards, which lose out,
will participate in future iterations of the isolation
protocol.
One
Card
Isolated
18183B-11
Plug and Play ISA Card
Isolation Algorithm
NOTE: During each read cycle, the Plug and Play hard-
ware drives the entire 8-bit databus, but only checks the
lower 2 bits.
If a card was driving the bus or if the card was in high im-
pedance and did not sense another card driving the bus,
then it should prepare for the next pair of I/O reads. The
card shifts the serial identifier by one bit and uses the
shifted bit to decide its response. The above sequence
is repeated for the entire 72-bit serial identifier.
The key element of this mechanism is that each card
contains a unique number, referred to as the serial iden-
tifier for the rest of the discussion. The serial identifier is
a 72-bit unique, non-zero, number composed of two,
32-bit fields and an 8-bit checksum. The first 32-bit field
is a vendor identifier. The other 32 bits can be any value,
for example, a serial number, part of a LAN address, or a
static number, as long as there will never be two cards in
a single system with the same 64 bit number. The serial
identifier is accessed bit-serially by the isolation logic
and is used to differentiate the cards.
At the end of this process, one card remains. This card is
assigned a handle referred to as the Card Select Num-
ber (CSN) that will be used later to select the card.
Cards which have been assigned a CSN will not partici-
pate in subsequent iterations of the isolation protocol.
Am79C961
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Cards must be assigned a CSN before they will respond
to the other commands defined in the specification.
There are two other special considerations for the soft-
ware protocol. During an iteration, it is possible that the
0x55 and 0xAA combination is never detected. It is also
possible that the checksum does not match If either of
these cases occur on the first iteration, it must be as-
sumed that the READ_DATA port is in conflict. If a
conflict is detected, then the READ_DATA port is relo-
cated. The above process is repeated until a non-
conflicting location for the READ_DATA port is found.
Theentirerangebetween0x203and0x3FFisavailable,
however in practice it is expected that only a few loca-
tions will be tried before software determines that no
Plug and Play cards are present.
It should be noted that the protocol permits the 8-bit
checksum to be stored in non-volatile memory on the
card or generated by the on-card logic in real-time. The
sameLFSRalgorithmdescribedintheinitiationkeysec-
tion of the Plug and Play specification is used in the
checksum generation.
Software Protocol
The Plug and Play software sends the initiation key to all
Plug and Play cards to place them into configuration
mode. The software is then ready to perform the isola-
tion protocol.
During subsequent iterations, the occurrence of either
of these two special cases should be interpreted as the
absence of any further Plug and Play cards (i.e. the last
card was found in the previous iteration). This termi-
nates the isolation protocol.
The Plug and Play software generates 72 pairs of l/O
read cycles from the READ_DATA port. The software
checks the data returned from each pair of I/O reads for
the 0x55 and 0xAA driven by the hardware. If both 0x55
and 0xAA are read back, then the software assumes
that the hardware had a “1” bit in that position. All other
results are assumed to be a “0.”
NOTE: The software must delay 1 ms prior to starting
the first pair of isolation reads, and must wait 250 msec
between each subsequent pair of isolation reads. This
delay gives the ISA card time to access information from
possibly very slow storage devices.
During the first 64 bits, software generates a checksum
using the received data. The checksum is compared
with the checksum read back in the last 8 bits of the
sequence.
Plug and Play Card Control Registers
The state transitions and card control commands for the
PCnet-ISA+ controller are shown in the following figure.
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Power up
RESET or
Reset Command
Set CSN = 0
Active
Commands
State
Wait for Key No active
commands
Initiation Key
Active
State
Commands
SLEEP
Reset
Wait for Key
Wake[CSN]
(WAKE = 0) AND (CSN = 0)
(WAKE ≠ 0) AND (Wake = CSN)
Lose serial
(WAKE <> CSN)
isolation OR
(WAKE <> CSN)
Active
Commands
Active
Commands
State
State
Isolation
Reset
Config
Reset
Wait for Key
Set RD_Data
Port
Serial Isolation
Wake[CSN]
Wait for Key
Wake[CSN]
Resource Data
Status
Logical Device
I/O Range Check
Activate
Set CSN
Configuration
Registers
18183B-13
Notes
1. CSN = Card Select Number
2. RESET or the Reset command
causes a state transition from the cur-
rent state to Wait for Key and sets all
CSNs to zero.
3. The Wait for Key command causes a
state transition from the current state
to Wait for Key.
Plug and Play ISA Card State Transitions
Plug and Play Registers
The PCnet-ISA+ controller supports all of the defined
Plug and Play card control registers. Refer to the tables
on the following pages for detailed information.
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Plug and Play Standard Registers
Address
Port Value
Name
Definition
Set RD_DATA Port
Serial Isolation
Config Control
0x00
0x01
0x02
Writing to this location modifies the address of the port used for reading from the
Plug and Play ISA cards. Bits[7:00] become I/O read port address bits [9:02].
Reads from this register are ignored. I/O Address bits 11:10 should = 00, and 1:0 = 11.
A read to this register causes a Plug and Play card in the Isolation state to compare
one bit of the board’s ID. This process is fully described above. This register is
read only.
Bit[0] - Reset all logical devices and restore configuration registers to their
power-up values.
Bit[1] - Return to the Wait for Key state
Bit[2] - Reset CSN to 0
A write to bit[0] of this register performs a reset function on all logical devices. This
resets the contents of configuration registers to their default state. All card’s logical
devices enter their default state and the CSN is preserved.
A write to bit[1] of this register causes all cards to enter the Wait for Key state but
all CSNs are preserved and logical devices are not affected.
A write to bit[2] of this register causes all cards to reset their CSN to zero.
This register is write-only. The values are not sticky, that is, hardware will
automatically clear them and there is no need for software to clear the bits.
Wake[CSN]
0x03
0x04
A write to this port will cause all cards that have a CSN that matches the write
data[7:0] to go from the Sleep state to either the Isolation state if the write data for
this command is zero or the Config state if the write data is not zero. This register
is write-only. Writing to this register resets the EEPROM pointer to the beginning of
the Plug and Play Data Structure.
Resource Data
A read from this address reads the next byte of resource information. The Status
register must be polled until bit[0] is set before this register may be read. This
register is read-only.
Status
0x05
0x06
Bit[0] when set indicates it is okay to read the next data byte from the Resource
Data register. This register is read-only.
Card Select Number
A write to this port sets a card’s CSN. The CSN is a value uniquely assigned to
each ISA card after the serial identification process so that each card may be
individually selected during a Wake [CSN] command. This register is read/write.
Logical Device Number
0x07
Selects the current logical device. This register is read only. The PCnet-ISA+ controller
has only 1 logical device, and this register contains a value of 0x00
is that the PCnet-ISA+ controller does not require as
Plug and Play Logical Device
Configuration Registers
The PCnet-ISA+ controller supports a subset of the
defined Plug and Play logical device control registers.
The reason for only supporting a subset of the registers
many system resources as Plug and Play allows. For
instance, Memory Descriptor 2 is not used, as the
PCnet-ISA+ controller only requires two memory de-
scriptors, one for the Boot PROM/Flash, and one for the
SRAM in Shared Memory Mode.
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Plug and Play Logical Device Control Registers
Address
Port Value
Name
Definition
Activate
0x30
For each logical device there is one activate register that controls whether or not
the logical device is active on the ISA bus. Bit[0], if set, activates the logical device.
Bits[7:1] are reserved and must be zero. This is a read/write register. Before a
logical device is activated, I/O range check must be disabled.
I/O Range Check
0x31
This register is used to perform a conflict check on the I/O port range programmed
for use by a logical device.
Bit[7:2] Reserved
Bit 1[1] Enable I/O Range check, if set then I/O Range Check is enabled. I/O range
check is only valid when the logical device is inactive.
Bit[0], if set, forces the logical device to respond to I/O reads of the logical device’s
assigned I/O range with a 0x55 when I/O range check is in operation. If clear, the
logical device drives 0xAA. This register is read/write.
Memory Space Configuration
Register
Index
Name
Definition
Memory base address
bits[23:16] descriptor 0
0x40
0x41
0x42
Read/write value indicating the selected memory base address bits[23:16] for
memory descriptor 0. This is the Boot Prom Space.
Memory base address
bits[15:08] descriptor 0
Read/write value indicating the selected memory base address bits[15:08] for
memory descriptor 0.
Memory control
Bits[2:1] specifies 8/16-bit control. The encoding is identical to memory control
(bits[4:3]) of the information field in the memory descriptor.
Bit[0], =0, indicates the next field is used as a range length for decode
(implies range length and base alignment of memory descriptor are equal).
Bit[0] is read-only.
Memory upper limit
address;
bits[23:16] or range
length;
bits[23:16] for
descriptor 0
0x43
0x44
Read/write value indicating the selected memory high address bits[23:16] for
memory descriptor 0.
If bit[0] of memory control is 0, this is the range length.
If bit[0] of memory control is 1, this is considered invalid.
Memory upper limit
bits[15:08] or range
length;
Read/write value indicating the selected memory high address bits[15:08] for
memory descriptor 0, either a memory address or a range length as described above.
bits[15:08] for
descriptor 0
Memory descriptor 1
0x48-0x4C Memory descriptor 1. This is the SRAM Space for Shared Memory.
I/O Space Configuration
Register
Index
Name
Definition
I/O port base address
bits[15:08] descriptor 0
0x60
Read/write value indicating the selected I/O lower limit address bits[15:08] for I/O
descriptor 0. If a logical device indicates it only uses 10 bit encoding, then bits[15:10]
do not need to be supported.
I/O port base address
bits[07:00] descriptor 0
0x61
Read/write value indicating the selected I/O lower limit address bits[07:00] for I/O
descriptor 0.
Am79C961
1-513
AMD
P R E L I M I N A R Y
I/O Interrupt Configuration
Register
Index
Name
Definition
Interrupt request level
select 0
0x70
Read/write value indicating selected interrupt level. Bits[3:0] select which interrupt
level used for Interrupt 0. One selects IRQL 1, fifteen selects IRQL fifteen. IRQL 0 is
not a valid interrupt selection and represents no interrupt selection.
Interrupt request type
select 0
0x71
Read/write value indicating which type of interrupt is used for the Request Level
selected above.
Bit[1] : Level, 1 = high, 0 = low
Bit[0] : Type, 1 = level, 0 = edge
The PCnet-ISA+ controller only supports Edge High and Level Low Interrupts.
DMA Channel Configuration
Register
Index
Name
Definition
DMA channel select 0
0x74
Read/write value indicating selected DMA channels. Bits[2:0] select which DMA
channel is in use for DMA 0. Zero selects DMA channel 0, seven selects DMA
channel 7. DMA channel 4, the cascade channel is used to indicate no DMA channel
is active.
This is a 2-Kbit device organized as 128 x 16 bit words.
A map of the device as used in the PCnet-ISA+ control-
ler is below. The information stored in the EEPROM is
as follows:
DETAILED FUNCTIONS
EEPROM
Interface
IEEE address
6 bytes
10 bytes
4 bytes
12 bytes
19 bytes
1 byte
TheEEPROMsupportedbythePCnet-ISA+ controlleris
an industry standard 93C56 2-Kbit EEPROM device
which uses a 4-wire interface. This device directly inter-
faces to the PCnet-ISA+ controller through a 4-wire
interface which uses 3 of the private data bus pins for
Data In, Data Out, and Serial Clock. The Chip Select pin
is a dedicated pin from the PCnet-ISA+ controller.
Reserved
EISA ID
ISACSRs
Plug and Play Defaults
8-Bit Checksum
External Shift Chain
Plug and Play Config Info
Note: All data stored in the EEPROM is stored in bit-
reversal format. Each word (16 bits) must be written into
the EEPROM with bit 15 swapped with bit 0, bit 14
swapped with bit 1, etc.
2 bytes
192 bytes
1-514
Am79C961
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This byte map is for the case where a non-PCnet Family
compatible software driver is implemented.
Serial EEPROM Byte Map
The following is a byte map of the XXC56 series of
EEPROMs used by the PCnet-ISA+ Ethernet Controller.
Word
Location
Byte 1
Byte 0
0
IEEE Address
(Bytes 0–5)
Byte 3
Byte 2
1
Byte 5
Byte 4
2
Byte 7
Byte 6
3
Byte 9
Byte 8
4
Byte 11
Byte 13
Byte 15
EISA Byte 1
EISA Byte 3
Byte 10
Byte 12
Byte 14
EISA Byte 0
EISA Byte 2
5
6
7
8
EISA Config Reg.
Internal Registers
9
MSRDA, ISACSR0
MSWRA, ISACSR1
A
B
MISC Config, ISACSR2
LED1 Config, ISACSR5
LED2 Config, ISACSR6
LED3 Config, ISACSR7
C
D
E
F
PnP 0x61
PnP 0x71
Unused
PnP 0x60
10
11
12
13
14
15
16
17
18
19
1A
1B
1F
20
PnP 0x70
PnP 0x74
PnP 0x40
PnP 0x42
PnP 0x44
PnP 0x48
PnP 0x4A
PnP 0x4C
PnP 0xF0
Plug and Play Reg.
PnP 0x41
PnP 0x43
Unused
PnP 0x49
PnP 0x4b
Unused
8-bit Checksum
External Shift Chain
Unused Locations
Plug and Play Starting Location
See Appendix C
Note:
Checksum is calculated on words 0 through 0x1Ah (first 54 Bytes).
Am79C961
1-515
AMD
P R E L I M I N A R Y
This byte map is for the case where a PCnet Family
Serial EEPROM Byte Map
The following is a byte map of the XXC56 series of
EEPROMs used by the PCnet-ISA+ Ethernet Controller.
compatible software driver is implemented.
(This byte map is an application reference for use in de-
veloping AMD software devices.)
Word
Location
0
1
Byte 1
Byte 0
Byte 3
Byte 2
IEEE Address
(Bytes 0–5)
2
Byte 5
Byte 4
3
Reserved
HWID (01H)
Reserved
Reserved
4
5
User Space 1
16-Bit Checksum 1
6
7
ASCII W(0 x 57H)
EISA Byte 1
ASCII W(0 x 57H)
EISA Byte 0
8
EISA Config Reg.
Internal Registers
9
EISA Byte 3
EISA Byte 2
A
B
C
D
E
F
MSRDA, ISACSR0
MSWRA, ISACSR1
MISC Config, ISACSR2
LED1 Config, ISACSR5
LED2 Config, ISACSR6
LED3 Config, ISACSR7
10
11
12
PnP 0x61
PnP 0x71
Unused
PnP 0x60
I/O Ports
PnP 0x70
PnP 0x74
PnP 0x40
PnP 0x42
PnP 0x44
PnP 0x48
PnP 0x4A
PnP 0x4C
PnP 0xF0
Interrupts
DMA Channels
ROM Memory
Plug and Play Reg. 13
PnP 0x41
PnP 0x43
Unused
14
15
16
17
18
19
1A
1B
1F
PnP 0x49
PnP 0x4b
Unused
RAM Memory
Vendor Byte
8-bit Checksum 2
External Shift Chain
Unused Locations
See Appendix C
Note:
20
Plug and Play Starting Location
See Appendix C
Checksum 1 is calculated on words 0 through 5 plus word 7.
Checksum 2 is calculated on words 0 through 0x1Ah (first 54 Bytes).
1-516
Am79C961
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AMD
and Play operation. These registers control the configu-
ration of the PCnet-ISA+ controller.
Plug and Play Register Map
The following chart and its bit descriptions show the in-
ternal configuration registers associated with the Plug
Plug and Play
Register
Bit 7
Bit 6
Bit 5
Bit 4
READ_DATA
SERIAL ISOLATION
Bit 3
Bit 2
Bit 1
Bit 0
0x00
0x01
0x02
0
0
0
0
0
RST
CSN
WAIT
KEY
RST
ALL
0x03
0x04
0x05
WAKE [CSN]
RESOURCE_DATA
0
0
0
0
0
0
0
READ
STATUS
0x06
0x07
0x30
0x31
CSN
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ACTIVATE
IORNG
0
IORNG
READ_DATA
Address of Plug and Play READ_DATA Port.
Used in the Serial Isolation process.
Resets CSN register to zero.
SERIAL_ISOLATION
RST_CSN
WAIT_KEY
RST_ALL
Resets Wait for Key State.
Resets all logical devices.
WAKE [CSN]
READ_STATS
RESOURCE_DATA
CSN
Will wake up if write data matches CSN Register.
Read Status of RESOURCE DATA.
Next pending byte read from EEPROM.
Plug and Play CSN Value.
ACTIVATE
Indicates that the PCnet-ISA+ device should be activated.
IORNG
Bits used to enable the I/O Range Check Command.
Am79C961
1-517
AMD
P R E L I M I N A R Y
The following chart and its bit descriptions show the in-
ternal command registers associated with the Plug and
Play operation. These registers control the PCnet-ISA+
controller Plug and Play operation.
Plug and
Play Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x60
0
0
0
0
0
0
1
IOAM3
0x61
IOAM2
IOAM1
IOAM0
0
0
0
0
0
0x70
0
0
0
0
IRQ3
IRQ2
IRQ1
IRQ0
0x71
0
0
0
0
0
0
IRQ_LVL
IRQ_TYPE
0x74
0
0
0
0
0
DMA2
DMA1
DMA0
0x40
0
0
0
0
1
1
0
0
1
0
1
0
0
1
0
0
BPAM3
0x41
BPAM2
BPAM1
BPAM0
0
0
0
0
0x42
0
0
0
0
0
BP_16B
0
0x43
1
1
1
1
1
1
BPSZ3
0x44
BPSZ2
BPSZ1
BPSZ0
0
0
0
0
0x48
0
0
0
0
1
0
SRAM3
0x49
SRAM2
SRAM1
SRAM0
0
0
0
0
0x4A
0x4B
0x4c
0
0
0
0
0
SR16B
0
SRSZ3
0
1
SRSZ2
0
1
SRSZ1
0
1
SRSZ0
0
1
0
1
0
1
0
0xF0
FL_SEL
BP_CS
APROM_EN AEN_CS
IO_MODE
IRQ[3:0]
IRQ selection on the ISA bus
(PnP 0x70). Controls which inter-
rupt will be asserted. ISA Edge
sensitive or EISA level mode is
controlled by IRQ_TYPE bit in
PnP 0x71. Default is ISA Edge
Sensitive. The IRQ signals will
not be driven unless PnP activate
register bit is set.
Plug & Play Register Locations Detailed
Description (Refer to the Plug & Play
Register Map above.)
IOAM[3:0]
I/O Address Address Match to
bits [8:5] of SA bus (PnP
0x60–0x61). Controls the base
address of PCnet-ISA+. The
IOAM will be written with a value
from the EEPROM.
IRQ[3:0]
ISA IRQ Pin
IRQ3 (Default)
IRQ4
IOAM[3:0]
Base Address (Hex)
0
0
0
1
1
1
1
1
0
1
1
0
0
0
1
1
1
0
0
0
1
1
0
1
1
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
200
220
240
260
280
2A0
2C0
2E0
300
320
340
360
380
3A0
3C0
3E0
IRQ5
IRQ9
IRQ10
IRQ11
IRQ12
IRQ15
IRQ_TYPE
IRQ Type (PnP 0x71). Indicates
the type of interrupt setting; Level
is 1, Edge is 0.
IRQ_LVL
IRQ Level (PnP 0x71). A read-
only register bit that indicates the
type of setting, active high or low.
Always
complement
of
IRQ_TYPE.
1-518
Am79C961
P R E L I M I N A R Y
DMA Channel Select (PnP
AMD
DMA[2:0]
BPSZ[3:0]
Boot PROM Size
0x74). Controls the DRQ and
DMA selection of PCnet-ISA+.
The DMA[2:0] register will be
written with a value from the
0
1
1
1
1
x
1
1
1
0
x
1
1
0
0
x
1
0
0
0
No Boot PROM Selected
8 K
16 K
32 K
64 K
EEPROM.
{For Bus Master
Mode Only} The DRQ signal will
not be driven unless EE_VALID
is set or Non-EEPROM sequen-
tial write process is complete.
SRAM[3:0]
Static RAM Address Match to
bits [16:13] of SA bus (PnP
0x48–0x49). Selects the starting
location of the Shared memory
by using SA[16:13] for perform-
ing address comparisons. The
shared memory address match,
the SMAM is asserted low.
SRAM[3] value must reflect the
external address match logic for
SA[16].
DMA[2:0]
DMA Channel (DRQ/DACK Pair)
0
1
1
1
1
0
1
1
1
1
0
1
Channel 3
Channel 5
Channel 6
Channel 7
BPAM[3:0]
Boot PROM Address Match to
bits [23:16] of SA bus (PnP
0x40–0x41). Selects the location
where the Boot PROM Address
match decode is started. The
BPAM will be written with a value
from the EEPROM.
SRAM[2:0]
SA[15:13]
SRAM Size
(K bytes)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8, 16, 32, 64
8
BPAM[3:0]
Address
Location (Hex)
C0000
Size Supported
(K bytes)
8, 16
8
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
8, 16, 32, 64
8, 16, 32
C2000
C4000
C6000
C8000
CA000
CC000
CE000
D0000
D2000
D4000
D6000
D8000
DA000
DC000
DE000
8
8
8, 16
8, 16
8
8
8, 16, 32
8
SR_16B
Static RAM 16-bit access (PnP
0x4A). Asserted if SRAM cycles
should respond as an 16-bit
device.
8, 16
8
8, 16, 32, 64
SRSZ[3:0]
Static RAM Size (PnP 0x4B–
0x4C). Selects the size of the
static RAM selected.
8
8, 16
8
SRSZ[3:0]
Shared Memory Size
8, 16, 32
0
1
1
1
1
x
1
1
1
0
x
1
1
0
0
x
1
0
0
0
No Static RAM Selected
8
8 K
8, 16
8
16 K
32 K
64 K
BP_16B
Boot PROM 16-bit access (PnP
0x42). Is asserted if Boot PROM
cycles should respond as an
16-bit device. In Bus Master
mode, all boot PROM cycles will
only be 8 bits in width.
Vendor Defined Byte (PnP 0x0F)
IO_MODE
I/O Mode. When set to one, the
internal selection will respond as
a 16-bit port, (i.e. drive IOCS16
pin). When IO_MODE is set to
zero, (Default), the internal I/O
BPSZ[3:0]
Boot
PROM
Size
(PnP
0x43–0x44). Selects the size of
the boot PROM selected.
Am79C961
1-519
AMD
P R E L I M I N A R Y
selection will respond as an 8-bit
memory device. In Bus Master
Mode, BPCS is replaced with
Flash_OE. IRQ12 becomes
Flash_WE. The Flash’s CS pin is
grounded. In shared memory
mode, BPCS is replaced with
Flash_CS. IRQ12 becomes
Static_RAM_CS pin. The SROE
and SRWE signals are con-
nected to both the SRAM and
Flash memory devices. FL_SEL
is cleared by a reset, which is the
default.
port.
AEN_CS
External Decode Logic for I/O
Registers. When written with a
one, the PCnet-ISA+ will use the
AEN pin as I/O chip select bar, to
allow for external decode logic
for the upper address bit of SA
[9:5]. The purpose of this pin is to
allow I/O locations, not sup-
ported with the IOAM[3:0],
selection, to be defined outside
the range 0x200–0x3F7. When
set to a zero, (Default), I/O Selec-
tion will use IOAM[3:0].
Shared Memory Configuration Bits (Not
Defined for Bus Master Mode)
In Shared Memory Mode, the address comparison
above the 15th bit must be performed by external logic.
All address comparisons for bit 15th and below will use
the internal compare logic.
APROM_EN
External Parallel IEEE Address
PROM. When set, the IRQ15 pin
is reconfigured to be an Address
Chip Select low, similar to APCS
pin in the existing PCnet-ISA
(Am79C960) device. The pur-
pose of this bit is to allow for both
a serial EEPROM and parallel
PROM to coexist. When
APROM_EN is set, the IEEE ad-
dress located in the serial
EEPROM will be ignored and
parallel access will occur over
SRAM[3:0],
SR_16B, SRSZ[3:0] These are not defined in bus-
master mode. BP_16B must be
written with a zero in bus-master
mode.
Note: In Bus Master Mode, the BP_16B is always con-
sidered an 8-bit device. If SBHE signal is left uncon-
nected, in shared memory mode (i.e. 8-bit Slot), all
memory and I/O access will assume 8-bit accesses. It is
the responsibility of external logic to drive MEMCS16
signal for the appropriate 128 Kbit segment decoded
from the LA[23:17] signals. MEMCS16 should be driven
when accessing an 8-bit memory resource.
the
PRDB
bus.
When
APROM_EN is cleared, default
state, the IEEE address will be
read in from the serial device and
written to an internal RAM. When
the I/O space of the IEEE PROM
is selected, PCnet-ISA+, will ac-
cess the contents of this RAM for
I/O read cycles. I/O write cycles
will be ignored.
Checksum Failure
After RESET, the PCnet-ISA+ controller begins reading
the EEPROM and storing the information in registers in-
side PCnet-ISA+ controller. PCnet-ISA+ controller does
a checksum on word locations 0-1Ah inclusive and if the
byte checksum = 0FFh, then the data read from the
EEPROM is considered good. If the checksum is not
equal to 0FFh, then the PCnet-ISA+ controller enters
what is called software relocatable mode.
BP_CS
Boot PROM Chip Select. When
BP_CS is set to one, BALE will
act as an external chip select (ac-
tive low) above bit 15 of the
address bus. BALE = 0, will se-
lect the boot PROM when MEMR
is asserted low if the BP_CS bit is
set and BPAM[2:0] match
In software relocatable mode, the device functions the
same as in Plug and Play mode, except that it does not
respond to the same initiation key as Plug and Play sup-
ports. Instead, a different key is used to bring
PCnet-ISA+ controlleroutoftheWaitForKeystate. This
key is as follows:
SA[15:13]
and
BPSZ[3:0]
matches the selected size.
When BP_CS is set to zero.
BALE will act as the normal ad-
dress latch strobe to capture the
upper address bits for memory
access to the boot PROM.
BP_CS is by default low. The pri-
mary purpose of this bit is to allow
non-ISA bus applications to sup-
port larger Boot PROMS or
non-standard Boot PROM/Flash
locations.
6B, 35, 9A, CD, E6, F3, 79, BC
5E, AF, 57, 2B, 15, 8A, C5, E2
F1, F8, 7C, 3E, 9F, 4F, 27, 13
09, 84, 42, A1, D0, 68, 34, 1A
FL_SEL
Flash Memory Device Selected.
When set, the Boot PROM is re-
placed with an external Flash
1-520
Am79C961
P R E L I M I N A R Y
AMD
the SROE and SRWE signals are connected to both the
SRAM and Flash devices.
Use Without EEPROM
In some designs, especially PC motherboard applica-
tions, it may be desirable to eliminate the EEPROM
altogether. This would save money, space, and power
consumption.
Optional IEEE Address PROM
Normally, the Ethernet physical address will be stored in
the EEPROM with the other configuration data. This re-
duces the parts count, board space requirements, and
power consumption. The option to use a standard
parallel8bitPROMisprovidedtomanufactureswhoare
concerned about the non-volatile nature of EEPROMs.
The operation of this mode is similar to when the
PCnet-ISA+ controller encounters a checksum error, ex-
cept that to enter this mode the SHFBUSY pin is left
unconnected. The device will enter software relocatable
mode, and the BIOS on the motherboard can wake up
the device, configure it, load the IEEE address (possibly
stored in Flash ROM) into the PCnet-ISA+ controller,
and activate the device.
To use a 8 bit parallel prom to store the IEEE address
data instead of storing it in the EEPROM, the
APROM_EN bit is set in the Plug and Play registers by
the EEPROM upon RESET. IRQ15 is redefined by the
setting of this bit to be APCS, or ADDRESS PROM
CHIPSELECT. Thispinisconnectedtoanexternal8bit
PROM, such as a 27LS19. The address pins of the
PROM are connected to the lower address pins of the
ISA bus, and the data lines are connected to the private
data bus.
External Scan Chain
The External Scan Chain is a set of bits stored in the
EEPROM which are not used in the PCnet-ISA+ control-
ler but which can be used with external hardware to
allow jumperless configuration of external devices.
After RESET, the PCnet-ISA+ controller begins reading
the EEPROM and storing the information in registers in-
side the PCnet-ISA+ controller. SHFBUSY is held high
during the read of the EEPROM. If external circuitry is
added, such as a shift register, which is clocked from
SCLK and is attached to DO from the EEPROM, data
read out of the EEPROM will be shifted into the shift reg-
ister. After reading the EEPROM to the end of the
External Shift Chain, and if there is a correct checksum,
SHFBUSY will go low. This will be used to latch the infor-
mation from the EEPROM into the shift register. If the
checksum is invalid, SHFBUSY will not go low, indicat-
ing that the EEPROM may be bad.
In this mode, any accesses to the IEEE address will be
passed to the external PROM and the data will be
passed through the PCnet-ISA+ controller to the system
data bus.
EISA Configuration Registers
The PCnet-ISA+ controller has support for the 4-byte
EISA Configuration Registers. These are used in EISA
systems to identify the card and load the appropriate
configuration file for that card. This feature is enabled
using bit 10 of ISACSR2. When set to 1, the EISA Con-
figuration registers will be enabled and will be read at I/O
location 0xC80-0xC83. The contents of these 4 regis-
ters are stored in the EEPROM and are automatically
read in at RESET.
For more information on the use of this function, please
refer to the technical reference manual.
Flash PROM
Bus Interface Unit (BIU)
Use
The bus interface unit is a mixture of a 20 MHz state ma-
chine and asynchronous logic. It handles two types of
accesses; accesses where the PCnet-ISA+ controller is
aslaveandaccesseswherethePCnet-ISA+ controlleris
the Current Master.
Instead of using a PROM or EPROM for the Boot
PROM, it may be desirable to use a Flash or EEPROM
type of device for storing the Boot code. This would al-
low for in-system updates and changes to the
information in the Boot ROM without opening up the PC.
It may also be desirable to store statistics or drivers in
the Flash device.
In slave mode, signals like IOCS16 are asserted and
deasserted as soon as the appropriate inputs are re-
ceived. IOCHRDY is asynchronously driven LOW if the
PCnet-ISA+ controller needs a wait state. It is released
synchronously when the PCnet-ISA+ controller is ready.
Interface
To use a Flash-type device with the PCnet-ISA+ control-
ler, Flash Select is set in register 0F0h of the Plug and
Play registers. Flash Select is cleared by RESET (de-
fault).
When the PCnet-ISA+ controller is the Current Master,
all the signals it generates are synchronous to the on-
chip 20 MHz clock.
DMA Transfers
In bus master mode, BPCS becomes Flash_OE and
IRQ12 becomes Flash_WE. The Flash ROM devices
CS pin is connected to ground.
The BIU will initiate DMA transfers according to the type
of operation being performed. There are three primary
types of DMA transfers:
In shared memory mode, BPCS becomes Flash_ CS
and IRQ12 becomes the static RAM Chip Select, and
1. Initialization Block DMA Transfers
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Once the BIU has been granted bus mastership, it will
perform four data transfer cycles (eight bytes) before re-
linquishing the bus. The four transfers within the
mastership period will always be read cycles to
contiguous addresses. There are 12 words to transfer
so there will be three bus mastership periods.
The Initialization Block is vectored by the contents of
CSR1 (least significant 16 bits of address) and CSR2
(most significant 8 bits of address). The block contains
the user defined conditions for PCnet-ISA+ controller
operation, together with the address and length
information to allow linkage of the transmit and receive
descriptor rings.
2. Descriptor DMA Transfers
There is an alternative method to initialize the
PCnet-ISA+ controller. Instead of initialization via the
initialization block in memory, data can be written di-
rectly into the appropriate registers. Either method may
be used at the discretion of the programmer. If the regis-
ters are written to directly, the INIT bit must not be set, or
the initialization block will be read in, thus overwriting
the previously written information. Please refer to
Appendix D for details on this alternative method.
Once the BIU has been granted bus mastership, it will
perform the appropriate number of data transfer cycles
before relinquishing the bus. The transfers within the
mastership period will always be of the same type
(either all read or all write), but may be to non-
contiguous addresses. Only the bytes which need to be
read or written are accessed.
3. Burst-Cycle DMA Transfers
Once the BIU has been granted bus mastership, it will
perform a series of consecutive data transfer cycles be-
fore relinquishing the bus. Each data transfer will be
performed sequentially, with the issue of the address,
and the transfer of the data with appropriate output sig-
nals to indicate selection of the active data bytes during
the transfer. All transfers within the mastership cycle will
be either read or write cycles, and will be to contiguous
addresses. The number of data transfer cycles within
the burst is dependent on the programming of the
DMAPLUS option (CSR4, bit 14).
Reinitialization
The transmitter and receiver section of the PCnet-ISA+
controller can be turned on via the initialization block
(MODE Register DTX, DRX bits; CSR15[1:0]). The
state of the transmitter and receiver are monitored
through CSR0 (RXON, TXON bits). The PCnet-ISA+
controller should be reinitialized if the transmitter and/or
the receiver were not turned on during the original in-
itialization and it was subsequently required to activate
them, or if either section shut off due to the detection of
an error condition (MERR, UFLO, TX BUFF error).
If DMAPLUS = 0, a maximum of 16 transfers will be per-
formed. This may be changed by writing to the burst
register (CSR80), but the default takes the same
amount of time as the Am2100 family of LANCE-based
boards, a little over 5 µs.
Reinitializationmaybedoneviatheinitializationblockor
by setting the STOP bit in CSR0, followed by writing to
CSR15, and then setting the START bit in CSR0. Note
that this form of restart will not perform the same in the
PCnet-ISA+ controller as in the LANCE. In particular, the
PCnet-ISA+ controller reloads the transmit and receive
descriptor pointers with their respective base ad-
dresses.This means that the software must clear the
descriptor’s own bits and reset its descriptor ring point-
ers before the restart of the PCnet-ISA controller. The
reload of descriptor base addresses is performed in the
LANCE only after initialization, so a restart of the
LANCE without initialization leaves the LANCE pointing
at the same descriptor locations as before the restart.
If DMAPLUS = 1, the burst will continue until the FIFO is
filled to its high threshold (32 bytes in transmit opera-
tion) or emptied to its low threshold (16 bytes in receive
operation). The exact number of transfer cycles in this
case will be dependent on the latency of the system bus
to the BIU’s mastership request and the speed of
bus operation.
Buffer Management Unit (BMU)
The buffer management unit is a micro-coded 20 MHz
state machine which implements the initialization block
and the descriptor architecture.
Buffer Management
Buffer management is accomplished through message
descriptor entries organized as ring structures in mem-
ory. There are two rings, a receive ring and a transmit
ring. The size of a message descriptor entry is 4 words
(8 bytes).
Initialization
PCnet-ISA+ controller initialization includes the reading
of the initialization block in memory to obtain the operat-
ing parameters. The initialization block is read when the
INIT bit in CSR0 is set. The INIT bit should be set before
or concurrent with the STRT bit to insure correct opera-
tion. Four words at a time are read and the bus is
released at the end of each block of reads, for a total of
three arbitration cycles. Once the initialization block has
been read in and processed, the BMU knows where the
receiveandtransmitdescriptorringsare. Oncompletion
of the read operation and after internal registers have
been updated, IDON will be set in CSR0, and an inter-
rupt generated if IENA is set.
Descriptor Rings
Each descriptor ring must be organized in a contiguous
area of memory. At initialization time (setting the INIT bit
in CSR0), the PCnet-ISA+ controller reads the user-de-
fined base address for the transmit and receive
descriptor rings, which must be on an 8-byte boundary,
as well as the number of entries contained in the de-
scriptor rings. By default, a maximum of 128 ring entries
is permitted when utilizing the initialization block, which
uses values of TLEN and RLEN to specify the transmit
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and receive descriptor ring lengths. However, the ring
lengthscanbemanuallydefined(upto65535)bywriting
the transmit and receive ring length registers
(CSR76,78) directly.
relinquish ownership or to write to any field in the
descriptor entry. A device that is not the current owner of
a descriptor entry cannot assume ownership or change
any field in the entry.
Each ring entry contains the following information:
Descriptor Ring Access Mechanism
At initialization, the PCnet-ISA+ controller reads the
baseaddressofboththetransmitandreceivedescriptor
rings into CSRs for use by the PCnet-ISA+ controller
during subsequent operation.
■ The address of the actual message data buffer
in user or host memory
■ The length of the message buffer
■ Status information indicating the condition of
the buffer
When transmit and receive functions begin, the base
address of each ring is loaded into the current descriptor
address registers and the address of the next descriptor
entry in the transmit and receive rings is computed and
loaded into the next descriptor address registers.
Receive descriptor entries are similar (but not identical)
totransmitdescriptorentries. Botharecomposedoffour
registers, each 16 bits wide for a total of 8 bytes.
To permit the queuing and de-queuing of message buff-
ers, ownership of each buffer is allocated to either the
PCnet-ISA+ controller or the host. The OWN bit within
the descriptor status information, either TMD or RMD
(see section on TMD or RMD), is used for this purpose.
“Deadly Embrace” conditions are avoided by the owner-
ship mechanism. Only the owner is permitted to
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N
N
N
N
•
•
•
24-Bit Base Address
Pointer to
Initialization Block
RCV Descriptor
Ring
1st desc.
start
2nd desc.
start
CSR2
IADR[23:16]
CSR1
IADR[15:0]
RES
RMD0
RMD0
RMD3
RMD1
RMD2
Initialization
Block
MODE
PADR[15:0]
Data
Data
Data
Buffer
N
RCV
Buffers
Buffer
1
Buffer
2
PADR[31:16]
PADRF[47:32]
LADRF[15:0]
LADRF[31:16]
LADRF[47:32]
LADRF[63:48]
RDRA[15:0]
M
M
M
M
•
•
•
XMT Descriptor
RLEN
RES
TDRA[15:0]
RES
TDRA[23:16]
RDRA[23:16]
Ring
2nd desc.
start
1st desc.
start
TLEN
TMD0
TMD0
TMD3
TMD1
TMD2
Data
Buffer
1
Data
Buffer
2
Data
Buffer
M
XMT
Buffers
18183B-14
Initialization Block and Descriptor Rings
Polling
A typical polling operation consists of the following: The
PCnet-ISA+ controller will use the current receive de-
scriptor address stored internally to vector to the
appropriate Receive Descriptor Table Entry (RDTE). It
will then use the current transmit descriptor address
(stored internally) to vector to the appropriate Transmit
Descriptor Table Entry (TDTE). These accesses will be
made to RMD1 and RMD0 of the current RDTE and
When there is no channel activity and there is no pre- or
post-receive or transmit activity being performed by the
PCnet-ISA+ controller then the PCnet-ISA+ controller
will periodically poll the current receive and transmit de-
scriptor entries in order to ascertain their ownership. If
the DPOLL bit in CSR4 is set, then the transmit polling
function is disabled.
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TMD1 and TMD0 of the current TDTE at periodic polling
intervals. All information collected during polling activity
will be stored internally in the appropriate CSRs. (i.e.
CSR18–19, CSR40, CSR20–21, CSR42, CSR50,
CSR52). Unowned descriptor status will be internally
ignored.
poll time count register is never reset. Note that if a non-
default is desired, then a strict sequence of setting the
INIT bit in CSR0, waiting for the IDON bit in CSR0, then
writing to CSR47, and then setting STRT in CSR0 must
be observed, otherwise the default value will not be
overwritten. See the CSR47 section for details.
A typical receive poll occurs under the following
conditions:
Setting the TDMD bit of CSR0 will cause the microcode
controller to exit the poll counting code and immediately
perform a polling operation. If RDTE ownership has not
been previously established, then an RDTE poll will be
performed ahead of the TDTE poll.
1) PCnet-ISA+ controller does not possess ownership
of the current RDTE and
the poll time has elapsed and
RXON = 1,
Transmit Descriptor Table Entry (TDTE)
or
If, after a TDTE access, the PCnet-ISA+ controller finds
that the OWN bit of that TDTE is not set, then the
PCnet-ISA+ controller resumes the poll time count and
reexamines the same TDTE at the next expiration of the
poll time count.
2) PCnet-ISA+ controller does not possess ownership
of the next RDTE and
the poll time has elapsed and
RXON = 1,
If RXON = 0, the PCnet-ISA+ controller will never poll
RDTE locations.
If the OWN bit of the TDTE is set, but STP = 0, the
PCnet-ISA+ controller will immediately request the bus
in order to reset the OWN bit of this descriptor; this con-
dition would normally be found following a LCOL or
RETRY error that occurred in the middle of a transmit
packet chain of buffers. After resetting the OWN bit of
this descriptor, the PCnet-ISA+ controller will again im-
mediately request the bus in order to access the next
TDTE location in the ring.
IfRXON=1, thesystemshouldalwayshaveatleastone
RDTE available for the possibility of a receive event.
When there is only one RDTE, there is no polling for next
RDTE.
A typical transmit poll occurs under the following
conditions:
1) PCnet-ISA+ controller does not possess ownership
of the current TDTE and
If the OWN bit is set and the buffer length is 0, the OWN
bit will be reset. In the LANCE the buffer length of 0 is
interpreted as a 4096-byte buffer. It is acceptable to
have a 0 length buffer on transmit with STP = 1 or STP =
1 and ENP = 1. It is not acceptable to have 0 length
buffer with STP = 0 and ENP = 1.
DPOLL = 0 and
TXON = 1 and
the poll time has elapsed,
or
If the OWN bit is set and the start of packet (STP) bit is
set, then microcode control proceeds to a routine that
will enable transmit data transfers to the FIFO.
2) PCnet-ISA+ controller does not possess ownership
of the current TDTE and
DPOLL = 0 and
TXON = 1 and
a packet has just been received,
If the transmit buffers are data chained (ENP=0 in the
first buffer), then the PCnet-ISA+ controller will look
ahead to the next transmit descriptor after it has
performed at least one transmit data transfer from the
first buffer. More than one transmit data transfer may
possibly take place, depending upon the state of the
transmitter. The transmit descriptor lookahead reads
TMD0 first and TMD1 second. The contents of TMD0
and TMD1 will be stored in Next TX Descriptor Address
(CSR32), Next TX Byte Count (CSR66) and Next TX
Status (CSR67) regardless of the state of the OWN bit.
This transmit descriptor lookahead operation is per-
formed only once.
or
3) PCnet-ISA+ controller does not possess ownership
of the current TDTE and
DPOLL = 0 and
TXON = 1 and
a packet has just been transmitted.
The poll time interval is nominally defined as 32,768
crystal clock periods, or 1.6 ms. However, the poll time
register is controlled internally by microcode, so any
other microcode controlled operation will interrupt the
incrementing of the poll count register. For example,
when a receive packet is accepted by the PCnet-ISA+
controller, the device suspends execution of the poll-
If the PCnet-ISA+ controller does not own the next TDTE
(i.e. the second TDTE for this packet), then it will com-
plete transmission of the current buffer and then update
the status of the current (first) TDTE with the BUFF and
UFLO bits being set. This will cause the transmitter to be
disabled (CSR0, TXON=0). The PCnet-ISA+ controller
will have to be restarted to restore the transmit function.
The situation that matches this description implies that
the system has not been able to stay ahead of the
time-incrementing microcode so that
a receive
microcode routine may instead be executed. Poll-time-
incrementing code is resumed when the receive
operation has completely finished. Note, however, that
following the completion of any receive or transmit op-
eration, a poll operation will always be performed. The
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PCnet-ISA+ controller in the transmit descriptor ring and
therefore, the condition is treated as a fatal error. To
avoid this situation, the system should always set the
transmit chain descriptor own bits in reverse order.
operation poll avoids inserting poll time counts between
successive transmit packets.
Whenever the PCnet-ISA+ controller completes a trans-
mit packet (either with or without error) and writes the
status information to the current descriptor, then the
TINT bit of CSR0 is set to indicate the completion of a
transmission. Thiscausesaninterruptsignal iftheIENA
bit of CSR0 has been set and the TINTM bit of CSR3
is reset.
If the PCnet-ISA+ controller does own the second TDTE
in a chain, it will gradually empty the contents of the first
buffer (as the bytes are needed by the transmit opera-
tion), perform a single-cycle DMA transfer to update the
status (reset the OWN bit in TMD1) of the first descrip-
tor, and then it may perform one data DMA access on
the second buffer in the chain before executing another
lookahead operation. (i.e. a lookahead to the third
descriptor.)
Receive Descriptor Table Entry (RDTE)
If the PCnet-ISA+ controller does not own both the cur-
rent and the next Receive Descriptor Table Entry, then
the PCnet-ISA+ controller will continue to poll according
to the polling sequence described above. If the receive
descriptor ring length is 1, there is no next descriptor,
and no look ahead poll will take place.
The PCnet-ISA+ controller can queue up to two packets
in the transmit FIFO. Call them packet “X” and packet
“Y”, where “Y” is after “X”. Assume that packet “X” is
currently being transmitted. Because the PCnet-ISA+
controller can perform lookahead data transfer over an
ENP, it is possible for the PCnet-ISA+ controller to up-
date a TDTE in a buffer belonging to packet “Y” while
packet “X” is being transmitted if packet “Y” uses data
chaining. This operation will result in non-sequential
TDTE accesses as packet “X” completes transmission
and the PCnet-ISA+ controller writes out its status, since
packet “X”’s TDTE is before the TDTE accessed as part
of the lookahead data transfer from packet “Y”.
If a poll operation has revealed that the current and the
next RDTE belongs to the PCnet-ISA+ controller, then
additional poll accesses are not necessary. Future poll
operations will not include RDTE accesses as long as
the PCnet-ISA+ controller retains ownership to the cur-
rent and the next RDTE.
When receive activity is present on the channel, the
PCnet-ISA+ controller waits for the complete address of
the message to arrive. It then decides whether to accept
or reject the packet based on all active addressing
schemes. If the packet is accepted the PCnet-ISA+ con-
troller checks the current receive buffer status register
CRST (CSR40) to determine the ownership of the cur-
rent buffer.
This should not cause any problem for properly written
software which processes buffers in sequence, waiting
for ownership before proceeding.
If an error occurs in the transmission before all of the
bytes of the current buffer have been transferred, then
TMD2 and TMD1 of the current buffer will be written; in
that case, data transfers from the next buffer will not
commence. Instead, followingtheTMD2/TMD1update,
the PCnet-ISA+ controller will go to the next transmit
packet, if any, skipping over the rest of the packet which
experienced an error, including chained buffers.
If ownership is lacking, then the PCnet-ISA+ controller
will immediately perform a (last ditch) poll of the current
RDTE. If ownership is still denied, then the PCnet-ISA+
controller has no buffer in which to store the incoming
message. The MISS bit will be set in CSR0 and an inter-
rupt will be generated if IENA = 1 (CSR0) and MISSM =
0 (CSR3). Another poll of the current RDTE will not oc-
cur until the packet has finished.
This is done by returning to the polling microcode where
it will immediately access the next descriptor and find
theconditionOWN=1andSTP=0asdescribedearlier.
In that case, the PCnet-ISA+ controller will reset the own
bit for this descriptor and continue in like manner until a
descriptor with OWN=0 (no more transmit packets in the
ring) or OWN = 1 and STP = 1 (the first buffer of a new
packet) is reached.
If the PCnet-ISA+ controller sees that the last poll (either
a normal poll or the last-ditch effort described in the
aboveparagraph)ofthecurrentRDTEshowsvalidown-
ership, then it proceeds to a poll of the next RDTE.
Following this poll, and regardless of the outcome of this
poll, transfers of receive data from the FIFO may begin.
Attheendofanytransmitoperation, whethersuccessful
or with errors, and the completion of the descriptor up-
dates, the PCnet-ISA+ controller will always perform
another poll operation. As described earlier, this poll op-
eration will begin with a check of the current RDTE,
unless the PCnet-ISA+ controller already owns that de-
scriptor. Then the PCnet-ISA+ controller will proceed to
polling the next TDTE. If the transmit descriptor OWN bit
has a zero value, then the PCnet-ISA+ controller will re-
sume poll time count incrementation. If the transmit
descriptor OWN bit has a value of ONE, then the
PCnet-ISA+ controller will begin filling the FIFO with
transmit data and initiate a transmission. This end-of-
Regardless of ownership of the second receive descrip-
tor, the PCnet-ISA+ controller will continue to perform
receive data DMA transfers to the first buffer, using
burst-cycle DMA transfers. If the packet length exceeds
the length of the first buffer, and the PCnet-ISA+ control-
ler does not own the second buffer, ownership of the
current descriptor will be passed back to the system by
writing a zero to the OWN bit of RMD1 and status will be
written indicating buffer (BUFF = 1) and possibly over-
flow (OFLO = 1) errors.
If the packet length exceeds the length of the first (cur-
rent) buffer, and the PCnet-ISA+ controller does own the
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second (next) buffer, ownership will be passed back to
the system by writing a zero to the OWN bit of RMD1
when the first buffer is full. Receive data transfers to the
second buffer may occur before the PCnet-ISA+ control-
ler proceeds to look ahead to the ownership of the third
buffer. Such action will depend upon the state of the
FIFO when the status has been updated on the first de-
scriptor. In any case, lookahead will be performed to the
thirdbufferandtheinformationgatheredwillbestoredin
the chip, regardless of the state of the ownership bit. As
in the transmit flow, lookahead operations are per-
formed only once.
This activity continues until the PCnet-ISA+ controller
recognizes the completion of the packet (the last byte of
this receive message has been removed from the
FIFO). The PCnet-ISA+ controller will subsequently
update the current RDTE status with the end of packet
(ENP) indication set, write the message byte count
(MCNT) of the complete packet into RMD2 and over-
write the “current” entries in the CSRs with the “next”
entries.
APAD_XMT = 1 (bit 11 in CSR4), transmit messages
will be padded with sufficient bytes (containing 00h) to
ensure that the receiving station will observe an
information field (destination address, source address,
length/type, data and FCS) of 64-bytes.
When
ASTRP_RCV = 1 (bit 10 in CSR4), the receiver will auto-
matically strip pad bytes from the received message by
observing the value in the length field, and stripping ex-
cess bytes if this value is below the minimum data size
(46 bytes). Both features can be independently over-
ridden to allow illegally short (less than 64 bytes of
packet data) messages to be transmitted and/or re-
ceived. The use of these features reduce bus bandwidth
usage because the pad bytes are not transferred to or
from host memory.
Framing (frame boundary delimitation, frame
synchronization)
The MAC engine will autonomously handle the con-
struction of the transmit frame. Once the Transmit FIFO
has been filled to the predetermined threshold (set by
XMTSP in CSR80), and providing access to the channel
is currently permitted, the MAC engine will commence
the 7-byte preamble sequence (10101010b, where first
bit transmitted is a 1). The MAC engine will subse-
quently append the Start Frame Delimiter (SFD) byte
(10101011b) followed by the serialized data from the
Transmit FIFO. Once the data has been completed, the
MAC engine will append the FCS (most significant bit
first) which was computed on the entire data portion of
the message.
Media Access Control
The Media Access Control engine incorporates the es-
sential protocol requirements for operation of a
compliant Ethernet/802.3 node, and provides the inter-
face between the FIFO sub-system and the Manchester
Encoder/Decoder (MENDEC).
The MAC engine is fully compliant to Section 4 of ISO/
IEC8802-3(ANSI/IEEEStandard1990SecondEdition)
and ANSI/IEEE 802.3 (1985).
Note that the user is responsible for the correct ordering
and content in each of the fields in the frame, including
the destination address, source address, length/type
and packet data.
The MAC engine provides programmable enhanced
features designed to minimize host supervision and pre
or post-message processing. These features include
the ability to disable retries after a collision, dynamic
FCS generation on a packet-by-packet basis, and auto-
matic pad field insertion and deletion to enforce
minimum frame size attributes.
The receive section of the MAC engine will detect an in-
coming preamble sequence and lock to the encoded
clock. The internal MENDEC will decode the serial bit
stream and present this to the MAC engine. The MAC
will discard the first 8 bits of information before search-
ing for the SFD sequence. Once the SFD is detected, all
subsequent bits are treated as part of the frame. The
MAC engine will inspect the length field to ensure mini-
mum frame size, strip unnecessary pad characters (if
enabled), and pass the remaining bytes through the Re-
ceive FIFO to the host. If pad stripping is performed, the
MAC engine will also strip the received FCS bytes, al-
though the normal FCS computation and checking will
occur. Note that apart from pad stripping, the frame will
be passed unmodified to the host. If the length field has
a value of 46 or greater, the MAC engine will not attempt
to validate the length against the number of bytes con-
tained in the message.
The two primary attributes of the MAC engine are:
■ Transmit and receive message data encapsulation
— Framing (frame boundary delimitation, frame
synchronization)
— Addressing (source and destination address
handling)
— Error detection (physical medium transmission
errors)
■ Media access management
— Medium allocation (collision avoidance)
— Contention resolution (collision handling)
If the frame terminates or suffers a collision before
64 bytes of information (after SFD) have been received,
the MAC engine will automatically delete the frame from
the Receive FIFO, without host intervention.
Transmit And Receive Message Data
Encapsulation
The MAC engine provides minimum frame size enforce-
ment for transmit and receive packets. When
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Addressing (source and destination address
handling)
will ignore up to seven additional bits at the end of a
message (dribbling bits), which can occur under normal
network operating conditions. The reception of eight ad-
ditional bits will cause the MAC engine to de-serialize
the entire byte, and will result in the received message
and FCS being modified.
The first 6 bytes of information after SFD will be inter-
pretedasthedestinationaddressfield. TheMACengine
provides facilities for physical, logical, and broadcast
address reception. In addition, multiple physical ad-
dresses can be constructed (perfect address filtering)
using external logic in conjunction with the EADI
interface.
The PCnet-ISA+ controller can handle up to 7 dribbling
bits when a received packet terminates. During the re-
ception, the CRC is generated on every serial bit
(including the dribbling bits) coming from the cable, al-
though the internally saved CRC value is only updated
on the eighth bit (on each byte boundary). The framing
error is reported to the user as follows:
Error detection (physical medium transmission
errors).
The MAC engine provides several facilities which report
and recover from errors on the medium. In addition, the
network is protected from gross errors due to inability of
the host to keep pace with the MAC engine activity.
1. Ifthenumberofthedribblingbitsare1to7andthere
is no CRC error, then there is no Framing error
(FRAM = 0).
On completion of transmission, the following transmit
status is available in the appropriate TMD and CSR
areas:
2. If the number of the dribbling bits are less than 8 and
there is a CRC error, then there is also a Framing
error (FRAM = 1).
■ The exact number of transmission retry attempts
3. If the number of dribbling bits = 0, then there is no
Framing error. There may or may not be a CRC
(FCS) error.
(ONE, MORE, or RTRY).
■ Whether the MAC engine had to Defer (DEF) due
to channel activity.
Counters are provided to report the Receive Collision
Count and Runt Packet Count used for network statis-
tics and utilization calculations.
■ Loss of Carrier, indicating that there was an
interruption in the ability of the MAC engine to
monitor its own transmission. Repeated LCAR
errors indicate a potentially faulty transceiver or
network connection.
Note that if the MAC engine detects a received packet
which has a 00b pattern in the preamble (after the first
8 bits, which are ignored), the entire packet will be
ignored. The MAC engine will wait for the network to go
inactive before attempting to receive the next packet.
■ Late Collision (LCOL) indicates that the
transmission suffered a collision after the slot time.
This is indicative of a badly configured network.
Late collisions should not occur in a normal
operating network.
Media Access Management
The basic requirement for all stations on the network is
to provide fairness of channel allocation. The
802.3/Ethernetprotocoldefinesamediaaccessmecha-
nism which permits all stations to access the channel
with equality. Any node can attempt to contend for the
channel by waiting for a predetermined time (Inter
Packet Gap interval) after the last activity, before trans-
mitting on the medium. The channel is a multidrop
communications medium (with various topological con-
figurations permitted) which allows a single station to
transmit and all other stations to receive. If two nodes
simultaneously contend for the channel, their signals
will interact, causing loss of data (defined as a collision).
It is the responsibility of the MAC to attempt to avoid and
recover from a collision, to guarantee data integrity for
the end-to-end transmission to the receiving station.
■ Collision Error (CERR) indicates that the
transceiver did not respond with an SQE Test
message within the predetermined time after a
transmission completed. This may be due to a
failed transceiver, disconnected or faulty trans-
ceiver drop cable, or the fact the transceiver does
not support this feature (or the feature is disabled).
In addition to the reporting of network errors, the MAC
engine will also attempt to prevent the creation of any
network error due to the inability of the host to service
the MAC engine. During transmission, if the host fails to
keeptheTransmitFIFOfilledsufficiently, causinganun-
derflow, the MAC engine will guarantee the message is
either sent as a runt packet (which will be deleted by the
receiving station) or has an invalid FCS (which will also
cause the receiver to reject the message).
Medium allocation (collision avoidance)
The IEEE 802.3 Standard (ISO/IEC 8802-3 1990) re-
quires that the CSMA/CD MAC monitor the medium
traffic by looking for carrier activity. When carrier is de-
tected the medium is considered busy, and the MAC
should defer to the existing message.
The status of each receive message is available in the
appropriate RMD and CSR areas. FCS and Framing er-
rors (FRAM) are reported, although the received frame
is still passed to the host. The FRAM error will only be
reported if an FCS error is detected and there are a non-
integralnumberofbitsinthemessage. TheMACengine
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The IEEE 802.3 Standard also allows optional two part
deferral after a receive message.
During the time period immediately after a transmission
has been completed, the external transceiver (in the
case of a standard AUI connected device), should gen-
eratetheSQETestmessage(anominal10MHzburstof
5-15 bit times duration) on the CI± pair (within 0.6 µs –
1.6 µs after the transmission ceases). During the time
period in which the SQE Test message is expected the
PCnet-ISA+ controller will not respond to receive carrier
sense.
See ANSI/IEEE Std 802.3-1990 Edition, 4.2.3.2.1:
“Note: It is possible for the PLS carrier sense
indication to fail to be asserted during a collision
on the media. If the deference process simply
times the interpacket gap based on this indica-
tion it is possible for a short interFrame gap to
be generated, leading to a potential reception
failure of a subsequent frame. To enhance sys-
tem robustness the following optional
measures, as specified in 4.2.8, are recom-
mended when InterFrameSpacingPart1 is
other than zero:
See ANSI/IEEE Std 802.3-1990 Edition,
7.2.4.6 (1)):
“At the conclusion of the output function, the
DTE opens a time window during which it ex-
pects to see the signal_quality_error signal
asserted on the Control In circuit. The time win-
dow begins when the CARRIER_STATUS
becomes CARRIER_OFF. If execution of the
output function does not cause CARRIER_ON
to occur, no SQE test occurs in the DTE. The
duration of the window shall be at least 4.0 µs
but no more than 8.0 µs. During the time win-
dow the Carrier Sense Function is inhibited.”
(1) Upon completing a transmission, start timing
the interpacket gap, as soon as transmitting
and carrierSense are both false.
(2) When timing an interpacket gap following re-
ception, reset the interpacket gap timing if
carrier Sense becomes true during the first 2/3
oftheinterpacketgaptiminginterval. Duringthe
final 1/3 of the interval the timer shall not be re-
set to ensure fair access to the medium. An
initial period shorter than 2/3 of the interval is
permissible including zero.”
The PCnet-ISA+ controller implements a carrier sense
“blinding” period within 0 - 4.0 µs from de-assertion of
carrier sense after transmission. This effectively means
that when transmit two part deferral is enabled
(DXMT2PD is cleared) the IFS1 time is from 4 µs to 6 µs
after a transmission. However, since IPG shrinkage be-
low 4 µs will rarely be encountered on a correctly
configured network, and since the fragment size will be
larger than the 4 µs blinding window, then the IPG
counterwillberesetbyaworstcaseIPGshrinkage/frag-
ment scenario and the PCnet-ISA+ controller will defer
its transmission. In addition, the PCnet-ISA+ controller
will not restart the “blinding” period if carrier is detected
within the 4.0 µs – 6.0 µs IFS1 period, but will com-
mence timing of the entire IFS1 period.
The MAC engine implements the optional receive two
part deferral algorithm, with a first part inter-frame-spac-
ing time of 6.0 µs. The second part of the
inter-frame-spacing interval is therefore 3.6 µs.
The PCnet-ISA+ controller will perform the two-part
deferral algorithm as specified in Section 4.2.8 (Process
Deference). The Inter Packet Gap (IPG) timer will start
timing the 9.6 µs InterFrameSpacing after the receive
carrier is de-asserted. During the first part deferral
(InterFrameSpacingPart1 - IFS1) the PCnet-ISA+ con-
trollerwilldeferanypendingtransmitframeandrespond
to the receive message. The IPG counter will be reset to
zero continuously until the carrier de-asserts, at which
point the IPG counter will resume the 9.6 µs count once
again. Once the IFS1 period of 6.0 µs has elapsed, the
PCnet-ISA+ controller will begin timing the second part
deferral (InterFrameSpacingPart2 - IFS2) of 3.6 µs.
Once IFS1 has completed, and IFS2 has commenced,
the PCnet-ISA+ controller will not defer to a receive
packet if a transmit packet is pending. This means that
the PCnet-ISA+ controller will not attempt to receive the
receive packet, since it will start to transmit, and gener-
ate a collision at 9.6 µs. The PCnet-ISA+ controller will
guarantee to complete the preamble (64-bit) and jam
(32-bit) sequence before ceasing transmission and in-
voking the random backoff algorithm.
Contention resolution (collision handling)
Collision detection is performed and reported to the
MAC engine by the integrated Manchester Encoder/
Decoder (MENDEC).
If a collision is detected before the complete preamble/
SFD sequence has been transmitted, the MAC Engine
will complete the preamble/SFD before appending the
jam sequence. If a collision is detected after the pream-
ble/SFD has been completed, but prior to 512 bits being
transmitted, the MAC Engine will abort the transmis-
sion, and append the jam sequence immediately. The
jam sequence is a 32-bit all zeroes pattern.
The MAC Engine will attempt to transmit a frame a total
of 16 times (initial attempt plus 15 retries) due to normal
collisions (those within the slot time). Detection of colli-
sion will cause the transmission to be re-scheduled,
dependent on the backoff time that the MAC Engine
computes. If a single retry was required, the ONE bit will
be set in the Transmit Frame Status (TMD1 in the Trans-
mit Descriptor Ring). If more than one retry was
In addition, transmit two part deferral is implemented as
an option which can be disabled using the DXMT2PD bit
(CSR3). Two-part deferral after transmission is useful
for ensuring that severe IPG shrinkage cannot occur in
specific circumstances, causing a transmit message to
follow a receive message so closely as to make them
indistinguishable.
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required, the MORE bit will be set. If all 16 attempts ex-
perienced collisions, the RTRY bit (in TMD2) will be set
(ONE and MORE will be clear), and the transmit mes-
sage will be flushed from the FIFO. If retries have been
disabled by setting the DRTY bit in the MODE register
(CSR15), the MAC Engine will abandon transmission of
the frame on detection of the first collision. In this case,
only the RTRY bit will be set and the transmit message
will be flushed from the FIFO.
External Crystal Characteristics
When using a crystal to drive the oscillator, the crystal
specification shown in the specification table may be
used to ensure less than ±0.5 ns jitter at DO±.
External Crystal Characteristics
Parameter
Min
Nom Max
Unit
MHz
PPM
PPM
pF
1.Parallel Resonant
Frequency
20
If a collision is detected after 512 bit times have been
transmitted, the collision is termed a late collision. The
MAC Engine will abort the transmission, append the jam
sequence, and set the LCOL bit. No retry attempt will be
scheduled on detection of a late collision, and the FIFO
will be flushed.
2.Resonant Frequency Error
(CL = 20 pF)
–50
–40
+50
+40
20
3.Change in Resonant Frequency
With Respect To Temperature
(0° – 70° C; CL = 20 pF)*
4.Crystal Capacitance
The IEEE 802.3 Standard requires use of a “truncated
binary exponential backoff” algorithm which provides a
controlled pseudo-random mechanism to enforce the
collision backoff interval, before re-transmission is
attempted.
5.Motional Crystal
Capacitance (C1)
0.022
25
pF
Ω
6.Series Resistance
7.Shunt Capacitance
8.Drive Level
7
pF
TBD
mW
See ANSI/IEEE Std 802.3-1990 Edition, 4.2.3.2.5:
* Requires trimming crystal spec; no trim is 50 ppm total
“At the end of enforcing a collision (jamming),
the CSMA/CD sublayer delays before attempt-
ing to re-transmit the frame. The delay is an
integer multiple of slotTime. The number of slot
times to delay before the nth re-transmission at-
tempt is chosen as a uniformly distributed
random integer r in the range:
External Clock Drive Characteristics
When driving the oscillator from an external clock
source, XTAL2 must be left floating (unconnected). An
external clock having the following characteristics must
be used to ensure less than ±0.5 ns jitter at DO±.
0 ≤ r < 2k, where k = min (n,10).”
Clock Frequency:
20 MHz ±0.01%
The PCnet-ISA+ controller provides an alternative algo-
rithm, which suspends the counting of the slot time/IPG
during the time that receive carrier sense is detected.
This algorithm aids in networks where large numbers of
nodes are present, and numerous nodes can be in
collision. The algorithm effectively accelerates the
increase in the backoff time in busy networks, and al-
lows nodes not involved in the collision to access the
channel while the colliding nodes await a reduction in
channel activity. Once channel activity is reduced, the
nodes resolving the collision time out their slot time
counters as normal.
Rise/Fall Time (tR/tF):
< 6 ns from 0.5 V
to VDD–0.5
XTAL1 HIGH/LOW Time
(tHIGH/tLOW):
40 – 60%
duty cycle
XTAL1 Falling Edge to
Falling Edge Jitter:
< ±0.2 ns at
2.5 V input (VDD/2)
MENDEC Transmit Path
The transmit section encodes separate clock and NRZ
data input signals into a standard Manchester encoded
serial bit stream. The transmit outputs (DO±) are de-
signed to operate into terminated transmission lines.
When operating into a 78 Ω terminated transmission
line, the transmit signaling meets the required output
levels and skew for Cheapernet, Ethernet, and
IEEE-802.3.
Manchester Encoder/Decoder
(MENDEC)
The integrated Manchester Encoder/Decoder provides
the PLS (Physical Layer Signaling) functions required
for a fully compliant IEEE 802.3 station. The MENDEC
providestheencodingfunctionfordatatobetransmitted
on the network using the high accuracy on-board oscil-
lator, driven by either the crystal oscillator or an external
CMOS-level compatible clock. The MENDEC also pro-
vides the decoding function from data received from the
network. The MENDEC contains a Power On Reset
(POR) circuit, which ensures that all analog portions of
the PCnet-ISA+ controller are forced into their correct
state during power-up, and prevents erroneous data
transmission and/or reception during this time.
Transmitter Timing and Operation
A 20 MHz fundamental-mode crystal oscillator provides
the basic timing reference for the MENDEC portion of
the PCnet-ISA+ controller. The crystal input is divided by
two to create the internal transmit clock reference. Both
clocks are fed into the Manchester Encoder to generate
the transitions in the encoded data stream. The internal
transmit clock is used by the MENDEC to internally syn-
chronize the Internal Transmit Data (ITXDAT) from the
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controller and Internal Transmit Enable (ITXEN). The in-
ternal transmit clock is also used as a stable bit-rate
clock by the receive section of the MENDEC and con-
troller.
The Carrier Detection circuitry detects the presence of
an incoming data packet by discerning and rejecting
noise from expected Manchester data, and controls the
stop and start of the phase-lock loop during clock acqui-
sition. Clock acquisition requires a valid Manchester bit
pattern of 1010b to lock onto the incoming message.
The oscillator requires an external 0.005% crystal, or an
external 0.01% CMOS-level input as a reference. The
accuracy requirements, if an external crystal is used,
are tighter because allowance for the on-chip oscillator
must be made to deliver a final accuracy of 0.01%.
When input amplitude and pulse width conditions are
met at DI±, a clock acquisition cycle is initiated.
Clock Acquisition
Transmissionisenabledbythecontroller. Aslongasthe
ITXEN request remains active, the serial output of the
controller will be Manchester encoded and appear at
DO±. When the internal request is dropped by the con-
troller, the differential transmit outputs go to one of two
idle states, dependent on TSEL in the Mode Register
(CSR15, bit 9):
When there is no activity at DI± (receiver is idle), the re-
ceive oscillator is phase-locked to STDCLK. The first
negative clock transition (bit cell center of first valid
Manchester “0”) after clock acquisition begins interrupts
the receive oscillator. The oscillator is then restarted at
the second Manchester “0” (bit time 4) and is phase-
locked to it. As a result, the MENDEC acquires the clock
from the incoming Manchester bit pattern in 4 bit times
with a “1010” Manchester bit pattern.
TSEL LOW: The idle state of DO± yields “zero”
differential to operate transformer-
coupled loads.
The internal receiver clock, IRXCLK, and the internal re-
ceived data, IRXDAT, are enabled 1/4 bit time after
clock acquisition in bit cell 5. IRXDAT is at a HIGH state
when the receiver is idle (no IRXCLK). IRXDAT how-
ever, is undefined when clock is acquired and may
remain HIGH or change to LOW state whenever
IRXCLK is enabled. At 1/4 bit time through bit cell 5, the
controller portion of the PCnet-ISA+ controller sees the
firstIRXCLKtransition. Thisalsostrobesintheincoming
fifth bit to the MENDEC as Manchester “1”. IRXDAT
maymakeatransitionaftertheIRXCLKrisingedgeinbit
cell 5, but its state is still undefined. The Manchester “1”
at bit 5 is clocked to IRXDAT output at 1/4 bit time in bit
cell 6.
TSEL HIGH: In this idle state, DO+ is positive
with respect to DO– (logical HIGH).
Receive Path
The principal functions of the receiver are to signal the
PCnet-ISA+ controller that there is information on the re-
ceive pair, and to separate the incoming Manchester
encoded data stream into clock and NRZ data.
The receiver section (see Receiver Block Diagram) con-
sists of two parallel paths. The receive data path is a
zerothreshold, widebandwidthlinereceiver. Thecarrier
path is an offset threshold bandpass detecting line re-
ceiver. Both receivers share common bias networks to
allow operation over a wide input common mode range.
PLL Tracking
After clock acquisition, the phase-locked clock is com-
pared to the incoming transition at the bit cell center
(BCC) and the resulting phase error is applied to a cor-
rection circuit. This circuit ensures that the
phase-locked clock remains locked on the received sig-
nal. Individual bit cell phase corrections of the Voltage
Controlled Oscillator (VCO) are limited to 10% of the
phase difference between BCC and phase-
locked clock.
Input Signal Conditioning
Transient noise pulses at the input data stream are re-
jected by the Noise Rejection Filter. Pulse width
rejection is proportional to transmit data rate which is
fixed at 10 MHz for Ethernet systems but which could be
different for proprietary networks. DC inputs more nega-
tive than minus 100 mV are also suppressed.
IRXDAT*
Manchester
Data
Receiver
DI±
Decoder
IRXCLK*
Noise
Reject
Filter
Carrier
Detect
Circuit
IRXCRS*
18183B-15
*Internal signal
Receiver Block Diagram
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Carrier Tracking and End of Message
Collision Detection
The carrier detection circuit monitors the DI± inputs after
IRXCRS is asserted for an end of message. IRXCRS
de-asserts 1 to 2 bit times after the last positive transi-
tion on the incoming message. This initiates the end of
reception cycle. The time delay from the last rising edge
of the message to IRXCRS deassert allows the last bit to
be strobed by IRXCLK and transferred to the controller
section, but prevents any extra bit(s) at the end of mes-
sage. When IRXCRS de-asserts an IRXCRS hold off
timer inhibits IRXCRS assertion for at least 2 bit times.
A MAU detects the collision condition on the network
and generates a differential signal at the CI± inputs. This
collision signal passes through an input stage which de-
tectssignallevelsandpulseduration. Whenthesignalis
detected by the MENDEC it sets the internal collision
signal, ICLSN, HIGH. The condition continues for ap-
proximately 1.5 bit times after the last LOW-to-HIGH
transition on CI±.
Jitter Tolerance Definition
The MENDEC utilizes a clock capture circuit to align its
internal data strobe with an incoming bit stream. The
clock acquisition circuitry requires four valid bits with the
values 1010b. Clock is phase-locked to the negative
transition at the bit cell center of the second “0” in the
pattern.
Data Decoding
The data receiver is a comparator with clocked output to
minimize noise sensitivity to the DI± inputs. Input error is
less than ± 35 mV to minimize sensitivity to input rise
andfalltime. IRXCLKstrobesthedatareceiveroutputat
1/4 bit time to determine the value of the Manchester bit,
and clocks the data out on IRXDAT on the following
IRXCLK. The data receiver also generates the signal
used for phase detector comparison to the internal
MENDEC voltage controlled oscillator (VCO).
Since data is strobed at 1/4 bit time, Manchester transi-
tions which shift from their nominal placement through
1/4 bit time will result in improperly decoded data. With
this as the criteria for an error, a definition of “Jitter Han-
dling” is:
Differential Input Terminations
The peak deviation approaching or crossing 1/4
bit cell position from nominal input transition, for
which the MENDEC section will properly de-
code data.
The differential input for the Manchester data (DI±)
should be externally terminated by two 40.2 Ω ±1% re-
sistors and one optional common-mode bypass
capacitor, as shown in the Differential Input Termination
diagram below. The differential input impedance, ZIDF,
and the common-mode input impedance, ZICM, are
specified so that the Ethernet specification for cable ter-
mination impedance is met using standard 1% resistor
terminators. If SIP devices are used, 39 Ω is the nearest
usable equivalent value. The CI± differential inputs are
terminated in exactly the same way as the DI± pair.
Attachment Unit Interface (AUI)
The AUI is the PLS (Physical Layer Signaling) to PMA
(Physical Medium Attachment) interface which con-
nects the DTE to a MAU. The differential interface
provided by the PCnet-ISA+ controller is fully compliant
with Section 7 of ISO 8802-3 (ANSI/IEEE 802.3).
After the PCnet-ISA+ controller initiates a transmission,
it will expect to see data “looped-back” on the DI± pair
(when the AUI port is selected). This will internally
generate a “carrier sense”, indicating that the integrity of
the data path to and from the MAU is intact, and that the
MAU is operating correctly. This “carrier sense” signal
must be asserted within sometime before end of trans-
mission. If “carrier sense” does not become active in
response to the data transmission, or becomes inactive
before the end of transmission, the loss of carrier
(LCAR) error bit will be set in the Transmit Descriptor
Ring (TMD3, bit 11) after the packet has been
transmitted.
AUI Isolation
Transformer
DI+
+
PCnet-ISA
DI-
40.2 Ω
40.2 Ω
0.01 µF
to 0.1 µF
18183B-16
Twisted Pair Transceiver (T-MAU)
Differential Input Termination
The T-MAU implements the Medium Attachment Unit
(MAU) functions for the Twisted Pair Medium, as speci-
fied by the supplement to IEEE 802.3 standard (Type
10BASE-T). The T-MAU provides twisted pair driver
and receiver circuits, including on-board transmit digital
predistortion and receiver squelch, and a number of ad-
ditional features including Link Status indication,
Automatic Twisted Pair Receive Polarity Detection/
Correction and Indication, Receive Carrier Sense,
Transmit Active and Collision Present indication.
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Twisted Pair Transmit Function
until valid data or greater than 5 consecutive link pulses
appear on the RXD± pair. During Link Fail, the Link
Status (LNKST indicated by LED0) signal is inactive.
When the link is identified as functional, the LNKST sig-
nal is asserted, and LED0 output will be activated.
The differential driver circuitry in the TXD± and TXP±
pins provides the necessary electrical driving capability
and the pre-distortion control for transmitting signals
over maximum length Twisted Pair cable, as specified
by the 10BASE-T supplement to the IEEE 802.3 Stan-
dard. The transmit function for data output meets the
propagation delays and jitter specified by the standard.
In order to inter-operate with systems which do not im-
plement Link Test, this function can be disabled by
setting the DLNKTST bit. With Link Test disabled, the
Data Driver, Receiver and Loopback functions as well
as Collision Detection remain enabled irrespective of
the presence or absence of data or link pulses on the
RXD± pair. Link Test pulses continue to be sent regard-
less of the state of the DLNKTST bit.
Twisted Pair Receive Function
The receiver complies with the receiver specifications of
the IEEE 802.3 10BASE-T Standard, including noise
immunity and received signal rejection criteria (‘Smart
Squelch’). Signals meeting these criteria appearing at
the RXD± differential input pair are routed to the MEN-
DEC. The receiver function meets the propagation
delaysandjitterrequirementsspecifiedbythestandard.
The receiver squelch level drops to half its threshold
value after unsquelch to allow reception of minimum
amplitude signals and to offset carrier fade in the event
of worst case signal attenuation conditions.
Polarity Detection and Reversal
The T-MAU receive function includes the ability to invert
the polarity of the signals appearing at the RXD± pair if
the polarity of the received signal is reversed (such as in
thecaseofawiringerror). Thisfeatureallowsdatapack-
ets received from a reverse wired RXD± input pair to be
corrected in the T-MAU prior to transfer to the
MENDEC. The polarity detection function is activated
following reset or Link Fail, and will reverse the receive
polarity based on both the polarity of any previous link
beat pulses and the polarity of subsequent packets with
a valid End Transmit Delimiter (ETD).
Note that the 10BASE-T Standard defines the receive
input amplitude at the external Media Dependent Inter-
face (MDI). Filter and transformer loss are not specified.
The T-MAU receiver squelch levels are designed to ac-
count for a 1 dB insertion loss at 10 MHz for the type of
receive filters and transformers usually used.
When in the Link Fail state, the T-MAU will recognize
link beat pulses of either positive or negative polarity.
Exit from the Link Fail state occurs at the reception of 5–
6 consecutive link beat pulses of identical polarity. On
entry to the Link Pass state, the polarity of the last 5 link
beat pulses is used to determine the initial receive polar-
ity configuration and the receiver is reconfigured to
subsequently recognize only link beat pulses of the pre-
viously recognized polarity.
Normal 10BASE-T compatible receive thresholds are
invoked when the LRT bit (CSR15, bit 9) is LOW. When
the LRT bit is set, the Low Receive Threshold option is
invoked, and the sensitivity of the T-MAU receiver is in-
creased. Increasing T-MAU sensitivity allows the use of
lines longer than the 100 m target distance of standard
10BASE-T(assumingtypical24AWGcable). Increased
receiver sensitivity compensates for the increased sig-
nal attenuation caused by the additional cable distance.
Positive link beat pulses are defined as transmitted sig-
nal with a positive amplitude greater than 585 mV with a
pulse width of 60 ns–200 ns. This positive excursion
may be followed by a negative excursion. This definition
is consistent with the expected received signal at a cor-
rectly wired receiver, when a link beat pulse, which fits
thetemplateofFigure14-12ofthe10BASE-TStandard,
is generated at a transmitter and passed through 100 m
of twisted pair cable.
However, making the receiver more sensitive means
that it is also more susceptible to extraneous noise, pri-
marily caused by coupling from co-resident services
(crosstalk). For this reason, end users may wish to in-
voke the Low Receive Threshold option on 4-pair cable
only. Multi-pair cables within the same outer sheath
have lower crosstalk attenuation, and may allow noise
emitted from adjacent pairs to couple into the receive
pair, and be of sufficient amplitude to falsely unsquelch
the T-MAU.
Negative link beat pulses are defined as transmitted sig-
nals with a negative amplitude greater than 585 mV with
a pulse width of 60 ns–200 ns. This negative excursion
may be followed by a positive excursion. This definition
is consistent with the expected received signal at a re-
verse wired receiver, when a link beat pulse which fits
the template of Figure 14-12 in the 10BASE-T Standard
is generated at a transmitter and passed through 100 m
of twisted pair cable.
Link Test Function
The link test function is implemented as specified by
10BASE-T standard. During periods of transmit pair in-
activity, ’Link beat pulses’ will be periodically sent over
the twisted pair medium to constantly monitor medium
integrity.
When the link test function is enabled (DLNKTST bit in
CSR15 is cleared), the absence of link beat pulses and
receivedataontheRXD± pairwillcausetheTMAUtogo
into the Link Fail state. In the Link Fail state, data trans-
mission, data reception, data loopback and the collision
detection functions are disabled and remain disabled
The polarity detection/correction algorithm will remain
“armed” until two consecutive packets with valid ETD of
identical polarity are detected. When “armed,” the re-
ceiver is capable of changing the initial or previous
polarity configuration according to the detected ETD
polarity.
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On receipt of the first packet with valid ETD following re-
set or link fail, the T-MAU will use the inferred polarity
information to configure its RXD± input, regardless of its
previous state. On receipt of a second packet with a
valid ETD with correct polarity, the detection/correction
algorithm will “lock-in” the received polarity. If the sec-
ond (or subsequent) packet is not detected as
confirming the previous polarity decision, the most re-
cently detected ETD polarity will be used as the default.
Note that packets with invalid ETD have no effect on up-
dating the previous polarity decision. Once two
consecutive packets with valid ETD have been re-
ceived, the T-MAU will lock the correction algorithm until
either a Link Fail condition occurs or RESET is asserted.
before the T-MAU deasserts COL and re-enables the
transmit circuitry.
Power Down
The T-MAU circuitry can be made to go into low power
mode. This feature is useful in battery powered or low
duty cycle systems. The T-MAU will go into power down
mode when RESET is active, coma mode is active, or
the T-MAU is not selected. Refer to the Power Down
Mode section for a description of the various power
down modes.
Any of the three conditions listed above resets the inter-
nal logic of the T-MAU and places the device into power
down mode. In this mode, the Twisted Pair driver pins
(TXD±,TXP±) are asserted LOW, and the internal T-
MAU status signals (LNKST, RCVPOL, XMT, RCV and
COLLISION) are inactive.
During polarity reversal, an internal POL signal will be
active. During normal polarity conditions, this internal
POL signal is inactive. The state of this signal can be
read by software and/or displayed by LED when en-
abled by the LED control bits in the ISA Bus
Configuration Registers (ISACSR5, 6, 7).
Once the SLEEP pin is deasserted, the T-MAU will be
forced into the Link Fail state. The T-MAU will move to
the Link Pass state only after 5–6 link beat pulses and/or
a single received message is detected on the RXD±
pair.
Twisted Pair Interface Status
Three internal signals (XMT, RCV and COL) indicate
whether the T-MAU is transmitting, receiving, or in a col-
lision state. These signals are internal signals and the
behavior of the LED outputs depends on how the LED
output circuitry is programmed.
In Snooze mode, the T-MAU receive circuitry will re-
main enabled even while the SLEEPpin is driven LOW.
The T-MAU circuitry will always go into power down
mode if RESET is asserted, coma is enabled, or the T-
MAU is not selected.
The T-MAU will power up in the Link Fail state and the
normal algorithm will apply to allow it to enter the Link
Pass state. In the Link Pass state, transmit or receive
activity will be indicated by assertion of RCV signal go-
ing active. If T-MAU is selected using the PORTSEL bits
in CSR15, when moving from AUI to T-MAU selection,
the T-MAU will be forced into the Link Fail state.
EADI (EXTERNAL ADDRESS DETECTION
INTERFACE)
Thisinterfaceisprovidedtoallowexternaladdressfilter-
ing. It is selected by setting the EADISEL bit in
ISACSR2. This feature is typically utilized for terminal
servers, bridges and/or router type products. The use of
external logic is required to capture the serial bit stream
from the PCnet-ISA+ controller, compare it with a table
of stored addresses or identifiers, and perform the de-
sired function.
In the Link Fail state, XMT, RCV and COL are inactive.
Collision Detect Function
Activity on both twisted pair signals RXD± and TXD±
constitutes a collision, thereby causing the COL signal
to be asserted. (COL is used by the LED control circuits)
COL will remain asserted until one of the two colliding
signals changes from active to idle. COL stays active for
2 bit times at the end of a collision.
The EADI interface operates directly from the NRZ de-
coded data and clock recovered by the Manchester
decoder or input to the GPSI, allowing the external ad-
dress detection to be performed in parallel with frame
reception and address comparison in the MAC Station
Address Detection (SAD) block.
Signal Quality Error (SQE) Test
(Heartbeat) Function
The SQE function is disabled when the 10BASE-T port
is selected and in Link Fail state.
SRDCLK is provided to allow clocking of the receive bit
stream into the external address detection logic.
SRDCLK runs only during frame reception activity.
Once a received frame commences and data and clock
are available, the EADI logic will monitor the alternating
(“1,0”) preamble pattern until the two ones of the Start
Frame Delimiter (“1,0,1,0,1,0,1,1”) are detected, at
which point the SF/BD output will be driven HIGH.
Jabber Function
The Jabber function inhibits the twisted pair transmit
function of the T-MAU if theTXD± circuit is active for an
excessive period (20 ms–150 ms). This prevents any
one node from disrupting the network due to a ‘stuck-on’
or faulty transmitter. If this maximum transmit time is ex-
ceeded, the T-MAU transmitter circuitry is disabled, the
JAB bit is set (CSR4, bit 1), and the COL signal as-
serted. Once the transmit data stream to the T-MAU is
removed, an “unjab” time of 250 ms– 750 ms will elapse
After SF/BD is asserted the serial data from SRD should
be de-serialized and sent to a content addressable
memory (CAM) or other address detection device.
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To allow simple serial to parallel conversion, SF/BD is
provided as a strobe and/or marker to indicate the de-
lineation of bytes, subsequent to the SFD. This provides
a mechanism to allow not only capture and/or decoding
of the physical or logical (group) address, it also facili-
tates the capture of header information to determine
protocol and or inter-networking information. The EAR
pin is driven LOW by the external address comparison
logic to reject the frame.
address, 2 bytes for length, no data, 4 bytes for FCS)
after the last bit of the destination address is available.
EAR must have a pulse width of at least 200 ns.
Note that setting the PROM bit (CSR15, bit 15) will
cause all receive frames to be received, regardless of
the state of the EAR input.
If the DRCUPA bit (CSR15.B) is set and the logical
address (LADRF) is set to zero, only frames which are
not rejected by EAR will be received.
If an internal address match is detected by comparison
with either the Physical or Logical Address field, the
frame will be accepted regardless of the condition of
EAR. Incoming frames which do not pass the internal
address comparison will continue to be received. This
allows approximately 58 byte times after the last desti-
nation address bit is available to generate the EAR
signal, assuming the device is not configured to accept
runt packets. EAR will be ignored after 64 byte times af-
ter the SFD, and the frame will be accepted if EAR has
not been asserted before this time. If Runt Packet Ac-
cept is configured, the EAR signal must be generated
priortothereceivemessagecompletion, whichcouldbe
as short as 12 byte times (assuming 6 bytes for source
The EADI interface will operate as long as the STRT bit
in CSR0 is set, even if the receiver and/or transmitter
are disabled by software (DTX and DRX bits in CSR15
set). This situation is useful as a power down mode in
that the PCnet-ISA+ controller will not perform any DMA
operations; this saves power by not utilizing the ISA bus
driver circuits. However, external circuitry could still re-
spond to specific frames on the network to facilitate
remote node control.
The table below summarizes the operation of the EADI
features.
Internal/External Address Recognition Capabilities
PROM
EAR
Required Timing
No timing requirements
Received Messages
All Received Frames
1
0
0
X
1
0
No timing requirements
All Received Frames
Low for 200 ns within 512 bits after SFD
Physical/Logical Matches
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To invoke the GPSI signals, follow the procedure below:
General Purpose Serial Interface (GPSI)
The PCnet-ISA+ controller contains a General Purpose
Serial Interface (GPSI) designed for testing the digital
portions of the chip. The MENDEC, AUI, and twisted
pair interface are by-passed once the device is set up in
the special “test mode” for accessing the GPSI func-
tions. Although this access is intended only for testing
the device, some users may find the non-encoded data
functions useful in some special applications. Note,
however, that the GPSI functions can be accessed only
when the PCnet-ISA+ devices operate as a bus master.
1. After reset or I/O read of Reset Address, write 10b
to PORTSEL bits in CSR15.
2. Set the ENTST bit in CSR4
3. Set the GPSIEN bit in CSR124 (see note below)
(The pins LA17–LA23 will change function after the
completion of the above three steps.)
4. Clear the ENTST bit in CSR4
5. Clear Media Select bits in ISACSR2
The PCnet-ISA+ GPSI signals are consistent with the
LANCEdigitalserialinterface. SincetheGPSI functions
can be accessed only through a special test mode, ex-
pect some loss of functionality to the device when the
GPSI is invoked. The AUI and 10BASE-T analog inter-
faces are disabled along with the internal MENDEC
logic. TheLA(unlatchedaddress)pinsareremovedand
become the GPSI signals, therefore, only 20 bits of ad-
dress space is available. The table below shows the
GPSI pin configuration:
6. Define the PORTSEL bits in the MODE register
(CSR15) to be 10b to define GPSI port. The
MODE register image is in the initialization block.
Note: LA pins will be tristated before writing to GPSIEN
bit. After writing to GPSIEN, LA[17–21] will be inputs,
LA[22–23] will be outputs.
GPSI Pin Configurations
LANCE
PCnet-ISA+
GPSI
Function
GPSI
I/O Type
PCnet-ISA+
Pin Number
PCnet-ISA+
Normal Pin Function
GPSI Pin GPSI Pin
Receive Data
I
I
RX
RXDAT
SRDCLK
RXCRS
CLSN
5
6
LA17
LA18
LA19
LA20
LA21
LA22
LA23
Receive Clock
Receive Carrier Sense
Collision
RCLK
RENA
CLSN
TCLK
TENA
TX
I
7
I
9
Transmit Clock
Transmit Enable
Transmit Data
Note:
I
STDCLK
TXEN
10
11
12
O
O
TXDAT
The GPSI Function is available only in the Bus Master Mode of operation.
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All unused instruction codes are reserved. See the table
below for a summary of supported instructions.
IEEE 1149.1 Test Access Port Interface
AnIEEE1149.1compatibleboundaryscanTestAccess
Port is provided for board-level continuity test and diag-
nostics. All digital input, output, and input/output pins
are tested. Analog pins, including the AUI differential
driver (DO±) and receivers (DI±, CI±), and the crystal in-
put(XTAL1/XTAL2)pins, aretested. TheT-MAUdrivers
TXD±, TXP±, and receiver RXD± are also tested.
Instruction Register and Decoding Logic
After hardware or software RESET, the IDCODE in-
struction is always invoked. The decoding logic gives
signals to control the data flow in the DATA registers ac-
cording to the current instruction.
The following is a brief summary of the IEEE 1149.1
compatible test functions implemented in the
PCnet-ISA+ controller.
Boundary Scan Register (BSR)
Each BSR cell has two stages. A flip-flop and a latch are
used in the SERIAL SHIFT STAGE and the PARALLEL
OUTPUT STAGE, respectively.
Boundary Scan Circuit
There are four possible operational modes in the BSR
cell:
The boundary scan test circuit requires four extra pins
(TCK, TMS, TDI and TDO ), defined as the Test Access
Port (TAP). It includes a finite state machine (FSM), an
instruction register, a data register array, and a
power-on reset circuit. Internal pull-up resistors are pro-
videdfortheTDI, TCK, andTMSpins. TheTCKpinmust
not be left unconnected. The boundary scan circuit re-
mains active during sleep.
1
2
3
4
Capture
Shift
Update
System Function
Other Data Registers
TAP FSM
(1) BYPASS REG (1 BIT)
The TAP engine is a 16-state FSM, driven by the Test
Clock (TCK) and the Test Mode Select (TMS) pins. This
FSM is in its reset state at power-up or RESET. An inde-
pendent power-on reset circuit is provided to ensure the
FSM is in the TEST_LOGIC_RESET state at power-up.
(2) DEV ID REG (32 bits)
Bits 31–28:
Bits 27–12:
Bits 11–1:
Version
Part number (2260)
Manufacturer ID. The 11 bit
manufacturer ID code for AMD is
00000000001 according to JEDEC
Publication 106-A.
Supported Instructions
In addition to the minimum IEEE 1149.1 requirements
(BYPASS, EXTEST and SAMPLE instructions), three
additional instructions (IDCODE, TRIBYP and SET-
BYP) are provided to further ease board-level testing.
Bit 0:
Always a logic 1
IEEE 1149.1 Supported Instruction Summary
Selected
Instruction
Name
Instruction
Code
Description
Data Reg
Mode
Test
EXTEST
IDCODE
SAMPLE
TRIBYP
SETBYP
BYPASS
External Test
BSR
0000
0001
0010
0011
0100
1111
ID Code Inspection
Sample Boundary
Force Tristate
ID REG
BSR
Normal
Normal
Normal
Test
Bypass
Bypass
Bypass
Control Boundary to 1/0
Bypass Scan
Normal
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separate 8-bit hardware bus cycles. The motherboard
Power Saving Modes
accesses the low byte before the high byte and the
PCnet-ISA+ controller has circuitry to specifically sup-
port this type of access.
The PCnet-ISA+ controller supports two hardware
power-savings modes. Both are entered by asserting
the SLEEP pin LOW.
The reset register causes a reset when read. Any value
will be accepted and the cycle may be 8 or 16 bits wide.
Writes are ignored.
In coma mode, the PCnet-ISA+ controller will go into
deep sleep with no support to automatically wake itself
up. Sleep mode is enabled when the AWAKE bit in
ISACSR2 is reset. This mode is the default power down
mode.
All PCnet-ISA+ controller register accesses should be
coded as 16-bit operations.
In Snooze mode, enabled by setting the AWAKE bit in
ISACSR2 and driving the SLEEP pin LOW, the T-MAU
receive circuitry will remain enabled even while the
SLEEP pin is driven LOW. The LED0 output will also
continue to function, indicating a good 10BASE-T link if
there are link beat pulses or valid frames present. This
LED0 pin can be used to drive a LED and/or external
hardware that directly controls the SLEEP pin of the
PCnet-ISA+ controller. This configuration effectively
wakes the system when there is any activity on the
10BASE-T link.
*Note that the RAP is cleared on Reset.
IEEE Address Access
The address PROM may be an external memory device
that contains the node’s unique physical Ethernet ad-
dress and any other data stored by the board
manufacturer. The software accesses must be 16-bit.
This information may be stored in the EEPROM.
Boot PROM Access
The boot PROM is an external memory resource lo-
cated by the address selected by the EEPROM or the
BPAMinputinsharedmemorymode. Itmaybesoftware
accessed as an 8- or 16-bit resource but the latter is rec-
ommended for best performance.
Access Operations (Software)
We begin by describing how byte and word data are ad-
dressed on the ISA bus, including conversion cycles
where 16-bit accesses are turned into 8-bit accesses
because the resource accessed did not support 16-bit
operations. Then we describe how registers and other
resources are accessed. This section is for the device
programmer, while the next section (bus cycles) is for
the hardware designer.
Static RAM Access
The static RAM is only present in the shared memory
mode. It is located at the address selected by the SMAM
input. It may be accessed as an 8- or 16-bit resource but
the latter is recommended for best performance.
I/O Resources
Bus Cycles (Hardware)
The PCnet-ISA+ controller has both I/O and memory re-
sources. In the I/O space the resources are organized
as indicated in the following table:
The PCnet-ISA+ controller supports both 8- and 16-bit
hardware bus cycles. The following sections outline
where any limitations apply based upon the architecture
mode and/or the resource that is being accessed
(PCnet-ISA+ controller registers, address PROM, boot
PROM, or shared memory SRAM). For completeness,
the following sections are arranged by architecture (Bus
Master Mode or Shared Memory Mode). SRAM re-
sources apply only to Shared Memory Mode.
Offset
0h
#Bytes
Register
16
2
IEEE Address
RDP
10h
12h
14h
16h
2
RAP (shared by RDP and IDP)
2
Reset
IDP
All resources (registers, PROMs, SRAM) are presented
to the ISA bus by the PCnet-ISA+ controller. With few ex-
ceptions, these resources can be configured for either
8-bit or 16-bit bus cycles. The I/O resources (registers,
address PROM) are width configured using the
EEPROM. The memory resources (boot PROM,
SRAM) are width configured by external hardware.
2
The PCnet-ISA+ controller does not respond to any ad-
dresses outside of the offset range 0-17h. I/O offsets
18h and up are not used by the PCnet-ISA+ controller.
I/O Register Access
For 16-bit memory accesses, hardware external to the
PCnet-ISA+ controller asserts MEMCS16when either of
the two memory resources is selected. The ISA bus re-
quires that all memory resources within a block of
128 Kbytes be the same width, either 8- or 16-bits. The
reason for this is that the MEMCS16 signal is generally
a decode of the LA17-23 address lines. 16-bit memory
capability is desirable since two 8-bit accesses take the
same amount of time as four 16-bit accesses.
The register address port (RAP) is shared by the regis-
ter data port (RDP) and the ISACSR data port (IDP) to
save registers. To access the Ethernet controller’s RDP
or IDP, the RAP should be written first, followed by the
read or write access to the RDP or IDP. I/O register ac-
cesses should be coded as 16-bit accesses, even if the
PCnet-ISA+ controller is hardware configured for 8-bit
I/O bus cycles. It is acceptable (and transparent) for the
motherboard to turn a 16-bit software access into two
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All accesses to 8-bit resources (which do not return
MEMCS16 or IOCS16) use SD0-7. If an odd byte is ac-
cessed, the Current Master swap buffer turns on. During
an odd byte read the swap buffer copies the data from
SD0-7 to the high byte. During an odd byte write the Cur-
rent Master swap buffer copies the data from the high
byte to SD0-7. The PCnet-ISA+ controller can be config-
ured to be an 8-bit I/O resource even in a 16-bit system;
this is set by the EEPROM. It is recommended that the
PCnet-ISA+ controller be configured for 8-bit only I/O
bus cycles for maximum compatibility with PC/AT clone
motherboards.
SD8-15. It is illegal to have A0=1 and SBHE=1 in any
bus cycle. The PCnet-ISA+ controller returns only
IOCS16; MEMCS16 must be generated by external
hardware if desired. The use of MEMCS16 applies only
to Shared Memory Mode.
The following table describes all possible types of ISA
bus accesses, including Permanent Master as Current
Master and PCnet-ISA+ controller as Current Master.
The PCnet-ISA+ controller will not work with 8-bit mem-
ory while it is Current Master. Any descriptions of 8-bit
memory accesses are for when the Permanent Master
is Current Master.
When the PCnet-ISA+ controller is in an 8-bit system
such as a PC/XT, SBHE and IOCS16 must be left un-
connected (these signals do not exist in the PC/XT).
This will force ALL resources (I/O and memory) to sup-
port only 8-bit bus cycles. The PCnet-ISA+ controller will
function in an 8-bit system only if configured for Shared
Memory Mode.
The two byte columns (D0–7 and D8–15) indicate
whether the bus master or slave is driving the byte.
CS16 is a shorthand for MEMCS16 and IOCS16.
Bus Master Mode
The PCnet-ISA+ controller can be configured as a Bus
Master only in systems that support bus mastering. In
addition, the system is assumed to support 16-bit
memory (DMA) cycles (the PCnet-ISA+ controler does
not use the MEMCS16signal on the ISA bus). This does
not preclude the PCnet-ISA+ controller from doing 8-bit
I/O transfers. The PCnet-ISA+ controller will not function
as a bus master in 8-bit platforms such as the PC/XT.
Accesses to 16-bit resources (which do return
MEMCS16 or IOCS16) use either or both SD0–7 and
SD8–15. A word access is indicated by A0=0 and
SBHE=0 and data is transferred on all 16 data lines. An
evenbyteaccessisindicatedbyA0=0andSBHE=1and
data is transferred on SD0–7. An odd-byte access is in-
dicated by A0=1 and SBHE=0 and data is transferred on
ISA Bus Accesses
R/W
RD
RD
RD
A0
0
SBHE
CS16
D0–7
Slave
Slave
Slave
D8–15
Float
Comments
Low byte RD
1
0
0
x
1
1
1
Float*
Float
High byte RD with swap
0
16-Bit RD converted to
low byte RD
RD
RD
1
0
0
1
0
0
0
1
0
0
0
0
x
1
1
Float
Slave
Slave
Slave
Float
High byte RD
16-Bit RD
WR
WR
WR
Master
Float*
Master
Low byte WR
Master
Master
High byte WR with swap
16-Bit WR converted to
low byte WR
WR
WR
1
0
0
0
0
0
Float
Master
Master
High byte WR
16-Bit WR
Master
*Motherboard SWAP logic drives
Refresh Cycles
because some motherboards generate a false DACK at
that time.
Although the PCnet-ISA+ controller is neither an origina-
tor or a receiver of refresh cycles, it does need to avoid
unintentional activity during a refresh cycle in bus mas-
ter mode. A refresh cycle is performed as follows: First,
the REF signal goes active. Then a valid refresh ad-
dress is placed on the address bus. MEMR goes active,
the refresh is performed, and MEMR goes inactive. The
refresh address is held for a short time and then goes
invalid. Finally, REF goes inactive. During a refresh cy-
cle, as indicated by REF being active, the PCnet-ISA+
controller ignores DACK if it goes active until it goes in-
active. It is necessary to ignore DACK during a refresh
Address PROM Cycles External PROM
The Address PROM is a small (16 bytes) 8-bit PROM
connected to the PCnet-ISA+ controller Private Data
Bus. The PCnet-ISA+ controller will support only 8-bit
ISA I/O bus cycles for the address PROM; this limitation
is transparent to software and does not preclude 16-bit
software I/O accesses. An access cycle begins with the
Permanent Master driving AEN LOW, driving the ad-
dresses valid, and driving IOR active. The PCnet-ISA+
controller detects this combination of signals and
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arbitrates for the Private Data Bus (PRDB) if necessary.
IOCHRDY is driven LOW during accesses to the ad-
dress PROM.
based family of Ethernet cards is not required but does
not have any harmful effects. IOCS16 is not asserted in
this cycle.
When the Private Data Bus becomes available, the
PCnet-ISA+ controller drives APCS active, releases
IOCHRDY, turns on the data path from PRD0-7, and en-
ables the SD0-7 drivers (but not SD8-15). During this
bus cycle, IOCS16 is not driven active. This condition is
maintained until IOR goes inactive, at which time the
bus cycle ends. Data is removed from SD0-7 within
30 ns.
ISA Configuration Register Cycles
The ISA configuration registers are accessed by placing
the address of the desired register into the RAP and
reading the IDP. The ISACSR bus cycles are identical
to all other PCnet-ISA+ controller register bus cycles.
Boot PROM Cycles
The Boot PROM is an 8-bit PROM connected to the
PCnet-ISA+ controllerPrivateDataBus(PRDB)andcan
occupy up to 64K of address space. Since the
PCnet-ISA+ controller does not generate MEMCS16,
only 8-bit ISA memory bus cycles to the boot PROM are
supported in Bus Master Mode; this limitation is trans-
parent to software and does not preclude 16-bit
software memory accesses. A boot PROM access cycle
begins with the Permanent Master driving the ad-
dresses valid, REF inactive, and MEMR active. (AEN is
not involved in memory cycles). The PCnet-ISA+ con-
troller detects this combination of signals, drives
IOCHRDY LOW, and reads a byte out of the Boot
PROM. The data byte read is driven onto the lower sys-
tem data bus lines and IOCHRDY is released. This
condition is maintained until MEMR goes inactive, at
which time the access cycle ends.
Address PROM Cycles Using EEPROM Data
Default mode. In this mode, the IEEE address informa-
tion is stored not in an external parallel PROM but in the
EEPROM along with other configuration information.
PCnet-ISA+ will respond to I/O reads from the IEEE ad-
dress (the first 16 bytes of the I/O map) by supplying
data from an internal RAM inside PCnet-ISA+. This in-
ternal RAM is loaded with the IEEE address at RESET
and is write protected.
Ethernet Controller Register Cycles
Ethernet controller registers (RAP, RDP, IDP) are natu-
rally 16-bit resources but can be configured to operate
with 8-bit bus cycles provided the proper protocol is fol-
lowed. This means on a read, the PCnet-ISA+ controller
will only drive the low byte of the system data bus; if an
odd byte is accessed, it will be swapped down. The high
byte of the system data bus is never driven by the
PCnet-ISA+ controller under these conditions. On a
write cycle, the even byte is placed in a holding register.
An odd byte write is internally swapped up and aug-
mented with the even byte in the holding register to
provide an internal 16-bit write. This allows the use of
8-bit I/O bus cycles which are more likely to be compat-
ible with all ISA-compatible clones, but requires that
both bytes be written in immediate succession. This is
accomplished simply by treating the PCnet-ISA+ con-
troller controller registers as 16-bit software resources.
The motherboard will convert the 16-bit accesses done
by software into two sequential 8-bit accesses, an even
byte access followed immediately by an odd byte
access.
The BPCS signal generated by the PCnet-ISA+ control-
ler is three 20 MHz clock cycles wide (300 ns). Including
delays, the Boot PROM has 275 ns to respond to the
BPCS signal from the PCnet-ISA+ controller. This signal
is intended to be connected to the CS pin on the boot
PROM, with the PROM OE pin tied to ground.
Current Master Operation
Current Master operation only occurs in the bus master
mode. It does not occur in shared memory mode.
There are three phases to the use of the bus by the
PCnet-ISA+ controller as Current Master, the Obtain
Phase, the Access Phase, and the Release Phase.
Obtain Phase
A Master Mode Transfer Cycle begins by asserting
DRQ. When the Permanent Master asserts DACK, the
PCnet-ISA+ controller asserts MASTER, signifying it
has taken control of the ISA bus. The Permanent Master
tristatestheaddress, command, anddatalineswithin60
ns of DACK going active. The Permanent Master drives
AEN inactive within 71 ns of MASTER going active.
An access cycle begins with the Permanent Master driv-
ingAENLOW, drivingtheaddressvalid, anddrivingIOR
or IOW active. The PCnet-ISA+ controller detects this
combination of signals and drives IOCHRDY LOW.
IOCS16 will also be driven LOW if 16-bit I/O bus cycles
are enabled. When the register data is ready, IOCHRDY
will be released HIGH. This condition is maintained until
IOR or IOW goes inactive, at which time the bus cycle
ends.
Access Phase
The ISA bus requires a wait of at least 125 ns after
MASTER is asserted before the new master is allowed
to drive the address, command, and data lines. The
PCnet-ISA+ controller will actually wait 3 clock cycles or
150 ns.
RESET Cycles
A read to the reset address causes an PCnet-ISA+ con-
troller reset. This has the same effect as asserting the
RESET pin on the PCnet-ISA+ controller, such as hap-
pens during a system power-up or hard boot. The
subsequent write cycle needed in the NE2100 LANCE
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The following signals are not driven by the Permanent Master Mode Memory Write Cycle
AMD
After the PCnet-ISA+ controller has acquired the ISA
bus, it can perform a memory write cycle. All timing is
generated relative to a 20 MHz clock which happens to
be the same as the network clock. Since there is no way
to tell if memory is 8- or 16-bit or when it is ready, the
PCnet-ISA+ controller by default assumes 16-bit, 1 wait
state memory. The wait state assumption is based on
the default value in the MSWRA register in ISACSR1.
Master and are simply pulled HIGH: BALE, IOCHRDY,
IOCS16, MEMCS16, SRDY. Therefore, the PCnet-ISA+
controller assumes the memory which it is accessing is
16 bits wide and can complete an access in the time pro-
grammed for the PCnet-ISA+ controller MEMR and
MEMW signals. Refer to the ISA Bus Configuration
Register description section.
Release Phase
The cycle begins with SA0-19, SBHE, and LA17-23 be-
ing presented. The ISA bus requires them to be valid at
least 28 ns before MEMW goes active and data to be
valid at least 22 ns before MEMW goes active. The
PCnet-ISA+ controller provides one clock or 50 ns of
setup time for all these signals.
When the PCnet-ISA+ controller is finished with the bus,
itdrivesthecommandlinesinactive. 50nslater, thecon-
troller tri-states the command, address, and data lines
and drives DRQ inactive. 50 ns later, the controller
drives MASTER inactive.
ThePermanentMasterdrivesAENactivewithin71nsof
MASTER going inactive. The Permanent Master is al-
lowed to drive the command lines no sooner than 60 ns
after DACK goes inactive.
The ISA bus requires MEMW to be active for at least
219 ns, andthePCnet-ISA+ controllerprovidesadefault
of 5 clocks, or 250 ns, but this can be tuned for faster
systems with the Master Mode Write Active (MSWRA)
register (ISACSR1). Also, if IOCHRDY is driven LOW,
the PCnet-ISA+ controller will wait. IOCHRDY must be
HIGH for the PCnet-ISA+ controller to continue.
Master Mode Memory Read Cycle
After the PCnet-ISA+ controller has acquired the ISA
bus, it can perform a memory read cycle. All timing is
generated relative to the 20 MHz clock (network clock).
Since there is no way to tell if memory is 8- or 16-bit or
when it is ready, the PCnet-ISA+ controller by default as-
sumes 16-bit, 1 wait state memory. The wait state
assumption is based on the default value in the MSRDA
register in ISACSR0.
The ISA bus requires data to be valid for at least 25 ns
after MEMW goes inactive, and the PCnet-ISA+ control-
ler provides one clock or 50 ns.
The ISA bus requires all command lines to remain inac-
tive for at least 97 ns before starting another bus cycle.
The PCnet-ISA+ controller provides at least two clocks
or 100 ns of inactive time when bit 4 in ISACSR2 is set.
The EISA bus requires all command lines to remain in-
active for at least 170 ns before starting another bus
cycle. When bit 4 in ISACSR4 is cleared, the
PCnet-ISA+ controller provides 200 ns of inactive time.
The cycle begins with SA0-19, SBHE, and LA17-23 be-
ing presented. The ISA bus requires them to be valid for
at least 28 ns before a read command and the
PCnet-ISA+ controller provides one clock or 50 ns of
setup time before asserting MEMR.
The ISA bus requires MEMR to be active for at least
219 ns, andthePCnet-ISA+ controllerprovidesadefault
of 5 clocks, or 250 ns, but this can be tuned for faster
systems with the Master Mode Read Active (MSRDA)
register (see section 2.5.2). Also, if IOCHRDY is driven
LOW, the PCnet-ISA+ controller will wait. The wait state
counter must expire and IOCHRDY must be HIGH for
the PCnet-ISA+ controller to continue.
Shared Memory Mode
Address PROM Cycles External PROM
The Address PROM is a small (16 bytes) 8-bit PROM
connected to the PCnet-ISA+ controller Private Data
Bus (PRDB). The PCnet-ISA+ controller will support
only 8-bit ISA I/O bus cycles for the address PROM; this
limitation is transparent to software and does not pre-
clude 16-bit software I/O accesses. An access cycle
begins with the Permanent Master driving AEN LOW,
driving the addresses valid, and driving IOR active. The
PCnet-ISA+ controller detects this combination of sig-
nals and arbitrates for the Private Data Bus if necessary.
IOCHRDY is always driven LOW during address PROM
accesses.
The PCnet-ISA+ controller then accepts the memory
read data. The ISA bus requires all command lines to re-
main inactive for at least 97 ns before starting another
bus cycle and the PCnet-ISA+ controller provides at
least two clocks or 100 ns of inactive time.
The ISA bus requires read data to be valid no more than
173 ns after receiving MEMR active and the PCnet-
ISA+ controller requires 10 ns of data setup time. The
ISA bus requires read data to provide at least 0 ns of
hold time and to be removed from the bus within 30 ns
after MEMR goes inactive. The PCnet-ISA+ controller
requires 0 ns of data hold time.
When the Private Data Bus becomes available, the
PCnet-ISA+ controller drives APCS active, releases
IOCHRDY, turns on the data path from PRD0-7, and en-
ables the SD0-7 drivers (but not SD8-15). During this
bus cycle, IOCS16 is not driven active. This condition is
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maintained until IOR goes inactive, at which time the
access cycle ends. Data is removed from SD0-7 within
30 ns.
ISA Configuration Register Cycles
The ISA configuration register is accessed by placing
the address of the desired register into the RAP and
reading the IDP. The ISACSR bus cycles are identical
to all other PCnet-ISA+ controller register bus cycles.
The PCnet-ISA+ controller will perform 8-bit ISA bus cy-
cle operation for all resources (registers, PROMs,
SRAM) if SBHE has been left unconnected, such as in
the case of an 8-bit system like the PC/XT.
Boot PROM Cycles
The Boot PROM is an 8-bit PROM connected to the
PCnet-ISA+ controller Private Data Bus (PRDB), and
can occupy up to 64 Kbytes of address space. In Shared
Memory Mode, an external address comparator is re-
sponsible for asserting BPAM to the PCnet-ISA+
controller. BPAM is intended to be a perfect decode of
thebootPROMaddressspace, i.e. LA17-23, SA16. The
LA bus must be latched with BALE in order to provide
stable signal for BPAM. REF inactive must be used by
the external logic to gate boot PROM address decoding.
This same logic must assert MEMCS16 to the ISA bus if
16-bit Boot PROM bus cycles are desired.
Ethernet Controller Register Cycles
Ethernet controller registers (RAP, RDP, ISACSR) are
naturally 16-bit resources but can be configured to oper-
ate with 8-bit bus cycles provided the proper protocol is
followed. This is programmable by the EEPROM. This
means on a read, the PCnet-ISA+ controller will only
drive the low byte of the system data bus; if an odd byte
is accessed, it will be swapped down. The high byte of
the system data bus is never driven by the PCnet-ISA+
controller under these conditions. On a write, the even
byte is placed in a holding register. An odd-byte write is
internally swapped up and augmented with the even
byte in the holding register to provide an internal 16-bit
write. This allows the use of 8-bit I/O bus cycles which
are more likely to be compatible with all clones, but re-
quires that both bytes be written in immediate
succession. This is accomplished simply by treating the
PCnet-ISA+ controller controller registers as 16-bit soft-
ware resources. The motherboard will convert the 16-bit
accesses done by software into two sequential 8-bit ac-
cesses, an even- byte access followed immediately by
an odd-byte access.
The PCnet-ISA+ controller assumes 16-bit ISA memory
bus cycles for the boot PROM. A 16-bit boot PROM bus
cycle begins with the Permanent Master driving the ad-
dresses valid and MEMR active. (AEN is not involved in
memory cycles). External hardware would assertBPAM
and MEMCS16. The PCnet-ISA+ controller detects this
combination of signals, drives IOCHRDY LOW, and
reads two bytes out of the boot PROM. The data bytes
read from the PROM are driven by the PCnet-ISA+ con-
troller onto SD0-15 and IOCHRDY is released. This
condition is maintained until MEMR goes inactive, at
which time the access cycle ends.
An access cycle begins with the Permanent Master driv-
ingAENLOW, drivingtheaddressvalid, anddrivingIOR
or IOW active. The PCnet-ISA+ controller detects this
combination of signals and drives IOCHRDY LOW.
IOCS16 will also be driven LOW if 16-bit I/O bus cycles
are enabled. When the register data is ready, IOCHRDY
will be released HIGH. This condition is maintained until
IOR or IOW goes inactive, at which time the bus cycle
ends.
The PCnet-ISA+ controller will perform 8-bit ISA bus cy-
cle operation for all resource (registers, PROMs,
SRAM) if SBHE has been left unconnected, such as in
the case of an 8-bit system like the PC/XT.
The BPCS signal generated by the PCnet-ISA+ control-
ler is three 20 MHz clock cycles wide (350 ns). Including
delays, the Boot PROM has 275 ns to respond to the
BPCS signal from the PCnet-ISA+ controller. This signal
is intended to be connected to the CS pin on the boot
PROM, with the PROM OE pin tied to ground.
The PCnet-ISA+ controller will perform 8-bit ISA bus cy-
cle operation for all resources (registers, PROMs,
SRAM) if SBHE has been left unconnected, such as in
the case of an 8-bit system like the PC/XT.
Static RAM Cycles
The shared memory SRAM is an 8-bit device connected
to the PCnet-ISA+ controller Private Bus, and can oc-
cupy up to 64 Kbytes of address space. In Shared
Memory Mode, an external address comparator is re-
sponsible for asserting SMAM to the PCnet-ISA+
controller. SMAM is intended to be a perfect decode of
the SRAM address space, i.e. LA17-23, SA16 for 64
Kbytes of SRAM. The LA signals must be latched by
BALE in order to provide a stable decode for SMAM.
RESET Cycles
A read to the reset address causes an PCnet-ISA+ con-
troller reset. This has the same effect as asserting the
RESET pin on the PCnet-ISA+ controller, such as hap-
pens during a system power-up or hard boot. The
subsequent write cycle needed in the NE2100 LANCE-
based family of Ethernet cards is not required but does
not have any harmful effects. IOCS16 is not asserted in
this cycle.
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The PCnet-ISA+ controller assumes 16-bit ISA memory
bus cycles for the SRAM, so this same logic must assert
MEMCS16 to the ISA bus if 16-bit bus cycles are to be
supported.
(registers, PROMs, SRAM) if SBHE has never been
driven active since the last RESET, such as in the case
of an 8-bit system like the PC/XT. In this case, the exter-
nal address decode logic must not assert MEMCS16 to
the ISA bus, which will be the case if MEMCS16 is left
unconnected. It is possible to manufacture a dual 8/16
bit PCnet-ISA+ controller adapter card, as the
MEMCS16 and SBHE signals do not exist in the PC/XT
environment.
A 16-bit SRAM bus cycle begins with the Permanent
Master driving the addresses valid, REF inactive, and
either MEMR or MEMW active. (AEN is not involved in
memory cycles). External hardware would assert
SMAM and MEMCS16. The PCnet-ISA+ controller de-
tects this combination of signals and initiates the SRAM
access.
At the memory device level, each SRAM Private Bus
read cycle takes two 50 ns clock periods for a maximum
read access time of 75 ns. The timing looks like this:
In a write cycle, the PCnet-ISA+ controller stores the
data into an internal holding register, allowing the ISA
bus cycle to finish normally. The data in the holding reg-
ister will then be written to the SRAM without the need
for ISA bus control. In the event the holding register is
already filled with unwritten SRAM data, the PCnet-ISA+
controller will extend the ISA write cycle by driving
IOCHRDY LOW until the unwritten data is stored in the
SRAM. The current ISA bus cycle will then complete
normally.
XTAL1
(20 MHz)
Address
SROE
In a read cycle, the PCnet-ISA+ controller arbitrates for
the Private Bus. If it is unavailable, the PCnet-ISA+ con-
troller drives IOCHRDY LOW. The PCnet-ISA+
controller compares the 16 bits of address on the Sys-
tem Address Bus with that of a data word held in an
internal pre-fetch register.
18183B-17
Static RAM Read Cycle
The address and SROE go active within 20 ns of the
clock going HIGH. Data is required to be valid 5 ns be-
fore the end of the second clock cycle. Address and
SROE have a 0 ns hold time after the end of the second
clock cycle. Note that the PCnet-ISA+ controller does
not normally provide a separate SRAM CS signal;
SRAM CS must always be asserted.
If the address does not match that of the prefetched
SRAM data, then the PCnet-ISA+ controller drives
IOCHRDY LOW and reads two bytes from the SRAM.
The PCnet-ISA+ controller then proceeds as though the
addressed data location had been prefetched.
SRAM Private Bus write cycles require three 50 ns clock
periods to guarantee non-negative address setup and
hold times with regard to SRWE. The timing is illustrated
as follows:
If the internal prefetch buffer contains the correct data,
then the pre-fetch buffer data is driven on the System
Data bus. If IOCHRDY was previously driven LOW due
to either Private Data Bus arbitration or SRAM access,
then it is released HIGH. The PCnet-ISA+ controller re-
mains in this state until MEMR is de-asserted, at which
time the PCnet-ISA+ controller performs a new prefetch
of the SRAM. In this way memory read wait states can
be minimized.
XTAL
(20 MHz)
Address/
The PCnet-ISA+ controller performs prefetches of the
SRAM between ISA bus cycles. The SRAM is
prefetched in an incrementing word address fashion.
Prefetched data are invalidated by any other activity on
the Private Bus, including Shared Memory Writes by
either the ISA bus or the network interface, and also ad-
dress and boot PROM reads.
Data
SRWE
18183B-18
Static RAM Write Cycle
The only way to configure the PCnet-ISA+ controller for
8-bit ISA bus cycles for SRAM accesses is to configure
the entire PCnet-ISA+ controller to support only 8-bit ISA
bus cycles. This is accomplished by leaving the SBHE
pin disconnected. The PCnet-ISA+ controller will per-
form 8-bit ISA bus cycle operation for all resources
Address and data are valid 20 ns after the rising edge of
the first clock period. SRWE goes active 20 ns after the
fallingedgeofthefirstclockperiod. SRWEgoesinactive
20 ns after the falling edge of the third clock period.
Address and data remain valid until the end of the third
clock period. Rise and fall times are nominally 5 ns.
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Non-negativesetupandholdtimesforaddressanddata
with respect to SRWE are guaranteed. SRWE has a
pulse width of typically 100 ns, minimum 75 ns.
withthevalueof00h. ThedefaultvalueofAPAD_XMTis
0, andthiswilldisableautopadgenerationafterRESET.
It is the responsibility of upper layer software to correctly
define the actual length field contained in the message
to correspond to the total number of LLC Data bytes en-
capsulated in the packet (length field as defined in the
IEEE 802.3 standard). The length value contained in the
message is not used by the PCnet-ISA+ controller to
compute the actual number of pad bytes to be inserted.
The PCnet-ISA+ controller will append pad bytes de-
pendent on the actual number of bits transmitted onto
the network. Once the last data byte of the frame has
completed prior to appending the FCS, the PCnet-ISA+
controller will check to ensure that 544 bits have been
transmitted. If not, pad bytes are added to extend the
frame size to this value, and the FCS is then added.
Transmit Operation
The transmit operation and features of the PCnet-ISA+
controller are controlled by programmable options.
Transmit Function Programming
Automatic transmit features, such as retry on collision,
FCS generation/transmission, and pad field insertion,
can all be programmed to provide flexibility in the
(re-)transmission of messages.
Disable retry on collision (DRTY) is controlled by the
DRTY bit of the Mode register (CSR15) in the initializa-
tion block.
The 544 bit count is derived from the following:
Minimum frame size (excluding preamble,
Automatic pad field insertion is controlled by the
APAD_XMT bit in CSR4. If APAD_XMT is set, auto-
matic pad field insertion is enabled, the DXMTFCS
feature is over-ridden, and the 4-byte FCS will be added
to the transmitted frame unconditionally. If APAD_XMT
is cleared, no pad field insertion will take place and runt
packet transmission is possible.
including FCS)
Preamble/SFD size 8 bytes
FCS size 4 bytes
64 bytes
512 bits
64 bits
32 bits
To be classed as a minimum-size frame at the receiver,
the transmitted frame must contain:
Preamble
+
(Min Frame Size + FCS) bits
The disable FCS generation/transmission feature can
be programmed dynamically on a frame by frame basis.
See the ADD_FCS description of TMD1.
At the point that FCS is to be appended, the transmitted
frame should contain:
Transmit FIFO Watermark (XMTFW in CSR80) sets the
point at which the BMU (Buffer Management Unit) re-
quests more data from the transmit buffers for the FIFO.
This point is based upon how many 16-bit bus transfers
(2 bytes) could be performed to the existing empty
space in the transmit FIFO.
Preamble
64
+
+
(Min Frame Size - FCS) bits
(512 32) bits
-
A minimum-length transmit frame from the PCnet-ISA+
controller will, therefore, be 576 bits after the FCS is
appended.
Transmit Start Point (XMTSP in CSR80) sets the point
when the transmitter actually tries to go out on the me-
dia. This point is based upon the number of bytes written
to the transmit FIFO for the current frame.
Transmit FCS Generation
Automatic generation and transmission of FCS for a
transmit frame depends on the value of DXMTFCS bit in
CSR15. When DXMTFCS = 0 the transmitter will gener-
ate and append the FCS to the transmitted frame. If the
automatic padding feature is invoked (APAD_XMT is
SET in CSR4), the FCS will be appended by the
PCnet-ISA+ controller regardless of the state of
DXMTFCS. Note that the calculated FCS is transmitted
most-significant bit first. The default value of DXMTFCS
is 0 after RESET.
When the entire frame is in the FIFO, attempts at trans-
mission of preamble will commence regardless of the
value in XMTSP. The default value of XMTSP is 10b,
meaning 64 bytes full.
Automatic Pad Generation
Transmit frames can be automatically padded to extend
them to 64 data bytes (excluding preamble). This allows
the minimum frame size of 64 bytes (512 bits) for
802.3/Ethernet to be guaranteed with no software inter-
vention from the host/controlling process. Setting the
APAD_XMT bit in CSR4 enables the automatic padding
feature. The pad is placed between the LLC data field
and FCS field in the 802.3 frame. FCS is always added if
the frame is padded, regardless of the state of
DXMTFCS. The transmit frame will be padded by bytes
Transmit Exception Conditions
Exception conditions for frame transmission fall into two
distinct categories; those which are the result of normal
network operation, and those which occur due to abnor-
mal network and/or host related events.
Normal events which may occur and which are handled
autonomously by the PCnet-ISA+ controller are
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basically collisions within the slot time with automatic re-
try. The PCnet-ISA+ controller will ensure that collisions
which occur within 512 bit times from the start of trans-
mission (including preamble) will be automatically
retried with no host intervention. The transmit FIFO en-
sures this by guaranteeing that data contained within
the FIFO will not be overwritten until at least 64 bytes
(512 bits) of data have been successfully transmitted
onto the network.
If 16 total attempts (initial attempt plus 15 retries) fail, the
PCnet-ISA+ controller sets the RTRY bit in the current
transmit TDTE in host memory (TMD2), gives up owner-
ship (sets the OWN bit to zero) for this packet, and
processes the next packet in the transmit ring for trans-
mission.
Preamble
1010....1010
SYNC
10101011
Dest.
ADDR
Srce.
ADDR.
LLC
Data
Length
Pad
FCS
56
8
6
6
2
4
Bits
Bits
Bytes
Bytes
Bytes
Bytes
46-1500
Bytes
18183B-19
16907B-12
ISO 8802-3 (IEEE/ANSI 802.3) Data Frame
Abnormal network conditions include:
The PCnet-ISA+ controller will abandon the transmit
process for the particular frame, set Late Collision
(LCOL) in the associated TMD3, and process the next
transmit frame in the ring. Frames experiencing a late
collision will not be re-tried. Recovery from thiscondition
must be performed by upper-layer software.
■ Loss of carrier
■ Late collision
■ SQE Test Error (Does not apply to 10BASE-T
port.)
These should not occur on a correctly configured 802.3
network, and will be reported if they do.
SQE Test Error
During the inter packet gap time following the comple-
tion of a transmitted message, the AUI CI± pair is
asserted by some transceivers as a self-test. The inte-
gral Manchester Encoder/Decoder will expect the SQE
Test Message (nominal 10 MHz sequence) to be re-
turned via the CI± pair within a 40 network bit time period
after DI± pair goes inactive. If the CI± inputs are not
asserted within the 40 network bit time period following
the completion of transmission, then the PCnet-ISA+
controller will set the CERR bit in CSR0. CERR will be
asserted in 10BASE-T mode after transmit if T-MAU is
inLinkFailstate. CERRwillnevercauseINTRtobeacti-
vated. It will, however, set the ERR bit in CSR0.
When an error occurs in the middle of a multi-buffer
frame transmission, the error status will be written in the
current descriptor. The OWN bit(s) in the subsequent
descriptor(s) will be reset until the STP (the next frame)
is found.
Loss of Carrier
A loss of carrier condition will be reported if the
PCnet-ISA+ controller cannot observe receive activity
while it is transmitting on the AUI port. After the
PCnet-ISA+ controller initiates a transmission, it will
expect to see data “looped back” on the DI± pair. This
will internally generate a “carrier sense,” indicating that
the integrity of the data path to and from the MAU is in-
tact, and that the MAU is operating correctly. This
“carrier sense” signal must be asserted before the end
of the transmission. If “carrier sense” does not become
active in response to the data transmission, or becomes
inactive before the end of transmission, the loss of car-
rier (LCAR) error bit will be set in TMD2 after the frame
has been transmitted. The frame will not be re-tried on
the basis of an LCAR error. In 10BASE-T mode LCAR
will indicate that Jabber or Link Fail state has occurred.
Host related transmit exception conditions include
BUFF and UFLO as described in the Transmit Descrip-
tor section.
Receive Operation
The receive operation and features of the PCnet-ISA+
controller are controlled by programmable options.
Receive Function Programming
Late Collision
Automatic pad field stripping is enabled by setting the
ASTRP_RCV bit in CSR4; this can provide flexibility in
the reception of messages using the 802.3 frame
format.
A late collision will be reported if a collision condition oc-
curs after one slot time (512 bit times) after the transmit
process was initiated (first bit of preamble commenced).
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AllreceiveframescanbeacceptedbysettingthePROM
bit in CSR15. When PROM is set, the PCnet-ISA+ con-
troller will attempt to receive all messages, subject to
minimum frame enforcement. Promiscuous mode over-
rides the effect of the Disable Receive Broadcast bit on
receiving broadcast frames.
The number of bytes to be stripped is calculated from
the embedded length field (as defined in the IEEE 802.3
definition) contained in the frame. The length indicates
the actual number of LLC data bytes contained in the
message. Any received frame which contains a length
field less than 46 bytes will have the pad field stripped (if
ASTRP_RCV is set). Receive frames which have a
length field of 46 bytes or greater will be passed to the
host unmodified.
The point at which the BMU will start to transfer data
from the receive FIFO to buffer memory is controlled by
the RCVFW bits in CSR80. The default established dur-
ing reset is 10b, which sets the threshold flag at 64 bytes
empty.
Since any valid Ethernet Type field value will always be
greater than a normal 802.3 Length field (≥46), the
PCnet-ISA+ controller will not attempt to strip valid
Ethernet frames.
Automatic Pad Stripping
During reception of an 802.3 frame the pad field can be
stripped automatically. ASTRP_RCV (bit 10 in CSR4) =
1 enables the automatic pad stripping feature. The pad
field will be stripped before the frame is passed to the
FIFO, thus preserving FIFO space for additional frames.
The FCS field will also be stripped, since it is computed
at the transmitting station based on the data and pad
field characters, and will be invalid for a receive frame
that has had the pad characters stripped.
Note that for some network protocols the value passed
in the Ethernet Type and/or 802.3 Length field is not
compliant with either standard and may cause
problems.
The diagram below shows the byte/bit ordering of the re-
ceivedlengthfieldforan802.3compatibleframeformat.
46–1500
Bytes
56
8
6
6
2
4
Bits
Bits
Bytes
Bytes
Bytes
Bytes
Preamble
SYNCH
Dest.
Srce.
Length
LLC
Pad
FCS
1010....1010
10101011
ADDR.
ADDR.
DATA
1–1500
Bytes
45–0
Bytes
Start of Packet
at Time= 0
Bit
0
Bit Bit
Bit
7
7
0
Most
Significant
Byte
Least
Significant
Byte
Increasing Time
18183B-20
IEEE/ANSI 802.3 Frame and Length Field Transmission Order
Receive FCS Checking
error is detected, this will be reported by the CRC bit in
RMD1.
Reception and checking of the received FCS is per-
formed automatically by the PCnet-ISA+ controller. Note
that if the Automatic Pad Stripping feature is enabled,
the received FCS will be verified against the value com-
puted for the incoming bit stream including pad
characters, but it will not be passed to the host. If a FCS
Receive Exception Conditions
Exception conditions for frame reception fall into two
distinct categories; those which are the result of normal
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network operation, and those which occur due to abnor-
mal network and/or host related events.
receiver will not check for the FCS. However, the user
can verify the FCS by software.
Normal events which may occur and which are handled
autonomously by the PCnet-ISA+ controller are basi-
cally collisions within the slot time and automatic runt
packet rejection. The PCnet-ISA+ controller will ensure
that collisions which occur within 512 bit times from the
start of reception (excluding preamble) will be automati-
cally deleted from the receive FIFO with no host
intervention. The receive FIFO will delete any frame
which is composed of fewer than 64 bytes provided that
the Runt Packet Accept (RPA bit in CSR124) feature
has not been enabled. This criteria will be met regard-
less of whether the receive frame was the first (or only)
frame in the FIFO or if the receive frame was queued be-
hind a previously received message.
During loopback, the FCS logic can be allocated to the
receiver by setting DXMTFCS = 1 in CSR15.
If DXMTFCS=0, the MAC Engine will calculate and ap-
pend the FCS to the transmitted message. The receive
messagepassedtothehostwillthereforecontainanad-
ditional 4 bytes of FCS. In this loopback configuration,
the receive circuitry cannot detect FCS errors if
theyoccur.
If DXMTFCS=1, the last four bytes of the transmit mes-
sage must contain the (software generated) FCS
computed for the transmit data preceding it. The MAC
Engine will transmit the data without addition of an FCS
field, and the FCS will be calculated and verified at
thereceiver.
Abnormal network conditions include:
The loopback facilities of the MAC Engine allow full op-
eration to be verified without disturbance to the network.
Loopback operation is also affected by the state of the
Loopback Control bits (LOOP, MENDECL, and INTL) in
CSR15. This affects whether the internal MENDEC is
considered part of the internal or external loop-
backpath.
■ FCS errors
■ Late collision
These should not occur on a correctly configured 802.3
network and will be reported if they do.
HostrelatedreceiveexceptionconditionsincludeMISS,
BUFF, and OFLO. These are described in the Receive
Descriptor section.
The multicast address detection logic uses the FCS
generator circuit. Therefore, in the loopback mode(s),
the multicast address detection feature of the MAC En-
gine, programmed by the contents of the Logical
Address Filter (LADRF [63:0] in CSRs 8–11) can onlybe
tested when DXMTFCS=1, allocating the FCS genera-
tor to the receiver. All other features operate identically
in loopback as in normal operation, such as automatic
transmit padding and receive pad stripping.
Loopback Operation
Loopback is a mode of operation intended for system di-
agnostics. In this mode, the transmitter and receiver are
both operating at the same time so that the controller re-
ceives its own transmissions. The controller provides
two types of internal loopback and one type of external
loopback. In internal loopback mode, the transmitted
data can be looped back to the receiver at one of two
places inside the controller without actually transmitting
any data to the external network. The receiver will move
the received data to the next receive buffer, where it can
beexaminedbysoftware. Alternatively, inexternalloop-
back mode, data can be transmitted to and received
from the external network.
When performing an internal loopback, no frame will be
transmitted to the network. However, when the PCnet-
ISA+ controller is configured for internal loopback the
receiver will not be able to detect network traffic. Exter-
nal loopback tests will transmit frames onto the network
if the AUI port is selected, and the PCnet-PCI controller
will receive network traffic while configured for external
loopback when the AUI port is selected. Runt Packet
Accept is automatically enabled when any loopback
mode is invoked.
There are restrictions on loopback operation. The
PCnet-ISA+ controller has only one FCS generator cir-
cuit. The FCS generator can be used by the transmitter
to generate the FCS to append to the frame, or it can be
used by the receiver to verify the FCS of the received
frame. It can not be used by the receiver and transmitter
simultaneously.
Loopback mode can be performed with any frame size.
Runt Packet Accept is internally enabled (RPA bit in
CSR124 is not affected) when any loopback mode is in-
voked. This is to be backwards compatible to the
LANCE (Am7990) software.
If the FCS generator is connected to the receiver, the
transmitter will not append an FCS to the frame, but the
receiver will check for one. The user can, however, cal-
culate the FCS value for a frame and include this
four-byte number in the transmit buffer.
When the 10BASE-T MAU is selected in external loop-
back mode, the collision detection is disabled. This is
necessary, because a collision in a 10BASE-T system is
defined as activity on the transmitter outputs and re-
ceiver inputs at the same time, which is exactly what
occurs during external loopback.
If the FCS generator is connected to the transmitter, the
transmitter will append an FCS to the frame, but the
1-547
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P R E L I M I N A R Y
Since a 10BASE-T hub does not normally feed the sta-
tion’s transmitter outputs back into the station’s receiver
inputs, the use of external loopback in a 10BASE-T sys-
temusuallyrequiressomesortofexternalhardwarethat
connects the outputs of the 10BASE-T MAU to
itsinputs.
Each status signal is ANDed with its corresponding
enable signal. The enabled status signals run to a com-
mon OR gate:
COL
COL E
JAB
JAB E
LEDs
RCVADDM
RCVADDM E
The PCnet-ISA+ controller’s LED control logic allows
programming of the status signals, which are displayed
on 3 LED outputs. One LED (LED0) is dedicated to dis-
playing 10BASE-T Link Status. The status signals
available are Collision, Jabber, Receive, Receive Polar-
ity (active when receive polarity is okay), and Transmit.
If more than one status signal is enabled, they are ORed
together. An optional pulse stretcher is available for
eachprogrammableoutput. Thisallowsemulationofthe
TPEX (Am79C98) and TPEX+ (Am79C100) LED
outputs.
RCV
RCV E
RVP
RVP E
XMT
XMT E
18183B-21
LED Control Logic
The output from the OR gate is run through a pulse
stretcher, which consists of a 3-bit shift register clocked
at 38 Hz. The data input of the shift register is at logic 0.
The OR gate output asynchronously sets all three bits of
the shift register when its output goes active. The output
of the shift register controls the associated LEDx pin.
Thus, the pulse stretcher provides an LED output of
52 ms to 78 ms.
Signal
Behavior
Active during Link OK
LNKST
Not active during Link Down
RCV
Active while receiving data
RVPOL
Active during receive polarity is OK
Not active during reverse receive polarity
RCVADDM Active during Receive with Address Match
XMT Active while transmitting data
Refer to the section “ISA Bus Configuration Registers”
for information on LED control via the ISACSRs.
1-548
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P R E L I M I N A R Y
AMD
PCnet-ISA+ CONTROLLER REGISTERS
by RESET or by setting the
STOP bit.
The PCnet-ISA+ controller implements all LANCE
(Am7990) registers, plus a number of additional regis-
ters. The PCnet-ISA+ controller registers are compatible
with the original LANCE, but there are some places
where previously reserved LANCE bits are now used by
the PCnet-ISA+ controller. If the reserved LANCE bits
were used as recommended, there should be no com-
patibility problems.
13
CERR
Collision Error indicates that the
collision inputs to the AUI port
failed to activate within 20 net-
work bit times after the chip
terminated transmission (SQE
Test). This feature is a trans-
ceiver test feature. CERR will be
set in 10BASE-T mode during
trasmit if in Link Fail state.
Register Access
CERR assertion will not result in
an interrupt being generated.
CERR assertion will set the ERR
bit.
Internal registers are accessed in a two-step operation.
First, the address of the register to be accessed is writ-
ten into the register address port (RAP). Subsequent
read or write operations will access the register pointed
to by the contents of the RAP. The data will be read from
(or written to) the selected register through the data port,
either the register data port (RDP) for control and status
registers (CSR) or the ISACSR register data port (IDP)
for ISA control and status registers (ISACSR)
CERR is set by the MAC layer
and cleared by writing a “1”. Writ-
ing a “0” has no effect. CERR is
cleared by RESET or by setting
the STOP bit.
12
MISS
Missed Frame is set when
PCnet-ISA+ controller has lost an
incoming receive frame because
a Receive Descriptor was not
available. This bit is the only
indication that receive data has
been lost since there is no re-
ceive descriptor available for
status information.
RAP: Register Address Port
Bit
Name
Description
15-7
RES
Reserved locations. Read and
written as zeroes.
6-0
RAP
Register Address Port select.
Selects the CSR or ISACSR
location to be accessed. RAP is
cleared by RESET.
When MISS is set, IRQ is as-
serted if IENA = 1 and the mask
bit MISSM (CSR3.12) is clear.
MISS assertion will set the ERR
bit.
Control and Status Registers
CSR0: PCnet-ISA+ Controller Status Register
MISS is set by the Buffer Man-
agement Unit and cleared by
writing a “1”. Writing a “0” has no
effect. MISS is cleared by RE-
SET or by setting the STOP bit.
Bit
Name
Description
15
ERR
Error is set by the ORing of
BABL, CERR, MISS, and MERR.
ERR remains set as long as any
of the error flags are true. ERR is
read only; write operations are
ignored.
11
MERR
Memory Error is set when
PCnet-ISA+ controller is a bus
master and has not received
DACK assertion after 50 µs after
DRQ assertion. Memory Error in-
dicates that PCnet-ISA+ con-
troller is not receiving bus mas-
tership in time to prevent
overflow/underflow conditions in
the receive and transmit FIFOs.
14
BABL
Babble is a transmitter time-out
error. It indicates that the trans-
mitter has been on the channel
longer than the time required to
send the maximum length frame.
BABL will be set if 1519 bytes or
greater are transmitted.
(MERR indicates a slightly differ-
ent condition for the LANCE; for
the LANCE MERR occurs when
READY has not been asserted
25.6 µs after the address has
been asserted.)
When BABL is set, IRQ is as-
serted if IENA = 1 and the mask
bit BABLM (CSR3.14) is clear.
BABL assertion will set the
ERR bit.
When MERR is set, IRQ is as-
serted if IENA = 1 and the mask
bit MERRM (CSR3.11) is clear.
BABL is set by the MAC layer and
cleared by writing a “1”. Writing a
“0” has no effect. BABL is cleared
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P R E L I M I N A R Y
MERR assertion will set the ERR
and INTR is set, IRQ will be
active.
bit.
INTR is cleared automatically
when the condition that caused
interrupt is cleared.
INTR is read only. INTR is
cleared by RESET or by setting
the STOP bit.
Interrupt Enable allows IRQ to be
active if the Interrupt Flag is set. If
IENA = “0” then IRQ will be dis-
abled regardless of the state of
INTR.
IENA is set by writing a “1” and
cleared by writing a “0”. IENA is
cleared by RESET or by setting
the STOP bit.
Receive On indicates that the
Receive function is enabled.
RXON is set if DRX (CSR15.0) =
“0” after the START bit is set. If
INIT and START are set to-
gether, RXON will not be set until
after the initialization block has
been read in.
MERR is set by the Bus Interface
Unit and cleared by writing a “1”.
Writing a “0” has no effect. MERR
is cleared by RESET or by setting
the STOP bit.
10
RINT
Receive Interrupt is set after re-
ception of a receive frame and
toggling of the OWN bit in the last
buffer in the Receive Descriptor
Ring.
6
5
IENA
When RINT is set, IRQ is as-
serted if IENA = 1 and the mask
bit RINTM (CSR3.10) is clear.
RINT is set by the Buffer Man-
agement Unit after the last
receive buffer has been updated
and cleared by writing a “1”. Writ-
ing a “0” has no effect. RINT is
cleared by RESET or by setting
the STOP bit.
RXON
9
TINT
Transmit Interrupt is set after
transmission of a transmit frame
and toggling of the OWN bit in the
last buffer in the Transmit De-
scriptor Ring.
RXON is read only. RXON is
cleared by RESET or by setting
the STOP bit.
4
TXON
Transmit On indicates that the
Transmit function is enabled.
TXON is set if DTX (CSR15.1) =
“0” after the START bit is set. If
INIT and START are set to-
gether, TXON will not be set until
after the initialization block has
been read in.
When TINT is set, IRQ is as-
serted if IENA = 1 and the mask
bit TINTM (CSR3.9) is clear.
TINT is set by the Buffer Man-
agement Unit after the last
transmit buffer has been updated
and cleared by writing a “1”.
Writing a “0” has no effect. TINT
is cleared by RESET or by setting
the STOP bit.
TXON is read only. TXON is
cleared by RESET or by setting
the STOP bit.
3
TDMD
Transmit Demand, when set,
causes the Buffer Management
Unit to access the Transmit
Descriptor Ring without waiting
for the poll-time counter to
elapse. If TXON is not enabled,
TDMD bit will be reset and no
Transmit Descriptor Ring access
will occur. TDMD is required to
be set if the DPOLL bit in CSR4 is
set; setting TDMD while DPOLL
8
IDON
Initialization Done indicates that
the initialization sequence has
completed. When IDON is set,
PCnet-ISA+ controller has read
the Initialization block from
memory.
When IDON is set, IRQ is as-
serted if IENA = 1 and the mask
bit IDONM (CSR3.8) is clear.
IDON is set by the Buffer Man-
agement
Unit
after
the
=
0
merely hastens the
initialization block has been read
from memory and cleared by
writing a “1”. Writing a “0” has no
effect. IDON is cleared by RE-
SET or by setting the STOP bit.
PCnet-ISA+
controller’s re-
sponse to a Transmit Descriptor
Ring Entry.
TDMD is set by writing a “1”. Writ-
ing a “0” has no effect. TDMD will
be cleared by the Buffer Manage-
ment Unit when it fetches a
Transmit Descriptor. TDMD is
cleared by RESET or by setting
the STOP bit.
7
INTR
Interrupt Flag indicates that one
or more of the following interrupt
causing conditions has occurred:
BABL, MISS, MERR, MPCO,
RCVCCO, RINT, TINT, IDON,
JAB or TXSTRT; and its associ-
ated mask bit is clear. If IENA = 1
1-550
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P R E L I M I N A R Y
STOPassertiondisablesthechip 7-0 IADR [23:16]
from all external activity. The chip
remains inactive until either
STRT or INIT are set. If STOP,
STRT and INIT are all set to-
gether, STOP will override STRT
and INIT.
AMD
2
STOP
Upper 8 bits of the address of the
Initialization Block. Bit locations
15-8 must be written with zeros.
Whenever this register is written,
CSR17 is updated with CSR2’s
contents.
Read/Write accessible only
when the STOP bit in CSR0 is
set. Unaffected by RESET.
STOP is set by writing a “1” or by
RESET. Writing a “0” has no ef-
fect. STOP is cleared by setting
either STRT or INIT.
CSR3: Interrupt Masks and Deferral Control
1
STRT
STRT
assertion
enables
PCnet-ISA+ controller to send
and receive frames, and perform
buffer management operations.
Setting STRT clears the STOP
bit. If STRT and INIT are set to-
gether, PCnet-ISA+ controller
initialization will be performed
first.
Bit
Name
Description
15
RES
Reserved location. Written as
zero and read as undefined.
14
BABLM
Babble Mask. If BABLM is set,
the BABL bit in CSR0 will be
masked and will not set INTR flag
in CSR0.
STRT is set by writing a “1”. Writ-
ing a “0” has no effect. STRT is
cleared by RESET or by setting
the STOP bit.
BABLM is cleared by RESET and
is not affected by STOP.
13
12
RES
Reserved location. Written as
zero and read as undefined.
0
INIT
INIT assertion enables PCnet-
ISA+ controller to begin the
initialization procedure which
reads in the initialization block
from memory. Setting INIT clears
the STOP bit. If STRT and INIT
are set together, PCnet-ISA+
controller initialization will be per-
formed first. INIT is not cleared
when the initialization sequence
has completed.
MISSM
Missed Frame Mask. If MISSM is
set, the MISS bit in CSR0 will be
masked and will not set INTR flag
in CSR0.
MISSM is cleared by RESET and
is not affected by STOP.
11
10
9
MERRM
RINTM
TINTM
IDONM
RES
Memory Error Mask. If MERRM
is set, the MERR bit in CSR0 will
be masked and will not set INTR
flag in CSR0.
INIT is set by writing a “1”. Writing
a “0” has no effect. INIT is cleared
by RESET or by setting the
STOP bit.
MERRM is cleared by RESET
and is not affected by STOP.
Receive Interrupt Mask. If
RINTM is set, the RINT bit in
CSR0 will be masked and will not
set INTR flag in CSR0.
CSR1: IADR[15:0]
Bit Name
RINTM is cleared by RESET and
is not affected by STOP.
Description
Transmit Interrupt Mask. If
TINTM is set, the TINT bit in
CSR0 will be masked and will not
set INTR flag in CSR0.
15-0 IADR [15:0]
Lower address of the Initializa-
tion address register. Bit location
0 must be zero. Whenever this
register is written, CSR16 is up-
dated with CSR1’s contents.
TINTM is cleared by RESET and
is not affected by STOP.
Read/Write accessible only
when the STOP bit in CSR0 is
set. Unaffected by RESET.
8
Initialization Done Mask. If
IDONM is set, the IDON bit in
CSR0 will be masked and will not
set INTR flag in CSR0.
CSR2: IADR[23:16]
IDONM is cleared by RESET and
is not affected by STOP.
Bit
Name
Description
7-6
Reserved locations. Written as
zero and read as undefined.
15-8
RES
Reserved locations. Read and
written as zero.
1-551
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LAPPEN
P R E L I M I N A R Y
Look Ahead Packet Processing
5
the PCnet-ISA+ controller, then
the PCnet-ISA+ controller will
stop advancing through the ring
entries and begin periodic polling
of this entry. When the STP bit is
found to be true, and the descrip-
tor that contains this setting is
owned by the PCnet-ISA+ con-
troller, then the PCnet-ISA+
controller will stop advancing
through the ring entries, store the
descriptor information that is has
just read, and wait for the next re-
ceive to arrive.
(LAPPEN) . When set to a one,
the LAPPEN bit will cause the
PCnet-ISA+ controller to gener-
ate an interrupt following the
descriptor write operation to the
first buffer of a receive packet.
This interrupt will be generated in
addition to the interrupt that is
generated following the descrip-
tor write operation to the last
buffer of a receive packet. The in-
terrupt will be signaled through
the RINT bit of CSR0.
Setting LAPPEN to a one also
enables the PCnet-ISA+ control-
ler to read the STP bit of the
receive descriptors. PCnet-ISA+
controller will use STP informa-
tion to determine where it should
begin writing a receive packet’s
data. Note that while in this
mode, the PCnet-ISA+ controller
can write intermediate packet
data to buffers whose descriptors
do not contain STP bits set to
one. Following the write to the
last descriptor used by a packet,
the PCnet-ISA+ controller will
scan through the next descriptor
entries to locate the next STP
bit that is set to a one. The
PCnet-ISA+ controller will begin
writing the next packet’s data to
the buffer pointed to by that
descriptor.
This behavior allows the host
software to pre-assign buffer
space in such a manner that the
“header” portion of a receive
packet will always be written to a
particular memory area, and the
“data” portion of a receive packet
will always be written to a sepa-
rate memory area. The interrupt
is generated when the “header”
bytes have been written to the
“header” memory area.
Read/Write accessible always.
The LAPPEN bit will be reset
zero by RESET and will unaf-
fected by the STOP. See
Appendix E for more information
on LAPP.
4
3
DXMT2PD
Disable Transmit Two Part
Deferral. (Described in the Media
Access Management section). If
DXMT2PD is set, Transmit Two
Part Deferral will be disabled.
Note that because several de-
scriptors may be allocated by the
host for each packet, and not all
messagesmayneedallofthede-
scriptors that are allocated
between descriptors that contain
STP = one, then some descrip-
tors/buffers may be skipped in
the ring. While performing the
search for the next STP bit that is
set to one, the PCnet-ISA+ con-
troller will advance through the
receive descriptor ring regard-
less of the state of ownership
bits. If any of the entries that are
examined during this search indi-
cate PCnet-ISA+ will RESET the
OWN bit to zero in these entries.
If a scanned entry indicates host
ownership with STP=“0”, then
the PCnet-ISA+ controller will not
alter the entry, but will advance to
the next entry.
DXMT2PD is cleared by RESET
and is not affected by STOP.
EMBA
Enable
Modified
Back-off
Algorithm. If EMBA is set, a modi-
fied back-off algorithm is
implemented as described in the
Media Access Management
section.
Read/Write accessible. EMBA is
cleared by RESET and is not af-
fected by STOP.
2-0
RES
Reserved locations. Written as
zero and read as undefined.
CSR4: Test and Features Control
Bit
Name
Description
15
ENTST
Enable Test Mode operation.
When ENTST is set, writing to
test mode registers CSR124 and
CSR126 is allowed, and other
When the STP bit is found to be
true, but the descriptor that con-
tains this setting is not owned by
1-552
Am79C961
P R E L I M I N A R Y
register test functions are en-
AMD
This bit indicates the MFC
(CSR112) has overflowed. Can
be cleared by writing a “1” to this
bit. Also cleared by RESET or
setting the STOP bit. Writing a “0”
has no effect.
abled. In order to set ENTST, it
must be written with a “1” during
the first write access to CSR4
after RESET. Once a “0” is
written to this bit location, ENTST
cannot be set until after the
PCnet-ISA+ controller is reset.
8
MFCOM
Missed Frame Counter Overflow
Mask.
ENTST is cleared by RESET.
If MFCOM is set, MFCO will not
set INTR in CSR0.
14 DMAPLUS
When DMAPLUS = “1” , the burst
transaction counter in CSR80 is
disabled. If DMAPLUS = “0”, the
burst transaction counter is
enabled.
MFCOM is set by Reset and is
not affected by STOP.
7-6
5
RES
Reserved locations. Read and
written as zero.
DMA-PLUS is cleared by
RESET.
RCVCCO
Receive Collision Counter Over-
flow.
13
12
TIMER
DPOLL
Timer Enable Register. If TIMER
is set, the Bus Timer Register,
CSR82, is enabled. If TIMER is
set, CSR82 must be written with
a value. If TIMER is cleared, the
Bus Timer Register is disabled.
This bit indicates the Receive
Collision Counter (CSR114) has
overflowed. It can be cleared by
writing a 1 to this bit. Also cleared
by RESET or setting the STOP
bit. Writing a 0 has no effect.
TIMER is cleared by RESET.
4
3
RCVCCOM
TXSTRT
Receive Collision Counter Over-
flow Mask.
Disable Transmit Polling. If
DPOLL is set, the Buffer Man-
agement Unit will disable
transmit polling. Likewise, if
DPOLL is cleared, automatic
transmit polling is enabled. If
DPOLL is set, TDMD bit in CSR0
must be periodically set in order
to initiate a manual poll of a trans-
mit descriptor. Transmit descrip-
tor polling will not take place if
TXON is reset.
If RCVCCOM is set, RCVCCO
will not set INTR in CSR0.
RCVCCOM is set by RESET and
is not affected by STOP.
Transmit Start status is set when-
ever
PCnet-ISA+
controller
begins trans- mission of a frame.
When TXSTRT is set, IRQ is as-
serted if IENA = 1 and the mask
bit TXSTRTM (CSR4.2) is clear.
DPOLL is cleared by RESET.
TXSTRT is set by the MAC Unit
and cleared by writing a “1”, set-
ting RESET or setting the STOP
bit. Writing a “0” has no effect.
11 APAD_XMT
Auto Pad Transmit. When set,
APAD_XMT enables the auto-
matic padding feature. Transmit
frames will be padded to extend
them to 64 bytes, including FCS.
The FCS is calculated for the en-
tire frame (including pad) and
appended after the pad field.
APAD_XMT will override the pro-
gramming of the DXMTFCS bit
(CSR15.3).
2
1
TXSTRTM
Transmit
Start
Mask.
If
TXSTRTM is set, the TXSTRT bit
in CSR4 will be masked and will
not set INTR flag in CSR0.
TXS-TRTM is set by RESET and
is not affected by STOP.
JAB
Jabber Error is set when the
PCnet-ISA+ controller Twisted-
pair MAU function exceeds an
allowed transmission limit. Jab-
ber is set by the TMAU cell and
can only be asserted in
10BASE-T mode.
APAD_ XMT is reset by activa-
tion of the RESET pin.
10 ASTRP_RCV
ASTRP_RCV enables the auto-
matic pad stripping feature. The
pad and FCS fields will be
stripped from receive frames and
not placed in the FIFO.
When JAB is set, IRQ is asserted
if IENA = 1 and the mask bit
JABM (CSR4.4) is clear.
ASTRP_ RCV is reset by activa-
tion of the RESET pin.
9
MFCO
Missed Frame Counter Overflow
Interrupt.
1-553
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AMD
P R E L I M I N A R Y
The JAB bit can be reset even if CSR9: Logical Address Filter, LADRF[31:16]
the jabber condition is still
present.
Bit
Name
Description
JAB is set by the TMAU circuit
and cleared by writing a “1”. Writ-
ing a “0” has no effect. JAB is also
cleared by RESET or setting the
STOP bit.
15-0 LADRF[31:16] Logical
Address
Filter,
LADRF[31:16]. Undefined until
initialized either automatically by
loading the initialization block or
directly by an I/O write to this
register.
0
JABM
Jabber Error Mask. If JABM is
set, the JAB bit in CSR4 will be
masked and will not set INTR flag
in CSR0.
Read/write accessible only when
STOP bit is set.
JABM is set by RESET and is not
affected by STOP.
CSR10: Logical Address Filter, LADRF[47:32]
CSR6: RCV/XMT Descriptor Table Length
Bit
Name
Description
Bit
Name
Description
15-0 LADRF[47:32] Logical
Address
Filter,
LADRF[47:32]. Undefined until
initialized either automatically by
loading the initialization block or
directly by an I/O write to this
register.
15-12 TLEN
Contains a copy of the transmit
encoded ring length (TLEN) field
read from the initialization block
during PCnet-ISA+ controller in-
itialization. This field is written
during the PCnet-ISA+ controller
initialization routine.
Read/write accessible only when
STOP bit is set.
Read accessible only when
STOP bit is set. Write operations
have no effect and should not be
performed. TLEN is only defined
after initialization.
CSR11: Logical Address Filter, LADRF[63:48]
Bit
Name
Description
15-0 LADRF[63:48] Logical
Address
Filter,
11-8 RLEN
Contains a copy of the receive
encoded ring length (RLEN) read
from the initialization block dur-
ing PCnet-ISA+ controller initiali-
zation. This field is written during
the PCnet-ISA+ controller initiali-
zation routine.
LADRF[63:48]. Undefined until
initialized either automatically by
loading the initialization block or
directly by an I/O write to this
register.
Read/write accessible only when
STOP bit is set.
Read accessible only when
STOP bit is set. Write operations
have no effect and should not be
performed. RLEN is only defined
after initialization.
CSR12: Physical Address Register, PADR[15:0]
Bit
Name
Description
7-0
RES
Reserved locations. Read as
zero. Write operations should not
be performed.
15-0 PADR[15:0]
Physical Address Register,
PADR[15:0]. Undefined until in-
itialized either automatically by
loading the initialization block or
directly by an I/O write to this
register. The PADR bits are
transmitted PADR[0] first and
PADR[47] last.
CSR8: Logical Address Filter, LADRF[15:0]
Bit Name Description
15-0 LADRF[15:0] Logical Address Filter, LADRF
[15:0]. Undefined until initialized
Read/write accessible only when
STOP bit is set.
either automatically by loading
the initialization block or directly
by an I/O write to this register.
Read/write accessible only when
STOP bit is set.
1-554
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P R E L I M I N A R Y
CSR13: Physical Address Register, PADR[31:16]
Bit Name Description
AMD
node ID) of the PCnet-ISA+ con-
troller will be disabled. Frames
addressed to the nodes individ-
ual physical address will not be
recognized (although the frame
may be accepted by the EADI
mechanism).
15-0 PADR[31:16] Physical Address Register,
PADR[31:16]. Undefined until in-
itialized either automatically by
loading the initialization block or
directly by an I/O write to this
register. The PADR bits are
transmitted PADR[0] first and
PADR[47] last.
Read/write accessible only when
STOP bit is set.
12 DLNKTST
Disable Link Status. When
DLNKTST = “1”, monitoring of
Link Pulses is disabled. When
DLNKTST = “0”, monitoring of
Link Pulses is enabled. This bit
only has meaning when the
10BASE-T network interface is
selected.
Read/write accessible only when
STOP bit is set.
CSR14: Physical Address Register, PADR[47:32]
Bit
Name
Description
Read/write accessible only when
STOP bit is set.
15-0 PADR[47:32] Physical Address Register,
PADR[47:32]. Undefined until in-
itialized either automatically by
loading the initialization block or
directly by an I/O write to this
register. The PADR bits are
transmitted PADR[0] first and
PADR[47] last.
11
DAPC
Disable Automatic Polarity Cor-
rection. When DAPC = “1”, the
10BASE-T receive polarity rever-
sal algorithm is disabled.
Likewise, when DAPC = “0”, the
polarity reversal algorithm is en-
abled.
Read/write accessible only when
STOP bit is set.
This bit only has meaning when
the 10BASE-T network interface
is selected.
CSR15: Mode Register
Read/write accessible only when
STOP bit is set.
Bit
Name
Description
10 MENDECL
MENDEC Loopback Mode. See
the description of the LOOP bit in
CSR15.
This register’s fields are loaded
during the PCnet-ISA+ controller
initialization routine with the cor-
responding Initialization Block
values. The register can also be
loaded directly by an I/O write.
Activating the RESET pin clears
all bits of CSR15 to zero.
Read/write accessible only when
STOP bit is set.
9
LRT/TSEL
LRT
Low Receive Threshold (T-MAU
Mode only)
Transmit Mode Select (AUI
Mode only)
15
14
PROM
Promiscuous Mode.
When PROM = “1”, all incoming
receive frames are accepted.
Low Receive Threshold. When
LRT = “1”, the internal twisted
pair receive thresholds are re-
duced by 4.5 dB below the
standard 10BASE-T value (ap-
proximately 3/5) and the
unsquelch threshold for the RXD
circuit will be 180-312 mV peak.
Read/write accessible only when
STOP bit is set.
DRCVBC
DisableReceiveBroadcast.When
set, disables the PCnet-ISA+
controller from receiving broad-
cast messages. Used for
protocols that do not support
broadcast addressing, except as
a function of multicast. DRCVBC
is cleared by activation of the
RESET pin (broadcast mes-
sages will be received).
When LRT = “0”, the unsquelch
threshold for the RXD circuit will
be the standard 10BASE-T
value, 300-520 mV peak.
In either case, the RXD circuit
post squelch threshold will be
one half of the unsquelch
threshold.
Read/write accessible only when
STOP bit is set.
This bit only has meaning when
the 10BASE-T network interface
is selected.
13
DRCVPA
Disable Receive Physical Ad-
dress. When set, the physical
address detection (Station or
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Read/write accessible only when 4
FCOLL
Force Collision. This bit allows
the collision logic to be tested.
PCnet-ISA+ controller must be in
internal loopback for FCOLL to
be valid. If FCOLL = “1”, a colli-
sion will be forced during
loopback transmission attempts;
a Retry Error will ultimately re-
sult. If FCOLL = “0”, the Force
Collision logic will be disabled.
STOP bit is set. Cleared by
RESET.
TSEL
Transmit Mode Select. TSEL
controls the levels at which the
AUI drivers rest when the AUI
transmit port is idle. When TSEL
= 0, DO+ and DO- yield “zero” dif-
ferential to operate transformer
coupled loads (Ethernet 2 and
802.3). When TSEL = 1, the DO+
idles at a higher value with re-
spect to DO- , yielding a logical
HIGH state (Ethernet 1).
Read/write accessible only when
STOP bit is set.
3
DXMTFCS
Disable Transmit CRC (FCS).
When DXMTFCS = 0, the trans-
mitter will generate and append a
FCS to the transmitted frame.
When DXMTFCS = 1, the FCS
logic is allocated to the receiver
and no FCS is generated or sent
with the transmitted frame.
This bit only has meaning when
the AUI network interface is
selected. Not available under
Auto-Select Mode.
Read/write accessible only when
STOP bit is set. Cleared by
RESET.
See also the ADD_FCS bit in
TMD1. If DXMTFCS is set, no
FCS will be generated. If both
DXMTFCS is set and ADD_FCS
is clear for a particular frame, no
FCS will be generated. If
ADD_FCS is set for a particular
frame, the state of DXMTFCS is
ignored and a FCS will be ap-
pended on that frame by the
transmit circuitry.
8-7 PORTSEL
[1:0]
Port Select bits allow for software
controlled selection of the net-
work medium. PORTSEL active
only when Media-Select Bit set to
0 in ISACSR2.
Read/write accessible only when
STOP bit is set. Cleared by
RESET.
The network port configuration
are as follows:
In loopback mode, this bit deter-
mines if the transmitter appends
FCS or if the receiver checks the
FCS.
PORTSEL[1:0]
Network Port
AUI
0 0
0 1
1 0
1 1
This bit was called DTCR in the
LANCE (Am7990).
10BASE-T
GPSI*
Read/write accessible only when
STOP bit is set.
Reserved
*Refer to the section on General Purpose Serial Interface for
detailed information on accessing GPSI.
2
LOOP
Loopback
Enable
allows
PCnet-ISA+ controller to operate
in full duplex mode for test pur-
6
INTL
Internal Loopback. See the de-
scription of LOOP, CSR15.2.
poses. When LOOP
= “1”,
loopback is enabled. In combina-
tion with INTL and MENDECL,
various loopback modes are de-
fined as follows:
Read/write accessible only when
STOP bit is set.
5
DRTY
Disable Retry. When DRTY = “1”,
PCnet-ISA+ controller will at-
tempt only one transmission. If
DRTY = “0”, PCnet-ISA+ control-
ler will attempt to transmit 16
times before signaling a retry
error.
Read/write accessible only when
STOP bit is set.
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This register is an alias of CSR2.
Whenever this register is written,
CSR2 is updated with CSR17’s
contents.
LOOP INTL MENDECL
Loopback Mode
Non-loopback
0
1
1
X
0
1
X
X
0
External Loopback
Read/Write accessible only
when the STOP bit in CSR0 is
set. Unaffected by RESET.
Internal Loopback Include
MENDEC
1
1
1
Internal Loopback Exclude
MENDEC
CSR18-19: Current Receive Buffer Address
Bit
Name
Description
Read/write accessible only when
STOP bit is set. LOOP is cleared
by RESET.
31-24 RES
23-0 CRBA
Reserved locations. Written as
zero and read as undefined.
Contains the current receive
buffer address to which the
PCnet-ISA+ controller will store
incoming frame data.
1
DTX
Disable Transmit. If this bit is set,
the PCnet-ISA+ controller will not
access the Transmit Descriptor
Ring and, therefore, no transmis-
sions will occur. DTX = “0” will set
TXON bit (CSR0.4) after STRT
(CSR0.1) is asserted. DTX is de-
fined after the initialization block
is read.
Read/write accessible only when
STOP bit is set.
CSR20-21: Current Transmit Buffer Address
Read/write accessible only when
STOP bit is set.
Bit
Name
Description
0
DRX
Disable Receiver. If this bit is set,
the PCnet-ISA+ controller will not
access the Receive Descriptor
Ring and, therefore, all receive
frame data are ignored. DRX =
“0” will set RXON bit (CSR0.5) af-
ter STRT (CSR0.1) is asserted.
DRX is defined after the initializa-
tion block is read.
31-24 RES
23-0 CXBA
Reserved locations. Written as
zero and read as undefined.
Contains the current transmit
buffer address from which the
PCnet-ISA+ controlleristransmit-
ting.
Read/write accessible only when
STOP bit is set.
Read/write accessible only when
STOP bit is set.
CSR22-23: Next Receive Buffer Address
CSR16: Initialization Block Address Lower
Bit
Name
Description
Bit
Name
Description
31-24 RES
23-0 NRBA
Reserved locations. Written as
zero and read as undefined.
15-0
IADR
Lower 16 bits of the address of
the Initialization Block. Bit loca-
tion 0 must be zero. This register
is an alias of CSR1. Whenever
this register is written, CSR1 is
updated with CSR16’s contents.
Contains the next receive buffer
address to which the PCnet-ISA+
controller will store incoming
frame data.
Read/write accessible only when
STOP bit is set.
Read/Write accessible only
when the STOP bit in CSR0 is
set. Unaffected by RESET.
CSR24-25: Base Address of Receive Ring
CSR17: Initialization Block Address Upper
Bit
Name
Description
Bit
Name
Description
31-24 RES
23-0 BADR
Reserved locations. Written as
zero and read as undefined.
15-8
RES
Reserved locations. Written as
zero and read as undefined.
Contains the base address of the
Receive Ring.
7-0
IADR
Upper 8 bits of the address of the
Initialization Block. Bit locations
15-8 must be written with zeros.
Read/write accessible only when
STOP bit is set.
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CSR36-37: Next Next Receive Descriptor Address
CSR26-27: Next Receive Descriptor Address
Bit
Name
Description
Bit
Name
Description
31-24 RES
23-0 NRDA
Reserved locations. Written as
zero and read as undefined.
31-0 NNRDA
Contains the next next RDRE ad-
dress pointer.
Contains the next RDRE address
pointer.
Read/write accessible only when
STOP bit is set.
Read/write accessible only when
STOP bit is set.
CSR38-39: NextNextTransmitDescriptor Address
Bit
Name
Description
CSR28-29: Current Receive Descriptor Address
31-0 NNXDA
Contains the next next TDRE ad-
dress pointer.
Bit
Name
Description
Read/write accessible only when
STOP bit is set.
31-24 RES
23-0 CRDA
Reserved locations. Written as
zero and read as undefined.
Contains the current RDRE ad-
dress pointer.
CSR40-41: Current Receive Status and Byte
Count
Read/write accessible only when
STOP bit is set.
Bit
Name
Description
31-24 CRST
Current Receive Status. This
field is a copy of bits 15:8 of
RMD1 of the current receive
descriptor.
CSR30-31: Base Address of Transmit Ring
Bit
Name
Description
Read/write accessible only when
STOP bit is set.
31-24 RES
23-0 BADX
Reserved locations. Written as
zero and read as undefined.
23-12 RES
11-0 CRBC
Reserved locations. Written as
zero and read as undefined.
Contains the base address of the
Transmit Ring.
Current Receive Byte Count.
This field is a copy of the BCNT
field of RMD2 of the current re-
ceive descriptor.
Read/write accessible only when
STOP bit is set.
CSR32-33: Next Transmit Descriptor Address
Read/write accessible only when
STOP bit is set.
Bit
Name
Description
31-24 RES
23-0 NXDA
Reserved locations. Written as
zero and read as undefined.
CSR42-43: Current Transmit Status and Byte
Count
Contains the next TDRE address
pointer.
Bit
Name
Description
Read/write accessible only when
STOP bit is set.
31-24 CXST
Current Transmit Status. This
field is a copy of bits 15:8 of
TMD1 of the current transmit
descriptor.
CSR34-35: Current Transmit Descriptor Address
Read/write accessible only when
STOP bit is set.
Bit
Name
Description
23-12 RES
11-0 CXBC
Reserved locations. Written as
zero and read as undefined.
31-24 RES
23-0 CXDA
Reserved locations. Written as
zero and read as undefined.
Current Transmit Byte Count.
This field is a copy of the BCNT
field of TMD2 of the current trans-
mit descriptor.
Contains the current TDRE ad-
dress pointer.
Read/write accessible only when
STOP bit is set.
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Read/write accessible only when
AMD
polling interval of 32,768 XTAL1
periods. The POLINT value of
0000 is created during the
microcode initialization routine,
and therefore might not be seen
when reading CSR47 after
RESET.
STOP bit is set.
CSR44-45: Next Receive Status and Byte Count
Bit
Name
Description
31-24 NRST
Next Receive Status. This field is
a copy of bits 15:8 of RMD1 of the
next receive descriptor.
If the user desires to program a
value for POLLINT other than the
default, then the correct proce-
dure is to first set INIT only in
CSR0. Then, when the initializa-
tion sequence is complete, the
user must set STOP in CSR0.
Then the user may write to
CSR47 and then set STRT in
CSR0. In this way, the default
value of 0000 in CSR47 will be
overwritten with the desired user
value.
Read/write accessible only when
STOP bit is set.
23-12 RES
11-0 NRBC
Reserved locations. Written as
zero and read as undefined.
Next Receive Byte Count. This
field is a copy of the BCNT field of
RMD2 of the next receive
descriptor.
Read/write accessible only when
STOP bit is set.
Read/write accessible only when
STOP bit is set.
CSR46: Poll Time Counter
CSR48-49: Temporary Storage
Bit
Name
Description
Bit
Name
Description
15-0
POLL
Poll Time Counter. This counter
is
incremented
by
the
31-0 TMP0
Temporary Storage location.
PCnet-ISA+ controller microcode
and is used to trigger the descrip-
tor ring polling operation of the
PCnet-ISA+ controller.
Read/write accessible only when
STOP bit is set.
CSR50-51: Temporary Storage
Read/write accessible only when
STOP bit is set.
Bit
Name
Description
CSR47: Polling Interval
Bit Name
31-0 TMP1
Temporary Storage location.
Read/write accessible only when
STOP bit is set.
Description
31-16 RES
Reserved locations. Written as
zero and read as undefined.
CSR52-53: Temporary Storage
15-0 POLLINT
Polling Interval. This register
contains the time that the
PCnet-ISA+ controller will wait
between successive polling op-
erations. The POLLINT value is
expressed as the two’s comple-
ment of the desired interval,
where each bit of POLLINT rep-
resents one-half of an XTAL1
period of time. POLLINT[3:0] are
ignored. (POLINT[16] is implied
to be a one, so POLLINT[15] is
significant, and does not repre-
sent the sign of the two’s
complement POLLINT value.)
Bit
Name
Description
31-0 TMP2
Temporary Storage location.
Read/write accessible only when
STOP bit is set.
CSR54-55: Temporary Storage
Bit
Name
Description
31-0 TMP3
Temporary Storage location.
Read/write accessible only when
STOP bit is set.
The default value of this register
is 0000. This corresponds to a
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CSR64-65: Next Transmit Buffer Address
CSR56-57: Temporary Storage
Bit
Name
Description
Bit
Name
Description
31-0 TMP4
Temporary Storage location.
31-24 RES
23-0 NXBA
Reserved locations. Written as
zero and read as undefined.
Read/write accessible only when
STOP bit is set.
Contains the next transmit buffer
address
from
which
the
PCnet-ISA+ controller will trans-
mit an outgoing frame.
CSR58-59: Temporary Storage
Read/write accessible only when
STOP bit is set.
Bit
Name
Description
31-0 TMP5
Temporary Storage location.
Read/write accessible only when
STOP bit is set.
CSR66-67: Next Transmit Status and Byte Count
Bit
Name
Description
CSR60-61: Previous Transmit Descriptor Address
31-24 NXST
Next Transmit Status. This field
is a copy of bits 15:8 of TMD1 of
the next transmit descriptor.
Bit
Name
Description
Read/write accessible only when
STOP bit is set.
31-24 RES
23-0 PXDA
Reserved locations. Written as
zero and read as undefined.
23-12 RES
11-0 NXBC
Reserved locations. Written as
zero and read as undefined.
Contains the previous TDRE ad-
dress pointer. The PCnet-ISA+
controller has the capability to
stack multiple transmit frames.
AccessibleonlywhenSTOPbitis
set.
Next Transmit Byte Count. This
field is a copy of the BCNT field of
TMD2 of the next transmit
descriptor.
Read/write accessible only when
STOP bit is set.
CSR62-63: Previous Transmit Status and Byte
Count
Read/write accessible only when
STOP bit is set.
Bit
Name
Description
CSR68-69: Transmit Status Temporary Storage
31-24 PXST
Previous Transmit Status. This
field is a copy of bits 15:8 of
TMD1 of the previous transmit
descriptor.
Bit
Name
Description
31-0 XSTMP
Transmit Status Temporary Stor-
age location.
Read/write accessible only when
STOP bit is set.
Read/write accessible only when
STOP bit is set.
23-12 RES
11-0 PXBC
Reserved locations. Written as
zero and read as undefined.
CSR70-71: Temporary Storage
AccessibleonlywhenSTOPbitis
set.
Bit
Name
Description
Previous Transmit Byte Count.
This field is a copy of the BCNT
field of TMD2 of the previous
transmit descriptor.
31-0 TMP8
Temporary Storage location.
Read/write accessible only when
STOP bit is set.
Read/write accessible only when
STOP bit is set.
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CSR72: Receive Ring Counter
Bit Name Description
can be manually altered; the ac-
tual transmit ring length is
defined by the current value in
this register.
15-0 RCVRC
Receive Ring Counter location.
Contains a Two’s complement
binary number used to number
the current receive descriptor.
This counter interprets the value
in CSR76 as pointing to the first
descriptor; a two’s complement
value of -1 (FFFFh) corresponds
to the last descriptor in the ring.
Read/write accessible only when
STOP bit is set.
CSR80: Burst and FIFO Threshold Control
Bit
Name
Description
15-14 RES
Reserved locations. Read as
ones. Written as zero.
Read/write accessible only when
STOP bit is set.
13-12RCVFW[1:0]
Receive
FIFO
Watermark.
RCVFW controls the point at
which ISA bus receive DMA is re-
quested in relation to the number
of received bytes in the receive
FIFO. RCVFW specifies the
number of bytes which must be
present (once the frame has
been verified as a non-runt) be-
fore receive DMA is requested.
Note however that in order for re-
ceive DMA to be performed for a
new frame, at least 64 bytes must
have been received. This effec-
tively avoids having to react to
receive frames which are runts or
suffer a collision during the slot
time (512 bit times). If the Runt
Packet Accept feature is en-
abled, receive DMA will be
requested as soon as either the
RCVFW threshold is reached, or
a complete valid receive frame is
detected (regardless of length).
RCVFW is set to a value of 10b
(64 bytes) after RESET.
CSR74: Transmit Ring Counter
Bit
Name
Description
15-0 XMTRC
Transmit Ring Counter location.
Contains a Two’s complement
binary number used to number
the current transmit descriptor.
This counter interprets the value
in CSR78 as pointing to the first
descriptor; a two’s complement
value of -1 (FFFFh) corresponds
to the last descriptor in the ring.
Read/write accessible only when
STOP bit is set.
CSR76: Receive Ring Length
Bit Name
Description
15-0 RCVRL
Receive Ring Length. Contains
the Two’s complement of the re-
ceive descriptor ring length. This
register is initialized during the
PCnet-ISA+ controller initializa-
tion routine based on the value in
the RLEN field of the initialization
block. This register can be manu-
ally altered; the actual receive
ring length is defined by the cur-
rent value in this register.
Read/write accessible only when
STOP bit is set.
RCVFW[1:0]
Bytes Received
00
01
10
11
16
32
64
Reserved
Read/write accessible only when
STOP bit is set.
11-10XMTSP[1:0]
Transmit Start Point. XMTSP
controls the point at which pre-
amble transmission attempts
commence in relation to the num-
ber of bytes written to the
transmit FIFO for the current
transmit frame. When the entire
frame is in the FIFO, transmis-
sion will start regardless of the
value in XMTSP. XMTSP is given
a value of 10b (64 bytes) after
RESET. Regardless of XMTSP,
the FIFO will not internally over
CSR78: Transmit Ring Length
Bit Name
Description
15-0 XMTRL
Transmit Ring Length. Contains
the two’s complement of the
transmit descriptor ring length.
This register is initialized during
the
PCnet-ISA+
controller
initialization routine based on the
value in the TLEN field of the
initialization block. This register
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write its data until at least 64
number of transfers specified in
DMABR have occured.
bytes (or the entire frame if <64
bytes) have been transmitted
onto the network. This ensures
that for collisions within the slot
time window, transmit data need
not be re-written to the transmit
FIFO, and re-tries will be handled
autonomously by the MAC. This
bit is read/write accessible only
when the STOP bit is set.
Read/write accessible only when
STOP bit is set.
CSR82: Bus Activity Timer
Bit Name
Description
15-0 DMABAT
Bus Activity Timer. If the TIMER
bit in CSR4 is set, this register
contains the maximum allowable
time that the PCnet-ISA+ control-
ler will take up on the system bus
during FIFO data transfers in
each bus mastership period. The
DMABAT starts counting upon
receipt of DACK from the host
system. The DMABAT Register
does not limit the number of
XMTSP[1:0]
Bytes Written
00
01
10
11
4
16
64
112
9-8 XMTFW[1:0]
Transmit FIFO Watermark.
XMTFW specifies the point at
which transmit DMA stops,
based upon the number of write
cycles that could be performed to
the transmit FIFO without FIFO
overflow. Transmit DMA is al-
lowed at any time when the
number of write cycles specified
by XMTFW could be executed
without causing transmit FIFO
overflow. XMTFW is set to a
value of 00b (8 cycles) after hard-
transfers
transfers.
during
Descriptor
A value of zero will limit the
PCnet-ISA+ controller to one bus
cycle per mastership period. A
non-zero value is interpreted as
an unsigned number with a reso-
lution of 100 ns. For instance, a
value of 51µs would be pro-
grammed with a value of 510.
When the TIMER bit in CSR4 is
set, DMABAT is enabled and
must be initialized by the user.
The DMABAT register is unde-
fined until written.
ware
RESET.
Read/write
accessible only when STOP bit is
set.
XMTFW[1:0]
Write Cycles
When the Bus Activity Timer reg-
ister (CSR82: DMABAT) is
enabled, the PCnet-ISA+ con-
trol- ler will relinquish the bus
when either the time specified in
DMABAT has elapsed or the
number of transfers specified in
DMABR have occured. When
ENTST (CSR4.15) is asserted,
all writes to this register will auto-
matically perform a decrement
cycle.
00
01
10
11
8
16
32
Reserved
7-0
DMABR
DMA Burst Register. This regis-
ter contains the maximum
allowable number of transfers to
system memory that the Bus In-
terface will perform during a
single DMA cycle. The Burst
Register is not used to limit the
number of transfers during
Descriptor transfers. A value of
zero will be interpreted as one
transfer. During RESET a value
of 16 is loaded in the BURST reg-
ister. If DMAPLUS (CSR4.14) is
set, the DMA Burst Register is
disabled.
Read/write accessible only when
STOP bit is set.
CSR84-85: DMA Address
Bit Name
Description
31-0 DMABA
DMA Address Register.
This register contains the ad-
dress of system memory for the
current DMA cycle. The Bus In-
terface Unit controls the Address
When the Bus Activity Timer reg-
ister (CSR82: DMABAT) is
enabled, the PCnet-ISA+ control-
ler will relinquish the bus when
either the time specified in
DMABAT has elapsed or the
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Register by issuing increment
AMD
length, a Two’s complemented
value is read. The RCON register
is undefined until written.
commands to increment the
memory address for sequential
operations. The DMABA register
is undefined until the first
PCnet-ISA+ controller DMA
operation.
Read/write accessible only when
STOP bit is set.
CSR94: Transmit Time Domain Reflectometry
Count
This register has meaning only if
the PCnet-ISA+ controller is in
Bus Master Mode.
Bit
Name
Description
Read/write accessible only when
STOP bit is set.
15-10 RES
Reserved locations. Read and
written as zero.
CSR86: Buffer Byte Counter
Bit Name
9-0 XMTTDR
Time Domain Reflectometry re-
flects the state of an internal
counter that counts from the start
of transmission to the occurrence
of loss of carrier. TDR is incre-
mented at a rate of 10 MHz.
Description
15-12 RES
Reserved, Read and written with
ones.
11-0 DMABC
DMA Byte Count Register. Con-
tains the Two’s complement of
the current size of the remaining
transmit or receive buffer in
bytes. This register is incre-
mented by the Bus Interface Unit.
The DMABC register is unde-
fined until written.
Read accessible only when
STOP bit is set. Write operations
are ignored. XMTTDR is cleared
by RESET.
CSR96-97: Bus Interface Scratch Register 0
Bit
Name
Description
Read/write accessible only when
STOP bit is set.
31-0 SCR0
This register is shared between
the Buffer Management Unit and
the Bus Interface Unit. All De-
scriptor Data communications
between the BIU and BMU are
written and read through SCR0
and SCR1 registers. The SCR0
register is undefined until written.
CSR88-89: Chip ID
Bit
Name
Description
31-28
Version. This 4-bit pattern is sili-
con revision dependent.
27-12
11-1
Part number. The 16-bit code for
the PCnet-ISA+ controller is
0010001001100000b.
Read/write accessible only when
STOP bit is set.
Manufacturer ID. The 11-bit
manufacturer code for AMD is
00000000001b. This code is per
the JEDEC Publication 106-A.
CSR98-99: Bus Interface Scratch Register 1
Bit
Name
Description
0
Always a logic 1.
31-0 SCR1
This register is shared between
the Buffer Management Unit and
the Bus Interface Unit. All De-
scriptor Data communications
between the BIU and BMU are
written and read through SCR0
and SCR1 registers.
This register is exactly the same
as the Chip ID register in the
JTAG description.
CSR92: Ring Length Conversion
Bit
Name
Description
Read/write accessible only when
STOP bit is set.
15-0 RCON
Ring Length Conversion Regis-
ter. This register performs a ring
length conversion from an en-
coded value as found in the
initialization block to a Two’s
complement value used for inter-
nal counting. By writing bits
15–12 with an encoded ring
CSR104-105: SWAP
Bit
Name
Description
31-0 SWAP
This register performs word and
byte swapping depending upon if
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P R E L I M I N A R Y
32-bit or 16-bit internal write op- CSR114: Receive Collision Count
erations are performed. This
register is used internally by the
BIU/BMU as a word or byte
swapper. The swap register can
perform 32-bit operations that
the PC can not; the register is ex-
ternally accessible for test
reasons only. CSR104 holds the
lower 16 bits and CSR105 holds
the upper 16 bits.
Bit
Name
Description
15-0 RCVCC
Counts the number of Receive
collisions seen, regular and late.
This register is always readable
and is cleared by STOP.
A write to this register performs
an increment when the ENTST
bit in CSR4 is set.
The swap function is defined as
follows:
When RCVCC is all 1’s (65535)
and a receive collision occurs,
RCVCC increments to 0 and sets
RCVCC0 bit (CSR4.5)
Internal Write
Operation
SWAP Register Result
32-Bit word
SRC[31:16]
SRC[15:0]
→
→
SWAP[15:0]
SWAP[31:16]
CSR124: Buffer Management Unit Test
Lower 16-Bit
(CSR104)
SRC[15:8]
SRC[7:0]
→
→
SWAP[ 7: 0]
SWAP[15:8]
Bit
Name
Description
This register is used to place the
BMU/BIU into various test modes
to support Test/Debug. This reg-
ister is writeable when the
ENTST bit in CSR4 is set.
Read/write accessible only when
STOP bit is set.
CSR108-109: Buffer Management Scratch
Bit
Name
Description
15-5
4
RES
Reserved locations. Written as
zero and read as undefined.
31-0 BMSCR
The Buffer Management Scratch
register is used for assembling
Receive and Transmit Status.
This register is also used as the
primary scan register for Buffer
GPSIEN
This
mode
places
the
PCnet-ISA+ controller in the
GPSI Mode. This mode will
reconfigure the External Address
Pins so that the GPSI port is ex-
posed. This allows bypassing the
MENDEC- TMAU logic. This bit
should only be set if the external
logic supports GPSI operation.
Damage to the device may occur
in a non-GPSI configuration. Re-
fer to the GPSI section.
Management
Test
Modes.
BMSCR register is undefined un-
til written.
Read/write accessible only when
STOP bit is set.
CSR112: Missed Frame Count
3
RPA
RES
Runt Packet Accept. This bit
forces the CORE receive logic to
accept Runt Packets. This bit al-
lows for faster testing.
Bit
Name
Description
15-0
MFC
Counts the number of missed
frames.
2-0
For test purposes only. Reserved
locations. Written as zero and
read as undefined.
This register is always readable
and is cleared by STOP.
A write to this register performs
an increment when the ENTST
bit in CSR4 is set.
ISA Bus Configuration Registers
The ISA Bus Data Port (IDP) allows access to registers
which are associated with the ISA bus. These registers
are called ISA Bus Configuration Registers (ISACSRs),
and are indexed by the value in the Register Address
Port(RAP). ThetablebelowdefinestheISACSRswhich
When MFC is all 1’s (65535) and
a missed frame occurs, MFC in-
crements to 0 and sets MFC0 bit
(CSR4.9).
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Am79C961
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can be accessed. All registers are 16 bits. The “Default” ISACSR2: Miscellaneous Configuration
Bit Name Description
AMD
value is the value in the register after reset and is
hexadecimal.
15 MODE_STATUS Mode Status. This is a read-only
register which indicates whether
the PCnet-ISA+ is configured in
shared memory mode. A set
condition indicates shared-
memory while a clear condition
indicates bus-master condition.
Refer to the section “LEDs” for information on LED
control logic.
ISACSR MNEMONIC
Default
Name
0
1
2
3
MSRDA
MSWRA
MC
0005H
Master Mode
Read Active
0005H
0002H
8000H*
Master Mode
Write Active
14 TMAU_LOOPE 10BASE-T External Loop back
Enable. This bit is usable only
when10BASE-TisselectedAND
PCnet-ISA+ is in external loop
back. External loop back is set
during initialization via the MODE
register. When TMAU_LOOPE
is set, a board level test is en-
abled via a loop back clip which
ties the 10BASE-T RJ45 transmit
pair to the receiver pair. This will
test all external components (i.e.
transformers, resistors, etc.) of
the 10BASE-T path. TMAU_
LOOPE assertion is not suitable
for live network tests. When
TMAU_LOOPE is deasserted,
default condition, external loop
back in 10BASE-T is allowed.
Miscellaneous
Configuration
EC
EEPROM
Configuration
4
5
6
7
8
LED0
LED1
LED2
LED3
SC
0000H
0084H
0008H
0090H
0000H
Link Integrity
Default: RCV
Default: RCVPOL
Default: XMT
Software
Configuration
(Read-Only
register)
*This value can be 0000H for systems that do not support
EEPROM option.
13
Reserved
Written with zero and read as un-
defined.
ISACSR0: Master Mode Read Active
12
SLOT_ID
Slot Identification. This is a read-
only register bit which indicates if
PCnet-ISA+ is either in an 16 or 8
bit slot. Reading a one indicates
an 8 bit slot. Zero indicates a
16-bit slot. (SLOT_ID bit is not
valid after the INIT bit is set in
CSR0.)
Bit
Name
Description
3-0
MSRDA
This register is used to tune the
MEMR command signal active
time. The value stored in MSRDA
defines the number of 50 ns peri-
ods that the command signal is
active. The default value of 5h in-
dicates 250 ns pulse widths. A
value of 0 or 1 will generate 50 ns
wide commands.
11 ISA_PROTECT ISA Protect. When set, the
ISACSR’s 0-2 and 4-7 are pro-
tected from being written over by
software drivers. When ISA_
PROTECT is cleared, ISACSR’s
0-7 are allowed to be written over
by software and reset by reading
the Software reset I/O location.
(Default is zero)
15-4
RES
Reserved locations. Written as
zero and read as undefined.
ISACSR1: Master Mode Write Active
Bit
Name
Description
10 EISA_DECODE EISA Decode. This control bit al-
lows EISA product identifier
3-0 MSWRA
This register is used to tune the
MEMW command signal active
time. The value stored in
MSWRA defines the number of
50 ns periods that the command
signal is active. The default value
of 5h indicates 250 ns pulse
widths. A value of 0 or 1 will gen-
erate 50 ns wide commands.
registers 12-bit decode xC80 -
xC83 (4 Bytes). Default is zero.
9
P&P_ACT
Plug and Play Active. When this
bit is set, PCnet-ISA+ will become
active after serially reading the
EEPROM. If check sum failure
exist, PCnet-ISA+ will not
beome active and alternate
15-4
RES
Reserved locations. Written as
zero and read as undefined.
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Am79C961
AMD
P R E L I M I N A R Y
access method to Plug and Play 3 EADISEL
EADI Select. Enables EADI
match mode.
registers will occur. Default is
zero.
When EADI mode is selected,
thepinsnamedLED1, LED2, and
LED3 change in function while
LED0 continues to indicate
10BASE-T Link Status.
8
APWEN
Address PROM Write Enable. It
is reset to zero by RESET. When
asserted, this pin allows write ac-
cess to the internal Address
PROM RAM. APWEN is used
also to protect the Flash device
from write cycles. When pro-
gramming of the Flash device is
required, the APWEN bit needs
to be set. When reset, this pin
protects the internal Address
PROM RAM, and external Flash
device from being overwritten.
LED
EADI Function
SF/BD
1
2
3
SRD
SRDCLK
2
AWAKE
Auto-Wake. If AWAKE = “1”, the
10BASE-T receive circuitry is ac-
tive during sleep and listens for
Link Pulses. LED0 indicates Link
Status and goes active if the
10BASE-T port comes of out of
“link fail” state. This LED0 pin can
be used by external circuitry to
re-enable the PCnet-ISA+ con-
troller and/or other devices.
7
6
EISA_LVL
DSDBUS
EISA Level. This bit is a read-
only register. It indicates if the
level or edge sensitive interrupts
have been selected. A set condi-
tion indicates level sensitive
interrupts. A clear condition indi-
cates ISA edge.
Disable Staggered Data Bus.
When this bit is a zero, the data
bus driver timing is staggered
from the address bus driver tim-
ing in Bus Master mode. When
this bit is a one, the data bus is
not staggered. It is similar to the
PCnet-ISA (Am79C960) timing.
This bit is reset to zero. For most
applications, this bit should not
have to be set.
When AWAKE = “0”, the Auto-
Wake circuity is disabled. This bit
only has meaning when the
10BASE-T network interface is
selected.
1,0 MEDSEL
Media Select. It was previously
defined as ASEL (Auto Select)
and XMAUSEL (External MAU
Select) in the PCnet-ISA. They
are now combined together and
defined to be software compat-
ible with ASEL and XMAUSEL in
the PCnet-ISA (Am79C960).
5 10BASE5_SEL 10BASE5 Select. When this bit is
a one, the DC to DC converter
will be deselected via the
DXCVR pin. When 10BASE5_
SEL is a zero, the DC to DC con-
verter will be selected via the
DXCVR bit when the AUI port is
selected to support a DC-DC
converter for 10BASE2 MUAs.
When 10BASE-T port is selected
by whatever means, DXCR pin
will high independent of the bit
selected by the driver software
mode register, MEDSEL bits,
and Auto Selection process.
10BASE5_SEL is reset to zero.
MEDSEL (1:0)
Function
Software Select (Mode Reg, CSR15)
10BASE-T Port
0 0
0 1
1 0
1 1
Auto Selection (Default)
AUI Port
ISACSR3: EEPROM Configuration
Bit
Name
Description
15 EE_VALID
EEPROM Valid. This bit is a
read-only register. When a one is
read, EE_PROM has a valid
checksum. The sum of the total
bytes reads should equals FF
hex. When a zero is read, check-
sum failed, or SHFTBUSY pin
was sampled with a zero which
indicates no EEPROM present.
4
ISAINACT
ISAINACT allows for reduced in-
active timing appropriate for
modern
ISA
machines.
ISAINACT is cleared when
RESET is asserted. When
ISAINACT is a zero, tMMR3 and
tMMW3 parameters are nomi-
nally 200 ns, which is com-
patible with EISA system. When
ISAINACT is set by writing a one,
tMMR3 and tMMW3 are nomi-
nally set to 100 ns.
14 EE_LOAD
EEPROM Load. When written
with a one, the device will load
the
EE_PROM
into
the
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PCnet-ISA+, performing self con-
ISACSR4: LED0 Status (Link Integrity)
AMD
figuration. This command must
be last write to ISACSR3 Regis-
ter. PCnet-ISA+ will not respond
to any slave commands while
loading the EE_PROM register.
EE_LOAD will be reset with a
zero after EE_PROM is read. It
takes approximately, 1.4 ms for
serial EEPROM load process to
complete.
Bit
Name
LNKST
RES
Description
ISACSR4 is a non-programma-
ble register that uses one bit to
reflect the status of the LED0 pin.
This pin defaults to twisted pair
MAU Link Status (LNKST) and is
not programmable.
15
LNKST is a read-only register bit
that indicates whether the Link
Status LED is asserted. When
LNKST is read as zero, the Link
Status LED is not asserted.
When LNKST is read as one, the
Link Status LED is asserted, indi-
cating good 10BASE-T integrity.
13–5
4
N/A
Reserved. Read and written as
zeros.
EE_EN
EEPROM Enable. When EE_EN
is written with a one, the lower
three bits of PRDB becomes SK,
DI and DO, respectively. EECS
and SHFBUSY are controlled by
the software select bits. This bit
must be written with a one to
write to or read from the
EEPROM. PCnet-ISA+ should
be in the STOP state when
EE_EN is written. When EN_EN
is cleared, DI/DO, SK, EECS and
SHFBUSY have no control.
14-0
Reserved locations. Written as
zero, read as undefined.
ISACSR5: LED1 Status
Bit
Name
Description
ISACSR5 controls the func-
tion(s) that the LED1 pin
displays. Multiple functions can
be simultaneously enabled on
this LED pin. The LED display will
indicate the logical OR of the en-
3
SHFBUSY
Shift Busy. SHFBUSY allows for
the control of the SHFBUSY pin.
When
a
one is written,
SHFBUSY goes high provided
EE_EN is a 1. When a zero is
written, SHFBUSY is held to a
zero. When EE_EN is cleared,
SHFBUSY will maintain the last
value programmed. (Refer to Bit
4 above, EE_EN, for detailed use
of this bit.)
abled
functions.
ISACSR5
defaults to Receive Status (RCV)
with pulse stretcher enabled
(PSE = 1) and is fully program-
mable.
15
LEDOUT
Indicates the current (non-
stretched) state of the function(s)
generated. Read only.
2
1
EECS
SK
EEPROM Chip Select. EECS as-
serts the chip select to the Serial
EEPROM. (Refer to Bit 4 above,
EE_EN, for detailed use of this
bit.)
14-8
7
RES
PSE
Reserved locations. Read and
written as zero.
Pulse Stretcher Enable. Extends
the LED illumination for each en-
abled function occurrence.
Serial Shift Clock. SK controls
the SK input to the Serial
EEPROM and the optional Exter-
nal Shift Logic. (Refer to Bit 4
above, EE_EN, for detailed use
of this bit.)
0 is disabled, 1 is enabled.
6
5
RES
Reserved locations. Read and
written as zero.
RCVADDM
Receive Address Match. This bit
when set allows for LED control
of only receive packets which
match internal address match.
0
DI/DO
Serial Shift Data In and Serial
Shift Data Out. When written, this
bit controls the DI input of the se-
rial EEPROM. When read, this bit
represents the DO value of the
serial EEPROM. (Refer to Bit 4
above, EE_EN, for detailed use
of this bit.)
4
XMT E
Enable Transmit Status Signal.
Indicates PCnet-ISA+ controller
transmit activity .
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P R E L I M I N A R Y
0 disables the signal, 1 enables
RVPOLE LEDXOR
Result
the signal.
0
1
1
X
0
1
10BASE-T polarity function
ignored
3
RVPOL E
Enable Receive Polarity Signal.
Enables LED pin assertion when
receive polarity is correct on the
10BASE-T port. Clearing the bit
indicates this function is to
be ignored.
LED1 pin low with “Good”
10BASE-T polarity (LED on)
LED1 pin high with “Good”
10BASE-T polarity (LED off)
13-8
7
RES
PSE
Reserved locations. Read and
written as zero.
2
1
0
RCV E
JAB E
COL E
Enable Receive Status Signal.
Indicates receive activity on the
network.
Pulse Stretcher Enable. Extends
the LED illumination for each en-
abled function occurrence.
0 disables the signal, 1 enables
the signal.
0 is disabled, 1 is enabled.
Enable Jabber Signal. Indicates
the PCnet-ISA+ controller is jab-
bering on the network.
6
5
RES
Reserved locations. Read and
written as zero.
0 disables the signal, 1 enables
the signal.
RCVADDM
Receive Address Match. This bit
when set allows for LED control
of only receive packets that
match internal address match.
Enable Collision Signal. Indi-
cates collision activity on the
network.
4
3
XMT E
Enable Transmit Status Signal.
Indicates PCnet-ISA+ controller
transmit activity .
0 disables the signal, 1 enables
the signal.
0 disables the signal, 1 enables
the signal.
ISACSR6: LED2 Status
RVPOL E
Enable Receive Polarity Signal.
Bit
Name
Description
Enables LED pin assertion when
receive polarity is correct on the
10BASE-T port. Clearing the bit
indicates this function is to
be ignored.
ISACSR6 controls the func-
tion(s) that the LED2 pin
displays. Multiple functions can
be simultaneously enabled on
this LED pin. The LED display will
indicate the logical OR of the en-
2
1
0
RCV E
JAB E
COL E
Enable Receive Status Signal.
Indicates receive activity on the
network.
abled
functions.
ISACSR6
0 disables the signal, 1 enables
the signal.
defaults to twisted pair MAU Re-
ceive Polarity (RCVPOL) with
pulse stretcher enabled (PSE =
1) and is fully programmable.
Enable Jabber Signal. Indicates
the PCnet-ISA+ controller is jab-
bering on the network.
15
14
LEDOUT
LEDXOR
Indicates the current (non-
stretched) state of the function(s)
generated. Read only.
0 disables the signal, 1 enables
the signal.
This bit when set causes LED2 to
be an active high signal when as-
serted. When this bit is cleared,
LED2 will be active low when
asserted.
Enable Collision Signal. Indi-
cates collision activity on the
network.
0 disables the signal, 1 enables
the signal.
(Note: This bit when used in con-
junction with the RVPOLE bit (Bit
3) of ISACSR5, ISACSR6, and
ISACSR7canbeusedtocreatea
“Polarity Bad” LED.)
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ISACSR7: LED3 Status
ISACSR8: Software Configuration Register
(Read-Only Register)
Bit
Bit
Name
Description
Description
ISACSR7 controls the func-
tion(s) that the LED3 pin
displays. Multiple functions can
be simultaneously enabled on
this LED pin. The LED display will
indicate the logical OR of the
enabled functions. ISACSR7 de-
faults to Transmit Status (XMT)
with pulse stretcher enabled
(PSE = 1) and is fully program-
mable.
15–12
11–8
7–4
3
Read-only image of SR_AM(3:0) of P&P
register 0x48 - 0x49.
Read-only image of BP_AM(3:0) of P&P
register 0x40 - 0x41.
Read-only image of IRQSEL(3:0) of P&P
register 0x70.
Reserved, written with zero,
read as undefined.
2–0
Read-only image of DMASEL(2:0) of
P&P register 0x74.
15
LEDOUT
Indicates the current (non-
stretched) state of the function(s)
generated. Read only.
Initialization Block
The figure below shows the Initialization Block memory
configuration. Note that the Initialization Block must be
based on a word (16-bit) boundary.
14-8
7
RES
PSE
Reserved locations. Read and
written as zero.
Pulse Stretcher Enable. Extends
the LED illumination for each en-
abled function occurrence.
Bits
15–12
Bits
11–8
Bits
7–4
Bits
3–0
Address
IADR+00
IADR+02
IADR+04
IADR+06
IADR+08
IADR+10
IADR+12
IADR+14
IADR+16
IADR+18
IADR+20
IADR+22
0 is disabled, 1 is enabled.
MODE 15-00
PADR 15-00
PADR 31-16
PADR 47-32
LADRF 15-00
LADRF 31-16
LADRF 47-32
LADRF 63-48
RDRA 15-00
6
5
RES
Reserved locations. Read and
written as zero.
RCVADDM
Receive Address Match. This bit
when set allows for LED control
of only receive packets that
match internal address match.
4
XMT E
Enable Transmit Status Signal.
Indicates PCnet-ISA+ controller
transmit activity .
0 disables the signal, 1 enables
the signal.
Enable Receive Polarity Signal.
RLEN
TLEN
RES
TDRA 15-00
RES TDRA 23-16
RDRA 23-16
3
2
RVPOL E
RCV E
Enables LED pin assertion when
receive polarity is correct on the
10BASE-T port. Clearing the bit
indicates this function is to be
ignored.
RLEN and TLEN
Enable Receive Status Signal.
Indicates receive activity on the
network.
The TLEN and RLEN fields in the initialization block are
3 bits wide, occupying bits 15,14, and 13, and the value
in these fields determines the number of Transmit and
Receive Descriptor Ring Entries (DRE) which are used
in the descriptor rings. Their meaning is as follows:
0 disables the signal, 1 enables
the signal.
1
0
JAB E
COL E
Enable Jabber Signal. Indicates
the PCnet-ISA+ controller is jab-
bering on the network.
0 disables the signal, 1 enables
the signal.
Enable Collision Signal. Indi-
cates collision activity on the
network.
0 disables the signal, 1 enables
the signal.
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Am79C961
AMD
R/TLEN
P R E L I M I N A R Y
determine if the message is actually intended for the
# of DREs
nodebycomparingthedestinationaddressofthestored
message with a list of acceptable logical addresses.
000
001
010
011
100
101
110
111
1
2
If the Logical Address Filter is loaded with all zeroes and
promiscuous mode is disabled, all incoming logical ad-
dresses except broadcast will be rejected.
4
8
16
32
64
128
The Broadcast address, which is all ones, does not go
through the Logical Address Filter and is handled as
follows:
1) If the Disable Broadcast Bit is cleared, the
broadcast address is accepted.
If a value other than those listed in the above table is de-
sired, CSR76 and CSR78 can be written after
initialization is complete. See the description of the ap-
propriate CSRs.
2) If the Disable Broadcast Bit is set and promiscuous
mode is enabled, the broadcast address is
accepted.
3) If the Disable Broadcast Bit is set and promiscous
modeisdisabled, thebroadcastaddressisrejected.
RDRA and TDRA
TDRA and RDRA indicate where the transmit and re-
ceive descriptor rings, respectively, begin. Each DRE
must be located on an 8-byte boundary.
If external loopback is used, the FCS logic must be allo-
cated to the receiver (by setting the DXMTFCS bit in
CSR15, and clearing the ADD_FCS bit in TMD1) when
using multicast addressing.
LADRF
TheLogicalAddressFilter(LADRF)isa64-bitmaskthat
is used to accept incoming Logical Addresses. If the first
bit in the incoming address (as transmitted on the wire)
is a “1”, the address is deemed logical. If the first bit is a
“0”, it is a physical address and is compared against the
physical address that was loaded through the initializa-
tion block.
PADR
This 48-bit value represents the unique node address
assigned by the IEEE and used for internal address
comparison. PADR[0] is the first address bit transmitted
on the wire, and must be zero. The six-hex-byte nomen-
clature used by the IEEE maps to the PCnet-ISA+
controller PADR register as follows: the first byte com-
prises PADR[7:0], with PADR[0] being the least
significant bit of the byte. The second IEEE byte maps to
PADR[15:8], again from LSbit to MSbit, and so on. The
sixth byte maps to PADR[47:40], the LSbit being
PADR[40].
A logical address is passed through the CRC generator,
producing a 32-bit result. The high order 6 bits of the
CRC are used to select one of the 64 bit positions in the
Logical Address Filter. If the selected filter bit is set, the
address is accepted and the frame is placed into
memory.
MODE
The Logical Address Filter is used in multicast address-
ing schemes. The acceptance of the incoming frame
based on the filter value indicates that the message may
be intended for the node. It is the node’s responsibility to
The mode register in the initialization block is copied into
CSR15 and interpreted according to the description of
CSR15.
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32-Bit Resultant CRC
26
Received Message
Destination Address
0
31
47
1
0
1
CRC
GEN
Logical
Address
Filter
(LADRF)
63
0
SEL
64
MUX
MATCH
MATCH = 1: Packet Accepted
MATCH = 0: Packet Rejected
18183B-22
6
Address Match Logic
13
FRAM
FRAMING ERROR indicates
that the incoming frame con-
tained a non-integer multiple of
eight bits and there was an FCS
error. If there was no FCS error
on the incoming frame, then
FRAM will not be set even if there
was a non integer multiple of
eight bits in the frame. FRAM is
not valid in internal loopback
mode. FRAM is valid only when
ENP is set and OFLO is not.
FRAM is written by the
PCnet-ISA+ controller.
Receive Descriptors
The Receive Descriptor Ring Entries (RDREs) are com-
posed of four receive message fields (RMD0-3).
Together they contain the following information:
■ The address of the actual message data buffer in
user (host) memory
■ The length of that message buffer
■ Status information indicating the condition of the
buffer. The eight most significant bits of RMD1
(RMD1[15:0]) are collectively termed the STATUS
of the receive descriptor.
12
OFLO
OVERFLOW error indicates that
the receiver has lost all or part of
the incoming frame, due to an in-
ability to store the frame in a
memory buffer before the inter-
nal FIFO overflowed. OFLO is
valid only when ENP is not set.
OFLO is written by the
PCnet-ISA+ controller.
RMD0
Holds LADRF [15:0]. This is combined with HADR [7:0]
in RMD1 to form the 24-bit address of the buffer pointed
to by this descriptor table entry. There are no restrictions
on buffer byte alignment or length.
RMD1
Bit
Name
Description
11
10
CRC
CRC indicates that the receiver
has detected a CRC (FCS) error
on the incoming frame. CRC is
valid only when ENP is set and
OFLO is not. CRC is written by
the PCnet-ISA+ controller.
15
OWN
This bit indicates that the de-
scriptor entry is owned by the
host (OWN=0) or by the
PCnet-ISA+ controller (OWN=1).
The PCnet-ISA+ controller clears
the OWN bit after filling the buffer
pointed to by the descriptor entry.
The host sets the OWN bit after
emptying the buffer. Once the
PCnet-ISA+ controller or host has
BUFF
BUFFER ERROR is set any time
the PCnet-ISA+ controller does
not own the next buffer while data
chaining a received frame. This
can occur in either of two ways:
relinquished ownership of
buffer, it must not change any
field in the descriptor entry.
a
1) The OWN bit of the next
buffer is zero
2) FIFO overflow occurred
before the PCnet-ISA+
controller polled the next
descriptor
14
ERR
ERR is the OR of FRAM, OFLO,
CRC, or BUFF. ERR is written by
the PCnet-ISA+ controller.
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If a Buffer Error occurs, an Over-
Transmit Descriptors
flow Error may also occur
internally in the FIFO, but will not
be reported in the descriptor
status entry unless both BUFF
and OFLO errors occur at the
same time. BUFF is written by
the PCnet-ISA+ controller.
TheTransmitDescriptorRingEntries(TDREs)arecom-
posed of four transmit message fields (TMD0-3).
Together they contain the following information:
■ The address of the actual message data buffer in
user or host memory
■ The length of the message buffer
9
STP
START OF PACKET indicates
that this is the first buffer used by
the PCnet-ISA+ controller for this
frame. It is used for data chaining
buffers. STP is written by the
PCnet-ISA+ controller in normal
operation. In SRPINT Mode
(CSR3.5 set to 1) this bit is writ-
ten by the driver.
■ Status information indicating the condition of the
buffer. The eight most significant bits of TMD1
(TMD1[15:8]) are collectively termed the STATUS
of the transmit descriptor.
Note that bit 13 of TMD1, which was formerly a reserved
bit in the LANCE (Am7990), is assigned a new meaning,
ADD_FCS.
8
ENP
END OF PACKET indicates that
this is the last buffer used by the
PCnet-ISA+ controller for this
frame. It is used for data chaining
buffers. If both STP and ENP are
set, the frame fits into one buffer
and there is no data chaining.
ENP is written by the PCnet-ISA+
controller.
TMD0
Holds LADR [15:0]. This is combined with HADR [7:0] in
TMD1 to form a 24-bit address of the buffer pointed to by
this descriptor table entry. There are no restrictions on
buffer byte alignment or length.
TMD1
7-0
HADR
The HIGH ORDER 8 address
bits of the buffer pointed to by this
descriptor. This field is written by
the host and is not changed by
the PCnet-ISA+ controller.
Bit
Name
Description
15
OWN
This bit indicates that the de-
scriptor entry is owned by the
host (OWN=0) or by the
PCnet-ISA+ controller (OWN=1).
The host sets the OWN bit after
filling the buffer pointed to by the
descriptor entry. The PCnet-ISA+
controller clears the OWN bit af-
ter transmitting the contents of
the buffer. Both the PCnet-ISA+
controller and the host must not
alter a descriptor entry after it has
relinquished ownership.
RMD2
Bit
Name
Description
15-12 ONES
MUST BE ONES. This field is
written by the host and un-
changed by the PCnet-ISA+
controller.
11-0 BCNT
BUFFER BYTE COUNT is the
length of the buffer pointed to by
this descriptor, expressed as the
two’s complement of the length
of the buffer. This field is written
by the host and is not changed by
the PCnet-ISA+ controller.
14
ERR
ERR is the OR of UFLO, LCOL,
LCAR, or RTRY. ERR is written
by the PCnet-ISA+ controller.
This bit is set in the current de-
scriptor when the error occurs,
and therefore may be set in any
descriptor of a chained buffer
transmission.
RMD3
Bit
Name
Description
13 ADD_FCS
ADD_FCS dynamically controls
the generation of FCS on a frame
by frame basis. It is valid only if
the STP bit is set. When
ADD_FCS is set, the state of
DXMTFCS is ignored and trans-
mitter FCS generation is
activated. When ADD_FCS = 0,
FCS generation is controlled by
DXMTFCS. ADD_FCS is written
15-12 RES
11-0 MCNT
RESERVED and read as zeros.
MESSAGE BYTE COUNT is the
length in bytes of the received
message, expressed as an un-
signed binary integer. MCNT is
valid only when ERR is clear and
ENP is set. MCNT is written by
the PCnet-ISA+ controller and
cleared by the host.
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AMD
by the host, and unchanged by
TMD2
Bit
the PCnet-ISA+ controller. This
was a reserved bit in the LANCE
(Am7990).
Name
Description
15-12 ONES
MUST BE ONES. This field is
written by the host and un-
changed by the PCnet-ISA+
controller.
12
11
MORE
ONE
MORE indicates that more than
one re-try was needed to trans-
mit a frame. MORE is written by
the PCnet-ISA+ controller. This
bit has meaning only if the ENP
or the ERR bit is set.
11-0 BCNT
BUFFER BYTE COUNT is the
length of the buffer pointed to by
this descriptor, expressed as the
two’s com- plement of the length
of the buffer. This is the number
of bytes from this buffer that will
be transmitted by the PCnet-
ISA+ controller. This field is
written by the host and is not
changed by the PCnet-ISA+
controller. There are no minimum
buffer size restrictions. Zero
length buffers are allowed for
protocols which require it.
ONE indicates that exactly one
re-try was needed to transmit a
frame. ONE flag is not valid when
LCOL is set. ONE is written by
the PCnet-ISA+ controller. This
bit has meaning only if the ENP
or the ERR bit is set.
10
DEF
DEFERRED indicates that the
PCnet-ISA+ controller had to de-
fer while trying to transmit a
frame. This condition occurs if
the channel is busy when the
PCnet-ISA+ controller is ready to
transmit. DEF is written by the
PCnet-ISA+ controller. This bit
has meaning only if the ENP or
ERR bits are set.
TMD3
Bit
Name
Description
15
BUFF
BUFFER ERROR is set by the
PCnet-ISA+ controller during
9
STP
START OF PACKET indicates
that this is the first buffer to be
used by the PCnet-ISA+ control-
ler for this frame. It is used for
data chaining buffers. The STP
bit must be set in the first buffer of
the frame, or the PCnet-ISA+
controller will skip over the de-
scriptor and poll the next
descriptor(s) until the OWN and
STP bits are set.
transmission
when
the
PCnet-ISA+ controller does not
find the ENP flag in the current
buffer and does not own the next
buffer. This can occur in either of
two ways:
1) The OWN bit of the next
buffer is zero.
2) FIFO underflow occurred
before the PCnet-ISA+
controller obtained the
next STATUS byte
STP is written by the host and is
not changed by the PCnet-ISA+
controller.
(TMD1[15:8]).
8
ENP
END OF PACKET indicates that
this is the last buffer to be used by
the PCnet-ISA+ controller for this
frame. It is used for data chaining
buffers. If both STP and ENP are
set, the frame fits into one buffer
and there is no data chaining.
ENP is written by the host and is
not changed by the PCnet-ISA+
controller.
BUFF error will turn off the trans-
mitter (CSR0, TXON = 0). If a
Buffer Error occurs, an Under-
flow Error will also occur. BUFF is
not valid when LCOL or RTRY er-
ror is set during transmit data
chaining. BUFF is written by the
PCnet-ISA+ controller.
14
UFLO
UNDERFLOW ERROR indi-
cates that the transmitter has
truncated a message due to data
late from memory. UFLO indi-
cates that the FIFO has emptied
before the end of the frame was
7-0
HADR
The HIGH ORDER 8 address
bits of the buffer pointed to by this
descriptor. This field is written by
the host and is not changed by
the PCnet-ISA+ controller.
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reached. Upon UFLO error, the 10
RTRY
RETRY ERROR indicates that
the transmitter has failed after 16
attempts to successfully transmit
a message, due to repeated colli-
sions on the medium. If DRTY = 1
in the MODE register, RTRY will
set after one failed transmission
attempt. RTRY is written by the
PCnet-ISA+ controller.
transmitter is turned off (CSR0,
TXON = 0). UFLO is written by
the PCnet-ISA+ controller.
13
12
RES
RESERVED bit. The PCnet-
ISA+ controller will write this bit
with a “0”.
LCOL
LATE COLLISION indicates that
a collision has occurred after the
slot time of the channel has
elapsed. The PCnet-ISA+ con-
troller does not re-try on late
collisions. LCOL is written by the
PCnet-ISA+ controller.
09-00 TDR
TIME
DOMAIN
REFLEC-
TOMETRY reflects the state of
an internal PCnet-ISA+ controller
counter that counts at a 10 MHz
rate from the start of a transmis-
sion to the occurrence of a
collision or loss of carrier. This
value is useful in determining the
approximate distance to a cable
fault. The TDR value is written by
the PCnet-ISA+ controller and is
valid only if RTRY is set.
11
LCAR
LOSS OF CARRIER is set in AUI
mode when the carrier is lost
during an PCnet-ISA+ controller-
initiated
transmission.
The
PCnet-ISA+ controller does not
stop transmission upon loss of
carrier. It will continue to transmit
the whole frame until done.
LCAR is written by the PCnet-
ISA+ controller.
Note that 10 MHz gives very low
resolution and in general has not
been found to be particularly use-
ful. This feature is here primarily
to maintain full compatibility with
the LANCE.
In 10BASE-T mode, LCAR will
be set when the T-MAU is in link
fail state.
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Register Summary
Ethernet Controller Registers
(Accessed via RDP Port)
User
RAP Addr
Symbol
Width
Register
Comments
00
01
CSR0
CSR1
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
32-bit
32-bit
32-bit
32-bit
32-bit
32-bit
32-bit
32-bit
32-bit
32-bit
32-bit
32-bit
32-bit
32-bit
32-bit
16-bit
32-bit
32-bit
32-bit
32-bit
32-bit
32-bit
32-bit
32-bit
32-bit
Y
Y
Y
Y
Y
PCnet-ISA+ controller status
Lower IADR: maps to location 16
Upper IADR: maps to location 17
Mask Register
02
CSR2
03
CSR3
04
CSR4
Miscellaneous Register
05
CSR5
Reserved
06
CSR6
RXTX: RX/TX Encoded Ring Lengths
Reserved
07
CSR7
08
CSR8
Y
Y
Y
Y
Y
Y
Y
Y
LADR0: LADRF[15:0]
09
CSR9
LADR1: LADRF[31:16]
10
CSR10
CSR11
CSR12
CSR13
CSR14
CSR15
CSR16
CSR18
CSR20
CSR22
CSR24
CSR26
CSR28
CSR30
CSR32
CSR34
CSR36
CSR38
CSR40
CSR42
CSR44
CSR46
CSR47
CSR48
CSR50
CSR52
CSR54
CSR56
CSR58
CSR60
CSR62
LADR2: LADRF[47:32]
11
LADR3: LADRF[63:48]
12
PADR0: PADR[15:0]
13
PADR1: PADR[31:16]
14
PADR2: PADR[47:32]
15
MODE: Mode Register
16-17
18-19
20-21
22-23
24-25
26-27
28-29
30-31
32-33
34-35
36-37
38-39
40-41
42-43
44-45
46
IADR: Base Address of INIT Block
CRBA: Current RCV Buffer Address
CXBA: Current XMT Buffer Address
NRBA: Next RCV Buffer Address
BADR: Base Address of RCV Ring
NRDA: Next RCV Descriptor Address
CRDA: Current RCV Descriptor Address
BADX: Base Address of XMT Ring
NXDA: Next XMT Descriptor Address
CXDA: Current XMT Descriptor Address
Next Next Receive Descriptor Address
Next Next Transmit Descriptor Address
CRBC: Current RCV Stat and Byte Count
Y
Y
CXBC: Current XMT Status and Byte Count
NRBC: Next RCV Stat and Byte Count
POLL: Poll Time Counter
47
Y
Polling Interval
48-49
50-51
52-53
54-55
56-57
58-59
60-61
62-63
TMP0: Temporary Storage
TMP1: Temporary Storage
TMP2: Temporary Storage
TMP3: Temporary Storage
TMP4: Temporary Storage
TMP5: Temporary Storage
PXDA: Previous XMT Descriptor Address
PXBC: Previous XMT Status and Byte Count
1-575
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P R E L I M I N A R Y
Register Summary
Ethernet Controller Registers
(Accessed via RDP Port) (continued)
User
RAP Addr
Symbol
Width
Register
Comments
64-65
66-67
68-69
70-71
72
CSR64
CSR66
CSR68
CSR70
CSR72
CSR74
CSR76
CSR78
CSR80
CSR82
CSR84
CSR86
CSR88
CSR92
CSR94
32-bit
32-bit
32-bit
32-bit
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
32-bit
16-bit
32-bit
16-bit
16-bit
NXBA: Next XMT Buffer Address
NXBC: Next XMT Status and Byte Count
XSTMP: XMT Status Temporary
RSTMP: RCV Status Temporary
RCVRC: RCV Ring Counter
XMTRC: XMT Ring Counter
RCVRL: RCV Ring Length
74
76
Y
Y
Y
Y
78
XMTRL: XMT Ring Length
80
DMABR: Burst Register
82
DMABAT: Bus Activity Timer
DMABA: Address Register
84-85
86
DMABC: Byte Counter/Register
Chip ID Register
88-89
92
Y
RCON: Ring Length Conversion Register
94
XMTTDR: Transmit Time Domain
Reflectometry
96-97
98-99
104-105
108-109
112
CSR96
CSR98
32-bit
32-bit
32-bit
32-bit
16-bit
16-bit
16-bit
16-bit
SCR0: BIU Scratch Register 0
SCR1: BIU Scratch Register 1
SWAP:16-bit word/byte Swap Register
BMSCR: BMU Scratch Register
Missed Frame Count
CSR104
CSR108
CSR112
CSR114
CSR124
CSR126
Y
Y
Y
114
Receive Collision Count
BMU Test Register
124
126
Reserved
Note: Although the PCnet-ISA+ controller has many registers that can be accessed by software, most of these registers are
intended for debugging and production testing purposes only. The registers with a “Y” are the only registers that should be
accessed by network software.
1-576
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AMD
Register Summary
ISACSR—ISA Bus Configuration Registers
(Accessed via IDP Port)
RAP Addr
Mnemonic
MSRDA
MSWRA
MC
Default
0005H
0005H
0002H
8000*H
0000H
0084H
0008H
0090H
0000H
Name
0
1
2
3
4
5
6
7
8
Master Mode Read Active
Master Mode Write Active
Miscellaneous Configuration
EEPROM Configuration
LED0 Status (Link Integrity)
LED1 Status (Default: RCV)
EC
LED0
LED1
LED2
LED3
SC
LED2 Status (Default: RCVPOL)
LED3 Status (Default: XMT)
Software Configuration (Read-Only
Register)
*This value can be 0000H for systems that do not support EEPROM option
I/O Address Offset
Offset
0h
#Bytes
Register
Address PROM
16
2
10h
12h
14h
16h
RDP
2
RAP (shared by RDP and IDP)
2
Reset
IDP
2
1-577
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P R E L I M I N A R Y
SYSTEM APPLICATION
ISA Bus Interface
as address PROM, boot PROM, RAP, and RDP are in
the same location with the same semantics. An addi-
tional set of registers (ISA CSR) is available to configure
on board resources such as ISA bus timing and LED op-
eration. However, loopback frames for the PCnet-ISA+
controller must contain more than 64 bytes of data if the
Runt Packet Accept feature is not enabled; this size limi-
tationdoesnotapplytoLANCE(Am7990)basedboards
such as the NE2100 and NE1500T.
Compatibility Considerations
Although 8 MHz is now widely accepted as the standard
speed at which to run the ISA bus, many machines have
been built which operate at higher speeds with non-
standard timing. Some machines do not correctly
support 16-bit I/O operations with wait states. Although
the PCnet-ISA+ controller is quite fast, some operations
still require an occasional wait state. The PCnet-ISA+
controllermovesdatathroughmemoryaccesses, there-
fore, I/O operations do not affect performance. By
configuring the PCnet-ISA+ controller as an 8-bit I/O de-
vice, compatibility with PC/AT-class machines is
obtained at virtually no cost in performance. To treat the
PCnet-ISA+ controller as an 8-bit software resource (for
non-ISA applications), the even-byte must be accessed
first, followed by an odd-byte access.
Bus Master
Bus Master mode is the preferred mode for client appli-
cations on PC/AT or similar machines supporting 16-bit
DMA with its unsurpassed combination of high perform-
ance and low cost.
Shared Memory
The shared memory mode is recommended for file serv-
ers or other applications where there is very high,
average or peak latency.
Memory cycle timing is an area where some tradeoffs
may be necessary. Any slow down in a memory cycle
translates directly into lower bandwidth. The
PCnet-ISA+ controller starts out with much higher
bandwidth than most slave type controllers and should
continue to be superior even if an extra 50 or 100 ns are
added to memory cycles.
The address compare circuit has the following
functions. It receives the 7 LA signals, generates
MEMCS16, and compares them to the desired shared
memory and boot PROM addresses. The logic latches
the address compare result when BALE goes inactive
and uses the appropriate SA signals to generate SMAM
and BPAM.
The memory cycle active time is tunable in 50 ns incre-
ments with a default of 250 ns. The memory cycle idle
time defaults to 200 ns and can be reprogrammed to
100 ns. See register description for ISACS42. Most ma-
chines should not need tuning.
All these functions can be performed in one PAL device.
To operate in an 8-bit PC/XT environment, the LA
signals should have weak pull-down resistors con-
nectedtothemtopresentalogic0levelwhennotdriven.
The PCnet-ISA+ controller is compatible with NE2100
and NE1500T software drivers. All the resources such
BPCS
CE
OE
PRDB[0-7]
D[0-7]
16-Bit System Data
SD[0-15]
Boot
PROM
PRDB[2]/EEDO
PRDB[1]/EEDI
PRDB[0]/EESK
PCnet-ISA+
Controller
A[0-15]
ISA
Bus
24-Bit System
Address
DO
DI
SK
CS
SA[0-19]
LA[17-23]
EEPROM
SHFBUSY
EECS
VCC
ORG
VCC
18183B-6
Bus Master Block Diagram
Plug and Play Compatible
1-578
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AMD
A[0-4]
D[0-7]
BPCS
IEEE
Address
PROM
PRDB[0-7]
SD[0-15]
G
16-Bit
System
Data
PRDB[0]/EESK
PRDB[1]/EEDI
PRDB[2]/EEDO
EECS
PCnet-ISA+
Controller
A[0-15]
D[0-7]
WE
SA[0-19]
LA[17-23]
24-Bit
System
Address
Flash
SHFBUSY
IRQ15/APCS IRQ12/FlashWE
ISA
Bus
OE
CS
VCC
SK
DI
EEPROM
DO
CS
VCC
ORG
18183B-7
Bus Master Block Diagram
Plug and Play Compatible with Flash Support
1-579
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P R E L I M I N A R Y
A[0-15]
Boot
PROM
CE
OE
D[0-7]
PRAB(0:15)
BPCS
PRDB[0-7]
SD[0-15]
SA[0-15]
PCnet-ISA+
Controller
16-Bit
System Data
2
1
0
PRDB[2]/EEDO
PRDB[1]/EEDI
PRDB[0]/EESK
EECS
DO
DI
EEPROM
24-Bit System
Address
VCC
SK
CS
SMAM
ORG
SHFBUSY
BPAM
ISA
Bus
SROE
SRWE
A[0-15]
D[0-7]
WE
SRAM
CS
OE
VCC
SHFBUSY
CLK
BPAM
SMAM
SIN
External
Glue
SA[16]
Logic
LA[17-23]
MEMCS16
18183B-9
Shared Memory Block Diagram
Plug and Play Compatible
1-580
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AMD
A[0-15]
D[0-7]
FLASH
WE
CS
PRDB[0-7]
PRAB[0-15]
OE
BPCS
SROE
SD[0-15]
PCnet-ISA+
16-Bit
System Data
Controller
PRDB[2]/EEDO
PRDB[1]/EEDI
DO
DI
24-Bit System
Address
EEPROM
SA[0-19]
SK
CS
VCC
PRDB[0]/EESK
EECS
ORG
SRWE
IRQ12/SRCS
ISA
Bus
SHFBUSY SRAM BPAM
OE
A[0-15]
SRAM
WE
CS
D[0-7]
SIN
MEMCS16
CLK
VCC
External
BPAM
SRAM
Glue
Logic
SHFBUSY
SA[16]
LA[17-23]
18183B-10
Shared Memory Block Diagram
Plug and Play Compatible with Flash Memory Support
1-581
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P R E L I M I N A R Y
Optional Address PROM Interface
Static RAM Interface (for Shared Memory
Only)
The suggested address PROM is the Am27LS19, a
32x8 device. APCS should be connected directly to the
device’s G input.
The SRAM is an 8Kx8 or 32Kx8 device. The PCnet-ISA+
controller can support 64 Kbytes of SRAM address
space. The PCnet-ISA+ controller provides SROE and
SRWE outputs which can go directly to the OE and WE
pins of the SRAM, respectively. The address lines are
connected as described in the shared memory section
and the data lines go to the Private Data Bus.
A4–A0
27LS19
32 x 8 PROM
G
Q7–Q0
AUI
18183B-23
The PCnet-ISA+ controller drives the AUI through a set
of transformers. The DI and CI inputs should each be
terminated with a pair of matched 39 Ω or 40.2 Ω resis-
tors connected in series with the middle node bypassed
to ground with a .01 µF to 0.1 µF capacitor. Refer to the
PCnet-ISA Technical Manual (PID #16850B) for net-
work interface design and refer to Appendix A for a list of
compatible AUI isolation transformers.
Address PROM Example
Boot PROM Interface
The boot PROM is a 8K–64K EPROM. Its OE pin
shouldbetiedtoground, andchipenableCEtoBPCSto
minimize power consumption at the expense of speed.
Shown below is a 27C128.
EEPROM Interface
Higher density EPROMs place an address line on the
pin that is defined for lower density EPROMs as the VPP
(programming voltage) pin. For READ only operation on
an EPROM, the VPP pin can assume any logic level, as
long as the voltage on the VPP pin does not exceed the
programming voltage threshold (typically 7 V to 12 V).
Therefore, a socket with a 27512 pinout will also support
2764 and 27128 EPROM devices.
The suggested EEPROM is the industry standard
93C56 2 Kbit serial EEPROM. This is used in the 16-bit
mode to provide 128 x 16-bit EEPROM locations to
store configuration information as well as the Plug and
Play information.
93C56
EECS
PRDB2/EEDO
PRDB1/EEDI
PRDB0/EESK
CS
DO
DI
A13-A0
DQ7-DQ0
VCC
27C128
16K x 8 EPROM
ORG
CLK
CE
OE
18183B-25
18183B-24
Boot PROM Example
1-582
Am79C961
P R E L I M I N A R Y
AMD
Technical Manual (PID #18216A) for more design de-
tails, and refer to Appendix A for a list of compatible
10BASE-T filter/transformer modules.
10BASE-T Interface
The diagram below shows the proper 10BASE-T net-
work interface design. Refer to the PCnet Family
Filter &
Transformer
Module
RJ45
Connector
61.9
TXD+
422.0
1:1
TXP+
TD+
TD-
1
2
XMT
Filter
1.21 K
61.9
PCnet-ISA+
TXD-
TXP-
Controller
422.0
1:1
RD+
RD-
3
6
RXD+
RXD-
RCV
Filter
100
18183B-26
Note: All resistors are ±1%
10BASE-T External Components and Hookup
Am79C961
1-583
AMD
P R E L I M I N A R Y
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . –65°C to +150°C
Commercial (C) Devices
Ambient Temperature
Temperature (TA) . . . . . . . . . . . . . . 0°C to +70°C
Under Bias . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Supply Voltages
(AVDD, DVDD) . . . . . . . . . . . . . . . . . . . . . 5 V ±5%
Supply Voltage to AVss
or DVSS (AVDD, DVDD) . . . . . . . . . . . –0.3 V to +6.0 V
All inputs within the range: . . AVSS – 0.5 V ≤ Vin ≤
AVDD + 0.5 V, or
Stresses above those listed under Absolute Maximum Rat-
ings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maxi-
mum Ratings for extended periods may affect device
reliability. Programming conditions may differ.
DVSS – 0.5 V ≤ Vin ≤
DVDD + 0.5 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise
specified (refer to page 19 for driver types)
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
Digital Input Voltage
VIL
VIH
Input LOW Voltage
Input HIGH Voltage
0.8
V
V
2.0
DVDD + 0.5
Digital Ouput Voltage
VOL
VOH
Output LOW Voltage
Output HIGH Voltage
0.5
10
V
V
(Note 1)
2.4
Digital Input Leakage Current
IIX Input Leakage Current
VDD = 5 V, VIN = 0 V
(Note 2)
–10
µA
Digital Ouput Leakage Current
IOZL
Output Low Leakage
Current (Note 3)
VOUT = 0 V
VOUT = VDD
–10
µA
µA
IOZH
Output High Leakage
Current (Note 3)
10
Crystal Input Current
VILX
VILHX
IILX
XTAL1 Input LOW
Threshold Voltage
VIN = External Clock
VIN = External Clock
VIN = DVSS
–0.5
3.5
0.8
V
V
XTAL1 Input HIGH
Threshold Voltage
VDD + 0.5
Active
Sleep
Active
µA
µA
µA
µA
XTAL1 Input LOW Current
–120
–10
0
0
+10
120
400
IIHX
XTAL1 Input HIGH Current
VIN = VDD
Sleep
Attachment Unit Interface
IIAXD Input Current at DI+
AVSS < VIN < AVDD
AVSS < VIN < AVDD
RL = 78 Ω
–500
–500
630
+500
+500
1200
+40
µA
µA
and DI–
IIAXC
Input current at
CI+ and CI–
VAOD
Differential Output Voltage
|(DO+)–(DO–)|
mV
mV
VAODOFF
Transmit Differential Output
Idle Voltage
RL = 78 Ω (Note 5)
–40
1-584
Am79C961
P R E L I M I N A R Y
AMD
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise
specified (continued)
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
Attachment Unit Interface (continued)
IAODOFF
VCMT
VODI
Transmit Differential
Output Idle Current
RL = 78 Ω (Note 4)
RL = 78 Ω
–1
+1
AVDD
25
mA
V
Transmit Output Common
Mode Voltage
2.5
DO± Transmit Differential
Output Voltage Imbalance
RL = 78 Ω (Note 5)
(Note 5)
mV
mV
mV
V
VATH
Receive Data Differential
Input Threshold
–35
–275
35
VASQ
VIRDVD
VICM
DI± and CI± Differential
Input Threshold (Squelch)
–160
+1.5
DI± and CI± Differential
Mode Input Voltage Range
–1.5
DI± and CI± Input Bias
Voltage
IIN = 0 mA
(Note 5)
AVDD–3.0
AVDD–1.0
–100
V
VOPD
DO± Undershoot Voltage
at Zero Differential on
Transmit Return to
Zero (ETD)
mV
Twisted Pair Interface
IIRXD
Input Current at RXD±
AVSS < VIN < AVDD
(Note 5)
–500
10
500
µA
RRXD
RXD± Differential Input
KΩ
Resistance
VTIVB
RXD+, RXD– Open Circuit
Input Voltage (Bias)
IIN = 0 mA
AVDD – 3.0
–3.1
AVDD – 1.5
+3.1
V
V
VTIDV
Differential Mode Input
AVDD = +5 V
Voltage Range (RXD±)
VTSQ+
VTSQ–
VTHS+
VTHS–
VLTSQ+
VLTSQ–
VLTHS+
VLTHS–
RXD Positive Squelch
Threshold (Peak)
Sinusoid
5 MHz ≤ f ≤10 MHz
300
–520
150
520
–300
293
mV
mV
mV
RXD Negative Squelch
Threshold (Peak)
Sinusoid
5 MHz ≤ f ≤10 MHz
RXD Post-Squelch
Positive Threshold (Peak)
Sinusoid
5 MHz ≤ f ≤10 MHz
RXD Post-Squelch
Negative Threshold (Peak)
Sinusoid
5 MHz ≤ f ≤10 MHz
–293
180
–150
312
mV
mV
RXD Positive Squelch
Threshold (Peak)
LRT = 1 (Note 6)
LRT = 1 (Note 6)
LRT = 1 (Note 6)
LRT = 1 (Note 6)
RXD Negative Squelch
Threshold (Peak)
–312
90
–180
156
mV
mV
mV
RXD Post-Squelch Positive
Threshold (Peak)
RXD Post-Squelch
–156
–90
Negative Threshold (Peak)
Am79C961
1-585
AMD
P R E L I M I N A R Y
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise
specified (continued)
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
Twisted Pair Interface (continued)
VRXDTH
VTXH
RXD Switching Threshold
(Note 5)
–35
35
mV
V
TXD± and TXP± Output
DVSS = 0 V
DVDD – 0.6
DVDD
HIGH Voltage
VTXL
TXD± and TXP± Output
LOW Voltage
DVDD = +5 V
DVSS
–40
DVSS + 0.6
+40
V
VTXI
TXD± and TXP±
Differential Output
Voltage Imbalance
mV
VTXOFF
TXD± and TXP± Idle
DVDD = +5 V
–40
+40
mV
Output Voltage
RTX
TXD± Differential Driver
Output Impedance
(Note 5)
(Note 5)
40
80
Ω
Ω
TXP± Differential Driver
Output Impedance
IEEE 1149.1 (JTAG) Test Port
VIL
VIH
VOL
VOH
IIL
TCK, TMS, TDI
TCK, TMS, TDI
TDO
0.8
0.4
V
V
2.0
2.4
IOL = 2.0 mA
V
TDO
IOH = –0.4 mA
V
TCK, TMS, TDI
TCK, TMS, TDI
TDO
VDD = 5.5 V, VI = 0.5 V
VDD =5.5 V, VI = 2.7 V
0.4 V < VOUT < VDD
–200
–100
+10
µA
µA
µA
IIH
IOZ
–10
Power Supply Current
IDD
Active Power Supply Current
XTAL1 = 20 MHz
75
mA
IDDCOMA
Coma Mode Power
Supply Current
SLEEP active
200
µA
IDDSNOOZE Snooze Mode Mall Power
Supply Current
Awake bit set active
10
mA
Notes:
1. VOH does not apply to open-drain output pins.
2. IIX applies to all input only pins except DI±, CI±, XTAL1 and PRDB[7:0].
3. IOZL applies to all three-state output pins and bi-directional pins, except PRDB[7:0]. IOZH applies to pins PRDB[7:0].
4. Correlated to other tested parameters—not tested directly.
5. Parameter not tested.
6. LRT is bit 9 of Mode register (CSR15)
1-586
Am79C961
P R E L I M I N A R Y
AMD
SWITCHING CHARACTERISTICS: BUS MASTER MODE
Parameter
Symbol
Input/Output Write Timing
tIOW1 AEN, SBHE, SA0–9 Setup
Parameter Description
Test Conditions
Min
Max
Unit
10
5
ns
ns
to ↓ IOW
tIOW2
AEN, SBHE,SA0–9 Hold
After ↑ IOW
tIOW3
tIOW4
tIOW5
tIOW6
tIOW7
tIOW8
tIOW9
IOW Assertion
100
55
10
10
0
ns
ns
ns
ns
ns
ns
ns
IOW Inactive
SD Setup to ↑ IOW
SD Hold After ↑ IOW
↓ IOCHRDY Delay From ↓ IOW
IOCHRDY Inactive
↑IOCHRDY to ↑ IOW
35
125
0
Input/Output Read Timing
tIOR1 AEN, SBHE, SA0–9 Setup
15
5
ns
ns
to ↓ IOR
tIOR2
AEN, SBHE,SA0–9 Hold
After ↑ IOR
tIOR3
tIOR4
tIOR5
tIOR6
tIOR7
tIOR8
IOR Inactive
55
0
ns
ns
ns
ns
ns
ns
SD Hold After ↑ IOR
SD Valid From ↓ IOR
↓ IOCHRDY Delay From ↓ IOR
IOCHRDY Inactive
20
110
35
0
0
125
–130
SD Valid From ↑ IOCHRDY
10
I/O To Memory Command Inactive
tIOM1 ↑ IOW/MEMW to ↓ (S)MEMR/IOR
tIOM2 ↑ (S)MEMR/IOR to ↓ IOW/MEMW
IOCS16 Timing
tIOCS1 AEN, SBHE, SA0–9 to ↓ IOCS16
tIOCS2
55
55
ns
ns
0
0
35
25
ns
ns
AEN, SBHE, SA0–9 to IOCS16
Tristated
Master Mode Bus Acquisition
tMMA1
tMMA2
tMMA3
tMMA4
tMMA5
REF Inactive to ↓ DACK
5
0
ns
ns
ns
ns
ns
↑ DRQ to ↓ DACK
DACK Inactive
55
↓ DACK to ↓ MASTER
35
↓ MASTER to Active Command,
SBHE, SA0–19, LA17–23
125
185
Am79C961
1-587
AMD
P R E L I M I N A R Y
SWITCHING CHARACTERISTICS: BUS MASTER MODE (continued)
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
Master Mode Bus Release
tMMBR1
tMMBR2
tMMBR3
tMMBR4
Command Deassert to ↓ DRQ
45
0
65
ns
ns
ns
ns
↓ DRQ to ↑ DACK
↓ DRQ to ↑ MASTER
40
–15
60
0
↓ DRQ to Command, SBHE,
SA0–19, LA17–23 Tristated
Master Write Cycles
tMMW1
SBHE, SA0–19, LA17–23,
Active to ↓ MEMW
(Note 1)
EXTIME + 45
MSWRA – 10
EXTIME + 65
MSWRA + 5
ns
tMMW2
tMMW3
tMMW4
MEMW Active
(Note 2)
(Note 1)
ns
ns
ns
MEMW Inactive
EXTIME + 97 EXTIME + 105
↑ MEMW to SBHE, SA0–19,
45
55
LA17–23,SD Inactive
tMMW5
tMMW6
tMMW7
SBHE, SA0–19, LA17–23, SD
Hold After ↑ MEMW
45
60
ns
ns
ns
SBHE, SA0–19, LA17–23,
SD Setup to ↓ MEMW
(Note 1)
EXTIME + 45
tMMW2 – 175
EXTIME + 55
↓ IOCHRDY Delay
From ↓ MEMW
tMMW8
tMMW9
tMMW10
tMMW11
IOCHRDY Inactive
55
ns
ns
ns
ns
↑ IOCHRDY to ↑ MEMW
SD Active to ↓ MEMW
SD Setup to ↓ MEMW
130
(Note 1)
(Note 1)
EXTIME + 20
EXTIME + 20
EXTIME + 60
EXTIME + 60
Master Read Cycles
tMMR1
SBHE, SA0–19, LA17–23,
Active to ↓ MEMR
(Note 1)
EXTIME + 45
MSRDA – 10
EXTIME + 60
MSRDA + 5
ns
tMMR2
tMMR3
tMMR4
MEMR Active
(Note 2)
(Note 1)
ns
ns
ns
MEMR Inactive
EXTIME + 97 EXTIME + 105
↑ MEMR to SBHE, SA0–19,
45
55
LA17–23 Inactive
tMMR5
tMMR6
tMMR7
SBHE, SA0–19, LA17–23
Hold After ↑ MEMW
45
55
ns
ns
ns
SBHE, SA0–19, LA17–23
Setup to ↓ MEMR
(Note 1)
EXTIME + 45
tMMR2 – 175
EXTIME + 55
↓ IOCHRDY Delay From
↓ MEMR
tMMR8
tMMR9
tMMR10
tMMR11
IOCHRDY Inactive
55
130
30
0
ns
ns
ns
ns
↑ IOCHRDY to ↑ MEMR
SD Setup to ↑ MEMR
SD Hold After ↑ MEMR
1-588
Am79C961
P R E L I M I N A R Y
AMD
SWITCHING CHARACTERISTICS: BUS MASTER MODE (continued)
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
Master Mode Address PROM Read
tMA1
tMA2
tMA3
tMA4
tMA5
tMA6
↓ IOR to ↓ APCS
125
140
20
0
260
155
ns
ns
ns
ns
ns
ns
APCS Active
PRDB Setup to ↑ APCS
PRDB Hold After ↑ APCS
↑ APCS to ↑ IOCHRDY
SD Valid From ↑ IOCHRDY
45
0
65
10
Master Mode Boot PROM Read
tMB1
tMB2
tMB3
REF, SBHE,SA0–19 Setup
to ↓ SMEMR
10
5
ns
ns
ns
REF, SBHE,SA0–19 Hold
↑ SMEMR
↓ IOCHRDY Delay
From ↓ SMEMR
0
35
tMB4
tMB5
SMEMR Inactive
55
125
290
45
20
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
↓ SMEMR to ↓ BPCS
BPCS Active
260
305
65
tMB6
tMB7
↑ BPCS to ↑ IOCHRDY
PRDB Setup to ↑ BPCS
PRDB Hold After ↑ BPCS
SD Valid From ↑ IOCHRDY
SD Hold After ↑ SMEMR
LA20–23 Hold From ↓ BALE
LA20–23 Setup to ↓ MEMR
↑ BALE Setup to ↓ MEMR
tMB8
tMB9
tMB10
tMB11
tMB12
tMB13
tMB14
0
10
20
0
10
10
10
Notes:
1. EXTIME is 100 ns when ISACSR2, bit 4, is cleared (default). EXTIME is 0 ns when ISACSR2, bit 4, is set.
2. MSRDA and MSWDA are parameters which are defined in registers ISACSR0 and ISACSR1, respectively.
Am79C961
1-589
AMD
P R E L I M I N A R Y
SWITCHING CHARACTERISTICS: BUS MASTER MODE—FLASH READ CYCLE
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
tMFR1
REF, SBHE,SA0–19 Setup
10
ns
to ↓ MEMR
tMFR2
REF, SBHE,SA0–19 Hold From
5
ns
↑ MEMR
tMFR3
tMFR4
tMFR5
tMFR6
tMFR7
tMFR8
tMFR9
tMFR10
tMFR11
tMFR12
tMFR13
tMFR14
↓ IOCHRDY to MEMR
↓ MEMR Inactive
0
55
125
190
45
20
0
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
↓ MEMR to ↓ BPCS
260
205
65
BPCS Active
↑ BPCS to ↑ IOCHRDY
PRDB Setup to ↑ of BPCS
PRDB Hold to ↑ of BPCS
SD Valid From ↑ IOCHRDY
SD Tristate to ↑ MEMR
LA20–23 Hold From ↓ BALE
LA20–23 Setup to ↓ MEMR
↑ BALE Setup to ↓ MEMR
0
10
20
0
10
10
15
SWITCHING CHARACTERISTICS: BUS MASTER MODE—FLASH WRITE CYCLE
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
tMFW1
SBHE, SA0–19 Setup
to ↓ MEMW
10
ns
tMFW2
SBHE, SA0–19 Hold
From ↑ MEMW
5
ns
tMFW3
tMFW4
tMFW5
tMFW6
tMFW7
tMFW8
tMFW9
tMFW10
tMFW11
tMFW12
tMFW13
tMFW14
tMFW15
↓ IOCHRDY to ↓ MEMW
MEMW Inactive
0
50
20
0
35
90
ns
ns
ns
ns
ns
ns
ns
ns
ns
↑ FL_WE to ↑ IOCHRDY
↑ MEMW Hold From ↑ IOCHRDY
SD Valid From ↓ MEMW
SD Hold From ↑ MEMW
PRDB Valid From ↓ MEMW
PRDB Setup to ↓ FL_WE
FL_WE Active
175
175
155
0
15
140
15
PRDB Hold From ↑ FL_WE
LA20–23 Hold From ↓ BALE
LA20–23 Setup to ↓ MEMW
↑ BALE Setup to ↓ MEMW
10
ns
ns
ns
10
15
1-590
Am79C961
P R E L I M I N A R Y
AMD
SWITCHING CHARACTERISTICS: SHARED MEMORY MODE
Parameter
Symbol
Input/Output Write Timing
tIOW1 AEN, SBHE, SA0–9 Setup
Parameter Description
Test Conditions
Min
Max
Unit
10
5
ns
ns
to ↓ IOW
tIOW2
AEN, SBHE,SA0–9 Hold
From ↑ IOW
tIOW3
tIOW4
tIOW5
tIOW6
tIOW7
tIOW8
tIOW9
IOW Assertion
150
55
10
10
0
ns
ns
ns
ns
ns
ns
ns
IOW Inactive
SD Setup to ↑ IOW
SD Hold After ↑ IOW
↓ IOCHRDY Delay From ↓ IOW
IOCHRDY Inactive
↑IOCHRDY to ↑ IOW
35
125
0
Input/Output Read Timing
tIOR1 AEN, SBHE, SA0–9 Setup
15
5
ns
ns
to ↓ IOR
tIOR2
AEN, SBHE,SA0–9 Hold
After ↑ IOR
tIOR3
tIOR4
tIOR5
tIOR6
tIOR7
tIOR8
IOR Inactive
55
0
ns
ns
ns
ns
ns
ns
SD Hold From ↑ IOR
SD Valid From ↓ IOR
↓ IOCHRDY Delay From ↓ IOR
IOCHRDY Inactive
20
110
35
0
0
125
–130
SD Valid From ↑ IOCHRDY
10
Memory Write Timing
tMW1 SA0–15, SBHE, ↓ SMAM Setup
10
5
ns
ns
to ↓ MEMW
tMW2
SA0–15, SBHE, ↑ SMAM Hold
From ↑ MEMW
tMW3
tMW4
tMW5
tMW6
tMW7
MEMW Assertion
150
55
10
10
0
ns
ns
ns
ns
ns
MEMW Inactive
SD Setup to ↑ MEMW
SD Hold From ↑ MEMW
↓ IOCHRDY Delay From
↓ MEMW
35
tMW8
tMW9
IOCHRDY Inactive
125
0
ns
ns
↑ MEMW to ↑ IOCHRDY
Am79C961
1-591
AMD
P R E L I M I N A R Y
SWITCHING CHARACTERISTICS: SHARED MEMORY MODE (continued)
Parameter
Symbol
Memory Read Timing
tMR1 SA0–15, SBHE, ↓ SMAM/BPAM
Parameter Description
Test Conditions
Min
Max
Unit
10
5
ns
ns
Setup to ↓ MEMR
tMR2
SA0–15, SBHE, ↑ SMAM/BPAM
Hold From ↑ MEMR
tMR3
tMR4
tMR5
tMR6
tMR7
tMR8
MEMR Inactive
55
0
ns
ns
ns
ns
ns
ns
SD Hold From ↑ MEMR
SD Valid From ↓ MEMR
↓ IOCHRDY Delay From ↓ MEMR
IOCHRDY Inactive
20
110
35
0
0
125
–130
SD Valid From ↑ IOCHRDY
10
I/O To Memory Command Inactive
tIOM1 ↓ IOW/MEMW to ↓ (S)MEMR/IOR
tIOM2 ↓ (S)MEMR/IOR to ↓ IOW/MEMW
IOCS16 Timing
tIOCS1 AEN, SBHE, SA0–9 to ↓ IOCS16
tIOCS2
55
55
ns
ns
0
0
35
25
ns
ns
AEN, SBHE, SA0–9 to IOCS16
Tristated
SRAM Read/Write, Boot PROM Read, Address PROM Read on Private Bus
tPR4
tPR5
tPR6
tPR7
PRAB Change to PRAB
Change, SRAM Access
95
20
0
105
ns
ns
ns
ns
PRDB Setup to PRAB
Change, SRAM Access
PRDB Hold From PRAB
Change, SRAM Access
PRAB Change to PRAB
Change, APROM Access
145
155
1-592
Am79C961
P R E L I M I N A R Y
AMD
SWITCHING CHARACTERISTICS: SHARED MEMORY MODE (continued)
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
SRAM Read/Write, Boot PROM Read, Address PROM Read on Private Bus (continued)
tPR8
PRDB Setup to PRAB
Change, APROM Access
20
0
ns
ns
ns
ns
ns
ns
tPR9
PRDB Hold After PRAB
Change, APROM Access
tPR10
tPR11
tPR12
tPR13
PRAB Change to PRAB
Change, BPROM Access
290
20
0
305
155
PRDB Setup to PRAB
Change, BPROM Access
PRDB Hold After PRAB
Change, BPROM Access
PRAB Change to PRAB
Change, SRAM Write
145
tPR14
tPR15
tPR16
PRAB Change to ↓ SRWE
PRAB Change to ↑ SRWE
20
30
ns
ns
ns
120
190
130
205
PRAB Change to PRAB Change,
Flash Access
tPR17
PRAB Change to PRAB Change,
Flash Write
190
170
205
180
ns
ns
tPR18
PRAB Change to↑ SRWE
Am79C961
1-593
AMD
P R E L I M I N A R Y
SWITCHING CHARACTERISTICS: SHARED MEMORY MODE—FLASH READ CYCLE
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
tMFR1
BPAM, REF, SBHE, SA0–19
10
ns
Setup to ↓ MEMR
tMFR2
BPAM, REF, SBHE, SA0–19 Hold
5
ns
From ↑ MEMR
tMFR3
tMFR4
tMFR5
tMFR6
tMFR7
tMFR8
↓ IOCHRDY to ↓ MEMR
MEMR Inactive
0
35
ns
ns
ns
ns
ns
ns
55
↓ MEMR to ↓ BPCS/SROE
BPCS/SROE Active
125
190
45
260
205
65
↑ BPCS/SROE to ↑ IOCHRDY
PRDB Setup to
20
↑ of BPCS/SROE
tMFR9
PRDB Hold to
0
ns
↑ of BPCS/SROE
tMFR10
tMFR11
SD Valid From ↑ IOCHRDY
SD Tristate to ↑ MEMR
0
0
10
20
ns
ns
SWITCHING CHARACTERISTICS: SHARED MEMORY MODE—FLASH WRITE CYCLE
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
tMFW1
BPAM, SBHE, SA0–19
10
ns
Setup to ↓ MEMW
tMFW2
BPAM, SBHE, SA0–19
5
ns
Hold After ↑ MEMW
tMFW3
tMFW4
tMFW5
tMFW6
tMFW7
tMFW8
tMFW9
↓ IOCHRDY to ↓ MEMW
MEMW Inactive
0
50
20
0
35
90
ns
ns
ns
ns
ns
ns
ns
↑ SRWE to ↑ IOCHRDY
↑ MEMW Hold From ↑ IOCHRDY
SD Valid From ↓ MEMW
SD Hold From ↑ MEMW
175
175
0
BPCS/PRDB Valid From
↓ MEMW
tMFW10
tMFW11
tMFW12
BPCS/PRDB Setup to ↓ SRWE
SRWE Active
15
140
15
ns
ns
ns
155
BPCS/PRDB Hold From ↑ SRWE
1-594
Am79C961
P R E L I M I N A R Y
AMD
SWITCHING CHARACTERISTICS: EADI
Parameter
Symbol
Parameter Description
SRD Setup to ↑ SRDCLK
SRD Hold to ↑ SRDCLK
Test Conditions
Min
40
Max
Unit
tEAD1
tEAD2
tEAD3
tEAD4
ns
ns
ns
ns
40
SF/BD Change to ↓ SRDCLK
–15
50
+15
EAR Deassertion to ↑
SRDCLK (First Rising Edge)
tEAD5
EAR Assertion From SFD
Event (Packet Rejection)
0
51,090
ns
ns
tEAD6
EAR Assertion
110
Note: External Address Detection interface is invoked by setting bit 3 in ISACSR2 and resetting bit 0 in ISACSR2. External
MAU select is not available when EADISEL bit is set.
SWITCHING CHARACTERISTICS: JTAG (IEEE 1149.1) INTERFACE
Parameter
Symbol
tJTG1
tJTG2
tJTG3
tJTG4
tJTG5
tJTG6
tJTG7
tJTG8
Parameter Description
TCK HIGH Assertion
TCK Period
Test Conditions
Min
20
50
5
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
TDI Setup to ↑ TCK
TDI, TMS Hold From ↑ TCK
TMS Setup to ↑ TCK
TDO Active From ↓ TCK
TDO Change From ↓ TCK
TDO Tristate From ↓ TCK
5
8
0
30
30
25
0
0
Note: JTAG logic is reset with an internal Power-On Reset circuit independent of Sleep Modes.
Am79C961
1-595
AMD
P R E L I M I N A R Y
SWITCHING CHARACTERISTICS: GPSI
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
Transmit Timing
tGPT1
tGPT2
tGPT3
tGPT4
tGPT5
tGPT6
tGPT7
STDCLK Period (802.3 Compliant)
STDCLK HIGH Time
99.99
40
100.01
60
ns
ns
ns
ns
ns
ns
ns
TXDAT and TXEN Delay from ↑ TCLK
RXCRS Setup to ↑ STDCLK(Last Bit)
RXCRS Hold From ↓ TENA
0
70
210
0
CLSN Active Time to Trigger Collision
(Note 1)
110
0
CLSN Active to ↓ RXCRS to Prevent
LCAR Assertion
tGPT8
CLSN Active to ↓ RXCRS for SQE
Hearbeat Window
0
0
4.0
µs
µs
tGPT9
CLSN Active to ↑ RXCRS for Normal Collision
51.2
Receive Timing
tGPR1
SRDCLK Period
(Note 2)
(Note 2)
(Note 2)
80
30
30
15
15
0
120
80
ns
ns
ns
ns
ns
ns
ns
tGPR2
SRDCLK High Time
tGPR3
SRDCLK Low Time
80
tGPR4
RXDAT and RXCRS Setup to ↑ SRDCLK
RXDAT Hold From ↑ RCLK
RXCRS Hold From ↓ SRDCLK
tGPR5
tGPR6
tGPR7
CLSN Active to First ↑ SRDCLK
0
(Collision Recognition)
tGPR8
CLSN Active to ↑ SRDCLKfor
Address Type Designation Bit
(Note 3)
51.2
210
µs
tGPR9
CLSN Setup to last ↑ SRDCLKfor
ns
Collision Recognition
tGPR10
tGPR11
CLSN Active
110
300
300
ns
ns
ns
CLSN Inactive Setup to First ↑ RCLK
CLSN Inactive Hold to Last ↑ RCLK
tGPR12
Notes:
1. CLSN must be asserted for a continuous period of 110 ns or more. Assertion for less than 110 ns period may or may
not result in CLSN recognition.
2. RCLK should meet jitter requirements of IEEE 802.3 specification.
3. CLSN assertion before 51.2 µs will be indicated as a normal collision. CLSN assertion after 51.2 µs will be
considered as a Late Receive Collision.
1-596
Am79C961
P R E L I M I N A R Y
AMD
SWITCHING CHARACTERISTICS: AUI
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
AUI Port
tDOTR
DO+,DO- Rise Time (10% to 90%)
DO+,DO- Fall Time (90% to 10%)
DO+,DO- Rise and fall Time Mismatch
DO+/- End of Transmission
2.5
2.5
–
5.0
5.0
1.0
375
45
ns
ns
ns
ns
ns
tDOTF
tDORM
tDOETD
tPWODI
200
15
DI Pulse Width Accept/Reject
Threshold
|VIN| > |VASQ
(Note 1)
|
|
|
|
tPWKDI
tPWOCI
tPWKCI
DI Pulse Width Maintain/Turn-Off
Threshold
|VIN| > |VASQ
(Note 2)
136
10
200
26
ns
ns
ns
CI Pulse Width Accept/Reject
Threshold
|VIN| > |VASQ
(Note 3)
CI Pulse Width Maintain/Turn-Off
Threshold
|VIN| > |VASQ
(Note 4)
90
160
Internal MENDEC Clock Timing
tX1
XTAL1 Period
VIN = External Clock
VIN = External Clock
VIN = External Clock
VIN = External Clock
VIN = External Clock
49.995
20
50.005
ns
ns
ns
ns
ns
tX1H
tX1L
tX1R
tX1F
XTAL1 HIGH Pulse Width
XTAL1 LOW Pulse width
XTAL1 Rise Time
20
5
5
XTAL1 Fall Time
Notes:
1. DI pulses narrower than tPWODI (min) will be rejected; pulses wider than tPWODI (max) will turn internal DI carrier sense on.
2. DI pulses narrower than tPWKDI (min) will maintain internal DI carrier sense on; pulses wider than tPWKDI (max) will turn
internal DI carrier sense off.
3. CI pulses narrower than tPWOCI (min) will be rejected; pulses wider than tPWOCI (max) will turn internal CI carrier sense on.
4. CI pulses narrower than tPWKCI (min) will maintain internal CI carrier sense on; pulses wider than tPWKCI (max) will turn
internal CI carrier sense off.
Am79C961
1-597
AMD
P R E L I M I N A R Y
SWITCHING CHARACTERISTICS: 10BASE-T INTERFACE
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
Transmit Timing
tTETD
tTR
Transmit Start of Idle
Transmitter Rise Time
Transmitter Fall Time
250
350
5.5
5.5
2
ns
ns
ns
ns
(10% to 90%)
tTF
(90% to 10%)
tTM
Transmitter Rise and Fall
Time Mismatch
tPERLP
tPWLP
Idle Signal Period
8
24
120
55
ms
ns
ns
Idle Link Pulse Width
(Note 1)
(Note 1)
75
45
tPWPLP
Predistortion Idle Link Pulse
Width
tJA
tJR
Receive Timing
Transmit Jabber Activation Time
20
150
750
ms
ms
Transmit Jabber Reset Time
250
tPWNRD
RXD Pulse Width Not to Turn
Off Internal Carrier Sense
VIN > VTHS (min)
VIN > VTHS (min)
136
–
ns
ns
tPWROFF
RXD Pulse Width to Turn Off
200
Note:
1. Not tested; parameter guaranteed by characterization.
SWITCHING CHARACTERISTICS: SERIAL EEPROM
Parameter
Symbol
Parameter Description
EESK High Time
Test Conditions
Min
790
790
-15
Max
Unit
ns
tSR1
tSR2
EESK Low Time
ns
tSR3
↑ EECS EEDI From ↓ EESK
15
15
ns
tSR4
↓ EECS, EEDI and SHFBUSY
From ↓ EESK
-15
ns
tSR5
tSR6
tSR7
tSL1
tSL2
tSL3
EECS Low Time
1590
35
ns
ns
ns
ns
ns
ns
EEDO Setup to ↑ EESK
EEDO Hold From ↑ EESK
EEDO Setup to ↓ IOR
EEDO Setup to ↑ IOCHRDY
0
95
140
160
EESK, EEDI, EECS and
235
SHFBUSY Delay From↑ IOW
1-598
Am79C961
P R E L I M I N A R Y
AMD
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Must be
Steady
Will be
Steady
May
Change
from H to L
Will be
Changing
from H to L
May
Change
from L to H
Will be
Changing
from L to H
Don’t Care,
Any Change
Permitted
Changing,
State
Unknown
Does Not
Apply
Center
Line is High-
Impedance
“Off” State
KS000010
Am79C961
1-599
AMD
P R E L I M I N A R Y
SWITCHING TEST CIRCUITS
IOL
Sense Point
VTHRESHOLD
CL
IOH
18183B-26
Normal and Three-State Outputs
AVDD
52.3 Ω
DO+
DO–
Test Point
154 Ω
100 pF
AVSS
18183B-27
AUI DO Switching Test Circuit
1-600
Am79C961
P R E L I M I N A R Y
AMD
SWITCHING TEST CIRCUITS
DVDD
294 Ω
TXD+
TXD–
Test Point
294 Ω
100 pF
Includes Test
Jig Capacitance
DVSS
18183B-28
TXD Switching Test Circuit
DVDD
715 Ω
TXP+
TXP–
Test Point
715 Ω
100 pF
Includes Test
Jig Capacitance
DVSS
18183B-29
TXP Outputs Test Circuit
Am79C961
1-601
AMD
P R E L I M I N A R Y
SWITCHING WAVEFORMS: BUS MASTER MODE
AEN, SBHE,
Stable
tIOW3
SA0–9
tIOW1
tIOW2
IOW
tIOW4
tIOW6
tIOW5
SD
18183B-30
I/O Write without Wait States
AEN, SBHE,
Stable
SA0–9
tIOW1
tIOW2
IOW
tIOW4
tIOW7
tIOW8
tIOW9
IOCHRDY
SD
tIOW5
tIOW6
18183B-31
I/O Write with Wait States
1-602
Am79C961
P R E L I M I N A R Y
AMD
SWITCHING WAVEFORMS: BUS MASTER MODE
EESK
(PRDB0)
EECS
0
1
1
0
0
A6 A5 A4 A3 A2 A1 A0
EEDI
(PRDB1)
EEDO
(PRDB2)
D0 D1 D2
D14 D15
Falling transition at 26th Word, if checksum is 0xFF.
18183B-32
SHFBUSY
Serial Shift EEPROM Interface Read Timing
tSR1
tSR2
EESK
(PRDB0)
tSR3
tSR4
tSR5
EECS
EEDI
(PRDB1)
SHFBSY
EED0
(PRDB2)
Stable
tSR6 tSR7
18183A-33
Serial EEPROM Control Timing
Am79C961
1-603
AMD
P R E L I M I N A R Y
SWITCHING WAVEFORMS: BUS MASTER MODE
EED0
(PRDB2)
tSL1
IOR
tSL2
IOCHRDY
IOW
tSL3
EESK, EEDI,
EECS,
SHFBUSY
18183B-34
Slave Serial EEPROM Latency Timing
AEN, SBHE,
Stable
SA0–9
tIOR1
tIOR2
IOR
tIOR3
tIOR4
tIOR5
Stable
SD
18183B-35
I/O Read without Wait States
1-604
Am79C961
P R E L I M I N A R Y
AMD
SWITCHING WAVEFORMS: BUS MASTER MODE
AEN, SBHE,
Stable
SA0–9
tIOR1
tIOR2
IOR
tIOR3
tIOR6
tIOR7
IOCHRDY
SD
tIOR8
tIOR4
Stable
18183B-36
I/O Read with Wait States
IOW, MEMW
MEMR, IOR
tIOM1
tIOM2
18183B-37
I/O to Memory Command Inactive Time
Am79C961
1-605
AMD
P R E L I M I N A R Y
SWITCHING WAVEFORMS: BUS MASTER MODE
AEN, SBHE,
SA0–9
tIOCS1
tIOCS2
IOCS16
18183B-38
IOCS16 Timings
REF
tMMA1
DRQ
tMMA2
DACK
tMMA3
MASTER
tMMA4
MEMR/MEMW
tMMA5
SBHE,
SA0–19,
LA17–23
18183B-39
Bus Acquisition
1-606
Am79C961
P R E L I M I N A R Y
AMD
SWITCHING WAVEFORMS: BUS MASTER MODE
DRQ
tMMBR1
tMMBR2
DACK
tMMBR3
MASTER
MEMR/MEMW
tMMBR4
SBHE, SA0–19,
LA17–23
18183B-40
Bus Release
(Non Wait)
(Wait States Added)
tMMW5
tMMW6
SBHE, SA0–19,
LA17–23
tMMW4
tMMW1
tMMW2
tMMW3
MEMW
tMMW7
tMMW8 tMMW9
IOCHRDY
tMMW11
tMMW10
SD0–15
18183B-41
Write Cycles
Am79C961
1-607
AMD
P R E L I M I N A R Y
SWITCHING WAVEFORMS: BUS MASTER MODE
(Non Wait)
(Wait States Added)
Stable
tMMR5
tMMR6
SBHE, SA0–19,
Stable
LA17–23
tMMR4
tMMR1
tMMR2
tMMR3
MEMR
tMMR7
tMMR8 tMMR9
IOCHRDY
tMMR10
tMMR11
tMMR10
tMMR11
Stable
Stable
SD0–15
18183B-42
Read Cycles
AEN, SBHE,
Stable
SA0–9
tIOR2
tIOR1
IOR
tIOR3
tIOR6
tMA5
IOCHRDY
tMA1
tMA2
APCS
(IRQ15)
tMA3
tMA4
PRDB0–7
SD0–7
tMA6
tIOR4
Stable
18183B-43
External Address PROM Read Cycle
1-608
Am79C961
P R E L I M I N A R Y
AMD
SWITCHING WAVEFORMS: BUS MASTER MODE
BALE
tMB12
Stable
LA20–23
tMB13
REF, SBHE,
Stable
SA0–19
tMB1
tMB2
MEMR
tMB14
tMB3
tMB4
tMB7
IOCHRDY
tMB5
tMB6
BPCS
tMB8
tMB9
PRDB0–7
SD0–7
tMB10
tMB11
Stable
18183B-44
Boot PROM Read Cycle
Am79C961
1-609
AMD
P R E L I M I N A R Y
SWITCHING WAVEFORMS: BUS MASTER MODE
BALE
tMFR12
Stable
LA20–23
tMFR13
REF, SBHE,
Stable
SA0–19
tMFR2
tMFR1
MEMR
tMFR14
tMFR3
tMFR4
tMFR7
IOCHRDY
tMFR5
tMFR6
BPCS
tMFR8
tMFR9
PRDB0–7
SD0–7
tMFR10
tMFR11
Stable
18183B-45
Flash Read Cycle
1-610
Am79C961
P R E L I M I N A R Y
AMD
SWITCHING WAVEFORMS: BUS MASTER MODE
BALE
tMFW13
Stable
LA20–23
tMFW14
SBHE,
SA0–19
Stable
tMFW1
tMFW2
MEMW
tMFW15
tMFW3
tMFW6
tMFR4
IOCHRDY
tMFW5
tMFW7
tMFW8
SD0-7
Stable
tMFW11
tMFW10
FL_WE (IRQ12)
tMFW12
tMFW9
Stable
PRDB0-7
18183B-46
Flash Write Cycle
Am79C961
1-611
AMD
P R E L I M I N A R Y
SWITCHING WAVEFORMS: SHARED MEMORY MODE
AEN, SBHE,
Stable
tIOW3
SA0–9
tIOW1
tIOW2
IOW
tIOW4
tIOW5
tIOW6
SD
18183B-47
I/O Write without Wait States
AEN, SBHE,
Stable
SA0–9
tIOW1
tIOW2
IOW
tIOW4
tIOW7
tIOW8
tIOW9
IOCHRDY
tIOW5
tIOW6
SD
18183B-48
I/O Write with Wait States
1-612
Am79C961
P R E L I M I N A R Y
AMD
SWITCHING WAVEFORMS: SHARED MEMORY MODE
AEN, SBHE,
Stable
SA0–9
tIOR1
tIOR2
IOR
tIOR3
tIOR5
tIOR4
SD
Stable
18183B-49
I/O Read without Wait States
AEN, SBHE,
Stable
SA0–9
tIOR1
tIOR2
IOR
tIOR3
tIOR6
tIOR7
IOCHRDY
tIOR8
tIOR4
Stable
SD
18183B-50
I/O Read with Wait States
Am79C961
1-613
AMD
P R E L I M I N A R Y
SWITCHING WAVEFORMS: SHARED MEMORY MODE
SA0–15,
SBHE
Stable
SMAM
tMW1
tMW3
tMW2
MEMW
tMW4
tMW5
tMW6
SD
18183B-51
Memory Write without Wait States
SA0–15,
SBHE
Stable
SMAM
tMW1
tMW2
MEMW
tMW4
tMW7
tMW8
tMW9
IOCHRDY
tMW5
tMW6
SD
18183B-52
Memory Write with Wait States
1-614
Am79C961
P R E L I M I N A R Y
AMD
SWITCHING WAVEFORMS: SHARED MEMORY MODE
SA0–15,
SBHE
Stable
SMAM
tMR1
tMR2
MEMR
tMR3
tMR4
tMR5
Stable
SD
18183B-53
Memory Read without Wait States
SA0–15,
SBHE
Stable
SMAM/BPAM
tMR1
tMR2
MEMR
tMR3
tMR6
tMR7
IOCHRDY
SD
tMR8
tMR4
Stable
18183B-54
Memory Read with Wait States
Am79C961
1-615
AMD
P R E L I M I N A R Y
SWITCHING WAVEFORMS: SHARED MEMORY MODE
IOW, MEMW
tIOM1
tIOM2
MEMR, IOR
18183B-55
I/O to Memory Command Inactive Time
AEN, SBHE,
SA0–9
tIOCS1
tIOCS2
IOCS16
18183B-56
IOCS16 Timings
1-616
Am79C961
P R E L I M I N A R Y
AMD
SWITCHING WAVEFORMS: SHARED MEMORY MODE
SBHE,
SA0–15,
Stable
BPAM
tSFW1
tSFW2
MEMW
tSFW3
tSFW6
tSFR4
IOCHRDY
tSFW5
tSFW7
tSFW8
SD0-7
Stable
tSFW11
tSFW10
SRWE
BPCS
tSFW12
tSFW9
Stable
PRDB0-7
18183B-57
Flash Write Cycle
Am79C961
1-617
AMD
P R E L I M I N A R Y
SWITCHING WAVEFORMS: SHARED MEMORY MODE
REF,
Stable
SBHE
SA0-15
tSFR1
tSFR2
MEMR
tSFR3
tSFR4
IOCHRDY
tSFR7
tSFR5
SROE
tSFR6
BPCS
tSFR8
tSFR9
PRDB0–7
tSFR10
tSFR11
SD0–7
Stable
18183B-58
Flash Read Cycle
1-618
Am79C961
P R E L I M I N A R Y
AMD
SWITCHING WAVEFORMS: SHARED MEMORY MODE
tPR13
tPR13
PRAB
tPR14
tPR14
tPR15
tPR15
SRWE
PRDB
SRCS
(IRQ12)
18183B-59
SRAM Write on Private Bus (When FL_Sel is Enabled)
tPR4
tPR4
PRAB
SROE
tPR5
tPR6
tPR5
tPR6
PRDB
SRCS
(IRQ12)
18183B-60
SRAM Read on Private Bus (When FL_Sel is Enabled)
Am79C961
1-619
AMD
P R E L I M I N A R Y
SWITCHING WAVEFORMS: SHARED MEMORY MODE
tPR10
tPR10
PRAB
BPCS
tPR11
tPR12
tPR11
tPR12
PRDB
18183B-61
Boot PROM Read on Private Bus
tPR7
PRAB0–9
APCS
(IRQ15)
tPR8
tPR9
PRDB
18183B-62
Address PROM Read on Private Bus
1-620
Am79C961
P R E L I M I N A R Y
AMD
SWITCHING WAVEFORMS: SHARED MEMORY MODE
tPR17
tPR17
PRAB0
tPR14
tPR14
tPR18
tPR18
SRWE
PRDB
FLCS
18183B-63
Flash Write on Private Bus
tPR16
tPR16
PRAB0
FLOE
FLCS
tPR11
tPR12
tPR11
tPR12
PRDB
18183B-64
Flash Read on Private Bus
Am79C961
1-621
AMD
P R E L I M I N A R Y
SWITCHING WAVEFORMS: GPSI
(First Bit Preamble)
(Last Bit )
tGPT1
tGPT2
Transmit
Clock
(STDCLK)
tGPT3
Transmit
Data
(TXDAT)
tGPT3
tGPT3
Transmit
Enable
(TXEN)
tGPT4
Carrier
Present
tGPT5
(RXCRS)
(Note 1)
tGPT6
tGPT9
Collision
(CLSN)
(Note 2)
tGPT7
tGPT8
18183B-65
Notes:
1. If RXCRS is not present during transmission, LCAR bit in TMD3 will be set.
2. If CLSN is not present during or shortly after transmission, CERR in CSR0 will be set.
Transmit Timing
(First Bit Preamble)
(Address Type Designation Bit) (Last Bit)
tGPR1
tGPR2
tGPR3
Receive
Clock
(SRDCLK)
tGPR4
tGPR4
tGPR5
tGPR5
Receive
Data
(RXDAT)
tGPR6
Carrier
Present
(RXCRS)
tGPR8
tGPR9
tGPR10
tGPR7
Collision
(CLSN),
Active
tGPR11
tGPR12
Collision
(CLSN),
Inactive
(No Collision)
18183B-66
Receive Timing
1-622
Am79C961
P R E L I M I N A R Y
AMD
SWITCHING WAVEFORMS: EADI
Preamble
Data Field
SRDCLK (LED3)
SRD (LED2)
One Zero One
tEAD2
SFD
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4
Bit 8 Bit 0
Bit 7 Bit 8
tEAD1
SF/BD (LED1)
tEAD4
tEAD3
tEAD3
Accept
EAR (MAUSEL)
Reject
tEAD6
tEAD5
18183B-67
EADI Reject Timing
SWITCHING WAVEFORMS: JTAG (IEEE 1149.1) INTERFACE
tJTG1
TCK
tJTG2
tJTG3
tJTG4
TDI
TMS
TDO
tJTG5
tJTG6
tJTG7
tJTG8
18183B-68
Test Access Port Timing
Am79C961
1-623
AMD
P R E L I M I N A R Y
SWITCHING WAVEFORMS: AUI
tX1H
XTAL1
tX1L
tX1F
tX1R
tXI
ISTDCLK
(Note 1)
ITXEN
(Note 1)
1
1
1
1
ITXDAT+
(Note 1)
0
0
tDOTR
tDOTF
DO+
DO–
1
DO±
18183B-69
Note:
1. Internal signal and is shown for clarification only.
Transmit Timing—Start of Packet
XTAL1
ISTDCLK
(Note 1)
ITXEN
(Note 1)
1
1
ITXDAT+
(Note 1)
0
0
DO+
DO–
tDOETD
Typical > 200 ns
DO±
1
0
0
Bit (n–2)
Bit (n–1)
Bit (n)
18183B-70
Note:
1. Internal signal and is shown for clarification only.
Transmit Timing—End of Packet (Last Bit = 0)
1-624
Am79C961
P R E L I M I N A R Y
AMD
SWITCHING WAVEFORMS: AUI
XTAL1
ISTDCLK
(Note 1)
ITXEN
(Note 1)
1
1
1
ITXDAT+
(Note 1)
0
DO+
DO–
tDOETD
DO±
Typical > 250 ns
1
0
Bit (n–2)
Bit (n–1) Bit (n)
18183B-71
Note:
1. Internal signal and is shown for clarification only.
Transmit Timing—End of Packet (Last Bit = 1)
Am79C961
1-625
AMD
P R E L I M I N A R Y
SWITCHING WAVEFORMS: AUI
tPWKDI
DI+/–
VASQ
tPWKDI
tPWODI
18183B-72
Receive Timing Diagram
tPWKCI
CI+/–
VASQ
tPWOCI
18183B-73
tPWKCI
Collision Timing Diagram
tDOETD
40 mV
DO+/–
0 V
100 mV max.
80 Bit Times
18183B-74
Port DO ETD Waveform
1-626
Am79C961
P R E L I M I N A R Y
AMD
SWITCHING WAVEFORMS: 10BASE-T INTERFACE
tTR
tTF
TXD+
tTETD
TXP+
TXD–
TXP–
XMT
18183B-75
Transmit Timing
tPWPLP
TXD+
TXP+
TXD–
TXP–
tPWLP
tPERLP
18183B-76
Idle Link Test Pulse
Am79C961
1-627
AMD
P R E L I M I N A R Y
SWITCHING WAVEFORMS: 10BASE-T INTERFACE
VTSQ+
VTHS+
VTHS–
RXD±
VTSQ–
18183B-77
Receive Thresholds (LRT = 0 in CSR15 bit 9)
VLTSQ+
VLTHS+
VLTHS–
RXD±
VLTSQ–
18183B-78
Receive Thresholds (LRT = 1 in CSR15 bit 9)
1-628
Am79C961
APPENDIX A
PCnet-ISA+ Compatible Media
Interface Modules
PCnet-ISA+ COMPATIBLE 10BASE-T
FILTERS AND TRANSFORMERS
The table below provides a sample list of PCnet-ISA+
compatible 10BASE-T filter and transformer modules
available from various vendors. Contact the respective
manufacturer for a complete and updated listing of
components.
Filters
and
Filters
Filters
Filters
Transformers Transformers Transformers
Manufacturer
Bel Fuse
Part No.
Package
Transformers and Choke
Dual Choke Dual Chokes
A556-2006-DE 16-pin 0.3” DIL
0556-2006-00 14-pin SIP
0556-2006-01 14-pin SIP
0556-6392-00 16-pin 0.5” DIL
√
√
Bel Fuse
Bel Fuse
√
√
Bel Fuse
Halo Electronics
Halo Electronics
Halo Electronics
PCA Electronics
PCA Electronics
PCA Electronics
Pulse Engineering
Pulse Engineering
Pulse Engineering
Pulse Engineering
Valor Electronics
Valor Electronics
FD02-101G
FD12-101G
FD22-101G
EPA1990A
EPA2013D
EPA2162
PE-65421
PE-65434
PE-65445
PE-65467
PT3877
16-pin 0.3” DIL
16-pin 0.3” DIL
16-pin 0.3” DIL
16-pin 0.3” DIL
16-pin 0.3” DIL
16-pin 0.3” SIP
16-pin 0.3” DIL
16-pin 0.3” SIL
16-pin 0.3” DIL
12-pin 0.5” SMT
16-pin 0.3” DIL
16-pin 0.3” DIL
√
√
√
√
√
√
√
√
√
√
√
FL1043
√
PCnet-ISA+ Compatible AUI Isolation
Transformers
various vendors. Contact the respective manufacturer
for a complete and updated listing of components.
The table below provides a sample list of PCnet-ISA+
compatible AUI isolation transformers available from
Manufacturer
Bel Fuse
Part No.
A553-0506-AB
S553-0756-AE
TD01-0756K
TG01-0756W
EP9531-4
Package
Description
50 µH
16-pin 0.3” DIL
16-pin 0.3” SMD
16-pin 0.3” DIL
16-pin 0.3” SMD
16-pin 0.3” DIL
16-pin 0.3” DIL
16-pin 0.3” SMT
16-pin 0.3” DIL
16-pin 0.3” SMD
Bel Fuse
75 µH
Halo Electronics
Halo Electronics
PCA Electronics
Pulse Engineering
Pulse Engineering
Valor Electronics
Valor Electronics
75 µH
75 µH
50 µH
PE64106
50 µH
PE65723
75 µH
LT6032
75 µH
ST7032
75 µH
Am79C961
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AMD
PCnet-ISA+ Compatible DC/DC Converters
The table below provides a sample list of PCnet-ISA+
compatible DC/DC converters available from various
vendors. Contact the respective manufacturer for a
complete and updated listing of components.
Manufacturer
Halo Electronics
Halo Electronics
PCA Electronics
PCA Electronics
PCA Electronics
Valor Electronics
Valor Electronics
Part No.
DCU0-0509D
DCU0-0509E
EPC1007P
EPC1054P
EPC1078
Package
24-pin DIP
24-pin DIP
24-pin DIP
24-pin DIP
24-pin DIP
24-pin DIP
24-pin DIP
Voltage
5/-9
Remote On/Off
No
Yes
No
5/-9
5/-9
5/-9
Yes
Yes
No
5/-9
PM7202
5/-9
PM7222
5/-9
Yes
MANUFACTURER CONTACT
INFORMATION
Contact the following companies for further infor-
mation on their products:
Company
Bel Fuse
U.S. and Domestic
Asia
Europe
Phone:
FAX:
(201) 432-0463
(201) 432-9542
852-328-5515
852-352-3706
33-1-69410402
33-1-69413320
Halo Electronics
Phone:
FAX:
(415) 969-7313
(415) 367-7158
65-285-1566
65-284-9466
PCA Electronics
(HPC in Hong Kong)
Phone:
FAX:
818-892-0761
818-894-5791
852-553-0165
852-873-1550
33-1-44894800
33-1-42051579
Pulse Engineering
Phone:
FAX:
(619) 674-8100
(619) 675-8262
852-425-1651
852-480-5974
353-093-24107
353-093-24459
Valor Electronics
Phone:
FAX:
(619) 537-2500
(619) 537-2525
852-513-8210
852-513-8214
49-89-6923122
49-89-6926542
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Am79C961
APPENDIX B
Layout Recommendations
for Reducing Noise
via to VDD plane
DECOUPLING LOW-PASS R/C
FILTER DESIGN
The PCnet-ISA+ controller is an integrated, single-chip
Ethernet controller, which contains both digital and ana-
log circuitry. The analog circuitry contains a high speed
Phase-Locked Loop (PLL) and Voltage Controlled
Oscillator (VCO). Because of the mixed signal charac-
teristics of this chip, some extra precautions must be
taken into account when designing with this device.
VDD Pin
VSS Pin
PCnet-ISA+
via to VSS plane
Described in this section is a simple decoupling low-
pass R/C filter that can significantly increase noise im-
munity of the PLL circuit, thus, prevent noise from
disrupting the VCO. Bit error rate, a common measure-
ment of network performance, as a result can be
drastically reduced. In certain cases the bit error rate
can be reduced by orders of magnitude.
AMD recommends that at least one low-frequency bulk
decoupling capacitor be used in the area of the
PCnet-ISA+ controller. 22 µF capacitors have worked
well for this. In addition, a total of four or five 0.1 µF ca-
pacitors have proven sufficient around the DVSS and
DVDD pins that supply the drivers of the ISA bus
output pins.
Implementation of this filter is not necessary to achieve
a functional product that meets the IEEE 802.3 specifi-
cation and provides adequate performance. However,
this filter will help designers meet those specifications
with more margin.
Analog Decoupling
The most critical pins are the analog supply and ground
pins. All of the analog supply and ground pins are lo-
cated in one corner of the device. Specific requirements
of the analog supply pins are listed below.
Digital Decoupling
AVSS1 and AVDD3
The DVSS pins that are sinking the most current are
those that provide the ground for the ISA bus output sig-
nals since these outputs require 24 mA drivers. The
DVSS10 and DVSS12 pins provide the ground for the
internal digital logic. In addition, DVSS11 provides
ground for the internal digital and for the Input and
I/O pins.
These pins provide the power and ground for the
Twisted Pair and AUI drivers. Hence, they are very
noisy. A dedicated 0.1 µF capacitor between these pins
is recommended.
AVSS2 and AVDD2
These pins are the most critical pins on the PCnet-ISA+
controller because they provide the power and ground
for the PLL portion of the chip. The VCO portion of the
PLL is sensitive to noise in the 60 kHz–200 kHz. range.
To prevent noise in this frequency range from disrupting
the VCO, AMD strongly recommends that the low-pass
filter shown below be implemented on these pins. Tests
using this filter have shown significantly increased noise
immunity and reduced Bit Error Rate (BER) statistics in
designs using the PCnet-ISA+ controller.
The CMOS technology used in fabricating the
PCnet-ISA+ controller employs an n-type substrate. In
this technology, all VDD pins are electrically connected to
eachotherinternally. Hence, inafour-layerboard, when
decoupling between VDD and critical VSS pins, the spe-
cific VDD pin that you connect to is not critical. In fact, the
VDD connection of the decoupling capacitor can be
made directly to the power plane, near the closest VDD
pin to the VSS pin of interest. However, we recommend
that the VSS connection of the decoupling capacitor be
made directly to the VSS pin of interest as shown.
Am79C961
1-631
AMD
voltage drop across the resistor, the R value should not
be more than 20 Ω.
33 µF to 6.8 µF
VDD Plane
AVDD2
Pin 108
R
C
2.7 Ω
33 µF
AVSS2
Pin 98
R1
4.3 Ω
6.8 Ω
10 Ω
20 Ω
22 µF
15 µF
10 µF
6.8 µF
1 Ω to 20 Ω
PCnet-ISA+
To determine the value for the resistor and capacitor,
the formula is:
AVSS2 and AVDD2/AVDD4
R * C ≥ 88
These pins provide power and ground for the AUI and
twisted pair receive circuitry. No specific decoupling
has been necessary on these pins.
Where R is in ohms and C is in microfarads. Some pos-
sible combinations are given below. To minimize the
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Am79C961
APPENDIX C
Sample
Configuration File
that is an ethernet controller. There are no compatible
devices with this logical device. The following record
should be returned by the card during the identification
process.
SAMPLE CONFIGURATION FILE
The following is a sample configuration file for the
PCnet-ISA+ device used in an AMD Ethernet card. This
card requires one DMA channel, one interrupt, one I/O
port in the 0x200-0x3FF range (0x20 bytes aligned).
The vendor ID of AMD is AMD. The vendor assigned
part number for this card is 2100 and the serial number
is 0x12345678. The card has only one logical device,
Note: All data stored in the EEPROM is stored in bit-
reversal format. Each word (16 bits) must be written
into the EEPROM with bit 15 swapped with bit 0, bit
14 swapped with bit 1, etc.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Plug and Play Header
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
DB 0x04
DB 0x43
DB 0x00
DB 0x21
DB 0x78
DB 0x56
DB 0x34
DB 0x12
DB Checksum
; Vendor EISA ID Byte 0
; Vendor EISA ID Byte 1
; Vendor Assigned ID Byte 0
; Vendor Assigned ID Byte 1
; Serial Number byte 0
; Serial Number byte 1
; Serial Number byte 2
; Serial Number byte 3
; Checksum calculated on above bits
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Plug and Play Version
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
DB 0x0A
DB 0x10
; Small Item, Plug and Play version
; BCD major version [7:4] = 1
; BCD minor version [3:0] = 0
; Vendor specific version number
DB 0x00
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Identifier String
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
DB 0x82
; Large Item, Type Identifier string (ANSI)
; Length Byte 0 (28 bytes)
; Length Byte 1
DB 0x1c
DB 0x00
DB ”AMD Ethernet Network Adapter”
; Identifier String
Am79C961
1-633
AMD
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Logical Device ID
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
DB 0x15
DB 0x11
DB 0x11
DB 0x22
DB 0x22
DB 0x01
; Small Item, Type Logical Device ID
; Logical Device ID byte 0
; Logical Device ID byte 1
; Logical Device ID byte 2
; Logical Device ID byte 3
; Logical Device Flags [0] – required for boot
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; I/O Port Descriptor
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
DB 0x47
DB 0x00
DB 0x00
DB 0x02
DB 0xE0
DB 0x03
DB 0x20
DB 0x18
; Small Item, type I/O Port
; Information, [0] = 0, 10 bit Decode
; Minimum Base Address [07:00]
; Minimum Base Address [15:08]
; Maximum Base Address [07:00]
; Maximum Base Address [15:08]
; Base Address Increment (32 ports)
; Number of ports required
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; DMA Descriptor
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
DB 0x2A
DB 0xE8
DB 0x06
; Small Item, type DMA Format
; DMA channel mask ch 3, 5, 6, 7
; 16–Bit only, Bus Master
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;IRQ Format
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
DB 0x23
DB 0x38
DB 0x9E
DB 0x01
; Small Item, type IRQ Format
; IRQs supported [7:0]
; IRQs supported [15:8]
3, 4, 5
9, 10, 11, 12, 15
; Information: High true, edge
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; End Tag
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
DB 0x78
; Small item, type END TAG
; Checksum
DB Checksum
1-634
Am79C961
APPENDIX D
Alternative Method
for Initialization
ThePCnet-ISA+ controllermaybeinitializedbyperform-
ing I/O writes only. That is, data can be written directly to
the appropriate control and status registers (CSR)
instead of reading from the Initialization Block in
memory. The registers that must be written are shown in
the table below. These are followed by writing the
START bit in CSR0.
Control and
Status Register
Comment
LADRF[15:0]
LADRF[31:16]
LADRF[47:32]
LADRF[63:48]
PADR[15:0]
PADR[31:16]
PADR[47:32]
Mode
CSR8
CSR9
CSR10
CSR11
CSR12
CSR13
CSR14
CSR15
CSR24-25
CSR30-31
CSR47
BADR
BADX
POLLINT
CSR76
RCVRL
CSR78
XMTRL
Note: The INIT bit must not be set or the initialization block will
be accessed instead.
Am79C961
1-635
APPENDIX E
Introduction of the
Look Ahead Packet Processing (LAPP) Concept
A driver for the PCnet-ISA+ controller would normally
require that the CPU copy receive frame data from the
controller’s buffer space to the application’s buffer
space after the entire frame has been received by the
controller. For applications that use a ping-pong win-
dowing style, the traffic on the network will be halted
until the current frame has been completely processed
by the entire application stack. This means that the time
between last byte of a receive frame arriving at the
client’s Ethernet controller and the client’s transmission
of the first byte of the next outgoing frame will be sepa-
rated by:
the reception of the frame actually ends at the network,
and how can the CPU be instructed to perform these
tasks during the network reception time?
The answer depends upon exactly what is happening in
thedriverandapplicationcode, butthestepsthatcanbe
performed at the same time as the receive data
are arriving include as much as the first three steps and
part of the fourth step shown in the sequence
above. By performing these steps before the entire
frame has arrived, the frame throughput can be sub-
stantially increased.
A good increase in performance can be expected when
the first three steps are performed before the end of the
network receive operation. A much more significant per-
formance increase could be realized if the PCnet-ISA+
controller could place the frame data directly into the
application’s buffer space; (i.e. eliminate the need for
step four.) In order to make this work, it is necessary
that the application buffer pointer be determined before
the frame has completely arrived, then the buffer pointer
in the next desriptor for the receive frame would need to
be modified in order to direct the PCnet-ISA+ controller
to write directly to the application buffer. More details on
this operation will be given later.
1) the time that it takes the client’s CPU’s interrupt
proceduretopasssoftwarecontrolfromthecurrent
task to the driver
2) plus the time that it takes the client driver to pass
the header data to the application and request an
application buffer
3) plus the time that it takes the application to gener-
ate the buffer pointer and then return the buffer
pointer to the driver
4) plus the time that it takes the client driver to transfer
all of the frame data from the controller’s buffer
space into the application’s buffer space and then
call the application again to process the complete
frame
An alternative modification to the existing system can
gain a smaller, but still significant improvement in per-
formance. This alternative leaves step four unchanged
in that the CPU is still required to perform the copy
operation, but it allows a large portion of the copy opera-
tion to be done before the frame has been completely
received by the controller, (i.e. the CPU can perform the
copy operation of the receive data from the PCnet-ISA+
controller’s buffer space into the application buffer
space before the frame data has completely arrived
from the network.) This allows the copy operation of
step four to be performed concurrently with the arrival of
network data, rather than sequentially, following the end
of network receive activity.
5) plus the time that it takes the application to process
the frame and generate the next outgoing frame
6) plus the time that it takes the client driver to set up
the descriptor for the controller and then write a
TDMD bit to CSR0
The sum of these times can often be about the same as
the time taken to actually transmit the frames on the
wire, thereby yielding a network utilization rate of less
than 50%.
AnimportantthingtonoteisthatthePCnet-ISA+ control-
ler’s data transfers to its buffer space are such that the
system bus is needed by the PCnet-ISA+ controller for
approximately 4% of the time. This leaves 96% of the
sytem bus bandwidth for the CPU to perform some of
the inter–frame operations in advance of the completion
of network receive activity, if possible. The question
then becomes: how much of the tasks that need to be
Outline of the LAPP Flow:
This section gives a suggested outline for a driver that
utilizes the LAPP feature of the PCnet-ISA+ controller.
Note: The labels in the following text are used as refer-
ences in the timeline diagram that follows.
performed between reception of
a frame and
transmission of the next frame can be performed before
1-636
Am79C961
AMD
SETUP:
message into that space. Only when the message
does not fit will it signal a buffer error condition—
there is no need to panic at the point that it discov-
ers that it does not yet own descriptor number 3.]
The driver should set up descriptors in groups of 3, with
theOWNandSTPbitsofeachsetofthreedescriptorsto
read as follows: 11b, 10b, 00b.
S2: The first task of the driver’s interrupt service routine
is to collect the header information from the
PCnet-ISA+ controller’s first buffer and pass it to
the application.
An option bit (LAPPEN) exists in CSR3, bit position 5.
The software should set this bit. When set, the LAPPEN
bit directs the PCnet-ISA+ to generate an INTERRUPT
when STP has been written to a receive descriptor by
the PCnet-ISA+ controller.
S3: The application will return an application buffer
pointer to the driver. The driver will add an offset to
the application data buffer pointer, since the
PCnet-ISA+ controller will be placing the first por-
tion of the message into the first and second buff-
ers. (The modified application data buffer pointer
willonlybedirectlyusedbythePCnet-ISA+ control-
ler when it reaches the third buffer.) The driver will
place the modified data buffer pointer into the final
descriptor of the group (#3) and will grant owner-
ship of this descriptor to the PCnet-ISA+ controller.
FLOW:
The PCnet-ISA+ controller polls the current receive de-
scriptor at some point in time before a message arrives.
The PCnet-ISA+ controller determines that this receive
buffer is OWNed by the PCnet-ISA+ controller and it
stores the descriptor information to be used when a
message does arrive.
N0: Frame preamble appears on the wire, followed by
SFD and destination address.
C5: Interleaved with S2, S3 and S4 driver activity, the
PCnet-ISA+ controller will write frame data to buffer
number 2.
N1: The 64th byte of frame data arrives from the wire.
This causes the PCnet-ISA+ controller to begin
frame data DMA operations to the first buffer.
S4: The driver will next proceed to copy the contents of
the PCnet-ISA+ controller’s first buffer to the begin-
ning of the application space. This copy will be to
the exact (unmodified) buffer pointer that was
passed by the application.
C0: When the 64th byte of the message arrives, the
PCnet-ISA+ controller performs a lookahead op-
eration to the next receive descriptor. This descrip-
tor should be owned by the PCnet-ISA+ controller.
C1: The PCnet-ISA+ controller intermittently requests
the bus to transfer frame data to the first buffer as it
arrives on the wire.
S5: After copying all of the data from the first buffer into
the beginning of the application data buffer, the
driver will begin to poll the ownership bit of the sec-
ond descriptor. The driver is waiting for the PCnet-
ISA+ controller to finish filling the second buffer.
S0: The driver remains idle.
C2: When the PCnet-ISA+ controller has completely
filled the first buffer, it writes status to the first
descriptor.
C6: At this point, knowing that it had not previously
owned the third descriptor, and knowing that the
current message has not ended (there is more data
in the fifo), the PCnet-ISA+ controller will make a
“last ditch lookahead” to the final (third) descriptor;
This time, the ownership will be TRUE (i.e. the de-
scriptor belongs to the controller), because the
driver wrote the application pointer into this de-
scriptor and then changed the ownership to give
the descriptor to the PCnet-ISA+ controller back at
S3. Note that if steps S1, S2 and S3 have not com-
pleted at this time, a BUFF error will result.
C3: When the first descriptor for the frame has been
written, changing ownership from the PCnet-ISA+
controllertotheCPU, thePCnet-ISA+ controllerwill
generate an SRP INTERRUPT. (This interrupt ap-
pears as a RINT interrupt in CSR0.)
S1: The SRP INTERRUPT causes the CPU to switch
tasks to allow the PCnet-ISA+ controller’s driver to
run.
C4: During the CPU interrupt-generated task switch-
ing, the PCnet-ISA+ controller is performing a
lookahead operation to the third descriptor. At this
point in time, the third descriptor is owned by the
CPU. [Note: Even though the third buffer is not
owned by the PCnet-ISA+ controller, existing AMD
Ethernet controllers will continue to perform data
DMA into the buffer space that the controller al-
ready owns (i.e. buffer number 2). The controller
does not know if buffer space in buffer number 2
will be sufficient or not, for this frame, but it has no
way to tell except by trying to move the entire
C7: After filling the second buffer and performing the
last chance lookahead to the next descriptor, the
PCnet-ISA+ controller will write the status and
change the ownership bit of descriptor number 2.
S6: After the ownership of descriptor number 2 has
been changed by the PCnet-ISA+ controller, the
next driver poll of the 2nd descriptor will show
ownership granted to the CPU. The driver now
copies the data from buffer number 2 into the “mid-
dle section” of the application buffer space. This
Am79C961
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AMD
operation is interleaved with the C7 and C8
operations.
C9: When the PCnet-ISA+ controller has finished all
data DMA operations, it writes status and changes
ownership of descriptor number 3.
C8: The PCnet-ISA+ controller will perform data DMA
to the last buffer, whose pointer is pointing to appli-
cation space. Data entering the last buffer will not
needtheinfamous“doublecopy”thatisrequiredby
existing drivers, since it is being placed directly into
the application buffer space.
S8: The driver sees that the ownership of descriptor
number 3 has changed, and it calls the application
to tell the application that a frame has arrived.
S9: The application processes the received frame and
generates the next TX frame, placing it into a TX
buffer.
N2: The message on the wire ends.
S7: When the driver completes the copy of buffer num-
ber 2 data to the application buffer space, it begins
polling descriptor number 3.
S10:The driver sets up the TX descriptor for the
PCnet-ISA+ controller.
Ethernet
Wire
activity:
Ethernet
Controller
activity:
Software
activity:
S10: Driver sets up TX descriptor.
S9: Application processes packet, generates TX packet.
S8: Driver calls application
to tell application that
{
packet has arrived.
C9: Controller writes descriptor #3.
S7: Driver polls descriptor of buffer #3.
C8: Controller is performing intermittent
bursts of DMA to fill data buffer #3.
N2: EOM
Buffer
#3
S6: Driver copies data from buffer #2 to the application buffer.
C7: Controller writes descriptor #2.
S5: Driver polls descriptor #2.
C6: "Last chance" lookahead to
descriptor #3 (OWN).
S4: Driver copies data from buffer #1 to the application buffer.
S3: Driver writes modified application
C5: Controller is performing intermittent
bursts of DMA to fill data buffer #2.
pointer to descriptor #3.
Buffer
#2
} {
S2: Driver call to application to
get application buffer pointer.
C4: Lookahead to descriptor #3 (OWN).
S1: Interrupt latency.
C3: SRP interrupt
}
is generated.
C2: Controller writes descriptor #1.
S0: Driver is idle.
Buffer
#1
C1: Controller is performing intermittent
bursts of DMA to fill data buffer #1.
C0: Lookahead to descriptor #2.
N1: 64th byte of packet
data arrives.
{
N0: Packet preamble, SFD
and destination address
are arriving.
18183B-79
Figure 1. Look Ahead Packet Processing (LAPP) Timeline
Am79C961
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AMD
LAPP Enable Software Requirements
LAPP Enable Rules for Parsing of
Descriptors
Software needs to set up a receive ring with descriptors
formed into groups of 3. The first descriptor of each
group should have OWN = 1 and STP = 1, the second
descriptor of each group should have OWN = 1 and STP
= 0. The third descriptor of each group should have
OWN = 0 and STP = 0. The size of the first buffer (as
indicated in the first descriptor), should beat least equal
to the largest expected header size; However, for maxi-
mum efficiency of CPU utilization, the first buffer size
shouldbelargerthantheheadersize. Itshouldbeequal
to the expected number of message bytes, minus the
time needed for Interrupt latency and minus the applica-
tion call latency, minus the time needed for the driver to
write to the third descriptor, minus the time needed for
the driver to copy data from buffer #1 to the application
bufferspace, andminusthetimeneededforthedriverto
copy data from buffer #2 to the application buffer space.
Note that the time needed for the copies performed by
the driver depends upon the sizes of the 2nd and 3rd
buffers, and that the sizes of the second and third buff-
ers need to be set accoring to the time needed for the
data copy operations! This means that an iterative self–
adjusting mechanism needs to be placed into the soft-
ware to determine the correct buffer sizing for optimal
operation. Fixed values for buffer sizes may be used; In
such a case, the LAPP method will still provide a signifi-
cant performance increase, but the performance in-
crease will not be maximized.
When using the LAPP method, software must use a
modified form of descriptor parsing as follows:
Software will examine OWN and STP to determine
where a RCV frame begins. RCV frames will only begin
in buffers that have OWN = 0 and STP = 1.
Software shall assume that a frame continues until it
finds either ENP = 1 or ERR= 1.
Software must discard all descriptors with OWN = 0 and
STP=0andmovetothenextdescriptorwhensearching
for the beginning of a new frame; ENP and ERR should
be ignored by software during this search.
Software cannot change an STP value in the receive
descriptor ring after the initial setup of the ring is com-
plete, even if software has ownership of the STP de-
scriptor unless the previous STP descriptor in the ring is
also OWNED by the software.
When LAPPEN = 1, then hardware will use a modified
form of descriptor parsing as follows:
The controller will examine OWN and STP to determine
where to begin placing a RCV frame. A new RCV frame
will only begin in a buffer that has OWN = 1 and STP = 1.
The controller will always obey the OWN bit for deter-
mining whether or not it may use the next buffer for a
chain.
The following diagram illustrates this setup for a receive
ring size of 9:
The controller will always mark the end of a frame with
either ENP = 1 or ERR= 1.
Descriptor
#9
OWN = 0 STP = 0
SIZE = S6
Descriptor
#8
OWN = 1 STP = 0
SIZE = S1+S2+S3+S4
A
= Expected message size in bytes
S1 = Interrupt latency
S2 = Application call latency
S3 =Time needed for driver to write
to third descriptor
Descriptor
#7
OWN = 1 STP = 1
SIZE = A-(S1+S2+S3+S4+S6)
S4 = Time needed for driver to copy
data from buffer #1 to
Descriptor
#6
OWN = 0 STP = 0
SIZE = S6
application buffer space
S6 = Time needed for driver to copy
data from buffer #2 to
Descriptor
#5
OWN = 1 STP = 0
SIZE = S1+S2+S3+S4
application buffer space
Descriptor
#4
OWN = 1 STP = 1
SIZE = A-(S1+S2+S3+S4+S6)
Note that the times needed for tasks S1, S2, S3,
Descriptor
#3
OWN = 0 STP = 0
SIZE = S6
S4, and S6 should be divided by 0.8 ms to yield
an equivalent number of network byte times
before subtracting these quantities from the
Descriptor
#2
OWN = 1 STP = 0
SIZE = S1+S2+S3+S4
expected message size A.
Descriptor
#1
OWN = 1 STP = 1
SIZE = A-(S1+S2+S3+S4+S6)
18183B-80
Figure 2. LAPP 3 Buffer Grouping
Am79C961
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AMD
The controller will discard all descriptors with OWN = 1
and STP = 0 and move to the next descriptor when
searching for a place to begin a new frame. It dis-
cards these desciptors by simply changing the owner-
ship bit from OWN=1 to OWN = 0. Such a descriptor is
unused for receive purposes by the controller, and the
driver must recognize this. (The driver will recognize
this if it follows the software rules.)
Some Examples of LAPP Descriptor
Interaction
Choose an expected frame size of 1060 bytes.
Choose buffer sizes of 800, 200 and 200 bytes.
1) Assume that a 1060 byte frame arrives correctly,
and that the timing of the early interrupt and the
software is smooth. The descriptors will have
changed from:
The controller will ignore all descriptors with OWN = 0
and STP = 0 and move to the next descriptor when
searching for a place to begin a new frame. In other
words, the controller is allowed to skip entries in the ring
that it does not own, but only when it is looking for a
place to begin a new frame.
Before the
After the
Descriptor
Number
Frame Arrived
STP
Frame Has Arrived
Comments
(After Frame Arrival)
OWN
ENP*
OWN
STP
ENP*
1
2
3
4
1
1
0
1
1
0
0
1
X
X
X
X
0
0
0
1
1
0
0
1
0
0
1
X
Bytes 1–800
Bytes 801–1000
Bytes 1001–1060
Controller’s current
location
5
6
1
0
1
0
0
1
X
X
X
1
0
1
0
0
1
X
X
X
Not yet used
Not yet used
Not yet used
etc.
*ENP or ERR
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Am79C961
AMD
2) Assume that instead of the expected 1060 byte
frame, a 900 byte frame arrives, either because
there was an error in the network, or because this is
the last frame in a file transmission sequence.
Before the
After the
Descriptor
Number
Frame Arrived
STP
Frame Has Arrived
Comments
(After Frame Arrival)
OWN
ENP*
OWN
STP
ENP*
1
2
3
4
1
1
0
1
1
0
0
1
X
X
X
X
0
0
0
1
1
0
0
1
0
1
Bytes 1–800
Bytes 801–900
Discarded buffer
?**
X
Controller’s current
location
5
6
1
0
1
0
0
1
X
X
X
1
0
1
0
0
1
X
X
X
Not yet used
Not yet used
Not yet used
etc.
*ENP or ERR
** Note that the PCnet-ISA+ controller might write a ZERO to ENP location in the 3rd descriptor. Here are the two possibilities:
1) If the controller finishes the data transfers into buffer number 2 after the driver writes the application’s modified buffer pointer
into the third descriptor, then the controller will write a ZERO to ENP for this buffer and will write a ZERO to OWN and STP.
2) If the controller finishes the data transfers into buffer number 2 before the driver writes the application’s modified buffer
pointer into the third descriptor, then the controller will complete the frame in buffer number two and then skip the then un-
owned third buffer. In this case, the PCnet-ISA+ controller will not have had the opportunity to RESET the ENP bit in this
descriptor, and it is possible that the software left this bit as ENP=1 from the last time through the ring. Therefore, the soft-
ware must treat the location as a don’t care; The rule is, after finding ENP=1 (or ERR=1) in descriptor number 2, the software
must ignore ENP bits until it finds the next STP=1.
Am79C961
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AMD
3) Assume that instead of the expected 1060 byte
frame, a 100 byte frame arrives, because there
was an error in the network, or because this is the
last frame in a file transmission sequence, or per-
haps because it is an acknowledge frame.
Before the
After the
Descriptor
Number
Frame Arrived
STP
Frame Has Arrived
Comments
(After Frame Arrival)
OWN
ENP*
OWN
STP
ENP*
1
2
3
4
1
1
0
1
1
0
0
1
X
X
X
X
0
0
0
1
1
0
0
1
1
0***
?**
X
Bytes 1–100
Discarded buffer
Discarded buffer
Controller’s current
location
5
6
1
0
1
0
0
1
X
X
X
1
0
1
0
0
1
X
X
X
Not yet used
Not yet used
Not yet used
etc.
*ENP or ERR
** Same as note in case 2 above, except that in this case, it is very unlikely that the driver can respond to the interrupt and get the
pointer from the application before the PCnet-ISA+ controller has completed its poll of the next descriptors. This means that
for almost all occurrences of this case, the PCnet-ISA+ controller will not find the OWN bit set for this descriptor and therefore,
the ENP bit will almost always contain the old value, since the PCnet-ISA+ controller will not have had an opportunity to modify
it.
***Note that even though the PCnet-ISA+ controller will write a ZERO to this ENP location, the software should treat the location
as a don’t care, since after finding the ENP=1 in descriptor number 2, the software should ignore ENP bits until it finds the next
STP=1.
Buffer Size Tuning
perfectly timed system will have the values for S5 and
S7 at a minimum.
For maximum performance, buffer sizes should be ad-
justed depending upon the expected frame size and the
values of the interrupt latency and application call la-
tency. The best driver code will minimize the CPU utili-
zation while also minimizing the latency from frame end
on the network to frame sent to application from driver
(frame latency). These objectives are aimed at increas-
ing throughput on the network while decreasing CPU
utilization.
An average increase in performance can be achieved if
the general guidelines of buffer sizes in Figure 2 is fol-
lowed. However, as was noted earlier, the correct sizing
forbufferswilldependupontheexpectedmessagesize.
Therearetwoproblemswithrelatingexpectedmessage
size with the correct buffer sizing:
1) Message sizes cannot always be accurately pre-
dicted, since a single application may expect differ-
ent message sizes at different times, therefore, the
buffer sizes chosen will not always maximize
throughput.
Note that the buffer sizes in the ring may be altered at
any time that the CPU has ownership of the correspond-
ing descriptor. The best choice for buffer sizes will
maximize the time that the driver is swapped out, while
minimizing the time from the last byte written by the
PCnet-ISA+ controller to the time that the data is passed
from the driver to the application. In the diagram, this
corresponds to maximizing S0, while minimizing the
time between C9 and S8. (The timeline happens to
show a minimal time from C9 to S8.)
2) Within a single application, message sizes might
be somewhat predicatable, but when the same
driver is to be shared with multiple applications,
there may not be a common predictable message
size.
Additional problems occur when trying to define the cor-
rect sizing because the correct size also depends upon
the interrupt latency, which may vary from system to
system, depending upon both the hardware and the
software installed in each system.
Note that by increasing the size of buffer number 1, we
increase the value of S0. However, when we increase
the size of buffer number 1, we also increase the value
of S4. If the size of buffer number 1 is too large, then the
driver will not have enough time to perform tasks S2, S3,
S4, S5 and S6. The result is that there will be delay from
the execution of task C9 until the execution of taskS8. A
In order to deal with the unpredictable nature of the
message size, the driver can implement a self tuning
1-642
Am79C961
AMD
mechanism that examines the amount of time spent in
tasks S5 and S7 as such: While the driver is polling for
each descriptor, it could count the number of poll opera-
tions performed and then adjust the number 1 buffer
size to a larger value, by adding “t” bytes to the buffer
count, if the number of poll operations was greater than
“x”. If fewer than “x” poll operations were needed for
each of S5 and S7, then the software should adjust the
buffer size to a smaller value by, subtracting “y” bytes
from the buffer count. Experiments with such a tuning
mechanism must be performed to determine the best
values for “X” and “y.”
The time from the end of frame arrival on the wire to
delivery of the frame to the application is labeled as
frame latency. For the one-interrupt method, frame la-
tency is minimized, while CPU utilization increases. For
the two-interrupt method, frame latency becomes
greater, while CPU utilization decreases.
Note that some of the CPU time that can be applied to
non-Ethernet tasks is used for task switching in the
CPU. One task switch is required to swap a non-
Ethernet task into the CPU (after S7A) and a second
taskswitchisneededtoswaptheEthernetdriverbackin
again (at S8A). If the time needed to perform these task
switches exceeds the time saved by not polling descrip-
tors, then there is a net loss in performance with this
method. Therefore, the NEW WORD method imple-
mented should be carefully chosen.
Note whenever the size of buffer number 1 is adjusted,
buffer sizes for buffer number 2 and buffer 3 should also
be adjusted.
In some systems the typical mix of receive frames on a
network for a client application consists mostly of large
data frames, with very few small frames. In this case, for
maximum efficiency of buffer sizing, when a frame ar-
rives under a certain size limit, the driver should not
adjust the buffer sizes in response to the short frame.
Figure 3 shows the event flow for the two-interrupt
method.
Figure 4 shows the buffer sizing for the two-interrupt
method. Note that the second buffer size will be about
the same for each method.
An Alternative LAPP Flow – the TWO Interrupt
Method
There is another alternative which is a marriage of the
two previous methods. This third possibility would use
the buffer sizes set by the two-interrupt method, but
would use the polling method of determining frame end.
This will give good frame latency but at the price of very
high CPU utilization.
An alternative to the above suggested flow is to use two
interrupts, one at the start of the Receive frame and the
other at the end of the receive frame, instead of just
looking for the SRP interupt as was described above.
This alternative attempts to reduce the amount of time
that the software “wastes” while polling for descriptor
own bits. This time would then be available for other
CPU tasks. It also minimizes the amount of time the
CPU needs for data copying. This savings can be ap-
plied to other CPU tasks.
Andstill, thereareevenmorecompromisepositionsthat
use various fixed buffer sizes and effectively, the flow of
the one-interrupt method. All of these compromises will
reduce the complexity of the one-interrupt method by
removing the heuristic buffer sizing code, but they all
become less efficient than heuristic code would allow.
Am79C961
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AMD
Ethernet
Ethernet
Controller
activity:
Wire
Software
activity:
activity:
S10: Driver sets up TX descriptor.
S9: Application processes packet, generates TX packet.
S8: Driver calls application
to tell application that
{
packet has arrived.
S8A: Interrupt latency.
C10: ERP interrupt
}
is generated.
C9: Controller writes descriptor #3.
S7: Driver is swapped out, allowing a non-Etherenet
application to run.
C8: Controller is performing intermittent
bursts of DMA to fill data buffer #3.
S7A: Driver Interrupt Service
Routine executes
{
RETURN.
N2: EOM
Buffer
#3
S6: Driver copies data from buffer #2 to the application buffer.
C7: Controller writes descriptor #2.
S5: Driver polls descriptor #2.
C6: "Last chance" lookahead to
descriptor #3 (OWN).
S4: Driver copies data from buffer #1 to the application buffer.
S3: Driver writes modified application
C5: Controller is performing intermittent
bursts of DMA to fill data buffer #2.
pointer to descriptor #3.
Buffer
#2
} {
S2: Driver call to application to
get application buffer pointer.
C4: Lookahead to descriptor #3 (OWN).
S1: Interrupt latency.
C3: SRP interrupt
}
is generated.
C2: Controller writes descriptor #1.
S0: Driver is idle.
Buffer
#1
C1: Controller is performing intermittent
bursts of DMA to fill data buffer #1.
C0: Lookahead to descriptor #2.
N1: 64th byte of packet
data arrives.
{
N0: Packet preamble, SFD
and destination address
are arriving.
18183B-81
Figure 3. LAPP Timeline for TWO-INTERRUPT Method
1-644
Am79C961
AMD
Descriptor
#9
OWN = 0
STP = 0
SIZE = 1518 - (S1+S2+S3+S4+HEADER_SIZE)
Descriptor
#8
OWN = 1
SIZE = S1+S2+S3+S4
STP = 0
STP = 1
A
= Expected message size in bytes
S1 = Interrupt latency
S2 = Application call latency
S3 =Time needed for driver to write
to third descriptor
S4 = Time needed for driver to copy
data from buffer #1 to
Descriptor
#7
OWN = 1
SIZE = HEADER_SIZE (minimum 64 bytes)
Descriptor
#6
OWN = 0
STP = 0
SIZE = 1518 - (S1+S2+S3+S4+HEADER_SIZE)
application buffer space
S6 = Time needed for driver to copy
data from buffer #2 to
Descriptor
#5
OWN = 1
SIZE = S1+S2+S3+S4
STP = 0
STP = 1
application buffer space
Descriptor
#4
OWN = 1
SIZE = HEADER_SIZE (minimum 64 bytes)
Note that the times needed for tasks S1, S2, S3,
Descriptor
#3
OWN = 0
STP = 0
S4, and S6 should be divided by 0.8 ms to yield
SIZE = 1518 - (S1+S2+S3+S4+HEADER_SIZE)
an equivalent number of network byte times
before subtracting these quantities from the
Descriptor
#2
OWN = 1
SIZE = S1+S2+S3+S4
STP = 0
expected message size A.
Descriptor
#1
OWN = 1
STP = 1
SIZE = HEADER_SIZE (minimum 64 bytes)
18183B-82
Figure 4. LAPP 3 Buffer Grouping for TWO-INTERRUPT Method
Am79C961
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APPENDIX F
Some Characteristics of the
XXC56 Serial EEPROMs
SWITCHING CHARACTERISTICS of a TYPICAL XXC56 SERIAL EEPROM INTERFACE
Applicable over recommended operating range from TA = –40∞C to +85∞C, VCC = +1.8 V to
+5.5 V, CL = 1 TTL Gate and 100 pF (unless otherwise noted)
Parameter
Symbol
Parameter Description
SK Clock Frequency
SK High Time
Test Conditions
Min
0
Max
Unit
MHz
ns
fSK
0.5
tSKH
tSKL
tCS
(Note 1)
500
500
500
100
200
0
SK Low Time
(Note 1)
ns
Minimum CS Low Time
CS Setup Time
(Note 2)
ns
tCSS
tDIS
Relative to SK
Relative to SK
Relative to SK
Relative to SK
AC Test
ns
DI Setup Time
ns
tCSH
tDIH
CS Hold Time
ns
DI Hold Time
200
ns
tPD1
tPD0
tSV
Output Delay to ‘1’
Output Delay to ‘0’
CS to Status Valid
CS to DO in High Impedance
Write Cycle Time
Endurance
1000
1000
1000
200
ns
AC Test
ns
AC Test
ns
tDF
AC Test; CS = VIL
ns
tWP
10
ms
Cycles
Number of Data Changes
per Bit
Typical
100,000
Notes:
1. The SK frequency specifies a minimum SK clock period of 2 ms, therefore in an SK clock cycle tSKH + tSKL must be greater than
or equal to 2 ms. For example, if the tSKL = 500 ns then the minimum tSKH = 1.5 ms in order to meet the SK frequency
specification.
2. CS must be brought low for a minimum of 500 ns (tCS) between consecutive instruction cycles.
INSTRUCTION SET FOR THE XXC56 SERIES OF EEPROMs
Op
Code
10
Address
Data
Instruction
SB
x8
x16
x8
x16
Comments
READ
1
A8–A0
A7–A0
Reads data stored in
memory, at specified address
EWEN
1
00
11XXXXXXX
11XXXXXX
Write enable must precede all
programming modes
ERASE
WRITE
ERAL
1
1
1
11
01
00
A8–A0
A0–A0
A7–A0
A7–A0
Erases memory location An–A0
Writes memory location An–A0
D7–D0
D7–D0
D15–D0
D15–D0
10XXXXXXX
10XXXXXX
Erases all memory locations.
Valid only at VCC = 4.5 V to 5.5 V
WRAL
EWDS
1
1
00
00
01XXXXXXX
00XXXXXXX
01XXXXXX
00XXXXXX
Writes all memory locations.
Valid when VCC = 5.0 V ± 10%
and Disable Register cleared
Disables all programming
instructions
1-646
Am79C961
AMD
VIH
VIL
CS
1 µs (1)
tCSH
tCSS
tDIS
tSKH
tSKL
VIH
VIL
SK
DI
tDIH
VIH
VIL
tPDO
tPDI
tDF
VOH
VOL
DO (READ)
tDF
tSV
VOH
VOL
Status Valid
DO (PROGRAM)
Note:
1. This is the minimum SK period.
18183B-57
Typical XXC56 Series
Serial EEPROM Control Timing
Am79C961
1-647
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