AM79C984_技术文档

PRELIMINARY

Am79C984A

enhanced Integrated Multiport Repeater (eIMR™)

DISTINCTIVE CHARACTERISTICS

■ Repeater functions comply with IEEE 802.3

■ Full LED support for individual port status LEDs

Repeater Unit speciﬁcations

and network utilization LEDs

■ Four integral 10BASE-T transceivers with on-

chip ﬁltering that eliminate the need for external

ﬁlter modules on the 10BASE-T transmit-data

(TXD) and receive-data (RXD) lines

■ Programmable extended distance mode on the

RXD lines, allowing connection to cables longer

than 100 meters

■ Twisted Pair Link Test capability conforming to

the 10BASE-T standard.The Link Test function

and the transmission of LinkTest pulses can be

optionally disabled through the control port to

allowdevicesthatdonotimplementtheLinkTest

function to work with the eIMR device.

■ One Reversible Attachment Unit Interface

(RAUI™) port that can be used either as a

standard IEEE-compliant AUI port for

connection to a Medium Attachment Unit (MAU),

or as a reversed port for direct connection to a

Media Access Controller (MAC)

■ Programmable option of automatic polarity

detection and correction permits automatic

recovery due to wiring errors

■ Low cost suitable for non-managed multiport

repeater designs

■ Expandable to increase number of repeater

ports with support for up to seven eIMR devices

without the need for an external arbiter

■ Full amplitude and timing regeneration for

retransmitted waveforms

■ CMOS device with a single +5-V supply

■ All ports can be individually isolated

(partitioned) in response to excessive collision

conditions or fault conditions.

GENERAL DESCRIPTION

The enhanced Integrated Multiport Repeater (eIMR)

device is a VLSI integrated circuit that provides a sys-

tem-level solution to designing non-managed multiport

repeaters.The device integrates the repeater functions

speciﬁed in Section 9 of the IEEE 802.3 standard and

Twisted Pair Transceiver functions complying with the

10BASE-T standard.

The eIMR device provides four Twisted Pair (TP) ports

and one RAUI port for direct connection to a MAC. The

total number of ports per repeater unit can be in-

creased by connecting multiple eIMR devices through

their expansion ports, hence, minimizing the total cost

per repeater port.

The device is fabricated in CMOS technology and

requires a single +5-V supply.

This document contains information on a product under development at Advanced Micro Devices. The

information is intended to help you evaluate this product. AMD reserves the right to change or discontinue

work on this proposed product without notice.

Publication# 20650 Rev: B Amendment/0

Issue Date: January 1998

P R E L I M I N A R Y

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges.The order number (Valid Combination) is formed

by a combination of the elements below.

Am79C984A

J

C

\W

ALTERNATE PACKAGING OPTION

\W = Trimmed and formed in a tray

TEMPERATURE RANGE

C = Commercial (0˚C to +70˚C)

PACKAGE TYPE

J = 84-Pin Plastic Leaded Chip Carrier (PL 084)

K = 100-Pin Plastic Quad Flat Pack (PQR100)

SPEED OPTION

Not Applicable

DEVICE NUMBER/DESCRIPTION

Am79C984A

enhanced Integrated Multiport Repeater (eIMR)

Valid Combinations

Am79C984A JC, KC\W

Valid Combinations list configurations planned to

be supported in volume for this device. Consult

the local AMD sales office to confirm availability

of specific valid combinations and to check on

newly released combinations.

2

Am79C984A

P R E L I M I N A R Y

BLOCK DIAGRAM

Am79C984A

3

P R E L I M I N A R Y

RELATED AMD PRODUCTS

Part No.

Description

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Am7992B

Am7996

IEEE 802.3/Ethernet/Cheapernet Transceiver

Am79C90

CMOS Local Area Network Controller for Ethernet (C-LANCE)

Twisted Pair Ethernet Transceiver (TPEX)

Am79C98

Am79C100

Am79C981

Am79C982

Am79C987

Am79C988

Am79C900

Am79C940

Am79C960

Am79C961

Am79C961A

Am79C965

Am79C970

Am79C970A

Am79C974

Am79C983

Am79C985

Twisted Pair Ethernet Transceiver Plus (TPEX+)

Integrated Multiport Repeater Plus (IMR+™)

basic Integrated Multiport Repeater (bIMR™)

Hardware Implemented Management Information Base (HIMIB™)

Quad Integrated Ethernet Transceiver (QuIET™)

Integrated Local Area Communications Controller (ILACC™)

Media Access Controller for Ethernet (MACE™)

PCnet™-ISA Single-Chip Ethernet Controller (for ISA bus)

PCnet™-ISA+ Single-Chip Ethernet Controller for ISA (with Microsoft® Plug n’Play® Support)

PCnet™-ISA II Full Duplex Single-Chip Ethernet Controller for ISA

PCnet™-32 Single-Chip 32-Bit Ethernet Controller

PCnet™-PCI Single-Chip Ethernet Controller (for PCI bus)

PCnet™-PCI II Full Duplex Single-Chip Ethernet Controller (for PCI bus)

PCnet™-SCSI Combination Ethernet and SCSI Controller for PCI Systems

Integrated Multiport Repeater 2 (IMR2™)

enhanced Integrated Multiport Repeater Plus (eIMR+™)

4

Am79C984A

P R E L I M I N A R Y

TABLE OF CONTENTS

DISTINCTIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-29

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-29

ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30

STANDARD PRODUCTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30

BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31

RELATED AMD PRODUCTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-32

CONNECTION DIAGRAM (PL 084) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-35

CONNECTION DIAGRAM (PQR100) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-36

LOGIC SYMBOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-37

LOGIC DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-37

PIN DESIGNATIONS (PL 084). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-38

Listed by Pin Number. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-38

PIN DESIGNATIONS (PQR100) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-39

Listed by Pin Number. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-39

PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-40

AUI Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-40

Twisted Pair Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-40

Expansion Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-40

Control Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-41

LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-41

Miscellaneous Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-41

FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-43

Basic Repeater Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-43

Repeater Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-43

Signal Regeneration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-43

Jabber Lockup Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-43

Collision Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-43

Fragment Extension. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-43

Auto Partitioning/Reconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-43

Detailed Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-44

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-44

AUI Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-44

TP Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-44

Twisted Pair Transmitters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-44

Twisted Pair Receivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-44

Link Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-45

Polarity Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-45

Visual Status Monitoring (LED) Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-45

Network Activity Display. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-46

Expansion Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-48

Internal Arbitration Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-48

IMR+ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-48

Control Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-49

Command/Response Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-50

Control Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-50

SET (Write Commands) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52

Chip Programmable Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52

Alternate AUI Partitioning Algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52

Alternate TP Partitioning Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52

AUI Port Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52

AUI Port Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52

TP Port Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52

TP Port Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52

Disable Link Test Function (Per TP port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52

Enable Link Test Function (Per TP port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52

Disable Link Pulse (Per TP Port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52

Am79C984A

5

P R E L I M I N A R Y

Enable Link Pulse (Per TP Port). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52

Disable Automatic Receiver Polarity Reversal (Per TP Port). . . . . . . . . . . . . . . . . 1-53

Enable Automatic Receiver Polarity Reversal (Per TP Port) . . . . . . . . . . . . . . . . . 1-53

Disable Receiver Extended Distance Mode (Per TP Port). . . . . . . . . . . . . . . . . . . 1-53

Enable Receiver Extended Distance Mode (Per TP Port) . . . . . . . . . . . . . . . . . . . 1-53

Disable Software Override of LEDs 5

(Per Port - AUI and TP, Global) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-53

Enable Software Override of Bank A LEDs (Per Port - AUI and TP, Global) . . . . . 1-53

Enable Software Override of Bank B LEDs (Per Port - AUI and TP, Global) . . . . . 1-54

Software Override of LED Blink Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-54

GET (Read Commands). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-54

AUI Port(s) Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-54

Alternate AUI Port(s) Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-54

TP Port Partitioning Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-54

Bit Rate Error Status of TP Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-54

Link Test Status of TP ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-55

Receive Polarity Status of TP Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-55

MJLP Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-55

Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-55

SYSTEMS APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-55

eIMR to TP Port Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-55

Twisted Pair Transmitters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-55

Twisted Pair Receivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-55

MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-57

Internal Arbitration Mode Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-57

IMR+ Mode External Arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-57

Visual Status Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-59

ABSOLUTE MAXIMUM RATINGS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-60

OPERATING RANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-60

DC CHARACTERISTICS over operating ranges unless otherwise speciﬁed . . . . . . . . . . . . . . . . . 1-60

SWITCHING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-62

KEY TO SWITCHING WAVEFORMS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-64

SWITCHING WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-64

SWITCHING TEST CIRCUIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-69

6

Am79C984A

P R E L I M I N A R Y

CONNECTION DIAGRAM (PL 084)

8

4

3

84 83

8180 78 7776 75

79

82

1110 9

12

7 6 5

2

1

74 LDC2

73 LDC1

REXT

AVSS

DI+

DI–

VDD

CI+

CI–

AVSS

DO+

DO–

13

14

15

16

17

18

19

20

21

72

71

70

LDC0

VDD

LDGB

69 LDGA

68

67

66

LDB4

DVSS

LDA4

65 LDB3

eIMR

Am79C984A

64

63

62

61

60

AMODE 22

LDA3

DVSS

LDB2

LDA2

VDD

23

24

VDD

DVSS

VDD

RST

25

26

27

28

29

30

31

32

59 LDB1

58

57

56

55

54

LDA1

DVSS

LDB0

LDA0

ACT7

CLK

DVSS

SELI_0

SELI_1

33

4142

4546 47

50 5152

53

48 49

3536

39 40

3738

43 44

34

20650A-2

20650B-2

Am79C984A

7

P R E L I M I N A R Y

CONNECTION DIAGRAM (PQR100)

RXD3–

NC

VDD

NC

1

2

3

4

5

6

7

8

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

NC

REXT

AVSS

DI+

DI–

VDD

CI+

NC

LDC2

LDC1

LDC0

VDD

LDGB

LDGA

LDB4

DVSS

LDA4

LDB3

LDA3

DVSS

LDB2

LDA2

VDD

LDB1

LDA1

NC

DVSS

LDB0

LDA0

ACT7

NC

ACT6

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

CI–

AVSS

DO+

DO–

AMODE

VDD

DVSS

VDD

RST

NC

eIMR

Am79C984A

CLK

DVSS

SELI_0

SELI_1

NC

SELO

20650B-3

8

Am79C984A

P R E L I M I N A R Y

LOGIC SYMBOL

V_DD

DAT

JAM

ACK

COL

TXD+

TXD–

RXD+

RXD–

Twisted Pair

Ports

(4 Ports)

Expansion

Port

SELO

SELI[1:0]

DO+

DO–

DI+

AUI

SI

SO

SCLK

AMODE

DI–

CI+

CI–

Test and

Control

Port

Am79C984

LDA[4:0], LDB[4:0]

LDGA, LDGB

LDC[2:0]

LED

Interface

ACT[7:0]

CLK

RST

DV_SS

AV_SS

20650A-4

20650B-4

LOGIC DIAGRAM

AUI

LED

Port

Repeater

State

Machine

Control

Port

Expansion

Port

Twisted Pair

Port 0

Twisted Pair

Port 3

20650A-5

20650B-5

Am79C984A

9

P R E L I M I N A R Y

PIN DESIGNATIONS (PL 084)

Listed by Pin Number

Pin No.

1

Pin Name

TXD3+

TXD3-

VDD

Pin No.

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

Pin Name

AMODE

VDD

Pin No.

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

Pin Name

SO

Pin No.

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

Pin Name

LDA3

2

SCLK

VDD

LDB3

LDA4

3

DVSS

VDD

4

RXD0+

RXD0-

RXD1+

RXD1-

RXD2+

RXD2-

RXD3+

RXD3-

REXT

AVSS

DI+

ACT0

ACT1

ACT2

DVSS

ACT3

ACT4

ACT5

ACT6

ACT7

LDA0

LDB0

DVSS

LDA1

LDB1

VDD

DVSS

LDB4

LDGA

LDGB

VDD

5

VDD

6

VDD

7

RST

8

CLK

9

DVSS

SELI_0

SELI_1

SELO

COL

LDC0

LDC1

LDC2

VDD

10

11

12

13

14

15

16

17

18

19

20

21

TXD0+

TXD0-

AVSS

TXD1+

TXD1-

VDD

DVSS

ACK

DI-

VDD

DAT

CI+

VDD

CI-

JAM

AVSS

DO+

NC

LDA2

LDB2

DVSS

TXD2+

TXD2-

AVSS

DVSS

SI

DO-

10

Am79C984A

P R E L I M I N A R Y

PIN DESIGNATIONS (PQR100)

Listed by Pin Number

Pin No.

1

Pin Name

RXD3-

NC

Pin No.

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

Pin Name

SELI_1

NC

Pin No.

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

Pin Name

ACT6

NC

Pin No.

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

Pin Name

LDC2

NC

2

3

NC

4

NC

5

REXT

AVSS

DI+

SELO

COL

DVSS

NC

ACT7

LDA0

LDB0

DVSS

NC

VDD

6

TXD0+

TXD0-

AVSS

TXD1+

TXD1-

VDD

7

8

DI-

9

VDD

CI+

ACK

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

DAT

LDA1

LDB1

VDD

CI-

VDD

JAM

AVSS

DO+

DO-

TXD2+

TXD2-

AVSS

TXD3+

TXD3-

VDD

NC

LDA2

LDB2

DVSS

LDA3

LDB3

LDA4

DVSS

LDB4

LDGA

LDGB

VDD

DVSS

SI

AMODE

VDD

DVSS

VDD

RST

SO

SCLK

VDD

ACT0

ACT1

ACT2

DVSS

ACT3

ACT4

ACT5

RXD0+

RXD0-

RXD1+

RXD1-

RXD2+

NC

CLK

DVSS

SELI_0

LDC0

LDC1

RXD2-

RXD3+

Notes:

1. Pin 40 has a bonding option depending on internal device name.

2. NC = No Connection.

Am79C984A

11

P R E L I M I N A R Y

state of the DAT pin is used in conjunction with JAM to

PIN DESCRIPTION

AUI Port

indicate a single port (DAT =1) or multiport (DAT=0) col-

lision. JAM is in the high-impedance state if neither the

SEL nor ACK signal is asserted.It is recommended that

JAM be pulled up or down via a high value resistor.

DI+, DI–

Data In

Differential Input

SELI

0-1

DI± are differential, Manchester receiver pins. The sig-

nals comply with IEEE 802.3, Section 7.

Select In

Input, Active LOW

DO+, DO–

Data Out

Differential Output

When the expansion bus is conﬁgured for Internal Arbi-

tration mode, these signals indicate that another eIMR

device is active; SELI or SELI is driven by SELO from

0

1

the upstream device. At reset, SELI selects between

DO± are differential, Manchester output driver pins.The

0

the Internal Arbitration mode and the IMR+ mode of the

expansion bus; a HIGH selects the Internal Arbitration

mode and a LOW selects the IMR+ mode.

signals comply with IEEE 802.3, Section 7.

CI+, CI–

Collision Input

Differential Input/Output

Arbitration

SELI_1

SELI_0

Mode

CI± are differential, Manchester I/O signals.As an input,

CI is a collision-receive indicator. As an output, CI gen-

erates a 10-MHz signal if the eIMR device senses a

collision.

X

1

0

Internal

IMR+

SELO

Select Out

Output, Active LOW

Twisted Pair Ports

TXD+ ,TXD–

0-3

Transmit Data

Differential Output

If the expansion bus is conﬁgured for Internal Arbitration

mode, an eIMR device drives this pin LOW when it is

TXD± are 10BASE-T port differential drivers (4 ports).

active or when either of its SELI

pins is LOW. An

0-1

active eIMR device is deﬁned as having one or more

ports receiving or colliding and/or is still transmitting

data from the internal FIFO, or extending a packet to the

minimum of 96 bit times. When the expansion bus is

conﬁgured for IMR+ mode, SELO is active when the

eIMR device is active (acquiring the functionality of the

REQ pin on the Am79C971 IMR+ device).

RXD+ , RXD–

0-3

Receive Data

Differential Input

RXD± are 10BASE-T port differential receive inputs

(4 ports).

Expansion Bus

ACK

Acknowledge

Input/Output, Active LOW, Open Drain

DAT

Data

Input/Output/3-State

This signal is asserted to indicate that an eIMR device

is active. It also signals to the other eIMR devices the

presence of a valid collision status on the JAM line and

valid data on the DAT line. When the eIMR device is

conﬁgured for Internal Arbitration mode, ACK is an I/O,

and must be pulled to VDD via a minimum equivalent

resistance of 1 kΩ. When the eIMR device is conﬁgured

for IMR+ mode, ACK is an input driven by an external

arbiter.

If the SELO and ACK pins are asserted during non-

collision conditions, the eIMR device drives NRZ data

onto the DAT line, regenerating the preamble if neces-

sary.During a collision, when JAM is HIGH, DAT is used

to differentiate between single-port (DAT=1) and multi-

port (DAT=0) collisions. DAT is an output when ACK is

asserted and the eIMR device’s ports are active; DAT

is an input when ACK is asserted and the ports are

inactive. If ACK is not asserted, DAT is in the high-im-

pedance state. It is recommended that DAT be pulled

up or down via a high value resistor.

COL

Collision

Input/Output, Active LOW, Open Drain

JAM

Jam

Whenasserted, COLindicatesthatmorethanoneeIMR

device is active. Each eIMR device generates the Col-

lision Jam sequence independently.When the eIMR de-

vice is conﬁgured for Internal Arbitration mode, COL is

Input/Output/3-State

The active eIMR device drives JAM HIGH, if it detects

a collision condition on one or more of its ports. The

12

Am79C984A

P R E L I M I N A R Y

an I/O and must be pulled to VDD via a minimum equiv-

multiple-eIMR conﬁguration, LDGA from each of the

eIMR devices can be tied together to drive a single glo-

bal LED in Bank A.

alent resistance of 1 kΩ. When the eIMR device expan-

sion port is conﬁgured for IMR+ mode, COL is an input

driven by an external arbiter.

LDGB

Global LED Driver, Bank B

Output, Open Drain

Control Port

AMODE

LDGB is the Global LED driver for LED Bank B. The

signal represents global CRS or JAB conditions. In a

multiple eIMR conﬁguration, LDGB from each of the

eIMR devices can be tied together to drive a single glo-

bal LED in Bank B.

AUI Mode

Input

At reset, this pin sets the AUI port to either normal or

reversed mode. If AMODE is LOW at the rising edge of

RST, the AUI port is set to the normal mode; if AMODE

is HIGH, the AUI port is set to the reversed mode.

LDC

0-2

LED Control

Input

SCLK

Serial Clock In

Input

These pins select the attributes that will be displayed

on LDA , LDB , LDGA, and LDGB. If an LED is pro-

Serial data (input or output) is clocked (in or out) on the

rising edge of the signal on this pin. SCLK is asynchro-

nous to CLK and can operate at frequencies up to 10

MHz.

0-4

grammed to display two attributes, the attribute associ-

ated with the periodic blink takes precedence.

ACT

0-7

SI

Activity Display

Output

Serial In

Input

These signals drive the activity LEDs, which indicate

the percentage of network utilization.The display is up-

dated every 250 ms.

The SI pin is used as a test/control serial input port.

Control commands are clocked in on this pin synchro-

nous to SCLK input.

Miscellaneous Pins

At reset, SI sets the state of the Automatic Polarity Re-

versal function. If SI is HIGH at the rising edge of RST,

Automatic Polarity Reversal is disabled. If SI is LOW at

the rising edge of RST, Automatic Polarity Reversal is

enabled.

RST

Reset

Input, Active LOW

When RST is LOW, the eIMR device resets to its default

state.On the rising (trailing) edge of RST, the eIMR also

monitors the state of the SELI , SI, and AMODE pins,

0-1

SO

Serial Out

Output

to conﬁgure the operating mode of the device. In multi-

ple eIMR systems, the falling (leading) edge of the RST

signal must be synchronized to CLK.

The SO pin is used as a control command serial output

port. Responses to control commands are clocked out

on this pin synchronous to the SCLK input.

CLK

Master Clock In

Input

This pin is a 20-MHz clock input.

LED Interface

LDA , LDB

0-4

REXT

LED Drivers

Output, Open Drain

External Reference

Input

LDA and LDB drive LED Bank A and LED Bank B,

This pin is used for an internal current reference.It must

0-4

respectively. LDA and LDB indicate the status of the

be tied to VDD via a 13-kΩ resistor with 1% tolerance.

0

AUI port; LDA and LDB indicate the status of the

1-4

VDD

four TP ports. The port attributes monitored by LDA

0-4

Power

and LDB are programmed by three pins, LDC

.

0-4

0-2

Power Pin

LDGA

This pin supplies power to the device.

Global LED Driver, Bank A

Output, Open Drain

LDGA is the Global LED driver for LED Bank A. The

signal represents global CRS or COL conditions. In a

Am79C984A

13

P R E L I M I N A R Y

DVSS

AVSS

Analog Ground

Ground Pin

Digital Ground

Ground Pin

This pin is the ground reference for the differential

receivers and drivers.

This pin is the ground reference for all the digital logic

in the eIMR device.

14

Am79C984A

P R E L I M I N A R Y

times. This is referred to as MAU Jabber Lockup Pro-

FUNCTIONAL DESCRIPTION

tection (MJLP). The MJLP status for the eIMR device

can be read through the Control Port, using the Get

MJLP Status command.

The Am79C984A eIMR device is a single-chip imple-

mentation of an IEEE 802.3/Ethernet repeater (or hub).

It is offered with four integral 10BASE-T ports plus one

RAUI port comprising the basic repeater.The eIMR de-

vice is also expandable, enabling the implementation of

high port count repeaters based on several eIMR de-

vices.

Collision Handling

The eIMR device will detect and respond to collision

conditions as speciﬁed in the IEEE 802.3 speciﬁcation.

Repeater conﬁgurations consisting of multiple eIMR

devices also comply with the IEEE 802.3 speciﬁcation,

using status signals provided by the expansion bus. In

particular, a repeater based on one or more eIMR de-

vices will handle the transmit collision and one-port-left

collision conditions correctly, as speciﬁed in Section 9

of the IEEE 802.3 speciﬁcation.

The eIMR chip complies with the full set of repeater

basic functions as deﬁned in Section 9 of ISO 8802.3

(ANSI/IEEE 802.3c).The basic repeaters functions are

summarized in the paragraphs below.

Basic Repeater Functions

The Am79C984A chip implements the basic repeater

functions as deﬁned by Section 9.5 of the ANSI/IEEE

802.3 speciﬁcation.

Fragment Extension

If the total packet length received is less than 96 bits,

including preamble, the eIMR device will extend the re-

peated packet length to 96 bits by appending a Jam se-

quence to the original fragment.

Repeater Function

If any single network port senses the start of a valid

packet on its receive lines, the eIMR device will retrans-

mit the received data to all other enabled network ports

(except when contention exists among any of the ports

or when the receive port is partitioned). To allow multi-

ple eIMR device conﬁgurations, the data will also be re-

peated on the expansion bus data line (DAT).

Auto Partitioning/Reconnection

Any of the TP ports or the AUI port can be partitioned if

the duration or frequency of collisions becomes exces-

sive. The eIMR device will continue to transmit data

packets to a partitioned port, but will not respond, as a

repeater, to activity on the partitioned port’s receiver.

The eIMR device will monitor the port and reconnect it

once certain criteria are met. The criteria for reconnec-

tion are speciﬁed by the IEEE 802.3 standard. In addi-

tion to the standard reconnection algorithm, the eIMR

device implements an alternative reconnection algo-

rithm, which provides a more robust partitioning func-

tion for the TP ports and/or AUI port. The eIMR device

partitions each TP port and the AUI port separately and

independently of other network ports.

Signal Regeneration

When retransmitting a packet, the eIMR device en-

sures that the outgoing packet complies with the IEEE

802.3 speciﬁcation in terms of preamble structure and

timing characteristics. Speciﬁcally, data packets re-

peated by the eIMR device will contain a minimum of 56

preamble bits before the Start-of-Frame Delimiter. In

addition, the eIMR restores the voltage amplitude of

the repeated waveform to levels speciﬁed in the IEEE

802.3 speciﬁcation. Finally, the eIMR device restores

signal symmetry to repeated data packets, removing jit-

ter and distortion caused by the network cabling. Jitter

present at the output of the AUI port will be better than

0.5 ns; jitter at the TP outputs will be better than 1.5 ns.

The eIMR device will partition an enabled network port

if either of the following conditions occurs at that port:

a. A collision condition exists continuously for more

than 2048 bit times. (AUI port—SQE signal active;

TP port—simultaneous transmit and receive).

b. A collision condition occurs during each of 32 con-

secutive attempts to transmit to that port.

The start-of-packet propagation delay for a repeater set

is the time delay between the ﬁrst edge transition of a

data packet on its input port to the ﬁrst edge transition

of the repeated packet on its output ports. The start-of-

packet propagation delay for the eIMR is within the

speciﬁcation given in Section 9.5.5.1 of the IEEE 802.3

standard.

In the AUI port, a collision condition is indicated by an

active SQE signal. In a TP port, a collision condition is

indicated when the port is simultaneously attempting to

transmit and receive.

Once a network port is partitioned, the eIMR device will

reconnect that port, according to the selected recon-

nection algorithm, as follows:

Jabber Lockup Protection

The eIMR device implements a built-in jabber protec-

tion scheme to ensure that the network is not disabled

by the transmission of excessively long data packets.

This protection scheme causes the eIMR device to in-

terrupt transmission for 96 bit-times if the device has

been transmitting continuously for more than 65,536 bit

a. Standard reconnection algorithm—A data packet

longer than 512-bit times (nominal) is transmitted or

received by the partitioned port without a collision.

Am79C984A

15

P R E L I M I N A R Y

b. Alternative reconnection algorithm—A data packet

power is maintained to the eIMR device, a reset dura-

tion of only 4 µs is required. This allows the eIMR de-

vice to reset its internal logic. During reset, the eIMR

registers are set to their default values. Also during re-

set, the eIMR device sets the output signals to their in-

active state; that is, all analog outputs are placed in

their idle state, no bidirectional signals are driven, all

active-HIGH signals are driven LOW and all active-

LOW signals are driven HIGH. In a multiple eIMR sys-

tem, the reset signal must be synchronized to CLK.

See Figure 10 in the Systems Applications section.

longer than 512-bit times (nominal) is transmitted by

the partitioned port without a collision.

A partitioned port can also be reconnected by disabling

and re-enabling the port.

All TP ports use the same reconnection algorithm; ei-

ther they must all use the standard algorithm, or they

must all use the alternative reconnection algorithm.

However, the reconnection algorithm for the AUI port is

programmed independently from that of the TP ports.

The eIMR device also monitors the state of the SELI

SI, and AMODE pins on the rising (trailing) edge of

RST to conﬁgure the operating mode of the device.

,

Detailed Functions

0-1

Reset

The eIMR device enters the reset state when the reset

(RST) pin is driven LOW. After the initial application of

power, the RST pin must be held LOW for a minimum

of 150 µs. If the RST pin is subsequently asserted while

Table 1 summarizes the state of the eIMR chip following

reset.

Table 1. eIMR States after Reset

State after Reset

Function

Pull Up/Pull Down

Active-LOW Outputs

HIGH

No

Active-HIGH Outputs

LOW

SO Output

HIGH

No

DAT, JAM

HIGH IMPEDANCE

IDLE

Either

No

Transmitters (TP and AUI)

Receivers (TP and AUI)

AUI Partitioning/Reconnection Algorithm

TP Partitioning/Reconnection Algorithm

Link Test Functions for TP Ports

ENABLED

Terminated

N/A

STANDARD ALGORITHM

ENABLED, TP PORTS IN LINK FAIL

N/A

Automatic Receiver Polarity Reversal Function DISABLED IF SI PIN IS HIGH

ENABLED IF SI PIN IS LOW

N/A

AUI Port

TP Port Interface

Twisted Pair Transmitters

The AUI Port is fully compatible with the IEEE 802.3,

Section 7 requirement for an AUI port. It has the signals

associated with an AUI port: DO, DI, and CI.

TXD is a differential twisted-pair driver. When properly

terminated, TXD will meet the electrical requirements

for 10BASE-T transmitters as speciﬁed in IEEE 802.3,

Section 14.3.1.2.

The AUI port has two modes of operation: normal and

reverse. When conﬁgured for normal operation, the

functionality is that of an AUI port on a MAC (CI is an

input).When conﬁgured for reverse operation, the func-

tionality is that of an AUI on a MAU (CI is an output).

The mode of the AUI port is set during the trailing (ris-

ing) edge of the reset pulse, by the state of the AMODE

pin. A LOW sets the AUI port to its normal mode (CI In-

put) and a HIGH sets the AUI port to its reversed (CI

Output) mode.

The TXD signal is ﬁltered on the chip to reduce har-

monic content per IEEE 802.3, Section 14.3.2.1

(10BASE-T). Since ﬁltering is performed in silicon, TXD

can connect directly to a standard transformer, thereby,

eliminating the need for external ﬁltering modules.

Proper termination is shown in the Systems Applica-

tions section.

Twisted Pair Receivers

The eIMR device can be connected directly to a MAC

through the AUI port.This requires that the AUI port be

conﬁgured for reverse operation. Refer to the Systems

Applications section for more details.

RXD is a differential twisted-pair receiver. When prop-

erly terminated, RXD will meet the electrical require-

ments for 10BASE-T receivers as speciﬁed in IEEE

802.3, Section 14.3.1.3. The receivers do not require

16

Am79C984A

P R E L I M I N A R Y

external ﬁlter modules. Proper termination is shown in

Visual Status Monitoring (LED) Support

the Systems Applications section.

The eIMR status port can be connected to LEDs to fa-

cilitate the visual monitoring of repeater port status.

The receiver’s threshold voltage can be programmed to

an extended-distance mode. In this mode, the differen-

tial receiver’s threshold is reduced to allow a longer

cable than the 100 meters speciﬁed in the IEEE 802.3

standard. For programming details, refer to the Control

Commands section.

The status port has twelve output signals, LDA , and

0-4

LDB , LDGA, and LDGB. LDA and LDB repre-

0-4

sent the four TP ports and AUI port. LDGA and LDGB

are global indicators. Attributes that may be monitored

are Carrier Sense (CRS), Collision (COL), Partition

(PAR), Link Status (LINK), Loopback (LB), Port Dis-

abled (DIS), and Jabber (JAB). Three control bits,

Link Test

The integrated TP ports implement the Link Test func-

tion, as speciﬁed in the IEEE 802.3 10BASE-T stan-

dard. The eIMR device will transmit Link Test pulses to

any TP port after that port’s transmitter has been inac-

tive for more than 8 ms to 17 ms. Conversely, if a TP

port does not receive any data packets or Link Test

pulses for more than 65 ms to 132 ms and the Link Test

function is enabled for that port, then that port will enter

the link-fail state.The eIMR device will disable a port in

link-fail state (i.e., disable repeater transmit and receive

functions) until it receives either four consecutive Link

Test pulses or a data packet.

LDC , select the particular attributes to be displayed

on the LEDs. Table 2 shows how the programming

0-2

combinations for LDC control the attributes that will

0-2

be monitored.

Each LED drive pin (LDGA, LDGB, LDA , and LDB

)

0-4

has two states: Off and LOW. When none of the se-

lected attributes are true, the driver is off and the diode

is unlit.When an attribute is true, the driver is LOW, and

the corresponding LEDs in Bank A or Bank B will be lit.

Some of the settings (LDC = 1) include a blink func-

2

tion.This allows two attributes to be selected for a given

state on the pin. As an example when LDC

= 110,

0-2

The Link Test function can be disabled via the eIMR

control port on a port-by-port basis, to allow the eIMR

device to operate with pre-10BASE-T networks that do

not implement the Link Test function. When the Link

Test function is disabled, the eIMR device will not allow

the TP port to enter link-fail state, even if no Link Test

pulses or data packets are being received. Note, how-

ever, that the eIMR device will always transmit Link Test

pulses to all TP ports, regardless of whether or not the

port is enabled, partitioned, in link-fail state, or has its

Link Test function disabled. Separate control com-

mands exist for enabling and disabling the transmission

of Link Test pulses on a port-by-port basis.

the LDA outputs relating to TP ports will be solidly lit

when there is a link established at that port. However,

whenever there is activity on a port, the corresponding

LDA pin will switch on (LOW) and off at a period of 130

ms. Note that a partition on that port will also cause the

pin to go LOW.

On LDC settings that have two attributes for a state on

a pin (blink or solid-on), the attribute causing the output

to blink has priority. (Those attributes are shown in

Table 2 with a blink period speciﬁed next to it.) If an at-

tribute has no blink period speciﬁed, the LED indicates

the attribute by being solidly lit.

Polarity Reversal

The LEDs can also be controlled via the control port.

The Enable Software Override commands turn the

LEDs on regardless of the attributes selected for dis-

play through the LDC setting. Enable Software Over-

The TP ports can be programmed to receive data if a

wiring error results in a data packet being received at a

TP port with reversed polarity. This function will be en-

abled upon reception of a negative EndTransmit Delim-

iter (ETD) or negative pulses and allows subsequent

packets to be received with the correct polarity.The po-

larity-reversal function is executed once following reset

or link-fail and can be programmed via the control port

to be enabled or disabled on a port-by-port basis. The

function may be enabled or disabled, following a reset,

depending on the level of the SI signal on the rising

edge of the RST pulse.

ride of Bank A LEDs causes the LDA and LDGA pins

0-4

to be driven LOW, and Enable Software Override of

Bank B LEDs causes the LDB and LDGB pins to be

0-4

driven LOW.The blink rate is set by the Software Over-

ride LED Blink Rate command. The periods are off,

512 ms, 1560 ms, or solid on.

Am79C984A

17

P R E L I M I N A R Y

Table 2. LED Attribute-Monitoring Program Options

LED Control

Global LEDs

TP LEDs

AUI LEDs

LDC₂

LDC₁

LDC₀

LDGA

CRS

LDGB

COL

LDA

LDB

LDA

LB

LDB

0

1-4

0

1

0

1

0

1

0

1

0

LINK (Note 2)

LINK

PAR

CRS

PAR

CRS

COL

LB

Reserved (Note 5)

LINK PAR

PAR

CRS 260-ms blk COL 260-ms blk CRS 260-ms blk COL 260-ms blk CRS 260-ms blk COL 260-ms blk

1

0

1

0

COL

JAB

LINK (Note 3)

CRS 512-ms blk

LINK

PAR (Note 3)

PAR or DIS

(Note 3)

PAR (Note 3)

PAR or DIS

CRS 512-ms blk

CRS

COL

CRS 130-ms blk

1

CRS

COL

LINK (Note 4)

PAR 1.56-s blk

COL (Note 4)

(Note 4)

PAR (Note 4)

PAR 1.56-s blk

Notes:

1. CRS = Carrier Sense, COL = Collision, JAB = Jabber, LINK = Link, LB = Loop Back, PAR = Partition, DIS = Port Disabled,

blk = Blink (Number = period of Blink).

2. For the LDC setting of 000: If the port is partitioned, the LINK LED is off.

0-2

3. All LEDs blink 16 times at 260 ms per blink after reset.

4. All LEDs are on for approximately 4 seconds after reset.

5. LDC = ‘010’ and ‘011’ are undeﬁned.

0-2

LED software override is executed in two stages, by

ﬁrst issuing the blink rate (Software Override of LED

Blink Rate) and then issuing the command to enable

the particular port LEDs (Enable Software Override of

Bank A/B LEDs). All port combinations selected for

software override control will reference the blink rate

last issued by the Software Override of the LED Blink

Rate command.

Figure 1 shows the recommended connection of LEDs.

When LDA , LDB , LDGA, or LDGB are LOW, the

LED lights.

0-4

V_DD

eIMR

LED

Interface

R

LDA , LDB , LDGA, and LDGB are open drain out-

0-4

put drivers that sink 12 mA of current to turn on the

LEDs. In a multiple eIMR conﬁguration, the outputs

from the global LED drivers (LDGA and LDGB) of each

chip can be tied together to drive a single pair of global

status LEDs.

LDA[4:0]

LDB[4:0]

LDGA

LDGB

Typical

CRS and COL are extended to make it easier for visual

recognition; that is, they will remain active for some

time even if the corresponding condition has expired.

Once carrier sense is active, CRS will remain active for

a minimum of 4 ms. Once a collision is detected, COL

is active for at least 4 ms. The exception to this rule is

20650B-6

20650A-6

Figure 1. Visual Monitoring Application—Direct

LED Drive

for selection LDC

= 111. For this selection, COL is

0-2

stretched to 100 µs.

Network Activity Display

When LDC = 000 or LDC = 001, the loopback at-

0-2

tribute (LB) for the AUI port is displayed on LDA . LB is

0

The eIMR status port can drive up to eight LEDs to in-

dicate the network-utilization level as a percentage of

bandwidth. The status port uses eight dedicated out-

true when DO on the MAU is successfully looped back

to DI on the AUI port. LB is false (off) if a loopback error

is detected, or if the AUI port is disabled or in the re-

verse mode. Transmit carrier sense is sampled at the

end of packet to determine the state of LB.The state of

LB remains latched until carrier sense is sampled again

for the next packet.The default/power-up state for LB is

false (off).

puts (ACT ) to drive a series of LEDs. The number of

0-7

LEDs in the series that will be lit increases as the

amount of network activity increases. ACT represents

0

the lowest level of activity; ACT represents the high-

7

est. ACT

are open-drain outputs that typically sink

0-7

12 mA of current to turn on the LEDs. See Figure 2.

18

Am79C984A

P R E L I M I N A R Y

V_DD

eIMR

LED

Interface

ACT[0]

ACT[1]

ACT[2]

ACT[3]

ACT[4]

ACT[5]

ACT[6]

ACT[7]

20650A-7

Figure 2. Network Activity Display

Table 3 shows ACT as a function of the percentage

0-7

of network utilization. The table uses a scale that is

more sensitive at low utilization levels. 100% utilization

represents the maximum number of events that could

occur in a given window of time.

Table 3. Network Utilization

Number of LEDs

Percentage Utilization

Lit by ACT

7-0

8

7

6

5

4

3

2

1

>80%

>64%

>32%

>16%

>8%

The update rate and corresponding internal sampling

window for ACT[7:0] is 250 ms. During this sampling

window, a counter is used to count the number of times

repeater transmit activity is TRUE. The counter uses a

free-running clock which has the granularity to detect

the minimum packet size of 96 bit times.

>4%

>2%

Figure 3 shows the timing relationship between the

sampling window, counting clock, and transmit activity.

>1%

latch data;

update display;

clear counter

next counting cycle

counter is active

Sampling

Window

Counting

Clock

Xmit

Activity

20650B-8

Figure 3. Activity Sampling

Am79C984A

19

P R E L I M I N A R Y

ACK and COL are mutually exclusive. If an eIMR driv-

Expansion Bus Interface

ing ACK senses COL LOW, the device will deassert

ACK.

The eIMR device expansion bus allows multiple eIMR

devices to be interconnected.

DAT and JAM are synchronized to CLK. DAT is the rep-

etition of data from any connected port (either TP or

AUI port) encoded in NRZ format. JAM is an internal

collision indicator. If JAM is HIGH, the active eIMR de-

vice has detected an internal collision across one or

more of its ports. When this occurs, the DAT signal dis-

tinguishes between single-port collisions and multiport

collisions. DAT = 1 indicates a single port collision;

DAT = 0 indicates a multiport collision.

The expansion bus supports two modes of operation:

internal arbitration mode and IMR+ mode. The internal

arbitration mode uses a modiﬁed daisy-chain scheme

to eliminate the need for any external arbitration cir-

cuitry.The IMR+ mode maintains the full functionality of

the IMR+ (Am79C981) expansion bus and beneﬁts

from minimum delays. In this mode, the eIMR device

requires external circuitry to handle arbitration for con-

trol of the bus.

The drive capabilities of the I/O signals on the expan-

sion bus (DAT, JAM, ACK, and COL) are sufﬁcient to

allow seven eIMR devices to be connected together

without the use of external transceivers or buffers.

The eIMR arbitration mode is determined at reset.This

occurs on the trailing edge of RST according to the

state of SELI , as illustrated in Figure 4.

0-1

Internal Arbitration Mode

The maximum number of eIMR devices that can be

daisy chained is limited by the propagation delay of the

eIMR devices. In practice, the depth of the cascade is

limited to three eIMR devices, thus allowing a maxi-

mum of seven eIMR devices connected together via

this expansion bus as shown in Figure 5.

The internal arbitration mode uses a daisy-chain (cas-

cade) conﬁguration. SELI are arbitration inputs and

0-1

SELO is the arbitration output. SELO goes LOW when

there is activity on one or more of the eIMR ports, or a

SELI input is LOW. The SEL lines are connected as

shown in Figure 5.This technique allows activity indica-

tion to propagate down the chain to the end device. All

unused SELI inputs must be tied to VDD.

The active device will not drive the data line, DAT,

until one bit time (100 ns) after SELO goes LOW. This

is to avoid a situation where two devices drive DAT

simultaneously.

ACK and COL are global activity I/O pins. When the

eIMR device senses activity, it drives ACK LOW.

IMR+ Mode

.

In IMR+ mode, the expansion bus requires an external

arbiter.The arbiter allows only one eIMR device to con-

trol the expansion bus. If more than one device at-

tempts to take control, the arbiter terminates all access

and signals a collision condition.

RST

SELI_0

Mode Selection

In IMR+ mode, DAT and JAM retain the same function-

ality as in internal arbitration mode, but ACK and COL

are inputs to the eIMR device, driven by the external ar-

biter. The arbiter should drive ACK LOW when exactly

one eIMR device is active. It should drive COL when

more than one eIMR device is active. SELO is an out-

put from the eIMR device. It indicates that the eIMR de-

vice has an active port and is requesting access to the

bus.

Arbitration

Mode

SELI_1

SELI_0

X

1

0

Internal

IMR+

20650B-9

Figure 4. Expansion Bus Mode Selection

When ACK is HIGH, DAT and JAM are in the high-

impedance state. DAT and JAM go active when ACK

goes LOW. Refer to the Systems Applications section

(Figure 13) for the conﬁguration of IMR+ mode of

operation.

An eIMR device drives COL LOW when it senses more

than one device is active; that is, if the device has an

active port AND a SELI input is LOW, OR both SELI in-

puts are LOW. In Boolean notation, the formula for COL

is:

Note: The IMR+ mode is recommended when arbitrating

between multiple boards.

COL = (Active port & (SELI + SELI ))+

1

0

(SELI & SELI )

1

0

.

where

& represents the Boolean AND operation

+ represents the Boolean OR operation

20

Am79C984A

P R E L I M I N A R Y

V_DD

1kΩ

SELI_0

SELI_1

SELO

SELI_0

SELI_1

SELO

SELI_0

SELI_1

SELO

SELI_0

SELI_1

SELO

SELI_0

SELI_1

SELO

SELI_0

SELI_1

SELO

SELI_0

SELI_1

SELO

20650A-10

20650B-10

Figure 5. Internal Arbitration—eIMR Devices in Cascade

a free-running clock synchronized to the input bit pat-

terns, or a series of individual transitions meeting the

setup-and-hold times with respect to the input bit pat-

tern. If the latter method is used, 20 SCLK clock transi-

tions are required for control commands that produce

SO data, and 14 SCLK clock transitions are required

for control commands that do not produce SO data.

Control Functions

The eIMR device receives control commands in the

form of byte-length data on the serial input pin, SI. If the

eIMR device is expected to provide data in response to

the command, it will send byte-length data to the serial-

output pin, SO. Both the input and output data streams

are clocked with the rising edge of the SCLK signal.

The byte-length data is in RS232 serial-data format;

that is, one start bit followed by eight data bits. The ex-

ternally generated clock at the SCLK pin may be either

Am79C984A

21

P R E L I M I N A R Y

end of a GET command, the eIMR device waits two

Command/Response Timing

SCLK cycles and then transmits the response on SO.

Figure 6 shows the command/response timing. At the

.

SCLK

SI

ST D0 D1 D2 D3 D4 D5 D6 D7

SO

ST D0 D1 D2 D3 D4 D5 D6 D7

20650A-11

20650B-11

Figure 6. Control Get Command/Response

Control Commands

Table 4. Summary of Default States after Reset

The following section details the operation of each con-

trol commands available in the eIMR device. In all

cases, the individual bits in each command are shown

with the most-signiﬁcant bit (bit 7) on the left and the

least-signiﬁcant bit (bit 0) on the right.Table 4 and Table

5 show a summary of default states and a summary of

control commands, respectively.

eIMR Programmable Option—S Off

AUI Partitioning Algorithm

TP Partitioning Algorithm

AUI/TP Port

Normal

Enabled

Link Test

Link Pulse

Note: Data is transmitted and received on the serial

data lines least-signiﬁcant bit ﬁrst and most-signiﬁcant

bit last.

Automatic Receiver Polarity

Reversal

State of SI at reset

Extended Distance Mode

Blink Rate

Disabled

Off

Software Override of LEDs

Disabled

22

Am79C984A

P R E L I M I N A R Y

Table 5. Control Port Command Summary

SI Data

Commands

SO Data

Set (Write Commands)

eIMR Chip Programmable Options

0000 10S0

Alternate AUI Partitioning Algorithm

Alternate TP Partitioning Algorithm

AUI Port Disable

0001 1111

0001 0000

0010 1111

0011 1111

0010 00##

0011 00##

0100 00##

0101 00##

0100 10##

0101 10##

0110 00##

AUI Port Enable

TP Port Disable

TP Port Enable

Disable Link Test Function (per TP port)

Enable Link Test Function (per TP port)

Disable Link Pulse (per TP port)

Enable Link Pulse (per TP port)

Disable Automatic Receiver Polarity Reversal

(per TP port)

Enable Automatic Receiver Polarity Reversal

(per TP port)

0111 00##

0110 10##

0111 10##

1001 ####

1011 ####

1100 ####

1110 1###

Disable Receiver Extended Distance Mode

(per TP port)

Enable Receiver Extended Distance Mode

(per TP port)

Disable Software Override of LEDs

(per Port - AUI & TP)

Enable Software Override of Bank A LEDs

(per Port - AUI & TP, Global)

Enable Software Override of Bank B LEDs

(per Port - AUI & TP, Global)

Software Override LED Blink Rate

Get (Read Commands)

AUI Port Status (B, S, and L Cleared)

AUI Port Status (B Cleared)

AUI Port Status (S, L, Cleared)

AUI Port status (None Cleared)

TP Port Partitioning Status

Bit Rate Error Status of TP Ports

Link Test Status of TP Ports

Receive Polarity Status of TP Ports

MJLP Status

1000 1111

1000 1101

1000 1011

1000 1001

1000 0000

1010 0000

1101 0000

1110 0000

1111 0000

1111 1111

PBSL 0000

0000 C3..C0

0000 E3..E0

0000 L3..L0

0000 P3..P0

M000 0000

0000 0011

Version

Am79C984A

23

P R E L I M I N A R Y

AUI Port Enable

SET (Write Commands)

Chip Programmable Option

SI

0011 1111

None

SO Data

SI Data

SO Data

0000 10S0

None

This command enables the AUI port.

TP Port Disable

The eIMR chip programmable option can be enabled

(or disabled) by setting (or resetting) the S bit in the

command string.

SI Data

SO Data

0010 00##

None

S

AUI SQE Test Mask

This command disables the TP port designated by the

two least-signiﬁcant bits of the command byte. Subse-

quently, the eIMR chip will ignore all inputs to the des-

ignated port and will not transmit a DAT or JAM pattern

on that port. Disabling the TP port also sets the parti-

tioning state machine of that port to the idle state.There-

fore, a partitioned port can be reconnected by ﬁrst

disabling the port and then enabling it.

Setting this bit allows the eIMR chip to ignore activity on

the CI signal pair, during the SQE test window, following

a transmission on the AUI port. Enabling this function

does not prevent the reporting of this condition by the

eIMR device.The two functions operate independently.

The SQE Test Window, as deﬁned in IEEE 802.3 (Sec-

tion 7.2.2.2.4) is from 6 bit times to 34 bit times (0.6 µs

to 3.4 µs). This includes the delay introduced by a 50-

meter AUI. CI activity that occurs outside this window is

not ignored and is treated as a true collision.

TP Port Enable

SI Data

SO Data

0011 00##

None

Alternate AUI Partitioning Algorithm

This command enables the TP port designated by the

two least-signiﬁcant bits of the command byte.

SI Data

0001 1111

None

SO Data

Disable Link Test Function (Per TP port)

Invoking this command sets the partition/reconnection

scheme for the AUI port to the alternate (transmit-only)

reconnection algorithm. To return the AUI port to the

standard (transmit or receive) reconnection algorithm,

it is necessary to reset the eIMR device. The standard

partitioning algorithm is selected on reset.

SI Data

SO Data

0100 00##

None

This command disables the Link Test function of the TP

port designated by the two least-signiﬁcant bits of the

command data. As a consequence of this, the port will

no longer be disconnected if it fails the Link Test. If a

port has the Link Test disabled, reading the Link Test

Status indicates a ‘Link Pass’.

Alternate TP Partitioning Algorithm

SI Data

SO Data

0001 0000

None

Enable Link Test Function (Per TP port)

Invoking this command sets the partition/reconnection

scheme for the TP ports to the alternate (transmit-only)

reconnection algorithm. To return the TP ports to the

standard (transmit or receive) reconnection algorithm,

it is necessary to reset the eIMR device. The standard

partitioning algorithm is selected on reset.

SI Data

SO Data

0101 00##

None

This command enables the Link Test function of the TP

port designated by the two least-signiﬁcant bits of the

command data. As a consequence of this, the port is

disconnected if it fails the Link Test.

AUI Port Disable

Disable Link Pulse (Per TP Port)

SI

0010 1111

None

SI Data

SO Data

0100 10##

None

SO Data

This command disables the AUI port.Subsequently, the

eIMR chip will ignore all inputs to this port and will not

transmit a DAT or JAM pattern on the AUI port.Disabling

the AUI port also sets the partitioning state machine of

the AUI port to the idle state. Therefore, a partitioned

port can be reconnected by ﬁrst disabling the AUI port

and then enabling the AUI port.

This command disables the transmission of the Link

pulse on the TP port designated by the two least-

signiﬁcant bits of the command byte.

Enable Link Pulse (Per TP Port)

SI Data

SO Data

0101 10##

None

This command enables the transmission of the Link

pulse on the TP port designated by the two least-

signiﬁcant bits of the command byte.

24

Am79C984A

P R E L I M I N A R Y

Disable Automatic Receiver Polarity Reversal (Per TP

Port)

Disable Software Override of LEDs

(Per Port - AUI and TP, Global)

SI Data

SO Data

0110 00##

None

SI Data

SO Data

1001 ####

None

This command disables the Automatic Receiver Polarity

Reversal function for the TP port designated by the two

least-signiﬁcant bits in the command byte. If this func-

tion is disabled on a TP port receiving with reversed

polarity (due to a wiring error), the TP port will fail the

Link Test due to the incorrect polarity of the received

Link pulses.

This command disables Software Override of the Port

LEDs.

Individual LEDs and combinations of LEDs can be

selected via the lower four bits of the command byte as

follows:

####

Port(s) affected

0000-0011 TP0 - TP3

0100-0111 Reserved

The state of Automatic Polarity Reversal function is set

by SI on reset. If SI is HIGH at the rising edge of RST,

the eIMR device disables Automatic Polarity Reversal.

If SI is LOW at the rising edge of RST, the eIMR device

enables Automatic Polarity Reversal.

1000

1001

1010

1011

1100

1101

1110

1111

AUI port

Reserved

All TP ports

All ports

Global

Reserved

Enable Automatic Receiver Polarity Reversal (Per TP

Port)

SI Data

SO Data

0111 00##

None

Following command execution, the attributes displayed

This command enables the Automatic Receiver Polarity

Reversal function for the TP port designated by the two

least-signiﬁcant bits in the command byte. If enabled in

a TP port, the eIMR chip will automatically invert the

polarity of that port’s receiver circuitry if the TP port is

detected as having reversed polarity (due to wiring er-

ror). After reversing the receiver polarity, the TP port

could then receive subsequent (reverse polarity)

packets correctly.

on the LEDs will be determined by LDC . Software

0-2

Override of LEDs is disabled after reset.

Enable Software Override of Bank A LEDs (Per Port -

AUI and TP, Global)

SI Data

SO Data

1011 ####

None

This command forces the LEDs in Bank A to blink. In-

dividual LEDs and combinations of LEDs can be select-

edviathelowerfourbitsofthecommandbyteasfollows:

Disable Receiver Extended Distance Mode (Per TP

Port)

####

Port(s) affected

SI Data

SO Data

0110 10##

None

0000-0011 TP0 - TP3

0100-0111 Reserved

This command disables the Receiver Extended

DistanceModeandrestorestheRXDcircuitofthetrans-

ceiver to normal squelch levels for the TP port driver

designated by the two least-signiﬁcant bits of the com-

mand data.

1000

1001

1010

1011

1100

1101

1110

1111

AUI port

Reserved

All TP ports

All ports

Global

Reserved

EnableReceiverExtendedDistanceMode(PerTPPort)

SI Data

SO Data

0111 10##

None

The designated LED driver(s) will switch between LOW

and ‘off’ at the rate set by the Software Override Blink

Rate command. Enable Software Override of Bank A

LEDs references the blink rate last issued and overrides

This command modiﬁes the RXD circuit of the trans-

ceiver for theTP port driver designated by the two least-

signiﬁcant bits of the command data.The RXD squelch-

threshold value is lowered to accommodate signal at-

tenuation associated with lines longer than 100 meters.

At reset, Receiver Extended Distance Mode is disabled

and the RXD circuit defaults to normal squelch-thresh-

old values.

any other attribute speciﬁed by LDC . Software Over-

0-2

ride of LEDs is disabled after reset.

Am79C984A

25

P R E L I M I N A R Y

Enable Software Override of Bank B LEDs (Per Port -

B

Bit Rate Error

AUI and TP, Global)

Thisbitissetto‘1’ifthereisaninstanceofFIFOoverﬂow

or underﬂow. The bit is cleared when the eIMR device

is read.

SI Data

SO Data

1100 ####

None

This command forces the LEDs in Bank B to blink. In-

dividual LEDs and combinations of LEDs can be select-

edviathelowerfourbitsofthecommandbyteasfollows:

S

SQE Test Status

This bit is set to ‘1’ if the SQE test error is detected by

the eIMR chip.The bit is cleared when the status is read.

####

Port(s) affected

L

Loopback Error

0000-0011 TP0 - TP3

0100-0111 Reserved

The MAU attached to the AUI port is required to loop-

back data transmitted to DO onto the DI circuit. If the

loopback carrier is not detected by the eIMR device, this

bit is set to‘1’.This bit is cleared when the status is read.

1000

1001

1010

1011

1100

1101

1110

1111

AUI port

Reserved

All TP ports

All ports

Global

Reserved

Alternate AUI Port(s) Status

There are three further variations of the AUI Port Status

Command allowing selective clearing of a combination

of B,S, and L bits. These are the following:

The designated LED driver(s) will switch between LOW

and ‘off’ at the rate set by the Software Override of LED

Blink Rate command. Enable Software Override of

Bank B LEDs references the blink rate last issued and

Alternate 1: B is not cleared, S and L are Cleared

SI Data

1000 1011

PBSL 0000

SO Data

overrides any other attribute speciﬁed by LDC . Soft-

Alternate 2: S and L are not cleared, B is Cleared

0-2

ware Override of LEDs is disabled after reset.

SI Data

SO Data

1000 1101

PBSL 0000

Software Override of LED Blink Rate

SI Data

SO Data

1110 1###

None

Alternate 3: None of S, B, and L are Cleared

SI Data

SO Data

1000 1001

PBSL 0000

This command sets the blink period of the LEDs with

Software Override enabled.The duty cycle is 50%.This

command defaults to ‘off’ at reset.

TP Port Partitioning Status

SI Data

SO Data

1000 0000

0000 P3..P0

Setting

Blink Period

Off

512 ms

1560 ms

Solid On

1110 1000

1110 1001

1110 1010

1110 1011

Pn = 0

Pn = 1

TP Port Partitioned

TP port Connected

where n is a port number in the range 0–3.

These settings apply to the blink rate for both Bank A

and Bank B. This command must precede the Enable

Software Override of Bank A/B LEDs command.All LED

combinations selected for Software Override will refer-

ence the blink rate last issued.

The response to this command gives the partitioning

status of all four TP ports. If a port is disabled, reading

its partitioning status will indicate that it is connected.

Bit Rate Error Status of TP Ports

SI Data

1010 0000

GET (Read Commands)

SO Data

0000 E3..E0

AUI Port(s) Status

En = 0

En = 1

No Error

FIFO Overﬂow

SI Data

SO Data

1000 1111

PBSL 0000

where n is a port number in the range 0–3.

The combined AUI status of the eIMR device allows a

single instruction to be used to monitor the AUI port.

The four local status bits are:

The response to this command gives the bit-rate-over-

ﬂow or underﬂow (data rate mismatch) condition of all

theTP ports.A 1 indicates that the FIFO has overﬂowed

or underﬂowed due to the amount of data received by

the corresponding port.

P

Partitioning Status

This bit is ‘0’ if the AUI port is partitioned and ‘1’ if the

AUI port is connected.

26

Am79C984A

P R E L I M I N A R Y

Link Test Status of TP ports

SYSTEMS APPLICATIONS

SI Data

SO Data

1101 0000

0000 L3..L0

eIMR to TP Port Connection

The eIMR device provides a system solution to designing

non-managed multiport repeaters.The eIMR device con-

nects directly to AC coupling modules for a 10BASE-T

hub. Figure 7 shows the simpliﬁed connection.

Ln = 0

Ln = 1

TP Port n in Link Test Failed

TP port n in Link Test Passed

where n is a port number in the range 0–3.

The response to this command gives the Link Test sta-

tus of all theTP ports.A disabled port continues to report

Link Test status. Re-enabling the port causes the port

to be placed in the Link Test Fail state.

Twisted Pair Transmitters

TXD signals need to be properly terminated to meet the

electrical requirement for 10BASE-T transmitters.Prop-

er termination is shown in Figure 8 which consists of a

110-Ω resistor and a 1:1 transformer.The load is a twisted-

pair cable that meets IEEE 802.3, Section 14.4 speciﬁ-

cations. The cable is terminated at the opposite end by

100 Ω.

Receive Polarity Status of TP Ports

SI Data

1110 0000

SO Data

0000 P3......P0

Pn = 0

Pn = 1

TP Port n Polarity Correct

TP port n Polarity Reversed

Twisted Pair Receivers

where n is a port number in the range 0–3.

RXD signals need to be properly terminated to meet the

electrical requirements for 10BASE-T receivers. Proper

termination is shown in Figure 9.Note that the receivers

do not require external ﬁlter modules.

The response to this command gives the Received Po-

larity status of all the TP ports. If the polarity is detected

as reversed for a TP port, then the eIMR device will set

the appropriate bit in this command’s result only if the

Polarity Reversal Function is enabled for that port.

MJLP Status

SI Data

SO Data

1111 0000

M000 0000

Each eIMR device contains an independent MAU Jab-

ber Lock Up Protection timer. The timer is designed to

inhibit the transmit function of the eIMR device if it has

been transmitting continuously for more than 65536 bit

times.This bit remains set and is only cleared when the

MJLP status is read using this command.

Version

SI Data

SO Data

1111 1111

0000 0011

The response to this command gives the version of the

eIMR device. 0011 was chosen to help distinguish the

eIMR device from the IMR (Am79C980) and the IMR+

(Am79C981) devices.

Am79C984A

27

P R E L I M I N A R Y

eIMR

TP Connector

1:1

TXD0+

TXD0–

110 Ω

100 Ω

1:1

RXD0+

RXD0–

1:1

TXD1+

TXD1–

110 Ω

100 Ω

RXD1+

RXD1–

1:1

TXD2+

TXD2–

110 Ω

100 Ω

RXD2+

RXD2–

1:1

TXD3+

TXD3–

110 Ω

100 Ω

RXD3+

RXD3–

RST

CLK

20650A-12

Figure 7. Simpliﬁed 10BASE-T Connection

1:1

TXD+

TXD-

Twisted Pair

100Ω

110Ω

20650A-13

20650B-13

Figure 8. TXD Termination

RXD+

1:1

Twisted Pair

100Ω

RXD–

20650A-14

20650B-14

Figure 9. RXD Termination

Am79C984A

28

P R E L I M I N A R Y

of the MAC and DO is connected to DI of the MAC,

MAC Interface

because the reverse conﬁguration only affects CI.

Where CI is an input in the normal mode, in the reverse

mode, CI is an output.Figure 10b shows the normal AUI

conﬁguration for reference.

The eIMR device can be connected directly to a MAC

through the AUI port.This requires that the AUI port be

conﬁgured in the reverse mode and connected as

shown in Figure 10a. Notice that DI is connected to DO

Am79C940

eIMR

Am7996

eIMR

1:1

DO+

DO–

DI+

DI–

DI+

DI–

DI+

DI–

40 Ω

1:1

DI+

DI–

DO+

DO–

DO+

DO–

DO+

DO–

0.1 µF

40 Ω

1:1

CI+

CI–

CI+

CI–

CI+

CI–

CI+

CI–

40 Ω

0.1 µF

39 – 150 Ω

0.1 µF

–9 V

b) Normal Mode (with MAU)

a) Reverse Mode (with MAC)

20650B-15

20650A-16

Figure 10. AUI Port Interconnections

Internal Arbitration Mode Connection

IMR+ Mode External Arbitration

The internal arbitration mode uses a modiﬁed daisy-

chain scheme to eliminate the need for any external

arbiter. In this mode, ACK and COL need to be pulled

up through a minimum resistance of 1 kΩ. The DAT and

JAM pins also need to be pulled down via a high value

resistor. Refer to Figure 11.

The IMR+ mode maintains the full functionality of AMD’s

IMR+ (Am79C981) device’s expansion bus. In this

mode, the eIMR device requires external circuitry to

handle arbitration for control of the bus.Figure 12 shows

the conﬁguration for the IMR+ mode of operation.

Am79C984A

29

P R E L I M I N A R Y

V_DD

eIMR

SELI_0

SELI_1

RST

(Note: In a multiple eIMR system, the reset

signal must be synchronized to CLK.)

SELO

74LS74

eIMR

SELI_0

SELI_1

RST

CLK

RST

D

Q

D

Q

SELO

CLK

P

C

P

C

V_DD

20 MHz

OSC

~1 kΩ

1 kΩ

eIMR

SELI_0

SELI_1

RST

V_DD

~1 kΩ

SELO

CLK

20650B-16

Figure 11. eIMR Internal Arbitration Mode Connection

eIMR

SELI_0

eIMR

SELI_0

SELO

SELI_1

DAT JAM ACK COL

SELI_1

DAT JAM ACK COL

1 kΩ

COL ACK SEL1 SEL2 SEL3

Arbiter

GCOL

20650B-17

Figure 12. IMR+ Mode External Arbitration

30

Am79C984A

P R E L I M I N A R Y

Visual Status Display

VDD

LDA/B[4:0] and LDGA/B provide visual status indicators

for the eIMR. LDA/B[4:0] displays Link, Carrier Sense,

Collision, and Partition information for the TP and AUI

ports. LDGA/B display global Carrier Sense, Collision,

and Jabber information.

LDA[4:0]

LDB[4:0]

In a multiple eIMR conﬁguration, the global LED drivers

(LDGA/B) from each chip can be tied together to drive

a single pair of global status LEDs.The open drain out-

put of these drivers facilitate this conﬁguration. Refer to

Figure 13.

LDGA

LDGB

LDA[4:0]

LDB[4:0]

LDGA

LDGB

20650B-18

20650A-19

Figure 13. Visual Status Display Connection

Am79C984A

31

P R E L I M I N A R Y

ABSOLUTE MAXIMUM RATINGS

OPERATING RANGES

Storage Temperature . . . . . . . . . . –65° C to +150° C

Ambient Temperature Under Bias . . . . 0° C to +70° C

Supply Voltage referenced to

Commercial (C) Devices

Temperature (T ) . . . . . . . . . . . . . . . . . 0° C to +70° C

A

Supply Voltages (V ) . . . . . . . . . . . . . . . . . +5 V ±5%

DD

AV or DV (AV , DV ). . . . . . . –0.3 V to +6.0 V

SS

DD

Operating ranges deﬁne those limits between which the

functionality of the device is guaranteed.

Stresses above those listed under ABSOLUTE MAXI-

MUM RATINGS may cause permanent device failure.

Functionality at or above these limits is not implied. Ex-

posure to Absolute Maximum Ratings for extended pe-

riods may affect reliability.Programming conditions may

differ.

DC CHARACTERISTICS over operating ranges unless otherwise speciﬁed

Parameter

Symbol

Parameter Description

Test Conditions

Min

Max

Unit

Digital I/O

V

Input LOW Voltage

V

= 0.0 V

–0.5

2.0

0.8

V

IL

SS

OL

V

Input HIGH Voltage

0.5 + V

IH

DD

V

Output LOW Voltage

I

= 4.0 mA

–

2.4

–

0.4

–

V

OL

V

Output HIGH Voltage

I

= –0.4 mA

OH

I

Input Leakage Current

V

<V <V

10

50

0.4

µA

V

IL

SS

IN

DD

I

Input Leakage Current for STR pin

Open Drain Output LOW Voltage (LED pins)

<V <V

–

ILSTR

SS

IN

DD

V

I

= 12 mA

–

OLOD

AUI Ports

I

Input Current at DI± and CI± Pairs

V

<V <V

–500

500

µA

V

IAXD

SS

IN

DD

V

DI±, CI± Open Circuit Input Voltage Range

I

= 0

V

– 3.0

V

– 1.0

AICM

IN

DD

V

Differential Mode Input Voltage Range

(DI, CI)

V

= 5.0 V

–2.5

+2.5

V

AIDV

DD

V

DI, CI Squelch Threshold

–

–275

-35

–160

+35

mV

ASQ

V

DI Switching Threshold

(Note 1)

R = 78 Ω

ATH

V

Differential Output Voltage (DO+) – (DO)

620

1100

AOD

L

V

Differential Output Voltage (CI+) – (CI–)

(Reverse Mode)

R = 78 Ω

L

AOC

V

DO Differential Output Voltage Imbalance

R = 78 Ω

–25

–40

–1.0

2.5

+25

+40

+1.0

mV

mA

V

AODI

L

V

OFF DO Differential Idle Output Voltage

R = 78 Ω

L

AOD

I

OFF DO Differential Idle Output Current

R = 78 Ω (Note 1)

L

AOD

V

DO+, DO- Common Mode Output Voltage

R = 78 Ω

V

DD

AOCM

L

Twisted Pair Ports

I

Input Current at RXD±

and CI± Pairs

AV <V <V

DD

–500

10

500

–

µA

IRXD

SS

IN

R

RXD Differential Input

(Note 1)

kΩ

RXD

V

RXD+, RXD– Open Circuit

Input Voltage (bias)

V

– 3.0

V

– 1.5

V

TIVB

DD

V

Differential Mode Input

Range (RXD)

V

= 5.0 V

–3.1

+3.1

V

TID

DD

32

Am79C984A

P R E L I M I N A R Y

DC CHARACTERISTICS (continued)

Parameter

Symbol

Parameter Description

Test Conditions

Sinusoid

Min

Max

Unit

Twisted Pair Ports (Continued)

V

RXD Positive Squelch Threshold

(peak)

300

–520

150

520

–300

293

mV

TSQ+

TSQ–

THS+

5 MHz<f<10 MHz

RXD Negative Squelch Threshold

(peak)

Sinusoid

5 MHz<f<10 MHz

RXD Post-Squelch Positive

Threshold (peak)

Sinusoid

5 MHz<f<10 MHz

V

RXD Post-Squelch Negative

Threshold (peak)

Sinusoid

5 MHz<f<10 MHz

–293

180

–150

365

THS–

V

RXD Positive Squelch Threshold

(peak) - Extended Distance Mode

Sinusoid

5 MHz<f<10 MHz

LTSQ+

LTSQ–

LTHS+

RXD Negative Squelch Threshold

(peak) - Extended Distance Mode

Sinusoid

5 MHz<f<10 MHz

–365

90

–180

175

RXD Post-Squelch Positive

Threshold - Extended Distance Mode

Sinusoid

5 MHz<f<10 MHz

V

RXD Post-Squelch Negative

Threshold - Extended Distance Mode

Sinusoid

5 MHz<f<10 MHz

–175

–60

–90

LTHS–

V

RXD Switching Threshold

(Note 1)

60

RXDTH

Power Supply Current

I

Power Supply Current

(Idle) (Note 2)

CLK = 20 MHz

–

100

350

mA

DD

V

= +5.25V

DD

Power Supply Current

(Transmitting)

CLK = 20 MHz

= +5.25V

V

DD

Notes:

1. Parameter not tested.

2. LED current not included. Maximum current rating on LED drivers is 12 mA.

Am79C984A

33

P R E L I M I N A R Y

SWITCHING CHARACTERISTICS

Parameter

Symbol

Parameter Description

Test Conditions

Min

Max

Unit

Clock and Reset Timing

t

CLK Clock Period

CLK Clock High

49.995

20

–

50.005

ns

µs

ns

CLK

t

30

10

–

CLKH

t

CLK Clock Low

CLKL

CLKR

t

CLK Rise Time

t

CLK Fall Time

–

CLKF

PRST

t

Reset Pulse Width after Power On

Reset Pulse Width

150

4

t

–

RST

t

Reset HIGH Setup Time with respect to

CLK

15

–

RSTSET

t

Reset LOW Hold Time

0

–

ns

RSTHLD

t

AMODE, SELI , and SI_D Setup Time

XRS

0

to Rising Edge of RST

t

AMODE,SELI , and SI_D Hold Time

400

–

ns

XRH

0

from Rising Edge of RST

AUI Port Timing

t

CLK Rising Edge to DO Toggle

–

30

7.0

1.0

375

45

ns

DOTD

DOTR

DO+, DO– Rise Time (10% to 90%)

DO+, DO– Fall Time (90% to 10%)

DO+, DO– Rise and Fall Time Mismatch

DO± End of Transmission

t

–

DOTF

t

–

DORM

t

275

15

136

DOETD

t

DI Pulse Width Accept/Reject Threshold

|V |>|V

| (Note 2)

| (Note 3)

PWODI

IN

ASQ

t

DI Pulse Width Not to Turn-off Internal

Carrier Sense

|V |>|V

200

PWKDI

IN

ASQ

t

CI Pulse Width Accept/Reject Threshold

CI Pulse Width Not to Turn-off Threshold

CI Rise Time (In Reverse Mode)

|V |>|V

| (Note 4)

| (Note 5)

10

75

–

26

160

7.0

1.0

ns

PWOCI

IN

ASQ

t

|V |>|V

IN

PWKCI

ASQ

t

CITR

t

CI Fall Time (In Reverse Mode)

–

CITF

t

CI+, CI– Rise and Fall Time Mismatch

(AUI in Reverse Mode)

–

CIRM

Expansion Bus Timing

t

CLK HIGH to SELO Driven LOW

CLK HIGH to SELO Driven HIGH

CLK HIGH to DAT/JAM Driven

CLK HIGH to DAT/JAM Not Driven

DAT/JAM Setup Time to CLK

DAT/JAM Hold Time from CLK

COL/ACK Setup Time to CLK

COL/ACK Hold Time from CLK

SI, SCLK Hold Time

C = 50 pF

15

14

10

9

30

–

ns

CLKHRL

CLKHRH

CLKHDR

L

t

C = 50 pF

L

C = 100 pF

L

t

C = 100 pF

CLKHDZ

L

t

DJSET

t

–

DJHOLD

t

10

9

–

CASET

t

–

CAHLD

t

50

–

SCLKHLD

34

Am79C984A

P R E L I M I N A R Y

SWITCHING CHARACTERISTICS (continued)

Parameter

Symbol

Parameter Description

Test Conditions

Min

Max

Unit

Twisted Pair Port Timing

t

CLK Rising Edge to TXD± Transition Delay

–

50

ns

TXTD

TETD

Transmit End of Transmission

250

136

375

200

t

RXD Pulse Width Maintain/Turn-off

Threshold

|V |>|V

| (Note 6)

PWKRD

IN

THS

t

Idle Signal Period

8

24

ms

ns

PERLP

t

Idle Link Test Pulse Width

75

120

PWLP

Control Port Timing

t

SCLK Clock Period

100

30

–

ns

SCLK

t

SCLK Clock HIGH

SCLKH

t

SCLK Clock LOW

–

SCLKL

SCLKR

t

SCLK Clock Rise Time

10

–

t

SCLK Clock Fall Time

–

SCLKF

t

SI Input Setup Time to SCLK Rising Edge

SI Input Hold Time from SCLK Rising Edge

SO Output Delay from SCLK Rising Edge

10

–

SISET

SIHLD

SODLY

t

–

t

C = 100 pF

40

L

Notes:

1. Parameter not tested.

2. DI pulses narrower than t

(min) will be rejected; pulses wider than t

(max) will turn internal DI carrier sense on.

PWODI

3. DI pulses narrower than t

carrier sense off.

(min) will maintain internal DI carrier on; pulses wider than t

(max) will turn internal DI

PWKDI

4. CI pulses narrower than t

(min) will be rejected; pulses wider than t

(max) will turn internal CI carrier sense on.

PWOCI

5. CI pulses narrower than t

carrier sense off.

(min) will maintain internal CI carrier on; pulses wider than t

(max) will turn internal CI

PWKCI

6. RXD pulses narrower than t

RXD carrier sense off.

(min) will maintain internal RXD carrier sense on; a pulse wider than t

(max) will turn

PWKRD

Am79C984A

35

P R E L I M I N A R Y

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

Must be

Steady

Will be

Steady

May

Change

from H to L

Will be

Changing

from H to L

May

Change

from L to H

Will be

Changing

from L to H

Don’t Care,

Any Change

Permitted

Changing,

State

Unknown

Does Not

Apply

Center

Line is High-

Impedance

“Off” State

KS000010-PAL

SWITCHING WAVEFORMS

t_CLK

t_CLKH

t_CLKL

CLK

t_CLKF

t_CLKR

20650A-20

20650B-19

Figure 14. Clock Timing

36

Am79C984A

P R E L I M I N A R Y

SWITCHING WAVEFORMS (continued)

t_SCLKR

t_SCLK

t_SCLKF

SCLK

t_SCLKH

t_SCLKL

SI

t_SISET

t_SODLY

t_SIHLD

SO

20650B-20

20650A-21

Figure 15. Control Port Timing

CLK

t_RSTSET

t_RSTHLD

RST

t_RST

or t_PRST

TCLK

Note: TCLK represents internal eIMR timing

20650B-21

20650A-22

Figure 16. Reset Timing

AMODE, SELI_0

t_XRH

t_XRS

RST

20650B-22

Figure 17. Mode Initialization

Am79C984A

37

P R E L I M I N A R Y

SWITCHING WAVEFORMS (continued)

CLK

TCLK

SELO

ACK

COL

t_DJHOLD

t_DJSET

DAT/JAM

IN

Note: TCLK represents internal eIMR timing

20650B-23

Figure 18. Expansion Bus Input Timing

CLK

TCLK

t_CLKHRH

t_CLKHRL

SELO

t_CASET

ACK

COL

t_CAHLD

t_CLKHDZ

t_CLKHDR

DAT/JAM

OUT

Note: TCLK represents internal eIMR timing

Figure 19. Expansion Bus Output Timing

20650B-24

38

Am79C984A

P R E L I M I N A R Y

SWITCHING WAVEFORMS (continued)

CLK

TCLK

t_CLKHRH

SELO

t_CASET

t_CLKHRL

ACK

COL

t_CASET

t_CAHLD

IN

DAT/JAM

20650B-25

Note: TCLK represents internal eIMR timing

20650A-26

Figure 20. Expansion Bus Collision Timing

CLK

DO+

DO–

t_DOETD

t_DOTD

t_DOTR

t_DOTF

20650B-26

Figure 21. AUI Timing Diagram

t_PWKDI

(t_PWKCI

)

(t_PWKCI

)

DI+

(CI±)

V_ASQ

t_PWODI

(t_PWOCI

)

20650A-28

20650B-27

Figure 22. AUI Receive Diagram

Am79C984A

39

P R E L I M I N A R Y

SWITCHING WAVEFORMS (continued)

1

0

1

0

1

0

1

0

ETD

CLK

t_TXETD

TXD+

TXD–

20650A-29

20650B-28

Figure 23. TP Ports Output Timing Diagram

t_PWLP

t_PERLP

Figure 24. TP Idle Link Test Pulse

t_PWKRD

V_TSQ+

V_THS+

V_THS–

RXD+/–

V_TSQ–

t_PWKRD

Figure 25. TP Receive Timing Diagram

40

Am79C984A

P R E L I M I N A R Y

SWITCHING TEST CIRCUIT

V_DD

Test Point

V_SS

20650A-32

20650B-31

Figure 26. Switching Test Circuit

Am79C984A

41

P R E L I M I N A R Y

PHYSICAL DIMENSIONS

PL 084

84-Pin Plastic LCC (measured in inches)

.062

.083

1.185

1.195

.042

.056

1.150

1.156

1.090

1.130

1.000

REF

Pin 1 I.D.

1.185

1.195

1.150

1.156

.013

.021

.007

.013

.026

.032

.090

.130

.165

.180

.050 REF

SEATING PLANE

16-038-SQ

PL 084

DF79

8-1-95 ae

TOP VIEW

SIDE VIEW

42

Am79C984A

P R E L I M I N A R Y

PHYSICAL DIMENSIONS

PQR100

100-Pin Plastic Quad Flat Pack

17.00

17.40

13.90

14.10

Pin 100

12.35

REF

Pin 80

Pin 1 I.D.

18.85

REF

19.90

20.10

23.00

23.40

Pin 30

Pin 50

2.70

2.90

3.35

MAX

0.65 BASIC

0.25

MIN

SEATING PLANE

16-038-PQR-2

PQR100

DA92

8-2-94 ae

Am79C984A

43

Trademarks

AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.

Am186, Am386, Am486, Am29000, bIMR, eIMR, eIMR+, GigaPHY, HIMIB, ILACC, IMR, IMR+, IMR2, ISA-HUB, MACE, Magic Packet, PCnet,

PCnet-FAST, PCnet-FAST+, PCnet-Mobile, QFEX, QFEXr, QuASI, QuEST, QuIET, TAXIchip, TPEX, andTPEX Plus are trademarks of Advanced

Micro Devices, Inc.

Microsoft is a registered trademark of Microsoft Corporation.

Product names used in this publication are for identiﬁcation purposes only and may be trademarks of their respective companies.


型号：	AM79C984
厂家：	AMD
描述：	enhanced Integrated Multiport Repeater (eIMR⑩) 强化综合多端中继器（ eIMR ™ ）中继器
文件：	总44页 (文件大小：221K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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