L160DB70VD [AMD]

Am29LV160D

Data Sheet

RETIRED

PRODUCT

This product has been retired and is not recommended for designs. For new and current designs,

S29AL016D supersedes Am29LV160D and is the factory-recommended migration path for this

device. Please refer to the S29AL016D data sheet for specifications and ordering information. Avail-

ability of this document is retained for reference and historical purposes only.

The following document contains information on Spansion memory products.

Continuity of Specifications

There is no change to this data sheet as a result of offering the device as a Spansion product. Any

changes that have been made are the result of normal data sheet improvement and are noted in the

document revision summary.

For More Information

Please contact your local sales office for additional information about Spansion memory solutions.

Publication Number

22358

Revision

B

Amendment

7

Issue Date

May 5, 2006

DATA SHEET

Am29LV160D

16 Megabit (2 M x 8-Bit/1 M x 16-Bit)

CMOS 3.0 Volt-only Boot Sector Flash Memory

This product has been retired and is not recommended for designs. For new and current designs, S29AL016D supersedes Am29LV160D and is the factory-recommended migration path

for this device. Please refer to the S29AL016D data sheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only.

DISTINCTIVE CHARACTERISTICS

■

Single power supply operation

— Full voltage range: 2.7 to 3.6 volt read and write

operations for battery-powered applications

— Regulated voltage range: 3.0 to 3.6 volt read and

write operations and for compatibility with high

performance 3.3 volt microprocessors

■

Manufactured on 0.23 µm process technology

— Fully compatible with 0.32 µm Am29LV160B device

■

High performance

— Access times as fast as 70 ns

■

Ultra low power consumption (typical values at

5 MHz)

— 200 nA Automatic Sleep mode current

— 200 nA standby mode current

— 9 mA read current

— 20 mA program/erase current

■

Flexible sector architecture

— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and

thirty-one 64 Kbyte sectors (byte mode)

— One 8 Kword, two 4 Kword, one 16 Kword, and

thirty-one 32 Kword sectors (word mode)

— Supports full chip erase

— Sector Protection features:

— A hardware method of locking a sector to prevent any

program or erase operations within that sector

— Sectors can be locked in-system or via programming

equipment

■

Embedded Algorithms

— Embedded Erase algorithm automatically

preprograms and erases the entire chip or any

combination of designated sectors

— Embedded Program algorithm automatically

writes and verifies data at specified addresses

■

Minimum 1,000,000 write cycle guarantee

per sector

■

20-year data retention at 125°C

— Reliable operation for the life of the system

■

Package option

— 48-ball FBGA

— 48-pin TSOP

— 44-pin SO

■

CFI (Common Flash Interface) compliant

— Provides device-specific information to the

system, allowing host software to easily

reconfigure for different Flash devices

■

Compatibility with JEDEC standards

— Pinout and software compatible with single-

power supply Flash

— Superior inadvertent write protection

■

Data# Polling and toggle bits

— Provides a software method of detecting program

or erase operation completion

■

Ready/Busy# pin (RY/BY#)

— Provides a hardware method of detecting

program or erase cycle completion (not available

on 44-pin SO)

■

Erase Suspend/Erase Resume

— Suspends an erase operation to read data from,

or program data to, a sector that is not being

erased, then resumes the erase operation

■

Hardware reset pin (RESET#)

— Hardware method to reset the device to reading

array data

Temporary Sector Unprotect feature allows code

changes in previously locked sectors

■

Unlock Bypass Program Command

— Reduces overall programming time when issuing

multiple program command sequences

■

Top or bottom boot block configurations

available

This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data

Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.

Publication#

22358

Rev:

B

Amendment:

7

Issue Date:

May 5, 2006

D A T A

S H E E T

GENERAL DESCRIPTION

The Am29LV160D is a 16 Mbit, 3.0 Volt-only Flash

memory organized as 2,097,152 bytes or 1,048,576

words. The device is offered in 48-ball FBGA, 44-pin

SO, and 48-pin TSOP packages. The word-wide data

(x16) appears on DQ15–DQ0; the byte-wide (x8) data

appears on DQ7–DQ0. This device is designed to be

programmed in-system with the standard system 3.0

volt V

CC

supply. A 12.0 V V

PP

or 5.0 V

CC

are not re-

quired for write or erase operations. The device can

also

be

programmed

in

standard

EPROM programmers.

The device offers access times of 70, 90, and 120 ns,

allowing high speed microprocessors to operate with-

out wait states. To eliminate bus contention the device

has separate chip enable (CE#), write enable (WE#)

and output enable (OE#) controls.

The device requires only a

single 3.0 volt power sup-

ply

for both read and write functions. Internally

generated and regulated voltages are provided for the

program and erase operations.

The Am29LV160D is entirely command set compatible

with the

JEDEC single-power-supply Flash stan-

dard.

Commands are written to the command register

using standard microprocessor write timings. Register

contents serve as input to an internal state-machine

that controls the erase and programming circuitry.

Write cycles also internally latch addresses and data

needed for the programming and erase operations.

Reading data out of the device is similar to reading

from other Flash or EPROM devices.

Device programming occurs by executing the program

command sequence. This initiates the

Embedded

Program

algorithm—an internal algorithm that auto-

matically times the program pulse widths and verifies

proper cell margin. The

Unlock Bypass

mode facili-

tates faster programming times by requiring only two

write cycles to program data instead of four.

Device erasure occurs by executing the erase com-

mand sequence. This initiates the

Embedded Erase

algorithm—an internal algorithm that automatically

preprograms the array (if it is not already programmed)

before executing the erase operation. During erase,

the device automatically times the erase pulse widths

and verifies proper cell margin.

The host system can detect whether a program or

erase operation is complete by observing the RY/BY#

pin, or by reading the DQ7 (Data# Polling) and DQ6

(toggle)

status bits.

After a program or erase cycle

has been completed, the device is ready to read array

data or accept another command.

The

sector erase architecture

allows memory sec-

tors to be erased and reprogrammed without affecting

the data contents of other sectors. The device is fully

erased when shipped from the factory.

Hardware data protection

measures include a low

V

CC

detector that automatically inhibits write opera-

tions during power transitions. The

hardware sector

protection

feature disables both program and erase

operations in any combination of the sectors of mem-

o r y. T h i s c a n b e a c h i ev e d i n - s y s t e m o r v i a

programming equipment.

The

Erase Suspend/Erase Resume

feature enables

the user to put erase on hold for any period of time to

read data from, or program data to, any sector that is

not selected for erasure. True background erase can

thus be achieved.

The

hardware RESET# pin

terminates any operation

in progress and resets the internal state machine to

reading array data. The RESET# pin may be tied to

the system reset circuitry. A system reset would thus

also reset the device, enabling the system micropro-

cessor to read the boot-up firmware from the Flash

memory.

The device offers two power-saving features. When

addresses have been stable for a specified amount of

time, the device enters the

automatic sleep mode.

The system can also place the device into the

standby mode.

Power consumption is greatly re-

duced in both these modes.

AMD’s Flash technology combines years of Flash

memory manufacturing experience to produce the

highest levels of quality, reliability and cost effective-

ness. The device electrically erases all bits within a

sector simultaneously via Fowler-Nordheim tunnel-

ing. The data is programmed using hot electron

injection.

2

Am29LV160D

May 5, 2006 22358B7

D A T A

S H E E T

TABLE OF CONTENTS

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9

Table 1. Am29LV160D Device Bus Operations ................................9

DQ3: Sector Erase Timer ....................................................... 28

Table 10. Write Operation Status ................................................... 28

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 29

Figure 7. Maximum Negative Overshoot Waveform ...................... 30

Figure 8. Maximum Positive Overshoot Waveform........................ 30

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 30

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 9. I

CC1

Current vs. Time (Showing Active and

Automatic Sleep Currents) ............................................................. 32

Figure 10. Typical I

CC1

vs. Frequency ........................................... 32

Word/Byte Configuration .......................................................... 9

Requirements for Reading Array Data ..................................... 9

Writing Commands/Command Sequences .............................. 9

Program and Erase Operation Status .................................... 10

Standby Mode ........................................................................ 10

Automatic Sleep Mode ........................................................... 10

RESET#: Hardware Reset Pin ............................................... 11

Output Disable Mode .............................................................. 11

Table 2. Sector Address Tables (Am29LV160DT) ..........................12

Table 3. Sector Address Tables (Am29LV160DB) ..........................13

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 11. Test Setup..................................................................... 33

Table 11. Test Specifications ......................................................... 33

Figure 12. Input Waveforms and Measurement Levels ................. 33

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 34

Read Operations .................................................................... 34

Figure 13. Read Operations Timings ............................................. 34

Hardware Reset (RESET#) .................................................... 35

Figure 14. RESET# Timings .......................................................... 35

Autoselect Mode ..................................................................... 14

Table 4. Am29LV160D Autoselect Codes (High Voltage Method) ..14

Word/Byte Configuration (BYTE#) ........................................ 36

Figure 15. BYTE# Timings for Read Operations............................ 36

Figure 16. BYTE# Timings for Write Operations............................ 36

Sector Protection/Unprotection ............................................... 14

Temporary Sector Unprotect .................................................. 15

Figure 1. Temporary Sector Unprotect Operation........................... 15

Figure 2. In-System Sector Protect/Unprotect Algorithms .............. 16

Erase/Program Operations ..................................................... 37

Figure 17. Program Operation Timings..........................................

Figure 18. Chip/Sector Erase Operation Timings ..........................

Figure 19. Data# Polling Timings (During Embedded Algorithms).

Figure 20. Toggle Bit Timings (During Embedded Algorithms)......

Figure 21. DQ2 vs. DQ6 for Erase and

Erase Suspend Operations ............................................................

Figure 22. Temporary Sector Unprotect/Timing Diagram ..............

Figure 23. Sector Protect/Unprotect Timing Diagram ....................

Figure 24. Alternate CE# Controlled Write Operation Timings ......

38

39

40

40

41

41

42

44

Common Flash Memory Interface (CFI) . . . . . . . 17

Table 5. CFI Query Identification String ..........................................17

Table 6. System Interface String .....................................................18

Table 7. Device Geometry Definition ..............................................18

Table 8. Primary Vendor-Specific Extended Query ........................19

Hardware Data Protection ...................................................... 19

Low V

CC

Write Inhibit .............................................................. 19

Write Pulse “Glitch” Protection ............................................... 19

Logical Inhibit .......................................................................... 19

Power-Up Write Inhibit ............................................................ 19

Command Definitions . . . . . . . . . . . . . . . . . . . . . . 20

Reading Array Data ................................................................ 20

Reset Command ..................................................................... 20

Autoselect Command Sequence ............................................ 20

Word/Byte Program Command Sequence ............................. 20

Unlock Bypass Command Sequence ..................................... 21

Figure 3. Program Operation .......................................................... 21

Chip Erase Command Sequence ........................................... 21

Sector Erase Command Sequence ........................................ 22

Erase Suspend/Erase Resume Commands ........................... 22

Figure 4. Erase Operation............................................................... 23

Command Definitions ............................................................. 24

Table 9. Am29LV160D Command Definitions ................................24

Write Operation Status . . . . . . . . . . . . . . . . . . . . . 25

DQ7: Data# Polling ................................................................. 25

Figure 5. Data# Polling Algorithm ................................................... 25

RY/BY#: Ready/Busy# ........................................................... 26

DQ6: Toggle Bit I .................................................................... 26

DQ2: Toggle Bit II ................................................................... 26

Reading Toggle Bits DQ6/DQ2 .............................................. 26

Figure 6. Toggle Bit Algorithm......................................................... 27

Erase and Programming Performance . . . . . . . 45

Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 45

TSOP and SO Pin Capacitance . . . . . . . . . . . . . . 45

Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 46

TS 048—48-Pin Standard TSOP ............................................ 46

TSR048—48-Pin Reverse TSOP ........................................... 47

FBC048—48-Ball Fine-Pitch Ball Grid Array (FBGA)

8 x 9 mm ................................................................................ 48

SO 044—44-Pin Small Outline Package ................................ 49

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 50

Revision A (January 1999) ..................................................... 50

Revision A+1 (April 19, 1999) ................................................. 50

Revision B (November 23, 1999) ............................................ 50

Revision B+1 (February 22, 2000) .......................................... 50

Revision B+2 (November 7, 2000) ......................................... 50

Revision B+3 (November 10, 2000) ....................................... 50

Revision B+4 (April 5, 2004) ................................................... 50

Revision B+5 (June 4, 2004) .................................................. 50

Revision B+6 (October 7, 2004) ............................................. 50

Revision B7 (May 5, 2006) ..................................................... 50

22358B7 May 5, 2006

Am29LV160D

3