L640MH01PI_技术文档

Am29LV640MH/L

Data Sheet

RETIRED

PRODUCT

This product has been retired and is not available for designs. For new and current designs,

S29GL064A supersedes Am29LV640M H/L and is the factory-recommended migration path. Please

refer to the S29GL064A datasheet for specifications and ordering information. Availability of this

document is retained for reference and historical purposes only.

April 2005

The following document specifies Spansion memory products that are now offered by both Advanced

Micro Devices and Fujitsu. Although the document is marked with the name of the company that

originally developed the specification, these products will be offered to customers of both AMD and

Fujitsu.

Continuity of Specifications

There is no change to this datasheet as a result of offering the device as a Spansion product. Any

changes that have been made are the result of normal datasheet improvement and are noted in the

document revision summary, where supported. Future routine revisions will occur when appro-

priate, and changes will be noted in a revision summary.

For More Information

Please contact your local AMD or Fujitsu sales office for additional information about Spansion

memory solutions.

Publication Number 26191 Revision F Amendment +3 Issue Date December 14, 2005

THIS PAGE LEFT INTENTIONALLY BLANK.

Am29LV640MH/L

64 Megabit (4 M x 16-Bit/8 M x 8-Bit) MirrorBit™

3.0 Volt-only Uniform Sector Flash Memory

with VersatileI/O™ Control

This product has been retired and is not available for designs. For new and current designs, S29GL064A supersedes Am29LV640M H/L and is the factory-recommended migration path.

Please refer to the S29GL064A datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only.

DISTINCTIVE CHARACTERISTICS

ARCHITECTURAL ADVANTAGES

— 4-word/8-byte page read buffer

— 16-word/32-byte write buffer

Single power supply operation

— 3 V for read, erase, and program operations

Low power consumption (typical values at 3.0 V, 5

MHz)

VersatileI/O™ control

— 30 mA typical active read current

— 50 mA typical erase/program current

— 1 µA typical standby mode current

— Device generates data output voltages and tolerates

data input voltages on the DQ inputs/outputs as

determined by the voltage on the V_IOpin; operates

from 1.65 to 3.6 V

Package options

Manufactured on 0.23 µm MirrorBit process

technology

— 56-pin TSOP

— 64-ball Fortified BGA

SecSi™ (Secured Silicon) Sector region

SOFTWARE FEATURES

— 128-word/256-byte sector for permanent, secure

identification through an 8-word/16-byte random

Electronic Serial Number, accessible through a

command sequence

— Program Suspend & Resume: read other sectors

before programming operation is completed

— Erase Suspend & Resume: read/program other

sectors before an erase operation is completed

— May be programmed and locked at the factory or by

the customer

— Data# polling & toggle bits provide status

— Unlock Bypass Program command reduces overall

multiple-word programming time

Flexible sector architecture

— One hundred twenty-eight 32 Kword/64-Kbyte sectors

— CFI (Common Flash Interface) compliant: allows host

system to identify and accommodate multiple flash

devices

Compatibility with JEDEC standards

— Provides pinout and software compatibility for

single-power supply flash, and superior inadvertent

write protection

HARDWARE FEATURES

— Sector Group Protection: hardware-level method of

preventing write operations within a sector group

Minimum 100,000 erase cycle guarantee per sector

20-year data retention at 125°C

— Temporary Sector Unprotect: V_ID-level method of

changing code in locked sectors

PERFORMANCE CHARACTERISTICS

— WP#/ACC input:

High performance

Write Protect input (WP#) protects first or last sector

regardless of sector protection settings

ACC (high voltage) accelerates programming time for

higher throughput during system production

— 90 ns access time

— 25 ns page read times

— 0.5 s typical sector erase time

— 22 µs typical effective write buffer word programming

time: 16-word/32-byte write buffer reduces overall

programming time for multiple-word/byte updates

— Hardware reset input (RESET#) resets device

— Ready/Busy# output (RY/BY#) indicates program or

erase cycle completion

Publication# 26191

Issue Date: December 14, 2005

Rev: F Amendment/3

This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data

Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.

Refer to AMD’s Website (www.amd.com) for the latest information.

D A T A S H E E T

GENERAL DESCRIPTION

The Am29LV640MH/L is a 64 Mbit, 3.0 volt single

power supply flash memory device organized as

4,194,304 words or 8,388,608 bytes. The device has

an 8-bit/16-bit bus and can be programmed either in

the host system or in standard EPROM programmers.

the same voltage level that is asserted on the V_IOpin.

Refer to the Ordering Information section for valid V_IO

options.

Hardware data protection measures include a low

V_CCdetector that automatically inhibits write opera-

tions during power transitions. The hardware sector

protection feature disables both program and erase

operations in any combination of sectors of memory.

This can be achieved in-system or via programming

equipment.

An access time of 90, 100, 110, or 120 ns is available.

Note that each access time has a specific operating

voltage range (V_CC) and an I/O voltage range (V_IO), as

specified in the Product Selector Guide and the Order-

ing Information sections. The device is offered in a

56-pin TSOP or 64-ball Fortified BGA package. Each

device has separate chip enable (CE#), write enable

(WE#) and output enable (OE#) controls.

The Erase Suspend/Erase Resume feature allows

the host system to pause an erase operation in a given

sector to read or program any other sector and then

complete the erase operation. The Program Sus-

pend/Program Resume feature enables the host sys-

tem to pause a program operation in a given sector to

read any other sector and then complete the program

operation.

Each device requires only a single 3.0 volt power

supply for both read and write functions. In addition to

a V_CCinput, a high-voltage accelerated program

(ACC) feature provides shorter programming times

through increased current on the WP#/ACC input. This

feature is intended to facilitate factory throughput dur-

ing system production, but may also be used in the

field if desired.

The hardware RESET# pin terminates any operation

in progress and resets the device, after which it is then

ready for a new operation. The RESET# pin may be

tied to the system reset circuitry. A system reset would

thus also reset the device, enabling the host system to

read boot-up firmware from the Flash memory device.

The device is entirely command set compatible with

the JEDEC single-power-supply Flash standard.

Commands are written to the device using standard

microprocessor write timing. Write cycles also inter-

nally latch addresses and data needed for the pro-

gramming and erase operations.

The device reduces power consumption in the

standby mode when it detects specific voltage levels

on CE# and RESET#, or when addresses have been

stable for a specified period of time.

The sector erase architecture allows memory sec-

tors to be erased and reprogrammed without affecting

the data contents of other sectors. The device is fully

erased when shipped from the factory.

The Write Protect (WP#) feature protects the first or

last sector by asserting a logic low on the WP#/ACC

pin. The protected sector will still be protected even

during accelerated programming.

Device programming and erasure are initiated through

command sequences. Once a program or erase oper-

ation has begun, the host system need only poll the

DQ7 (Data# Polling) or DQ6 (toggle) status bits or

monitor the Ready/Busy# (RY/BY#) output to deter-

mine whether the operation is complete. To facilitate

programming, an Unlock Bypass mode reduces com-

mand sequence overhead by requiring only two write

cycles to program data instead of four.

The SecSi™ (Secured Silicon) Sector provides a

128-word/256-byte area for code or data that can be

permanently protected. Once this sector is protected,

no further changes within the sector can occur.

Spansion MirrorBit flash technology combines years of

Flash memory manufacturing experience to produce

the highest levels of quality, reliability and cost effec-

tiveness. The device electrically erases all bits within a

sector simultaneously via hot-hole assisted erase. The

data is programmed using hot electron injection.

The VersatileI/O™ (V_IO) control allows the host sys-

tem to set the voltage levels that the device generates

and tolerates on the CE# control input and DQ I/Os to

2

Am29LV640MH/L

December 14, 2005

D A T A S H E E T

MIRRORBIT 64 MBIT DEVICE FAMILY

Device

Bus

Sector Architecture

Packages

V_IO

RY/BY#

WP#, ACC

WP# Protection

48-pin TSOP (std. & rev. pinout),

63-ball FBGA

LV065MU

x8

Uniform (64 Kbyte)

Yes

ACC only

No WP#

Boot (8 x 8 Kbyte

at top & bottom)

48-pin TSOP, 63-ball Fine-pitch BGA,

64-ball Fortified BGA

2 x 8 Kbyte

top or bottom

LV640MT/B

LV640MH/L

LV641MH/L

LV640MU

x8/x16

x16

No

Yes

No

WP#/ACC pin

56-pin TSOP (std. & rev. pinout),

64-ball Fortified BGA

1 x 64 Kbyte

high or low

Uniform (64 Kbyte)

Uniform (32 Kword)

Separate WP#

and ACC pins

1 x 32 Kword

top or bottom

48-pin TSOP (std. & rev. pinout)

64-ball Fortified BGA,

64-Ball Fine-Pitch BGA

x16

Yes

ACC only

No WP#

Related Documents

To download related documents, click on the following

links or go to www.amd.com→Flash Memory→Prod-

uct Information→MirrorBit→Flash Information→Tech-

nical Documentation.

Implementing a Common Layout for AMD MirrorBit

and Intel StrataFlash Memory Devices

Migrating from Single-byte to Three-byte Device IDs

AMD MirrorBit™ White Paper

MirrorBit™ Flash Memory Write Buffer Programming

and Page Buffer Read

December 14, 2005

Am29LV640MH/L

3

D A T A S H E E T

TABLE OF CONTENTS

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 6

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 10

Table 1. Device Bus Operations .....................................................10

Word/Byte Configuration ........................................................ 11

VersatileIO™ (V_IO) Control ..................................................... 11

Requirements for Reading Array Data ................................... 11

Page Mode Read .................................................................... 11

Writing Commands/Command Sequences ............................ 11

Write Buffer ............................................................................. 11

Accelerated Program Operation ............................................. 11

Autoselect Functions .............................................................. 12

Standby Mode ........................................................................ 12

Automatic Sleep Mode ........................................................... 12

RESET#: Hardware Reset Pin ............................................... 12

Output Disable Mode .............................................................. 12

Autoselect Mode ..................................................................... 16

Table 2. Autoselect Codes, (High Voltage Method) .......................16

Sector Group Protection and Unprotection ............................. 16

Table 3. Sector Group Protection/Unprotection Address Table ......16

Write Protect (WP#) ................................................................ 18

Temporary Sector Group Unprotect ....................................... 18

Figure 1. Temporary Sector Group Unprotect Operation................ 18

Figure 2. In-System Sector Group

Erase Suspend/Erase Resume Commands ........................... 32

Command Definitions ............................................................. 33

Command Definitions (x16 Mode, BYTE# = V_IH) ............................ 33

Command Definitions (x8 Mode, BYTE# = V_IL)............................... 34

Write Operation Status . . . . . . . . . . . . . . . . . . . . 35

DQ7: Data# Polling ................................................................. 35

Figure 8. Data# Polling Algorithm .................................................. 36

RY/BY#: Ready/Busy# ............................................................ 37

DQ6: Toggle Bit I .................................................................... 37

Figure 9. Toggle Bit Algorithm........................................................ 38

DQ2: Toggle Bit II ................................................................... 38

Reading Toggle Bits DQ6/DQ2 ............................................... 39

DQ5: Exceeded Timing Limits ................................................ 39

DQ3: Sector Erase Timer ....................................................... 39

DQ1: Write-to-Buffer Abort ..................................................... 39

Table 10. Write Operation Status ................................................... 40

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 41

Figure 10. Maximum Negative Overshoot Waveform .................... 41

Figure 11. Maximum Positive

Overshoot Waveform ..................................................................... 41

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 41

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 42

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 12. Test Setup..................................................................... 43

Table 1. Test Specifications ........................................................... 43

Key to Switching Waveforms. . . . . . . . . . . . . . . . 43

Figure 13. Input Waveforms and

Measurement Levels...................................................................... 43

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 44

Read-Only Operations ........................................................... 44

Figure 14. Read Operation Timings............................................... 44

Figure 15. Page Read Timings ...................................................... 45

Hardware Reset (RESET#) .................................................... 46

Figure 16. Reset Timings............................................................... 46

Erase and Program Operations .............................................. 47

Figure 17. Program Operation Timings.......................................... 48

Figure 18. Accelerated Program Timing Diagram.......................... 48

Figure 19. Chip/Sector Erase Operation Timings .......................... 49

Figure 20. Data# Polling Timings

Protect/Unprotect Algorithms .......................................................... 19

SecSi (Secured Silicon) Sector Flash Memory Region .......... 20

Figure 3. SecSi Sector Protect Verify.............................................. 21

Hardware Data Protection ...................................................... 21

Low VCC Write Inhibit ............................................................ 21

Write Pulse “Glitch” Protection ............................................... 21

Logical Inhibit .......................................................................... 21

Power-Up Write Inhibit ............................................................ 21

Common Flash Memory Interface (CFI) . . . . . . . 21

CFI Query Identification String........................................................ 22

System Interface String................................................................... 22

Table 6. Device Geometry Definition .............................................. 23

Table 7. Primary Vendor-Specific Extended Query ........................ 24

Command Definitions . . . . . . . . . . . . . . . . . . . . . 24

Reading Array Data ................................................................ 24

Reset Command ..................................................................... 25

Autoselect Command Sequence ............................................ 25

Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 25

Word/Byte Program Command Sequence ............................. 25

Unlock Bypass Command Sequence ..................................... 26

Write Buffer Programming ...................................................... 26

Accelerated Program .............................................................. 27

Figure 4. Write Buffer Programming Operation............................... 28

Figure 5. Program Operation .......................................................... 29

Program Suspend/Program Resume Command Sequence ... 29

Figure 6. Program Suspend/Program Resume............................... 30

Chip Erase Command Sequence ........................................... 30

Sector Erase Command Sequence ........................................ 30

Figure 7. Erase Operation............................................................... 31

(During Embedded Algorithms)...................................................... 50

Figure 21. Toggle Bit Timings (During Embedded Algorithms)...... 51

Figure 22. DQ2 vs. DQ6................................................................. 51

Temporary Sector Unprotect .................................................. 52

Figure 23. Temporary Sector Group Unprotect Timing Diagram ... 52

Figure 24. Sector Group Protect and Unprotect Timing Diagram .. 53

Alternate CE# Controlled Erase and Program Operations ..... 54

Figure 25. Alternate CE# Controlled Write (Erase/Program)

Operation Timings.......................................................................... 55

Erase And Programming Performance . . . . . . . 56

Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 56

TSOP Pin and BGA Package Capacitance . . . . . 56

Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 57

TS056/TSR056—56-Pin Standard and Reverse Pinout

Thin Small Outline Package (TSOP) ...................................... 57

LAA064—64-Ball Fortified Ball Grid Array (FBGA) 13 x 11 mm

Package .................................................................................. 58

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 59

4

Am29LV640MH/L

December 14, 2005

D A T A S H E E T

PRODUCT SELECTOR GUIDE

Part Number

Am29LV640MH/L

112R

(V_IO= 1.65–

3.6 V)

90R

(V_IO= 3.0–

3.6 V)

101R

(V_IO= 2.7–

3.6 V)

120R

(V_IO= 1.65

–3.6 V)

V_CC= 3.0–3.6 V

Speed

Option

101

112

120

(V_IO= 1.65–

3.6 V)

V_CC= 2.7–3.6 V

(V_IO= 2.7–

3.6 V)

(V_IO= 1.65

–3.6 V)

Max. Access Time (ns)

Max. CE# Access Time (ns)

Max. Page access time

90

100

110

120

25

30

40

30

40

(t_PACC

)

Max. OE# Access Time (ns)

Notes:

1. See “AC Characteristics” for full specifications.

2. For the Am29LV640MH-L device, the last numeric digit in the

speed option (e.g. 101, 112, 120) is used for internal

purposes only. Please use OPNs as listed on p. 9 when

placing orders.

BLOCK DIAGRAM

DQ0–DQ15 (A-1)

RY/BY#

V_CC

V_SS

Sector Switches

V_IO

Erase Voltage

Generator

Input/Output

Buffers

RESET#

WE#

WP#/ACC

BYTE#

State

Control

Command

Register

PGM Voltage

Generator

Data

Latch

Chip Enable

Output Enable

Logic

STB

CE#

OE#

Y-Decoder

X-Decoder

Y-Gating

STB

V_CCDetector

Timer

Cell Matrix

A21–A0

December 14, 2005 26191F3

Am29LV640MH/L

5

D A T A S H E E T

CONNECTION DIAGRAMS

NC

1

2

56 NC

55 NC

A15

A14

A13

A12

A11

A10

A9

3

54 A16

53 BYTE#

V_SS

52

51 DQ15/A-1

50 DQ7

4

5

6

7

8

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

V_CC

9

56-Pin Standard TSOP

A8

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

A19

A20

WE#

RESET#

A21

WP#/ACC

RY/BY#

A18

A17

A7

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

A6

A5

A4

OE#

V_SS

A3

A2

CE#

A0

A1

NC 27

NC 28

30 NC

29 V_IO

NC

1

2

3

4

5

6

7

8

9

56 NC

55 NC

A16

54 A15

53 A14

52 A13

51 A12

50 A11

49 A10

48 A9

BYTE#

V_SS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13 10

DQ5 11

DQ12 12

DQ4 13

V_CC14

DQ11 15

DQ3 16

DQ10 17

DQ2 18

DQ9 19

DQ1 20

DQ8 21

DQ0 22

OE# 23

V_SS24

47 A8

56-Pin Reverse TSOP

46 A19

45 A20

44 WE#

43 RESET#

42 A21

41 WP#/ACC

40 RY/BY#

39 A18

38 A17

37 A7

36 A6

35 A5

34 A4

33 A3

CE# 25

A0 26

32 A2

31 A1

NC 27

30 NC

V_IO28

29 NC

6

Am29LV640MH/L

26191F3 December 14, 2005

D A T A S H E E T

CONNECTION DIAGRAMS

64-Ball Fortified BGA

Top View, Balls Facing Down

A8

B8

C8

D8

E8

F8

G8

NC

H8

NC

V_IO

V_SS

NC

A7

B7

C7

D7

E7

F7

G7

H7

A13

A12

A14

A15

A16

BYTE# DQ15/A-1 V_SS

A6

A9

B6

A8

C6

D6

E6

F6

G6

H6

DQ6

A10

A11

DQ7

DQ14

DQ13

A5

B5

C5

D5

E5

F5

G5

H5

WE# RESET#

A21

A19

DQ5

DQ12

V_CC

DQ4

A4 B4

C4

D4

E4

F4

G4

H4

RY/BY# WP#/ACC A18

A20

DQ2

DQ10

DQ11

DQ3

A3

A7

B3

C3

A6

D3

A5

E3

F3

G3

H3

A17

DQ0

DQ8

DQ9

DQ1

A2

A3

B2

A4

C2

A2

D2

A1

E2

A0

F2

G2

H2

CE#

OE#

V_SS

A1

B1

C1

D1

E1

F1

G1

NC

H1

NC

V_IO

NC

age and/or data integrity may be compromised if the

package body is exposed to temperatures above 150°C

for prolonged periods of time.

Special Package Handling Instructions

Special handling is required for Flash Memory prod-

ucts in molded packages (TSOP and BGA). The pack-

December 14, 2005

Am29LV640MH/L

7

D A T A S H E E T

RESET#

RY/BY#

BYTE#

= Hardware Reset Pin input

= Ready/Busy output

PIN DESCRIPTION

A21–A0

= 22 Address inputs

DQ14–DQ0 = 15 Data inputs/outputs

= Selects 8-bit or 16-bit mode

DQ15/A-1

= DQ15 (Data input/output, word mode),

V_CC

= 3.0 volt-only single power supply

(see Product Selector Guide for

speed options and voltage

supply tolerances)

A-1 (LSB Address input, byte mode)

CE#

OE#

WE#

= Chip Enable input

= Output Enable input

= Write Enable input

V_IO

V_SS

NC

= Output Buffer power

= Device Ground

WP#/ACC = Hardware Write Protect input/Pro-

gramming Acceleration input

= Pin Not Connected Internally

Logic Symbol

22

A21–A0

16 or 8

DQ15–DQ0

(A-1)

CE#

OE#

WE#

WP#/ACC

RESET#

V_IO

RY/BY#

BYTE#

8

Am29LV640MH/L

December 14, 2005

D A T A S H E E T

ORDERING INFORMATION

Standard Products

Standard products are available in several packages and operating ranges. The order

number (Valid Combination) is formed by a combination of the following:

Am29LV640M

H

120R

PC

I

TEMPERATURE RANGE

Industrial (–40°C to +85°C)

I

=

PACKAGE TYPE

E

=

56-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 056)

56-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR056)

F

PC

64-Ball Fortified Ball Grid Array,

1.0 mm pitch, 13 x 11 mm package (LAA064)

SPEED OPTION

See Product Selector Guide and Valid Combinations

SECTOR ARCHITECTURE AND WP# PROTECTION (WP# = V_IL)

H

L

=

Uniform sector device, highest address sector protected

Uniform sector device, lowest address sector protected

DEVICE NUMBER/DESCRIPTION

Am29LV640MH/L

64 Megabit (4 M x 16-Bit/8 M x 8-Bit) MirrorBit™ Uniform Sector Flash Memory

with VersatileIO™ Control, 3.0 Volt-only Read, Program, and Erase

Valid Combinations for

TSOP Package (Note 2)

Speed

(ns)

V_IO

V_CC

Valid Combinations for

Fortified BGA Package (Note 2)

V_IO

V_CC

Range (V) Range (V)

Speed

(ns)

Range Range

(V)

Am29LV640MH90R

Am29LV640ML90R

Package

Order Number

(V)

90

3.0–3.6

1.65–3.6

2.7–3.6

3.0–3.6

2.7–3.6

Marking

Am29LV640MH112

Am29LV640ML112

Am29LV640MH90R

Am29LV640ML90R

L640MH90NI

L640ML90NI

3.0–

3.6

3.0–

3.6

110

120

100

110

120

90

Am29LV640MH120

Am29LV640MH101

Am29LV640ML101

L640MH01PI

L640ML01PI

2.7–

3.6

100

110

120

100

110

120

Am29LV640ML120

EI,

FI

Am29LV640MH101R

Am29LV640ML101R

Am29LV640MH112

Am29LV640ML112

L640MH11PI

L640ML11PI

1.65–

3.6

2.7–

3.6

Am29LV640MH112R

Am29LV640ML112R

Am29LV640MH120

Am29LV640ML120

L640MH12PI

L640ML12PI

1.65–

3.6

1.65–3.6

3.0–3.6

PCI

Am29LV640MH120R

Am29LV640ML120R

Am29LV640MH101R

Am29LV640ML101R

L640MH01NI

L640ML01NI

2.7–

3.

Am29LV640MH112R

Am29LV640ML112R

L640MH11NI

L640ML11NI

1.65–

3.6

3.0–

3.6

Am29LV640MH120R

Am29LV640ML120R

L640MH12NI

L640ML12NI

1.65–

3.6

Valid Combinations

Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to

confirm availability of specific valid combinations and to check on newly released combinations.

Notes:

1. For the Am29LV640MH-L device, the last numeric digit in the speed

modify the speed option indicator as follows [101R = 10R, 112R =

11R, 120R = 12R, 90R, 101, 112, 120 = no change] Example:

Am29LV640MH12RPCIN. For Fortified BGA packages, the

designator “N” will also appear at the end of the package marking.

Example: L640MH12NIN.

option (e.g. 101, 112, 120) is used for internal purposes only.

2. To select product with ESN factory-locked into the SecSi Sector:

1) select order number from the valid combinations given above,

2) add designator “N” at the end of the order number, and 3)

December 14, 2005

Am29LV640MH/L

9

D A T A S H E E T

DEVICE BUS OPERATIONS

This section describes the requirements and use of

the device bus operations, which are initiated through

the internal command register. The command register

itself does not occupy any addressable memory loca-

tion. The register is a latch used to store the com-

mands, along with the address and data information

needed to execute the command. The contents of the

register serve as inputs to the internal state machine.

The state machine outputs dictate the function of the

device. Table 1 lists the device bus operations, the in-

puts and control levels they require, and the resulting

output. The following subsections describe each of

these operations in further detail.

Table 1. Device Bus Operations

DQ8–DQ15

Addresses

(Note 2)

DQ0–

DQ7

BYTE#

= V_IH

BYTE#

= V_IL

Operation

CE# OE# WE# RESET#

WP#

X

ACC

X

Read

L

H

L

H

A_IN

D_OUT

DQ8–DQ14

= High-Z,

DQ15 = A-1

Write (Program/Erase)

Accelerated Program

(Note 3)

X

(Note 4) (Note 4)

L

H

V_HH

V_CC

0.3 V

±

V_CC±

0.3 V

Standby

X

H

X

High-Z High-Z

High-Z

Output Disable

Reset

L

H

X

H

X

H

L

X

High-Z High-Z

High-Z

X

SA, A6 =L,

A3=L, A2=L, (Note 4)

A1=H, A0=L

Sector Group Protect

(Note 2)

L

H

L

V_ID

H

X

SA, A6=H,

A3=L, A2=L, (Note 4)

A1=H, A0=L

Sector Group Unprotect

(Note 2)

L

H

X

L

V_ID

H

X

Temporary Sector

Group Unprotect

X

A_IN

(Note 4) (Note 4)

High-Z

Legend: L = Logic Low = V_IL, H = Logic High = V_IH, V_ID= 11.5–12.5 V, V_HH= 11.5–12.5 V, X = Don’t Care, SA = Sector Address,

A_IN= Address In, D_IN= Data In, D_OUT= Data Out

Notes:

1. Addresses are A21:A0 in word mode; A21:A-1 in byte

mode. Sector addresses are A21:A15 in both modes.

unprotected as determined by the method described in

“Sector Group Protection and Unprotection”. All sectors are

unprotected when shipped from the factory (The SecSi

Sector may be factory protected depending on version

ordered.)

2. The sector protect and sector unprotect functions may also

be implemented via programming equipment. See the

“Sector Group Protection and Unprotection” section.

4. D_INor D_OUTas required by command sequence, data

polling, or sector protect algorithm (see Figure 2).

3. If WP# = V_IL, the first or last sector remains protected. If

WP# = V_IH, the first or last sector will be protected or

10

Am29LV640MH/L

December 14, 2005

D A T A S H E E T

asynchronous operation; the microprocessor supplies

Word/Byte Configuration

the specific word location.

The BYTE# pin controls whether the device data I/O

pins operate in the byte or word configuration. If the

BYTE# pin is set at logic ‘1’, the device is in word con-

figuration, DQ0–DQ15 are active and controlled by

CE# and OE#.

The random or initial page access is equal to t_ACCor

t_CEand subsequent page read accesses (as long as

the locations specified by the microprocessor falls

within that page) is equivalent to t_PACC. When CE# is

deasserted and reasserted for a subsequent access,

the access time is t_ACCor t_CE. Fast page mode ac-

cesses are obtained by keeping the “read-page ad-

dresses” constant and changing the “intra-read page”

addresses.

If the BYTE# pin is set at logic ‘0’, the device is in byte

configuration, and only data I/O pins DQ0–DQ7 are

active and controlled by CE# and OE#. The data I/O

pins DQ8–DQ14 are tri-stated, and the DQ15 pin is

used as an input for the LSB (A-1) address function.

Writing Commands/Command Sequences

VersatileIO™ (V_IO) Control

To write a command or command sequence (which in-

cludes programming data to the device and erasing

sectors of memory), the system must drive WE# and

CE# to V_IL, and OE# to V_IH.

The VersatileIO™ (V_IO) control allows the host system

to set the voltage levels that the device generates and

tolerates on CE# and DQ I/Os to the same voltage

level that is asserted on V_IO. See “Ordering Informa-

tion” on page 9 for V_IOoptions on this device.

The device features an Unlock Bypass mode to facili-

tate faster programming. Once the device enters the

Unlock Bypass mode, only two write cycles are re-

quired to program a word or byte, instead of four. The

“Word/Byte Program Command Sequence” section

has details on programming data to the device using

both standard and Unlock Bypass command se-

quences.

For example, a V_I/Oof 1.65–3.6 volts allows for I/O at

the 1.8 or 3 volt levels, driving and receiving signals to

and from other 1.8 or 3 V devices on the same data

bus.

Requirements for Reading Array Data

To read array data from the outputs, the system must

drive the CE# and OE# pins to V_IL. CE# is the power

control and selects the device. OE# is the output con-

trol and gates array data to the output pins. WE#

should remain at V_IH.

An erase operation can erase one sector, multiple sec-

tors, or the entire device. Table 2 indicates the address

space that each sector occupies.

Refer to the DC Characteristics table for the active

current specification for the write mode. The AC Char-

acteristics section contains timing specification tables

and timing diagrams for write operations.

The internal state machine is set for reading array data

upon device power-up, or after a hardware reset. This

ensures that no spurious alteration of the memory

content occurs during the power transition. No com-

mand is necessary in this mode to obtain array data.

Standard microprocessor read cycles that assert valid

addresses on the device address inputs produce valid

data on the device data outputs. The device remains

enabled for read access until the command register

contents are altered.

Write Buffer

Write Buffer Programming allows the system to write a

maximum of 16 words/32 bytes in one programming

operation. This results in faster effective programming

time than the standard programming algorithms. See

“Write Buffer” for more information.

See “Reading Array Data” for more information. Refer

to the AC Read-Only Operations table for timing speci-

fications and to Figure 14 for the timing diagram. Refer

to the DC Characteristics table for the active current

specification on reading array data.

Accelerated Program Operation

The device offers accelerated program operations

through the ACC function. This is one of two functions

provided by the WP#/ACC pin. This function is prima-

rily intended to allow faster manufacturing throughput

at the factory.

Page Mode Read

If the system asserts V_HHon this pin, the device auto-

matically enters the aforementioned Unlock Bypass

mode, temporarily unprotects any protected sectors,

and uses the higher voltage on the pin to reduce the

time required for program operations. The system

would use a two-cycle program command sequence

as required by the Unlock Bypass mode. Removing

V_HHfrom the WP#/ACC pin returns the device to nor-

mal operation. Note that the WP#/ACC pin must not be

The device is capable of fast page mode read and is

compatible with the page mode Mask ROM read oper-

ation. This mode provides faster read access speed

for random locations within a page. The page size of

the device is 4 words/8 bytes. The appropriate page is

selected by the higher address bits A(max)–A2. Ad-

dress bits A1–A0 in word mode (A1–A-1 in byte mode)

determine the specific word within a page. This is an

December 14, 2005

Am29LV640MH/L

11

D A T A S H E E T

at V_HHfor operations other than accelerated program- this mode when addresses remain stable for t_ACC

+

ming, or device damage may result. In addition, no ex-

ternal pullup is necessary since the WP#/ACC pin has

internal pullup to V_CC.

30 ns. The automatic sleep mode is independent of

the CE#, WE#, and OE# control signals. Standard ad-

dress access timings provide new data when ad-

dresses are changed. While in sleep mode, output

data is latched and always available to the system.

Refer to the DC Characteristics table for the automatic

sleep mode current specification.

Autoselect Functions

If the system writes the autoselect command se-

quence, the device enters the autoselect mode. The

system can then read autoselect codes from the inter-

nal register (which is separate from the memory array)

on DQ7–DQ0. Standard read cycle timings apply in

this mode. Refer to the Autoselect Mode and Autose-

lect Command Sequence sections for more informa-

tion.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of re-

setting the device to reading array data. When the RE-

SET# pin is driven low for at least a period of t_RP, the

device immediately terminates any operation in

progress, tristates all output pins, and ignores all

read/write commands for the duration of the RESET#

pulse. The device also resets the internal state ma-

chine to reading array data. The operation that was in-

terrupted should be reinitiated once the device is

ready to accept another command sequence, to en-

sure data integrity.

Standby Mode

When the system is not reading or writing to the de-

vice, it can place the device in the standby mode. In

this mode, current consumption is greatly reduced,

and the outputs are placed in the high impedance

state, independent of the OE# input.

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at V_SS0.3 V, the device

draws CMOS standby current (I_CC4). If RESET# is held

at V_ILbut not within V_SS0.3 V, the standby current will

be greater.

The device enters the CMOS standby mode when the

CE# and RESET# pins are both held at V_IO0.3 V.

(Note that this is a more restricted voltage range than

V_IH.) If CE# and RESET# are held at V_IH, but not within

V_IO0.3 V, the device will be in the standby mode, but

the standby current will be greater. The device re-

quires standard access time (t_CE) for read access

when the device is in either of these standby modes,

before it is ready to read data.

The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash

memory, enabling the system to read the boot-up firm-

ware from the Flash memory.

If the device is deselected during erasure or program-

ming, the device draws active current until the

operation is completed.

Refer to the AC Characteristics tables for RESET# pa-

rameters and to Figure 16 for the timing diagram.

Output Disable Mode

When the OE# input is at V_IH, output from the device is

disabled. The output pins are placed in the high

impedance state.

Refer to the DC Characteristics table for the standby

current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device en-

ergy consumption. The device automatically enables

12

Am29LV640MH/L

December 14, 2005

D A T A S H E E T

8-bit

16-bit

Sector Size

Address Range

(in hexadecimal)

Address Range

(in hexadecimal)

Sector

SA0

A21–A15

(Kbytes/Kwords)

64/32

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

000000–00FFFF

010000–01FFFF

020000–02FFFF

030000–03FFFF

040000–04FFFF

050000–05FFFF

060000–06FFFF

070000–07FFFF

080000–08FFFF

090000–09FFFF

0A0000–0AFFFF

0B0000–0BFFFF

0C0000–0CFFFF

0D0000–0DFFFF

0E0000–0EFFFF

0F0000–0FFFFF

100000–10FFFF

110000–11FFFF

120000–12FFFF

130000–13FFFF

140000–14FFFF

150000–15FFFF

160000–16FFFF

170000–17FFFF

180000–18FFFF

190000–19FFFF

1A0000–1AFFFF

1B0000–1BFFFF

1C0000–1CFFFF

1D0000–1DFFFF

1E0000–1EFFFF

1F0000–1FFFFF

200000–20FFFF

210000–21FFFF

220000–22FFFF

230000–23FFFF

240000–24FFFF

250000–25FFFF

260000–26FFFF

270000–27FFFF

280000–28FFFF

290000–29FFFF

2A0000–2AFFFF

2B0000–2BFFFF

2C0000–2CFFFF

2D0000–2DFFFF

2E0000–2EFFFF

2F0000–2FFFFF

300000–30FFFF

310000–31FFFF

320000–32FFFF

330000–33FFFF

340000–34FFFF

350000–35FFFF

360000–36FFFF

370000–37FFFF

000000–007FFF

008000–00FFFF

010000–017FFF

018000–01FFFF

020000–027FFF

028000–02FFFF

030000–037FFF

038000–03FFFF

040000–047FFF

048000–04FFFF

050000–057FFF

058000–05FFFF

060000–067FFF

068000–06FFFF

070000–077FFF

078000–07FFFF

080000–087FFF

088000–08FFFF

090000–097FFF

098000–09FFFF

0A0000–0A7FFF

0A8000–0AFFFF

0B0000–0B7FFF

0B8000–0BFFFF

0C0000–0C7FFF

0C8000–0CFFFF

0D0000–0D7FFF

0D8000–0DFFFF

0E0000–0E7FFF

0E8000–0EFFFF

0F0000–0F7FFF

0F8000–0FFFFF

100000–107FFF

108000–10FFFF

110000–117FFF

118000–11FFFF

120000–127FFF

128000–12FFFF

130000–137FFF

138000–13FFFF

140000–147FFF

148000–14FFFF

150000–157FFF

158000–15FFFF

160000–167FFF

168000–16FFFF

170000–177FFF

178000–17FFFF

180000–187FFF

188000–18FFFF

190000–197FFF

198000–19FFFF

1A0000–1A7FFF

1A8000–1AFFFF

1B0000–1B7FFF

1B8000–1BFFFF

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

December 14, 2005

Am29LV640MH/L

13

D A T A S H E E T

8-bit

16-bit

Sector Size

Address Range

(in hexadecimal)

Address Range

(in hexadecimal)

Sector

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

SA71

SA72

SA73

SA74

SA75

SA76

SA77

SA78

SA79

SA80

SA81

SA82

SA83

SA84

SA85

SA86

SA87

SA88

SA89

SA90

SA91

SA92

SA93

SA94

SA95

SA96

SA97

SA98

SA99

SA100

SA101

SA102

SA103

SA104

SA105

SA106

SA107

SA108

SA109

SA110

SA111

A21–A15

(Kbytes/Kwords)

64/32

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

380000–38FFFF

390000–39FFFF

3A0000–3AFFFF

3B0000–3BFFFF

3C0000–3CFFFF

3D0000–3DFFFF

3E0000–3EFFFF

3F0000–3FFFFF

400000–40FFFF

410000–41FFFF

420000–42FFFF

430000–43FFFF

440000–44FFFF

450000–45FFFF

460000–46FFFF

470000–47FFFF

480000–48FFFF

490000–49FFFF

4A0000–4AFFFF

4B0000–4BFFFF

4C0000–4CFFFF

4D0000–4DFFFF

4E0000–4EFFFF

4F0000–4FFFFF

500000–50FFFF

510000–51FFFF

520000–52FFFF

530000–53FFFF

540000–54FFFF

550000–55FFFF

560000–56FFFF

570000–57FFFF

580000–58FFFF

590000–59FFFF

5A0000–5AFFFF

5B0000–5BFFFF

5C0000–5CFFFF

5D0000–5DFFFF

5E0000–5EFFFF

5F0000–5FFFFF

600000–60FFFF

610000–61FFFF

620000–62FFFF

630000–63FFFF

640000–64FFFF

650000–65FFFF

660000–66FFFF

670000–67FFFF

680000–68FFFF

690000–69FFFF

6A0000–6AFFFF

6B0000–6BFFFF

6C0000–6CFFFF

6D0000–6DFFFF

6E0000–6EFFFF

6F0000–6FFFFF

1C0000–1C7FFF

1C8000–1CFFFF

1D0000–1D7FFF

1D8000–1DFFFF

1E0000–1E7FFF

1E8000–1EFFFF

1F0000–1F7FFF

1F8000–1FFFFF

200000–207FFF

208000–20FFFF

210000–217FFF

218000–21FFFF

220000–227FFF

228000–22FFFF

230000–237FFF

238000–23FFFF

240000–247FFF

248000–24FFFF

250000–257FFF

258000–25FFFF

260000–267FFF

268000–26FFFF

270000–277FFF

278000–27FFFF

280000–287FFF

288000–28FFFF

290000–297FFF

298000–29FFFF

2A0000–2A7FFF

2A8000–2AFFFF

2B0000–2B7FFF

2B8000–2BFFFF

2C0000–2C7FFF

2C8000–2CFFFF

2D0000–2D7FFF

2D8000–2DFFFF

2E0000–2E7FFF

2E8000–2EFFFF

2F0000–2F7FFF

2F8000–2FFFFF

300000–307FFF

308000–30FFFF

310000–317FFF

318000–31FFFF

320000–327FFF

328000–32FFFF

330000–337FFF

338000–33FFFF

340000–347FFF

348000–34FFFF

350000–357FFF

358000–35FFFF

360000–367FFF

368000–36FFFF

370000–377FFF

378000–37FFFF

14

Am29LV640MH/L

December 14, 2005

D A T A S H E E T

8-bit

16-bit

Sector Size

(Kbytes/Kwords)

Address Range

(in hexadecimal)

Address Range

(in hexadecimal)

Sector

SA112

SA113

SA114

SA115

SA116

SA117

SA118

SA119

SA120

SA121

SA122

SA123

SA124

SA125

SA126

SA127

A21–A15

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

64/32

700000–70FFFF

710000–71FFFF

720000–72FFFF

730000–73FFFF

740000–74FFFF

750000–75FFFF

760000–76FFFF

770000–77FFFF

780000–78FFFF

790000–79FFFF

7A0000–7AFFFF

7B0000–7BFFFF

7C0000–7CFFFF

7D0000–7DFFFF

7E0000–7EFFFF

7F0000–7FFFFF

380000–387FFF

388000–38FFFF

390000–397FFF

398000–39FFFF

3A0000–3A7FFF

3A8000–3AFFFF

3B0000–3B7FFF

3B8000–3BFFFF

3C0000–3C7FFF

3C8000–3CFFFF

3D0000–3D7FFF

3D8000–3DFFFF

3E0000–3E7FFF

3E8000–3EFFFF

3F0000–3F7FFF

3F8000–3FFFFF

64/32

Note: The address range is A21:A-1 in byte mode (BYTE# = V_IL) or A21:A0 in word mode (BYTE# = V_IH).

December 14, 2005

Am29LV640MH/L

15

D A T A S H E E T

In addition, when verifying sector protection, the sector

Autoselect Mode

address must appear on the appropriate highest order

address bits (see Table 2). Table 3 shows the remain-

ing address bits that are don’t care. When all neces-

sary bits have been set as required, the programming

equipment may then read the corresponding identifier

code on DQ7–DQ0.

The autoselect mode provides manufacturer and de-

vice identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This

mode is primarily intended for programming equip-

ment to automatically match a device to be pro-

grammed with its corresponding programming

algorithm. However, the autoselect codes can also be

accessed in-system through the command register.

To access the autoselect codes in-system, the host

system can issue the autoselect command via the

command register, as shown in Tables 10 and 11. This

method does not require V_ID. Refer to the Autoselect

Command Sequence section for more information.

When using programming equipment, the autoselect

mode requires V_IDon address pin A9. Address pins

A6, A3, A2, A1, and A0 must be as shown in Table 3.

Table 2. Autoselect Codes, (High Voltage Method)

DQ8 to DQ15

A21 A14

A8

A9 to A6

A7

A5 A3

to to

A4 A2

Description

CE# OE# WE# to

to

A1 A0

DQ7 to DQ0

BYTE#= BYTE# =

A15 A10

V_IH

00

22

V_IL

V_ID

Manufacturer ID: AMD

Cycle 1

L

H

X

L

X

L

H

L

X

01h

7Eh

0Ch

X

Cycle 2

H

X

V_ID

X

L

X

Cycle 3

H

22

X

01h

Sector Protection

Verification

01h (protected),

00h (unprotected)

V_ID

L

H

SA

X

L

X

L

H

L

X

SecSi Sector Indicator

Bit (DQ7), WP# protects

highest address sector

98h (factory locked),

18h (not factory locked)

L

H

X

SecSi Sector Indicator

Bit (DQ7), WP# protects

lowest address sector

88h (factory locked),

08h (not factory locked)

V_ID

L

H

X

L

X

Legend: L = Logic Low = V_IL, H = Logic High = V_IH, SA = Sector Address, X = Don’t care.

the algorithms and Figure 24 shows the timing dia-

gram. This method uses standard microprocessor bus

cycle timing. For sector group unprotect, all unpro-

tected sector groups must first be protected prior to

the first sector group unprotect write cycle.

Sector Group Protection and

Unprotection

The hardware sector group protection feature disables

both program and erase operations in any sector

group. In this device, a sector group consists of four

adjacent sectors that are protected or unprotected at

the same time (see Table 4). The hardware sector

group unprotection feature re-enables both program

and erase operations in previously protected sector

groups. Sector group protection/unprotection can be

implemented via two methods.

The device is shipped with all sector groups unpro-

tected. AMD offers the option of programming and pro-

tecting sector groups at its factory prior to shipping the

device through AMD’s ExpressFlash™ Service. Con-

tact an AMD representative for details.

It is possible to determine whether a sector group is

protected or unprotected. See the Autoselect Mode

section for details.

Sector protection/unprotection requires V_IDon the RE-

SET# pin only, and can be implemented either in-sys-

tem or via programming equipment. Figure 2 shows

Table 3. Sector Group Protection/Unprotection Address Table

Sector Group

SA0

A21–A15

0000000

0000001

0000010

0000011

00001xx

00010xx

00011xx

SA1

SA2

SA3

SA4–SA7

SA8–SA11

SA12–SA15

16

Am29LV640MH/L

December 14, 2005

D A T A S H E E T

Table 3. Sector Group Protection/Unprotection Address Table

Sector Group

SA16–SA19

SA20–SA23

SA24–SA27

SA28–SA31

SA32–SA35

SA36–SA39

SA40–SA43

SA44–SA47

SA48–SA51

SA52–SA55

SA56–SA59

SA60–SA63

SA64–SA67

SA68–SA71

SA72–SA75

SA76–SA79

SA80–SA83

SA84–SA87

SA88–SA91

SA92–SA95

SA96–SA99

SA100–SA103

SA104–SA107

SA108–SA111

SA112–SA115

SA116–SA119

SA120–SA123

SA124

A21–A15

00100xx

00101xx

00110xx

00111xx

01000xx

01001xx

01010xx

01011xx

01100xx

01101xx

01110xx

01111xx

10000xx

10001xx

10010xx

10011xx

10100xx

10101xx

10110xx

10111xx

11000xx

11001xx

11010xx

11011xx

11100xx

11101xx

11110xx

1111100

1111101

1111110

1111111

SA125

SA126

SA127

December 14, 2005

Am29LV640MH/L

17

D A T A S H E E T

Unprotection”. Note: No external pullup is necessary

since the WP#/ACC pin has internal pullup to V_CC

Write Protect (WP#)

.

The Write Protect function provides a hardware

method of protecting the first or last sector without

using V_ID. Write Protect is one of two functions pro-

vided by the WP#/ACC input.

Temporary Sector Group Unprotect

(Note: In this device, a sector group consists of four ad-

jacent sectors that are protected or unprotected at the

same time (see Table 4).

If the system asserts V_ILon the WP#/ACC pin, the de-

vice disables program and erase functions in the first

or last sector independently of whether those sectors

were protected or unprotected using the method de-

scribed in “Sector Group Protection and Unprotection”.

Note that if WP#/ACC is at V_ILwhen the device is in

the standby mode, the maximum input load current is

increased. See the table in “DC Characteristics”.

This feature allows temporary unprotection of previ-

ously protected sector groups to change data in-sys-

tem. The Sector Group Unprotect mode is activated by

setting the RESET# pin to V_ID. During this mode, for-

merly protected sector groups can be programmed or

erased by selecting the sector group addresses. Once

V_IDis removed from the RESET# pin, all the previously

protected sector groups are protected again. Figure 1

shows the algorithm, and Figure 23 shows the timing

diagrams, for this feature.

If the system asserts V_IHon the WP#/ACC pin, the de-

vice reverts to whether the first or last sector was pre-

viously set to be protected or unprotected using the

method described in “Sector Group Protection and

START

RESET# = V_ID

(Note 1)

Perform Erase or

Program Operations

RESET# = V_IH

Temporary Sector

Group Unprotect

Completed (Note 2)

Notes:

1. All protected sector groups unprotected (If WP# = V_IL, the first or last sector will remain protected).

2. All previously protected sector groups are protected once again.

Figure 1. Temporary Sector Group Unprotect Operation

18

Am29LV640MH/L

December 14, 2005

D A T A S H E E T

START

PLSCNT = 1

RESET# = V_ID

Protect all sector

groups: The indicated

portion of the sector

group protect algorithm

must be performed for all

unprotected sector

groups prior to issuing

the first sector group

unprotect address

RESET# = V_ID

Wait 1 μs

Temporary Sector

Group Unprotect

Mode

Temporary Sector

Group Unprotect

Mode

No

First Write

Cycle = 60h?

First Write

Cycle = 60h?

Yes

Set up sector

group address

All sector

groups

No

protected?

Yes

Sector Group Protect:

Write 60h to sector

group address with

A6–A0 = 0xx0010

Set up first sector

group address

Sector Group

Unprotect:

Wait 150 µs

Write 60h to sector

group address with

A6–A0 = 1xx0010

Verify Sector Group

Protect: Write 40h

to sector group

address with

A6–A0 = 0xx0010

Reset

PLSCNT = 1

Increment

PLSCNT

Wait 15 ms

Verify Sector Group

Unprotect: Write

40h to sector group

address with

Read from

sector group address

with A6–A0

= 0xx0010

Increment

PLSCNT

A6–A0 = 1xx0010

No

PLSCNT

= 25?

Read from

sector group

address with

Data = 01h?

Yes

A6–A0 = 1xx0010

No

Yes

Set up

next sector group

address

Protect

another

sector group?

Yes

No

PLSCNT

= 1000?

Data = 00h?

Yes

Device failed

No

Yes

Remove V_ID

from RESET#

Last sector

group

verified?

No

Device failed

Write reset

command

Yes

Remove V_ID

from RESET#

Sector Group

Unprotect

Sector Group

Protect

Sector Group

Protect complete

Write reset

command

Algorithm

Sector Group

Unprotect complete

Figure 2. In-System Sector Group

Protect/Unprotect Algorithms

December 14, 2005

Am29LV640MH/L

19

D A T A S H E E T

AMD offers the device with the SecSi Sector either

SecSi (Secured Silicon) Sector Flash

Memory Region

factory locked or customer lockable. The fac-

tory-locked version is always protected when shipped

from the factory, and has the SecSi (Secured Silicon)

Sector Indicator Bit permanently set to a “1.” The cus-

tomer-lockable version is shipped with the SecSi Sec-

tor unprotected, allowing customers to program the

sector after receiving the device. The customer-lock-

able version also has the SecSi Sector Indicator Bit

permanently set to a “0.” Thus, the SecSi Sector Indi-

cator Bit prevents customer-lockable devices from

being used to replace devices that are factory locked.

The SecSi (Secured Silicon) Sector feature provides a

Flash memory region that enables permanent part

identification through an Electronic Serial Number

(ESN). The SecSi Sector is 128 words/256 bytes in

length, and uses a SecSi Sector Indicator Bit (DQ7) to

indicate whether or not the SecSi Sector is locked

when shipped from the factory. This bit is permanently

set at the factory and cannot be changed, which pre-

vents cloning of a factory locked part. This ensures the

security of the ESN once the product is shipped to the

field.

The SecSi sector address space in this device is allo-

cated as follows:

SecSi Sector Address Range

Standard Factory

Locked

ExpressFlash

Factory Locked

x16

x8

Customer Lockable

000000h–

000007h

000000h–

00000Fh

ESN or determined

by customer

ESN

Determined by customer

000008h–

00007Fh

000010h–

0000FFh

Determined

by customer

Unavailable

The system accesses the SecSi Sector through a

command sequence (see “Enter SecSi Sector/Exit

SecSi Sector Command Sequence”). After the system

has written the Enter SecSi Sector command se-

quence, it may read the SecSi Sector by using the ad-

dresses normally occupied by the first sector (SA0).

This mode of operation continues until the system is-

sues the Exit SecSi Sector command sequence, or

until power is removed from the device. On power-up,

or following a hardware reset, the device reverts to

sending commands to sector SA0.

gram and protect the 128-word/256 bytes SecSi

sector. See Table 5 for SecSi Sector addressing.

The system may program the SecSi Sector using the

write-buffer, accelerated and/or unlock bypass meth-

ods, in addition to the standard programming com-

mand sequence. See Command Definitions.

Programming and protecting the SecSi Sector must be

used with caution since, once protected, there is no

procedure available for unprotecting the SecSi Sector

area and none of the bits in the SecSi Sector memory

space can be modified in any way.

Factory Locked: SecSi Sector Programmed and

Protected At the Factory

The SecSi Sector area can be protected using one of

the following procedures:

In devices with an ESN, the SecSi Sector is protected

when the device is shipped from the factory. The SecSi

Sector cannot be modified in any way. See Table 5 for

SecSi Sector addressing.

■ Write the three-cycle Enter SecSi Sector Region

command sequence, and then follow the in-system

sector protect algorithm as shown in Figure 2, ex-

cept that RESET# may be at either V_IHor V_ID. This

allows in-system protection of the SecSi Sector

without raising any device pin to a high voltage.

Note that this method is only applicable to the SecSi

Sector.

Customers may opt to have their code programmed by

AMD through the AMD ExpressFlash service. The de-

vices are then shipped from AMD’s factory with the

SecSi Sector permanently locked. Contact an AMD

representative for details on using AMD’s Express-

Flash service.

■ To verify the protect/unprotect status of the SecSi

Sector, follow the algorithm shown in Figure 3.

Customer Lockable: SecSi Sector NOT

Programmed or Protected At the Factory

Once the SecSi Sector is programmed, locked and

verified, the system must write the Exit SecSi Sector

Region command sequence to return to reading and

writing within the remainder of the array.

As an alternative to the factory-locked version, the de-

vice may be ordered such that the customer may pro-

20

Am29LV640MH/L

December 14, 2005

D A T A S H E E T

START

If data = 00h,

RESET# =

V_IHor V_ID

SecSi Sector is

unprotected.

If data = 01h,

SecSi Sector is

protected.

Wait 1 ms

Write 60h to

any address

Remove V_IHor V_ID

from RESET#

Write 40h to SecSi

Sector address

with A6 = 0,

Write reset

command

A1 = 1, A0 = 0

SecSi Sector

Protect Verify

complete

Read from SecSi

Sector address

with A6 = 0,

A1 = 1, A0 = 0

Figure 3. SecSi Sector Protect Verify

pins to prevent unintentional writes when V_CCis

greater than V_LKO

Hardware Data Protection

.

The command sequence requirement of unlock cycles

for programming or erasing provides data protection

against inadvertent writes (refer to Tables 10 and 11

for command definitions). In addition, the following

hardware data protection measures prevent accidental

erasure or programming, which might otherwise be

caused by spurious system level signals during V_CC

power-up and power-down transitions, or from system

noise.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE#

or WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# =

V_IL, CE# = V_IHor WE# = V_IH. To initiate a write cycle,

CE# and WE# must be a logical zero while OE# is a

logical one.

Low V_CCWrite Inhibit

When V_CCis less than V_LKO, the device does not ac-

cept any write cycles. This protects data during V_CC

power-up and power-down. The command register

and all internal program/erase circuits are disabled,

and the device resets to the read mode. Subsequent

writes are ignored until V_CCis greater than V_LKO. The

system must provide the proper signals to the control

Power-Up Write Inhibit

If WE# = CE# = V_ILand OE# = V_IHduring power up,

the device does not accept commands on the rising

edge of WE#. The internal state machine is automati-

cally reset to the read mode on power-up.

COMMON FLASH MEMORY INTERFACE (CFI)

The Common Flash Interface (CFI) specification out-

lines device and host system software interrogation

handshake, which allows specific vendor-specified

software algorithms to be used for entire families of

devices. Software support can then be device-inde-

pendent, JEDEC ID-independent, and forward- and

backward-compatible for the specified flash device

families. Flash vendors can standardize their existing

interfaces for long-term compatibility.

55h, any time the device is ready to read array data.

The system can read CFI information at the addresses

given in Tables 6–9. To terminate reading CFI data,

the system must write the reset command.

The system can also write the CFI query command

when the device is in the autoselect mode. The device

enters the CFI query mode, and the system can read

CFI data at the addresses given in Tables 6–9. The

system must write the reset command to return the

device to reading array data.

This device enters the CFI Query mode when the sys-

tem writes the CFI Query command, 98h, to address

December 14, 2005

Am29LV640MH/L

21

D A T A S H E E T

For further information, please refer to the CFI Specifi-

cation and CFI Publication 100, available via the World

Wide Web at http://www.amd.com/flash/cfi. Alterna-

tively, contact a sales office or representative for cop-

ies of these documents.

Table 4. CFI Query Identification String

Addresses

(x16)

Addresses

(x8)

Data

Description

Query Unique ASCII string “QRY”

10h

11h

12h

20h

22h

24h

0051h

0052h

0059h

13h

14h

26h

28h

0002h

0000h

Primary OEM Command Set

15h

16h

2Ah

2Ch

0040h

0000h

Address for Primary Extended Table

17h

18h

2Eh

30h

0000h

Alternate OEM Command Set (00h = none exists)

Address for Alternate OEM Extended Table (00h = none exists)

19h

1Ah

32h

34h

0000h

Table 5. System Interface String

Description

Addresses

(x16)

Addresses

(x8)

Data

V_CCMin. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

1Bh

1Ch

36h

38h

0027h

V_CCMax. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

0036h

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

3Ah

3Ch

3Eh

40h

42h

44h

46h

48h

4Ah

4Ch

0000h

0007h

000Ah

0000h

0001h

0005h

0004h

0000h

V_PPMin. voltage (00h = no V_PPpin present)

V_PPMax. voltage (00h = no V_PPpin present)

Typical timeout per single byte/word write 2^Nµs

Typical timeout for Min. size buffer write 2^Nµs (00h = not supported)

Typical timeout per individual block erase 2^Nms

Typical timeout for full chip erase 2^Nms (00h = not supported)

Max. timeout for byte/word write 2^Ntimes typical

Max. timeout for buffer write 2^Ntimes typical

Max. timeout per individual block erase 2^Ntimes typical

Max. timeout for full chip erase 2^Ntimes typical (00h = not supported)

22

Am29LV640MH/L

December 14, 2005

D A T A S H E E T

Table 6. Device Geometry Definition

Addresses Addresses

(x16)

(x8)

Data

Description

27h

4Eh

0017h

Device Size = 2^Nbyte

28h

29h

50h

52h

0002h

0000h

Flash Device Interface description (refer to CFI publication 100)

2Ah

2Bh

54h

56h

0005h

0000h

Max. number of byte in multi-byte write = 2^N

(00h = not supported)

Number of Erase Block Regions within device (01h = uniform device, 02h = boot

device)

2Ch

58h

0001h

2Dh

2Eh

2Fh

30h

5Ah

5Ch

5Eh

60h

007Fh

0000h

0001h

Erase Block Region 1 Information

(refer to the CFI specification or CFI publication 100)

31h

32h

33h

34h

62h

64h

66h

68h

0000h

Erase Block Region 2 Information (refer to CFI publication 100)

Erase Block Region 3 Information (refer to CFI publication 100)

Erase Block Region 4 Information (refer to CFI publication 100)

35h

36h

37h

38h

6Ah

6Ch

6Eh

70h

0000h

39h

3Ah

3Bh

3Ch

72h

74h

76h

78h

0000h

December 14, 2005

Am29LV640MH/L

23

D A T A S H E E T

Table 7. Primary Vendor-Specific Extended Query

Addresses Addresses

(x16)

(x8)

Data

Description

40h

41h

42h

80h

82h

84h

0050h

0052h

0049h

Query-unique ASCII string “PRI”

43h

44h

86h

88h

0031h

0033h

Major version number, ASCII

Minor version number, ASCII

Address Sensitive Unlock (Bits 1-0)

0 = Required, 1 = Not Required

45h

8Ah

0008h

Process Technology (Bits 7-2) 0010b = 0.23 µm MirrorBit

Erase Suspend

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

46h

47h

48h

49h

4Ah

4Bh

4Ch

8Ch

8Eh

90h

92h

94h

96h

98h

0002h

0001h

0004h

0000h

0001h

Sector Protect

0 = Not Supported, X = Number of sectors in per group

Sector Temporary Unprotect

00 = Not Supported, 01 = Supported

Sector Protect/Unprotect scheme

04 = 29LV800 mode

Simultaneous Operation

00 = Not Supported, X = Number of Sectors in Bank

Burst Mode Type

00 = Not Supported, 01 = Supported

Page Mode Type

00 = Not Supported, 01 = 4 Word/8 Byte Page, 02 = 8 Word/16 Byte Page

ACC (Acceleration) Supply Minimum

4Dh

4Eh

9Ah

9Ch

00B5h

00C5h

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

ACC (Acceleration) Supply Maximum

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

Top/Bottom Boot Sector Flag

0004h/

0005h

00h = Uniform Device without WP# protect, 02h = Bottom Boot Device, 03h = Top

Boot Device, 04h = Uniform sectors bottom WP# protect, 05h = Uniform sectors top

WP# protect

4Fh

50h

9Eh

A0h

Program Suspend

0001h

00h = Not Supported, 01h = Supported

COMMAND DEFINITIONS

Writing specific address and data commands or se-

quences into the command register initiates device op-

erations. Tables 10 and 11 define the valid register

command sequences. Writing incorrect address and

data values or writing them in the improper se-

quence may place the device in an unknown state. A

reset command is then required to return the device to

reading array data.

after completing an Embedded Program or Embedded

Erase algorithm.

After the device accepts an Erase Suspend command,

the device enters the erase-suspend-read mode, after

which the system can read data from any

non-erase-suspended sector. After completing a pro-

gramming operation in the Erase Suspend mode, the

system may once again read array data with the same

exception. See the Erase Suspend/Erase Resume

Commands section for more information.

All addresses are latched on the falling edge of WE#

or CE#, whichever happens later. All data is latched on

the rising edge of WE# or CE#, whichever happens

first. Refer to the AC Characteristics section for timing

diagrams.

The system must issue the reset command to return

the device to the read (or erase-suspend-read) mode if

DQ5 goes high during an active program or erase op-

eration, or if the device is in the autoselect mode. See

the next section, Reset Command, for more informa-

tion.

Reading Array Data

The device is automatically set to reading array data

after device power-up. No commands are required to

retrieve data. The device is ready to read array data

See also Requirements for Reading Array Data in the

Device Bus Operations section for more information.

24

Am29LV640MH/L

December 14, 2005

D A T A S H E E T

The Read-Only Operations table provides the read pa-

The reset command may be written between the se-

quence cycles in an autoselect command sequence.

Once in the autoselect mode, the reset command

must be written to return to the read mode. If the de-

vice entered the autoselect mode while in the Erase

Suspend mode, writing the reset command returns the

device to the erase-suspend-read mode.

rameters, and Figure 14 shows the timing diagram.

Reset Command

Writing the reset command resets the device to the

read or erase-suspend-read mode. Address bits are

don’t cares for this command.

If DQ5 goes high during a program or erase operation,

writing the reset command returns the device to the

read mode (or erase-suspend-read mode if the device

was in Erase Suspend).

The reset command may be written between the se-

quence cycles in an erase command sequence before

erasing begins. This resets the device to the read

mode. Once erasure begins, however, the device ig-

nores reset commands until the operation is complete.

Note that if DQ1 goes high during a Write Buffer Pro-

gramming operation, the system must write the

Write-to-Buffer-Abort Reset command sequence to

reset the device for the next operation.

The reset command may be written between the

sequence cycles in a program command sequence

before programming begins. This resets the device to

the read mode. If the program command sequence is

written while the device is in the Erase Suspend mode,

writing the reset command returns the device to the

erase-suspend-read mode. Once programming be-

gins, however, the device ignores reset commands

until the operation is complete.

Autoselect Command Sequence

The autoselect command sequence allows the host

system to read several identifier codes at specific ad-

dresses:

A7:A0

(x16)

A6:A-1

(x8)

Identifier Code

Manufacturer ID

Device ID, Cycle 1

00h

01h

00h

02h

Device ID, Cycle 2

0Eh

1Ch

Device ID, Cycle 3

0Fh

1Eh

SecSi Sector Factory Protect

Sector Protect Verify

03h

06h

(SA)02h

(SA)04h

Note: The device ID is read over three cycles. SA = Sector Address

Tables 10 and 11 show the address requirements and

codes. This method is an alternative to that shown in

Table 3, which is intended for PROM programmers

and requires V_IDon address pin A9. The autoselect

command sequence may be written to an address that

is either in the read or erase-suspend-read mode. The

autoselect command may not be written while the de-

vice is actively programming or erasing.

Sector command sequence. The device continues to

access the SecSi Sector region until the system is-

sues the four-cycle Exit SecSi Sector command se-

quence. The Exit SecSi Sector command sequence

returns the device to normal operation. Tables 10 and

11 show the address and data requirements for both

command sequences. See also “SecSi (Secured Sili-

con) Sector Flash Memory Region” for further informa-

tion. Note that the ACC function and unlock bypass

modes are not available when the SecSi Sector is en-

abled.

The autoselect command sequence is initiated by first

writing two unlock cycles. This is followed by a third

write cycle that contains the autoselect command. The

device then enters the autoselect mode. The system

may read at any address any number of times without

initiating another autoselect command sequence:

Word/Byte Program Command Sequence

Programming is a four-bus-cycle operation. The pro-

gram command sequence is initiated by writing two

unlock write cycles, followed by the program set-up

command. The program address and data are written

next, which in turn initiate the Embedded Program al-

gorithm. The system is not required to provide further

controls or timings. The device automatically provides

internally generated program pulses and verifies the

programmed cell margin. Tables 10 and 11 show the

address and data requirements for the word/byte pro-

gram command sequence, respectively.

The system must write the reset command to return to

the read mode (or erase-suspend-read mode if the de-

vice was previously in Erase Suspend).

Enter SecSi Sector/Exit SecSi Sector

Command Sequence

The SecSi Sector region provides a secured data area

containing an 8-word/16-byte random Electronic Serial

Number (ESN). The system can access the SecSi

Sector region by issuing the three-cycle Enter SecSi

December 14, 2005

Am29LV640MH/L

25

D A T A S H E E T

When the Embedded Program algorithm is complete,

by a third write cycle containing the Write Buffer Load

command written at the Sector Address in which pro-

gramming will occur. The fourth cycle writes the sector

address and the number of word locations, minus one,

to be programmed. For example, if the system will pro-

gram 6 unique address locations, then 05h should be

written to the device. This tells the device how many

write buffer addresses will be loaded with data and

therefore when to expect the Program Buffer to Flash

command. The number of locations to program cannot

exceed the size of the write buffer or the operation will

abort.

the device then returns to the read mode and ad-

dresses are no longer latched. The system can deter-

mine the status of the program operation by using

DQ7 or DQ6. Refer to the Write Operation Status sec-

tion for information on these status bits.

Any commands written to the device during the Em-

bedded Program Algorithm are ignored. Note that a

hardware reset immediately terminates the program

operation. The program command sequence should

be reinitiated once the device has returned to the read

mode, to ensure data integrity. Note that the ACC

function and unlock bypass modes are not available

when the SecSi Sector is enabled.

The fifth cycle writes the first address location and

data to be programmed. The write-buffer-page is se-

lected by address bits A_MAX–A₄. All subsequent ad-

dress/data pairs must fall within the

selected-write-buffer-page. The system then writes the

remaining address/data pairs into the write buffer.

Write buffer locations may be loaded in any order.

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed

from “0” back to a “1.” Attempting to do so may

cause the device to set DQ5 = 1, or cause the DQ7

and DQ6 status bits to indicate the operation was suc-

cessful. However, a succeeding read will show that the

data is still “0.” Only erase operations can convert a “0”

to a “1.”

The write-buffer-page address must be the same for

all address/data pairs loaded into the write buffer.

(This means Write Buffer Programming cannot be per-

formed across multiple write-buffer pages. This also

means that Write Buffer Programming cannot be per-

formed across multiple sectors. If the system attempts

to load programming data outside of the selected

write-buffer page, the operation will abort.

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to pro-

gram words to the device faster than using the stan-

dard program command sequence. The unlock bypass

command sequence is initiated by first writing two un-

lock cycles. This is followed by a third write cycle con-

taining the unlock bypass command, 20h. The device

then enters the unlock bypass mode. A two-cycle un-

lock bypass program command sequence is all that is

required to program in this mode. The first cycle in this

sequence contains the unlock bypass program com-

mand, A0h; the second cycle contains the program

address and data. Additional data is programmed in

the same manner. This mode dispenses with the initial

two unlock cycles required in the standard program

command sequence, resulting in faster total program-

ming time. Tables 10 and 11 show the requirements

for the command sequence.

Note that if a Write Buffer address location is loaded

multiple times, the address/data pair counter will be

decremented for every data load operation. The host

system must therefore account for loading a

write-buffer location more than once. The counter

decrements for each data load operation, not for each

unique write-buffer-address location. Note also that if

an address location is loaded more than once into the

buffer, the final data loaded for that address will be

programmed.

Once the specified number of write buffer locations

have been loaded, the system must then write the Pro-

gram Buffer to Flash command at the sector address.

Any other address and data combination aborts the

Write Buffer Programming operation. The device then

begins programming. Data polling should be used

while monitoring the last address location loaded into

the write buffer. DQ7, DQ6, DQ5, and DQ1 should be

monitored to determine the device status during Write

Buffer Programming.

During the unlock bypass mode, only the Unlock By-

pass Program and Unlock Bypass Reset commands

are valid. To exit the unlock bypass mode, the system

must issue the two-cycle unlock bypass reset com-

mand sequence. The first cycle must contain the data

90h. The second cycle must contain the data 00h. The

device then returns to the read mode.

The write-buffer programming operation can be sus-

pended using the standard program suspend/resume

commands. Upon successful completion of the Write

Buffer Programming operation, the device is ready to

execute the next command.

Write Buffer Programming

Write Buffer Programming allows the system write to a

maximum of 16 words/32 bytes in one programming

operation. This results in faster effective programming

time than the standard programming algorithms. The

Write Buffer Programming command sequence is initi-

ated by first writing two unlock cycles. This is followed

The Write Buffer Programming Sequence can be

aborted in the following ways:

26

Am29LV640MH/L

December 14, 2005

D A T A S H E E T

■ Load a value that is greater than the page buffer

quired when using Write-Buffer-Programming features

in Unlock Bypass mode.

size during the Number of Locations to Program

step.

Accelerated Program

■ Write to an address in a sector different than the

one specified during the Write-Buffer-Load com-

mand.

The device offers accelerated program operations

through the WP#/ACC pin. When the system asserts

V_HHon the WP#/ACC pin, the device automatically en-

ters the Unlock Bypass mode. The system may then

write the two-cycle Unlock Bypass program command

sequence. The device uses the higher voltage on the

WP#/ACC pin to accelerate the operation. Note that

the WP#/ACC pin must not be at V_HHfor operations

other than accelerated programming, or device dam-

age may result. In addition, no external pullup is nec-

essary since the WP#/ACC pin has internal pullup to

■ Write an Address/Data pair to

a

different

write-buffer-page than the one selected by the

Starting Address during the write buffer data load-

ing stage of the operation.

■ Write data other than the Confirm Command after

the specified number of data load cycles.

The abort condition is indicated by DQ1 = 1, DQ7 =

DATA# (for the last address location loaded), DQ6 =

toggle, and DQ5=0. A Write-to-Buffer-Abort Reset

command sequence must be written to reset the de-

vice for the next operation. Note that the full 3-cycle

Write-to-Buffer-Abort Reset command sequence is re-

V_CC

.

Figure 5 illustrates the algorithm for the program oper-

ation. Refer to the Erase and Program Operations

table in the AC Characteristics section for parameters,

and Figure 17 for timing diagrams.

December 14, 2005

Am29LV640MH/L

27

D A T A S H E E T

Write “Write to Buffer”

command and

Sector Address

Part of “Write to Buffer”

Command Sequence

Write number of addresses

to program minus 1(WC)

and Sector Address

Write first address/data

Yes

WC = 0 ?

No

Write to a different

sector address

Abort Write to

Buffer Operation?

Yes

Write to buffer ABORTED.

Must write “Write-to-buffer

Abort Reset” command

sequence to return

No

(Note 1)

Write next address/data pair

to read mode.

WC = WC - 1

Write program buffer to

flash sector address

Notes:

1. When Sector Address is specified, any address in

the selected sector is acceptable. However, when

loading Write-Buffer address locations with data, all

addresses must fall within the selected Write-Buffer

Page.

Read DQ7 - DQ0 at

Last Loaded Address

2. DQ7 may change simultaneously with DQ5.

Therefore, DQ7 should be verified.

3. If this flowchart location was reached because

DQ5= “1”, then the device FAILED. If this flowchart

location was reached because DQ1= “1”, then the

Write to Buffer operation was ABORTED. In either

case, the proper reset command must be written

before the device can begin another operation. If

DQ1=1, write the

Yes

DQ7 = Data?

No

Write-Buffer-Programming-Abort-Reset

command. if DQ5=1, write the Reset command.

No

DQ1 = 1?

Yes

DQ5 = 1?

Yes

4. See Table 11 for command sequences required for

write buffer programming.

Read DQ7 - DQ0 with

address = Last Loaded

Address

Yes

(Note 2)

DQ7 = Data?

No

(Note 3)

FAIL or ABORT

PASS

Figure 4. Write Buffer Programming Operation

28

Am29LV640MH/L

December 14, 2005

D A T A S H E E T

START

Write Program

Command Sequence

Data Poll

from System

Embedded

Program

algorithm

in progress

Verify Data?

Yes

No

Increment Address

Last Address?

Yes

Programming

Completed

Note: See Table 11 for program command sequence.

Figure 5. Program Operation

autoselect, and CFI functions are unavailable when an

program operation is in progress.

Program Suspend/Program Resume

Command Sequence

The system may also write the autoselect command

sequence when the device is in the Program Suspend

mode. The system can read as many autoselect

codes as required. When the device exits the autose-

lect mode, the device reverts to the Program Suspend

mode, and is ready for another valid operation. See

Autoselect Command Sequence for more information.

The Program Suspend command allows the system to

interrupt a programming operation or a Write to Buffer

programming operation so that data can be read from

any non-suspended sector. When the Program Sus-

pend command is written during a programming pro-

cess, the device halts the program operation within 15

μs maximum (5 μs typical) and updates the status bits.

Addresses are not required when writing the Program

Suspend command.

After the Program Resume command is written, the

device reverts to programming. The system can de-

termine the status of the program operation using the

DQ7 or DQ6 status bits, just as in the standard pro-

gram operation. See Write Operation Status for more

information.

After the programming operation has been sus-

pended, the system can read array data from any

non-suspended sector. The Program Suspend com-

mand may also be issued during a programming oper-

ation while an erase is suspended. In this case, data

may be read from any addresses not in Erase Sus-

pend or Program Suspend. If a read is needed from

the SecSi Sector area (One-time Program area), then

user must use the proper command sequences to

enter and exit this region. Note that the SecSi Sector,

The system must write the Program Resume com-

mand (address bits are don’t care) to exit the Program

Suspend mode and continue the programming opera-

tion. Further writes of the Resume command are ig-

nored. Another Program Suspend command can be

written after the device has resume programming.

December 14, 2005

Am29LV640MH/L

29

D A T A S H E E T

Program Operation

or Write-to-Buffer

Sequence in Progress

Write Program Suspend

Command Sequence

Write address/data

XXXh/B0h

Command is also valid for

Erase-suspended-program

operations

Wait 15 μs

Autoselect and SecSi Sector

read operations are also allowed

Read data as

required

Data cannot be read from erase- or

program-suspended sectors

Done

No

reading?

Yes

Write Program Resume

Command Sequence

Write address/data

XXXh/30h

Device reverts to

operation prior to

Program Suspend

Figure 6. Program Suspend/Program Resume

mediately terminates the erase operation. If that oc-

curs, the chip erase command sequence should be

reinitiated once the device has returned to reading

array data, to ensure data integrity. Note that the

SecSi Sector, autoselect, and CFI functions are un-

available when an erase operation is in progress.

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase

command sequence is initiated by writing two unlock

cycles, followed by a set-up command. Two additional

unlock write cycles are then followed by the chip erase

command, which in turn invokes the Embedded Erase

algorithm. The device does not require the system to

preprogram prior to erase. The Embedded Erase algo-

rithm automatically preprograms and verifies the entire

memory for an all zero data pattern prior to electrical

erase. The system is not required to provide any con-

trols or timings during these operations. Tables 10 and

11 show the address and data requirements for the

chip erase command sequence.

Figure 7 illustrates the algorithm for the erase opera-

tion. Refer to the Erase and Program Operations ta-

bles in the AC Characteristics section for parameters,

and Figure 19 section for timing diagrams.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector

erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two ad-

ditional unlock cycles are written, and are then fol-

lowed by the address of the sector to be erased, and

the sector erase command. Tables 10 and 11 show the

address and data requirements for the sector erase

command sequence.

When the Embedded Erase algorithm is complete, the

device returns to the read mode and addresses are no

longer latched. The system can determine the status

of the erase operation by using DQ7, DQ6, or DQ2.

Refer to the Write Operation Status section for infor-

mation on these status bits.

The device does not require the system to preprogram

prior to erase. The Embedded Erase algorithm auto-

matically programs and verifies the entire memory for

Any commands written during the chip erase operation

are ignored. However, note that a hardware reset im-

30

Am29LV640MH/L

December 14, 2005

D A T A S H E E T

an all zero data pattern prior to electrical erase. The

The system can monitor DQ3 to determine if the sec-

tor erase timer has timed out (See the section on DQ3:

Sector Erase Timer.). The time-out begins from the ris-

ing edge of the final WE# pulse in the command

sequence.

system is not required to provide any controls or tim-

ings during these operations.

After the command sequence is written, a sector erase

time-out of 50 µs occurs. During the time-out period,

additional sector addresses and sector erase com-

mands may be written. Loading the sector erase buffer

may be done in any sequence, and the number of sec-

tors may be from one sector to all sectors. The time

between these additional cycles must be less than 50

µs, otherwise erasure may begin. Any sector erase ad-

dress and command following the exceeded time-out

may or may not be accepted. It is recommended that

processor interrupts be disabled during this time to en-

sure all commands are accepted. The interrupts can

be re-enabled after the last Sector Erase command is

written. Any command other than Sector Erase or

Erase Suspend during the time-out period resets

the device to the read mode. The system must re-

write the command sequence and any additional ad-

dresses and commands. Note that the SecSi Sector,

autoselect, and CFI functions are unavailable when an

erase operation is in progress.

When the Embedded Erase algorithm is complete, the

device returns to reading array data and addresses

are no longer latched. The system can determine the

status of the erase operation by reading DQ7, DQ6, or

DQ2 in the erasing sector. Refer to the Write Opera-

tion Status section for information on these status bits.

Once the sector erase operation has begun, only the

Erase Suspend command is valid. All other com-

mands are ignored. However, note that a hardware

reset immediately terminates the erase operation. If

that occurs, the sector erase command sequence

should be reinitiated once the device has returned to

reading array data, to ensure data integrity.

Figure 7 illustrates the algorithm for the erase opera-

tion. Refer to the Erase and Program Operations ta-

bles in the AC Characteristics section for parameters,

and Figure 19 section for timing diagrams.

START

Write Erase

Command Sequence

(Notes 1, 2)

Data Poll to Erasing

Bank from System

Embedded

Erase

algorithm

in progress

No

Data = FFh?

Yes

Erasure Completed

Notes:

1. See Tables 10 and 11 for erase command sequence.

2. See the section on DQ3 for information on the sector erase timer.

Figure 7. Erase Operation

December 14, 2005

Am29LV640MH/L

31

D A T A S H E E T

After an erase-suspended program operation is com-

Erase Suspend/Erase Resume

Commands

plete, the device returns to the erase-suspend-read

mode. The system can determine the status of the

program operation using the DQ7 or DQ6 status bits,

just as in the standard word program operation.

Refer to the Write Operation Status section for more

information.

The Erase Suspend command, B0h, allows the sys-

tem to interrupt a sector erase operation and then read

data from, or program data to, any sector not selected

for erasure. This command is valid only during the sec-

tor erase operation, including the 50 µs time-out pe-

riod during the sector erase command sequence. The

Erase Suspend command is ignored if written during

the chip erase operation or Embedded Program

algorithm.

In the erase-suspend-read mode, the system can also

issue the autoselect command sequence. Refer to the

Autoselect Mode and Autoselect Command Sequence

sections for details.

To resume the sector erase operation, the system

must write the Erase Resume command. Further

writes of the Resume command are ignored. Another

Erase Suspend command can be written after the chip

has resumed erasing.

When the Erase Suspend command is written during

the sector erase operation, the device requires a max-

imum of 20 (typical 5 µs) to suspend the erase opera-

tion. However, when the Erase Suspend command is

written during the sector erase time-out, the device im-

mediately terminates the time-out period and sus-

pends the erase operation.

Note: During an erase operation, this flash device per-

forms multiple internal operations which are invisible

to the system. When an erase operation is suspended,

any of the internal operations that were not fully com-

pleted must be restarted. As such, if this flash device

is continually issued suspend/resume commands in

rapid succession, erase progress will be impeded as a

function of the number of suspends. The result will be

a longer cumulative erase time than without suspends.

Note that the additional suspends do not affect device

reliability or future performance. In most systems rapid

erase/suspend activity occurs only briefly. In such

cases, erase performance will not be significantly im-

pacted.

After the erase operation has been suspended, the

device enters the erase-suspend-read mode. The sys-

tem can read data from or program data to any sector

not selected for erasure. (The device “erase sus-

pends” all sectors selected for erasure.) Reading at

any address within erase-suspended sectors pro-

duces status information on DQ7–DQ0. The system

can use DQ7, or DQ6 and DQ2 together, to determine

if a sector is actively erasing or is erase-suspended.

Refer to the Write Operation Status section for infor-

mation on these status bits.

32

Am29LV640MH/L

December 14, 2005

D A T A S H E E T

Command Definitions

Table 8. Command Definitions (x16 Mode, BYTE# = V_IH)

Bus Cycles (Notes 2–5)

Command

Sequence

(Note 1)

First

Second

Third

Fourth

Fifth

Sixth

Addr Data Addr Data

Addr

Data

Addr

Data

Addr Data Addr Data

Read (Note 5)

1

4

6

RA

XXX

555

RD

F0

Reset (Note 6)

Manufacturer ID

Device ID (Note 8)

AA

2AA

55

555

90

X00

X01

0001

227E

X0E 220C X0F 2201

SecSi™ Sector Factory Protect

(Note 9)

4

555

AA

2AA

55

555

90

X03

(Note 10)

00/01

Sector Group Protect Verify

(Note 10)

(SA)X02

Enter SecSi Sector Region

Exit SecSi Sector Region

Program

3

4

6

1

3

2

6

1

555

SA

AA

29

2AA

55

555

SA

88

90

A0

25

XXX

PA

00

PD

WC

Write to Buffer (Note 11)

Program Buffer to Flash

Write to Buffer Abort Reset (Note 12)

Unlock Bypass

SA

PA

PD

WBL

PD

555

XXX

555

XXX

55

AA

A0

90

2AA

PA

55

PD

00

55

555

F0

20

Unlock Bypass Program (Note 13)

Unlock Bypass Reset (Note 14)

Chip Erase

XXX

2AA

AA

B0

30

555

80

555

AA

2AA

55

555

SA

10

30

Sector Erase

Program/Erase Suspend (Note 15)

Program/Erase Resume (Note 16)

CFI Query (Note 17)

98

Legend:

X = Don’t care

RA = Read Address of memory location to be read.

PD = Program Data for location PA. Data latches on rising edge of

WE# or CE# pulse, whichever happens first.

SA = Sector Address of sector to be verified (in autoselect mode) or

erased. Address bits A21–A15 uniquely select any sector.

WBL = Write Buffer Location. Address must be within same write

buffer page as PA.

RD = Read Data read from location RA during read operation.

PA = Program Address . Addresses latch on falling edge of WE# or

CE# pulse, whichever happens later.

WC = Word Count. Number of write buffer locations to load minus 1.

Notes:

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

3. Shaded cells indicate read cycles. All others are write cycles.

4. During unlock and command cycles, when lower address bits are

555 or 2AA as shown in table, address bits above A11 and data

bits above DQ7 are don’t care.

9. If WP# protects highest address sector, data is 98h for factory

locked and 18h for not factory locked. If WP# protects lowest

address sector, data is 88h for factory locked and 08h for not

factor locked.

10. Data is 00h for an unprotected sector group and 01h for a

protected sector group.

11. Total number of cycles in command sequence is determined by

number of words written to write buffer. Maximum number of

cycles in command sequence is 21, including "Program Buffer to

Flash" command.

12. Command sequence resets device for next command after

aborted write-to-buffer operation.

13. Unlock Bypass command is required prior to Unlock Bypass

Program command.

14. Unlock Bypass Reset command is required to return to read

mode when device is in unlock bypass mode.

5. No unlock or command cycles required when device is in read

mode.

6. Reset command is required to return to read mode (or to

erase-suspend-read mode if previously in Erase Suspend) when

device is in autoselect mode, or if DQ5 goes high while device is

providing status information.

7. Fourth cycle of the autoselect command sequence is a read

cycle. Data bits DQ15–DQ8 are don’t care. Except for RD, PD

and WC. See Autoselect Command Sequence section for more

information.

15. System may read and program in non-erasing sectors, or enter

autoselect mode, when in Erase Suspend mode. Erase Suspend

command is valid only during a sector erase operation.

8. Device ID must be read in three cycles.

16. Erase Resume command is valid only during Erase Suspend

mode.

December 14, 2005

Am29LV640MH/L

33

D A T A S H E E T

Table 9. Command Definitions (x8 Mode, BYTE# = V_IL)

Bus Cycles (Notes 2–5)

Command

Sequence

(Note 1)

First

Second

Third

Fourth

Fifth

Sixth

Addr Data Addr Data

Addr

Data

Addr

Data

Addr Data Addr Data

Read (Note 6)

Reset (Note 7)

Manufacturer ID

1

4

6

RA

RD

F0

XXX

AAA

AA

555

55

AAA

90

X00

X02

01

7E

Device ID (Note 9)

X1C

0C

X1E

01

SecSi™ Sector Factory Protect

(Note 10)

4

AAA

AA

555

55

AAA

90

X06

(Note 10)

00/01

Sector Group Protect Verify

(Note 11)

(SA)X04

Enter SecSi Sector Region

Exit SecSi Sector Region

Program

3

4

6

1

3

2

6

1

AAA

SA

AA

29

555

55

AAA

SA

88

90

A0

25

XXX

PA

00

PD

BC

Write to Buffer (Note 12)

Program Buffer to Flash

Write to Buffer Abort Reset (Note 13)

Unlock Bypass

SA

PA

PD

WBL

PD

AAA

XXX

AAA

XXX

AA

A0

90

555

PA

55

PD

00

55

AAA

F0

20

Unlock Bypass Program (Note 14)

Unlock Bypass Reset (Note 15)

Chip Erase

XXX

555

AA

B0

30

AAA

80

AAA

AA

555

55

AAA

SA

10

30

Sector Erase

Program/Erase Suspend (Note 16)

Program/Erase Resume (Note 17)

CFI Query (Note 18)

98

Legend:

X = Don’t care

RA = Read Address of memory location to be read.

PD = Program Data for location PA. Data latches on rising edge of

WE# or CE# pulse, whichever happens first.

SA = Sector Address of sector to be verified (in autoselect mode) or

erased. Address bits A21–A15 uniquely select any sector.

WBL = Write Buffer Location. Address must be within same write

buffer page as PA.

RD = Read Data read from location RA during read operation.

PA = Program Address . Addresses latch on falling edge of WE# or

CE# pulse, whichever happens later.

BC = Byte Count. Number of write buffer locations to load minus 1.

Notes:

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

3. Shaded cells indicate read cycles. All others are write cycles.

4. During unlock and command cycles, when lower address bits are

555 or AAA as shown in table, address bits above A11 are don’t

care.

10. If WP# protects highest address sector, data is 98h for factory

locked and 18h for not factory locked. If WP# protects lowest

address sector, data is 88h for factory locked and 08h for not

factor locked.

11. Data is 00h for an unprotected sector group and 01h for a

protected sector group.

12. Total number of cycles in command sequence is determined by

number of bytes written to write buffer. Maximum number of

cycles in command sequence is 37, including "Program Buffer to

Flash" command.

13. Command sequence resets device for next command after

aborted write-to-buffer operation.

14. Unlock Bypass command is required prior to Unlock Bypass

Program command.

15. Unlock Bypass Reset command is required to return to read

mode when device is in unlock bypass mode.

5. Unless otherwise noted, address bits A21–A11 are don’t cares.

6. No unlock or command cycles required when device is in read

mode.

7. Reset command is required to return to read mode (or to

erase-suspend-read mode if previously in Erase Suspend) when

device is in autoselect mode, or if DQ5 goes high while device is

providing status information.

8. Fourth cycle of autoselect command sequence is a read cycle.

Data bits DQ15–DQ8 are don’t care. See Autoselect Command

Sequence section or more information.

16. System may read and program in non-erasing sectors, or enter

autoselect mode, when in Erase Suspend mode. Erase Suspend

command is valid only during a sector erase operation.

9. Device ID must be read in three cycles.

17. Erase Resume command is valid only during Erase Suspend

mode.

34

Am29LV640MH/L

December 14, 2005

D A T A S H E E T

WRITE OPERATION STATUS

The device provides several bits to determine the sta-

tus of a program or erase operation: DQ2, DQ3, DQ5,

DQ6, and DQ7. Table 12 and the following subsec-

tions describe the function of these bits. DQ7 and DQ6

each offer a method for determining whether a pro-

gram or erase operation is complete or in progress.

The device also provides a hardware-based output

signal, RY/BY#, to determine whether an Embedded

Program or Erase operation is in progress or has been

completed.

algorithm is complete, or if the device enters the Erase

Suspend mode, Data# Polling produces a “1” on DQ7.

The system must provide an address within any of the

sectors selected for erasure to read valid status infor-

mation on DQ7.

After an erase command sequence is written, if all

sectors selected for erasing are protected, Data# Poll-

ing on DQ7 is active for approximately 100 µs, then the

device returns to the read mode. If not all selected

sectors are protected, the Embedded Erase algorithm

erases the unprotected sectors, and ignores the se-

lected sectors that are protected. However, if the sys-

tem reads DQ7 at an address within a protected

sector, the status may not be valid.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host sys-

tem whether an Embedded Program or Erase algo-

rithm is in progress or completed, or whether the

device is in Erase Suspend. Data# Polling is valid after

the rising edge of the final WE# pulse in the command

sequence.

Just prior to the completion of an Embedded Program

or Erase operation, DQ7 may change asynchronously

with DQ0–DQ6 while Output Enable (OE#) is asserted

low. That is, the device may change from providing

status information to valid data on DQ7. Depending on

when the system samples the DQ7 output, it may read

the status or valid data. Even if the device has com-

pleted the program or erase operation and DQ7 has

valid data, the data outputs on DQ0–DQ6 may be still

invalid. Valid data on DQ0–DQ7 will appear on suc-

cessive read cycles.

During the Embedded Program algorithm, the device

outputs on DQ7 the complement of the datum pro-

grammed to DQ7. This DQ7 status also applies to pro-

gramming during Erase Suspend. When the

Embedded Program algorithm is complete, the device

outputs the datum programmed to DQ7. The system

must provide the program address to read valid status

information on DQ7. If a program address falls within a

protected sector, Data# Polling on DQ7 is active for

approximately 1 µs, then the device returns to the read

mode.

Table 12 shows the outputs for Data# Polling on DQ7.

Figure 8 shows the Data# Polling algorithm. Figure 20

in the AC Characteristics section shows the Data#

Polling timing diagram.

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase

December 14, 2005

Am29LV640MH/L

35

D A T A S H E E T

START

Read DQ7–DQ0

Addr = VA

Yes

DQ7 = Data?

No

DQ5 = 1?

Yes

Read DQ7–DQ0

Addr = VA

Yes

DQ7 = Data?

No

PASS

FAIL

Notes:

1. VA = Valid address for programming. During a sector erase operation, a valid

address is any sector address within the sector being erased. During chip erase, a

valid address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simulta-

neously with DQ5.

Figure 8. Data# Polling Algorithm

36

Am29LV640MH/L

December 14, 2005

D A T A S H E E T

After an erase command sequence is written, if all

RY/BY#: Ready/Busy#

sectors selected for erasing are protected, DQ6 tog-

gles for approximately 100 µs, then returns to reading

array data. If not all selected sectors are protected, the

Embedded Erase algorithm erases the unprotected

sectors, and ignores the selected sectors that are pro-

tected.

The RY/BY# is a dedicated, open-drain output pin

which indicates whether an Embedded Algorithm is in

progress or complete. The RY/BY# status is valid after

the rising edge of the final WE# pulse in the command

sequence. Since RY/BY# is an open-drain output, sev-

eral RY/BY# pins can be tied together in parallel with a

pull-up resistor to V_CC

.

The system can use DQ6 and DQ2 together to deter-

mine whether a sector is actively erasing or is

erase-suspended. When the device is actively erasing

(that is, the Embedded Erase algorithm is in progress),

DQ6 toggles. When the device enters the Erase Sus-

pend mode, DQ6 stops toggling. However, the system

must also use DQ2 to determine which sectors are

erasing or erase-suspended. Alternatively, the system

can use DQ7 (see the subsection on DQ7: Data# Poll-

ing).

If the output is low (Busy), the device is actively eras-

ing or programming. (This includes programming in

the Erase Suspend mode.) If the output is high

(Ready), the device is in the read mode, the standby

mode, or in the erase-suspend-read mode. Table 12

shows the outputs for RY/BY#.

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded

Program or Erase algorithm is in progress or com-

plete, or whether the device has entered the Erase

Suspend mode. Toggle Bit I may be read at any ad-

dress, and is valid after the rising edge of the final

WE# pulse in the command sequence (prior to the

program or erase operation), and during the sector

erase time-out.

If a program address falls within a protected sector,

DQ6 toggles for approximately 1 μs after the program

command sequence is written, then returns to reading

array data.

DQ6 also toggles during the erase-suspend-program

mode, and stops toggling once the Embedded Pro-

gram algorithm is complete.

During an Embedded Program or Erase algorithm op-

eration, successive read cycles to any address cause

DQ6 to toggle. The system may use either OE# or

CE# to control the read cycles. When the operation is

complete, DQ6 stops toggling.

Table 12 shows the outputs for Toggle Bit I on DQ6.

Figure 9 shows the toggle bit algorithm. Figure 21 in

the “AC Characteristics” section shows the toggle bit

timing diagrams. Figure 22 shows the differences be-

tween DQ2 and DQ6 in graphical form. See also the

subsection on DQ2: Toggle Bit II.

December 14, 2005

Am29LV640MH/L

37

D A T A S H E E T

START

Read DQ7–DQ0

No

Toggle Bit

= Toggle?

Yes

No

DQ5 = 1?

Yes

Read DQ7–DQ0

Twice

Toggle Bit

= Toggle?

No

Yes

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Note: The system should recheck the toggle bit even if DQ5 = “1” because the toggle

bit may stop toggling as DQ5 changes to “1.” See the subsections on DQ6 and DQ2

for more information.

Figure 9. Toggle Bit Algorithm

whether the sector is actively erasing or is erase-sus-

DQ2: Toggle Bit II

pended. DQ6, by comparison, indicates whether the

device is actively erasing, or is in Erase Suspend, but

cannot distinguish which sectors are selected for era-

sure. Thus, both status bits are required for sector and

mode information. Refer to Table 12 to compare out-

puts for DQ2 and DQ6.

The “Toggle Bit II” on DQ2, when used with DQ6, indi-

cates whether a particular sector is actively erasing

(that is, the Embedded Erase algorithm is in progress),

or whether that sector is erase-suspended. Toggle Bit

II is valid after the rising edge of the final WE# pulse in

the command sequence.

Figure 9 shows the toggle bit algorithm in flowchart

form, and the section “DQ2: Toggle Bit II” explains the

algorithm. See also the RY/BY#: Ready/Busy# sub-

section. Figure 21 shows the toggle bit timing diagram.

DQ2 toggles when the system reads at addresses

within those sectors that have been selected for era-

sure. (The system may use either OE# or CE# to con-

trol the read cycles.) But DQ2 cannot distinguish

38

Am29LV640MH/L

December 14, 2005

D A T A S H E E T

Figure 22 shows the differences between DQ2 and

grammed to “0.” Only an erase operation can

change a “0” back to a “1.” Under this condition, the

device halts the operation, and when the timing limit

has been exceeded, DQ5 produces a “1.”

DQ6 in graphical form.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 9 for the following discussion. When-

ever the system initially begins reading toggle bit sta-

tus, it must read DQ7–DQ0 at least twice in a row to

determine whether a toggle bit is toggling. Typically,

the system would note and store the value of the tog-

gle bit after the first read. After the second read, the

system would compare the new value of the toggle bit

with the first. If the toggle bit is not toggling, the device

has completed the program or erase operation. The

system can read array data on DQ7–DQ0 on the fol-

lowing read cycle.

In all these cases, the system must write the reset

command to return the device to the reading the array

(or to erase-suspend-read if the device was previously

in the erase-suspend-program mode).

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the

system may read DQ3 to determine whether or not

erasure has begun. (The sector erase timer does not

apply to the chip erase command.) If additional

sectors are selected for erasure, the entire time-out

also applies after each additional sector erase com-

mand. When the time-out period is complete, DQ3

switches from a “0” to a “1.” If the time between addi-

tional sector erase commands from the system can be

assumed to be less than 50 µs, the system need not

monitor DQ3. See also the Sector Erase Command

Sequence section.

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the sys-

tem also should note whether the value of DQ5 is high

(see the section on DQ5). If it is, the system should

then determine again whether the toggle bit is tog-

gling, since the toggle bit may have stopped toggling

just as DQ5 went high. If the toggle bit is no longer

toggling, the device has successfully completed the

program or erase operation. If it is still toggling, the de-

vice did not completed the operation successfully, and

the system must write the reset command to return to

reading array data.

After the sector erase command is written, the system

should read the status of DQ7 (Data# Polling) or DQ6

(Toggle Bit I) to ensure that the device has accepted

the command sequence, and then read DQ3. If DQ3 is

“1,” the Embedded Erase algorithm has begun; all fur-

ther commands (except Erase Suspend) are ignored

until the erase operation is complete. If DQ3 is “0,” the

device will accept additional sector erase commands.

To ensure the command has been accepted, the sys-

tem software should check the status of DQ3 prior to

and following each subsequent sector erase com-

mand. If DQ3 is high on the second status check, the

last command might not have been accepted.

The remaining scenario is that the system initially de-

termines that the toggle bit is toggling and DQ5 has

not gone high. The system may continue to monitor

the toggle bit and DQ5 through successive read cy-

cles, determining the status as described in the previ-

ous paragraph. Alternatively, it may choose to perform

other system tasks. In this case, the system must start

at the beginning of the algorithm when it returns to de-

termine the status of the operation (top of Figure 9).

Table 12 shows the status of DQ3 relative to the other

status bits.

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program, erase, or

write-to-buffer time has exceeded a specified internal

pulse count limit. Under these conditions DQ5 pro-

duces a “1,” indicating that the program or erase cycle

was not successfully completed.

DQ1: Write-to-Buffer Abort

DQ1 indicates whether a Write-to-Buffer operation

was aborted. Under these conditions DQ1 produces a

“1”.

The

system

must

issue

the

Write-to-Buffer-Abort-Reset command sequence to re-

turn the device to reading array data. See Write Buffer

Programming section for more details.

The device may output a “1” on DQ5 if the system tries

to program a “1” to a location that was previously pro-

December 14, 2005

Am29LV640MH/L

39

D A T A S H E E T

Table 10. Write Operation Status

DQ7

DQ5

DQ2

Status

(Note 2)

DQ6

(Note 1)

DQ3

N/A

1

(Note 2)

DQ1 RY/BY#

Embedded Program Algorithm

Embedded Erase Algorithm

Program-Suspended

DQ7#

0

Toggle

0

No toggle

Toggle

0

Standard

Mode

N/A

Invalid (not allowed)

Data

1

0

Program

Suspend

Mode

Program-

Sector

Suspend

Non-Program

Read

Suspended Sector

Erase-Suspended

1

No toggle

Toggle

0

N/A

Toggle

N/A

Erase-

Sector

Suspend

Erase

Suspend

Mode

Non-EraseSuspended

Read

Data

Sector

Erase-Suspend-Program

(Embedded Program)

DQ7#

0

N/A

Busy (Note 3)

Abort (Note 4)

DQ7#

Toggle

0

N/A

0

1

0

Write-to-

Buffer

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program, Embedded Erase, or Write-to-Buffer operation has exceeded the

maximum timing limits. Refer to the section on DQ5 for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

3. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location.

4. DQ1 switches to ‘1’ when the device has aborted the write-to-buffer operation.

40

Am29LV640MH/L

December 14, 2005

D A T A S H E E T

ABSOLUTE MAXIMUM RATINGS

Storage Temperature, Plastic Packages . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Ambient Temperature with Power Applied . . . . . . . . . . . . . . . . . . –65°C to +125°C

Voltage with Respect to Ground

V_CC(Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V

V_IO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V

A9, OE#, ACC, and RESET# (Note 2) . . . . . . . . . . . . . .–0.5 V to +12.5 V

All other pins (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V_CC+0.5 V

Output Short Circuit Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions,

input or I/O pins may overshoot V_SSto –2.0 V for periods of up to 20 ns. Maximum

DC voltage on input or I/O pins is V_CC+0.5 V. See Figure 10. During voltage

transitions, input or I/O pins may overshoot to V_CC+2.0 V for periods up to 20 ns.

See Figure 11.

2. Minimum DC input voltage on pins A9, OE#, ACC, and RESET# is –0.5 V. During

voltage transitions, A9, OE#, ACC, and RESET# may overshoot V_SSto –2.0 V for

periods of up to 20 ns. See Figure 10. Maximum DC input voltage on pin A9, OE#,

ACC, and RESET# is +12.5 V which may overshoot to +14.0 V for periods up to

20 ns.

3. No more than one output may be shorted to ground at a time. Duration of the short

circuit should not be greater than one second.

Stresses above those listed under “Absolute Maximum Ratings” may cause permanent

damage to the device. This is a stress rating only; functional operation of the device

at these or any other conditions above those indicated in the operational sections of

this data sheet is not implied. Exposure of the device to absolute maximum rating con-

ditions for extended periods may affect device reliability.

20 ns

V_CC

+2.0 V

+0.8 V

V_CC

+0.5 V

–0.5 V

–2.0 V

2.0 V

20 ns

Figure 10. Maximum Negative

Overshoot Waveform

Figure 11. Maximum Positive

Overshoot Waveform

OPERATING RANGES

Industrial (I) Devices

Ambient Temperature (T_A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

Supply Voltages

V_CC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.7–3.6 V

V_IO(Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.65–3.6 V

Notes:

1. Operating ranges define those limits between which the functionality of the device

is guaranteed.

2. See Ordering Information section for valid V_CC/V_IOrange combinations. The I/Os

will not operate at 3 V when V_IO= 1.8 V.

December 14, 2005

Am29LV640MH/L

41

D A T A S H E E T

DC CHARACTERISTICS

CMOS Compatible

Parameter

Symbol

Parameter Description

(Notes)

Test Conditions

Min

Typ

Max

Unit

V_IN= V_SSto V_CC

V_CC= V_{CC max}

,

I_LI

Input Load Current (1)

±1.0

µA

I_LIT

I_LR

A9, ACC Input Load Current

Reset Leakage Current

V_CC= V_{CC max}; A9 = 12.5 V

V_CC= V_{CC max}; RESET# = 12.5 V

35

µA

V

_OUT= V_SSto V_CC

,

I_LO

Output Leakage Current

±1.0

µA

V_CC= V_{CC max}

5 MHz

1 MHz

15

30

20

50

I_CC1

V_CCActive Read Current (2, 3)

CE# = V_IL,OE# = V_IH,

mA

I_CC2

I_CC3

I_CC4

V_CCInitial Page Read Current (2, 3)

V_CCIntra-Page Read Current (2, 3)

V_CCActive Write Current (3, 4)

CE# = V_IL,OE# = V_IH

mA

10

50

20

60

CE#, RESET# = V_CC± 0.3 V,

WP# = V_IH

I_CC5

I_CC6

I_CC7

V_CCStandby Current (3)

V_CCReset Current (3)

1

5

µA

RESET# = V_SS± 0.3 V, WP# = V_IH

V_IH= V_CC± 0.3 V;

Automatic Sleep Mode (3, 5)

V

_IL= V_SS± 0.3 V, WP# = V_IH

V_IL1

V_IH1

V_IL2

V_IH2

V_HH

Input Low Voltage 1(6, 7)

–0.5

1.9

0.8

V

_CC+ 0.5

Input High Voltage 1 (6, 7)

Input Low Voltage 2 (6, 8)

0.3 x V_IO

V_IO+ 0.5

12.5

–0.5

1.9

Input High Voltage 2 (6, 8)

Voltage for ACC Program Acceleration

V_CC= 2.7 –3.6 V

11.5

Voltage for Autoselect and Temporary Sector

Unprotect

V_ID

11.5

12.5

V

V_OL

V_OH1

V_OH2

V_LKO

0.15 x V_IO

Output Low Voltage (9)

I_OL= 4.0 mA, V_CC= V_{CC min}= V_IO

I_OH= –2.0 mA, V_CC= V_{CC min}= V_IO

I_OH= –100 µA, V_CC= V_{CC min}= V_IO

V

0.85 V_IO

V_IO–0.4

2.3

Output High Voltage

Low V_CCLock-Out Voltage (10)

2.5

Notes:

1. On the WP#/ACC pin only, the maximum input load current when

6. If V_IO< V_CC, maximum V_ILfor CE# and DQ I/Os is 0.3 V_IO. If V_IO

<

WP# = V_ILis 5.0 µA.

V_CC, minimum V_IHfor CE# and DQ I/Os is 0.7 V_IO. Maximum V_IH

for these connections is V_IO+ 0.3 V.

7. V_CCvoltage requirements.

8. V_IOvoltage requirements.

9. Includes RY/BY#

2. The I_CCcurrent listed is typically less than 2 mA/MHz, with OE# at

V_IH.

3. Maximum I_CCspecifications are tested with V_CC= V_CCmax.

4. I_CCactive while Embedded Erase or Embedded Program is in

progress.

10. Not 100% tested.

5. Automatic sleep mode enables the low power mode when

addresses remain stable for t_ACC+ 30 ns.

42

Am29LV640MH/L

December 14, 2005

D A T A S H E E T

TEST CONDITIONS

Table 11. Test Specifications

Test Condition All Speeds

1 TTL gate

3.3 V

Unit

Output Load

2.7 kΩ

Output Load Capacitance, C_L

(including jig capacitance)

Device

Under

Test

30

pF

Input Rise and Fall Times

Input Pulse Levels

5

ns

V

0.0–3.0

C

L

6.2 kΩ

Input timing measurement

reference levels (See Note)

1.5

V

Output timing measurement

reference levels

0.5 V_IO

Note: If V_IO< V_CC, the reference level is 0.5 V_IO.

Note: Diodes are IN3064 or equivalent

Figure 12. Test Setup

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Changing, State Unknown

Don’t Care, Any Change Permitted

Does Not Apply

Center Line is High Impedance State (High Z)

3.0 V

1.5 V

0.5 V_IOV

Input

Measurement Level

Output

0.0 V

Note: If V_IO< V_CC, the input measurement reference level is 0.5 V_IO.

Figure 13. Input Waveforms and

Measurement Levels

December 14, 2005

Am29LV640MH/L

43

D A T A S H E E T

AC CHARACTERISTICS

Read-Only Operations

Parameter

Speed Options

Description

Test Setup

101,

101R

JEDEC Std.

90R

90

112R

112

120R

120

Unit

ns

t_AVAV

t_AVQV

t_ELQV

t_RC

Read Cycle Time (Note 1)

Address to Output Delay

Min

100

110

CE#, OE# =

t_ACC

Max

V_IL

90

100

120

ns

t_CE

t_PACC

t_OE

OE# = V_IL

Chip Enable to Output Delay

Page Access Time

Max

90

25

100

30

ns

30

40

30

40

t_GLQV

t_EHQZ

t_GHQZ

Output Enable to Output Delay

Chip Enable to Output High Z (Note 1)

Output Enable to Output High Z (Note 1)

30

t_DF

16

t_DF

Output Hold Time From Addresses, CE# or

OE#, Whichever Occurs First

t_AXQX

t_OH

Min

0

ns

Read

Output Enable Hold

Time (Note 1)

t_OEH

Toggle and

10

Data# Polling

Notes:

1. Not 100% tested.

2. See Figure 12 and Table 13 for test specifications.

3. AC Specifications listed are tested with V_IO= V_CC. Contact AMD for

^{information on AC operation with V}_IO≠ V_CC

.

t_RC

Addresses Stable

t_ACC

Addresses

CE#

t_RH

t_DF

t_OE

OE#

t_OEH

WE#

t_CE

t_OH

Output Valid

HIGH Z

Outputs

RESET#

RY/BY#

0 V

Figure 14. Read Operation Timings

44

Am29LV640MH/L

December 14, 2005

D A T A S H E E T

AC CHARACTERISTICS

Same Page

A21

-

A2

A0

A1

Ad

Aa

t_ACC

Ab

t_PACC

Ac

t_PACC

Data Bus

Qa

Qb

Qc

Qd

CE#

OE#

* Figure shows device in word mode. Addresses are A1–A-1 for byte mode.

Figure 15. Page Read Timings

December 14, 2005

Am29LV640MH/L

45

D A T A S H E E T

AC CHARACTERISTICS

Hardware Reset (RESET#)

Parameter

JEDEC

Std.

Description

All Speed Options

Unit

RESET# Pin Low (During Embedded Algorithms) to

Read Mode (See Note)

t_Ready

Max

20

μs

RESET# Pin Low (NOT During Embedded

Algorithms) to Read Mode (See Note)

t_Ready

500

ns

t_RP

t_RH

t_RPD

t_RB

RESET# Pulse Width

Min

500

50

20

0

ns

µs

ns

Reset High Time Before Read (See Note)

RESET# Input Low to Standby Mode

RY/BY# Output High to CE#, OE# pin Low

Notes:

1. Not 100% tested.

2. AC Specifications listed are tested with V_IO= V_CC. Contact AMD for information on AC operation with V_IO≠ V_CC

.

RY/BY#

CE#f, OE#

RESET#

t_RH

t_RP

t_Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

t_Ready

RY/BY#

t_RB

CE#f, OE#

RESET#

t_RP

Figure 16. Reset Timings

46

Am29LV640MH/L

December 14, 2005

D A T A S H E E T

AC CHARACTERISTICS

Erase and Program Operations

Parameter

Speed Options

101,

112,

120,

JEDEC

t_AVAV

Std.

t_WC

t_AS

Description

90R

101R

112R

120R Unit

Write Cycle Time (Note 1)

Address Setup Time

Min

90

100

110

120

ns

t_AVWL

0

15

45

0

Address Setup Time to OE# low during toggle bit

polling

t_ASO

t_AH

Min

ns

t_WLAX

Address Hold Time

Address Hold Time From CE# or OE# high

during toggle bit polling

t_AHT

t_DVWH

t_WHDX

t_DS

t_DH

Data Setup Time

Min

45

0

ns

Data Hold Time

t_OEPH

Output Enable High during toggle bit polling

20

Read Recovery Time Before Write

(OE# High to WE# Low)

t_GHWL

Min

0

ns

t_ELWL

t_WHEH

t_WLWH

t_WHDL

t_CS

t_CH

CE# Setup Time

Min

Typ

0

ns

µs

sec

ns

µs

ns

µs

CE# Hold Time

t_WP

Write Pulse Width

35

30

352

11

22

8.8

t_WPH

Write Pulse Width High

Write Buffer Program Operation (Notes 2, 3)

Per Byte

Per Word

Per Byte

Per Word

Byte

Effective Write Buffer Program

Operation (Notes 2, 4)

Accelerated Effective Write Buffer

Program Operation (Notes 2, 4)

t_WHWH1

17.6

100

90

Single Word/Byte Program

Operation (Note 2, 5)

Typ

Word

Byte

Single Word/Byte Accelerated

Programming Operation (Note 2, 5)

Word

90

t_WHWH2

t_WHWH2Sector Erase Operation (Note 2)

Typ

Min

Max

0.5

250

50

t_VHH

t_VCS

t_BUSY

t_POLL

V_HHRise and Fall Time (Note 1)

V_CCSetup Time (Note 1)

WE# High to RY/BY# Low

90

100

110

120

Program Valid Before Status Polling (Note 7)

4

Notes:

1. Not 100% tested.

6. AC Specifications listed are tested with V_IO= V_CC. Contact AMD

for information on AC operation with V_IOV_CC

7. When using the program suspend/resume feature, if the

suspend command is issued within t_POLL, t_POLLmust be fully

re-applied upon resuming the programming operation. If the

suspend command is issued after t_POLL, t_POLLis not required

again prior to reading the status bits upon resuming.

≠

.

2. See the “Erase and Programming Performance” section for more

information.

3. For 1–16 words/1–32 bytes programmed.

4. Effective write buffer specification is based upon a

16-word/32-byte write buffer operation.

5. Word/Byte programming specification is based upon a single

word/byte programming operation not utilizing the write buffer.

December 14, 2005

Am29LV640MH/L

47

D A T A S H E E T

AC CHARACTERISTICS

Program Command Sequence (last two cycles)

Read Status Data (last two cycles)

t_AS

PA

t_WC

Addresses

555h

PA

t_AH

CE#

OE#

t_CH

t_POLL

t_WP

WE#

Data

t_WPH

t_WHWH1

t_CS

t_DS

t_DH

PD

D_OUT

A0h

Status

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. PA = program address, PD = program data, D_OUTis the true data at the program address.

ILLUSTRATION SHOWS DEVICE IN WORD MODE.

Figure 17. Program Operation Timings

V_HH

V_ILor V_IH

ACC

t_VHH

Figure 18. Accelerated Program Timing Diagram

48

Am29LV640MH/L

December 14, 2005

D A T A S H E E T

AC CHARACTERISTICS

Erase Command Sequence (last two cycles)

Read Status Data

VA

t_AS

SA

t_WC

VA

Addresses

CE#

2AAh

555h for chip erase

t_AH

t_CH

OE#

t_WP

WE#

t_WPH

t_WHWH2

t_CS

t_DS

t_DH

In

Data

Complete

55h

30h

Progress

10 for Chip Erase

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”.

2. Illustration shows device in word mode.

Figure 19. Chip/Sector Erase Operation Timings

December 14, 2005

Am29LV640MH/L

49

D A T A S H E E T

AC CHARACTERISTICS

t_RC

VA

Addresses

VA

t_POLL

t_ACC

t_CE

CE#

t_CH

t_OE

OE#

t_OEH

t_DF

WE#

t_OH

High Z

DQ15 and DQ7

Valid Data

Complement

True

DQ14–DQ8, DQ6–DQ0

RY/BY#

Status Data

True

Valid Data

Status Data

t_BUSY

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data

read cycle.

Figure 20. Data# Polling Timings

(During Embedded Algorithms)

50

Am29LV640MH/L

December 14, 2005

D A T A S H E E T

AC CHARACTERISTICS

t_AHT

t_AS

Addresses

t_AHT

t_ASO

CE#

t_OEH

WE#

t_CEPH

t_OEPH

OE#

t_DH

Valid Data

t_OE

Valid

Status

Valid

Status

Valid

Status

DQ6/DQ2

RY/BY#

Valid Data

(first read)

(second read)

(stops toggling)

Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status

read cycle, and array data read cycle.

Figure 21. Toggle Bit Timings (During Embedded Algorithms)

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

Erase

Erase Suspend

Read

Erase

WE#

Erase

Erase Suspend

Read

Suspend

Program

Complete

DQ6

DQ2

Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle

DQ2 and DQ6.

Figure 22. DQ2 vs. DQ6

December 14, 2005

Am29LV640MH/L

51

D A T A S H E E T

AC CHARACTERISTICS

Temporary Sector Unprotect

Parameter

JEDEC

Std

Description

All Speed Options

Unit

t_VIDR

V_IDRise and Fall Time (See Note)

Min

500

ns

RESET# Setup Time for Temporary Sector

Unprotect

t_RSP

4

µs

Notes:

1. Not 100% tested.

2. AC Specifications listed are tested with V_IO= V_CC. Contact AMD for information on AC operation with V_IO≠ V_CC

.

V_ID

RESET#

V_SS, V_IL,

or V_IH

V_SS, V_IL,

or V_IH

t_VIDR

Program or Erase Command Sequence

CE#

WE#

t_RRB

t_RSP

RY/BY#

Figure 23. Temporary Sector Group Unprotect Timing Diagram

52

Am29LV640MH/L

December 14, 2005

D A T A S H E E T

AC CHARACTERISTICS

V

ID

IH

V

RESET#

SA, A6,

A3, A2,

A1, A0

Valid*

Sector Group Protect or Unprotect

60h 60h

Valid*

Status

Verify

40h

Data

Sector Group Protect: 150 µs,

Sector Group Unprotect: 15 ms

1 µs

CE#

WE#

OE#

Note: For sector group protect, A6:A0 = 0xx0010. For sector group unprotect, A6:A0 = 1xx0010.N

Figure 24. Sector Group Protect and Unprotect Timing Diagram

December 14, 2005

Am29LV640MH/L

53

D A T A S H E E T

AC CHARACTERISTICS

Alternate CE# Controlled Erase and Program Operations

Parameter

Speed Options

101, 112, 120,

JEDEC

t_AVAV

Std.

t_WC

t_AS

Description

90R 101R 112R 120R Unit

Write Cycle Time (Note 1)

Address Setup Time

Address Hold Time

Data Setup Time

Data Hold Time

Min

90

100

110

120

ns

t_AVWL

t_ELAX

t_DVEH

t_EHDX

0

45

0

t_AH

t_DS

t_DH

Read Recovery Time Before Write

(OE# High to WE# Low)

t_GHEL

Min

0

ns

t_WLEL

t_EHWH

t_ELEH

t_EHEL

t_WS

t_WH

t_CP

WE# Setup Time

Min

Typ

0

ns

µs

WE# Hold Time

CE# Pulse Width

45

30

352

11

22

8.8

t_CPH

CE# Pulse Width High

Write Buffer Program Operation (Notes 2, 3)

Per Byte

Effective Write Buffer Program

Operation (Notes 2, 4)

Per Word

Per Byte

Per Word

Byte

Accelerated Effective Write Buffer

Program Operation (Notes 2, 4)

17.6

100

90

t_WHWH1

Single Word/Byte Program

Operation (Note 2, 5)

Typ

Word

Single Word/Byte Accelerated

Programming Operation (Note 2,

5)

Byte

Typ

Word

90

µs

t_WHWH2

t_WHWH2Sector Erase Operation (Note 7)

Typ

Min

Max

0.5

50

4

sec

ns

t_RH

RESET# High Time Before Write

Program Valid Before Status Polling (Note 7)

t_POLL

µs

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for

more information.

6. AC Specifications listed are tested with V_IO= V_CC. Contact

^{AMD for information on AC operation with V}_IO≠ V_CC

.

3. For 1–16 words/1–32 bytes programmed.

7. When using the program suspend/resume feature, if the

suspend command is issued within t_POLL, t_POLLmust be fully

re-applied upon resuming the programming operation. If the

suspend command is issued after t_POLL, t_POLLis not

required again prior to reading the status bits upon

resuming.

4. Effective write buffer specification is based upon a

16-word/32-byte write buffer operation.

5. Word/Byte programming specification is based upon a

single word/byte programming operation not utilizing the

write buffer.

54

Am29LV640MH/L

December 14, 2005

D A T A S H E E T

AC Characteristics

555 for program

2AA for erase

PA for program

SA for sector erase

555 for chip erase

Data# Polling

Addresses

PA

t_WC

t_AS

t_AH

t_WH

WE#

OE#

t_POLL

t_GHEL

t_{WHWH1 or 2}

t_CP

CE#

t_WS

t_CPH

t_DS

t_BUSY

t_DH

DQ7#,

DQ15

D_OUT

Data

t_RH

A0 for program

55 for erase

PD for program

30 for sector erase

10 for chip erase

RESET#

RY/BY#

Notes:

1. Figure indicates last two bus cycles of a program or erase operation.

2. PA = program address, SA = sector address, PD = program

data.

3. DQ7# is the complement of the data written to the device.

D_OUTis the data written to the device.

4. Illustration shows device in word mode.

Figure 25. Alternate CE# Controlled Write (Erase/Program)

Operation Timings

December 14, 2005

Am29LV640MH/L

55

D A T A S H E E T

ERASE AND PROGRAMMING PERFORMANCE

Parameter

Typ (Note 1) Max (Note 2)

Unit

Comments

Sector Erase Time

0.5

15

sec

Excludes 00h

programming prior to

erasure (Note 6)

Chip Erase Time

64

128

sec

Byte

Word

Byte

100

90

800

720

1800

57

µs

Single Word/Byte Program Time (Note 3)

Accelerated Single Word/Byte Program Time

(Note 3)

Word

90

Total Write Buffer Program Time (Note 4)

352

11

Excludes system level

overhead (Note 7)

Per Byte

Per Word

Effective Write Buffer Program Time (Note 5)

22

113

Total Accelerated Effective Write Buffer

Program Time (Note 4)

282

1560

µs

Per Byte

Per Word

8.8

17.6

92

49

98

µs

Effective Accelerated Write Buffer Program

Time (Note 4)

Chip Program Time, using the Write Buffer

170

sec

Notes:

1. Typical program and erase times assume the following

conditions: 25°C, 3.0 V V_CC. Programming specifications

assume that all bits are programmed to 00h.

5. Effective write buffer specification is calculated on a

per-word/per-byte basis for a 16-word/32-byte write buffer

operation.

6. In the pre-programming step of the Embedded Erase

algorithm, all bits are programmed to 00h before erasure.

2. Maximum values are measured at V_CC= 3.0 V, worst case

temperature. Maximum values are valid up to and including

100,000 program/erase cycles.

7. System-level overhead is the time required to execute the

command sequence(s) for the program command. See

Tables 8 and 9 for further information on command

definitions.

3. Word/Byte programming specification is based upon a

single word/byte programming operation not utilizing the

write buffer.

8. The device has a minimum erase and program cycle

endurance of 100,000 cycles.

4. For 1-16 words or 1-32 bytes programmed in a single write

buffer programming operation.

LATCHUP CHARACTERISTICS

Description

Min

Max

Input voltage with respect to V_SSon all pins except I/O pins

(including A9, OE#, and RESET#)

–1.0 V

12.5 V

Input voltage with respect to V_SSon all I/O pins

V_CCCurrent

–1.0 V

V_CC+ 1.0 V

+100 mA

–100 mA

Note: Includes all pins except V_CC. Test conditions: V_CC= 3.0 V, one pin at a time.

TSOP PIN AND BGA PACKAGE CAPACITANCE

Parameter Symbol

Parameter Description

Test Setup

Typ

6

Max

7.5

5.0

12

Unit

pF

TSOP

C_IN

Input Capacitance

V_IN= 0

V_OUT= 0

V_IN= 0

Fine-pitch BGA

TSOP

4.2

8.5

5.4

7.5

3.9

C_OUT

C_IN2

Output Capacitance

Fine-pitch BGA

TSOP

6.5

9

Control Pin Capacitance

Fine-pitch BGA

4.7

Notes:

1. Sampled, not 100% tested.

2. Test conditions T_A= 25°C, f = 1.0 MHz.

DATA RETENTION

Parameter Description

Test Conditions

150°C

Min

10

Unit

Years

Minimum Pattern Data Retention Time

125°C

20

56

Am29LV640MH/L

December 14, 2005

D A T A S H E E T

PHYSICAL DIMENSIONS

TS056/TSR056—56-Pin Standard and Reverse Pinout

Thin Small Outline Package (TSOP)

NOTES:

PACKAGE

TS/TSR 56

JEDEC

MO-142 (B) EC

1

CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm).

(DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982.)

SYMBOL

MIN.

---

NOM.

---

MAX.

1.20

0.15

1.05

0.23

0.27

0.16

0.21

2

3

4

PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP).

A

A1

A2

b1

b

PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN), INK OR LASER MARK.

0.05

0.95

0.17

0.10

---

1.00

0.20

0.22

---

TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS

DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE

LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE.

5

6

DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE

MOLD PROTUSION IS 0.15 mm PER SIDE.

c1

c

---

DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE

DAMBAR PROTUSION SHALL BE 0.08 mm TOTAL IN EXCESS OF b

DIMENSION AT MAX MATERIAL CONDITION. MINIMUM SPACE BETWEEN

PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 mm.

D

19.90

18.30

20.00

18.40

20.20

18.50

D1

E

e

13.90

14.00

14.10

7

THESE DIMESIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN

0.10 mm AND 0.25 mm FROM THE LEAD TIP.

0.50 BASIC

L

0.50

0˚

0.60

3˚

0.70

5˚

8. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED FROM THE

SEATING PLANE.

O

R

N

0.08

---

0.20

9

DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.

56

3160\38.10A

December 14, 2005

Am29LV640MH/L

57

D A T A S H E E T

PHYSICAL DIMENSIONS

LAA064—64-Ball Fortified Ball Grid Array (FBGA) 13 x 11 mm Package

58

Am29LV640MH/L

December 14, 2005

D A T A S H E E T

REVISION SUMMARY

Revision A (March 19, 2002)

Revision D+1 (September 10, 2002)

Initial release as abbreviated Advance Information

data sheet. This document contains information that

was previously released in publication number 25301.

Product Selector Guide

Added Note 2.

Ordering Information

Added Note 1.

The package marking for the Fortified BGA option has

been updated.

Sector Erase Command Sequence

Deleted statement that describes the outcome of

when the Embedded Erase operation is in progress.

Physical Dimensions

Added drawing that shows both TS056 and TSR056

specifications.

Revision E (December 5, 2002)

Product Selector Guide and Read-Only

Characteristics

Revision B (April 26, 2002)

Expanded data sheet to full specification version.

Added a 30 ns option to t_PACCand t_OEstandard for the

112R and 120R speed options.

Revision C (May 23, 2002)

Customer Lockable: SecSi Sector NOT

Programmed or Protected at the factory.

Changed packaging from 63-ball FBGA to 64-ball For-

tified BGA. Changed Block Diagram: Moved V_IOfrom

RY/BY# to Input/Output Buffers. Changed note about

WP#/ACC pin to indicate internal pullup to V_CC. Modi-

fied Table 4: Sector Group Protection/Unprotection Ad-

dress Table. Changed 47h Address data from 0004h

to 0001h in Table 9.

Added second bullet, SecSi sector-protect verify text

and figure 3.

SecSi Sector Flash Memory Region, and Enter

SecSi Sector/Exit SecSi Sector Command

Sequence

Noted that the ACC function and unlock bypass modes

are not available when the SecSi sector is enabled.

Revision D (August 8, 2002)

Alternate CE# Controlled Erase and Program

Operations

Byte/Word Program Command Sequence, Sector

Erase Command Sequence, and Chip Erase Com-

mand Sequence

Added t_RHparameter to table.

Erase and Program Operations

Noted that the SecSi Sector, autoselect, and CFI

functions are unavailable when a program or erase

operation is in progress.

Added t_BUSYparameter to table.

TSOP and BGA PIN Capacitance

Common Flash Memory Interface (CFI)

Added the FBGA package.

Changed CFI website address

Program Suspend/Program Resume Command

Sequence

Figure 6. Program Suspend/Program Resume

Changed 15 μs typical to maximum and added 5 μs

typical.

Change wait time to 15 μs.

CMOS Compatible

Erase Suspend/Erase Resume Commands

Added I_LRrow to table. Changed V_IH1and V_IH2mini-

mum to 1.9. Removed typos in notes.

Changed typical from 20 μs to 5 μs and added a maxi-

mum of 20 μs.

Hardware Reset, CMOS Tables, Erase and Program

Operations, Temporary Sector Unprotect, and

Alternate CE# Controlled Erase and Program

Operations

Special package handling instructions

Modified the special handling wording.

DC Characteristics table

Added Note.

Deleted the Iacc specification row.

Revision E+1 (February 16, 2003)

CFI

Distinctive Characteristics

Changed text in the third paragraph of CFI to read

“reading array data.”

Corrected performance characteristics.

December 14, 2005

Am29LV640MH/L

59

D A T A S H E E T

DC Characteristics table

Product Selector Guide

Added note 2.

Corrected note reference number on V_OLspecification.

Ordering Information

Hardware Reset (RESET#)

Corrected Valid Combinations table.

Added t_RBspecification to table.

Added Note.

Revision F+1 (February 17, 2004)

AC Characteristics

Erase Suspend/Erase Resume Commands

Removed 90, 90R speed option. Added Note

Added note (last paragraph) in reference to erase op-

eration.

Input values in the t_WHWH1 and t_WHWH2 parameters in

the Erase and Program Options table that were previ-

ously TBD. Also, added note 5.

AC Characteristics - Erase and Program

Operations, and Alternate CE# Controlled Erase

and Program Operations

Input values in the t_WHWH1 and t_WHWH2 parameters in

the Alternate CE# Controlled Erase and Program Op-

tions table that were previously TBD. Also, added note

5.

Added t_POLLinformation.

AC Characteristics - Program Operation Timings,

Data# Polling Timings, and Alternate CE#

Controlled Write (Erase/Program) Operation

Timings

Erase and Programming Performance

Input values into table that were previously TBD.

Added notes 3 and 4.

Updated figures to show t_POLLinformation.

Trademarks

Revision E+2 (June 11, 2003)

Updated.

Ordering Information

Added 90R speed grade, modified note.

Revision F+2 (August 23, 2004)

Added Max programming specifications.

Erase and Programming Performance

Modified table, supplied values for Typical.

Added notation referencing superseding documenta-

tion.

Revision F (August 14, 2003)

Revision F+3 (December 14, 2005)

Global

Converted document to new Spansion template.

Global

Ordering Information

This product has been retired and is not available for

designs. For new and current designs, S29GL064A

supersedes Am29LV640M H/L and is the factory-rec-

ommended migration path. Please refer to the

S29GL064A datasheet for specifications and ordering

information. Availability of this document is retained for

reference and historical purposes only.

Added note for ordering and marking information re-

lated to “N” (factory-protected SecSi Sector) devices.

Command Definitions

Corrected Program Erase/Suspend addressing from

BA to don’t care.

Trademarks

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

ExpressFlash is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

60

Am29LV640MH/L

December 14, 2005


型号：	L640MH01PI
厂家：	AMD
描述：	64 Megabit (4 M x 16-Bit/8 M x 8-Bit) MirrorBit⑩ 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O⑩ Control 64兆位（4M ×16位/ 8的M× 8位） MirrorBit⑩ 3.0伏只统一部门快闪记忆体与VersatileI / O⑩控制
文件：	总62页 (文件大小：1108K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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