LV640MB [AMD]
64 Megabit (4 M x 16-Bit) MirrorBit⑩ 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O⑩ Control; 64兆位（4M ×16位） MirrorBit⑩ 3.0伏只统一部门快闪记忆体与VersatileI / O⑩控制
| 型号： | LV640MB |
| 厂家： | 
AMD |
| 描述： | 64 Megabit (4 M x 16-Bit) MirrorBit⑩ 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O⑩ Control |
| 文件： | 总60页 (文件大小：1120K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Am29LV641MH/L
Data Sheet
RETIRED
PRODUCT
This product has been retired and is not available for designs. For new and current designs,
S29GL064A supersedes Am29LV641M H/L and is the factory-recommended migration path. Please
refer to the S29GL064A datasheet for specifications and ordering information. Availability of this
document is retained for reference and historical purposes only.
April 2005
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that
originally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appro-
priate, and changes will be noted in a revision summary.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number 25261 Revision B Amendment +10 Issue Date December 21, 2005
THIS PAGE LEFT INTENTIONALLY BLANK.
Am29LV641MH/L
64 Megabit (4 M x 16-Bit) MirrorBit™ 3.0 Volt-only
Uniform Sector Flash Memory with VersatileI/O™ Control
This product has been retired and is not available for designs. For new and current designs, S29GL064A supersedes Am29LV641M H/L and is the factory-recommended migration path.
Please refer to the S29GL064A datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only.
ARCHITECTURAL ADVANTAGES
Low power consumption (typical values at 3.0 V, 5
MHz)
Single power supply operation
— 30 mA typical active read current
— 50 mA typical erase/program current
— 1 µA typical standby mode current
— 3 V for read, erase, and program operations
VersatileI/O™ control
— Device generates data output voltages and tolerates
data input voltages on CE# and the DQ inputs/outputs
as determined by the voltage on the VIO pin; operates
from 1.65 to 3.6 V
Package options
— 48-pin TSOP
SOFTWARE & HARDWARE FEATURES
Manufactured on 0.23 µm MirrorBit process
technology
Software features
— Program Suspend & Resume: read other sectors
before programming operation is completed
SecSi™ (Secured Silicon) Sector region
— 128-word sector for permanent, secure identification
through an 8-word random Electronic Serial Number,
accessible through a command sequence
— Erase Suspend & Resume: read/program other
sectors before an erase operation is completed
— Data# polling & toggle bits provide status
— May be programmed and locked at the factory or by
the customer
— Unlock Bypass Program command reduces overall
multiple-word programming time
Flexible sector architecture
— CFI (Common Flash Interface) compliant: allows host
system to identify and accommodate multiple flash
devices
— One hundred twenty-eight 32 Kword sectors
Compatibility with JEDEC standards
— Provides pinout and software compatibility for
single-power supply flash, and superior inadvertent
write protection
Hardware features
— Sector Group Protection: hardware-level method of
preventing write operations within a sector group
— Temporary Sector Unprotect: VID-level method of
changing code in locked sectors
Minimum 100,000 erase cycle guarantee per sector
20-year data retention at 125°C
— ACC (high voltage) input accelerates programming
time for higher throughput during system production
PERFORMANCE CHARACTERISTICS
— Write Protect input (WP#) protects first or last sector
regardless of sector protection settings
High performance
— 90 ns access time
— Hardware reset input (RESET#) resets device
— 25 ns page read times
— 0.5 s typical sector erase time
— 22 µs typical effective write buffer word programming
time: 16-word write buffer reduces overall
programming time for multiple-word updates
— 4-word page read buffer
— 16-word write buffer
This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication# 25261
Amendment/+10
Rev: B
Issue Date: December 21, 2005
Refer to AMD’s Website (www.amd.com) for the latest information.
D A T A S H E E T
GENERAL DESCRIPTION
The Am29LV641MH/L is a 64 Mbit, 3.0 volt single
power supply flash memory devices organized as
4,194,304 words. The devices have a 16-bit wide data
bus, and can be programmed either in the host system
or in standard EPROM programmers.
Refer to the Ordering Information section for valid VIO
options.
Hardware data protection measures include a low
VCC detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of sectors of memory.
This can be achieved in-system or via programming
equipment.
An access time of 90, 100, 110, or 120 ns is available.
Note that each access time has a specific operating
voltage range (VCC) and an I/O voltage range (VIO), as
specified in the Product Selector Guide and the Order-
ing Information sections. The device is offered in a
48-pin TSOP package. Each device has separate chip
enable (CE#), write enable (WE#) and output enable
(OE#) controls.
The Erase Suspend/Erase Resume feature allows
the host system to pause an erase operation in a given
sector to read or program any other sector and then
complete the erase operation. The Program Sus-
pend/Program Resume feature enables the host sys-
tem to pause a program operation in a given sector to
read any other sector and then complete the program
operation.
Each device requires only a single 3.0 volt power
supply for both read and write functions. In addition to
a VCC input, a high-voltage accelerated program
(ACC) input provides shorter programming times
through increased current. This feature is intended to
facilitate factory throughput during system production,
but may also be used in the field if desired.
The hardware RESET# pin terminates any operation
in progress and resets the device, after which it is then
ready for a new operation. The RESET# pin may be
tied to the system reset circuitry. A system reset would
thus also reset the device, enabling the host system to
read boot-up firmware from the Flash memory device.
The device is entirely command set compatible with
the JEDEC single-power-supply Flash standard.
Commands are written to the device using standard
microprocessor write timing. Write cycles also inter-
nally latch addresses and data needed for the pro-
gramming and erase operations.
The device reduces power consumption in the
standby mode when it detects specific voltage levels
on CE# and RESET#, or when addresses have been
stable for a specified period of time.
The sector erase architecture allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
The SecSi™ (Secured Silicon) Sector provides a
128-word area for code or data that can be perma-
nently protected. Once this sector is protected, no fur-
ther changes within the sector can occur.
Device programming and erasure are initiated through
command sequences. Once a program or erase oper-
ation has begun, the host system need only poll the
DQ7 (Data# Polling) or DQ6 (toggle) status bits to de-
termine whether the operation is complete. To facilitate
programming, an Unlock Bypass mode reduces com-
mand sequence overhead by requiring only two write
cycles to program data instead of four.
The Write Protect (WP#) feature protects the first or
last sector by asserting a logic low on the WP# pin.
The protected sector will still be protected even during
accelerated programming.
AMD MirrorBit flash technology combines years of
Flash memory manufacturing experience to produce
the highest levels of quality, reliability and cost effec-
tiveness. The device electrically erases all bits within a
sector simultaneously via hot-hole assisted erase. The
data is programmed using hot electron injection.
The VersatileI/O™ (VIO) control allows the host sys-
tem to set the voltage levels that the device generates
and tolerates on the CE# control input and DQ I/Os to
the same voltage level that is asserted on the VIO pin.
2
Am29LV641MH/L
December 21, 2005
D A T A S H E E T
MIRRORBIT 64 MBIT DEVICE FAMILY
Device
Bus
Sector Architecture
Packages
VIO
RY/BY#
WP#, ACC
WP# Protection
48-pin TSOP (std. & rev. pinout),
63-ball FBGA
LV065MU
x8
Uniform (64K-byte)
Yes
Yes
ACC only
No WP#
Boot (8x8K-byte
@ top & bottom)
48-pin TSOP, 63-ball Fine-pitch BGA,
64-ball Fortified BGA
2 x 8 Kbyte top
or bottom
LV640MT/B
LV640MH/L
LV641MH/L
LV640MU
x8/x16
x8/x16
x16
No
Yes
Yes
Yes
Yes
Yes
No
WP#/ACC pin
WP#/ACC pin
56-pin TSOP (std. & rev. pinout),
64 Fortified BGA
1 x 64 Kbyte
high or low
Uniform (64K-byte)
Uniform (32K-word)
Uniform (32K-word)
Separate WP# 1 x 32 Kword top
48-pin TSOP (std. & rev. pinout)
and ACC pins
or bottom
63-ball Fine-pitch BGA,
64 Ball Fortified BGA
x16
Yes
ACC only
No WP#
RELATED DOCUMENTS
To download related documents, click on the following
links or go to www.amd.com→Flash Memory→Prod-
uct Information→MirrorBit→Flash Information→Tech-
nical Documentation.
Implementing a Common Layout for AMD MirrorBit
and Intel StrataFlash Memory Devices
AMD MirrorBit™ White Paper
Migrating from Single-byte to Three-byte Device IDs
MirrorBit™ Flash Memory Write Buffer Programming
and Page Buffer Read
December 21, 2005
Am29LV641MH/L
3
D A T A S H E E T
TABLE OF CONTENTS
Continuity of Specifications ....................................................... i
For More Information ................................................................. i
Product Selector Guide. . . . . . . . . . . . . . . . . . . . . 5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 6
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . 8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 9
Table 1. Device Bus Operations .......................................................9
VersatileIO™ (VIO) Control ....................................................... 9
Requirements for Reading Array Data ..................................... 9
Page Mode Read .................................................................... 10
Writing Commands/Command Sequences ............................ 10
Write Buffer ............................................................................. 10
Accelerated Program Operation ............................................. 10
Autoselect Functions .............................................................. 10
Standby Mode ........................................................................ 10
Automatic Sleep Mode ........................................................... 10
RESET#: Hardware Reset Pin ............................................... 11
Output Disable Mode .............................................................. 11
Table 2. Sector Address Table ........................................................12
Autoselect Mode..................................................................... 14
Table 3. Autoselect Codes, (High Voltage Method) .......................14
Sector Group Protection and Unprotection ............................. 15
Table 4. Sector Group Protection/Unprotection Address Table .....15
Write Protect (WP#) ................................................................ 16
Temporary Sector Group Unprotect ....................................... 16
Figure 1. Temporary Sector Group Unprotect Operation................ 16
Figure 2. In-System Sector Group Protect/Unprotect Algorithms ... 17
SecSi (Secured Silicon) Sector Flash Memory Region .......... 18
Table 5. SecSi Sector Contents ......................................................18
Figure 3. SecSi Sector Protect Verify.............................................. 19
Hardware Data Protection ...................................................... 19
Low VCC Write Inhibit ............................................................ 19
Write Pulse “Glitch” Protection ............................................... 19
Logical Inhibit .......................................................................... 19
Power-Up Write Inhibit ............................................................ 19
Common Flash Memory Interface (CFI) . . . . . . . 19
Table 6. CFI Query Identification String .............................. 20
Table 7. System Interface String......................................................20
Table 8. Device Geometry Definition................................... 21
Table 9. Primary Vendor-Specific Extended Query............. 22
Command Definitions . . . . . . . . . . . . . . . . . . . . . 22
Reading Array Data ................................................................ 22
Reset Command ..................................................................... 23
Autoselect Command Sequence ............................................ 23
Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 23
Word Program Command Sequence ..................................... 23
Unlock Bypass Command Sequence ..................................... 24
Write Buffer Programming ...................................................... 24
Accelerated Program .............................................................. 25
Figure 4. Write Buffer Programming Operation............................... 26
Figure 5. Program Operation .......................................................... 27
Program Suspend/Program Resume Command Sequence ... 27
Figure 6. Program Suspend/Program Resume............................... 28
Chip Erase Command Sequence ........................................... 28
Sector Erase Command Sequence ........................................ 28
Erase Suspend/Erase Resume Commands ...........................29
Figure 7. Erase Operation.............................................................. 30
Command Definitions ............................................................. 31
Table 10. Command Definitions...................................................... 31
Write Operation Status. . . . . . . . . . . . . . . . . . . . . 32
DQ7: Data# Polling ................................................................. 32
Figure 8. Data# Polling Algorithm .................................................. 32
DQ6: Toggle Bit I .................................................................... 33
Figure 9. Toggle Bit Algorithm........................................................ 33
DQ2: Toggle Bit II ................................................................... 34
Reading Toggle Bits DQ6/DQ2 ............................................... 34
DQ5: Exceeded Timing Limits ................................................ 34
DQ3: Sector Erase Timer ....................................................... 34
DQ1: Write-to-Buffer Abort ..................................................... 35
Table 11. Write Operation Status ................................................... 35
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 36
Figure 10. Maximum Negative Overshoot Waveform ................... 36
Figure 11. Maximum Positive Overshoot Waveform..................... 36
Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 36
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 37
Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 12. Test Setup.................................................................... 38
Table 12. Test Specifications ......................................................... 38
Key to Switching Waveforms. . . . . . . . . . . . . . . . 38
Figure 13. Input Waveforms and
Measurement Levels...................................................................... 38
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 39
Read-Only Operations ........................................................... 39
Figure 14. Read Operation Timings............................................... 39
Figure 15. Page Read Timings ...................................................... 40
Hardware Reset (RESET#) .................................................... 41
Figure 16. Read Operation Timings............................................... 41
Figure 17. Reset Timings............................................................... 42
Erase and Program Operations .............................................. 43
Figure 18. Program Operation Timings.......................................... 44
Figure 19. Accelerated Program Timing Diagram.......................... 44
Figure 20. Chip/Sector Erase Operation Timings .......................... 45
Figure 21. Data# Polling Timings
(During Embedded Algorithms)...................................................... 46
Figure 22. Toggle Bit Timings
(During Embedded Algorithms)...................................................... 47
Figure 23. DQ2 vs. DQ6................................................................. 47
Temporary Sector Unprotect .................................................. 48
Figure 24. Temporary Sector Group Unprotect Timing Diagram ... 48
Figure 25. Sector Group Protect and Unprotect Timing Diagram .. 49
Alternate CE# Controlled Erase and Program Operations ..... 50
Figure 26. Alternate CE# Controlled Write (Erase/Program)
Operation Timings.......................................................................... 51
Erase And Programming Performance. . . . . . . . 52
Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 52
TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . . 53
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 54
TS 048—48-Pin Standard Thin Small Outline Package .........54
TSR048—48-Pin Reverse Thin Small Outline Package .........55
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 56
4
Am29LV641MH/L
December 21, 2005
D A T A S H E E T
PRODUCT SELECTOR GUIDE
Part Number
Am29LV641MH/L
90R
101R
112R
120R
(VIO = 1.65–3.6 V)
VCC = 3.0–3.6 V
(VIO = 3.0–3.6 V) (VIO = 2.7–3.6 V) (VIO = 1.65–3.6 V)
Speed
Option
101
112
120
VCC = 2.7–3.6 V
(VIO = 2.7–3.6 V)
(VIO = 1.65–3.6 V)
(VIO = 1.65–3.6 V)
Max. Access Time (ns)
90
90
100
100
110
110
120
120
Max. CE# Access Time
(ns)
Max. Page access time
25
25
30
30
30
30
40
40
30
30
40
40
(tPACC
)
Max. OE# Access Time
(ns)
Notes:
1. See “AC Characteristics” for full specifications.
2. For the Am29LV641MH/L device, the last numeric digit in the speed option (e.g. 101, 112, 120) is used for internal purposes only.
Please use OPNs as listed when placing orders.
BLOCK DIAGRAM
DQ0–DQ15
VCC
Sector Switches
VSS
VIO
Erase Voltage
Generator
Input/Output
Buffers
RESET#
WE#
WP#
ACC
State
Control
Command
Register
PGM Voltage
Generator
Data
Latch
Chip Enable
Output Enable
Logic
STB
CE#
OE#
Y-Decoder
Y-Gating
STB
VCC Detector
Timer
Cell Matrix
X-Decoder
A21–A0
December 21, 2005
Am29LV641MH/L
5
D A T A S H E E T
CONNECTION DIAGRAMS
A15
A14
A13
A12
A11
A10
A9
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
VIO
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
A8
48-Pin Standard TSOP
A21
A20
WE#
RESET#
ACC
WP#
A19
A18
A17
A7
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A6
A5
A4
A3
A2
A1
OE#
VSS
CE#
A0
A16
VIO
1
2
3
4
5
6
7
8
48
A15
A14
A13
A12
A11
A10
A9
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
A8
48-Pin Reverse TSOP
9
A21
A20
WE#
RESET#
ACC
WP#
A19
A18
A17
A7
A6
A5
A4
A3
A2
A1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
OE#
VSS
CE#
A0
6
Am29LV641MH/L
December 21, 2005
D A T A S H E E T
PIN DESCRIPTION
LOGIC SYMBOL
A21–A0
= 22 Address inputs
22
DQ15–DQ0 = 16 Data inputs/outputs
A21–A0
16
CE#
= Chip Enable input
DQ15–DQ0
CE#
OE#
= Output Enable input
= Write Enable input
OE#
WE#
WP#
ACC
RESET#
VCC
WE#
WP#
ACC
RESET#
VIO
= Hardware Write Protect input
= Acceleration input
= Hardware Reset Pin input
= 3.0 volt-only single power supply
(see Product Selector Guide for
speed options and voltage
supply tolerances)
VIO
VSS
NC
= Output Buffer power
= Device Ground
= Pin Not Connected Internally
December 21, 2005
Am29LV641MH/L
7
D A T A S H E E T
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the following:
Am29LV641M
H
120R
E
I
TEMPERATURE RANGE
Industrial (–40°C to +85°C)
I
=
PACKAGE TYPE
E
F
=
=
48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048)
48-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR048)
SPEED OPTION
See Product Selector Guide and Valid Combinations
SECTOR ARCHITECTURE AND SECTOR WRITE PROTECTION (WP# = 0)
H
L
=
=
Uniform sector device, highest address sector protected
Uniform sector device, lowest address sector protected
DEVICE NUMBER/DESCRIPTION
Am29LV641MH/L
64 Megabit (4 M x 16-Bit) MirrorBit Uniform Sector Flash Memory with VersatileIO™ Control
3.0 Volt-only Read, Program, and Erase
Valid Combinations for
TSOP Packages
Speed
(ns)
VIO
Range
VCC
Range
Am29LV641MH90R,
Am29LV641ML90R
3.0–
3.6 V
3.0–
3.6 V
90
Am29LV641MH101,
Am29LV641ML101
100
110
120
100
110
120
2.7–3.6 V
1.65–3.6 V
1.65–3.6 V
2.7–3.6 V
1.65–3.6 V
1.65–3.6 V
Am29LV641MH112,
Am29LV641ML112
2.7–
3.6 V
Am29LV641MH120,
EI, FI
Am29LV641ML120
Am29LV641MH101R,
Am29LV641ML101R
Am29LV641MH112R,
Am29LV641ML112R
3.0–
3.6 V
Am29LV641MH120R,
Am29LV641ML120R
Valid Combinations
Valid Combinations list configurations planned to be supported in
volume for this device. Consult the local AMD sales office to confirm
availability of specific valid combinations and to check on newly re-
leased combinations.
Note:
For the Am29LV641MH/L device, the last numeric digit in the speed
option (e.g. 101, 112, 120) is used for internal purposes only. Please
use OPNs as listed when placing orders.
8
Am29LV641MH/L
December 21, 2005
D A T A S H E E T
DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the in-
puts and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Table 1. Device Bus Operations
Addresses
(Note 2)
DQ0–
DQ15
Operation
CE# OE# WE# RESET#
WP#
X
ACC
L/H
L/H
VHH
Read
L
L
L
H
H
H
L
L
H
H
AIN
AIN
AIN
DOUT
Write (Program/Erase)
Accelerated Program
(Note 3)
(Note 3)
(Note 4)
(Note 4)
L
H
VCC
0.3 V
±
VCC ±
0.3 V
Standby
X
X
X
H
X
High-Z
Output Disable
Reset
L
H
X
H
X
H
L
X
X
L/H
L/H
X
X
High-Z
High-Z
X
SA, A6 =L, A3=L,
A2=L, A1=H, A0=L
Sector Group Protect (Note 2)
L
L
X
H
H
X
L
L
VID
VID
VID
H
H
H
L/H
L/H
L/H
(Note 4)
(Note 4)
(Note 4)
Sector Group Unprotect
(Note 2)
SA, A6=H, A3=L,
A2=L, A1=H, A0=L
Temporary Sector Group
Unprotect
X
AIN
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 11.5–12.5 V, X = Don’t Care, SA = Sector Address,
AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Addresses are A21:A0. Sector addresses are A21:A15.
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Group
Protection and Unprotection” section.
3. If WP# = VIL, the first or last sector remains protected. If WP# = VIH, the first or last sector will be protected or unprotected as
determined by the method described in “Sector Group Protection and Unprotection”. All sectors are unprotected when shipped
from the factory (The SecSi Sector may be factory protected depending on version ordered.)
4. DIN or DOUT as required by command sequence, data polling, or sector protect algorithm (see Figure 2).
VersatileIO™ (VIO) Control
Requirements for Reading Array Data
The VersatileIO™ (VIO) control allows the host system
to set the voltage levels that the device generates and
tolerates on CE# and DQ I/Os to the same voltage
level that is asserted on VIO. See “Ordering Informa-
tion” on page 8 for VIO options on this device.
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at VIH.
For example, a VI/O of 1.65–3.6 volts allows for I/O at
the 1.8 or 3 volt levels, driving and receiving signals to
and from other 1.8 or 3 V devices on the same data
bus.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
December 21, 2005
Am29LV641MH/L
9
D A T A S H E E T
data on the device data outputs. The device remains
Accelerated Program Operation
enabled for read access until the command register
contents are altered.
The device offers accelerated program operations
through the ACC function. This function is primarily in-
tended to allow faster manufacturing throughput dur-
ing system production.
See “Reading Array Data” for more information. Refer
to the AC Read-Only Operations table for timing speci-
fications and to Figure 14 for the timing diagram. Refer
to the DC Characteristics table for the active current
specification on reading array data.
If the system asserts VHH on this pin, the device auto-
matically enters the aforementioned Unlock Bypass
mode, temporarily unprotects any protected sectors,
and uses the higher voltage on the pin to reduce the
time required for program operations. The system
would use a two-cycle program command sequence
as required by the Unlock Bypass mode. Removing
VHH from the ACC pin returns the device to normal op-
eration. Note that the ACC pin must not be at VHH for
operations other than accelerated programming, or
device damage may result.
Page Mode Read
The device is capable of fast page mode read and is
compatible with the page mode Mask ROM read oper-
ation. This mode provides faster read access speed
for random locations within a page. The page size of
the device is 4 words. The appropriate page is se-
lected by the higher address bits A(max)–A2. Address
bits A1–A0 determine the specific word within a page.
This is an asynchronous operation; the microproces-
sor supplies the specific word location.
Autoselect Functions
If the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in
this mode. Refer to the Autoselect Mode and Autose-
lect Command Sequence sections for more informa-
tion.
The random or initial page access is equal to tACC or
tCE and subsequent page read accesses (as long as
the locations specified by the microprocessor falls
within that page) is equivalent to tPACC. When CE# is
deasserted and reasserted for a subsequent access,
the access time is tACC or tCE. Fast page mode ac-
cesses are obtained by keeping the “read-page ad-
dresses” constant and changing the “intra-read page”
addresses.
Standby Mode
When the system is not reading or writing to the de-
vice, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at VIO 0.3 V.
(Note that this is a more restricted voltage range than
VIH.) If CE# and RESET# are held at VIH, but not within
VIO 0.3 V, the device will be in the standby mode, but
the standby current will be greater. The device re-
quires standard access time (tCE) for read access
when the device is in either of these standby modes,
before it is ready to read data.
The device features an Unlock Bypass mode to facili-
tate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are re-
quired to program a word, instead of four. The “Word
Program Command Sequence” section has details on
programming data to the device using both standard
and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Table 2 indicates the address
space that each sector occupies.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
Refer to the DC Characteristics table for the active
current specification for the write mode. The AC Char-
acteristics section contains timing specification tables
and timing diagrams for write operations.
Refer to the DC Characteristics table for the standby
current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device en-
ergy consumption. The device automatically enables
Write Buffer
Write Buffer Programming allows the system to write a
maximum of 16 words in one programming operation.
This results in faster effective programming time than
the standard programming algorithms. See “Write
Buffer” for more information.
this mode when addresses remain stable for tACC
+
30 ns. The automatic sleep mode is independent of
the CE#, WE#, and OE# control signals. Standard ad-
dress access timings provide new data when ad-
10
Am29LV641MH/L
December 21, 2005
D A T A S H E E T
dresses are changed. While in sleep mode, output
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VSS 0.3 V, the device
draws CMOS standby current (ICC4). If RESET# is held
at VIL but not within VSS 0.3 V, the standby current will
be greater.
data is latched and always available to the system.
Refer to the DC Characteristics table for the automatic
sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the RE-
SET# pin is driven low for at least a period of tRP, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
Refer to the AC Characteristics tables for RESET# pa-
rameters and to Figure 17 for the timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high
impedance state.
December 21, 2005
Am29LV641MH/L
11
D A T A S H E E T
Table 2. Sector Address Table
16-bit
16-bit
Address Range
Address Range
(in hexadecimal)
Sector
SA0
A21–A15
(in hexadecimal)
000000–007FFF
008000–00FFFF
010000–017FFF
018000–01FFFF
020000–027FFF
028000–02FFFF
030000–037FFF
038000–03FFFF
040000–047FFF
048000–04FFFF
050000–057FFF
058000–05FFFF
060000–067FFF
068000–06FFFF
070000–077FFF
078000–07FFFF
080000–087FFF
088000–08FFFF
090000–097FFF
098000–09FFFF
0A0000–0A7FFF
0A8000–0AFFFF
0B0000–0B7FFF
0B8000–0BFFFF
0C0000–0C7FFF
0C8000–0CFFFF
0D0000–0D7FFF
0D8000–0DFFFF
0E0000–0E7FFF
0E8000–0EFFFF
0F0000–0F7FFF
0F8000–0FFFFF
200000–207FFF
208000–20FFFF
210000–217FFF
218000–21FFFF
220000–227FFF
228000–22FFFF
230000–237FFF
238000–23FFFF
240000–247FFF
248000–24FFFF
250000–257FFF
258000–25FFFF
Sector
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA96
SA97
SA98
SA99
SA100
SA101
SA102
SA103
SA104
SA105
SA106
SA107
A21–A15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
100000–107FFF
108000–10FFFF
110000–117FFF
118000–11FFFF
120000–127FFF
128000–12FFFF
130000–137FFF
138000–13FFFF
140000–147FFF
148000–14FFFF
150000–157FFF
158000–15FFFF
160000–167FFF
168000–16FFFF
170000–177FFF
178000–17FFFF
180000–187FFF
188000–18FFFF
190000–197FFF
198000–19FFFF
1A0000–1A7FFF
1A8000–1AFFFF
1B0000–1B7FFF
1B8000–1BFFFF
1C0000–1C7FFF
1C8000–1CFFFF
1D0000–1D7FFF
1D8000–1DFFFF
1E0000–1E7FFF
1E8000–1EFFFF
1F0000–1F7FFF
1F8000–1FFFFF
300000–307FFF
308000–30FFFF
310000–317FFF
318000–31FFFF
320000–327FFF
328000–32FFFF
330000–337FFF
338000–33FFFF
340000–347FFF
348000–34FFFF
350000–357FFF
358000–35FFFF
SA1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA64
SA65
SA66
SA67
SA68
SA69
SA70
SA71
SA72
SA73
SA74
SA75
12
Am29LV641MH/L
December 21, 2005
D A T A S H E E T
Table 2. Sector Address Table (Continued)
16-bit
16-bit
Address Range
Address Range
(in hexadecimal)
Sector
SA76
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
SA85
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
SA95
A21–A15
(in hexadecimal)
260000–267FFF
268000–26FFFF
270000–277FFF
278000–27FFFF
280000–287FFF
288000–28FFFF
290000–297FFF
298000–29FFFF
2A0000–2A7FFF
2A8000–2AFFFF
2B0000–2B7FFF
2B8000–2BFFFF
2C0000–2C7FFF
2C8000–2CFFFF
2D0000–2D7FFF
2D8000–2DFFFF
2E0000–2E7FFF
2E8000–2EFFFF
2F0000–2F7FFF
2F8000–2FFFFF
Sector
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
A21–A15
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
360000–367FFF
368000–36FFFF
370000–377FFF
378000–37FFFF
380000–387FFF
388000–38FFFF
390000–397FFF
398000–39FFFF
3A0000–3A7FFF
3A8000–3AFFFF
3B0000–3B7FFF
3B8000–3BFFFF
3C0000–3C7FFF
3C8000–3CFFFF
3D0000–3D7FFF
3D8000–3DFFFF
3E0000–3E7FFF
3E8000–3EFFFF
3F0000–3F7FFF
3F8000–3FFFFF
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Note: All sectors are 32 Kwords in size.
December 21, 2005
Am29LV641MH/L
13
D A T A S H E E T
In addition, when verifying sector protection, the sector
Autoselect Mode
address must appear on the appropriate highest order
address bits (see Table 2). Table 3 shows the remain-
ing address bits that are don’t care. When all neces-
sary bits have been set as required, the programming
equipment may then read the corresponding identifier
code on DQ7–DQ0.
The autoselect mode provides manufacturer and de-
vice identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equip-
ment to automatically match a device to be pro-
grammed with its corresponding programming
algorithm. However, the autoselect codes can also be
accessed in-system through the command register.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 10. This method
does not require VID. Refer to the Autoselect Com-
mand Sequence section for more information.
When using programming equipment, the autoselect
mode requires VID on address pin A9. Address pins
A6, A3, A2, A1, and A0 must be as shown in Table 3.
Table 3. Autoselect Codes, (High Voltage Method)
A21
to
A14
to
A8
to
A5
to
A3
to
Description
CE# OE# WE#
A9
A6
A1
A0
DQ15 to DQ0
A15
A10
A7
A4
A2
VID
Manufacturer ID: AMD
Cycle 1
L
L
L
L
H
H
X
X
X
L
X
L
L
L
L
H
L
0001h
227Eh
2213h
2201h
L
VID
Cycle 2
X
X
X
L
X
H
H
H
H
Cycle 3
H
Sector Protection
Verification
XX01h (protected),
XX00h (unprotected)
VID
VID
L
L
L
L
H
H
SA
X
X
X
X
X
L
L
X
X
L
L
H
H
L
SecSi Sector Indicator Bit
(DQ7), WP# protects
highest address sector
XX98h (factory locked),
XX18h (not factory locked)
H
SecSi Sector Indicator Bit
(DQ7), WP# protects
lowest address sector
XX88h (factory locked),
XX08h (not factory locked)
VID
L
L
H
X
X
X
L
X
L
H
H
Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
14
Am29LV641MH/L
December 21, 2005
D A T A S H E E T
Table 4. Sector Group Protection/Unprotection
Address Table
Sector Group Protection and
Unprotection
Sector Group
A21–A17
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
The hardware sector group protection feature disables
both program and erase operations in any sector
group. In this device, a sector group consists of four
adjacent sectors that are protected or unprotected at
the same time (see Table 4). The hardware sector
group unprotection feature re-enables both program
and erase operations in previously protected sector
groups. Sector group protection/unprotection can be
implemented via two methods.
SA0–SA3
SA4–SA7
SA8–SA11
SA12–SA15
SA16–SA19
SA20–SA23
SA24–SA27
SA28–SA31
SA32–SA35
SA36–SA39
SA40–SA43
SA44–SA47
SA48–SA51
SA52–SA55
SA56–SA59
SA60–SA63
SA64–SA67
SA68–SA71
SA72–SA75
SA76–SA79
SA80–SA83
SA84–SA87
SA88–SA91
SA92–SA95
SA96–SA99
SA100–SA103
SA104–SA107
SA108–SA111
SA112–SA115
SA116–SA119
SA120–SA123
SA124–SA127
Sector protection/unprotection requires VID on the RE-
SET# pin only, and can be implemented either in-sys-
tem or via programming equipment. Figure 2 shows
the algorithms and Figure 25 shows the timing dia-
gram. This method uses standard microprocessor bus
cycle timing. For sector group unprotect, all unpro-
tected sector groups must first be protected prior to
the first sector group unprotect write cycle.
The device is shipped with all sector groups unpro-
tected. AMD offers the option of programming and pro-
tecting sector groups at its factory prior to shipping the
device through AMD’s ExpressFlash™ Service. Con-
tact an AMD representative for details.
It is possible to determine whether a sector group is
protected or unprotected. See the Autoselect Mode
section for details.
Note: All sector groups are 128 Kwords in size.
December 21, 2005
Am29LV641MH/L
15
D A T A S H E E T
Write Protect (WP#)
The Write Protect function provides a hardware
method of protecting the first or last sector without
using VID.
START
If the system asserts VIL on the WP# pin, the device
disables program and erase functions in the first or last
sector independently of whether those sectors were
protected or unprotected using the method described
in “Sector Group Protection and Unprotection”. Note
that if WP# is at VIL when the device is in the standby
mode, the maximum input load current is increased.
See the table in “DC Characteristics”.
RESET# = VID
(Note 1)
Perform Erase or
Program Operations
RESET# = VIH
If the system asserts VIH on the WP# pin, the device
reverts to whether the first or last sector was previ-
ously set to be protected or unprotected using the
method described in “Sector Group Protection and
Unprotection”.
Temporary Sector
Group Unprotect
Completed (Note 2)
Temporary Sector Group Unprotect
(Note: In this device, a sector group consists of four adjacent
sectors that are protected or unprotected at the same time
(see Table 4).
Notes:
1. All protected sector groups unprotected (If WP# = VIL,
the first or last sector will remain protected).
This feature allows temporary unprotection of previ-
ously protected sector groups to change data in-sys-
tem. The Sector Group Unprotect mode is activated by
setting the RESET# pin to VID. During this mode, for-
merly protected sector groups can be programmed or
erased by selecting the sector group addresses. Once
VID is removed from the RESET# pin, all the previously
protected sector groups are protected again. Figure 1
shows the algorithm, and Figure 24 shows the timing
diagrams, for this feature.
2. All previously protected sector groups are protected
once again.
Figure 1. Temporary Sector Group
Unprotect Operation
16
Am29LV641MH/L
December 21, 2005
D A T A S H E E T
START
START
PLSCNT = 1
PLSCNT = 1
RESET# = VID
Protect all sector
groups: The indicated
portion of the sector
group protect algorithm
must be performed for all
unprotected sector
groups prior to issuing
the first sector group
unprotect address
RESET# = VID
Wait 1 μs
Wait 1 μs
Temporary Sector
Group Unprotect
Mode
Temporary Sector
Group Unprotect
Mode
No
No
First Write
Cycle = 60h?
First Write
Cycle = 60h?
Yes
Yes
Set up sector
group address
All sector
groups
No
protected?
Yes
Sector Group Protect:
Write 60h to sector
group address with
A6–A0 = 0xx0010
Set up first sector
group address
Sector Group
Unprotect:
Wait 150 µs
Write 60h to sector
group address with
A6–A0 = 1xx0010
Verify Sector Group
Protect: Write 40h
to sector group
address with
A6–A0 = 0xx0010
Reset
PLSCNT = 1
Increment
PLSCNT
Wait 15 ms
Verify Sector Group
Unprotect: Write
40h to sector group
address with
Read from
sector group address
with A6–A0
= 0xx0010
Increment
PLSCNT
A6–A0 = 1xx0010
No
No
PLSCNT
= 25?
Read from
sector group
address with
Data = 01h?
Yes
A6–A0 = 1xx0010
No
Yes
Set up
next sector group
address
Protect
another
sector group?
Yes
No
PLSCNT
= 1000?
Data = 00h?
Yes
Device failed
No
Yes
Remove VID
from RESET#
Last sector
group
verified?
No
Device failed
Write reset
command
Yes
Remove VID
from RESET#
Sector Group
Unprotect
Sector Group
Protect
Sector Group
Protect complete
Write reset
command
Algorithm
Algorithm
Sector Group
Unprotect complete
Figure 2. In-System Sector Group Protect/Unprotect Algorithms
Am29LV641MH/L
December 21, 2005
17
D A T A S H E E T
Factory Locked: SecSi Sector Programmed and
SecSi (Secured Silicon) Sector Flash
Memory Region
Protected At the Factory
In devices with an ESN, the SecSi Sector is protected
when the device is shipped from the factory. The SecSi
Sector cannot be modified in any way. A factory locked
device has an 8-word random ESN at addresses
000000h–000007h.
The SecSi (Secured Silicon) Sector feature provides a
Flash memory region that enables permanent part
identification through an Electronic Serial Number
(ESN). The SecSi Sector is 128 words in length, and
uses a SecSi Sector Indicator Bit (DQ7) to indicate
whether or not the SecSi Sector is locked when
shipped from the factory. This bit is permanently set at
the factory and cannot be changed, which prevents
cloning of a factory locked part. This ensures the secu-
rity of the ESN once the product is shipped to the field.
Customers may opt to have their code programmed by
AMD through the AMD ExpressFlash service. The de-
vices are then shipped from AMD’s factory with the
SecSi Sector permanently locked. Contact an AMD
representative for details on using AMD’s Express-
Flash service.
AMD offers the device with the SecSi Sector either
factory locked or customer lockable. The fac-
tory-locked version is always protected when shipped
from the factory, and has the SecSi (Secured Silicon)
Sector Indicator Bit permanently set to a “1.” The cus-
tomer-lockable version is shipped with the SecSi Sec-
tor unprotected, allowing customers to program the
sector after receiving the device. The customer-lock-
able version also has the SecSi Sector Indicator Bit
permanently set to a “0.” Thus, the SecSi Sector Indi-
cator Bit prevents customer-lockable devices from
being used to replace devices that are factory locked.
Customer Lockable: SecSi Sector NOT
Programmed or Protected At the Factory
As an alternative to the factory-locked version, the de-
vice may be ordered such that the customer may pro-
gram and protect the 128-word SecSi sector.
The system may program the SecSi Sector using the
write-buffer, accelerated and/or unlock bypass meth-
ods, in addition to the standard programming com-
mand sequence. See Command Definitions.
Programming and protecting the SecSi Sector must be
used with caution since, once protected, there is no
procedure available for unprotecting the SecSi Sector
area and none of the bits in the SecSi Sector memory
space can be modified in any way.
The SecSi sector address space in this device is allo-
cated as follows:
Table 5. SecSi Sector Contents
SecSi Sector
Address Range
Standard
Factory Locked Factory Locked
ExpressFlash
Customer
Lockable
The SecSi Sector area can be protected using one of
the following procedures:
ESN or
determined by
customer
000000h–000007h
000008h–00007Fh
ESN
Determined by
customer
■ Write the three-cycle Enter SecSi Sector Region
command sequence, and then follow the in-system
sector protect algorithm as shown in Figure 2, ex-
cept that RESET# may be at either VIH or VID. This
allows in-system protection of the SecSi Sector
without raising any device pin to a high voltage.
Note that this method is only applicable to the SecSi
Sector.
Determined by
customer
Unavailable
The system accesses the SecSi Sector through a
command sequence (see “Enter SecSi Sector/Exit
SecSi Sector Command Sequence”). After the system
has written the Enter SecSi Sector command se-
quence, it may read the SecSi Sector by using the ad-
dresses normally occupied by the first sector (SA0).
This mode of operation continues until the system is-
sues the Exit SecSi Sector command sequence, or
until power is removed from the device. On power-up,
or following a hardware reset, the device reverts to
sending commands to sector SA0.
■ To verify the protect/unprotect status of the SecSi
Sector, follow the algorithm shown in Figure 3.
Once the SecSi Sector is programmed, locked and
verified, the system must write the Exit SecSi Sector
Region command sequence to return to reading and
writing within the remainder of the array.
18
Am29LV641MH/L
December 21, 2005
D A T A S H E E T
data protection measures prevent accidental erasure
or programming, which might otherwise be caused by
spurious system level signals during VCC power-up
and power-down transitions, or from system noise.
START
If data = 00h,
SecSi Sector is
unprotected.
If data = 01h,
SecSi Sector is
protected.
Low VCC Write Inhibit
RESET# =
VIH or VID
When VCC is less than VLKO, the device does not ac-
cept any write cycles. This protects data during VCC
power-up and power-down. The command register
and all internal program/erase circuits are disabled,
and the device resets to the read mode. Subsequent
writes are ignored until VCC is greater than VLKO. The
system must provide the proper signals to the control
pins to prevent unintentional writes when VCC is
Wait 1 μs
Write 60h to
any address
Remove VIH or VID
from RESET#
Write 40h to SecSi
Sector address
with A6 = 0,
greater than VLKO
.
Write reset
command
A1 = 1, A0 = 0
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE#
or WE# do not initiate a write cycle.
SecSi Sector
Protect Verify
complete
Read from SecSi
Sector address
with A6 = 0,
Logical Inhibit
A1 = 1, A0 = 0
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Figure 3. SecSi Sector Protect Verify
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up,
the device does not accept commands on the rising
edge of WE#. The internal state machine is automati-
cally reset to the read mode on power-up.
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 10 for com-
mand definitions). In addition, the following hardware
COMMON FLASH MEMORY INTERFACE (CFI)
The Common Flash Interface (CFI) specification out-
lines device and host system software interrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire families of
devices. Software support can then be device-inde-
pendent, JEDEC ID-independent, and forward- and
backward-compatible for the specified flash device
families. Flash vendors can standardize their existing
interfaces for long-term compatibility.
The system can also write the CFI query command
when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read
CFI data at the addresses given in Tables 6–9. The
system must write the reset command to return the
device to reading array data.
For further information, please refer to the CFI Specifi-
cation and CFI Publication 100, available via the World
Wide Web at http://www.amd.com/flash/cfi. Alterna-
tively, contact an AMD representative for copies of
these documents.
This device enters the CFI Query mode when the sys-
tem writes the CFI Query command, 98h, to address
55h, any time the device is ready to read array data.
The system can read CFI information at the addresses
given in Tables 6–9. To terminate reading CFI data,
the system must write the reset command.
December 21, 2005
Am29LV641MH/L
19
D A T A S H E E T
Table 6. CFI Query Identification String
Addresses (x16)
Data
Description
10h
11h
12h
0051h
0052h
0059h
Query Unique ASCII string “QRY”
13h
14h
0002h
0000h
Primary OEM Command Set
15h
16h
0040h
0000h
Address for Primary Extended Table
17h
18h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
Address for Alternate OEM Extended Table (00h = none exists)
19h
1Ah
0000h
0000h
Table 7. System Interface String
Description
Addresses (x16)
Data
VCC Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Bh
0027h
VCC Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Ch
0036h
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
0000h
0000h
0007h
0007h
000Ah
0000h
0001h
0005h
0004h
0000h
VPP Min. voltage (00h = no VPP pin present)
VPP Max. voltage (00h = no VPP pin present)
Typical timeout per single byte/word write 2N µs
Typical timeout for Min. size buffer write 2N µs (00h = not supported)
Typical timeout per individual block erase 2N ms
Typical timeout for full chip erase 2N ms (00h = not supported)
Max. timeout for byte/word write 2N times typical
Max. timeout for buffer write 2N times typical
Max. timeout per individual block erase 2N times typical
Max. timeout for full chip erase 2N times typical (00h = not supported)
20
Am29LV641MH/L
December 21, 2005
D A T A S H E E T
Table 8. Device Geometry Definition
Addresses (x16)
Data
Description
27h
0017h
Device Size = 2N byte
28h
29h
0001h
0000h
Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh
0005h
0000h
Max. number of byte in multi-byte write = 2N
(00h = not supported)
Number of Erase Block Regions within device (01h = uniform device, 02h = boot
device)
2Ch
0001h
2Dh
2Eh
2Fh
30h
007Fh
0000h
0000h
0001h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
31h
32h
33h
34h
0000h
0000h
0000h
0000h
Erase Block Region 2 Information (refer to CFI publication 100)
Erase Block Region 3 Information (refer to CFI publication 100)
Erase Block Region 4 Information (refer to CFI publication 100)
35h
36h
37h
38h
0000h
0000h
0000h
0000h
39h
3Ah
3Bh
3Ch
0000h
0000h
0000h
0000h
December 21, 2005
Am29LV641MH/L
21
D A T A S H E E T
Table 9. Primary Vendor-Specific Extended Query
Addresses (x16)
Data
Description
40h
41h
42h
0050h
0052h
0049h
Query-unique ASCII string “PRI”
43h
44h
0031h
0033h
Major version number, ASCII
Minor version number, ASCII
Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not Required
45h
0008h
Process Technology (Bits 7-2) 0010b = 0.23 µm MirrorBit
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
46h
47h
48h
49h
4Ah
4Bh
4Ch
0002h
0004h
0001h
0004h
0000h
0000h
0001h
Sector Protect
0 = Not Supported, X = Number of sectors in per group
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
Sector Protect/Unprotect scheme
04 = 29LV800 mode
Simultaneous Operation
00 = Not Supported, X = Number of Sectors in Bank
Burst Mode Type
00 = Not Supported, 01 = Supported
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
ACC (Acceleration) Supply Minimum
4Dh
4Eh
00B5h
00C5h
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
Top/Bottom Boot Sector Flag
0004h/
0005h
00h = Uniform Device without WP# protect, 02h = Bottom Boot Device, 03h = Top
Boot Device, 04h = Uniform sectors bottom WP# protect, 05h = Uniform sectors top
WP# protect
4Fh
50h
Program Suspend
0001h
00h = Not Supported, 01h = Supported
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates device op-
erations. Table 10 defines the valid register command
sequences. Writing incorrect address and data val-
ues or writing them in the improper sequence may
place the device in an unknown state. A reset com-
mand is then required to return the device to reading
array data.
first. Refer to the AC Characteristics section for timing
diagrams.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is ready to read array data
after completing an Embedded Program or Embedded
Erase algorithm.
All addresses are latched on the falling edge of WE#
or CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
After the device accepts an Erase Suspend command,
the device enters the erase-suspend-read mode, after
which the system can read data from any
22
Am29LV641MH/L
December 21, 2005
D A T A S H E E T
non-erase-suspended sector. After completing a pro-
Autoselect Command Sequence
The autoselect command sequence allows the host
system to read several identifier codes at specific ad-
dresses:
gramming operation in the Erase Suspend mode, the
system may once again read array data with the same
exception. See the Erase Suspend/Erase Resume
Commands section for more information.
Identifier Code
Manufacturer ID
A7:A0
00h
The system must issue the reset command to return
the device to the read (or erase-suspend-read) mode if
DQ5 goes high during an active program or erase op-
eration, or if the device is in the autoselect mode. See
the next section, Reset Command, for more informa-
tion.
Device ID, Cycle 1
01h
Device ID, Cycle 2
0Eh
Device ID, Cycle 3
0Fh
SecSi Sector Factory Protect
Sector Protect Verify
03h
(SA)02h
See also Requirements for Reading Array Data in the
Device Bus Operations section for more information.
The Read-Only Operations table provides the read pa-
rameters, and Figure 14 shows the timing diagram.
Note: The device ID is read over three cycles. SA = Sector Address
Table 10 shows the address and data requirements.
This method is an alternative to that shown in Table 3,
which is intended for PROM programmers and re-
quires VID on address pin A9. The autoselect com-
mand sequence may be written to an address that is
either in the read or erase-suspend-read mode. The
autoselect command may not be written while the de-
vice is actively programming or erasing.
Reset Command
Writing the reset command resets the device to the
read or erase-suspend-read mode. Address bits are
don’t cares for this command.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to the read
mode. Once erasure begins, however, the device ig-
nores reset commands until the operation is complete.
The autoselect command sequence is initiated by first
writing two unlock cycles. This is followed by a third
write cycle that contains the autoselect command. The
device then enters the autoselect mode. The system
may read at any address any number of times without
initiating another autoselect command sequence
The reset command may be written between the
sequence cycles in a program command sequence
before programming begins. This resets the device to
the read mode. If the program command sequence is
written while the device is in the Erase Suspend mode,
writing the reset command returns the device to the
erase-suspend-read mode. Once programming be-
gins, however, the device ignores reset commands
until the operation is complete.
The system must write the reset command to return to
the read mode (or erase-suspend-read mode if the de-
vice was previously in Erase Suspend).
Enter SecSi Sector/Exit SecSi Sector
Command Sequence
The SecSi Sector region provides a secured data area
containing an 8-word random Electronic Serial Num-
ber (ESN). The system can access the SecSi Sector
region by issuing the three-cycle Enter SecSi Sector
command sequence. The device continues to access
the SecSi Sector region until the system issues the
four-cycle Exit SecSi Sector command sequence. The
Exit SecSi Sector command sequence returns the de-
vice to normal operation. Table 10 shows the address
and data requirements for both command sequences.
See also “SecSi (Secured Silicon) Sector Flash
Memory Region” for further information. Note that the
ACC function and unlock bypass modes are not avail-
able when the SecSi Sector is enabled.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command
must be written to return to the read mode. If the de-
vice entered the autoselect mode while in the Erase
Suspend mode, writing the reset command returns the
device to the erase-suspend-read mode.
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to the
read mode (or erase-suspend-read mode if the device
was in Erase Suspend).
Note that if DQ1 goes high during a Write Buffer Pro-
gramming operation, the system must write the
Write-to-Buffer-Abort Reset command sequence to
reset the device for the next operation.
Word Program Command Sequence
Programming is a four-bus-cycle operation. The pro-
gram command sequence is initiated by writing two
unlock write cycles, followed by the program set-up
command. The program address and data are written
next, which in turn initiate the Embedded Program al-
gorithm. The system is not required to provide further
December 21, 2005
Am29LV641MH/L
23
D A T A S H E E T
controls or timings. The device automatically provides
Write Buffer Programming
internally generated program pulses and verifies the
programmed cell margin. Table 10 shows the address
and data requirements for the word program command
sequence.
Write Buffer Programming allows the system write to a
maximum of 16 words in one programming operation.
This results in faster effective programming time than
the standard programming algorithms. The Write
Buffer Programming command sequence is initiated
by first writing two unlock cycles. This is followed by a
third write cycle containing the Write Buffer Load com-
mand written at the Sector Address in which program-
ming will occur. The fourth cycle writes the sector
address and the number of word locations, minus one,
to be programmed. For example, if the system will pro-
gram 6 unique address locations, then 05h should be
written to the device. This tells the device how many
write buffer addresses will be loaded with data and
therefore when to expect the Program Buffer to Flash
command. The number of locations to program cannot
exceed the size of the write buffer or the operation will
abort.
When the Embedded Program algorithm is complete,
the device then returns to the read mode and ad-
dresses are no longer latched. The system can deter-
mine the status of the program operation by using
DQ7 or DQ6. Refer to the Write Operation Status sec-
tion for information on these status bits.
Any commands written to the device during the Em-
bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program
operation. The program command sequence should
be reinitiated once the device has returned to the read
mode, to ensure data integrity. Note that the ACC
function and unlock bypass modes are not available
when the SecSi Sector is enabled.
The fifth cycle writes the first address location and
data to be programmed. The write-buffer-page is se-
lected by address bits AMAX–A4. All subsequent ad-
dress/data pairs must fall within the
selected-write-buffer-page. The system then writes the
remaining address/data pairs into the write buffer.
Write buffer locations may be loaded in any order.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from “0” back to a “1.” Attempting to do so may
cause the device to set DQ5 = 1, or cause the DQ7
and DQ6 status bits to indicate the operation was suc-
cessful. However, a succeeding read will show that the
data is still “0.” Only erase operations can convert a “0”
to a “1.”
The write-buffer-page address must be the same for
all address/data pairs loaded into the write buffer.
(This means Write Buffer Programming cannot be per-
formed across multiple write-buffer pages. This also
means that Write Buffer Programming cannot be per-
formed across multiple sectors. If the system attempts
to load programming data outside of the selected
write-buffer page, the operation will abort.
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to pro-
gram words to the device faster than using the stan-
dard program command sequence. The unlock bypass
command sequence is initiated by first writing two un-
lock cycles. This is followed by a third write cycle con-
taining the unlock bypass command, 20h. The device
then enters the unlock bypass mode. A two-cycle un-
lock bypass program command sequence is all that is
required to program in this mode. The first cycle in this
sequence contains the unlock bypass program com-
mand, A0h; the second cycle contains the program
address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program
command sequence, resulting in faster total program-
ming time. Table 10 shows the requirements for the
command sequence.
Note that if a Write Buffer address location is loaded
multiple times, the address/data pair counter will be
decremented for every data load operation. The host
system must therefore account for loading a
write-buffer location more than once. The counter dec-
rements for each data load operation, not for each
unique write-buffer-address location. Note also that if
an address location is loaded more than once into the
buffer, the final data loaded for that address will be
programmed.
Once the specified number of write buffer locations
have been loaded, the system must then write the Pro-
gram Buffer to Flash command at the sector address.
Any other address and data combination aborts the
Write Buffer Programming operation. The device then
begins programming. Data polling should be used
while monitoring the last address location loaded into
the write buffer. DQ7, DQ6, DQ5, and DQ1 should be
monitored to determine the device status during Write
Buffer Programming.
During the unlock bypass mode, only the Unlock By-
pass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com-
mand sequence. The first cycle must contain the data
90h. The second cycle must contain the data 00h. The
device then returns to the read mode.
24
Am29LV641MH/L
December 21, 2005
D A T A S H E E T
The write-buffer programming operation can be sus-
toggle, and DQ5=0. A Write-to-Buffer-Abort Reset
command sequence must be written to reset the de-
vice for the next operation. Note that the full 3-cycle
Write-to-Buffer-Abort Reset command sequence is re-
quired when using Write-Buffer-Programming features
in Unlock Bypass mode.
pended using the standard program suspend/resume
commands. Upon successful completion of the Write
Buffer Programming operation, the device is ready to
execute the next command.
The Write Buffer Programming Sequence can be
aborted in the following ways:
Accelerated Program
■ Load a value that is greater than the page buffer
size during the Number of Locations to Program
step.
The device offers accelerated program operations
through the ACC pin. When the system asserts VHH on
the ACC pin, the device automatically enters the Un-
lock Bypass mode. The system may then write the
two-cycle Unlock Bypass program command se-
quence. The device uses the higher voltage on the
ACC pin to accelerate the operation. Note that the
ACC pin must not be at VHH for operations other than
accelerated programming, or device damage may re-
sult.
■ Write to an address in a sector different than the
one specified during the Write-Buffer-Load com-
mand.
■ Write an Address/Data pair to
a
different
write-buffer-page than the one selected by the
Starting Address during the write buffer data load-
ing stage of the operation.
Figure 5 illustrates the algorithm for the program oper-
ation. Refer to the Erase and Program Operations
table in the AC Characteristics section for parameters,
and Figure 18 for timing diagrams.
■ Write data other than the Confirm Command after
the specified number of data load cycles.
The abort condition is indicated by DQ1 = 1, DQ7 =
DATA# (for the last address location loaded), DQ6 =
December 21, 2005
Am29LV641MH/L
25
D A T A S H E E T
Write “Write to Buffer”
command and
Sector Address
Part of “Write to Buffer”
Command Sequence
Write number of addresses
to program minus 1(WC)
and Sector Address
Write first address/data
Yes
WC = 0 ?
No
Write to a different
sector address
Abort Write to
Buffer Operation?
Yes
Write to buffer ABORTED.
Must write “Write-to-buffer
Abort Reset” command
sequence to return
No
(Note 1)
Write next address/data pair
to read mode.
WC = WC - 1
Write program buffer to
flash sector address
Notes:
1. When Sector Address is specified, any address in
the selected sector is acceptable. However, when
loading Write-Buffer address locations with data, all
addresses must fall within the selected Write-Buffer
Page.
Read DQ7 - DQ0 at
Last Loaded Address
2. DQ7 may change simultaneously with DQ5.
Therefore, DQ7 should be verified.
3. If this flowchart location was reached because
DQ5= “1”, then the device FAILED. If this flowchart
location was reached because DQ1= “1”, then the
Write to Buffer operation was ABORTED. In either
case, the proper reset command must be written
before the device can begin another operation. If
DQ1=1, write the
Yes
DQ7 = Data?
No
No
Write-Buffer-Programming-Abort-Reset
command. if DQ5=1, write the Reset command.
No
DQ1 = 1?
Yes
DQ5 = 1?
Yes
4. See Table 10 for command sequences required for
write buffer programming.
Read DQ7 - DQ0 with
address = Last Loaded
Address
Yes
(Note 2)
DQ7 = Data?
No
(Note 3)
FAIL or ABORT
PASS
Figure 4. Write Buffer Programming Operation
Am29LV641MH/L
26
December 21, 2005
D A T A S H E E T
Program Suspend/Program Resume
Command Sequence
The Program Suspend command allows the system to
interrupt a programming operation or a Write to Buffer
programming operation so that data can be read from
any non-suspended sector. When the Program Sus-
pend command is written during a programming pro-
cess, the device halts the program operation within 5
µs typical (maximum of 15 µs) and updates the status
bits. Addresses are not required when writing the Pro-
gram Suspend command.
START
Write Program
Command Sequence
Data Poll
from System
Embedded
Program
algorithm
in progress
After the programming operation has been sus-
pended, the system can read array data from any
non-suspended sector. The Program Suspend com-
mand may also be issued during a programming oper-
ation while an erase is suspended. In this case, data
may be read from any addresses not in Erase Sus-
pend or Program Suspend. If a read is needed from
the SecSi Sector area (One-time Program area), then
user must use the proper command sequences to
enter and exit this region. Note that the SecSi Sector,
autoselect, and CFI functions are unavailable when an
program operation is in progress.
Verify Data?
Yes
No
No
Increment Address
Last Address?
Yes
The system may also write the autoselect command
sequence when the device is in the Program Suspend
mode. The system can read as many autoselect codes
as required. When the device exits the autoselect
mode, the device reverts to the Program Suspend
mode, and is ready for another valid operation. See
Autoselect Command Sequence for more information.
Programming
Completed
Note: See Table 10 for program command sequence.
Figure 5. Program Operation
After the Program Resume command is written, the
device reverts to programming. The system can deter-
mine the status of the program operation using the
DQ7 or DQ6 status bits, just as in the standard pro-
gram operation. See Write Operation Status for more
information.
The system must write the Program Resume com-
mand (address bits are don’t care) to exit the Program
Suspend mode and continue the programming opera-
tion. Further writes of the Resume command are ig-
nored. Another Program Suspend command can be
written after the device has resume programming.
December 21, 2005
Am29LV641MH/L
27
D A T A S H E E T
When the Embedded Erase algorithm is complete, the
device returns to the read mode and addresses are no
longer latched. The system can determine the status
of the erase operation by using DQ7, DQ6, or DQ2.
Refer to the Write Operation Status section for infor-
mation on these status bits.
Program Operation
or Write-to-Buffer
Sequence in Progress
Write Program Suspend
Command Sequence
Write address/data
XXXh/B0h
Any commands written during the chip erase operation
are ignored. However, note that a hardware reset im-
mediately terminates the erase operation. If that oc-
curs, the chip erase command sequence should be
reinitiated once the device has returned to reading
array data, to ensure data integrity. Note that the
SecSi Sector, autoselect, and CFI functions are un-
available when an erase operation is in progress.
Command is also valid for
Erase-suspended-program
operations
Wait 15 μs
Autoselect and SecSi Sector
read operations are also allowed
Read data as
required
Data cannot be read from erase- or
program-suspended sectors
Figure 7 illustrates the algorithm for the erase opera-
tion. Refer to the Erase and Program Operations ta-
bles in the AC Characteristics section for parameters,
and Figure 20 section for timing diagrams.
Done
reading?
No
Yes
Sector Erase Command Sequence
Write Program Resume
Command Sequence
Write address/data
XXXh/30h
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two ad-
ditional unlock cycles are written, and are then fol-
lowed by the address of the sector to be erased, and
the sector erase command. Table 10 shows the ad-
dress and data requirements for the sector erase com-
mand sequence.
Device reverts to
operation prior to
Program Suspend
Figure 6. Program Suspend/Program Resume
The device does not require the system to preprogram
prior to erase. The Embedded Erase algorithm auto-
matically programs and verifies the entire memory for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Table 10
shows the address and data requirements for the chip
erase command sequence.
After the command sequence is written, a sector erase
time-out of 50 µs occurs. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time
between these additional cycles must be less than 50
µs, otherwise erasure may begin. Any sector erase ad-
dress and command following the exceeded time-out
may or may not be accepted. It is recommended that
processor interrupts be disabled during this time to en-
sure all commands are accepted. The interrupts can
be re-enabled after the last Sector Erase command is
written. Any command other than Sector Erase or
Erase Suspend during the time-out period resets
the device to the read mode. The system must re-
write the command sequence and any additional ad-
dresses and commands. Note that the SecSi Sector,
autoselect, and CFI functions are unavailable when an
erase operation is in progress.
28
Am29LV641MH/L
December 21, 2005
D A T A S H E E T
The system can monitor DQ3 to determine if the sec-
After the erase operation has been suspended, the
device enters the erase-suspend-read mode. The sys-
tem can read data from or program data to any sector
not selected for erasure. (The device “erase sus-
pends” all sectors selected for erasure.) Reading at
any address within erase-suspended sectors pro-
duces status information on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
Refer to the Write Operation Status section for infor-
mation on these status bits.
tor erase timer has timed out (See the section on DQ3:
Sector Erase Timer.). The time-out begins from the ris-
ing edge of the final WE# pulse in the command
sequence.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses
are no longer latched. The system can determine the
status of the erase operation by reading DQ7, DQ6, or
DQ2 in the erasing sector. Refer to the Write Opera-
tion Status section for information on these status bits.
After an erase-suspended program operation is com-
plete, the device returns to the erase-suspend-read
mode. The system can determine the status of the
program operation using the DQ7 or DQ6 status bits,
just as in the standard word program operation.
Refer to the Write Operation Status section for more
information.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other com-
mands are ignored. However, note that a hardware
reset immediately terminates the erase operation. If
that occurs, the sector erase command sequence
should be reinitiated once the device has returned to
reading array data, to ensure data integrity.
In the erase-suspend-read mode, the system can also
issue the autoselect command sequence. Refer to the
Autoselect Mode and Autoselect Command Sequence
sections for details.
Figure 7 illustrates the algorithm for the erase opera-
tion. Refer to the Erase and Program Operations ta-
bles in the AC Characteristics section for parameters,
and Figure 20 section for timing diagrams.
To resume the sector erase operation, the system
must write the Erase Resume command. Further
writes of the Resume command are ignored. Another
Erase Suspend command can be written after the chip
has resumed erasing.
Erase Suspend/Erase Resume
Commands
The Erase Suspend command, B0h, allows the sys-
tem to interrupt a sector erase operation and then read
data from, or program data to, any sector not selected
for erasure. This command is valid only during the sec-
tor erase operation, including the 50 µs time-out pe-
riod during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program
algorithm.
Note: During an erase operation, this flash device per-
forms multiple internal operations which are invisible
to the system. When an erase operation is suspended,
any of the internal operations that were not fully com-
pleted must be restarted. As such, if this flash device
is continually issued suspend/resume commands in
rapid succession, erase progress will be impeded as a
function of the number of suspends. The result will be
a longer cumulative erase time than without suspends.
Note that the additional suspends do not affect device
reliability or future performance. In most systems rapid
erase/suspend activity occurs only briefly. In this ex-
ample, erase performance will not be significantly im-
pacted.
When the Erase Suspend command is written during
the sector erase operation, the device requires a typi-
cal of 5 µs (maximum of 20 µs) to suspend the erase
operation. However, when the Erase Suspend com-
mand is written during the sector erase time-out, the
device immediately terminates the time-out period and
suspends the erase operation.
December 21, 2005
Am29LV641MH/L
29
D A T A S H E E T
START
Write Erase
Command Sequence
(Notes 1, 2)
Data Poll to Erasing
Bank from System
Embedded
Erase
algorithm
in progress
No
Data = FFh?
Yes
Erasure Completed
Notes:
1. See Table 10 for erase command sequence.
2. See the section on DQ3 for information on the sector
erase timer.
Figure 7. Erase Operation
30
Am29LV641MH/L
December 21, 2005
D A T A S H E E T
Command Definitions
Table 10. Command Definitions
Bus Cycles (Notes 1–4)
Command Sequence (Notes)
Read (Note 5)
Addr Data Addr Data
Addr
Data
Addr
Data
Addr Data Addr Data
1
1
4
6
RA
XXX
555
555
RD
F0
Reset (Note 6)
Manufacturer ID
AA
AA
2AA
2AA
55
55
555
555
90
90
X00
X01
0001
227E
Device ID (Note 8)
X0E 2213 X0F 2201
SecSi™ Sector Factory Protect
(Note 9)
4
4
555
555
AA
AA
2AA
2AA
55
55
555
555
90
90
X03
(Note 9)
00/01
Sector Group Protect Verify
(Note 10)
(SA)X02
Enter SecSi Sector Region
Exit SecSi Sector Region
Program
3
4
4
6
1
3
3
2
2
6
6
1
1
1
555
555
555
555
SA
AA
AA
AA
AA
29
2AA
2AA
2AA
2AA
55
55
55
55
555
555
555
SA
88
90
A0
25
XXX
PA
00
PD
WC
Write to Buffer (Note 11)
Program Buffer to Flash
Write to Buffer Abort Reset (Note 12)
Unlock Bypass
SA
PA
PD
WBL
PD
555
555
XXX
XXX
555
555
XXX
XXX
55
AA
AA
A0
90
2AA
2AA
PA
55
55
PD
00
55
55
555
555
F0
20
Unlock Bypass Program (Note 13)
Unlock Bypass Reset (Note 14)
Chip Erase
XXX
2AA
2AA
AA
AA
B0
30
555
555
80
80
555
555
AA
AA
2AA
2AA
55
55
555
SA
10
30
Sector Erase
Program/Erase Suspend (Note 15)
Program/Erase Resume (Note 16)
CFI Query (Note 17)
98
Legend:
X = Don’t care
RA = Read Address of the memory location to be read.
RD = Read Data read from location RA during read operation.
PA = Program Address. Addresses latch on the falling edge of the WE#
or CE# pulse, whichever happens later.
SA = Sector Address of sector to be verified (in autoselect mode) or
erased. Address bits A21–A15 uniquely select any sector.
WBL = Write Buffer Location. Address must be within the same write
buffer page as PA.
WC = Word Count. Number of write buffer locations to load minus 1.
PD = Program Data for location PA. Data latches on the rising edge of
WE# or CE# pulse, whichever happens first.
Notes:
1. See Table 1 for description of bus operations.
10. The data is 00h for an unprotected sector group and 01h for a
protected sector group.
2. All values are in hexadecimal.
11. The total number of cycles in the command sequence is
determined by the number of words written to the write buffer. The
maximum number of cycles in the command sequence is 21,
including "Program Buffer to Flash" command.
3. Shaded cells indicate read cycles. All other are write cycles.
4. During unlock and command cycles, when lower address bits are
555 or 2AA as shown in table, address bits higher than A11 and
data bits higher than DQ7 are don’t care.
12. Command sequence resets device for next command after
aborted write-to-buffer operation.
5. No unlock or command cycles required when device is in read
mode.
13. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
6. The Reset command is required to return to the read mode (or to
the erase-suspend-read mode if previously in Erase Suspend)
when the device is in the autoselect mode, or if DQ5 goes high
while the device is providing status information.
14. The Unlock Bypass Reset command is required to return to the
read mode when the device is in the unlock bypass mode.
15. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation.
7. The fourth cycle of the autoselect command sequence is a read
cycle. Data bits DQ15–DQ8 are don’t care. See the Autoselect
Command Sequence section for more information.
8. The device ID must be read in three cycles.
16. The Erase Resume command is valid only during the Erase
Suspend mode.
9. If WP# protects the highest address sector, the data is 98h for
factory locked and 18h for not factory locked. If WP# protects the
lowest address sector, the data is 88h for factory locked and 08h
for not factor locked.
17. Command is valid when device is ready to read array data or when
device is in autoselect mode.
December 21, 2005
Am29LV641MH/L
31
D A T A S H E E T
WRITE OPERATION STATUS
The device provides several bits to determine the status of a
program or erase operation: DQ2, DQ3, DQ5, DQ6, and
DQ7. Table 11 and the following subsections describe the
function of these bits. DQ7 and DQ6 each offer a method for
determining whether a program or erase operation is com-
plete or in progress.
invalid. Valid data on DQ0–DQ7 will appear on suc-
cessive read cycles.
Table 11 shows the outputs for Data# Polling on DQ7.
Figure 8 shows the Data# Polling algorithm. Figure 21
in the AC Characteristics section shows the Data#
Polling timing diagram.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system
whether an Embedded Program or Erase algorithm is in
progress or completed, or whether the device is in Erase
Suspend. Data# Polling is valid after the rising edge of the
final WE# pulse in the command sequence.
START
Read DQ7–DQ0
Addr = VA
During the Embedded Program algorithm, the device out-
puts on DQ7 the complement of the datum programmed to
DQ7. This DQ7 status also applies to programming during
Erase Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to
DQ7. The system must provide the program address to
read valid status information on DQ7. If a program address
falls within a protected sector, Data# Polling on DQ7 is ac-
tive for approximately 1 µs, then the device returns to the
read mode.
Yes
DQ7 = Data?
No
No
DQ5 = 1?
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase
algorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
The system must provide an address within any of the
sectors selected for erasure to read valid status infor-
mation on DQ7.
Yes
Read DQ7–DQ0
Addr = VA
After an erase command sequence is written, if all
sectors selected for erasing are protected, Data# Poll-
ing on DQ7 is active for approximately 100 µs, then the
device returns to the read mode. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se-
lected sectors that are protected. However, if the sys-
tem reads DQ7 at an address within a protected
sector, the status may not be valid.
Yes
DQ7 = Data?
No
PASS
FAIL
Just prior to the completion of an Embedded Program
or Erase operation, DQ7 may change asynchronously
with DQ0–DQ6 while Output Enable (OE#) is asserted
low. That is, the device may change from providing
status information to valid data on DQ7. Depending on
when the system samples the DQ7 output, it may read
the status or valid data. Even if the device has com-
pleted the program or erase operation and DQ7 has
valid data, the data outputs on DQ0–DQ6 may be still
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is any sector address
within the sector being erased. During chip erase, a
valid address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
Figure 8. Data# Polling Algorithm
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Am29LV641MH/L
December 21, 2005
D A T A S H E E T
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or com-
plete, or whether the device has entered the Erase
Suspend mode. Toggle Bit I may be read at any ad-
dress, and is valid after the rising edge of the final
WE# pulse in the command sequence (prior to the
program or erase operation), and during the sector
erase time-out.
START
Read DQ7–DQ0
During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address cause
DQ6 to toggle. The system may use either OE# or
CE# to control the read cycles. When the operation is
complete, DQ6 stops toggling.
Read DQ7–DQ0
No
Toggle Bit
= Toggle?
After an erase command sequence is written, if all sectors
selected for erasing are protected, DQ6 toggles for approxi-
mately 100 µs, then returns to reading array data. If not all
selected sectors are protected, the Embedded Erase algo-
rithm erases the unprotected sectors, and ignores the se-
lected sectors that are protected.
Yes
No
DQ5 = 1?
Yes
The system can use DQ6 and DQ2 together to determine
whether a sector is actively erasing or is erase-suspended.
When the device is actively erasing (that is, the Embedded
Erase algorithm is in progress), DQ6 toggles. When the de-
vice enters the Erase Suspend mode, DQ6 stops toggling.
However, the system must also use DQ2 to determine
which sectors are erasing or erase-suspended. Alterna-
tively, the system can use DQ7 (see the subsection on
DQ7: Data# Polling).
Read DQ7–DQ0
Twice
Toggle Bit
= Toggle?
No
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 μs after the program
command sequence is written, then returns to reading
array data.
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
Program/Erase
Operation Complete
Table 11 shows the outputs for Toggle Bit I on DQ6.
Figure 9 shows the toggle bit algorithm. Figure 22 in
the “AC Characteristics” section shows the toggle bit
timing diagrams. Figure 23 shows the differences be-
tween DQ2 and DQ6 in graphical form. See also the
subsection on DQ2: Toggle Bit II.
Note: The system should recheck the toggle bit even if
DQ5 = “1” because the toggle bit may stop toggling as DQ5
changes to “1.” See the subsections on DQ6 and DQ2 for
more information.
Figure 9. Toggle Bit Algorithm
December 21, 2005
Am29LV641MH/L
33
D A T A S H E E T
the toggle bit and DQ5 through successive read cy-
DQ2: Toggle Bit II
cles, determining the status as described in the previ-
ous paragraph. Alternatively, it may choose to perform
other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to de-
termine the status of the operation (top of Figure 9).
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
DQ5: Exceeded Timing Limits
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. (The system may use either OE# or CE# to con-
trol the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus-
pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era-
sure. Thus, both status bits are required for sector and
mode information. Refer to Table 11 to compare out-
puts for DQ2 and DQ6.
DQ5 indicates whether the program, erase, or
write-to-buffer time has exceeded a specified internal
pulse count limit. Under these conditions DQ5 produces a
“1,” indicating that the program or erase cycle was not suc-
cessfully completed.
The device may output a “1” on DQ5 if the system tries
to program a “1” to a location that was previously pro-
grammed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the
device halts the operation, and when the timing limit
has been exceeded, DQ5 produces a “1.”
Figure 9 shows the toggle bit algorithm in flowchart
form, and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the DQ6: Toggle Bit I subsection.
Figure 22 shows the toggle bit timing diagram. Figure
23 shows the differences between DQ2 and DQ6 in
graphical form.
In all these cases, the system must write the reset
command to return the device to the reading the array
(or to erase-suspend-read if the device was previously
in the erase-suspend-program mode).
DQ3: Sector Erase Timer
Reading Toggle Bits DQ6/DQ2
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not
erasure has begun. (The sector erase timer does not
apply to the chip erase command.) If additional
sectors are selected for erasure, the entire time-out
also applies after each additional sector erase com-
mand. When the time-out period is complete, DQ3
switches from a “0” to a “1.” If the time between addi-
tional sector erase commands from the system can be
assumed to be less than 50 µs, the system need not
monitor DQ3. See also the Sector Erase Command
Sequence section.
Refer to Figure 9 for the following discussion. When-
ever the system initially begins reading toggle bit sta-
tus, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically,
the system would note and store the value of the tog-
gle bit after the first read. After the second read, the
system would compare the new value of the toggle bit
with the first. If the toggle bit is not toggling, the device
has completed the program or erase operation. The
system can read array data on DQ7–DQ0 on the fol-
lowing read cycle.
After the sector erase command is written, the system
should read the status of DQ7 (Data# Polling) or DQ6
(Toggle Bit I) to ensure that the device has accepted
the command sequence, and then read DQ3. If DQ3 is
“1,” the Embedded Erase algorithm has begun; all fur-
ther commands (except Erase Suspend) are ignored
until the erase operation is complete. If DQ3 is “0,” the
device will accept additional sector erase commands.
To ensure the command has been accepted, the sys-
tem software should check the status of DQ3 prior to
and following each subsequent sector erase com-
mand. If DQ3 is high on the second status check, the
last command might not have been accepted.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys-
tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is tog-
gling, since the toggle bit may have stopped toggling
just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the de-
vice did not completed the operation successfully, and
the system must write the reset command to return to
reading array data.
The remaining scenario is that the system initially de-
termines that the toggle bit is toggling and DQ5 has
not gone high. The system may continue to monitor
Table 11 shows the status of DQ3 relative to the other
status bits.
34
Am29LV641MH/L
December 21, 2005
D A T A S H E E T
Write-to-Buffer-Abort-Reset command sequence to re-
DQ1: Write-to-Buffer Abort
turn the device to reading array data. See Write Buffer
Programming section for more details.
DQ1 indicates whether a Write-to-Buffer operation
was aborted. Under these conditions DQ1 produces a
“1”.
The
system
must
issue
the
Table 11. Write Operation Status
DQ7
DQ5
DQ2
Status
(Note 2)
DQ7#
0
DQ6
(Note 1)
DQ3
N/A
1
(Note 2)
DQ1
0
Embedded Program Algorithm
Embedded Erase Algorithm
Program-Suspended
Toggle
Toggle
0
0
No toggle
Toggle
Standard
Mode
N/A
Invalid (not allowed)
Data
Program
Suspend
Mode
Program-
Sector
Suspend
Non-Program
Read
Suspended Sector
Erase-Suspended
1
No toggle
Toggle
0
N/A
Toggle
N/A
N/A
N/A
Erase-
Sector
Suspend
Erase
Suspend
Mode
Non-Erase Suspended
Read
Data
Sector
Erase-Suspend-Program
(Embedded Program)
DQ7#
0
N/A
Busy (Note 3)
Abort (Note 4)
DQ7#
DQ7#
Toggle
Toggle
0
0
N/A
N/A
N/A
N/A
0
1
Write-to-
Buffer
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program, Embedded Erase, or Write-to-Buffer operation has exceeded the
maximum timing limits. Refer to the section on DQ5 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
3. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location.
4. DQ1 switches to ‘1’ when the device has aborted the write-to-buffer operation.
December 21, 2005
Am29LV641MH/L
35
D A T A S H E E T
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C
20 ns
20 ns
+0.8 V
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . –65°C to +125°C
–0.5 V
–2.0 V
Voltage with Respect to Ground
VCC (Note 1) . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V
VIO. . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V
20 ns
A9, OE#, ACC, and RESET#
(Note 2). . . . . . . . . . . . . . . . . . . .–0.5 V to +12.5 V
Figure 10. Maximum Negative
Overshoot Waveform
All other pins (Note 1). . . . . . –0.5 V to VCC +0.5 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V.
During voltage transitions, input or I/O pins may
overshoot VSS to –2.0 V for periods of up to 20 ns.
Maximum DC voltage on input or I/O pins is VCC +0.5 V.
See Figure 10. During voltage transitions, input or I/O
pins may overshoot to VCC +2.0 V for periods up to 20 ns.
See Figure 11.
20 ns
VCC
+2.0 V
VCC
+0.5 V
2. Minimum DC input voltage on pins A9, OE#, ACC, and
RESET# is –0.5 V. During voltage transitions, A9, OE#,
ACC, and RESET# may overshoot VSS to –2.0 V for
periods of up to 20 ns. See Figure 10. Maximum DC
input voltage on pin A9, OE#, ACC, and RESET# is
+12.5 V which may overshoot to +14.0 V for periods up
to 20 ns.
2.0 V
20 ns
20 ns
Figure 11. Maximum Positive
Overshoot Waveform
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This
is a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.
OPERATING RANGES
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C
Supply Voltages
VCC (regulated voltage range) . . . . . . . . . . . 3.0–3.6 V
VCC (full voltage range). . . . . . . . . . . . . . . . . 2.7–3.6 V
VIO (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . 1.65–3.6V
Notes:
1. Operating ranges define those limits between which the
functionality of the device is guaranteed.
2. See Ordering Information section for valid VCC/VIO range
combinations. The I/Os will not operate at 3 V when VIO
1.8 V.
=
36
Am29LV641MH/L
December 21, 2005
D A T A S H E E T
DC CHARACTERISTICS
CMOS Compatible
Parameter
Symbol
Parameter Description
(Notes)
Test Conditions
VIN = VSS to VCC
Min
Typ
Max
Unit
,
ILI
Input Load Current (1)
±1.0
µA
VCC = VCC max
ILIT
ILR
A9, ACC Input Load Current
Reset Leakage Current
VCC = VCC max; A9 = 12.5 V
VCC = VCC max; RESET# = 12.5 V
35
35
µA
µA
V
OUT = VSS to VCC
,
ILO
Output Leakage Current
±1.0
µA
VCC = VCC max
5 MHz
1 MHz
15
15
30
10
50
20
20
50
20
60
VCC Active Read Current
(2, 3)
ICC1
CE# = VIL, OE# = VIH,
mA
ICC2
ICC3
ICC4
VCC Initial Page Read Current (2, 3)
VCC Intra-Page Read Current (2, 3)
VCC Active Write Current (3, 4)
CE# = VIL, OE# = VIH
CE# = VIL, OE# = VIH
CE# = VIL, OE# = VIH
mA
mA
mA
CE#, RESET# = VCC ± 0.3 V,
WP# = VIH
ICC5
ICC6
ICC7
VCC Standby Current (3)
VCC Reset Current (3)
1
1
1
5
5
5
µA
µA
µA
RESET# = VSS ± 0.3 V, WP# = VIH
V
IH = VCC ± 0.3 V;
Automatic Sleep Mode (3, 5)
VIL = VSS ± 0.3 V, WP# = VIH
ACC pin
VCC pin
10
30
20
60
mA
mA
V
IACC
ACC Accelerated Program Current (3) CE# = VIL, OE# = VIH
VIL1
VIH1
VIL2
VIH2
Input Low Voltage 1(5, 6)
Input High Voltage 1 (5, 6)
Input Low Voltage 2 (5, 7)
Input High Voltage 2 (5, 7)
–0.5
1.9
0.8
VCC + 0.5
0.3 x VIO
VIO + 0.5
V
–0.5
1.9
V
V
Voltage for ACC Program
VCC = 2.7 –3.6 V
Acceleration
VHH
VID
11.5
11.5
12.5
V
V
Voltage for Autoselect and Temporary
VCC = 2.7 –3.6 V
12.5
Sector Unprotect
VOL
VOH1
Output Low Voltage
IOL = 4.0 mA, VCC = VCC min = VIO
IOH = –2.0 mA, VCC = VCC min = VIO 0.85 VIO
0.15 x VIO
V
V
V
V
Output High Voltage
VOH2
IOH = –100 µA, VCC = VCC min = VIO
VIO–0.4
2.3
VLKO
Low VCC Lock-Out Voltage (8)
2.5
Notes:
1. On the WP#/ACC pin only, the maximum input load current when WP# = VIL is 5.0 µA.
2. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.
3. Maximum ICC specifications are tested with VCC = VCCmax.
4. ICC active while Embedded Erase or Embedded Program is in progress.
5. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. TIf VIO < VCC, maximum VIL
for CE# and DQ I/Os is 0.3 VIO. If VIO < VCC, minimum VIH for CE# and DQ I/Os is 0.7 VIO. Maximum VIH for these connections is
VIO + 0.3 V
6. VCC voltage requirements.
7. VIO voltage requirements.
8. Not 100% tested.
9. Includes RY/BY#
December 21, 2005
Am29LV641MH/L
37
D A T A S H E E T
TEST CONDITIONS
Table 12. Test Specifications
Test Condition All Speeds
Output Load 1 TTL gate
3.3 V
Unit
2.7 kΩ
Device
Under
Test
Output Load Capacitance, CL
(including jig capacitance)
30
pF
Input Rise and Fall Times
Input Pulse Levels
5
ns
V
C
L
6.2 kΩ
0.0–3.0
Input timing measurement
reference levels (See Note)
1.5
V
V
Output timing measurement
reference levels
0.5 VIO
Note: Diodes are IN3064 or equivalent
Figure 12. Test Setup
Note: If VIO < VCC, the reference level is 0.5 VIO.
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Changing, State Unknown
Don’t Care, Any Change Permitted
Does Not Apply
Center Line is High Impedance State (High Z)
3.0 V
1.5 V
0.5 VIO V
Input
Measurement Level
Output
0.0 V
Note: If VIO < VCC, the input measurement reference level is 0.5 VIO.
Figure 13. Input Waveforms and
Measurement Levels
38
Am29LV641MH/L
December 21, 2005
D A T A S H E E T
AC CHARACTERISTICS
Read-Only Operations
Parameter
Speed Options
JEDE
C
101R,
101 112R 112 120R 120 Unit
Std. Description
Test Setup
90R
tAVAV tRC Read Cycle Time (Note 1)
tAVQV tACC Address to Output Delay
Min
90
90
100
100
110
110
110
120
120
120
ns
ns
CE#, OE# =
VIL
Max
tELQV tCE Chip Enable to Output Delay
tPACC Page Access Time
OE# = VIL
Max
Max
Max
90
25
25
100
30
ns
ns
ns
30
30
40
40
30
30
40
40
tGLQV tOE Output Enable to Output Delay
30
Chip Enable to Output High Z (Note
1)
tEHQZ tDF
Max
Max
16
16
ns
ns
Output Enable to Output High Z
tGHQZ tDF
(Note 1)
Output Hold Time From Addresses,
tAXQX tOH
Min
Min
Min
0
0
ns
ns
ns
CE# or OE#, Whichever Occurs First
Read
Output Enable
tOEH Hold Time (Note
Toggle and
Data# Polling
10
1)
Notes:
1. Not 100% tested.
2. See Figure 12 and Table 12 for test specifications.
3. AC Specifications listed are tested with VIO = VCC. Contact AMD for information on AC operation with VIO ≠ VCC
.
tRC
Addresses Stable
Addresses
CE#
tACC
tRH
tRH
tDF
tOE
OE#
WE#
tOEH
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
Figure 14. Read Operation Timings
December 21, 2005
Am29LV641MH/L
39
D A T A S H E E T
AC CHARACTERISTICS
Same Page
A21
-
-
A2
A0
A1
Ad
Aa
tACC
Ab
tPACC
Ac
tPACC
tPACC
Data Bus
Qa
Qb
Qc
Qd
CE#
OE#
Figure 15. Page Read Timings
40
Am29LV641MH/L
December 21, 2005
D A T A S H E E T
AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
JEDEC
Std.
Description
All Speed Options
Unit
RESET# Pin Low (During Embedded Algorithms)
to Read Mode (See Note)
tReady
Max
Max
20
μs
RESET# Pin Low (NOT During Embedded
Algorithms) to Read Mode (See Note)
tReady
500
ns
tRP
tRH
RESET# Pulse Width
Min
Min
Min
500
50
ns
ns
μs
Reset High Time Before Read (See Note)
RESET# Low to Standby Mode
tRPD
20
Notes:
1. Not 100% tested.
2. AC Specifications listed are tested with VIO = VCC. Contact AMD for information on AC operation with VIO ≠ VCC
.
AC Characteristics
tRC
Addresses Stable
Addresses
CE#
tACC
tRH
tRH
tDF
tOE
OE#
WE#
tOEH
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
Figure 16. Read Operation Timings
December 21, 2005
Am29LV641MH/L
41
D A T A S H E E T
CE#, OE#
RESET#
tRH
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
CE#, OE#
RESET#
tRP
Figure 17. Reset Timings
42
Am29LV641MH/L
December 21, 2005
D A T A S H E E T
AC CHARACTERISTICS
Erase and Program Operations
Parameter
Speed Options
JEDEC
tAVAV
Std.
tWC
tAS
Description
90R
101
112
120
Unit
ns
Write Cycle Time (Note 1)
Address Setup Time
Min
Min
90
100
110
120
tAVWL
0
15
45
0
ns
Address Setup Time to OE# low during toggle bit
polling
tASO
tAH
Min
Min
Min
ns
ns
ns
tWLAX
Address Hold Time
Address Hold Time From CE# or OE# high
during toggle bit polling
tAHT
tDVWH
tWHDX
tDS
tDH
Data Setup Time
Min
Min
Min
45
0
ns
ns
ns
Data Hold Time
tOEPH
Output Enable High during toggle bit polling
20
Read Recovery Time Before Write
(OE# High to WE# Low)
tGHWL
tGHWL
Min
0
ns
tELWL
tWHEH
tWLWH
tWHDL
tCS
tCH
CE# Setup Time
Min
Min
Min
Min
Typ
0
0
ns
ns
ns
ns
µs
CE# Hold Time
tWP
Write Pulse Width
35
30
352
tWPH
Write Pulse Width High
Write Buffer Program Operation (Notes 2, 3)
Effective Word Program Time, using the Write
Buffer (Notes 2, 4)
Typ
22
µs
Effective Accelerated Word Program Time, using
the Write Buffer (Notes 2, 4)
tWHWH1
tWHWH1
Typ
Typ
Typ
17.6
100
90
µs
µs
µs
Single Word Program Operation (Note 2, 5)
Accelerated Single Word Programming
Operation (Note 2, 5)
tWHWH2
tWHWH2 Sector Erase Operation (Note 2)
Typ
Min
Min
Max
0.5
250
50
4
sec
ns
tVHH
tVCS
VHH Rise and Fall Time (Note 1)
VCC Setup Time (Note 1)
µs
tPOLL
Program Valid Before Status Polling (Note 7)
µs
Notes:
1. Not 100% tested.
2. See the “Erase And Programming Performance” section for more information.
3. For 1–16 words programmed.
4. Effective write buffer specification is based upon a 16-word write buffer operation.
5. Word programming specification is based upon a single word programming operation not utilizing the write buffer.
6. AC Specifications listed are tested with VIO = VCC. Contact AMD for information on AC operation with VIO ≠ VCC
7. When using the program suspend/resume feature, if the suspend command is issued within tPOLL, tPOLL must be fully
.
re-applied upon resuming the programming operation. If the suspend command is issued after tPOLL, tPOLL is not required
again prior to reading the status bits upon resuming.
December 21, 2005
Am29LV641MH/L
43
D A T A S H E E T
AC CHARACTERISTICS
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tAS
PA
tWC
Addresses
555h
PA
PA
tAH
CE#
OE#
tCH
tPOLL
tWP
WE#
Data
tWPH
tWHWH1
tCS
tDS
tDH
PD
DOUT
A0h
Status
tBUSY
tRB
RY/BY#
VCC
tVCS
Notes:
1. PA = program address, PD = program data, DOUT is the true data at the program address.
2. Illustration shows device in word mode.
Figure 18. Program Operation Timings
VHH
VIL or VIH
VIL or VIH
ACC
tVHH
tVHH
Figure 19. Accelerated Program Timing Diagram
44
Am29LV641MH/L
December 21, 2005
D A T A S H E E T
AC CHARACTERISTICS
Erase Command Sequence (last two cycles)
Read Status Data
VA
tAS
SA
tWC
VA
Addresses
CE#
2AAh
555h for chip erase
tAH
tCH
OE#
tWP
WE#
tWPH
tWHWH2
tCS
tDS
tDH
In
Data
VCC
Complete
55h
30h
Progress
10 for Chip Erase
tVCS
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”.
2. These waveforms are for the word mode.
Figure 20. Chip/Sector Erase Operation Timings
December 21, 2005
Am29LV641MH/L
45
D A T A S H E E T
AC CHARACTERISTICS
tRC
VA
Addresses
VA
VA
tPOLL
tACC
tCE
CE#
tCH
tOE
OE#
tOEH
tDF
WE#
tOH
High Z
High Z
DQ15 and DQ7
Valid Data
Complement
Complement
True
DQ14–DQ8, DQ6–DQ0
RY/BY#
Status Data
True
Valid Data
Status Data
tBUSY
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
Figure 21. Data# Polling Timings
(During Embedded Algorithms)
46
Am29LV641MH/L
December 21, 2005
D A T A S H E E T
AC CHARACTERISTICS
tAHT
tAS
Addresses
tAHT
tASO
CE#
tOEH
WE#
tCEPH
tOEPH
OE#
tDH
Valid Data
tOE
Valid
Status
Valid
Status
Valid
Status
DQ6/DQ2
Valid Data
(first read)
(second read)
(stops toggling)
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status
read cycle, and array data read cycle
Figure 22. Toggle Bit Timings
(During Embedded Algorithms)
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase
Complete
WE#
Erase
Erase Suspend
Read
DQ6
DQ2
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle
DQ2 and DQ6.
Figure 23. DQ2 vs. DQ6
December 21, 2005
Am29LV641MH/L
47
D A T A S H E E T
AC CHARACTERISTICS
Temporary Sector Unprotect
Parameter
JEDEC
Std
Description
All Speed Options
Unit
tVIDR
VID Rise and Fall Time (See Note)
Min
Min
500
ns
RESET# Setup Time for Temporary Sector
Unprotect
tRSP
4
µs
Notes:
1. Not 100% tested.
2. AC Specifications listed are tested with VIO = VCC. Contact AMD for information on AC operation with VIO ≠ VCC
.
VID
VID
RESET#
VSS, VIL,
or VIH
VSS, VIL,
or VIH
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
tRSP
Figure 24. Temporary Sector Group Unprotect Timing Diagram
48
Am29LV641MH/L
December 21, 2005
D A T A S H E E T
AC CHARACTERISTICS
V
ID
IH
V
RESET#
SA, A6,
A1, A0
Valid*
Sector Group Protect or Unprotect
60h 60h
Valid*
Valid*
Status
Verify
40h
Data
Sector Group Protect: 150 µs,
Sector Group Unprotect: 15 ms
1 µs
CE#
WE#
OE#
* For sector group protect, A6:A0 = 0xx0010. For sector group unprotect, A6:A0 = 1xx0010.
Figure 25. Sector Group Protect and Unprotect Timing Diagram
December 21, 2005
Am29LV641MH/L
49
D A T A S H E E T
AC CHARACTERISTICS
Alternate CE# Controlled Erase and Program Operations
Parameter
Speed Options
101, 112, 120,
JEDEC
tAVAV
Std.
tWC
tAS
Description
90R 101R 112R 120R Unit
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
Min
Min
Min
Min
Min
90
100
110
120
ns
ns
ns
ns
ns
tAVWL
tELAX
tDVEH
tEHDX
0
45
45
0
tAH
tDS
tDH
Read Recovery Time Before Write
(OE# High to WE# Low)
tGHEL
tGHEL
Min
0
ns
tWLEL
tEHWH
tELEH
tEHEL
tWS
tWH
tCP
WE# Setup Time
Min
Min
Min
Min
Typ
0
0
ns
ns
ns
ns
µs
WE# Hold Time
CE# Pulse Width
45
30
352
tCPH
CE# Pulse Width High
Write Buffer Program Operation (Notes 2, 3)
Effective Word Program Time, using the Write
Buffer (Notes 2, 4)
Typ
22
µs
Effective Accelerated Word Program Time, using
the Write Buffer (Notes 2, 4)
tWHWH1
tWHWH1
Typ
Typ
Typ
17.6
100
90
µs
µs
µs
Single Word Program Operation (Note 2, 5)
Accelerated Single Word Programming Operation
(Note 2, 5)
tWHWH2
tWHWH2 Sector Erase Operation (Note 2)
Typ
Min
Max
0.5
50
4
sec
ns
tRH
Reset High Time Before Write (Note 1)
tPOLL
Program Valid Before Status Polling (Note 7)
µs
Notes:
1. Not 100% tested.
2. See the “Erase And Programming Performance” section for more information.
3. For 1–16 words programmed.
4. Effective write buffer specification is based upon a 16-word write buffer operation.
5. Word programming specification is based upon a single word programming operation not utilizing the write buffer.
6. AC Specifications listed are tested with VIO = VCC. Contact AMD for information on AC operation with VIO ≠ VCC
7. When using the program suspend/resume feature, if the suspend command is issued within tPOLL, tPOLL must be fully
.
re-applied upon resuming the programming operation. If the suspend command is issued after tPOLL, tPOLL is not required
again prior to reading the status bits upon resuming.
50
Am29LV641MH/L
December 21, 2005
D A T A S H E E T
AC CHARACTERISTICS
555 for program
PA for program
2AA for erase
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tAS
tAH
tWH
WE#
OE#
tPOLL
tGHEL
tWHWH1 or 2
tCP
CE#
tWS
tCPH
tDS
tBUSY
tDH
DQ7#,
DQ15
DOUT
Data
tRH
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.
4. Waveforms are for the word mode.
Figure 26. Alternate CE# Controlled Write (Erase/Program)
Operation Timings
December 21, 2005
Am29LV641MH/L
51
D A T A S H E E T
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ (Note 1) Max (Note 2)
Unit
sec
sec
µs
Comments
Sector Erase Time
0.5
64
15
Excludes 00h programming prior to
erasure (Note 6)
Chip Erase Time
128
800
Single Word Program Time (Note 3)
100
Accelerated Single Word Program Time
(Note 3)
90
352
22
720
1800
113
µs
µs
µs
µs
µs
Total Write Buffer Program Time
(Note 4)
Excludes system level overhead (Note 7)
Effective Word Program Time, using the
Write Buffer (Note 5)
Total Accelerated Write Buffer Program
Time (Note 4)
282
17.6
1560
98
Effective Accelerated Word Program
Time, using the Write Buffer (Note 4)
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC. Programming specifications assume that
all bits are programmed to 00h.
2. Maximum values are measured at VCC = 3.0 V, worst case temperature. Maximum values are valid up to and including 100,000
program/erase cycles.
3. Word programming specification is based upon a single word/byte programming operation not utilizing the write buffer.
4. For 1-16 words programmed in a single write buffer programming operation.
5. Effective write buffer specification is calculated on a per-word basis for a 16-word write buffer operation.
6. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.
7. System-level overhead is the time required to execute the command sequence(s) for the program command. See Table 10 for
further information on command definitions.
8. The device has a minimum erase and program cycle endurance of 100,000 cycles.
LATCHUP CHARACTERISTICS
Description
Min
Max
Input voltage with respect to VSS on all pins except I/O pins
(including A9, OE#, and RESET#)
–1.0 V
12.5 V
Input voltage with respect to VSS on all I/O pins
VCC Current
–1.0 V
VCC + 1.0 V
+100 mA
–100 mA
Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.
52
Am29LV641MH/L
December 21, 2005
D A T A S H E E T
TSOP PIN CAPACITANCE
Parameter
Symbol
Parameter Description
Input Capacitance
Test Setup
VIN = 0
Typ
6
Max
7.5
12
Unit
pF
CIN
COUT
CIN2
Output Capacitance
VOUT = 0
VIN = 0
8.5
7.5
pF
Control Pin Capacitance
9
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
DATA RETENTION
Parameter Description
Test Conditions
150°C
Min
10
Unit
Years
Years
Minimum Pattern Data Retention Time
125°C
20
December 21, 2005
Am29LV641MH/L
53
D A T A S H E E T
PHYSICAL DIMENSIONS
TS 048—48-Pin Standard Thin Small Outline Package
Dwg rev AA; 10/99
54
Am29LV641MH/L
December 21, 2005
D A T A S H E E T
PHYSICAL DIMENSIONS
TSR048—48-Pin Reverse Thin Small Outline Package
Dwg rev AA; 10/99
December 21, 2005
Am29LV641MH/L
55
D A T A S H E E T
REVISION SUMMARY
Figure 5. Program Suspend/Program Resume
Revision A (August 3, 2001)
Changed wait from 1ms to 15μs.
Initial release as abbreviated Advance Information
data sheet.
Erase Resume/Erase Resume Commands
Added a maximum of 20μs.
Revision A+1 (October 3, 2001)
Alternate CE# Controlled Erase and Program
Operations
Global
Added 120 ns speed option.
Added TRH parameter to table.
Ordering Information
Special package handling instructions
Changed operating voltage range for 90 ns device.
Modified the special handling wording.
Physical Dimensions
DC Characteristics table
Added section.
Deleted the IACC specification row.
Revision B (March 14, 2002)
CFI
Global
Changed text in the third paragraph of CFI to read
“reading array data.”
Expanded data sheet to full specification version.
Revision B+3 (September 10, 2002)
Revision B+1 (April 26, 2002)
Product Selector Guide
MirrorBit 64 Mbit Device Family
Added Note 2.
Deleted Am29LV641MT/B.
Ordering Information
Figure 2, In-System Sector Group
Protect/Unprotect Algorithms
Added Note 1.
Added A3 and A2 address requirement.
Sector Erase Command Sequence
Sector Group Protection/Unprotection
Deleted statement that describes the outcome of
when the Embedded Erase operation is in progress.
Deleted reference to alternate method of sector pro-
tection.
Revision B+4 (October 15, 2002)
Autoselect Command
Erase and Programming Performance
Substituted text with ID code table for easier refer-
ence.
Changed values for typical and maximum times on
word program time and write buffer program time to
TBD. Inserted TBD for maximum chip erase time.
Table 10, Command Definitions
Combined Notes 4 and 5 from Revision B. Corrected
number of cycles indicated for Write-to-Buffer and Au-
toselect Device ID command sequences.
Revision B+5 (November 26, 2002)
Product Selector Guide and Read-Only
Characteristics
Figure 25, Sector Group Protect and Unprotect
Timing Diagram
Added a 30 ns option to tPACC and tOE standard for the
112R and 120R speed options.
In the note, added A3 and A2 address requirement.
Customer Lockable: SecSi Sector NOT
Programmed or Protected at the factory.
Revision B+2 (August 1, 2002)
Mirrorbit 64 MBIT Device Family
Added second bullet, SecSi sector-protect verify text
and figure 3.
Added 64 Fortified BGA to table.
Program Suspend/Program Resume Command
Sequence
SecSi Sector Flash Memory Region, and Enter
SecSi Sector/Exit SecSi Sector Command
Sequence
Changed program operation wait time from 1ms to
15μs.
Noted that the ACC function and unlock bypass modes
are not available when the SecSi sector is enabled.
56
Am29LV641MH/L
December 21, 2005
D A T A S H E E T
Byte/Word Program Command Sequence, Sector
Erase Command Sequence, and Chip Erase
Command Sequence
Revision B+7 (June 12, 2003)
Ordering Information
Added 90R speed grade, modified note.
Noted that the SecSi Sector, autoselect, and CFI func-
tions are unavailable when a program or erase opera-
tion is in progress.
Erase and programming Performance
Modified table, inserted values for Typical.
Common Flash Memory Interface (CFI)
Revision B+8 (February 13, 2004)
Changed CFI website address
Table 1 Device Bus Operations
Figure 6. Program Suspend/Program Resume
Modified ACC column, replaced instances of X to L/H.
Change wait time to 15 μs.
Word/Byte Program Command Sequence
CMOS Compatible
Removed reference to byte.
Added ILR row to table
Erase Suspend/Erase Resume Commands
Changed VIH1 and VIH2 minimum to 1.9.
Removed typos in notes.
Added note on flash device performance during sus-
pend/erase mode.
Hardware Reset, CMOS Tables, Erase and Program
Operations, Temporary Sector Unprotect, and
Alternate CE# Controlled Erase and Program
Operations
Table 10 Command Definitions
Modified Program/Erase Suspend and Program/Erase
Resume from BA to XXX (Don’t Care).
Added Note.
AC Characteristics - Erase and Program
Operations
Revision B+6 (February 16, 2003)
Added tPOLL information and note.
Distinctive Characteristics
AC Characteristics - Alternate CE# Controlled
Erase and Program Operations
Corrected performance characteristics.
Added tPOLL information and note.
Product Selector Guide
Added note 3.
AC Characteristics Figures
Added tPOLL timing to Figure 18, Program Operation
Timings; Figure 21, Data# Polling Timings (During
Embedded Algorithms); and Figure 26, Alternate CE#
Controlled Write (Erase/Program) Operation Timings.
Ordering Information
Corrected Valid Combination to reflect speed option
changes.
Added Note.
Erase and Programming Performance
AC Characteristics
Removed reference to byte.
Removed 90, 90R speed option.
Trademarks
Added Note
Updated.
Input values in the tWHWH1 and tWHWH2 parameters in
the Erase and Program Options table that were previ-
ously TBD. Also added notes 5 and 6.
Revision B+9 (August 23, 2004)
Added Max programming specifications.
Input values in the tWHWH1 and tWHWH2 parameters in
the Alternate CE# Controlled Erase and Program Op-
tions table that were previously TBD. Also added notes
5.
Added notation referencing superseding documenta-
tion.
Revision B+10 (December 21, 2005)
Erase and Programming Performance
Global
Input values into table that were previously TBD.
This product has been retired and is not available for
designs. For new and current designs, S29GL064A
supersedes Am29LV641M H/L and is the factory-rec-
ommended migration path. Please refer to the
S29GL064A datasheet for specifications and ordering
information. Availability of this document is retained for
reference and historical purposes only.
Added note 3 and 4.
December 21, 2005
Am29LV641MH/L
57
D A T A S H E E T
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limita-
tion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as con-
templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor de-
vices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design mea-
sures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating
conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign
Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au-
thorization by the respective government entity will be required for export of those products.
Trademarks
Copyright © 2004-2005 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
58
Am29LV641MH/L
December 21, 2005
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