MACH211SP-12VC [AMD]
High-Density EE CMOS Programmable Logic; 高密度EE CMOS可编程逻辑
| 型号： | MACH211SP-12VC |
| 厂家： | 
AMD |
| 描述： | High-Density EE CMOS Programmable Logic |
| 文件： | 总37页 (文件大小：253K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FINAL
COM’L: -7.5/10/12/15/20
IND: -10/12/14/18/24
MACH211SP-7/10/12/15/20
High-Density EE CMOS Programmable Logic
DISTINCTIVE CHARACTERISTICS
■ JTAG-Compatible, 5-V in-system programming
■ Peripheral Component Interconnect (PCI)
compliant (-7/-10)
■ 44 Pins
■ Programmable power-down mode
■ 32 Outputs
■ 64 Macrocells
■ 7.5 ns t Commercial
PD
10 ns t Industrial
■ 64 Flip-flops; 2 clock choices
■ 4 “PAL26V16” blocks with buried macrocells
■ Improved routing over the MACH210
PD
■ 133 MHz f
CNT
■ 34 Bus-Friendly™ Inputs and I/Os
IN-SYSTEM PROGRAMMING
In-system programming allows the MACH211SP to be
programmed while soldered onto a system board. Pro-
gramming the MACH211SP in-system yields numer-
ous benefits at all stages of development: prototyping,
manufacturing, and in the field. Since insertion into a
programmer isn’t needed, multiple handling steps and
the resulting bent leads are eliminated.The design can
be modified in-system for design changes and debug-
ging while prototyping, programming boards in produc-
tion, and field upgrades.
The MACH211SP offers advantages not available in
other CPLD architectures with in-system programming.
MACH devices have extensive routing resources for
pin-out retention; design changes resulting in pin-out
changes for other CPLDs cancel the advantages of
in-system programming. The MACH211SP can be em-
ployed in any JTAG (IEEE 1149.1) compliant chain.
GENERAL DESCRIPTION
The MACH211SP is a member of AMD’s EE CMOS
Performance Plus MACH 2 device family. This device
has approximately six times the logic macrocell capa-
bility of the popular PAL22V10 without loss of speed.
programmable polarity. If a registered configuration is
chosen, the register can be configured as D-type or
T-type to help reduce the number of product terms.The
register type decision can be made by the designer or
by the software. All output macrocells can be con-
nected to an I/O cell. If a buried macrocell is desired,
the internal feedback path from the macrocell can be
used, which frees up the I/O pin for use as an input.
The MACH211SP consists of four PAL blocks inter-
connected by a programmable switch matrix. The four
PAL blocks are essentially “PAL26V16” structures com-
plete with product-term arrays and programmable
macrocells, which can be programmed as high speed
or low power, and buried macrocells. The switch matrix
connects the PAL blocks to each other and to all input
pins, providing a high degree of connectivity between
the fully-connected PAL blocks. This allows designs to
be placed and routed efficiently.
The MACH211SP has dedicated buried macrocells
which, in addition to the capabilities of the output
macrocell, also provide input registers or latches for
use in synchronizing signals and reducing setup time
requirements.
The MACH211SP is an enhanced version of the
MACH211, adding the JTAG-compatible in-system pro-
gramming feature.
The MACH211SP has two kinds of macrocell: output
and buried. The MACH211SP output macrocell pro-
vides registered, latched, or combinatorial outputs with
Publication# 20405 Rev: B Amendment/0
Issue Date: February 1996
BLOCK DIAGRAM
I/O –I/O
I/O –I/O
8 15
0
7
8
8
8
8
I/O Cells
8
I/O Cells
8
8
8
2
Macrocells
Macrocells
Macrocells
Macrocells
OE
52 x 68
AND Logic Array
and
OE
52 x 68
AND Logic Array
and
Logic Allocator
Logic Allocator
26
26
Switch Matrix
26
26
52 x 68
AND Logic Array
and
52 x 68
AND Logic Array
and
2
Logic Allocator
Logic Allocator
OE
OE
2
Macrocells
8
Macrocells
Macrocells
8
Macrocells
8
8
8
8
8
8
I/O Cells
I/O Cells
I/O –I/O
I/O –I/O
16 23
24
31
CLK /I
0
0
1
CLK /I
1
20405B-1
2
MACH211SP-7/10/12/15/20
CONNECTION DIAGRAM MACH211SP
Top View
44-Pin PLCC
40
1 44 43 42 41
6
5
4
3
2
I/O27
I/O26
I/O25
I/O24
TDO
39
7
8
I/O5
I/O6
38
37
36
35
34
I/O7
9
TDI
10
11
12
CLK0/I0
GND
TCK
GND
CLK1/I1
TMS
33
32
13
14
I/O8
I/O23
I/O22
I/O21
31
30
29
I/O9
15
16
17
I/O10
I/O11
28
18 19 20 21 22 23 24 25 26 27
20405B-2
PIN DESIGNATIONS
CLK/I = Clock or Input
TDI = Test Data In
TCK = Test Clock
GND = Ground
I
= Input
I/O = Input/Output
= Supply Voltage
TMS = Test Mode Select
TDO = Test Data Out
V
CC
MACH211SP-7/10/12/15/20
3
CONNECTION DIAGRAM MACH211SP
Top View
44-Pin TQFP
1
2
3
4
5
6
7
8
33
32
31
30
29
28
27
26
25
24
23
I/O5
I/O6
I/O7
I/O27
I/O26
I/O25
I/O24
TDO
GND
CLK1/I1
TMS
TDI
CLK0/I0
GND
TCK
I/O8
I/O9
I/O10
I/O11
9
10
11
I/O23
I/O22
I/O21
20405B-3
PIN DESIGNATIONS
CLK/I = Clock or Input
TDI = Test Data In
TCK = Test Clock
GND = Ground
I
= Input
TMS = Test Mode Select
TDO = Test Data Out
I/O = Input/Output
V
= Supply Voltage
CC
4
MACH211SP-7/10/12/15/20
ORDERING INFORMATION
Commercial Products
AMD programmable logic products for commercial applications are available with several ordering options. The order number
(Valid Combination) is formed by a combination of:
MACH 211
SP
-7
J
C
FAMILY TYPE
OPTIONAL PROCESSING
MACH = Macro Array CMOS High-Speed
Blank = Standard Processing
DEVICE NUMBER
OPERATING CONDITIONS
211 = 64 Macrocells, 44 Pins,
Power-Down mode,
C = Commercial (0°C to +70°C)
Bus-Friendly Inputs and I/Os
PACKAGE TYPE
J = 44-Pin Plastic Leaded Chip
Carrier (PL 044)
V = 44-Pin Thin Quad Flat Pack
(PQT044)
PRODUCT DESIGNATION
SP = In-system Programmable
SPEED
-7 = 7.5 ns t
PD
-10 = 10 ns t
-12 = 12 ns t
-15 = 15 ns t
-20 = 20 ns t
PD
PD
PD
PD
Valid Combinations
Valid Combinations
MACH211SP-7
The Valid Combinations table lists configurations planned to
be supported in volume for this device. Consult the local AMD
sales office to confirm availability of specific valid combina-
tions and to check on newly released combinations.
MACH211SP-10
MACH211SP-12
MACH211SP-15
MACH211SP-20
JC, VC
MACH211SP-7/10/12/15/20 (Com’l)
5
ORDERING INFORMATION
Industrial Products
AMD programmable logic products for industrial applications are available with several ordering options.The order number (Valid
Combination) is formed by a combination of:
MACH 211
SP -10
J
I
FAMILY TYPE
OPTIONAL PROCESSING
MACH = Macro Array CMOS High-Speed
Blank = Standard Processing
DEVICE NUMBER
OPERATING CONDITIONS
211 = 64 Macrocells, 44 Pins,
Power-Down mode,
I = Industrial (–40°C to +85°C)
Bus-Friendly Inputs and I/Os
PACKAGE TYPE
J = 44-Pin Plastic Leaded Chip
Carrier (PL 044)
PRODUCT DESIGNATION
SP = In-system Programmable
SPEED
-10 = 10 ns t
-12 = 12 ns t
PD
PD
-14 = 14.5 ns t
PD
-18 = 18 ns t
-24 = 24 ns t
PD
PD
Valid Combinations
Valid Combinations
MACH211SP-10
The Valid Combinations table lists configurations planned to
be supported in volume for this device. Consult the local AMD
sales office to confirm availability of specific valid combina-
tions and to check on newly released combinations.
MACH211SP-12
MACH211SP-14
MACH211SP-18
MACH211SP-24
JI
6
MACH211SP-10/12/14/18/24 (Ind)
Table 1. Logic Allocation
Macrocell
Output Buried
FUNCTIONAL DESCRIPTION
The MACH211SP consists of four PAL blocks con-
nected by a switch matrix.There are 32 I/O pins feeding
the switch matrix. These signals are distributed to the
four PAL blocks for efficient design implementation.
There are two clock pins that can also be used as ded-
icated inputs.
Available Clusters
C , C , C
M
M
M
M
M
0
2
4
6
8
0
1
2
M
M
M
M
M
C , C , C , C
1
3
5
7
9
0
1
2
3
4
C , C , C , C
1
2
3
The PAL Blocks
C , C , C , C
2
3
4
5
Each PAL block in the MACH211SP (Figure 1) contains
a 64-product-term logic array, a logic allocator, 8 output
macrocells, 8 buried macrocells, and 8 I/O cells. The
switch matrix feeds each PAL block with 26 inputs.This
makes the PAL block look effectively like an indepen-
dent “PAL26V16” with 8 buried macrocells.
C , C , C , C
3
4
5
6
C , C , C , C
4
5
6
7
C , C , C , C
5
6
7
8
C , C , C , C
6
7
8
9
In addition to the logic product terms, two output enable
product terms, an asynchronous reset product term,
and an asynchronous preset product term are pro-
vided. One of the two output enable product terms can
be chosen within each I/O cell in the PAL block. All
flip-flops within the PAL block are initialized together.
C , C , C , C
7
8
9
10
C , C , C , C
11
8
9
10
M
M
M
C , C , C , C
10
12
14
9
10
11
12
M
M
M
C
C
C
, C , C , C
11 12
11
13
15
10
11
13
14
15
The Switch Matrix
, C , C , C
12 13
The MACH211SP switch matrix is fed by the inputs and
feedback signals from the PAL blocks. Each PAL block
provides 16 internal feedback signals and 8 I/O feed-
back signals. The switch matrix distributes these sig-
nals back to the PAL blocks in an efficient manner that
also provides for high performance. The design soft-
ware automatically configures the switch matrix when
fitting a design into the device.
, C , C , C
12
13
14
C
, C , C
14 15
13
C
, C
15
14
feedback whether configured with or without the
flip-flop. The registers can be configured as D-type or
T-type, allowing for product-term optimization.
The flip-flops can individually select one of two clock/
gate pins, which are also available as data inputs. The
registers are clocked on the LOW-to-HIGH transition of
the clock signal. The latch holds its data when the gate
input is HIGH, and is transparent when the gate input
is LOW. The flip-flops can also be asynchronously ini-
tialized with the common asynchronous reset and pre-
set product terms.
The Product-term Array
The MACH211SP product-term array consists of 64
product terms for logic use, and 4 special-purpose
product terms. Two of the special-purpose product
terms provide programmable output enable; one pro-
vides asynchronous reset, and one provides asynchro-
nous preset.
The Logic Allocator
The buried macrocells are the same as the output
macrocells if they are used for generating logic. In that
case, the only thing that distinguishes them from the
output macrocells is the fact that there is no I/O cell
connection, and the signal is only used internally. The
buried macrocell can also be configured as an input
register or latch.
The logic allocator in the MACH211SP takes the 64
logic product terms and allocates them to the 16
macrocells as needed. Each macrocell can be driven
by up to 16 product terms. The design software auto-
matically configures the logic allocator when fitting the
design into the device.
The I/O Cell
Table 1 illustrates which product term clusters are avail-
able to each macrocell within a PAL block. Refer to
Figure 1 for cluster and macrocell numbers.
The I/O cell in the MACH211SP consists of a
three-state output buffer. The three-state buffer can be
configured in one of three ways: always enabled, al-
ways disabled, or controlled by a product term. If prod-
uct term control is chosen, one of two product terms
may be used to provide the control. The two product
terms that are available are common to all I/O cells in a
PAL block.
The Macrocell
The MACH211SP has two types of macrocell: output
and buried. The output macrocells can be configured
as either registered, latched, or combinatorial, with pro-
grammable polarity. The macrocell provides internal
MACH211SP-7/10/12/15/20
7
These choices make it possible to use the macrocell as
an output, an input, a bidirectional pin, or a three-state
output for use in driving a bus.
should be programmed. The configuration file is dis-
cussed in detail in the MACHPRO software manual.
The MACH211SP devices tristate the outputs during
programming.They have one security bit which inhibits
program and verify.This allows the user to protect pro-
prietary patterns and designs.
Power-Down Mode
The MACH211SP features a programmable low-power
mode in which individual signal paths can be pro-
grammed as low power. These low-power speed paths
will be slightly slower than the non-low-power paths.
This feature allows speed critical paths to run at maxi-
mum frequency while the rest of the paths operate in
the low-power mode, resulting in power savings of up
to 75%. If all signals in a PAL block are low-power, then
total power is reduced further.
Program verification of a MACH device involves read-
ing back the programmed pattern and comparing it with
the original JEDEC file. The AMD method of program
verification performed on the MACH devices permits
the verification of one device at a time.
Accidental Programming or Erasure
Protection
In-System Programming
It is virtually impossible to program or erase a MACH
device inadvertently. The following conditions must be
met before programming actually takes place:
Programming is the process where MACH devices are
loaded with a pattern defined in a JEDEC file obtained
from MACHXL software or third-party software. Pro-
gramming is accomplished through four JTAG pins:
Test Mode Select (TMS), Test Clock (TCK), Test Data
In (TDI), and Test Data Out (TDO). The MACH211SP
can be employed in any JTAG (IEEE 1149.1) compli-
ant chain. While the MACH211SP is fully JTAG com-
patible, it supports the BYPASS instruction, not the
EXTEST and SAMPLE/PRELOAD instructions. The
MACH211SP can be programmed across the commer-
cial temperature range. Programming the MACH de-
vice after it has been placed on a circuit board is easily
accomplished. Programming is initiated by placing the
device into programming mode, using the MACHPRO
programming software provided by AMD. The device is
bulk erased and the JEDEC file is then loaded. After
the data is transferred into the device, the PROGRAM
instruction is loaded. Further programming details can
be found in application note, “Advanced In-circuit
Programming Guidelines.”
■ The device must be in the password-protected
program mode
■ The programming or bulk erase instruction must be
in the instruction register
If the above conditions are not met, the programming
circuitry cannot be activated.
To ensure that the AMD ten year device data retention
guarantee applies, 100 program/erase cycle limit
should not be exceeded.
Bus-Friendly Inputs and I/Os
The MACH211SP inputs and I/Os include two inverters
in series which loop back to the input. This double
inversion reinforces the state of the input and pulls the
voltage away from the input threshold voltage. For an
illustration of this configuration, please turn to the
Input/Output Equivalent Schematics section.
On-Board Programming Options
PCI Compliance
Since the MACHPRO software performs these steps
automatically, the following programming options are
published for reference.
The MACH211SP-7/10 is fully compliant with the PCI
Local Bus Specification published by the PCI Special
Interest Group. The MACH211SP-7/10’s predictable
timing ensures compliance with the PCI AC specifica-
tions independent of the design. On the other hand, in
CPLD and FPGA architectures without predictable tim-
ing, PCI compliance is dependent upon routing and
product term distribution.
The configuration file, which is also known as the chain
file, defines the MACH device JTAG chain.The file con-
tains the information concerning which JEDEC file is to
be placed into which device, the state which the out-
puts should be placed, and whether the security fuses
8
MACH211SP-7/10/12/15/20
0
4
8
12
16
20
24
28
32
36
40
47
43
51
Output Enable
Output Enable
Asynchronous Reset
Asynchronous Preset
I/O
Cell
I/O
Output
Macro
Cell
M0
Buried
Macro
Cell
M1
M2
I/O
Cell
I/O
Output
Macro
Cell
Buried
Macro
Cell
M3
M4
0
I/O
Cell
I/O
Output
Macro
Cell
C0
C1
Buried
Macro
Cell
C2
M5
M6
M7
M8
M9
C3
I/O
Cell
I/O
C4
Output
Macro
Cell
C5
C6
Buried
Macro
Cell
Switch
Matrix
C7
I/O
Cell
C8
I/O
Output
Macro
Cell
C9
C10
C11
C12
C13
C14
C15
Buried
Macro
Cell
I/O
I/O
I/O
I/O
Cell
Output
Macro
Cell
M10
Buried
Macro
Cell
M11
M12
M13
63
I/O
Cell
Output
Macro
Cell
Buried
Macro
Cell
I/O
Cell
Output
Macro
Cell
M14
M15
Buried
Macro
Cell
2
0
4
8
16
12
8
16
20
24
28
32
36
40
43
47
51
20405B-4
Figure 1. MACH211SP PAL Block
MACH211SP-7/10/12/15/20
9
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . . –65°C to +150°C
Commercial (C) Devices
Ambient Temperature
Ambient Temperature (T )
A
with Power Applied. . . . . . . . . . . . . . –55°C to +125°C
Operating in Free Air. . . . . . . . . . . . . . . .0°C to +70°C
Supply Voltage with
Supply Voltage (V
)
CC
Respect to Ground. . . . . . . . . . . . . . . –0.5 V to +7.0 V
with Respect to Ground . . . . . . . . +4.75 V to +5.25 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
DC Input Voltage . . . . . . . . . . . .–0.5 V to V + 0.5 V
CC
DC Output or
I/O Pin Voltage . . . . . . . . . . . . . .–0.5 V to V + 0.5 V
CC
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Latchup Current (T = 0°C to 70°C). . . . . . . . 200 mA
A
Stresses above those listed under Absolute Maximum
Ratings may cause permanent device failure. Functionality at
or above these limits is not implied. Exposure to Absolute
Maximum Ratings for extended periods may affect device
reliability. Programming conditions may differ.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter
Symbol
Parameter Description
Output HIGH Voltage
Test Conditions
= –3.2 mA, V = Min, V = V or V
IL
Min
Typ
Max
Unit
V
V
I
2.4
OH
OH
CC
IN
IH
V
Output LOW Voltage
I
= 16 mA, V = Min, V = V or V
IL
0.5
V
OL
OL
CC
IN
IH
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
V
Input HIGH Voltage
Input LOW Voltage
2.0
V
V
IH
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
V
0.8
IL
I
Input HIGH Current
Input LOW Current
V
= 5.25 V, V = Max (Note 2)
10
µA
µA
IH
IN
CC
I
V
= 0 V, V = Max (Note 2)
–10
IL
IN
CC
Off-State Output Leakage
Current HIGH
V
= 5.25 V, V = Max
= V or V (Note 2)
IH IL
OUT CC
I
10
µA
µA
OZH
V
IN
Off-State Output Leakage
Current LOW
V
= 0 V, V = Max
= V or V (Note 2)
IH IL
OUT CC
I
–10
OZL
V
IN
I
Output Short-Circuit Current
Supply Current (Static)
Supply Current (Active)
V
= 0.5 V, V = Max (Notes 3, 5)
–30
–160
mA
mA
mA
SC
OUT
CC
V
= 5 V, T = 25°C, f = 0 MHz (Note 4)
40
45
CC
A
I
CC
V
= 5 V, T = 25°C, f = 1 MHz (Note 4)
A
CC
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included.
2. I/O pin leakage is the worst case of I and I (or I and I ).
IL
OZL
IH
OZH
3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second.
= 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
V
OUT
4. This parameter is measured in low-power mode with a 16-bit up/down counter pattern. This pattern is programmed in each
PAL block and is capable of being loaded, enabled and reset.
5. This parameter is not 100% tested, but is evaluated at initial characterization and at any time the design is modified where
capacitance may be affected.
10
MACH211SP-7/10 (Com’l)
CAPACITANCE (Note 1)
Parameter
Symbol
Parameter Description
Test Conditions
= 5.0 V, T = 25°C
Typ
6
Unit
pF
C
Input Capacitance
Output Capacitance
V = 2.0 V
IN
V
IN
CC
A
f = 1 MHz
C
V
= 2.0 V
8
pF
OUT
OUT
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
-7
-10
Parameter
Symbol
Parameter Description
Min
Max
Min
Max
Unit
ns
t
Input, I/O, or Feedback to Combinatorial Output (Note 3)
7.5
10
PD
D-type
T-type
5.5
6.5
0
6.5
7.5
0
ns
Setup Time from Input, I/O, or Feedback to Clock
(Note 3)
t
S
H
ns
t
Register Data Hold Time
Clock to Output (Note 3)
ns
t
t
4.5
6
ns
CO
WL
WH
LOW
3
3
5
5
ns
Clock Width
t
HIGH
D-type
T-type
D-type
T-type
ns
100
91
80
74
100
91
100
6.5
0
MHz
MHz
MHz
MHz
MHz
ns
External Feedback
1/(t + t
)
S
CO
Maximum
Frequency
(Note 1)
f
133
125
166.7
5.5
0
MAX
Internal Feedback (f
No Feedback
)
CNT
1/(t + t
)
WL
WH
t
Setup Time from Input, I/O, or Feedback to Gate
Latch Data Hold Time
SL
t
ns
HL
t
Gate to Output
7
7
ns
GO
t
Gate Width LOW
3
5
ns
GWL
Input, I/O, or Feedback to Output Through Transparent Input or
Output Latch
t
9.5
12
ns
PDL
t
Input Register Setup Time
2
2
2
2
ns
ns
SIR
HIR
ICO
t
Input Register Hold Time
t
Input Register Clock to Combinatorial Output
11
13
ns
D-type
Input Register Clock to Output Register Setup
T-type
9
10
11
5
ns
t
ICS
10
ns
t
LOW
3
ns
WICL
Input Register Clock Width
HIGH
t
3
166.7
2
5
ns
WICH
f
Maximum Input Register Frequency
Input Latch Setup Time
100
2
MHz
ns
MAXIR
t
SIL
HIL
t
Input Latch Hold Time
2
2
ns
t
Input Latch Gate to Combinatorial Output
Input Latch Gate to Output Through Transparent Output Latch
12
14
14
16
ns
IGO
t
ns
IGOL
Setup Time from Input, I/O, or Feedback Through Transparent Input
Latch to Output Latch Gate
t
7.5
8.5
ns
SLL
MACH211SP-7/10 (Com’l)
11
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
(continued)
-7
-10
Parameter
Symbol
Parameter Description
Input Latch Gate to Output Latch Setup
Input Latch Gate Width LOW
Min
10
3
Max
Min
11
5
Max
Unit
ns
t
IGS
t
ns
WIGL
Input, I/O, or Feedback to Output Through Transparent Input and
Output Latches
t
12.5
9.5
14
15
ns
PDLL
t
Asynchronous Reset to Registered or Latched Output
Asynchronous Reset Width (Note 1)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AR
t
5
5
10
10
ARW
t
Asynchronous Reset Recovery Time (Note 1)
Asynchronous Preset to Registered or Latched Output
Asynchronous Preset Width (Note 1)
ARR
t
9.5
15
AP
t
5
5
10
10
APW
t
Asynchronous Preset Recovery Time (Note 1)
Input, I/O, or Feedback to Output Enable (Note 1)
Input, I/O, or Feedback to Output Disable (Note 1)
APR
t
9.5
9.5
10
10
0
12
12
10
10
0
EA
ER
t
t
t
Increase for Powered-down Macrocell (Note 3)
LP
PD
t
t Increase for Powered-down Macrocell (Note 3)
S
LPS
t
t
t
Increase for Powered-down Macrocell (Note 3)
Increase for Powered-down Macrocell (Note 3)
LPCO
CO
EA
t
10
10
LPEA
Notes:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where frequency may be affected.
2. See Switching Test Circuit for test conditions.
3. If a signal is powered-down, this parameter must be added to its respective high-speed parameter.
12
MACH211SP-7/10 (Com’l)
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . . –65°C to +150°C
Commercial (C) Devices
Ambient Temperature
Ambient Temperature (T )
A
with Power Applied. . . . . . . . . . . . . . –55°C to +125°C
Operating in Free Air. . . . . . . . . . . . . . . .0°C to +70°C
Supply Voltage with
Supply Voltage (V
)
CC
Respect to Ground. . . . . . . . . . . . . . . –0.5 V to +7.0 V
with Respect to Ground . . . . . . . . +4.75 V to +5.25 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
DC Input Voltage . . . . . . . . . . . .–0.5 V to V + 0.5 V
CC
DC Output or
I/O Pin Voltage . . . . . . . . . . . . . .–0.5 V to V + 0.5 V
CC
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Latchup Current (T = 0°C to 70°C). . . . . . . . 200 mA
A
Stresses above those listed under Absolute Maximum
Ratings may cause permanent device failure. Functionality at
or above these limits is not implied. Exposure to Absolute
Maximum Ratings for extended periods may affect device
reliability. Programming conditions may differ.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter
Symbol
Parameter Description
Output HIGH Voltage
Test Conditions
= –3.2 mA, V = Min, V = V or V
IL
Min
Typ
Max
Unit
V
V
I
2.4
OH
OH
CC
IN
IH
V
Output LOW Voltage
I
= 16 mA, V = Min, V = V or V
IL
0.5
V
OL
OL
CC
IN
IH
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
V
Input HIGH Voltage
Input LOW Voltage
2.0
V
V
IH
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
V
0.8
IL
I
Input HIGH Current
Input LOW Current
V
= 5.25 V, V = Max (Note 2)
10
µA
µA
IH
IN
CC
I
V
= 0 V, V = Max (Note 2)
–10
IL
IN
CC
Off-State Output Leakage
Current HIGH
V
= 5.25 V, V = Max
= V or V (Note 2)
IH IL
OUT CC
I
10
µA
µA
OZH
V
IN
Off-State Output Leakage
Current LOW
V
= 0 V, V = Max
= V or V (Note 2)
IH IL
OUT CC
I
–10
OZL
V
IN
I
Output Short-Circuit Current
Supply Current (Static)
Supply Current (Active)
V
= 0.5 V, V = Max (Notes 3, 5)
–30
–160
mA
mA
mA
SC
OUT
CC
V
= 5 V, T = 25°C, f = 0 MHz (Note 4)
40
45
CC
A
I
CC
V
= 5 V, T = 25°C, f = 1 MHz (Note 4)
A
CC
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included.
2. I/O pin leakage is the worst case of I and I (or I and I ).
IL
OZL
IH
OZH
3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second.
= 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
V
OUT
4. This parameter is measured in low-power mode with a 16-bit up/down counter pattern. This pattern is programmed in each
PAL block and is capable of being loaded, enabled and reset.
5. This parameter is not 100% tested, but is evaluated at initial characterization and at any time the design is modified where
capacitance may be affected.
MACH211SP-12/15/20 (Com’l)
13
CAPACITANCE (Note 1)
Parameter
Symbol
Parameter Description
Test Conditions
= 5.0 V, T = 25°C
Typ
6
Unit
pF
C
Input Capacitance
Output Capacitance
V = 2.0 V
IN
V
IN
CC
A
f = 1 MHz
C
V
= 2.0 V
8
pF
OUT
OUT
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
-12
-15
-20
Parameter
Symbol
Parameter Description
Min
Max
Min
Max
Min
Max
Unit
Input, I/O, or Feedback to Combinatorial Output
(Note 3)
t
12
15
20
ns
PD
D-type
7
8
0
10
11
0
13
14
0
ns
ns
Setup Time from Input, I/O, or
Feedback to Clock
t
S
T-type
t
Register Data Hold Time
Clock to Output (Note 3)
ns
H
t
t
8
10
12
ns
CO
WL
WH
LOW
6
6
8
8
ns
Clock Width
t
HIGH
6
6
ns
D-type
66.7
62.5
83.3
76.9
50
40
MHz
MHz
MHz
MHz
External
Feedback
1/(t + t
)
S
CO
T-type
D-type
T-type
47.6
66.6
62.5
38.5
50
Maximum
Frequency
(Note 1)
f
MAX
Internal Feedback (f
No
)
CNT
47.6
1/(t + t
)
83.3
83.3
62.5
MHz
WL
WH
Feedback
t
Setup Time from Input, I/O, or Feedback to Gate
Latch Data Hold Time
7
0
10
0
13
0
ns
ns
ns
ns
SL
t
HL
t
Gate to Output
10
14
11
17
12
22
GO
t
Gate Width LOW
6
6
8
GWL
Input, I/O, or Feedback to Output Through
Transparent Input or Output Latch
t
ns
PDL
t
Input Register Setup Time
2
2
2
2
3
ns
ns
ns
ns
ns
ns
ns
SIR
HIR
ICO
t
Input Register Hold Time
2.5
t
Input Register Clock to Combinatorial Output
15
18
23
D-type
12
13
6
15
16
6
20
21
8
Input Register Clock to Output Register
Setup
t
ICS
T-type
t
LOW
Input Register Clock Width
HIGH
WICL
t
6
6
8
WICH
Maximum Input Register
Frequency
f
1/(t
+ t )
WICH
83.3
83.3
62.5
MHz
MAXIR
WICL
t
Input Latch Setup Time
Input Latch Hold Time
2
2
2
2
3
ns
ns
SIL
t
2.5
HIL
14
MACH211SP-12/15/20 (Com’l)
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
(continued)
-12
-15
-20
Parameter
Symbol
Parameter Description
Min
Max
Min
Max
Min
Max
Unit
t
Input Latch Gate to Combinatorial Output
17
20
25
ns
IGO
Input Latch Gate to Output Through Transparent
Output Latch
t
19
22
27
ns
ns
IGOL
SetupTime from Input, I/O, or FeedbackThrough
Transparent Input Latch to Output Latch Gate
t
9
12
15
SLL
t
Input Latch Gate to Output Latch Setup
Input Latch Gate Width LOW
13
6
16
6
21
8
ns
ns
IGS
t
WIGL
Input, I/O, or Feedback to Output Through
Transparent Input and Output Latches
t
16
16
19
20
24
25
ns
ns
PDLL
Asynchronous Reset to Registered or Latched
Output
t
AR
t
Asynchronous Reset Width (Note 1)
12
8
15
10
20
15
ns
ns
ARW
t
Asynchronous Reset Recovery Time (Note 1)
ARR
Asynchronous Preset to Registered or Latched
Output
t
16
20
25
ns
AP
t
Asynchronous Preset Width (Note 1)
12
8
15
10
20
15
ns
ns
ns
APW
t
Asynchronous Preset Recovery Time (Note 1)
Input, I/O, or Feedback to Output Enable (Note 1)
APR
t
15
15
15
15
15
15
EA
Input, I/O, or Feedback to Output Disable
(Note 1)
t
ns
ER
t
Increase for Powered-down Macrocell
PD
t
10
10
0
10
10
0
10
10
0
ns
ns
ns
LP
(Note 3)
t
t Increase for Powered-down Macrocell (Note 3)
LPS
S
t
Increase for Powered-down Macrocell
CO
t
LPCO
(Note 3)
t
Increase for Powered-down Macrocell
EA
t
10
10
10
ns
LPEA
(Note 3)
Notes:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where frequency may be affected.
2. See Switching Test Circuit for test conditions.
3. If a signal is powered-down, this parameter must be added to its respective high-speed parameter.
MACH211SP-12/15/20 (Com’l)
15
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . . –65°C to +150°C
Industrial (I) Devices
Ambient Temperature
Temperature (T )
A
with Power Applied. . . . . . . . . . . . . . –55°C to +125°C
Operating in Free Air. . . . . . . . . . . . . .–40°C to +85°C
Supply Voltage with
Supply Voltage (V
)
CC
Respect to Ground. . . . . . . . . . . . . . . –0.5 V to +7.0 V
with Respect to Ground . . . . . . . . . . +4.5 V to +5.5 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
DC Input Voltage . . . . . . . . . . . .–0.5 V to V + 0.5 V
CC
DC Output or
I/O Pin Voltage . . . . . . . . . . . . . .–0.5 V to V + 0.5 V
CC
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Latchup Current (T = –40°C to +85°C). . . . . 200 mA
A
Stresses above those listed under Absolute Maximum
Ratings may cause permanent device failure. Functionality at
or above these limits is not implied. Exposure to Absolute
Maximum Ratings for extended periods may affect device
reliability. Programming conditions may differ.
DC CHARACTERISTICS over INDUSTRIAL operating ranges unless otherwise specified
Parameter
Symbol
Parameter Description
Output HIGH Voltage
Test Conditions
= –3.2 mA, V = Min, V = V or V
IL
Min
Typ
Max
Unit
V
V
I
2.4
OH
OH
CC
IN
IH
V
Output LOW Voltage
I
= 16 mA, V = Min, V = V or V
IL
0.5
V
OL
OL
CC
IN
IH
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
V
Input HIGH Voltage
Input LOW Voltage
2.0
V
V
IH
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
V
0.8
IL
I
Input HIGH Leakage Current
Input LOW Leakage Current
V
= 5.25 V, V = Max (Note 2)
10
µA
µA
IH
IN
CC
I
V
= 0 V, V = Max (Note 2)
–10
IL
IN
CC
Off-State Output Leakage
Current HIGH
V
= 5.25 V, V = Max
= V or V (Note 2)
IH IL
OUT CC
I
10
µA
µA
OZH
V
IN
Off-State Output Leakage
Current LOW
V
= 0 V, V = Max
= V or V (Note 2)
IH IL
OUT CC
I
–10
OZL
V
IN
I
Output Short-Circuit Current
Supply Current (Static)
Supply Current (Active)
V
= 0.5 V, V = Max (Notes 3, 5)
–30
–160
mA
mA
mA
SC
OUT
CC
V
= 5 V, T = 25°C, f = 0 MHz (Note 4)
40
45
CC
A
I
CC
V
= 5 V, T = 25°C, f = 1 MHz (Note 4)
A
CC
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included.
2. I/O pin leakage is the worst case of I and I (or I and I ).
IL
OZL
IH
OZH
3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second.
= 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
V
OUT
4. This parameter is measured in low-power mode with a 16-bit up/down counter pattern. This pattern is programmed in each
PAL block and is capable of being loaded, enabled and reset.
5. This parameter is not 100% tested, but is evaluated at initial characterization and at any time the design is modified where
capacitance may be affected.
16
MACH211SP-10/12 (Ind)
CAPACITANCE (Note 1)
Parameter
Symbol
Parameter Description
Test Conditions
= 5.0 V, T = 25°C
Typ
6
Unit
pF
C
Input Capacitance
Output Capacitance
V = 2.0 V
IN
V
IN
CC
A
f = 1 MHz
C
V
= 2.0 V
8
pF
OUT
OUT
SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2)
-10
-12
Parameter
Symbol
Parameter Description
Min
Max
Min
Max
Unit
ns
t
Input, I/O, or Feedback to Combinatorial Output (Note 3)
10
12
PD
D-type
T-type
6.5
7.5
0
8
9
0
ns
t
Setup Time from Input, I/O, or Feedback to Clock
S
H
ns
t
Register Data Hold Time
Clock to Output (Note 3)
ns
t
t
6
7.5
ns
CO
WL
WH
LOW
5
5
6
6
ns
Clock Width
t
HIGH
D-type
T-type
D-type
T-type
ns
80
74
100
91
100
6.5
0
64
59
80
72.5
80
8
MHz
MHz
MHz
MHz
MHz
ns
External Feedback
1/(t + t
)
S
CO
Maximum
Frequency
(Note 1)
f
MAX
Internal Feedback (f
No Feedback
)
CNT
1/(t + t
)
WL
WH
t
Setup Time from Input, I/O, or Feedback to Gate
Latch Data Hold Time
SL
t
0
ns
HL
t
Gate to Output
8
8.5
ns
GO
t
Gate Width LOW
5
6
ns
GWL
Input, I/O, or Feedback to Output Through Transparent Input or
Output Latch
t
12
14.5
ns
PDL
t
Input Register Setup Time
2
2
2.5
3
ns
ns
SIR
HIR
ICO
t
Input Register Hold Time
t
Input Register Clock to Combinatorial Output
13
16
ns
D-type
Input Register Clock to Output Register Setup
T-type
10
11
5
12
13
6
ns
t
ICS
ns
t
LOW
ns
WICL
Input Register Clock Width
HIGH
t
5
6
ns
WICH
f
Maximum Input Register Frequency
Input Latch Setup Time
1/(t
+ t )
WICH
100
2
80
2.5
3
MHz
ns
MAXIR
WICL
t
SIL
t
Input Latch Hold Time
2
ns
HIL
t
Input Latch Gate to Combinatorial Output
14
16
17
ns
IGO
t
Input Latch Gate to Output Through Transparent Output Latch
19.5
ns
IGOL
MACH211SP-10/12 (Ind)
17
SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2) (continued)
-10
-12
Parameter
Symbol
Parameter Description
Min
Max
Min
Max
Unit
Setup Time from Input, I/O, or Feedback Through Transparent Input
Latch to Output Latch Gate
t
8.5
10.5
ns
SLL
t
Input Latch Gate to Output Latch Setup
Input Latch Gate Width LOW
11
5
13.5
6
ns
ns
IGS
t
WIGL
Input, I/O, or Feedback to Output Through Transparent Input and
Output Latches
t
14
15
17
ns
PDLL
t
Asynchronous Reset to Registered or Latched Output
Asynchronous Reset Width (Note 1)
19.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AR
t
10
10
12
10
ARW
t
Asynchronous Reset Recovery Time (Note 1)
Asynchronous Preset to Registered or Latched Output
Asynchronous Preset Width (Note 1)
ARR
t
15
18
AP
t
10
10
12
10
APW
t
Asynchronous Preset Recovery Time (Note 1)
Input, I/O, or Feedback to Output Enable (Note 1)
Input, I/O, or Feedback to Output Disable (Note 1)
APR
t
15
15
10
10
0
15
15
10
10
0
EA
ER
t
t
t
Increase for Powered-down Macrocell (Note 3)
LP
PD
t
t Increase for Powered-down Macrocell (Note 3)
S
LPS
t
t
t
Increase for Powered-down Macrocell (Note 3)
Increase for Powered-down Macrocell (Note 3)
LPCO
CO
EA
t
10
10
LPEA
Notes:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
2. See Switching Test Circuit for test conditions.
3. If a signal is powered-down, this parameter must be added to its respective high-speed parameter.
18
MACH211SP-10/12 (Ind)
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . . –65°C to +150°C
Industrial (I) Devices
Ambient Temperature
Ambient Temperature (T )
A
with Power Applied. . . . . . . . . . . . . . –55°C to +125°C
Operating in Free Air. . . . . . . . . . . . . .–40°C to +85°C
Supply Voltage with
Supply Voltage (V
)
CC
Respect to Ground. . . . . . . . . . . . . . . –0.5 V to +7.0 V
with Respect to Ground . . . . . . . . . . +4.5 V to +5.5 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
DC Input Voltage . . . . . . . . . . . .–0.5 V to V + 0.5 V
CC
DC Output or
I/O Pin Voltage . . . . . . . . . . . . . .–0.5 V to V + 0.5 V
CC
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Latchup Current (T = –40°C to 85°C). . . . . . 200 mA
A
Stresses above those listed under Absolute Maximum
Ratings may cause permanent device failure. Functionality at
or above these limits is not implied. Exposure to Absolute
Maximum Ratings for extended periods may affect device
reliability. Programming conditions may differ.
DC CHARACTERISTICS over INDUSTRIAL operating ranges unless otherwise specified
Parameter
Symbol
Parameter Description
Output HIGH Voltage
Test Conditions
= –3.2 mA, V = Min, V = V or V
IL
Min
Typ
Max
Unit
V
V
I
2.4
OH
OH
CC
IN
IH
V
Output LOW Voltage
I
= 16 mA, V = Min, V = V or V
IL
0.5
V
OL
OL
CC
IN
IH
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
V
Input HIGH Voltage
Input LOW Voltage
2.0
V
V
IH
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
V
0.8
IL
I
Input HIGH Leakage Current
Input LOW Leakage Current
V
= 5.25 V, V = Max (Note 2)
10
µA
µA
IH
IN
CC
I
V
= 0 V, V = Max (Note 2)
–10
IL
IN
CC
Off-State Output Leakage
Current HIGH
V
= 5.25 V, V = Max
= V or V (Note 2)
IH IL
OUT CC
I
10
µA
µA
OZH
V
IN
Off-State Output Leakage
Current LOW
V
= 0 V, V = Max
= V or V (Note 2)
IH IL
OUT CC
I
–10
OZL
V
IN
I
Output Short-Circuit Current
Supply Current (Static)
Supply Current (Active)
V
= 0.5 V, V = Max (Notes 3, 5)
–30
–160
mA
mA
mA
SC
OUT
CC
V
= 5 V, T = 25°C, f = 0 MHz (Note 4)
40
45
CC
A
I
CC
V
= 5 V, T = 25°C, f = 1 MHz (Note 4)
A
CC
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included.
2. I/O pin leakage is the worst case of I and I (or I and I ).
IL
OZL
IH
OZH
3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second.
= 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
V
OUT
4. This parameter is measured in low-power mode with a 16-bit up/down counter pattern. This pattern is programmed in each
PAL block and is capable of being loaded, enabled and reset.
5. This parameter is not 100% tested, but is evaluated at initial characterization and at any time the design is modified where
capacitance may be affected.
MACH211SP-14/18/24 (Ind)
19
CAPACITANCE (Note 1)
Parameter
Symbol
Parameter Description
Test Conditions
= 5.0 V, T = 25°C
Typ
6
Unit
pF
C
Input Capacitance
Output Capacitance
V = 2.0 V
IN
V
IN
CC
A
f = 1 MHz
C
V
= 2.0 V
8
pF
OUT
OUT
SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2)
-14
-18
-24
Parameter
Symbol
Parameter Description
Min
Max
Min
Max
Min
Max
Unit
Input, I/O, or Feedback to Combinatorial Output
(Note 3)
t
14.5
18
24
ns
PD
D-type
8.5
10
0
12
13.5
0
16
17
0
ns
ns
Setup Time from Input, I/O, or
Feedback to Clock
t
S
T-type
t
Register Data Hold Time
Clock to Output (Note 3)
ns
H
t
t
10
12
14.5
ns
CO
WL
WH
LOW
7.5
7.5
53
7.5
7.5
40
38
53
44
10
10
ns
Clock Width
t
HIGH
ns
D-type
32
MHz
MHz
MHz
MHz
External
Feedback
1/(t + t
)
S
CO
T-type
D-type
T-type
50
30.5
38
Maximum
Frequency
(Note 1)
61.5
57
f
MAX
Internal Feedback (f
No
)
CNT
34.5
1/(t + t
)
66.5
66.5
50
MHz
WL
WH
Feedback
t
Setup Time from Input, I/O, or Feedback to Gate
Latch Data Hold Time
8.5
0
12
0
16
0
ns
ns
ns
ns
SL
t
HL
t
Gate to Output
12
17
13.5
20.5
14.5
26.5
GO
t
Gate Width LOW
7.5
7.5
10
GWL
Input, I/O, or Feedback to Output Through
Transparent Input or Output Latch
t
ns
PDL
t
Input Register Setup Time
2.5
3
2.5
3.5
2.5
4
ns
ns
ns
ns
ns
ns
ns
SIR
HIR
ICO
t
Input Register Hold Time
t
Input Register Clock to Combinatorial Output
18
22
28
D-type
14.5
16
18
19.5
7.5
24
25.5
10
Input Register Clock to Output Register
Setup
t
ICS
T-type
t
LOW
Input Register Clock Width
HIGH
7.5
7.5
WICL
t
7.5
10
WICH
Maximum Input Register
Frequency
f
1/(t
+ t )
WICH
66.5
66.5
50
MHz
MAXIR
WICL
t
Input Latch Setup Time
Input Latch Hold Time
2.5
3
2.5
3.5
2.5
4
ns
ns
ns
SIL
t
HIL
t
Input Latch Gate to Combinatorial Output
20.5
24
30
IGO
20
MACH211SP-14/18/24 (Ind)
SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2) (continued)
-14
-18
-24
Parameter
Symbol
Parameter Description
Min
Max
Min
Max
Min
Max
Unit
Input Latch Gate to Output Through Transparent
Output Latch
t
23
26.5
32.5
ns
IGOL
SetupTime from Input, I/O, or FeedbackThrough
Transparent Input Latch to Output Latch Gate
t
11
14.5
18
ns
SLL
t
Input Latch Gate to Output Latch Setup
Input Latch Gate Width LOW
16
19.5
7.5
25.5
10
ns
ns
IGS
t
7.5
WIGL
Input, I/O, or Feedback to Output Through
Transparent Input and Output Latches
t
19.5
19.5
23
24
29
30
ns
ns
PDLL
Asynchronous Reset to Registered or Latched
Output
t
AR
t
Asynchronous Reset Width (Note 1)
14.5
10
18
12
24
18
ns
ns
ARW
t
Asynchronous Reset Recovery Time (Note 1)
ARR
Asynchronous Preset to Registered or Latched
Output
t
19.5
24
30
ns
AP
t
Asynchronous Preset Width (Note 1)
14.5
10
18
12
24
18
ns
ns
ns
APW
t
Asynchronous Preset Recovery Time (Note 1)
Input, I/O, or Feedback to Output Enable (Note 1)
APR
t
14.5
14.5
18
18
24
24
EA
Input, I/O, or Feedback to Output Disable
(Note 1)
t
ns
ER
t
Increase for Powered-down Macrocell
PD
t
10
10
0
10
10
0
10
10
0
ns
ns
ns
LP
(Note 3)
t
t Increase for Powered-down Macrocell (Note 3)
LPS
S
t
Increase for Powered-down Macrocell
CO
t
LPCO
(Note 3)
t
Increase for Powered-down Macrocell
EA
t
10
10
10
ns
LPEA
(Note 3)
Notes:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
2. See Switching Test Circuit for test conditions.
3. If a signal is powered-down, this parameter must be added to its respective high-speed parameter.
MACH211SP-14/18/24 (Ind)
21
TYPICAL I CHARACTERISTICS
CC
V
= 5 V,T = 25°C
CC
A
200
High Speed
150
I
(mA)
CC
100
Low Power
50
0
0
10
20
30
40
50
60
70
80
90
Frequency (MHz)
20405B-5
The selected “typical” pattern is a 16-bit up/down counter.This pattern is programmed in each PAL block and is capable of being
loaded, enabled, and reset.
Maximum frequency shown uses internal feedback and a D-type register.
22
MACH211SP-7/10/12/15/20
TYPICAL THERMAL CHARACTERISTICS
Measured at 25°C ambient. These parameters are not tested.
Typ
Parameter
Symbol
Parameter Description
Thermal impedance, junction to case
TQFP
11.3
41
PLCC
4
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
θ
θ
jc
ja
Thermal impedance, junction to ambient
30.4
18.5
15.9
13.5
12.8
200 lfpm air
400 lfpm air
600 lfpm air
800 lfpm air
35
33.7
32.6
32
Thermal impedance, junction to ambient
with air flow
θ
jma
Plastic θ Considerations
jc
The data listed for plastic θ are for reference only and are not recommended for use in calculating junction temperatures. The
jc
heat-flow paths in plastic-encapsulated devices are complex, making the θ measurement relative to a specific location on the
jc
package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of
the package. Furthermore, θ tests on packages are performed in a constant-temperature bath, keeping the package surface at
jc
a constant temperature. Therefore, the measurements can only be used in a similar environment. TQFP thermal measurements
are taken with components on a six-layer printed circuit board.
MACH211SP-7/10/12/15/20
23
SWITCHING WAVEFORMS
Input, I/O, or
V
T
Feedback
t
PD
Combinatorial
Output
V
T
20405B-6
Combinatorial Output
Input, I/O, or
Feedback
Input, I/O, or
V
V
T
T
Feedback
t
t
S
H
t
t
HL
SL
V
Gate
V
T
T
Clock
t
CO
t
PDL
t
GO
Registered
Output
Latched
Out
V
V
T
T
20405B-7
20405B-8
Registered Output
Latched Output
t
WH
Gate
V
T
Clock
t
GWL
t
WL
20405B-9
20405B-10
Clock Width
Gate Width
Registered
Input
Registered
Input
V
V
T
T
t
t
HIR
SIR
Input
Register
Clock
Input
Register
Clock
V
V
T
T
t
ICO
Output
Register
Clock
t
Combinatorial
Output
V
ICS
T
V
T
20405B-11
20405B-12
Registered Input
Input Register to Output Register Setup
Notes:
1. V = 1.5 V.
T
2. Input pulse amplitude 0 V to 3.0 V.
3. Input rise and fall times 2 ns–4 ns typical.
24
MACH211SP-7/10/12/15/20
SWITCHING WAVEFORMS
Latched
In
V
T
t
t
HIL
SIL
V
T
Gate
t
IGO
Combinatorial
Output
V
T
20405B-13
Latched Input
t
PDLL
Latched
In
V
T
Latched
Out
V
T
t
IGOL
Input
Latch Gate
t
SLL
t
IGS
V
T
Output
Latch Gate
20405B-14
Latched Input and Output
Notes:
1. V = 1.5 V.
T
2. Input pulse amplitude 0 V to 3.0 V.
3. Input rise and fall times 2 ns–4 ns typical.
MACH211SP-7/10/12/15/20
25
SWITCHING WAVEFORMS
t
WICH
Input
Latch
Gate
V
Clock
V
T
T
t
WICL
t
WIGL
20405B-15
20405B-16
Input Register Clock Width
Input Latch Gate Width
t
t
ARW
APW
Input, I/O, or
Feedback
Input, I/O,
or Feedback
V
V
T
T
t
t
AP
AR
Registered
Output or
Latched
Output
Registered
Output or
Latched
Output
V
V
T
T
t
t
ARR
APR
Clock or
Input Latch
Gate
Clock or
Input Latch
Gate
V
V
T
T
20405B-17
20405B-18
Asynchronous Reset
Asynchronous Preset
Input, I/O, or
Feedback
V
T
t
t
EA
ER
V
– 0.5 V
+ 0.5 V
OH
V
Outputs
T
V
OL
20405B-19
Output Disable/Enable
Notes:
1. V = 1.5 V.
T
2. Input pulse amplitude 0 V to 3.0 V.
3. Input rise and fall times 2 ns–4 ns typical.
26
MACH211SP-7/10/12/15/20
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Must be
Steady
Will be
Steady
May
Change
from H to L
Will be
Changing
from H to L
May
Change
from L to H
Will be
Changing
from L to H
Don’t Care,
Any Change
Permitted
Changing,
State
Unknown
Does Not
Apply
Center
Line is High-
Impedance
“Off” State
KS000010-PAL
SWITCHING TEST CIRCUIT
5 V
S
1
R
1
2
Output
Test Point
R
C
L
20405B-20
Commercial
Specification
, t
S
C
R
R
2
Measured Output Value
1
L
1
t
Closed
PD CO
35 pF
5 pF
1.5 V
Z → H: Open
Z → L: Closed
t
EA
300 Ω
390 Ω
H → Z: Open
L → Z: Closed
H → Z: V – 0.5 V
OH
t
ER
L → Z: V + 0.5 V
OL
* Switching several outputs simultaneously should be avoided for accurate measurement.
MACH211SP-7/10/12/15/20
27
F
PARAMETERS
MAX
The parameter f
the device is guaranteed to operate. Because the flexi-
bility inherent in programmable logic devices offers a
is the maximum clock rate at which
The third type of design is a simple data path applica-
tion. In this case, input data is presented to the flip-flop
and clocked through; no feedback is employed. Under
these conditions, the period is limited by the sum of the
MAX
choice of clocked flip-flop designs, f
is specified for
MAX
three types of synchronous designs.
data setup time and the data hold time (t + t ). How-
S
H
ever, a lower limit for the period of each f
type is the
MAX
The first type of design is a state machine with feed-
back signals sent off-chip.This external feedback could
go back to the device inputs, or to a second device in a
multi-chip state machine.The slowest path defining the
period is the sum of the clock-to-output time and the
minimum clock period (t
+ t ). Usually, this mini-
WH
WL
mum clock period determines the period for the third
, designated “f no feedback.”
f
MAX
MAX
For devices with input registers, one additional f
pa-
MAX
input setup time for the external signals (t + t ). The
rameter is specified: f
. Because this involves no
S
CO
MAXIR
reciprocal, f
, is the maximum frequency with exter-
feedback, it is calculated the same way as f
no
MAX
MAX
nal feedback or in conjunction with an equivalent speed
device. This f is designated “f external.”
feedback. The minimum period will be limited either by
the sum of the setup and hold times (t
+ t ) or the
MAX
MAX
SIR
HIR
sum of the clock widths (t
+ t
). The clock
WICL
WICH
The second type of design is a single-chip state ma-
chine with internal feedback only. In this case, flip-flop
inputs are defined by the device inputs and flip-flop out-
puts. Under these conditions, the period is limited by
the internal delay from the flip-flop outputs through the
internal feedback and logic to the flip-flop inputs. This
widths are normally the limiting parameters, so that
is specified as 1/(t + t ). Note that if both
f
MAXIR
WICL
WICH
input and output registers are use in the same path, the
overall frequency will be limited by t
.
ICS
All frequencies except f
internal are calculated from
MAX
f
is designated “f
internal”. A simple internal
other measured AC parameters. f
internal is mea-
MAX
MAX
MAX
counter is a good example of this type of design; there-
sured directly.
fore, this parameter is sometimes called “f
”
CNT.
CLK
CLK
(SECOND
CHIP)
REGISTER
LOGIC
REGISTER
LOGIC
t
t
t
S
S
CO
f
External; 1/(t + t
)
f
Internal (f
)
MAX
S
CO
MAX
CNT
CLK
CLK
REGISTER
LOGIC
REGISTER
LOGIC
t
S
t
t
HIR
SIR
f
No Feedback; 1/(t + t ) or 1/(t
+ t
)
f
; 1/(t
+ t ) or 1/(t
+ t
)
MAX
S
H
WH
WL
MAXIR
SIR
HIR
WICL
WICH
20405B-21
28
MACH211SP-7/10/12/15/20
ENDURANCE CHARACTERISTICS
The MACH families are manufactured using AMD’s ad-
vanced Electrically Erasable process. This technology
uses an EE cell to replace the fuse link used in bipolar
parts. As a result, the device can be erased and repro-
grammed, a feature which allows 100% testing at the
factory.
Endurance Characteristics
Parameter
Symbol
Parameter Description
Min Pattern Data Retention Time
Max Reprogramming Cycles
Min
10
Units
Years
Years
Cycles
Test Conditions
Max Storage Temperature
Max Operating Temperature
Normal Programming Conditions
t
DR
20
N
100
MACH211SP-7/10/12/15/20
29
INPUT/OUTPUT EQUIVALENT SCHEMATICS
V
CC
100 kΩ
V
CC
1 kΩ
ESD
Protection
Input
V
CC
V
CC
100 kΩ
1 kΩ
Preload
Circuitry
Feedback
Input
I/O
20405B-22
30
MACH211SP-7/10/12/15/20
POWER-UP RESET
The MACH devices have been designed with the capa-
bility to reset during system power-up. Following
power-up, all flip-flops will be reset to LOW. The output
state will depend on the logic polarity. This feature pro-
vides extra flexibility to the designer and is especially
valuable in simplifying state machine initialization. A
timing diagram and parameter table are shown below.
Due to the synchronous operation of the power-up
reset and the wide range of ways V
steady state, two conditions are required to insure a
valid power-up reset. These conditions are:
can rise to its
CC
1. The V rise must be monotonic.
CC
2. Following reset, the clock input must not be driven
from LOW to HIGH until all applicable input and
feedback setup times are met.
Parameter Symbol
Parameter Descriptions
Power-Up Reset Time
Input or Feedback Setup Time
Clock Width LOW
Max
Unit
t
10
µs
PR
t
S
See Switching Characteristics
t
WL
V
CC
4 V
Power
t
PR
Registered
Output
t
S
Clock
t
WL
20405B-23
Power-Up Reset Waveform
MACH211SP-7/10/12/15/20
31
DEVELOPMENT SYSTEMS (subject to change)
For more information on the products listed below, please consult the AMD FusionPLD Catalog.
MANUFACTURER
Advanced Micro Devices, Inc.
SOFTWARE DEVELOPMENT SYSTEMS
®
P.O. Box 3453, MS 1028
MACHXL Software
Sunnyvale, CA 94088-3543
(800) 222-9323 or (408) 732-2400
Ver. 3.0
Advanced Micro Devices, Inc.
P.O. Box 3453, MS 1028
Sunnyvale, CA 94088-3543
(800) 222-9323 or (408) 732-2400
Design Center/AMD Software
Advanced Micro Devices, Inc.
P.O. Box 3453, MS 1028
Sunnyvale, CA 94088-3543
(800) 222-9323 or (408) 732-2400
AMD-ABEL Software
Data I/O MACH Fitters
Advanced Micro Devices, Inc.
P.O. Box 3453, MS 1028
Sunnyvale, CA 94088-3543
(800) 222-9323 or (408) 732-2400
PROdeveloper/AMD
Software
PROsynthesis/AMD Software
Cadence Design Systems
555 River Oaks Pkwy
San Jose, CA 95134
(408) 943-1234
PLD™ Designer
Verilog, LeapFrog, RapidSim Simulators
Ver. 9504
Data I/O Corporation
10525 Willows Road N.E.
P.O. Box 97046
Redmond, WA 98073-9746
(800) 332-8246 or (206) 881-6444
ABEL™ Software
Synario™ Software
Mentor Graphics Corp.
PLDSynthesis™ II
QuickSim Simulator
8005 S.W. Boeckman Rd.
Wilsonville, OR 97070-7777
(800) 547-3000 or (503) 685-7000
MicroSim Corp.
20 Fairbanks
Irvine, CA 92718
(714) 770-3022
Design Center Software
PLDesigner™-XL Software
SUSIE™ Simulator
MINC Incorporated
6755 Earl Drive, Suite 200
Colorado Springs, CO 80918
(800) 755-FPGA or (719) 590-1155
SUSIE-CAD
10000 Nevada Highway, Suite 201
Boulder City, NV 89005
(702) 293-2271
Synopsys Logic Modeling
19500 NW Gibbs Dr.
P.O. Box 310
®
SmartModel Library
Beaverton, OR 97075
(503) 690-6900
Teradyne EDA
321 Harrison Ave.
Boston, MA 02118
MultiSIM Interactive Simulator
LASAR
(800) 777-2432 or (617) 422-2793
32
MACH211SP-7/10/12/15/20
DEVELOPMENT SYSTEMS (subject to change) (continued)
MANUFACTURER
SOFTWARE DEVELOPMENT SYSTEMS
Viewlogic Systems, Inc.
293 Boston Post Road West
Marlboro, MA 01752
ViewPLD or PROPLD
(Requires PROSim Simulator MACH Fitter)
ViewSim Simulator
(800) 442-4660 or (508) 480-0881
MANUFACTURER
TEST GENERATION SYSTEM
Acugen Software, Inc.
427-3 Amherst St., Suite 391
Nashua, NH 03063
ATGEN™ Test Generation Software
PLDCheck 90
(603) 891-1995
iNt GmbH
Busenstrasse 6
D-8033 Martinsried, Munich, Germany
(87) 857-6667
Advanced Micro Devices is not responsible for any information relating to the products of third parties. The inclusion of such information is not a
representation nor an endorsement by AMD of these products.
MACH211SP-7/10/12/15/20
33
APPROVED PROGRAMMERS (subject to change)
For more information on the products listed below, please consult the AMD FusionPLD Catalog.
MANUFACTURER
Advin Systems, Inc.
PROGRAMMER CONFIGURATION
1050-L East Duane Ave.
Sunnyvale, CA 94086
(408) 243-7000
Pilot U84
BP Microsystems
100 N. Post Oak Rd.
Houston, TX 77055-7237
(800) 225-2102 or (713) 688-4600
BP1148
BP1200
BP2100
Data I/O Corporation
10525 Willows Road N.E.
P.O. Box 97046
Redmond, WA 98073-9746
(800) 332-8246 or (206) 881-6444
UniSite™
Model 2900
Model 3900
FLEX-700
AutoSite
Hi/Lo
4F, No. 2, Sec. 5, Ming Shoh E. Rd.
Taipei, Taiwan
ALL-07
Logical Devices Inc./Digelec
692 S. Military Trail
Deerfield Beach, FL 33442
(800) 331-7766 or (305) 428-6868
ALLPRO™-88
SMS North America, Inc.
16522 NE 135th Place
Redmond, WA 98052
(800) 722-4122
or
Sprint
Expert
Multisite
SMS
lm Grund 15
D-7988 Vangen Im Allgau, Germany
07522-5018
Stag Microsystems Inc.
1600 Wyatt Dr. Suite 3
Santa Clara, CA 95054
(408) 988-1118
Stag Quazar
Stag Eclipse
or
Stag House
Martinfield, Welwyn Garden City
Herfordshire UK AL7 1JT
707-332148
System General
510 S. Park Victoria Dr.
Milpitas, CA 95035
(408) 263-6667
or
Turpro-1
FX
TX
3F, No. 1, Alley 8, Lane 45
Bao Shing Rd., Shin Diau
Taipei, Taiwan
2-917-3005
34
MACH211SP-7/10/12/15/20
APPROVED ON-BOARD PROGRAMMERS
MANUFACTURER
PROGRAMMER CONFIGURATION
Corelis, Inc.
12607 Hidden Creek Way, Suite H
Cerritos, California 70703
(310) 926-6727
JTAG PROG
Advanced Micro Devices
P.O. Box 3453, MS-1028
Sunnyvale, CA 94088-3453
(800) 222-9323
MACHpro
PROGRAMMER SOCKET ADAPTERS (subject to change)
MANUFACTURER
PART NUMBER
California Integration Technologies
656 Main Street
Placerville, CA 95667
(916) 626-6168
Contact Manufacturer
EDI Corporation
P.O. Box 366
Patterson, CA 95363
(209) 892-3270
Contact Manufacturer
Contact Manufacturer
Contact Manufacturer
Contact Manufacturer
Emulation Technology
2344 Walsh Ave., Bldg. F
Santa Clara, CA 95051
(408) 982-0660
Logical Systems Corp.
P.O. Box 6184
Syracuse, NY 13217-6184
(315) 478-0722
Procon Technologies, Inc.
1333 Lawrence Expwy, Suite 207
Santa Clara, CA 95051
(408) 246-4456
MACH211SP-7/10/12/15/20
35
PHYSICAL DIMENSIONS*
PL 044
44-Pin Plastic Leaded Chip Carrier (measured in inches)
.062
.083
.685
.695
.042
.056
.650
.656
Pin 1 I.D.
.685
.695
.500 .590
REF .630
.650
.656
.013
.021
.009
.015
.026
.032
.090
.120
.165
.180
.050 REF
SEATING PLANE
16-038-SQ
PL 044
DA78
6-28-94 ae
TOP VIEW
SIDE VIEW
* For reference only. BSC is an ANSI standard for Basic Space Centering.
36
MACH211SP-7/10/12/15/20
PHYSICAL DIMENSIONS
PQT044
44-Pin Thin Quad Flat Pack (measured in millimeters)
44
1
11.80
12.20
9.80
10.20
9.80
10.20
11.80
12.20
11° – 13°
0.95
1.05
1.20 MAX
16-038-PQT-2
PQT 44
7-11-95 ae
11° – 13°
0.80 BSC
0.30
0.45
1.00 REF.
Trademarks
Copyright 1996 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, MACH, and PAL are registered trademarks of Advanced Micro Devices, Inc.
Bus-Friendly is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
MACH211SP-7/10/12/15/20
37
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